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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ieee1394...
[deliverable/linux.git] / drivers / net / macb.c
CommitLineData
89e5785f
HS		 1/*
2 * Atmel MACB Ethernet Controller driver
3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/clk.h>
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/slab.h>
17#include <linux/init.h>
18#include <linux/netdevice.h>
19#include <linux/etherdevice.h>
89e5785f 20#include <linux/dma-mapping.h>
89e5785f 21#include <linux/platform_device.h>
6c36a707 22#include <linux/phy.h>
89e5785f 23
a09e64fb
RK		 24#include <mach/board.h>
25#include <mach/cpu.h>
89e5785f
HS		 26
27#include "macb.h"
28
89e5785f
HS		 29#define RX_BUFFER_SIZE 128
30#define RX_RING_SIZE 512
31#define RX_RING_BYTES (sizeof(struct dma_desc) * RX_RING_SIZE)
32
33/* Make the IP header word-aligned (the ethernet header is 14 bytes) */
34#define RX_OFFSET 2
35
36#define TX_RING_SIZE 128
37#define DEF_TX_RING_PENDING (TX_RING_SIZE - 1)
38#define TX_RING_BYTES (sizeof(struct dma_desc) * TX_RING_SIZE)
39
40#define TX_RING_GAP(bp) \
41 (TX_RING_SIZE - (bp)->tx_pending)
42#define TX_BUFFS_AVAIL(bp) \
43 (((bp)->tx_tail <= (bp)->tx_head) ? \
44 (bp)->tx_tail + (bp)->tx_pending - (bp)->tx_head : \
45 (bp)->tx_tail - (bp)->tx_head - TX_RING_GAP(bp))
46#define NEXT_TX(n) (((n) + 1) & (TX_RING_SIZE - 1))
47
48#define NEXT_RX(n) (((n) + 1) & (RX_RING_SIZE - 1))
49
50/* minimum number of free TX descriptors before waking up TX process */
51#define MACB_TX_WAKEUP_THRESH (TX_RING_SIZE / 4)
52
53#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
54 | MACB_BIT(ISR_ROVR))
55
56static void __macb_set_hwaddr(struct macb *bp)
57{
58 u32 bottom;
59 u16 top;
60
61 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
62 macb_writel(bp, SA1B, bottom);
63 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
64 macb_writel(bp, SA1T, top);
65}
66
67static void __init macb_get_hwaddr(struct macb *bp)
68{
69 u32 bottom;
70 u16 top;
71 u8 addr[6];
72
73 bottom = macb_readl(bp, SA1B);
74 top = macb_readl(bp, SA1T);
75
76 addr[0] = bottom & 0xff;
77 addr[1] = (bottom >> 8) & 0xff;
78 addr[2] = (bottom >> 16) & 0xff;
79 addr[3] = (bottom >> 24) & 0xff;
80 addr[4] = top & 0xff;
81 addr[5] = (top >> 8) & 0xff;
82
d1d5741d 83 if (is_valid_ether_addr(addr)) {
89e5785f 84 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
d1d5741d
SS		 85 } else {
86 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
87 random_ether_addr(bp->dev->dev_addr);
88 }
89e5785f
HS		 89}
90
6c36a707 91static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
89e5785f 92{
6c36a707 93 struct macb *bp = bus->priv;
89e5785f
HS		 94 int value;
95
89e5785f
HS		 96 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
97 | MACB_BF(RW, MACB_MAN_READ)
6c36a707
R		 98 | MACB_BF(PHYA, mii_id)
99 | MACB_BF(REGA, regnum)
89e5785f
HS		 100 | MACB_BF(CODE, MACB_MAN_CODE)));
101
6c36a707
R		 102 /* wait for end of transfer */
103 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
104 cpu_relax();
89e5785f
HS		 105
106 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
89e5785f
HS		 107
108 return value;
109}
110
6c36a707
R		 111static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
112 u16 value)
89e5785f 113{
6c36a707 114 struct macb *bp = bus->priv;
89e5785f
HS		 115
116 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
117 | MACB_BF(RW, MACB_MAN_WRITE)
6c36a707
R		 118 | MACB_BF(PHYA, mii_id)
119 | MACB_BF(REGA, regnum)
89e5785f 120 | MACB_BF(CODE, MACB_MAN_CODE)
6c36a707 121 | MACB_BF(DATA, value)));
89e5785f 122
6c36a707
R		 123 /* wait for end of transfer */
124 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
125 cpu_relax();
126
127 return 0;
128}
89e5785f 129
6c36a707
R		 130static int macb_mdio_reset(struct mii_bus *bus)
131{
132 return 0;
89e5785f
HS		 133}
134
6c36a707 135static void macb_handle_link_change(struct net_device *dev)
89e5785f 136{
6c36a707
R		 137 struct macb *bp = netdev_priv(dev);
138 struct phy_device *phydev = bp->phy_dev;
139 unsigned long flags;
89e5785f 140
6c36a707 141 int status_change = 0;
89e5785f 142
6c36a707
R		 143 spin_lock_irqsave(&bp->lock, flags);
144
145 if (phydev->link) {
146 if ((bp->speed != phydev->speed) ||
147 (bp->duplex != phydev->duplex)) {
148 u32 reg;
149
150 reg = macb_readl(bp, NCFGR);
151 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
152
153 if (phydev->duplex)
154 reg |= MACB_BIT(FD);
179956f4 155 if (phydev->speed == SPEED_100)
6c36a707
R		 156 reg |= MACB_BIT(SPD);
157
158 macb_writel(bp, NCFGR, reg);
159
160 bp->speed = phydev->speed;
161 bp->duplex = phydev->duplex;
162 status_change = 1;
163 }
89e5785f
HS		 164 }
165
6c36a707 166 if (phydev->link != bp->link) {
c8f15686 167 if (!phydev->link) {
6c36a707
R		 168 bp->speed = 0;
169 bp->duplex = -1;
170 }
171 bp->link = phydev->link;
89e5785f 172
6c36a707
R		 173 status_change = 1;
174 }
89e5785f 175
6c36a707
R		 176 spin_unlock_irqrestore(&bp->lock, flags);
177
178 if (status_change) {
179 if (phydev->link)
180 printk(KERN_INFO "%s: link up (%d/%s)\n",
181 dev->name, phydev->speed,
182 DUPLEX_FULL == phydev->duplex ? "Full":"Half");
183 else
184 printk(KERN_INFO "%s: link down\n", dev->name);
185 }
89e5785f
HS		 186}
187
6c36a707
R		 188/* based on au1000_eth. c*/
189static int macb_mii_probe(struct net_device *dev)
89e5785f 190{
6c36a707
R		 191 struct macb *bp = netdev_priv(dev);
192 struct phy_device *phydev = NULL;
193 struct eth_platform_data *pdata;
194 int phy_addr;
89e5785f 195
6c36a707
R		 196 /* find the first phy */
197 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
298cf9be
LB		 198 if (bp->mii_bus->phy_map[phy_addr]) {
199 phydev = bp->mii_bus->phy_map[phy_addr];
6c36a707
R		 200 break;
201 }
202 }
203
204 if (!phydev) {
205 printk (KERN_ERR "%s: no PHY found\n", dev->name);
206 return -1;
207 }
208
209 pdata = bp->pdev->dev.platform_data;
210 /* TODO : add pin_irq */
211
212 /* attach the mac to the phy */
213 if (pdata && pdata->is_rmii) {
214 phydev = phy_connect(dev, phydev->dev.bus_id,
215 &macb_handle_link_change, 0, PHY_INTERFACE_MODE_RMII);
216 } else {
217 phydev = phy_connect(dev, phydev->dev.bus_id,
218 &macb_handle_link_change, 0, PHY_INTERFACE_MODE_MII);
219 }
220
221 if (IS_ERR(phydev)) {
222 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
223 return PTR_ERR(phydev);
224 }
225
226 /* mask with MAC supported features */
227 phydev->supported &= PHY_BASIC_FEATURES;
228
229 phydev->advertising = phydev->supported;
230
231 bp->link = 0;
232 bp->speed = 0;
233 bp->duplex = -1;
234 bp->phy_dev = phydev;
235
236 return 0;
89e5785f
HS		 237}
238
6c36a707 239static int macb_mii_init(struct macb *bp)
89e5785f 240{
6c36a707
R		 241 struct eth_platform_data *pdata;
242 int err = -ENXIO, i;
89e5785f 243
6c36a707
R		 244 /* Enable managment port */
245 macb_writel(bp, NCR, MACB_BIT(MPE));
89e5785f 246
298cf9be
LB		 247 bp->mii_bus = mdiobus_alloc();
248 if (bp->mii_bus == NULL) {
249 err = -ENOMEM;
250 goto err_out;
251 }
252
253 bp->mii_bus->name = "MACB_mii_bus";
254 bp->mii_bus->read = &macb_mdio_read;
255 bp->mii_bus->write = &macb_mdio_write;
256 bp->mii_bus->reset = &macb_mdio_reset;
257 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%x", bp->pdev->id);
258 bp->mii_bus->priv = bp;
259 bp->mii_bus->parent = &bp->dev->dev;
6c36a707 260 pdata = bp->pdev->dev.platform_data;
89e5785f 261
6c36a707 262 if (pdata)
298cf9be 263 bp->mii_bus->phy_mask = pdata->phy_mask;
89e5785f 264
298cf9be
LB		 265 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
266 if (!bp->mii_bus->irq) {
6c36a707 267 err = -ENOMEM;
298cf9be 268 goto err_out_free_mdiobus;
89e5785f
HS		 269 }
270
6c36a707 271 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 272 bp->mii_bus->irq[i] = PHY_POLL;
89e5785f 273
298cf9be 274 platform_set_drvdata(bp->dev, bp->mii_bus);
89e5785f 275
298cf9be 276 if (mdiobus_register(bp->mii_bus))
6c36a707 277 goto err_out_free_mdio_irq;
89e5785f 278
6c36a707
R		 279 if (macb_mii_probe(bp->dev) != 0) {
280 goto err_out_unregister_bus;
281 }
89e5785f 282
6c36a707 283 return 0;
89e5785f 284
6c36a707 285err_out_unregister_bus:
298cf9be 286 mdiobus_unregister(bp->mii_bus);
6c36a707 287err_out_free_mdio_irq:
298cf9be
LB		 288 kfree(bp->mii_bus->irq);
289err_out_free_mdiobus:
290 mdiobus_free(bp->mii_bus);
6c36a707
R		 291err_out:
292 return err;
89e5785f
HS		 293}
294
295static void macb_update_stats(struct macb *bp)
296{
297 u32 __iomem *reg = bp->regs + MACB_PFR;
298 u32 *p = &bp->hw_stats.rx_pause_frames;
299 u32 *end = &bp->hw_stats.tx_pause_frames + 1;
300
301 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
302
303 for(; p < end; p++, reg++)
0f0d84e5 304 *p += __raw_readl(reg);
89e5785f
HS		 305}
306
89e5785f
HS		 307static void macb_tx(struct macb *bp)
308{
309 unsigned int tail;
310 unsigned int head;
311 u32 status;
312
313 status = macb_readl(bp, TSR);
314 macb_writel(bp, TSR, status);
315
316 dev_dbg(&bp->pdev->dev, "macb_tx status = %02lx\n",
317 (unsigned long)status);
318
319 if (status & MACB_BIT(UND)) {
bdcba151 320 int i;
89e5785f 321 printk(KERN_ERR "%s: TX underrun, resetting buffers\n",
bdcba151
GC		 322 bp->dev->name);
323
324 head = bp->tx_head;
325
326 /*Mark all the buffer as used to avoid sending a lost buffer*/
327 for (i = 0; i < TX_RING_SIZE; i++)
328 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
329
330 /* free transmit buffer in upper layer*/
331 for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) {
332 struct ring_info *rp = &bp->tx_skb[tail];
333 struct sk_buff *skb = rp->skb;
334
335 BUG_ON(skb == NULL);
336
337 rmb();
338
339 dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len,
340 DMA_TO_DEVICE);
341 rp->skb = NULL;
342 dev_kfree_skb_irq(skb);
343 }
344
89e5785f
HS		 345 bp->tx_head = bp->tx_tail = 0;
346 }
347
348 if (!(status & MACB_BIT(COMP)))
349 /*
350 * This may happen when a buffer becomes complete
351 * between reading the ISR and scanning the
352 * descriptors. Nothing to worry about.
353 */
354 return;
355
356 head = bp->tx_head;
357 for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) {
358 struct ring_info *rp = &bp->tx_skb[tail];
359 struct sk_buff *skb = rp->skb;
360 u32 bufstat;
361
362 BUG_ON(skb == NULL);
363
364 rmb();
365 bufstat = bp->tx_ring[tail].ctrl;
366
367 if (!(bufstat & MACB_BIT(TX_USED)))
368 break;
369
370 dev_dbg(&bp->pdev->dev, "skb %u (data %p) TX complete\n",
371 tail, skb->data);
372 dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len,
373 DMA_TO_DEVICE);
374 bp->stats.tx_packets++;
375 bp->stats.tx_bytes += skb->len;
376 rp->skb = NULL;
377 dev_kfree_skb_irq(skb);
378 }
379
380 bp->tx_tail = tail;
381 if (netif_queue_stopped(bp->dev) &&
382 TX_BUFFS_AVAIL(bp) > MACB_TX_WAKEUP_THRESH)
383 netif_wake_queue(bp->dev);
384}
385
386static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
387 unsigned int last_frag)
388{
389 unsigned int len;
390 unsigned int frag;
391 unsigned int offset = 0;
392 struct sk_buff *skb;
393
394 len = MACB_BFEXT(RX_FRMLEN, bp->rx_ring[last_frag].ctrl);
395
396 dev_dbg(&bp->pdev->dev, "macb_rx_frame frags %u - %u (len %u)\n",
397 first_frag, last_frag, len);
398
399 skb = dev_alloc_skb(len + RX_OFFSET);
400 if (!skb) {
401 bp->stats.rx_dropped++;
402 for (frag = first_frag; ; frag = NEXT_RX(frag)) {
403 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
404 if (frag == last_frag)
405 break;
406 }
407 wmb();
408 return 1;
409 }
410
411 skb_reserve(skb, RX_OFFSET);
89e5785f
HS		 412 skb->ip_summed = CHECKSUM_NONE;
413 skb_put(skb, len);
414
415 for (frag = first_frag; ; frag = NEXT_RX(frag)) {
416 unsigned int frag_len = RX_BUFFER_SIZE;
417
418 if (offset + frag_len > len) {
419 BUG_ON(frag != last_frag);
420 frag_len = len - offset;
421 }
27d7ff46
ACM		 422 skb_copy_to_linear_data_offset(skb, offset,
423 (bp->rx_buffers +
424 (RX_BUFFER_SIZE * frag)),
425 frag_len);
89e5785f
HS		 426 offset += RX_BUFFER_SIZE;
427 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
428 wmb();
429
430 if (frag == last_frag)
431 break;
432 }
433
434 skb->protocol = eth_type_trans(skb, bp->dev);
435
436 bp->stats.rx_packets++;
437 bp->stats.rx_bytes += len;
89e5785f
HS		 438 dev_dbg(&bp->pdev->dev, "received skb of length %u, csum: %08x\n",
439 skb->len, skb->csum);
440 netif_receive_skb(skb);
441
442 return 0;
443}
444
445/* Mark DMA descriptors from begin up to and not including end as unused */
446static void discard_partial_frame(struct macb *bp, unsigned int begin,
447 unsigned int end)
448{
449 unsigned int frag;
450
451 for (frag = begin; frag != end; frag = NEXT_RX(frag))
452 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
453 wmb();
454
455 /*
456 * When this happens, the hardware stats registers for
457 * whatever caused this is updated, so we don't have to record
458 * anything.
459 */
460}
461
462static int macb_rx(struct macb *bp, int budget)
463{
464 int received = 0;
465 unsigned int tail = bp->rx_tail;
466 int first_frag = -1;
467
468 for (; budget > 0; tail = NEXT_RX(tail)) {
469 u32 addr, ctrl;
470
471 rmb();
472 addr = bp->rx_ring[tail].addr;
473 ctrl = bp->rx_ring[tail].ctrl;
474
475 if (!(addr & MACB_BIT(RX_USED)))
476 break;
477
478 if (ctrl & MACB_BIT(RX_SOF)) {
479 if (first_frag != -1)
480 discard_partial_frame(bp, first_frag, tail);
481 first_frag = tail;
482 }
483
484 if (ctrl & MACB_BIT(RX_EOF)) {
485 int dropped;
486 BUG_ON(first_frag == -1);
487
488 dropped = macb_rx_frame(bp, first_frag, tail);
489 first_frag = -1;
490 if (!dropped) {
491 received++;
492 budget--;
493 }
494 }
495 }
496
497 if (first_frag != -1)
498 bp->rx_tail = first_frag;
499 else
500 bp->rx_tail = tail;
501
502 return received;
503}
504
bea3348e 505static int macb_poll(struct napi_struct *napi, int budget)
89e5785f 506{
bea3348e
SH		 507 struct macb *bp = container_of(napi, struct macb, napi);
508 struct net_device *dev = bp->dev;
509 int work_done;
89e5785f
HS		 510 u32 status;
511
512 status = macb_readl(bp, RSR);
513 macb_writel(bp, RSR, status);
514
bea3348e 515 work_done = 0;
89e5785f
HS		 516 if (!status) {
517 /*
518 * This may happen if an interrupt was pending before
519 * this function was called last time, and no packets
520 * have been received since.
521 */
908a7a16 522 netif_rx_complete(napi);
89e5785f
HS		 523 goto out;
524 }
525
526 dev_dbg(&bp->pdev->dev, "poll: status = %08lx, budget = %d\n",
bea3348e 527 (unsigned long)status, budget);
89e5785f
HS		 528
529 if (!(status & MACB_BIT(REC))) {
530 dev_warn(&bp->pdev->dev,
531 "No RX buffers complete, status = %02lx\n",
532 (unsigned long)status);
908a7a16 533 netif_rx_complete(napi);
89e5785f
HS		 534 goto out;
535 }
536
bea3348e
SH		 537 work_done = macb_rx(bp, budget);
538 if (work_done < budget)
908a7a16 539 netif_rx_complete(napi);
89e5785f
HS		 540
541 /*
542 * We've done what we can to clean the buffers. Make sure we
543 * get notified when new packets arrive.
544 */
545out:
546 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
547
548 /* TODO: Handle errors */
549
bea3348e 550 return work_done;
89e5785f
HS		 551}
552
553static irqreturn_t macb_interrupt(int irq, void *dev_id)
554{
555 struct net_device *dev = dev_id;
556 struct macb *bp = netdev_priv(dev);
557 u32 status;
558
559 status = macb_readl(bp, ISR);
560
561 if (unlikely(!status))
562 return IRQ_NONE;
563
564 spin_lock(&bp->lock);
565
566 while (status) {
89e5785f
HS		 567 /* close possible race with dev_close */
568 if (unlikely(!netif_running(dev))) {
569 macb_writel(bp, IDR, ~0UL);
570 break;
571 }
572
573 if (status & MACB_RX_INT_FLAGS) {
908a7a16 574 if (netif_rx_schedule_prep(&bp->napi)) {
89e5785f
HS		 575 /*
576 * There's no point taking any more interrupts
577 * until we have processed the buffers
578 */
579 macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
6c36a707
R		 580 dev_dbg(&bp->pdev->dev,
581 "scheduling RX softirq\n");
908a7a16 582 __netif_rx_schedule(&bp->napi);
89e5785f
HS		 583 }
584 }
585
586 if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND)))
587 macb_tx(bp);
588
589 /*
590 * Link change detection isn't possible with RMII, so we'll
591 * add that if/when we get our hands on a full-blown MII PHY.
592 */
593
594 if (status & MACB_BIT(HRESP)) {
595 /*
596 * TODO: Reset the hardware, and maybe move the printk
597 * to a lower-priority context as well (work queue?)
598 */
599 printk(KERN_ERR "%s: DMA bus error: HRESP not OK\n",
600 dev->name);
601 }
602
603 status = macb_readl(bp, ISR);
604 }
605
606 spin_unlock(&bp->lock);
607
608 return IRQ_HANDLED;
609}
610
611static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
612{
613 struct macb *bp = netdev_priv(dev);
614 dma_addr_t mapping;
615 unsigned int len, entry;
616 u32 ctrl;
617
618#ifdef DEBUG
619 int i;
620 dev_dbg(&bp->pdev->dev,
621 "start_xmit: len %u head %p data %p tail %p end %p\n",
27a884dc 622 skb->len, skb->head, skb->data,
4305b541 623 skb_tail_pointer(skb), skb_end_pointer(skb));
89e5785f
HS		 624 dev_dbg(&bp->pdev->dev,
625 "data:");
626 for (i = 0; i < 16; i++)
627 printk(" %02x", (unsigned int)skb->data[i]);
628 printk("\n");
629#endif
630
631 len = skb->len;
632 spin_lock_irq(&bp->lock);
633
634 /* This is a hard error, log it. */
635 if (TX_BUFFS_AVAIL(bp) < 1) {
636 netif_stop_queue(dev);
637 spin_unlock_irq(&bp->lock);
638 dev_err(&bp->pdev->dev,
639 "BUG! Tx Ring full when queue awake!\n");
640 dev_dbg(&bp->pdev->dev, "tx_head = %u, tx_tail = %u\n",
641 bp->tx_head, bp->tx_tail);
642 return 1;
643 }
644
645 entry = bp->tx_head;
646 dev_dbg(&bp->pdev->dev, "Allocated ring entry %u\n", entry);
647 mapping = dma_map_single(&bp->pdev->dev, skb->data,
648 len, DMA_TO_DEVICE);
649 bp->tx_skb[entry].skb = skb;
650 bp->tx_skb[entry].mapping = mapping;
651 dev_dbg(&bp->pdev->dev, "Mapped skb data %p to DMA addr %08lx\n",
652 skb->data, (unsigned long)mapping);
653
654 ctrl = MACB_BF(TX_FRMLEN, len);
655 ctrl |= MACB_BIT(TX_LAST);
656 if (entry == (TX_RING_SIZE - 1))
657 ctrl |= MACB_BIT(TX_WRAP);
658
659 bp->tx_ring[entry].addr = mapping;
660 bp->tx_ring[entry].ctrl = ctrl;
661 wmb();
662
663 entry = NEXT_TX(entry);
664 bp->tx_head = entry;
665
666 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
667
668 if (TX_BUFFS_AVAIL(bp) < 1)
669 netif_stop_queue(dev);
670
671 spin_unlock_irq(&bp->lock);
672
673 dev->trans_start = jiffies;
674
675 return 0;
676}
677
678static void macb_free_consistent(struct macb *bp)
679{
680 if (bp->tx_skb) {
681 kfree(bp->tx_skb);
682 bp->tx_skb = NULL;
683 }
684 if (bp->rx_ring) {
685 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
686 bp->rx_ring, bp->rx_ring_dma);
687 bp->rx_ring = NULL;
688 }
689 if (bp->tx_ring) {
690 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
691 bp->tx_ring, bp->tx_ring_dma);
692 bp->tx_ring = NULL;
693 }
694 if (bp->rx_buffers) {
695 dma_free_coherent(&bp->pdev->dev,
696 RX_RING_SIZE * RX_BUFFER_SIZE,
697 bp->rx_buffers, bp->rx_buffers_dma);
698 bp->rx_buffers = NULL;
699 }
700}
701
702static int macb_alloc_consistent(struct macb *bp)
703{
704 int size;
705
706 size = TX_RING_SIZE * sizeof(struct ring_info);
707 bp->tx_skb = kmalloc(size, GFP_KERNEL);
708 if (!bp->tx_skb)
709 goto out_err;
710
711 size = RX_RING_BYTES;
712 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
713 &bp->rx_ring_dma, GFP_KERNEL);
714 if (!bp->rx_ring)
715 goto out_err;
716 dev_dbg(&bp->pdev->dev,
717 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
718 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
719
720 size = TX_RING_BYTES;
721 bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
722 &bp->tx_ring_dma, GFP_KERNEL);
723 if (!bp->tx_ring)
724 goto out_err;
725 dev_dbg(&bp->pdev->dev,
726 "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
727 size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
728
729 size = RX_RING_SIZE * RX_BUFFER_SIZE;
730 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
731 &bp->rx_buffers_dma, GFP_KERNEL);
732 if (!bp->rx_buffers)
733 goto out_err;
734 dev_dbg(&bp->pdev->dev,
735 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
736 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
737
738 return 0;
739
740out_err:
741 macb_free_consistent(bp);
742 return -ENOMEM;
743}
744
745static void macb_init_rings(struct macb *bp)
746{
747 int i;
748 dma_addr_t addr;
749
750 addr = bp->rx_buffers_dma;
751 for (i = 0; i < RX_RING_SIZE; i++) {
752 bp->rx_ring[i].addr = addr;
753 bp->rx_ring[i].ctrl = 0;
754 addr += RX_BUFFER_SIZE;
755 }
756 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
757
758 for (i = 0; i < TX_RING_SIZE; i++) {
759 bp->tx_ring[i].addr = 0;
760 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
761 }
762 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
763
764 bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
765}
766
767static void macb_reset_hw(struct macb *bp)
768{
769 /* Make sure we have the write buffer for ourselves */
770 wmb();
771
772 /*
773 * Disable RX and TX (XXX: Should we halt the transmission
774 * more gracefully?)
775 */
776 macb_writel(bp, NCR, 0);
777
778 /* Clear the stats registers (XXX: Update stats first?) */
779 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
780
781 /* Clear all status flags */
782 macb_writel(bp, TSR, ~0UL);
783 macb_writel(bp, RSR, ~0UL);
784
785 /* Disable all interrupts */
786 macb_writel(bp, IDR, ~0UL);
787 macb_readl(bp, ISR);
788}
789
790static void macb_init_hw(struct macb *bp)
791{
792 u32 config;
793
794 macb_reset_hw(bp);
795 __macb_set_hwaddr(bp);
796
797 config = macb_readl(bp, NCFGR) & MACB_BF(CLK, -1L);
798 config |= MACB_BIT(PAE); /* PAuse Enable */
799 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
800 if (bp->dev->flags & IFF_PROMISC)
801 config |= MACB_BIT(CAF); /* Copy All Frames */
802 if (!(bp->dev->flags & IFF_BROADCAST))
803 config |= MACB_BIT(NBC); /* No BroadCast */
804 macb_writel(bp, NCFGR, config);
805
806 /* Initialize TX and RX buffers */
807 macb_writel(bp, RBQP, bp->rx_ring_dma);
808 macb_writel(bp, TBQP, bp->tx_ring_dma);
809
810 /* Enable TX and RX */
6c36a707 811 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
89e5785f
HS		 812
813 /* Enable interrupts */
814 macb_writel(bp, IER, (MACB_BIT(RCOMP)
815 | MACB_BIT(RXUBR)
816 | MACB_BIT(ISR_TUND)
817 | MACB_BIT(ISR_RLE)
818 | MACB_BIT(TXERR)
819 | MACB_BIT(TCOMP)
820 | MACB_BIT(ISR_ROVR)
821 | MACB_BIT(HRESP)));
89e5785f 822
89e5785f
HS		 823}
824
446ebd01
PV		 825/*
826 * The hash address register is 64 bits long and takes up two
827 * locations in the memory map. The least significant bits are stored
828 * in EMAC_HSL and the most significant bits in EMAC_HSH.
829 *
830 * The unicast hash enable and the multicast hash enable bits in the
831 * network configuration register enable the reception of hash matched
832 * frames. The destination address is reduced to a 6 bit index into
833 * the 64 bit hash register using the following hash function. The
834 * hash function is an exclusive or of every sixth bit of the
835 * destination address.
836 *
837 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
838 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
839 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
840 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
841 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
842 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
843 *
844 * da[0] represents the least significant bit of the first byte
845 * received, that is, the multicast/unicast indicator, and da[47]
846 * represents the most significant bit of the last byte received. If
847 * the hash index, hi[n], points to a bit that is set in the hash
848 * register then the frame will be matched according to whether the
849 * frame is multicast or unicast. A multicast match will be signalled
850 * if the multicast hash enable bit is set, da[0] is 1 and the hash
851 * index points to a bit set in the hash register. A unicast match
852 * will be signalled if the unicast hash enable bit is set, da[0] is 0
853 * and the hash index points to a bit set in the hash register. To
854 * receive all multicast frames, the hash register should be set with
855 * all ones and the multicast hash enable bit should be set in the
856 * network configuration register.
857 */
858
859static inline int hash_bit_value(int bitnr, __u8 *addr)
860{
861 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
862 return 1;
863 return 0;
864}
865
866/*
867 * Return the hash index value for the specified address.
868 */
869static int hash_get_index(__u8 *addr)
870{
871 int i, j, bitval;
872 int hash_index = 0;
873
874 for (j = 0; j < 6; j++) {
875 for (i = 0, bitval = 0; i < 8; i++)
876 bitval ^= hash_bit_value(i*6 + j, addr);
877
878 hash_index |= (bitval << j);
879 }
880
881 return hash_index;
882}
883
884/*
885 * Add multicast addresses to the internal multicast-hash table.
886 */
887static void macb_sethashtable(struct net_device *dev)
888{
889 struct dev_mc_list *curr;
890 unsigned long mc_filter[2];
891 unsigned int i, bitnr;
892 struct macb *bp = netdev_priv(dev);
893
894 mc_filter[0] = mc_filter[1] = 0;
895
896 curr = dev->mc_list;
897 for (i = 0; i < dev->mc_count; i++, curr = curr->next) {
898 if (!curr) break; /* unexpected end of list */
899
900 bitnr = hash_get_index(curr->dmi_addr);
901 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
902 }
903
904 macb_writel(bp, HRB, mc_filter[0]);
905 macb_writel(bp, HRT, mc_filter[1]);
906}
907
908/*
909 * Enable/Disable promiscuous and multicast modes.
910 */
911static void macb_set_rx_mode(struct net_device *dev)
912{
913 unsigned long cfg;
914 struct macb *bp = netdev_priv(dev);
915
916 cfg = macb_readl(bp, NCFGR);
917
918 if (dev->flags & IFF_PROMISC)
919 /* Enable promiscuous mode */
920 cfg |= MACB_BIT(CAF);
921 else if (dev->flags & (~IFF_PROMISC))
922 /* Disable promiscuous mode */
923 cfg &= ~MACB_BIT(CAF);
924
925 if (dev->flags & IFF_ALLMULTI) {
926 /* Enable all multicast mode */
927 macb_writel(bp, HRB, -1);
928 macb_writel(bp, HRT, -1);
929 cfg |= MACB_BIT(NCFGR_MTI);
930 } else if (dev->mc_count > 0) {
931 /* Enable specific multicasts */
932 macb_sethashtable(dev);
933 cfg |= MACB_BIT(NCFGR_MTI);
934 } else if (dev->flags & (~IFF_ALLMULTI)) {
935 /* Disable all multicast mode */
936 macb_writel(bp, HRB, 0);
937 macb_writel(bp, HRT, 0);
938 cfg &= ~MACB_BIT(NCFGR_MTI);
939 }
940
941 macb_writel(bp, NCFGR, cfg);
942}
943
89e5785f
HS		 944static int macb_open(struct net_device *dev)
945{
946 struct macb *bp = netdev_priv(dev);
947 int err;
948
949 dev_dbg(&bp->pdev->dev, "open\n");
950
6c36a707
R		 951 /* if the phy is not yet register, retry later*/
952 if (!bp->phy_dev)
953 return -EAGAIN;
954
89e5785f
HS		 955 if (!is_valid_ether_addr(dev->dev_addr))
956 return -EADDRNOTAVAIL;
957
958 err = macb_alloc_consistent(bp);
959 if (err) {
960 printk(KERN_ERR
961 "%s: Unable to allocate DMA memory (error %d)\n",
962 dev->name, err);
963 return err;
964 }
965
bea3348e
SH		 966 napi_enable(&bp->napi);
967
89e5785f
HS		 968 macb_init_rings(bp);
969 macb_init_hw(bp);
89e5785f 970
6c36a707
R		 971 /* schedule a link state check */
972 phy_start(bp->phy_dev);
89e5785f 973
6c36a707 974 netif_start_queue(dev);
89e5785f
HS		 975
976 return 0;
977}
978
979static int macb_close(struct net_device *dev)
980{
981 struct macb *bp = netdev_priv(dev);
982 unsigned long flags;
983
89e5785f 984 netif_stop_queue(dev);
bea3348e 985 napi_disable(&bp->napi);
89e5785f 986
6c36a707
R		 987 if (bp->phy_dev)
988 phy_stop(bp->phy_dev);
989
89e5785f
HS		 990 spin_lock_irqsave(&bp->lock, flags);
991 macb_reset_hw(bp);
992 netif_carrier_off(dev);
993 spin_unlock_irqrestore(&bp->lock, flags);
994
995 macb_free_consistent(bp);
996
997 return 0;
998}
999
1000static struct net_device_stats *macb_get_stats(struct net_device *dev)
1001{
1002 struct macb *bp = netdev_priv(dev);
1003 struct net_device_stats *nstat = &bp->stats;
1004 struct macb_stats *hwstat = &bp->hw_stats;
1005
6c36a707
R		 1006 /* read stats from hardware */
1007 macb_update_stats(bp);
1008
89e5785f
HS		 1009 /* Convert HW stats into netdevice stats */
1010 nstat->rx_errors = (hwstat->rx_fcs_errors +
1011 hwstat->rx_align_errors +
1012 hwstat->rx_resource_errors +
1013 hwstat->rx_overruns +
1014 hwstat->rx_oversize_pkts +
1015 hwstat->rx_jabbers +
1016 hwstat->rx_undersize_pkts +
1017 hwstat->sqe_test_errors +
1018 hwstat->rx_length_mismatch);
1019 nstat->tx_errors = (hwstat->tx_late_cols +
1020 hwstat->tx_excessive_cols +
1021 hwstat->tx_underruns +
1022 hwstat->tx_carrier_errors);
1023 nstat->collisions = (hwstat->tx_single_cols +
1024 hwstat->tx_multiple_cols +
1025 hwstat->tx_excessive_cols);
1026 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1027 hwstat->rx_jabbers +
1028 hwstat->rx_undersize_pkts +
1029 hwstat->rx_length_mismatch);
1030 nstat->rx_over_errors = hwstat->rx_resource_errors;
1031 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
1032 nstat->rx_frame_errors = hwstat->rx_align_errors;
1033 nstat->rx_fifo_errors = hwstat->rx_overruns;
1034 /* XXX: What does "missed" mean? */
1035 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
1036 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
1037 nstat->tx_fifo_errors = hwstat->tx_underruns;
1038 /* Don't know about heartbeat or window errors... */
1039
1040 return nstat;
1041}
1042
1043static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1044{
1045 struct macb *bp = netdev_priv(dev);
6c36a707
R		 1046 struct phy_device *phydev = bp->phy_dev;
1047
1048 if (!phydev)
1049 return -ENODEV;
89e5785f 1050
6c36a707 1051 return phy_ethtool_gset(phydev, cmd);
89e5785f
HS		 1052}
1053
1054static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1055{
1056 struct macb *bp = netdev_priv(dev);
6c36a707 1057 struct phy_device *phydev = bp->phy_dev;
89e5785f 1058
6c36a707
R		 1059 if (!phydev)
1060 return -ENODEV;
1061
1062 return phy_ethtool_sset(phydev, cmd);
89e5785f
HS		 1063}
1064
6c36a707
R		 1065static void macb_get_drvinfo(struct net_device *dev,
1066 struct ethtool_drvinfo *info)
89e5785f
HS		 1067{
1068 struct macb *bp = netdev_priv(dev);
1069
1070 strcpy(info->driver, bp->pdev->dev.driver->name);
1071 strcpy(info->version, "$Revision: 1.14 $");
1072 strcpy(info->bus_info, bp->pdev->dev.bus_id);
1073}
1074
89e5785f
HS		 1075static struct ethtool_ops macb_ethtool_ops = {
1076 .get_settings = macb_get_settings,
1077 .set_settings = macb_set_settings,
1078 .get_drvinfo = macb_get_drvinfo,
89e5785f
HS		 1079 .get_link = ethtool_op_get_link,
1080};
1081
1082static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1083{
1084 struct macb *bp = netdev_priv(dev);
6c36a707 1085 struct phy_device *phydev = bp->phy_dev;
89e5785f
HS		 1086
1087 if (!netif_running(dev))
1088 return -EINVAL;
1089
6c36a707
R		 1090 if (!phydev)
1091 return -ENODEV;
89e5785f 1092
6c36a707 1093 return phy_mii_ioctl(phydev, if_mii(rq), cmd);
89e5785f
HS		 1094}
1095
06c3fd6a 1096static int __init macb_probe(struct platform_device *pdev)
89e5785f
HS		 1097{
1098 struct eth_platform_data *pdata;
1099 struct resource *regs;
1100 struct net_device *dev;
1101 struct macb *bp;
6c36a707 1102 struct phy_device *phydev;
89e5785f
HS		 1103 unsigned long pclk_hz;
1104 u32 config;
1105 int err = -ENXIO;
1106
1107 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1108 if (!regs) {
1109 dev_err(&pdev->dev, "no mmio resource defined\n");
1110 goto err_out;
1111 }
1112
1113 err = -ENOMEM;
1114 dev = alloc_etherdev(sizeof(*bp));
1115 if (!dev) {
1116 dev_err(&pdev->dev, "etherdev alloc failed, aborting.\n");
1117 goto err_out;
1118 }
1119
89e5785f
HS		 1120 SET_NETDEV_DEV(dev, &pdev->dev);
1121
1122 /* TODO: Actually, we have some interesting features... */
1123 dev->features |= 0;
1124
1125 bp = netdev_priv(dev);
1126 bp->pdev = pdev;
1127 bp->dev = dev;
1128
1129 spin_lock_init(&bp->lock);
1130
0cc8674f
AV		 1131#if defined(CONFIG_ARCH_AT91)
1132 bp->pclk = clk_get(&pdev->dev, "macb_clk");
1133 if (IS_ERR(bp->pclk)) {
1134 dev_err(&pdev->dev, "failed to get macb_clk\n");
1135 goto err_out_free_dev;
1136 }
1137 clk_enable(bp->pclk);
1138#else
89e5785f
HS		 1139 bp->pclk = clk_get(&pdev->dev, "pclk");
1140 if (IS_ERR(bp->pclk)) {
1141 dev_err(&pdev->dev, "failed to get pclk\n");
1142 goto err_out_free_dev;
1143 }
1144 bp->hclk = clk_get(&pdev->dev, "hclk");
1145 if (IS_ERR(bp->hclk)) {
1146 dev_err(&pdev->dev, "failed to get hclk\n");
1147 goto err_out_put_pclk;
1148 }
1149
1150 clk_enable(bp->pclk);
1151 clk_enable(bp->hclk);
0cc8674f 1152#endif
89e5785f
HS		 1153
1154 bp->regs = ioremap(regs->start, regs->end - regs->start + 1);
1155 if (!bp->regs) {
1156 dev_err(&pdev->dev, "failed to map registers, aborting.\n");
1157 err = -ENOMEM;
1158 goto err_out_disable_clocks;
1159 }
1160
1161 dev->irq = platform_get_irq(pdev, 0);
38515e90 1162 err = request_irq(dev->irq, macb_interrupt, IRQF_SAMPLE_RANDOM,
89e5785f
HS		 1163 dev->name, dev);
1164 if (err) {
1165 printk(KERN_ERR
1166 "%s: Unable to request IRQ %d (error %d)\n",
1167 dev->name, dev->irq, err);
1168 goto err_out_iounmap;
1169 }
1170
1171 dev->open = macb_open;
1172 dev->stop = macb_close;
1173 dev->hard_start_xmit = macb_start_xmit;
1174 dev->get_stats = macb_get_stats;
446ebd01 1175 dev->set_multicast_list = macb_set_rx_mode;
89e5785f 1176 dev->do_ioctl = macb_ioctl;
bea3348e 1177 netif_napi_add(dev, &bp->napi, macb_poll, 64);
89e5785f
HS		 1178 dev->ethtool_ops = &macb_ethtool_ops;
1179
1180 dev->base_addr = regs->start;
1181
89e5785f
HS		 1182 /* Set MII management clock divider */
1183 pclk_hz = clk_get_rate(bp->pclk);
1184 if (pclk_hz <= 20000000)
1185 config = MACB_BF(CLK, MACB_CLK_DIV8);
1186 else if (pclk_hz <= 40000000)
1187 config = MACB_BF(CLK, MACB_CLK_DIV16);
1188 else if (pclk_hz <= 80000000)
1189 config = MACB_BF(CLK, MACB_CLK_DIV32);
1190 else
1191 config = MACB_BF(CLK, MACB_CLK_DIV64);
1192 macb_writel(bp, NCFGR, config);
1193
89e5785f 1194 macb_get_hwaddr(bp);
89e5785f 1195 pdata = pdev->dev.platform_data;
6c36a707 1196
89e5785f 1197 if (pdata && pdata->is_rmii)
0cc8674f
AV		 1198#if defined(CONFIG_ARCH_AT91)
1199 macb_writel(bp, USRIO, (MACB_BIT(RMII) | MACB_BIT(CLKEN)) );
1200#else
89e5785f 1201 macb_writel(bp, USRIO, 0);
0cc8674f 1202#endif
89e5785f 1203 else
0cc8674f
AV		 1204#if defined(CONFIG_ARCH_AT91)
1205 macb_writel(bp, USRIO, MACB_BIT(CLKEN));
1206#else
89e5785f 1207 macb_writel(bp, USRIO, MACB_BIT(MII));
0cc8674f 1208#endif
89e5785f
HS		 1209
1210 bp->tx_pending = DEF_TX_RING_PENDING;
1211
1212 err = register_netdev(dev);
1213 if (err) {
1214 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
1215 goto err_out_free_irq;
1216 }
1217
6c36a707
R		 1218 if (macb_mii_init(bp) != 0) {
1219 goto err_out_unregister_netdev;
1220 }
89e5785f 1221
6c36a707 1222 platform_set_drvdata(pdev, dev);
89e5785f 1223
e174961c
JB		 1224 printk(KERN_INFO "%s: Atmel MACB at 0x%08lx irq %d (%pM)\n",
1225 dev->name, dev->base_addr, dev->irq, dev->dev_addr);
89e5785f 1226
6c36a707
R		 1227 phydev = bp->phy_dev;
1228 printk(KERN_INFO "%s: attached PHY driver [%s] "
1229 "(mii_bus:phy_addr=%s, irq=%d)\n",
1230 dev->name, phydev->drv->name, phydev->dev.bus_id, phydev->irq);
1231
89e5785f
HS		 1232 return 0;
1233
6c36a707
R		 1234err_out_unregister_netdev:
1235 unregister_netdev(dev);
89e5785f
HS		 1236err_out_free_irq:
1237 free_irq(dev->irq, dev);
1238err_out_iounmap:
1239 iounmap(bp->regs);
1240err_out_disable_clocks:
0cc8674f 1241#ifndef CONFIG_ARCH_AT91
89e5785f 1242 clk_disable(bp->hclk);
89e5785f 1243 clk_put(bp->hclk);
0cc8674f
AV		 1244#endif
1245 clk_disable(bp->pclk);
6c36a707 1246#ifndef CONFIG_ARCH_AT91
89e5785f 1247err_out_put_pclk:
6c36a707 1248#endif
89e5785f
HS		 1249 clk_put(bp->pclk);
1250err_out_free_dev:
1251 free_netdev(dev);
1252err_out:
1253 platform_set_drvdata(pdev, NULL);
1254 return err;
1255}
1256
06c3fd6a 1257static int __exit macb_remove(struct platform_device *pdev)
89e5785f
HS		 1258{
1259 struct net_device *dev;
1260 struct macb *bp;
1261
1262 dev = platform_get_drvdata(pdev);
1263
1264 if (dev) {
1265 bp = netdev_priv(dev);
84b7901f
AN		 1266 if (bp->phy_dev)
1267 phy_disconnect(bp->phy_dev);
298cf9be
LB		 1268 mdiobus_unregister(bp->mii_bus);
1269 kfree(bp->mii_bus->irq);
1270 mdiobus_free(bp->mii_bus);
89e5785f
HS		 1271 unregister_netdev(dev);
1272 free_irq(dev->irq, dev);
1273 iounmap(bp->regs);
0cc8674f 1274#ifndef CONFIG_ARCH_AT91
89e5785f 1275 clk_disable(bp->hclk);
89e5785f 1276 clk_put(bp->hclk);
0cc8674f
AV		 1277#endif
1278 clk_disable(bp->pclk);
89e5785f
HS		 1279 clk_put(bp->pclk);
1280 free_netdev(dev);
1281 platform_set_drvdata(pdev, NULL);
1282 }
1283
1284 return 0;
1285}
1286
c1f598fd
HS		 1287#ifdef CONFIG_PM
1288static int macb_suspend(struct platform_device *pdev, pm_message_t state)
1289{
1290 struct net_device *netdev = platform_get_drvdata(pdev);
1291 struct macb *bp = netdev_priv(netdev);
1292
1293 netif_device_detach(netdev);
1294
1295#ifndef CONFIG_ARCH_AT91
1296 clk_disable(bp->hclk);
1297#endif
1298 clk_disable(bp->pclk);
1299
1300 return 0;
1301}
1302
1303static int macb_resume(struct platform_device *pdev)
1304{
1305 struct net_device *netdev = platform_get_drvdata(pdev);
1306 struct macb *bp = netdev_priv(netdev);
1307
1308 clk_enable(bp->pclk);
1309#ifndef CONFIG_ARCH_AT91
1310 clk_enable(bp->hclk);
1311#endif
1312
1313 netif_device_attach(netdev);
1314
1315 return 0;
1316}
1317#else
1318#define macb_suspend NULL
1319#define macb_resume NULL
1320#endif
1321
89e5785f 1322static struct platform_driver macb_driver = {
06c3fd6a 1323 .remove = __exit_p(macb_remove),
c1f598fd
HS		 1324 .suspend = macb_suspend,
1325 .resume = macb_resume,
89e5785f
HS		 1326 .driver = {
1327 .name = "macb",
72abb461 1328 .owner = THIS_MODULE,
89e5785f
HS		 1329 },
1330};
1331
1332static int __init macb_init(void)
1333{
06c3fd6a 1334 return platform_driver_probe(&macb_driver, macb_probe);
89e5785f
HS		 1335}
1336
1337static void __exit macb_exit(void)
1338{
1339 platform_driver_unregister(&macb_driver);
1340}
1341
1342module_init(macb_init);
1343module_exit(macb_exit);
1344
1345MODULE_LICENSE("GPL");
1346MODULE_DESCRIPTION("Atmel MACB Ethernet driver");
1347MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
72abb461 1348MODULE_ALIAS("platform:macb");
Linux kernel - Deliverables
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