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8250.c: port.lock is irq-safe
[deliverable/linux.git] / drivers / net / macb.c
CommitLineData
89e5785f
HS		 1/*
2 * Atmel MACB Ethernet Controller driver
3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/clk.h>
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/slab.h>
17#include <linux/init.h>
18#include <linux/netdevice.h>
19#include <linux/etherdevice.h>
89e5785f 20#include <linux/dma-mapping.h>
89e5785f 21#include <linux/platform_device.h>
6c36a707 22#include <linux/phy.h>
89e5785f
HS		 23
24#include <asm/arch/board.h>
6c36a707 25#include <asm/arch/cpu.h>
89e5785f
HS		 26
27#include "macb.h"
28
89e5785f
HS		 29#define RX_BUFFER_SIZE 128
30#define RX_RING_SIZE 512
31#define RX_RING_BYTES (sizeof(struct dma_desc) * RX_RING_SIZE)
32
33/* Make the IP header word-aligned (the ethernet header is 14 bytes) */
34#define RX_OFFSET 2
35
36#define TX_RING_SIZE 128
37#define DEF_TX_RING_PENDING (TX_RING_SIZE - 1)
38#define TX_RING_BYTES (sizeof(struct dma_desc) * TX_RING_SIZE)
39
40#define TX_RING_GAP(bp) \
41 (TX_RING_SIZE - (bp)->tx_pending)
42#define TX_BUFFS_AVAIL(bp) \
43 (((bp)->tx_tail <= (bp)->tx_head) ? \
44 (bp)->tx_tail + (bp)->tx_pending - (bp)->tx_head : \
45 (bp)->tx_tail - (bp)->tx_head - TX_RING_GAP(bp))
46#define NEXT_TX(n) (((n) + 1) & (TX_RING_SIZE - 1))
47
48#define NEXT_RX(n) (((n) + 1) & (RX_RING_SIZE - 1))
49
50/* minimum number of free TX descriptors before waking up TX process */
51#define MACB_TX_WAKEUP_THRESH (TX_RING_SIZE / 4)
52
53#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
54 | MACB_BIT(ISR_ROVR))
55
56static void __macb_set_hwaddr(struct macb *bp)
57{
58 u32 bottom;
59 u16 top;
60
61 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
62 macb_writel(bp, SA1B, bottom);
63 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
64 macb_writel(bp, SA1T, top);
65}
66
67static void __init macb_get_hwaddr(struct macb *bp)
68{
69 u32 bottom;
70 u16 top;
71 u8 addr[6];
72
73 bottom = macb_readl(bp, SA1B);
74 top = macb_readl(bp, SA1T);
75
76 addr[0] = bottom & 0xff;
77 addr[1] = (bottom >> 8) & 0xff;
78 addr[2] = (bottom >> 16) & 0xff;
79 addr[3] = (bottom >> 24) & 0xff;
80 addr[4] = top & 0xff;
81 addr[5] = (top >> 8) & 0xff;
82
d1d5741d 83 if (is_valid_ether_addr(addr)) {
89e5785f 84 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
d1d5741d
SS		 85 } else {
86 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
87 random_ether_addr(bp->dev->dev_addr);
88 }
89e5785f
HS		 89}
90
6c36a707 91static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
89e5785f 92{
6c36a707 93 struct macb *bp = bus->priv;
89e5785f
HS		 94 int value;
95
89e5785f
HS		 96 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
97 | MACB_BF(RW, MACB_MAN_READ)
6c36a707
R		 98 | MACB_BF(PHYA, mii_id)
99 | MACB_BF(REGA, regnum)
89e5785f
HS		 100 | MACB_BF(CODE, MACB_MAN_CODE)));
101
6c36a707
R		 102 /* wait for end of transfer */
103 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
104 cpu_relax();
89e5785f
HS		 105
106 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
89e5785f
HS		 107
108 return value;
109}
110
6c36a707
R		 111static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
112 u16 value)
89e5785f 113{
6c36a707 114 struct macb *bp = bus->priv;
89e5785f
HS		 115
116 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
117 | MACB_BF(RW, MACB_MAN_WRITE)
6c36a707
R		 118 | MACB_BF(PHYA, mii_id)
119 | MACB_BF(REGA, regnum)
89e5785f 120 | MACB_BF(CODE, MACB_MAN_CODE)
6c36a707 121 | MACB_BF(DATA, value)));
89e5785f 122
6c36a707
R		 123 /* wait for end of transfer */
124 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
125 cpu_relax();
126
127 return 0;
128}
89e5785f 129
6c36a707
R		 130static int macb_mdio_reset(struct mii_bus *bus)
131{
132 return 0;
89e5785f
HS		 133}
134
6c36a707 135static void macb_handle_link_change(struct net_device *dev)
89e5785f 136{
6c36a707
R		 137 struct macb *bp = netdev_priv(dev);
138 struct phy_device *phydev = bp->phy_dev;
139 unsigned long flags;
89e5785f 140
6c36a707 141 int status_change = 0;
89e5785f 142
6c36a707
R		 143 spin_lock_irqsave(&bp->lock, flags);
144
145 if (phydev->link) {
146 if ((bp->speed != phydev->speed) ||
147 (bp->duplex != phydev->duplex)) {
148 u32 reg;
149
150 reg = macb_readl(bp, NCFGR);
151 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
152
153 if (phydev->duplex)
154 reg |= MACB_BIT(FD);
179956f4 155 if (phydev->speed == SPEED_100)
6c36a707
R		 156 reg |= MACB_BIT(SPD);
157
158 macb_writel(bp, NCFGR, reg);
159
160 bp->speed = phydev->speed;
161 bp->duplex = phydev->duplex;
162 status_change = 1;
163 }
89e5785f
HS		 164 }
165
6c36a707 166 if (phydev->link != bp->link) {
c8f15686 167 if (!phydev->link) {
6c36a707
R		 168 bp->speed = 0;
169 bp->duplex = -1;
170 }
171 bp->link = phydev->link;
89e5785f 172
6c36a707
R		 173 status_change = 1;
174 }
89e5785f 175
6c36a707
R		 176 spin_unlock_irqrestore(&bp->lock, flags);
177
178 if (status_change) {
179 if (phydev->link)
180 printk(KERN_INFO "%s: link up (%d/%s)\n",
181 dev->name, phydev->speed,
182 DUPLEX_FULL == phydev->duplex ? "Full":"Half");
183 else
184 printk(KERN_INFO "%s: link down\n", dev->name);
185 }
89e5785f
HS		 186}
187
6c36a707
R		 188/* based on au1000_eth. c*/
189static int macb_mii_probe(struct net_device *dev)
89e5785f 190{
6c36a707
R		 191 struct macb *bp = netdev_priv(dev);
192 struct phy_device *phydev = NULL;
193 struct eth_platform_data *pdata;
194 int phy_addr;
89e5785f 195
6c36a707
R		 196 /* find the first phy */
197 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
198 if (bp->mii_bus.phy_map[phy_addr]) {
199 phydev = bp->mii_bus.phy_map[phy_addr];
200 break;
201 }
202 }
203
204 if (!phydev) {
205 printk (KERN_ERR "%s: no PHY found\n", dev->name);
206 return -1;
207 }
208
209 pdata = bp->pdev->dev.platform_data;
210 /* TODO : add pin_irq */
211
212 /* attach the mac to the phy */
213 if (pdata && pdata->is_rmii) {
214 phydev = phy_connect(dev, phydev->dev.bus_id,
215 &macb_handle_link_change, 0, PHY_INTERFACE_MODE_RMII);
216 } else {
217 phydev = phy_connect(dev, phydev->dev.bus_id,
218 &macb_handle_link_change, 0, PHY_INTERFACE_MODE_MII);
219 }
220
221 if (IS_ERR(phydev)) {
222 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
223 return PTR_ERR(phydev);
224 }
225
226 /* mask with MAC supported features */
227 phydev->supported &= PHY_BASIC_FEATURES;
228
229 phydev->advertising = phydev->supported;
230
231 bp->link = 0;
232 bp->speed = 0;
233 bp->duplex = -1;
234 bp->phy_dev = phydev;
235
236 return 0;
89e5785f
HS		 237}
238
6c36a707 239static int macb_mii_init(struct macb *bp)
89e5785f 240{
6c36a707
R		 241 struct eth_platform_data *pdata;
242 int err = -ENXIO, i;
89e5785f 243
6c36a707
R		 244 /* Enable managment port */
245 macb_writel(bp, NCR, MACB_BIT(MPE));
89e5785f 246
72cfe922
AN		 247 bp->mii_bus.name = "MACB_mii_bus";
248 bp->mii_bus.read = &macb_mdio_read;
249 bp->mii_bus.write = &macb_mdio_write;
250 bp->mii_bus.reset = &macb_mdio_reset;
9d9326d3 251 snprintf(bp->mii_bus.id, MII_BUS_ID_SIZE, "%x", bp->pdev->id);
72cfe922 252 bp->mii_bus.priv = bp;
6c36a707
R		 253 bp->mii_bus.dev = &bp->dev->dev;
254 pdata = bp->pdev->dev.platform_data;
89e5785f 255
6c36a707
R		 256 if (pdata)
257 bp->mii_bus.phy_mask = pdata->phy_mask;
89e5785f 258
6c36a707
R		 259 bp->mii_bus.irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
260 if (!bp->mii_bus.irq) {
261 err = -ENOMEM;
262 goto err_out;
89e5785f
HS		 263 }
264
6c36a707
R		 265 for (i = 0; i < PHY_MAX_ADDR; i++)
266 bp->mii_bus.irq[i] = PHY_POLL;
89e5785f 267
6c36a707 268 platform_set_drvdata(bp->dev, &bp->mii_bus);
89e5785f 269
6c36a707
R		 270 if (mdiobus_register(&bp->mii_bus))
271 goto err_out_free_mdio_irq;
89e5785f 272
6c36a707
R		 273 if (macb_mii_probe(bp->dev) != 0) {
274 goto err_out_unregister_bus;
275 }
89e5785f 276
6c36a707 277 return 0;
89e5785f 278
6c36a707
R		 279err_out_unregister_bus:
280 mdiobus_unregister(&bp->mii_bus);
281err_out_free_mdio_irq:
282 kfree(bp->mii_bus.irq);
283err_out:
284 return err;
89e5785f
HS		 285}
286
287static void macb_update_stats(struct macb *bp)
288{
289 u32 __iomem *reg = bp->regs + MACB_PFR;
290 u32 *p = &bp->hw_stats.rx_pause_frames;
291 u32 *end = &bp->hw_stats.tx_pause_frames + 1;
292
293 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
294
295 for(; p < end; p++, reg++)
0f0d84e5 296 *p += __raw_readl(reg);
89e5785f
HS		 297}
298
89e5785f
HS		 299static void macb_tx(struct macb *bp)
300{
301 unsigned int tail;
302 unsigned int head;
303 u32 status;
304
305 status = macb_readl(bp, TSR);
306 macb_writel(bp, TSR, status);
307
308 dev_dbg(&bp->pdev->dev, "macb_tx status = %02lx\n",
309 (unsigned long)status);
310
311 if (status & MACB_BIT(UND)) {
bdcba151 312 int i;
89e5785f 313 printk(KERN_ERR "%s: TX underrun, resetting buffers\n",
bdcba151
GC		 314 bp->dev->name);
315
316 head = bp->tx_head;
317
318 /*Mark all the buffer as used to avoid sending a lost buffer*/
319 for (i = 0; i < TX_RING_SIZE; i++)
320 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
321
322 /* free transmit buffer in upper layer*/
323 for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) {
324 struct ring_info *rp = &bp->tx_skb[tail];
325 struct sk_buff *skb = rp->skb;
326
327 BUG_ON(skb == NULL);
328
329 rmb();
330
331 dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len,
332 DMA_TO_DEVICE);
333 rp->skb = NULL;
334 dev_kfree_skb_irq(skb);
335 }
336
89e5785f
HS		 337 bp->tx_head = bp->tx_tail = 0;
338 }
339
340 if (!(status & MACB_BIT(COMP)))
341 /*
342 * This may happen when a buffer becomes complete
343 * between reading the ISR and scanning the
344 * descriptors. Nothing to worry about.
345 */
346 return;
347
348 head = bp->tx_head;
349 for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) {
350 struct ring_info *rp = &bp->tx_skb[tail];
351 struct sk_buff *skb = rp->skb;
352 u32 bufstat;
353
354 BUG_ON(skb == NULL);
355
356 rmb();
357 bufstat = bp->tx_ring[tail].ctrl;
358
359 if (!(bufstat & MACB_BIT(TX_USED)))
360 break;
361
362 dev_dbg(&bp->pdev->dev, "skb %u (data %p) TX complete\n",
363 tail, skb->data);
364 dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len,
365 DMA_TO_DEVICE);
366 bp->stats.tx_packets++;
367 bp->stats.tx_bytes += skb->len;
368 rp->skb = NULL;
369 dev_kfree_skb_irq(skb);
370 }
371
372 bp->tx_tail = tail;
373 if (netif_queue_stopped(bp->dev) &&
374 TX_BUFFS_AVAIL(bp) > MACB_TX_WAKEUP_THRESH)
375 netif_wake_queue(bp->dev);
376}
377
378static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
379 unsigned int last_frag)
380{
381 unsigned int len;
382 unsigned int frag;
383 unsigned int offset = 0;
384 struct sk_buff *skb;
385
386 len = MACB_BFEXT(RX_FRMLEN, bp->rx_ring[last_frag].ctrl);
387
388 dev_dbg(&bp->pdev->dev, "macb_rx_frame frags %u - %u (len %u)\n",
389 first_frag, last_frag, len);
390
391 skb = dev_alloc_skb(len + RX_OFFSET);
392 if (!skb) {
393 bp->stats.rx_dropped++;
394 for (frag = first_frag; ; frag = NEXT_RX(frag)) {
395 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
396 if (frag == last_frag)
397 break;
398 }
399 wmb();
400 return 1;
401 }
402
403 skb_reserve(skb, RX_OFFSET);
89e5785f
HS		 404 skb->ip_summed = CHECKSUM_NONE;
405 skb_put(skb, len);
406
407 for (frag = first_frag; ; frag = NEXT_RX(frag)) {
408 unsigned int frag_len = RX_BUFFER_SIZE;
409
410 if (offset + frag_len > len) {
411 BUG_ON(frag != last_frag);
412 frag_len = len - offset;
413 }
27d7ff46
ACM		 414 skb_copy_to_linear_data_offset(skb, offset,
415 (bp->rx_buffers +
416 (RX_BUFFER_SIZE * frag)),
417 frag_len);
89e5785f
HS		 418 offset += RX_BUFFER_SIZE;
419 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
420 wmb();
421
422 if (frag == last_frag)
423 break;
424 }
425
426 skb->protocol = eth_type_trans(skb, bp->dev);
427
428 bp->stats.rx_packets++;
429 bp->stats.rx_bytes += len;
430 bp->dev->last_rx = jiffies;
431 dev_dbg(&bp->pdev->dev, "received skb of length %u, csum: %08x\n",
432 skb->len, skb->csum);
433 netif_receive_skb(skb);
434
435 return 0;
436}
437
438/* Mark DMA descriptors from begin up to and not including end as unused */
439static void discard_partial_frame(struct macb *bp, unsigned int begin,
440 unsigned int end)
441{
442 unsigned int frag;
443
444 for (frag = begin; frag != end; frag = NEXT_RX(frag))
445 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
446 wmb();
447
448 /*
449 * When this happens, the hardware stats registers for
450 * whatever caused this is updated, so we don't have to record
451 * anything.
452 */
453}
454
455static int macb_rx(struct macb *bp, int budget)
456{
457 int received = 0;
458 unsigned int tail = bp->rx_tail;
459 int first_frag = -1;
460
461 for (; budget > 0; tail = NEXT_RX(tail)) {
462 u32 addr, ctrl;
463
464 rmb();
465 addr = bp->rx_ring[tail].addr;
466 ctrl = bp->rx_ring[tail].ctrl;
467
468 if (!(addr & MACB_BIT(RX_USED)))
469 break;
470
471 if (ctrl & MACB_BIT(RX_SOF)) {
472 if (first_frag != -1)
473 discard_partial_frame(bp, first_frag, tail);
474 first_frag = tail;
475 }
476
477 if (ctrl & MACB_BIT(RX_EOF)) {
478 int dropped;
479 BUG_ON(first_frag == -1);
480
481 dropped = macb_rx_frame(bp, first_frag, tail);
482 first_frag = -1;
483 if (!dropped) {
484 received++;
485 budget--;
486 }
487 }
488 }
489
490 if (first_frag != -1)
491 bp->rx_tail = first_frag;
492 else
493 bp->rx_tail = tail;
494
495 return received;
496}
497
bea3348e 498static int macb_poll(struct napi_struct *napi, int budget)
89e5785f 499{
bea3348e
SH		 500 struct macb *bp = container_of(napi, struct macb, napi);
501 struct net_device *dev = bp->dev;
502 int work_done;
89e5785f
HS		 503 u32 status;
504
505 status = macb_readl(bp, RSR);
506 macb_writel(bp, RSR, status);
507
bea3348e 508 work_done = 0;
89e5785f
HS		 509 if (!status) {
510 /*
511 * This may happen if an interrupt was pending before
512 * this function was called last time, and no packets
513 * have been received since.
514 */
bea3348e 515 netif_rx_complete(dev, napi);
89e5785f
HS		 516 goto out;
517 }
518
519 dev_dbg(&bp->pdev->dev, "poll: status = %08lx, budget = %d\n",
bea3348e 520 (unsigned long)status, budget);
89e5785f
HS		 521
522 if (!(status & MACB_BIT(REC))) {
523 dev_warn(&bp->pdev->dev,
524 "No RX buffers complete, status = %02lx\n",
525 (unsigned long)status);
bea3348e 526 netif_rx_complete(dev, napi);
89e5785f
HS		 527 goto out;
528 }
529
bea3348e
SH		 530 work_done = macb_rx(bp, budget);
531 if (work_done < budget)
532 netif_rx_complete(dev, napi);
89e5785f
HS		 533
534 /*
535 * We've done what we can to clean the buffers. Make sure we
536 * get notified when new packets arrive.
537 */
538out:
539 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
540
541 /* TODO: Handle errors */
542
bea3348e 543 return work_done;
89e5785f
HS		 544}
545
546static irqreturn_t macb_interrupt(int irq, void *dev_id)
547{
548 struct net_device *dev = dev_id;
549 struct macb *bp = netdev_priv(dev);
550 u32 status;
551
552 status = macb_readl(bp, ISR);
553
554 if (unlikely(!status))
555 return IRQ_NONE;
556
557 spin_lock(&bp->lock);
558
559 while (status) {
89e5785f
HS		 560 /* close possible race with dev_close */
561 if (unlikely(!netif_running(dev))) {
562 macb_writel(bp, IDR, ~0UL);
563 break;
564 }
565
566 if (status & MACB_RX_INT_FLAGS) {
bea3348e 567 if (netif_rx_schedule_prep(dev, &bp->napi)) {
89e5785f
HS		 568 /*
569 * There's no point taking any more interrupts
570 * until we have processed the buffers
571 */
572 macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
6c36a707
R		 573 dev_dbg(&bp->pdev->dev,
574 "scheduling RX softirq\n");
bea3348e 575 __netif_rx_schedule(dev, &bp->napi);
89e5785f
HS		 576 }
577 }
578
579 if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND)))
580 macb_tx(bp);
581
582 /*
583 * Link change detection isn't possible with RMII, so we'll
584 * add that if/when we get our hands on a full-blown MII PHY.
585 */
586
587 if (status & MACB_BIT(HRESP)) {
588 /*
589 * TODO: Reset the hardware, and maybe move the printk
590 * to a lower-priority context as well (work queue?)
591 */
592 printk(KERN_ERR "%s: DMA bus error: HRESP not OK\n",
593 dev->name);
594 }
595
596 status = macb_readl(bp, ISR);
597 }
598
599 spin_unlock(&bp->lock);
600
601 return IRQ_HANDLED;
602}
603
604static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
605{
606 struct macb *bp = netdev_priv(dev);
607 dma_addr_t mapping;
608 unsigned int len, entry;
609 u32 ctrl;
610
611#ifdef DEBUG
612 int i;
613 dev_dbg(&bp->pdev->dev,
614 "start_xmit: len %u head %p data %p tail %p end %p\n",
27a884dc 615 skb->len, skb->head, skb->data,
4305b541 616 skb_tail_pointer(skb), skb_end_pointer(skb));
89e5785f
HS		 617 dev_dbg(&bp->pdev->dev,
618 "data:");
619 for (i = 0; i < 16; i++)
620 printk(" %02x", (unsigned int)skb->data[i]);
621 printk("\n");
622#endif
623
624 len = skb->len;
625 spin_lock_irq(&bp->lock);
626
627 /* This is a hard error, log it. */
628 if (TX_BUFFS_AVAIL(bp) < 1) {
629 netif_stop_queue(dev);
630 spin_unlock_irq(&bp->lock);
631 dev_err(&bp->pdev->dev,
632 "BUG! Tx Ring full when queue awake!\n");
633 dev_dbg(&bp->pdev->dev, "tx_head = %u, tx_tail = %u\n",
634 bp->tx_head, bp->tx_tail);
635 return 1;
636 }
637
638 entry = bp->tx_head;
639 dev_dbg(&bp->pdev->dev, "Allocated ring entry %u\n", entry);
640 mapping = dma_map_single(&bp->pdev->dev, skb->data,
641 len, DMA_TO_DEVICE);
642 bp->tx_skb[entry].skb = skb;
643 bp->tx_skb[entry].mapping = mapping;
644 dev_dbg(&bp->pdev->dev, "Mapped skb data %p to DMA addr %08lx\n",
645 skb->data, (unsigned long)mapping);
646
647 ctrl = MACB_BF(TX_FRMLEN, len);
648 ctrl |= MACB_BIT(TX_LAST);
649 if (entry == (TX_RING_SIZE - 1))
650 ctrl |= MACB_BIT(TX_WRAP);
651
652 bp->tx_ring[entry].addr = mapping;
653 bp->tx_ring[entry].ctrl = ctrl;
654 wmb();
655
656 entry = NEXT_TX(entry);
657 bp->tx_head = entry;
658
659 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
660
661 if (TX_BUFFS_AVAIL(bp) < 1)
662 netif_stop_queue(dev);
663
664 spin_unlock_irq(&bp->lock);
665
666 dev->trans_start = jiffies;
667
668 return 0;
669}
670
671static void macb_free_consistent(struct macb *bp)
672{
673 if (bp->tx_skb) {
674 kfree(bp->tx_skb);
675 bp->tx_skb = NULL;
676 }
677 if (bp->rx_ring) {
678 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
679 bp->rx_ring, bp->rx_ring_dma);
680 bp->rx_ring = NULL;
681 }
682 if (bp->tx_ring) {
683 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
684 bp->tx_ring, bp->tx_ring_dma);
685 bp->tx_ring = NULL;
686 }
687 if (bp->rx_buffers) {
688 dma_free_coherent(&bp->pdev->dev,
689 RX_RING_SIZE * RX_BUFFER_SIZE,
690 bp->rx_buffers, bp->rx_buffers_dma);
691 bp->rx_buffers = NULL;
692 }
693}
694
695static int macb_alloc_consistent(struct macb *bp)
696{
697 int size;
698
699 size = TX_RING_SIZE * sizeof(struct ring_info);
700 bp->tx_skb = kmalloc(size, GFP_KERNEL);
701 if (!bp->tx_skb)
702 goto out_err;
703
704 size = RX_RING_BYTES;
705 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
706 &bp->rx_ring_dma, GFP_KERNEL);
707 if (!bp->rx_ring)
708 goto out_err;
709 dev_dbg(&bp->pdev->dev,
710 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
711 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
712
713 size = TX_RING_BYTES;
714 bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
715 &bp->tx_ring_dma, GFP_KERNEL);
716 if (!bp->tx_ring)
717 goto out_err;
718 dev_dbg(&bp->pdev->dev,
719 "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
720 size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
721
722 size = RX_RING_SIZE * RX_BUFFER_SIZE;
723 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
724 &bp->rx_buffers_dma, GFP_KERNEL);
725 if (!bp->rx_buffers)
726 goto out_err;
727 dev_dbg(&bp->pdev->dev,
728 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
729 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
730
731 return 0;
732
733out_err:
734 macb_free_consistent(bp);
735 return -ENOMEM;
736}
737
738static void macb_init_rings(struct macb *bp)
739{
740 int i;
741 dma_addr_t addr;
742
743 addr = bp->rx_buffers_dma;
744 for (i = 0; i < RX_RING_SIZE; i++) {
745 bp->rx_ring[i].addr = addr;
746 bp->rx_ring[i].ctrl = 0;
747 addr += RX_BUFFER_SIZE;
748 }
749 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
750
751 for (i = 0; i < TX_RING_SIZE; i++) {
752 bp->tx_ring[i].addr = 0;
753 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
754 }
755 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
756
757 bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
758}
759
760static void macb_reset_hw(struct macb *bp)
761{
762 /* Make sure we have the write buffer for ourselves */
763 wmb();
764
765 /*
766 * Disable RX and TX (XXX: Should we halt the transmission
767 * more gracefully?)
768 */
769 macb_writel(bp, NCR, 0);
770
771 /* Clear the stats registers (XXX: Update stats first?) */
772 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
773
774 /* Clear all status flags */
775 macb_writel(bp, TSR, ~0UL);
776 macb_writel(bp, RSR, ~0UL);
777
778 /* Disable all interrupts */
779 macb_writel(bp, IDR, ~0UL);
780 macb_readl(bp, ISR);
781}
782
783static void macb_init_hw(struct macb *bp)
784{
785 u32 config;
786
787 macb_reset_hw(bp);
788 __macb_set_hwaddr(bp);
789
790 config = macb_readl(bp, NCFGR) & MACB_BF(CLK, -1L);
791 config |= MACB_BIT(PAE); /* PAuse Enable */
792 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
793 if (bp->dev->flags & IFF_PROMISC)
794 config |= MACB_BIT(CAF); /* Copy All Frames */
795 if (!(bp->dev->flags & IFF_BROADCAST))
796 config |= MACB_BIT(NBC); /* No BroadCast */
797 macb_writel(bp, NCFGR, config);
798
799 /* Initialize TX and RX buffers */
800 macb_writel(bp, RBQP, bp->rx_ring_dma);
801 macb_writel(bp, TBQP, bp->tx_ring_dma);
802
803 /* Enable TX and RX */
6c36a707 804 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
89e5785f
HS		 805
806 /* Enable interrupts */
807 macb_writel(bp, IER, (MACB_BIT(RCOMP)
808 | MACB_BIT(RXUBR)
809 | MACB_BIT(ISR_TUND)
810 | MACB_BIT(ISR_RLE)
811 | MACB_BIT(TXERR)
812 | MACB_BIT(TCOMP)
813 | MACB_BIT(ISR_ROVR)
814 | MACB_BIT(HRESP)));
89e5785f 815
89e5785f
HS		 816}
817
446ebd01
PV		 818/*
819 * The hash address register is 64 bits long and takes up two
820 * locations in the memory map. The least significant bits are stored
821 * in EMAC_HSL and the most significant bits in EMAC_HSH.
822 *
823 * The unicast hash enable and the multicast hash enable bits in the
824 * network configuration register enable the reception of hash matched
825 * frames. The destination address is reduced to a 6 bit index into
826 * the 64 bit hash register using the following hash function. The
827 * hash function is an exclusive or of every sixth bit of the
828 * destination address.
829 *
830 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
831 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
832 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
833 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
834 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
835 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
836 *
837 * da[0] represents the least significant bit of the first byte
838 * received, that is, the multicast/unicast indicator, and da[47]
839 * represents the most significant bit of the last byte received. If
840 * the hash index, hi[n], points to a bit that is set in the hash
841 * register then the frame will be matched according to whether the
842 * frame is multicast or unicast. A multicast match will be signalled
843 * if the multicast hash enable bit is set, da[0] is 1 and the hash
844 * index points to a bit set in the hash register. A unicast match
845 * will be signalled if the unicast hash enable bit is set, da[0] is 0
846 * and the hash index points to a bit set in the hash register. To
847 * receive all multicast frames, the hash register should be set with
848 * all ones and the multicast hash enable bit should be set in the
849 * network configuration register.
850 */
851
852static inline int hash_bit_value(int bitnr, __u8 *addr)
853{
854 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
855 return 1;
856 return 0;
857}
858
859/*
860 * Return the hash index value for the specified address.
861 */
862static int hash_get_index(__u8 *addr)
863{
864 int i, j, bitval;
865 int hash_index = 0;
866
867 for (j = 0; j < 6; j++) {
868 for (i = 0, bitval = 0; i < 8; i++)
869 bitval ^= hash_bit_value(i*6 + j, addr);
870
871 hash_index |= (bitval << j);
872 }
873
874 return hash_index;
875}
876
877/*
878 * Add multicast addresses to the internal multicast-hash table.
879 */
880static void macb_sethashtable(struct net_device *dev)
881{
882 struct dev_mc_list *curr;
883 unsigned long mc_filter[2];
884 unsigned int i, bitnr;
885 struct macb *bp = netdev_priv(dev);
886
887 mc_filter[0] = mc_filter[1] = 0;
888
889 curr = dev->mc_list;
890 for (i = 0; i < dev->mc_count; i++, curr = curr->next) {
891 if (!curr) break; /* unexpected end of list */
892
893 bitnr = hash_get_index(curr->dmi_addr);
894 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
895 }
896
897 macb_writel(bp, HRB, mc_filter[0]);
898 macb_writel(bp, HRT, mc_filter[1]);
899}
900
901/*
902 * Enable/Disable promiscuous and multicast modes.
903 */
904static void macb_set_rx_mode(struct net_device *dev)
905{
906 unsigned long cfg;
907 struct macb *bp = netdev_priv(dev);
908
909 cfg = macb_readl(bp, NCFGR);
910
911 if (dev->flags & IFF_PROMISC)
912 /* Enable promiscuous mode */
913 cfg |= MACB_BIT(CAF);
914 else if (dev->flags & (~IFF_PROMISC))
915 /* Disable promiscuous mode */
916 cfg &= ~MACB_BIT(CAF);
917
918 if (dev->flags & IFF_ALLMULTI) {
919 /* Enable all multicast mode */
920 macb_writel(bp, HRB, -1);
921 macb_writel(bp, HRT, -1);
922 cfg |= MACB_BIT(NCFGR_MTI);
923 } else if (dev->mc_count > 0) {
924 /* Enable specific multicasts */
925 macb_sethashtable(dev);
926 cfg |= MACB_BIT(NCFGR_MTI);
927 } else if (dev->flags & (~IFF_ALLMULTI)) {
928 /* Disable all multicast mode */
929 macb_writel(bp, HRB, 0);
930 macb_writel(bp, HRT, 0);
931 cfg &= ~MACB_BIT(NCFGR_MTI);
932 }
933
934 macb_writel(bp, NCFGR, cfg);
935}
936
89e5785f
HS		 937static int macb_open(struct net_device *dev)
938{
939 struct macb *bp = netdev_priv(dev);
940 int err;
941
942 dev_dbg(&bp->pdev->dev, "open\n");
943
6c36a707
R		 944 /* if the phy is not yet register, retry later*/
945 if (!bp->phy_dev)
946 return -EAGAIN;
947
89e5785f
HS		 948 if (!is_valid_ether_addr(dev->dev_addr))
949 return -EADDRNOTAVAIL;
950
951 err = macb_alloc_consistent(bp);
952 if (err) {
953 printk(KERN_ERR
954 "%s: Unable to allocate DMA memory (error %d)\n",
955 dev->name, err);
956 return err;
957 }
958
bea3348e
SH		 959 napi_enable(&bp->napi);
960
89e5785f
HS		 961 macb_init_rings(bp);
962 macb_init_hw(bp);
89e5785f 963
6c36a707
R		 964 /* schedule a link state check */
965 phy_start(bp->phy_dev);
89e5785f 966
6c36a707 967 netif_start_queue(dev);
89e5785f
HS		 968
969 return 0;
970}
971
972static int macb_close(struct net_device *dev)
973{
974 struct macb *bp = netdev_priv(dev);
975 unsigned long flags;
976
89e5785f 977 netif_stop_queue(dev);
bea3348e 978 napi_disable(&bp->napi);
89e5785f 979
6c36a707
R		 980 if (bp->phy_dev)
981 phy_stop(bp->phy_dev);
982
89e5785f
HS		 983 spin_lock_irqsave(&bp->lock, flags);
984 macb_reset_hw(bp);
985 netif_carrier_off(dev);
986 spin_unlock_irqrestore(&bp->lock, flags);
987
988 macb_free_consistent(bp);
989
990 return 0;
991}
992
993static struct net_device_stats *macb_get_stats(struct net_device *dev)
994{
995 struct macb *bp = netdev_priv(dev);
996 struct net_device_stats *nstat = &bp->stats;
997 struct macb_stats *hwstat = &bp->hw_stats;
998
6c36a707
R		 999 /* read stats from hardware */
1000 macb_update_stats(bp);
1001
89e5785f
HS		 1002 /* Convert HW stats into netdevice stats */
1003 nstat->rx_errors = (hwstat->rx_fcs_errors +
1004 hwstat->rx_align_errors +
1005 hwstat->rx_resource_errors +
1006 hwstat->rx_overruns +
1007 hwstat->rx_oversize_pkts +
1008 hwstat->rx_jabbers +
1009 hwstat->rx_undersize_pkts +
1010 hwstat->sqe_test_errors +
1011 hwstat->rx_length_mismatch);
1012 nstat->tx_errors = (hwstat->tx_late_cols +
1013 hwstat->tx_excessive_cols +
1014 hwstat->tx_underruns +
1015 hwstat->tx_carrier_errors);
1016 nstat->collisions = (hwstat->tx_single_cols +
1017 hwstat->tx_multiple_cols +
1018 hwstat->tx_excessive_cols);
1019 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1020 hwstat->rx_jabbers +
1021 hwstat->rx_undersize_pkts +
1022 hwstat->rx_length_mismatch);
1023 nstat->rx_over_errors = hwstat->rx_resource_errors;
1024 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
1025 nstat->rx_frame_errors = hwstat->rx_align_errors;
1026 nstat->rx_fifo_errors = hwstat->rx_overruns;
1027 /* XXX: What does "missed" mean? */
1028 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
1029 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
1030 nstat->tx_fifo_errors = hwstat->tx_underruns;
1031 /* Don't know about heartbeat or window errors... */
1032
1033 return nstat;
1034}
1035
1036static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1037{
1038 struct macb *bp = netdev_priv(dev);
6c36a707
R		 1039 struct phy_device *phydev = bp->phy_dev;
1040
1041 if (!phydev)
1042 return -ENODEV;
89e5785f 1043
6c36a707 1044 return phy_ethtool_gset(phydev, cmd);
89e5785f
HS		 1045}
1046
1047static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1048{
1049 struct macb *bp = netdev_priv(dev);
6c36a707 1050 struct phy_device *phydev = bp->phy_dev;
89e5785f 1051
6c36a707
R		 1052 if (!phydev)
1053 return -ENODEV;
1054
1055 return phy_ethtool_sset(phydev, cmd);
89e5785f
HS		 1056}
1057
6c36a707
R		 1058static void macb_get_drvinfo(struct net_device *dev,
1059 struct ethtool_drvinfo *info)
89e5785f
HS		 1060{
1061 struct macb *bp = netdev_priv(dev);
1062
1063 strcpy(info->driver, bp->pdev->dev.driver->name);
1064 strcpy(info->version, "$Revision: 1.14 $");
1065 strcpy(info->bus_info, bp->pdev->dev.bus_id);
1066}
1067
89e5785f
HS		 1068static struct ethtool_ops macb_ethtool_ops = {
1069 .get_settings = macb_get_settings,
1070 .set_settings = macb_set_settings,
1071 .get_drvinfo = macb_get_drvinfo,
89e5785f
HS		 1072 .get_link = ethtool_op_get_link,
1073};
1074
1075static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1076{
1077 struct macb *bp = netdev_priv(dev);
6c36a707 1078 struct phy_device *phydev = bp->phy_dev;
89e5785f
HS		 1079
1080 if (!netif_running(dev))
1081 return -EINVAL;
1082
6c36a707
R		 1083 if (!phydev)
1084 return -ENODEV;
89e5785f 1085
6c36a707 1086 return phy_mii_ioctl(phydev, if_mii(rq), cmd);
89e5785f
HS		 1087}
1088
06c3fd6a 1089static int __init macb_probe(struct platform_device *pdev)
89e5785f
HS		 1090{
1091 struct eth_platform_data *pdata;
1092 struct resource *regs;
1093 struct net_device *dev;
1094 struct macb *bp;
6c36a707 1095 struct phy_device *phydev;
89e5785f
HS		 1096 unsigned long pclk_hz;
1097 u32 config;
1098 int err = -ENXIO;
0795af57 1099 DECLARE_MAC_BUF(mac);
89e5785f
HS		 1100
1101 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1102 if (!regs) {
1103 dev_err(&pdev->dev, "no mmio resource defined\n");
1104 goto err_out;
1105 }
1106
1107 err = -ENOMEM;
1108 dev = alloc_etherdev(sizeof(*bp));
1109 if (!dev) {
1110 dev_err(&pdev->dev, "etherdev alloc failed, aborting.\n");
1111 goto err_out;
1112 }
1113
89e5785f
HS		 1114 SET_NETDEV_DEV(dev, &pdev->dev);
1115
1116 /* TODO: Actually, we have some interesting features... */
1117 dev->features |= 0;
1118
1119 bp = netdev_priv(dev);
1120 bp->pdev = pdev;
1121 bp->dev = dev;
1122
1123 spin_lock_init(&bp->lock);
1124
0cc8674f
AV		 1125#if defined(CONFIG_ARCH_AT91)
1126 bp->pclk = clk_get(&pdev->dev, "macb_clk");
1127 if (IS_ERR(bp->pclk)) {
1128 dev_err(&pdev->dev, "failed to get macb_clk\n");
1129 goto err_out_free_dev;
1130 }
1131 clk_enable(bp->pclk);
1132#else
89e5785f
HS		 1133 bp->pclk = clk_get(&pdev->dev, "pclk");
1134 if (IS_ERR(bp->pclk)) {
1135 dev_err(&pdev->dev, "failed to get pclk\n");
1136 goto err_out_free_dev;
1137 }
1138 bp->hclk = clk_get(&pdev->dev, "hclk");
1139 if (IS_ERR(bp->hclk)) {
1140 dev_err(&pdev->dev, "failed to get hclk\n");
1141 goto err_out_put_pclk;
1142 }
1143
1144 clk_enable(bp->pclk);
1145 clk_enable(bp->hclk);
0cc8674f 1146#endif
89e5785f
HS		 1147
1148 bp->regs = ioremap(regs->start, regs->end - regs->start + 1);
1149 if (!bp->regs) {
1150 dev_err(&pdev->dev, "failed to map registers, aborting.\n");
1151 err = -ENOMEM;
1152 goto err_out_disable_clocks;
1153 }
1154
1155 dev->irq = platform_get_irq(pdev, 0);
38515e90 1156 err = request_irq(dev->irq, macb_interrupt, IRQF_SAMPLE_RANDOM,
89e5785f
HS		 1157 dev->name, dev);
1158 if (err) {
1159 printk(KERN_ERR
1160 "%s: Unable to request IRQ %d (error %d)\n",
1161 dev->name, dev->irq, err);
1162 goto err_out_iounmap;
1163 }
1164
1165 dev->open = macb_open;
1166 dev->stop = macb_close;
1167 dev->hard_start_xmit = macb_start_xmit;
1168 dev->get_stats = macb_get_stats;
446ebd01 1169 dev->set_multicast_list = macb_set_rx_mode;
89e5785f 1170 dev->do_ioctl = macb_ioctl;
bea3348e 1171 netif_napi_add(dev, &bp->napi, macb_poll, 64);
89e5785f
HS		 1172 dev->ethtool_ops = &macb_ethtool_ops;
1173
1174 dev->base_addr = regs->start;
1175
89e5785f
HS		 1176 /* Set MII management clock divider */
1177 pclk_hz = clk_get_rate(bp->pclk);
1178 if (pclk_hz <= 20000000)
1179 config = MACB_BF(CLK, MACB_CLK_DIV8);
1180 else if (pclk_hz <= 40000000)
1181 config = MACB_BF(CLK, MACB_CLK_DIV16);
1182 else if (pclk_hz <= 80000000)
1183 config = MACB_BF(CLK, MACB_CLK_DIV32);
1184 else
1185 config = MACB_BF(CLK, MACB_CLK_DIV64);
1186 macb_writel(bp, NCFGR, config);
1187
89e5785f 1188 macb_get_hwaddr(bp);
89e5785f 1189 pdata = pdev->dev.platform_data;
6c36a707 1190
89e5785f 1191 if (pdata && pdata->is_rmii)
0cc8674f
AV		 1192#if defined(CONFIG_ARCH_AT91)
1193 macb_writel(bp, USRIO, (MACB_BIT(RMII) | MACB_BIT(CLKEN)) );
1194#else
89e5785f 1195 macb_writel(bp, USRIO, 0);
0cc8674f 1196#endif
89e5785f 1197 else
0cc8674f
AV		 1198#if defined(CONFIG_ARCH_AT91)
1199 macb_writel(bp, USRIO, MACB_BIT(CLKEN));
1200#else
89e5785f 1201 macb_writel(bp, USRIO, MACB_BIT(MII));
0cc8674f 1202#endif
89e5785f
HS		 1203
1204 bp->tx_pending = DEF_TX_RING_PENDING;
1205
1206 err = register_netdev(dev);
1207 if (err) {
1208 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
1209 goto err_out_free_irq;
1210 }
1211
6c36a707
R		 1212 if (macb_mii_init(bp) != 0) {
1213 goto err_out_unregister_netdev;
1214 }
89e5785f 1215
6c36a707 1216 platform_set_drvdata(pdev, dev);
89e5785f
HS		 1217
1218 printk(KERN_INFO "%s: Atmel MACB at 0x%08lx irq %d "
0795af57 1219 "(%s)\n",
89e5785f 1220 dev->name, dev->base_addr, dev->irq,
0795af57 1221 print_mac(mac, dev->dev_addr));
89e5785f 1222
6c36a707
R		 1223 phydev = bp->phy_dev;
1224 printk(KERN_INFO "%s: attached PHY driver [%s] "
1225 "(mii_bus:phy_addr=%s, irq=%d)\n",
1226 dev->name, phydev->drv->name, phydev->dev.bus_id, phydev->irq);
1227
89e5785f
HS		 1228 return 0;
1229
6c36a707
R		 1230err_out_unregister_netdev:
1231 unregister_netdev(dev);
89e5785f
HS		 1232err_out_free_irq:
1233 free_irq(dev->irq, dev);
1234err_out_iounmap:
1235 iounmap(bp->regs);
1236err_out_disable_clocks:
0cc8674f 1237#ifndef CONFIG_ARCH_AT91
89e5785f 1238 clk_disable(bp->hclk);
89e5785f 1239 clk_put(bp->hclk);
0cc8674f
AV		 1240#endif
1241 clk_disable(bp->pclk);
6c36a707 1242#ifndef CONFIG_ARCH_AT91
89e5785f 1243err_out_put_pclk:
6c36a707 1244#endif
89e5785f
HS		 1245 clk_put(bp->pclk);
1246err_out_free_dev:
1247 free_netdev(dev);
1248err_out:
1249 platform_set_drvdata(pdev, NULL);
1250 return err;
1251}
1252
06c3fd6a 1253static int __exit macb_remove(struct platform_device *pdev)
89e5785f
HS		 1254{
1255 struct net_device *dev;
1256 struct macb *bp;
1257
1258 dev = platform_get_drvdata(pdev);
1259
1260 if (dev) {
1261 bp = netdev_priv(dev);
84b7901f
AN		 1262 if (bp->phy_dev)
1263 phy_disconnect(bp->phy_dev);
6c36a707
R		 1264 mdiobus_unregister(&bp->mii_bus);
1265 kfree(bp->mii_bus.irq);
89e5785f
HS		 1266 unregister_netdev(dev);
1267 free_irq(dev->irq, dev);
1268 iounmap(bp->regs);
0cc8674f 1269#ifndef CONFIG_ARCH_AT91
89e5785f 1270 clk_disable(bp->hclk);
89e5785f 1271 clk_put(bp->hclk);
0cc8674f
AV		 1272#endif
1273 clk_disable(bp->pclk);
89e5785f
HS		 1274 clk_put(bp->pclk);
1275 free_netdev(dev);
1276 platform_set_drvdata(pdev, NULL);
1277 }
1278
1279 return 0;
1280}
1281
c1f598fd
HS		 1282#ifdef CONFIG_PM
1283static int macb_suspend(struct platform_device *pdev, pm_message_t state)
1284{
1285 struct net_device *netdev = platform_get_drvdata(pdev);
1286 struct macb *bp = netdev_priv(netdev);
1287
1288 netif_device_detach(netdev);
1289
1290#ifndef CONFIG_ARCH_AT91
1291 clk_disable(bp->hclk);
1292#endif
1293 clk_disable(bp->pclk);
1294
1295 return 0;
1296}
1297
1298static int macb_resume(struct platform_device *pdev)
1299{
1300 struct net_device *netdev = platform_get_drvdata(pdev);
1301 struct macb *bp = netdev_priv(netdev);
1302
1303 clk_enable(bp->pclk);
1304#ifndef CONFIG_ARCH_AT91
1305 clk_enable(bp->hclk);
1306#endif
1307
1308 netif_device_attach(netdev);
1309
1310 return 0;
1311}
1312#else
1313#define macb_suspend NULL
1314#define macb_resume NULL
1315#endif
1316
89e5785f 1317static struct platform_driver macb_driver = {
06c3fd6a 1318 .remove = __exit_p(macb_remove),
c1f598fd
HS		 1319 .suspend = macb_suspend,
1320 .resume = macb_resume,
89e5785f
HS		 1321 .driver = {
1322 .name = "macb",
72abb461 1323 .owner = THIS_MODULE,
89e5785f
HS		 1324 },
1325};
1326
1327static int __init macb_init(void)
1328{
06c3fd6a 1329 return platform_driver_probe(&macb_driver, macb_probe);
89e5785f
HS		 1330}
1331
1332static void __exit macb_exit(void)
1333{
1334 platform_driver_unregister(&macb_driver);
1335}
1336
1337module_init(macb_init);
1338module_exit(macb_exit);
1339
1340MODULE_LICENSE("GPL");
1341MODULE_DESCRIPTION("Atmel MACB Ethernet driver");
1342MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
72abb461 1343MODULE_ALIAS("platform:macb");
Linux kernel - Deliverables
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