Commit | Line | Data |
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89e5785f HS |
1 | /* |
2 | * Atmel MACB Ethernet Controller driver | |
3 | * | |
4 | * Copyright (C) 2004-2006 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/clk.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/moduleparam.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/types.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/init.h> | |
a6b7a407 | 18 | #include <linux/interrupt.h> |
89e5785f HS |
19 | #include <linux/netdevice.h> |
20 | #include <linux/etherdevice.h> | |
89e5785f | 21 | #include <linux/dma-mapping.h> |
89e5785f | 22 | #include <linux/platform_device.h> |
6c36a707 | 23 | #include <linux/phy.h> |
89e5785f | 24 | |
a09e64fb RK |
25 | #include <mach/board.h> |
26 | #include <mach/cpu.h> | |
89e5785f HS |
27 | |
28 | #include "macb.h" | |
29 | ||
89e5785f HS |
30 | #define RX_BUFFER_SIZE 128 |
31 | #define RX_RING_SIZE 512 | |
32 | #define RX_RING_BYTES (sizeof(struct dma_desc) * RX_RING_SIZE) | |
33 | ||
34 | /* Make the IP header word-aligned (the ethernet header is 14 bytes) */ | |
35 | #define RX_OFFSET 2 | |
36 | ||
37 | #define TX_RING_SIZE 128 | |
38 | #define DEF_TX_RING_PENDING (TX_RING_SIZE - 1) | |
39 | #define TX_RING_BYTES (sizeof(struct dma_desc) * TX_RING_SIZE) | |
40 | ||
41 | #define TX_RING_GAP(bp) \ | |
42 | (TX_RING_SIZE - (bp)->tx_pending) | |
43 | #define TX_BUFFS_AVAIL(bp) \ | |
44 | (((bp)->tx_tail <= (bp)->tx_head) ? \ | |
45 | (bp)->tx_tail + (bp)->tx_pending - (bp)->tx_head : \ | |
46 | (bp)->tx_tail - (bp)->tx_head - TX_RING_GAP(bp)) | |
47 | #define NEXT_TX(n) (((n) + 1) & (TX_RING_SIZE - 1)) | |
48 | ||
49 | #define NEXT_RX(n) (((n) + 1) & (RX_RING_SIZE - 1)) | |
50 | ||
51 | /* minimum number of free TX descriptors before waking up TX process */ | |
52 | #define MACB_TX_WAKEUP_THRESH (TX_RING_SIZE / 4) | |
53 | ||
54 | #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \ | |
55 | | MACB_BIT(ISR_ROVR)) | |
56 | ||
57 | static void __macb_set_hwaddr(struct macb *bp) | |
58 | { | |
59 | u32 bottom; | |
60 | u16 top; | |
61 | ||
62 | bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr)); | |
63 | macb_writel(bp, SA1B, bottom); | |
64 | top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4))); | |
65 | macb_writel(bp, SA1T, top); | |
66 | } | |
67 | ||
68 | static void __init macb_get_hwaddr(struct macb *bp) | |
69 | { | |
70 | u32 bottom; | |
71 | u16 top; | |
72 | u8 addr[6]; | |
73 | ||
74 | bottom = macb_readl(bp, SA1B); | |
75 | top = macb_readl(bp, SA1T); | |
76 | ||
77 | addr[0] = bottom & 0xff; | |
78 | addr[1] = (bottom >> 8) & 0xff; | |
79 | addr[2] = (bottom >> 16) & 0xff; | |
80 | addr[3] = (bottom >> 24) & 0xff; | |
81 | addr[4] = top & 0xff; | |
82 | addr[5] = (top >> 8) & 0xff; | |
83 | ||
d1d5741d | 84 | if (is_valid_ether_addr(addr)) { |
89e5785f | 85 | memcpy(bp->dev->dev_addr, addr, sizeof(addr)); |
d1d5741d SS |
86 | } else { |
87 | dev_info(&bp->pdev->dev, "invalid hw address, using random\n"); | |
88 | random_ether_addr(bp->dev->dev_addr); | |
89 | } | |
89e5785f HS |
90 | } |
91 | ||
6c36a707 | 92 | static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum) |
89e5785f | 93 | { |
6c36a707 | 94 | struct macb *bp = bus->priv; |
89e5785f HS |
95 | int value; |
96 | ||
89e5785f HS |
97 | macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) |
98 | | MACB_BF(RW, MACB_MAN_READ) | |
6c36a707 R |
99 | | MACB_BF(PHYA, mii_id) |
100 | | MACB_BF(REGA, regnum) | |
89e5785f HS |
101 | | MACB_BF(CODE, MACB_MAN_CODE))); |
102 | ||
6c36a707 R |
103 | /* wait for end of transfer */ |
104 | while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR))) | |
105 | cpu_relax(); | |
89e5785f HS |
106 | |
107 | value = MACB_BFEXT(DATA, macb_readl(bp, MAN)); | |
89e5785f HS |
108 | |
109 | return value; | |
110 | } | |
111 | ||
6c36a707 R |
112 | static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum, |
113 | u16 value) | |
89e5785f | 114 | { |
6c36a707 | 115 | struct macb *bp = bus->priv; |
89e5785f HS |
116 | |
117 | macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) | |
118 | | MACB_BF(RW, MACB_MAN_WRITE) | |
6c36a707 R |
119 | | MACB_BF(PHYA, mii_id) |
120 | | MACB_BF(REGA, regnum) | |
89e5785f | 121 | | MACB_BF(CODE, MACB_MAN_CODE) |
6c36a707 | 122 | | MACB_BF(DATA, value))); |
89e5785f | 123 | |
6c36a707 R |
124 | /* wait for end of transfer */ |
125 | while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR))) | |
126 | cpu_relax(); | |
127 | ||
128 | return 0; | |
129 | } | |
89e5785f | 130 | |
6c36a707 R |
131 | static int macb_mdio_reset(struct mii_bus *bus) |
132 | { | |
133 | return 0; | |
89e5785f HS |
134 | } |
135 | ||
6c36a707 | 136 | static void macb_handle_link_change(struct net_device *dev) |
89e5785f | 137 | { |
6c36a707 R |
138 | struct macb *bp = netdev_priv(dev); |
139 | struct phy_device *phydev = bp->phy_dev; | |
140 | unsigned long flags; | |
89e5785f | 141 | |
6c36a707 | 142 | int status_change = 0; |
89e5785f | 143 | |
6c36a707 R |
144 | spin_lock_irqsave(&bp->lock, flags); |
145 | ||
146 | if (phydev->link) { | |
147 | if ((bp->speed != phydev->speed) || | |
148 | (bp->duplex != phydev->duplex)) { | |
149 | u32 reg; | |
150 | ||
151 | reg = macb_readl(bp, NCFGR); | |
152 | reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); | |
153 | ||
154 | if (phydev->duplex) | |
155 | reg |= MACB_BIT(FD); | |
179956f4 | 156 | if (phydev->speed == SPEED_100) |
6c36a707 R |
157 | reg |= MACB_BIT(SPD); |
158 | ||
159 | macb_writel(bp, NCFGR, reg); | |
160 | ||
161 | bp->speed = phydev->speed; | |
162 | bp->duplex = phydev->duplex; | |
163 | status_change = 1; | |
164 | } | |
89e5785f HS |
165 | } |
166 | ||
6c36a707 | 167 | if (phydev->link != bp->link) { |
c8f15686 | 168 | if (!phydev->link) { |
6c36a707 R |
169 | bp->speed = 0; |
170 | bp->duplex = -1; | |
171 | } | |
172 | bp->link = phydev->link; | |
89e5785f | 173 | |
6c36a707 R |
174 | status_change = 1; |
175 | } | |
89e5785f | 176 | |
6c36a707 R |
177 | spin_unlock_irqrestore(&bp->lock, flags); |
178 | ||
179 | if (status_change) { | |
180 | if (phydev->link) | |
181 | printk(KERN_INFO "%s: link up (%d/%s)\n", | |
182 | dev->name, phydev->speed, | |
183 | DUPLEX_FULL == phydev->duplex ? "Full":"Half"); | |
184 | else | |
185 | printk(KERN_INFO "%s: link down\n", dev->name); | |
186 | } | |
89e5785f HS |
187 | } |
188 | ||
6c36a707 R |
189 | /* based on au1000_eth. c*/ |
190 | static int macb_mii_probe(struct net_device *dev) | |
89e5785f | 191 | { |
6c36a707 | 192 | struct macb *bp = netdev_priv(dev); |
7455a76f | 193 | struct phy_device *phydev; |
6c36a707 | 194 | struct eth_platform_data *pdata; |
7455a76f | 195 | int ret; |
6c36a707 | 196 | |
7455a76f | 197 | phydev = phy_find_first(bp->mii_bus); |
6c36a707 R |
198 | if (!phydev) { |
199 | printk (KERN_ERR "%s: no PHY found\n", dev->name); | |
200 | return -1; | |
201 | } | |
202 | ||
203 | pdata = bp->pdev->dev.platform_data; | |
204 | /* TODO : add pin_irq */ | |
205 | ||
206 | /* attach the mac to the phy */ | |
7455a76f JP |
207 | ret = phy_connect_direct(dev, phydev, &macb_handle_link_change, 0, |
208 | pdata && pdata->is_rmii ? | |
209 | PHY_INTERFACE_MODE_RMII : | |
210 | PHY_INTERFACE_MODE_MII); | |
211 | if (ret) { | |
6c36a707 | 212 | printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); |
7455a76f | 213 | return ret; |
6c36a707 R |
214 | } |
215 | ||
216 | /* mask with MAC supported features */ | |
217 | phydev->supported &= PHY_BASIC_FEATURES; | |
218 | ||
219 | phydev->advertising = phydev->supported; | |
220 | ||
221 | bp->link = 0; | |
222 | bp->speed = 0; | |
223 | bp->duplex = -1; | |
224 | bp->phy_dev = phydev; | |
225 | ||
226 | return 0; | |
89e5785f HS |
227 | } |
228 | ||
6c36a707 | 229 | static int macb_mii_init(struct macb *bp) |
89e5785f | 230 | { |
6c36a707 R |
231 | struct eth_platform_data *pdata; |
232 | int err = -ENXIO, i; | |
89e5785f | 233 | |
3dbda77e | 234 | /* Enable management port */ |
6c36a707 | 235 | macb_writel(bp, NCR, MACB_BIT(MPE)); |
89e5785f | 236 | |
298cf9be LB |
237 | bp->mii_bus = mdiobus_alloc(); |
238 | if (bp->mii_bus == NULL) { | |
239 | err = -ENOMEM; | |
240 | goto err_out; | |
241 | } | |
242 | ||
243 | bp->mii_bus->name = "MACB_mii_bus"; | |
244 | bp->mii_bus->read = &macb_mdio_read; | |
245 | bp->mii_bus->write = &macb_mdio_write; | |
246 | bp->mii_bus->reset = &macb_mdio_reset; | |
247 | snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%x", bp->pdev->id); | |
248 | bp->mii_bus->priv = bp; | |
249 | bp->mii_bus->parent = &bp->dev->dev; | |
6c36a707 | 250 | pdata = bp->pdev->dev.platform_data; |
89e5785f | 251 | |
6c36a707 | 252 | if (pdata) |
298cf9be | 253 | bp->mii_bus->phy_mask = pdata->phy_mask; |
89e5785f | 254 | |
298cf9be LB |
255 | bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); |
256 | if (!bp->mii_bus->irq) { | |
6c36a707 | 257 | err = -ENOMEM; |
298cf9be | 258 | goto err_out_free_mdiobus; |
89e5785f HS |
259 | } |
260 | ||
6c36a707 | 261 | for (i = 0; i < PHY_MAX_ADDR; i++) |
298cf9be | 262 | bp->mii_bus->irq[i] = PHY_POLL; |
89e5785f | 263 | |
91523947 | 264 | dev_set_drvdata(&bp->dev->dev, bp->mii_bus); |
89e5785f | 265 | |
298cf9be | 266 | if (mdiobus_register(bp->mii_bus)) |
6c36a707 | 267 | goto err_out_free_mdio_irq; |
89e5785f | 268 | |
6c36a707 R |
269 | if (macb_mii_probe(bp->dev) != 0) { |
270 | goto err_out_unregister_bus; | |
271 | } | |
89e5785f | 272 | |
6c36a707 | 273 | return 0; |
89e5785f | 274 | |
6c36a707 | 275 | err_out_unregister_bus: |
298cf9be | 276 | mdiobus_unregister(bp->mii_bus); |
6c36a707 | 277 | err_out_free_mdio_irq: |
298cf9be LB |
278 | kfree(bp->mii_bus->irq); |
279 | err_out_free_mdiobus: | |
280 | mdiobus_free(bp->mii_bus); | |
6c36a707 R |
281 | err_out: |
282 | return err; | |
89e5785f HS |
283 | } |
284 | ||
285 | static void macb_update_stats(struct macb *bp) | |
286 | { | |
287 | u32 __iomem *reg = bp->regs + MACB_PFR; | |
288 | u32 *p = &bp->hw_stats.rx_pause_frames; | |
289 | u32 *end = &bp->hw_stats.tx_pause_frames + 1; | |
290 | ||
291 | WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4); | |
292 | ||
293 | for(; p < end; p++, reg++) | |
0f0d84e5 | 294 | *p += __raw_readl(reg); |
89e5785f HS |
295 | } |
296 | ||
89e5785f HS |
297 | static void macb_tx(struct macb *bp) |
298 | { | |
299 | unsigned int tail; | |
300 | unsigned int head; | |
301 | u32 status; | |
302 | ||
303 | status = macb_readl(bp, TSR); | |
304 | macb_writel(bp, TSR, status); | |
305 | ||
306 | dev_dbg(&bp->pdev->dev, "macb_tx status = %02lx\n", | |
307 | (unsigned long)status); | |
308 | ||
ee33c585 | 309 | if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) { |
bdcba151 | 310 | int i; |
ee33c585 EW |
311 | printk(KERN_ERR "%s: TX %s, resetting buffers\n", |
312 | bp->dev->name, status & MACB_BIT(UND) ? | |
313 | "underrun" : "retry limit exceeded"); | |
bdcba151 | 314 | |
39eddb4c RR |
315 | /* Transfer ongoing, disable transmitter, to avoid confusion */ |
316 | if (status & MACB_BIT(TGO)) | |
317 | macb_writel(bp, NCR, macb_readl(bp, NCR) & ~MACB_BIT(TE)); | |
318 | ||
bdcba151 GC |
319 | head = bp->tx_head; |
320 | ||
321 | /*Mark all the buffer as used to avoid sending a lost buffer*/ | |
322 | for (i = 0; i < TX_RING_SIZE; i++) | |
323 | bp->tx_ring[i].ctrl = MACB_BIT(TX_USED); | |
324 | ||
d3e61457 TA |
325 | /* Add wrap bit */ |
326 | bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP); | |
327 | ||
bdcba151 GC |
328 | /* free transmit buffer in upper layer*/ |
329 | for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) { | |
330 | struct ring_info *rp = &bp->tx_skb[tail]; | |
331 | struct sk_buff *skb = rp->skb; | |
332 | ||
333 | BUG_ON(skb == NULL); | |
334 | ||
335 | rmb(); | |
336 | ||
337 | dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len, | |
338 | DMA_TO_DEVICE); | |
339 | rp->skb = NULL; | |
340 | dev_kfree_skb_irq(skb); | |
341 | } | |
342 | ||
89e5785f | 343 | bp->tx_head = bp->tx_tail = 0; |
39eddb4c RR |
344 | |
345 | /* Enable the transmitter again */ | |
346 | if (status & MACB_BIT(TGO)) | |
347 | macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TE)); | |
89e5785f HS |
348 | } |
349 | ||
350 | if (!(status & MACB_BIT(COMP))) | |
351 | /* | |
352 | * This may happen when a buffer becomes complete | |
353 | * between reading the ISR and scanning the | |
354 | * descriptors. Nothing to worry about. | |
355 | */ | |
356 | return; | |
357 | ||
358 | head = bp->tx_head; | |
359 | for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) { | |
360 | struct ring_info *rp = &bp->tx_skb[tail]; | |
361 | struct sk_buff *skb = rp->skb; | |
362 | u32 bufstat; | |
363 | ||
364 | BUG_ON(skb == NULL); | |
365 | ||
366 | rmb(); | |
367 | bufstat = bp->tx_ring[tail].ctrl; | |
368 | ||
369 | if (!(bufstat & MACB_BIT(TX_USED))) | |
370 | break; | |
371 | ||
372 | dev_dbg(&bp->pdev->dev, "skb %u (data %p) TX complete\n", | |
373 | tail, skb->data); | |
374 | dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len, | |
375 | DMA_TO_DEVICE); | |
376 | bp->stats.tx_packets++; | |
377 | bp->stats.tx_bytes += skb->len; | |
378 | rp->skb = NULL; | |
379 | dev_kfree_skb_irq(skb); | |
380 | } | |
381 | ||
382 | bp->tx_tail = tail; | |
383 | if (netif_queue_stopped(bp->dev) && | |
384 | TX_BUFFS_AVAIL(bp) > MACB_TX_WAKEUP_THRESH) | |
385 | netif_wake_queue(bp->dev); | |
386 | } | |
387 | ||
388 | static int macb_rx_frame(struct macb *bp, unsigned int first_frag, | |
389 | unsigned int last_frag) | |
390 | { | |
391 | unsigned int len; | |
392 | unsigned int frag; | |
393 | unsigned int offset = 0; | |
394 | struct sk_buff *skb; | |
395 | ||
396 | len = MACB_BFEXT(RX_FRMLEN, bp->rx_ring[last_frag].ctrl); | |
397 | ||
398 | dev_dbg(&bp->pdev->dev, "macb_rx_frame frags %u - %u (len %u)\n", | |
399 | first_frag, last_frag, len); | |
400 | ||
401 | skb = dev_alloc_skb(len + RX_OFFSET); | |
402 | if (!skb) { | |
403 | bp->stats.rx_dropped++; | |
404 | for (frag = first_frag; ; frag = NEXT_RX(frag)) { | |
405 | bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED); | |
406 | if (frag == last_frag) | |
407 | break; | |
408 | } | |
409 | wmb(); | |
410 | return 1; | |
411 | } | |
412 | ||
413 | skb_reserve(skb, RX_OFFSET); | |
bc8acf2c | 414 | skb_checksum_none_assert(skb); |
89e5785f HS |
415 | skb_put(skb, len); |
416 | ||
417 | for (frag = first_frag; ; frag = NEXT_RX(frag)) { | |
418 | unsigned int frag_len = RX_BUFFER_SIZE; | |
419 | ||
420 | if (offset + frag_len > len) { | |
421 | BUG_ON(frag != last_frag); | |
422 | frag_len = len - offset; | |
423 | } | |
27d7ff46 ACM |
424 | skb_copy_to_linear_data_offset(skb, offset, |
425 | (bp->rx_buffers + | |
426 | (RX_BUFFER_SIZE * frag)), | |
427 | frag_len); | |
89e5785f HS |
428 | offset += RX_BUFFER_SIZE; |
429 | bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED); | |
430 | wmb(); | |
431 | ||
432 | if (frag == last_frag) | |
433 | break; | |
434 | } | |
435 | ||
436 | skb->protocol = eth_type_trans(skb, bp->dev); | |
437 | ||
438 | bp->stats.rx_packets++; | |
439 | bp->stats.rx_bytes += len; | |
89e5785f HS |
440 | dev_dbg(&bp->pdev->dev, "received skb of length %u, csum: %08x\n", |
441 | skb->len, skb->csum); | |
442 | netif_receive_skb(skb); | |
443 | ||
444 | return 0; | |
445 | } | |
446 | ||
447 | /* Mark DMA descriptors from begin up to and not including end as unused */ | |
448 | static void discard_partial_frame(struct macb *bp, unsigned int begin, | |
449 | unsigned int end) | |
450 | { | |
451 | unsigned int frag; | |
452 | ||
453 | for (frag = begin; frag != end; frag = NEXT_RX(frag)) | |
454 | bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED); | |
455 | wmb(); | |
456 | ||
457 | /* | |
458 | * When this happens, the hardware stats registers for | |
459 | * whatever caused this is updated, so we don't have to record | |
460 | * anything. | |
461 | */ | |
462 | } | |
463 | ||
464 | static int macb_rx(struct macb *bp, int budget) | |
465 | { | |
466 | int received = 0; | |
467 | unsigned int tail = bp->rx_tail; | |
468 | int first_frag = -1; | |
469 | ||
470 | for (; budget > 0; tail = NEXT_RX(tail)) { | |
471 | u32 addr, ctrl; | |
472 | ||
473 | rmb(); | |
474 | addr = bp->rx_ring[tail].addr; | |
475 | ctrl = bp->rx_ring[tail].ctrl; | |
476 | ||
477 | if (!(addr & MACB_BIT(RX_USED))) | |
478 | break; | |
479 | ||
480 | if (ctrl & MACB_BIT(RX_SOF)) { | |
481 | if (first_frag != -1) | |
482 | discard_partial_frame(bp, first_frag, tail); | |
483 | first_frag = tail; | |
484 | } | |
485 | ||
486 | if (ctrl & MACB_BIT(RX_EOF)) { | |
487 | int dropped; | |
488 | BUG_ON(first_frag == -1); | |
489 | ||
490 | dropped = macb_rx_frame(bp, first_frag, tail); | |
491 | first_frag = -1; | |
492 | if (!dropped) { | |
493 | received++; | |
494 | budget--; | |
495 | } | |
496 | } | |
497 | } | |
498 | ||
499 | if (first_frag != -1) | |
500 | bp->rx_tail = first_frag; | |
501 | else | |
502 | bp->rx_tail = tail; | |
503 | ||
504 | return received; | |
505 | } | |
506 | ||
bea3348e | 507 | static int macb_poll(struct napi_struct *napi, int budget) |
89e5785f | 508 | { |
bea3348e | 509 | struct macb *bp = container_of(napi, struct macb, napi); |
bea3348e | 510 | int work_done; |
89e5785f HS |
511 | u32 status; |
512 | ||
513 | status = macb_readl(bp, RSR); | |
514 | macb_writel(bp, RSR, status); | |
515 | ||
bea3348e | 516 | work_done = 0; |
89e5785f HS |
517 | |
518 | dev_dbg(&bp->pdev->dev, "poll: status = %08lx, budget = %d\n", | |
bea3348e | 519 | (unsigned long)status, budget); |
89e5785f | 520 | |
bea3348e | 521 | work_done = macb_rx(bp, budget); |
b336369c | 522 | if (work_done < budget) { |
288379f0 | 523 | napi_complete(napi); |
89e5785f | 524 | |
b336369c JH |
525 | /* |
526 | * We've done what we can to clean the buffers. Make sure we | |
527 | * get notified when new packets arrive. | |
528 | */ | |
529 | macb_writel(bp, IER, MACB_RX_INT_FLAGS); | |
530 | } | |
89e5785f HS |
531 | |
532 | /* TODO: Handle errors */ | |
533 | ||
bea3348e | 534 | return work_done; |
89e5785f HS |
535 | } |
536 | ||
537 | static irqreturn_t macb_interrupt(int irq, void *dev_id) | |
538 | { | |
539 | struct net_device *dev = dev_id; | |
540 | struct macb *bp = netdev_priv(dev); | |
541 | u32 status; | |
542 | ||
543 | status = macb_readl(bp, ISR); | |
544 | ||
545 | if (unlikely(!status)) | |
546 | return IRQ_NONE; | |
547 | ||
548 | spin_lock(&bp->lock); | |
549 | ||
550 | while (status) { | |
89e5785f HS |
551 | /* close possible race with dev_close */ |
552 | if (unlikely(!netif_running(dev))) { | |
553 | macb_writel(bp, IDR, ~0UL); | |
554 | break; | |
555 | } | |
556 | ||
557 | if (status & MACB_RX_INT_FLAGS) { | |
b336369c JH |
558 | /* |
559 | * There's no point taking any more interrupts | |
560 | * until we have processed the buffers. The | |
561 | * scheduling call may fail if the poll routine | |
562 | * is already scheduled, so disable interrupts | |
563 | * now. | |
564 | */ | |
565 | macb_writel(bp, IDR, MACB_RX_INT_FLAGS); | |
566 | ||
288379f0 | 567 | if (napi_schedule_prep(&bp->napi)) { |
6c36a707 R |
568 | dev_dbg(&bp->pdev->dev, |
569 | "scheduling RX softirq\n"); | |
288379f0 | 570 | __napi_schedule(&bp->napi); |
89e5785f HS |
571 | } |
572 | } | |
573 | ||
ee33c585 EW |
574 | if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) | |
575 | MACB_BIT(ISR_RLE))) | |
89e5785f HS |
576 | macb_tx(bp); |
577 | ||
578 | /* | |
579 | * Link change detection isn't possible with RMII, so we'll | |
580 | * add that if/when we get our hands on a full-blown MII PHY. | |
581 | */ | |
582 | ||
b19f7f71 AS |
583 | if (status & MACB_BIT(ISR_ROVR)) { |
584 | /* We missed at least one packet */ | |
585 | bp->hw_stats.rx_overruns++; | |
586 | } | |
587 | ||
89e5785f HS |
588 | if (status & MACB_BIT(HRESP)) { |
589 | /* | |
590 | * TODO: Reset the hardware, and maybe move the printk | |
591 | * to a lower-priority context as well (work queue?) | |
592 | */ | |
593 | printk(KERN_ERR "%s: DMA bus error: HRESP not OK\n", | |
594 | dev->name); | |
595 | } | |
596 | ||
597 | status = macb_readl(bp, ISR); | |
598 | } | |
599 | ||
600 | spin_unlock(&bp->lock); | |
601 | ||
602 | return IRQ_HANDLED; | |
603 | } | |
604 | ||
6e8cf5c0 TP |
605 | #ifdef CONFIG_NET_POLL_CONTROLLER |
606 | /* | |
607 | * Polling receive - used by netconsole and other diagnostic tools | |
608 | * to allow network i/o with interrupts disabled. | |
609 | */ | |
610 | static void macb_poll_controller(struct net_device *dev) | |
611 | { | |
612 | unsigned long flags; | |
613 | ||
614 | local_irq_save(flags); | |
615 | macb_interrupt(dev->irq, dev); | |
616 | local_irq_restore(flags); | |
617 | } | |
618 | #endif | |
619 | ||
89e5785f HS |
620 | static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev) |
621 | { | |
622 | struct macb *bp = netdev_priv(dev); | |
623 | dma_addr_t mapping; | |
624 | unsigned int len, entry; | |
625 | u32 ctrl; | |
4871953c | 626 | unsigned long flags; |
89e5785f HS |
627 | |
628 | #ifdef DEBUG | |
629 | int i; | |
630 | dev_dbg(&bp->pdev->dev, | |
631 | "start_xmit: len %u head %p data %p tail %p end %p\n", | |
27a884dc | 632 | skb->len, skb->head, skb->data, |
4305b541 | 633 | skb_tail_pointer(skb), skb_end_pointer(skb)); |
89e5785f HS |
634 | dev_dbg(&bp->pdev->dev, |
635 | "data:"); | |
636 | for (i = 0; i < 16; i++) | |
637 | printk(" %02x", (unsigned int)skb->data[i]); | |
638 | printk("\n"); | |
639 | #endif | |
640 | ||
641 | len = skb->len; | |
4871953c | 642 | spin_lock_irqsave(&bp->lock, flags); |
89e5785f HS |
643 | |
644 | /* This is a hard error, log it. */ | |
645 | if (TX_BUFFS_AVAIL(bp) < 1) { | |
646 | netif_stop_queue(dev); | |
4871953c | 647 | spin_unlock_irqrestore(&bp->lock, flags); |
89e5785f HS |
648 | dev_err(&bp->pdev->dev, |
649 | "BUG! Tx Ring full when queue awake!\n"); | |
650 | dev_dbg(&bp->pdev->dev, "tx_head = %u, tx_tail = %u\n", | |
651 | bp->tx_head, bp->tx_tail); | |
5b548140 | 652 | return NETDEV_TX_BUSY; |
89e5785f HS |
653 | } |
654 | ||
655 | entry = bp->tx_head; | |
656 | dev_dbg(&bp->pdev->dev, "Allocated ring entry %u\n", entry); | |
657 | mapping = dma_map_single(&bp->pdev->dev, skb->data, | |
658 | len, DMA_TO_DEVICE); | |
659 | bp->tx_skb[entry].skb = skb; | |
660 | bp->tx_skb[entry].mapping = mapping; | |
661 | dev_dbg(&bp->pdev->dev, "Mapped skb data %p to DMA addr %08lx\n", | |
662 | skb->data, (unsigned long)mapping); | |
663 | ||
664 | ctrl = MACB_BF(TX_FRMLEN, len); | |
665 | ctrl |= MACB_BIT(TX_LAST); | |
666 | if (entry == (TX_RING_SIZE - 1)) | |
667 | ctrl |= MACB_BIT(TX_WRAP); | |
668 | ||
669 | bp->tx_ring[entry].addr = mapping; | |
670 | bp->tx_ring[entry].ctrl = ctrl; | |
671 | wmb(); | |
672 | ||
673 | entry = NEXT_TX(entry); | |
674 | bp->tx_head = entry; | |
675 | ||
e072092f RC |
676 | skb_tx_timestamp(skb); |
677 | ||
89e5785f HS |
678 | macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART)); |
679 | ||
680 | if (TX_BUFFS_AVAIL(bp) < 1) | |
681 | netif_stop_queue(dev); | |
682 | ||
4871953c | 683 | spin_unlock_irqrestore(&bp->lock, flags); |
89e5785f | 684 | |
6ed10654 | 685 | return NETDEV_TX_OK; |
89e5785f HS |
686 | } |
687 | ||
688 | static void macb_free_consistent(struct macb *bp) | |
689 | { | |
690 | if (bp->tx_skb) { | |
691 | kfree(bp->tx_skb); | |
692 | bp->tx_skb = NULL; | |
693 | } | |
694 | if (bp->rx_ring) { | |
695 | dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES, | |
696 | bp->rx_ring, bp->rx_ring_dma); | |
697 | bp->rx_ring = NULL; | |
698 | } | |
699 | if (bp->tx_ring) { | |
700 | dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES, | |
701 | bp->tx_ring, bp->tx_ring_dma); | |
702 | bp->tx_ring = NULL; | |
703 | } | |
704 | if (bp->rx_buffers) { | |
705 | dma_free_coherent(&bp->pdev->dev, | |
706 | RX_RING_SIZE * RX_BUFFER_SIZE, | |
707 | bp->rx_buffers, bp->rx_buffers_dma); | |
708 | bp->rx_buffers = NULL; | |
709 | } | |
710 | } | |
711 | ||
712 | static int macb_alloc_consistent(struct macb *bp) | |
713 | { | |
714 | int size; | |
715 | ||
716 | size = TX_RING_SIZE * sizeof(struct ring_info); | |
717 | bp->tx_skb = kmalloc(size, GFP_KERNEL); | |
718 | if (!bp->tx_skb) | |
719 | goto out_err; | |
720 | ||
721 | size = RX_RING_BYTES; | |
722 | bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size, | |
723 | &bp->rx_ring_dma, GFP_KERNEL); | |
724 | if (!bp->rx_ring) | |
725 | goto out_err; | |
726 | dev_dbg(&bp->pdev->dev, | |
727 | "Allocated RX ring of %d bytes at %08lx (mapped %p)\n", | |
728 | size, (unsigned long)bp->rx_ring_dma, bp->rx_ring); | |
729 | ||
730 | size = TX_RING_BYTES; | |
731 | bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size, | |
732 | &bp->tx_ring_dma, GFP_KERNEL); | |
733 | if (!bp->tx_ring) | |
734 | goto out_err; | |
735 | dev_dbg(&bp->pdev->dev, | |
736 | "Allocated TX ring of %d bytes at %08lx (mapped %p)\n", | |
737 | size, (unsigned long)bp->tx_ring_dma, bp->tx_ring); | |
738 | ||
739 | size = RX_RING_SIZE * RX_BUFFER_SIZE; | |
740 | bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size, | |
741 | &bp->rx_buffers_dma, GFP_KERNEL); | |
742 | if (!bp->rx_buffers) | |
743 | goto out_err; | |
744 | dev_dbg(&bp->pdev->dev, | |
745 | "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n", | |
746 | size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers); | |
747 | ||
748 | return 0; | |
749 | ||
750 | out_err: | |
751 | macb_free_consistent(bp); | |
752 | return -ENOMEM; | |
753 | } | |
754 | ||
755 | static void macb_init_rings(struct macb *bp) | |
756 | { | |
757 | int i; | |
758 | dma_addr_t addr; | |
759 | ||
760 | addr = bp->rx_buffers_dma; | |
761 | for (i = 0; i < RX_RING_SIZE; i++) { | |
762 | bp->rx_ring[i].addr = addr; | |
763 | bp->rx_ring[i].ctrl = 0; | |
764 | addr += RX_BUFFER_SIZE; | |
765 | } | |
766 | bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP); | |
767 | ||
768 | for (i = 0; i < TX_RING_SIZE; i++) { | |
769 | bp->tx_ring[i].addr = 0; | |
770 | bp->tx_ring[i].ctrl = MACB_BIT(TX_USED); | |
771 | } | |
772 | bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP); | |
773 | ||
774 | bp->rx_tail = bp->tx_head = bp->tx_tail = 0; | |
775 | } | |
776 | ||
777 | static void macb_reset_hw(struct macb *bp) | |
778 | { | |
779 | /* Make sure we have the write buffer for ourselves */ | |
780 | wmb(); | |
781 | ||
782 | /* | |
783 | * Disable RX and TX (XXX: Should we halt the transmission | |
784 | * more gracefully?) | |
785 | */ | |
786 | macb_writel(bp, NCR, 0); | |
787 | ||
788 | /* Clear the stats registers (XXX: Update stats first?) */ | |
789 | macb_writel(bp, NCR, MACB_BIT(CLRSTAT)); | |
790 | ||
791 | /* Clear all status flags */ | |
792 | macb_writel(bp, TSR, ~0UL); | |
793 | macb_writel(bp, RSR, ~0UL); | |
794 | ||
795 | /* Disable all interrupts */ | |
796 | macb_writel(bp, IDR, ~0UL); | |
797 | macb_readl(bp, ISR); | |
798 | } | |
799 | ||
800 | static void macb_init_hw(struct macb *bp) | |
801 | { | |
802 | u32 config; | |
803 | ||
804 | macb_reset_hw(bp); | |
805 | __macb_set_hwaddr(bp); | |
806 | ||
807 | config = macb_readl(bp, NCFGR) & MACB_BF(CLK, -1L); | |
808 | config |= MACB_BIT(PAE); /* PAuse Enable */ | |
809 | config |= MACB_BIT(DRFCS); /* Discard Rx FCS */ | |
8dd4bd00 | 810 | config |= MACB_BIT(BIG); /* Receive oversized frames */ |
89e5785f HS |
811 | if (bp->dev->flags & IFF_PROMISC) |
812 | config |= MACB_BIT(CAF); /* Copy All Frames */ | |
813 | if (!(bp->dev->flags & IFF_BROADCAST)) | |
814 | config |= MACB_BIT(NBC); /* No BroadCast */ | |
815 | macb_writel(bp, NCFGR, config); | |
816 | ||
817 | /* Initialize TX and RX buffers */ | |
818 | macb_writel(bp, RBQP, bp->rx_ring_dma); | |
819 | macb_writel(bp, TBQP, bp->tx_ring_dma); | |
820 | ||
821 | /* Enable TX and RX */ | |
6c36a707 | 822 | macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE)); |
89e5785f HS |
823 | |
824 | /* Enable interrupts */ | |
825 | macb_writel(bp, IER, (MACB_BIT(RCOMP) | |
826 | | MACB_BIT(RXUBR) | |
827 | | MACB_BIT(ISR_TUND) | |
828 | | MACB_BIT(ISR_RLE) | |
829 | | MACB_BIT(TXERR) | |
830 | | MACB_BIT(TCOMP) | |
831 | | MACB_BIT(ISR_ROVR) | |
832 | | MACB_BIT(HRESP))); | |
89e5785f | 833 | |
89e5785f HS |
834 | } |
835 | ||
446ebd01 PV |
836 | /* |
837 | * The hash address register is 64 bits long and takes up two | |
838 | * locations in the memory map. The least significant bits are stored | |
839 | * in EMAC_HSL and the most significant bits in EMAC_HSH. | |
840 | * | |
841 | * The unicast hash enable and the multicast hash enable bits in the | |
842 | * network configuration register enable the reception of hash matched | |
843 | * frames. The destination address is reduced to a 6 bit index into | |
844 | * the 64 bit hash register using the following hash function. The | |
845 | * hash function is an exclusive or of every sixth bit of the | |
846 | * destination address. | |
847 | * | |
848 | * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] | |
849 | * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] | |
850 | * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] | |
851 | * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] | |
852 | * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] | |
853 | * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] | |
854 | * | |
855 | * da[0] represents the least significant bit of the first byte | |
856 | * received, that is, the multicast/unicast indicator, and da[47] | |
857 | * represents the most significant bit of the last byte received. If | |
858 | * the hash index, hi[n], points to a bit that is set in the hash | |
859 | * register then the frame will be matched according to whether the | |
860 | * frame is multicast or unicast. A multicast match will be signalled | |
861 | * if the multicast hash enable bit is set, da[0] is 1 and the hash | |
862 | * index points to a bit set in the hash register. A unicast match | |
863 | * will be signalled if the unicast hash enable bit is set, da[0] is 0 | |
864 | * and the hash index points to a bit set in the hash register. To | |
865 | * receive all multicast frames, the hash register should be set with | |
866 | * all ones and the multicast hash enable bit should be set in the | |
867 | * network configuration register. | |
868 | */ | |
869 | ||
870 | static inline int hash_bit_value(int bitnr, __u8 *addr) | |
871 | { | |
872 | if (addr[bitnr / 8] & (1 << (bitnr % 8))) | |
873 | return 1; | |
874 | return 0; | |
875 | } | |
876 | ||
877 | /* | |
878 | * Return the hash index value for the specified address. | |
879 | */ | |
880 | static int hash_get_index(__u8 *addr) | |
881 | { | |
882 | int i, j, bitval; | |
883 | int hash_index = 0; | |
884 | ||
885 | for (j = 0; j < 6; j++) { | |
886 | for (i = 0, bitval = 0; i < 8; i++) | |
887 | bitval ^= hash_bit_value(i*6 + j, addr); | |
888 | ||
889 | hash_index |= (bitval << j); | |
890 | } | |
891 | ||
892 | return hash_index; | |
893 | } | |
894 | ||
895 | /* | |
896 | * Add multicast addresses to the internal multicast-hash table. | |
897 | */ | |
898 | static void macb_sethashtable(struct net_device *dev) | |
899 | { | |
22bedad3 | 900 | struct netdev_hw_addr *ha; |
446ebd01 | 901 | unsigned long mc_filter[2]; |
f9dcbcc9 | 902 | unsigned int bitnr; |
446ebd01 PV |
903 | struct macb *bp = netdev_priv(dev); |
904 | ||
905 | mc_filter[0] = mc_filter[1] = 0; | |
906 | ||
22bedad3 JP |
907 | netdev_for_each_mc_addr(ha, dev) { |
908 | bitnr = hash_get_index(ha->addr); | |
446ebd01 PV |
909 | mc_filter[bitnr >> 5] |= 1 << (bitnr & 31); |
910 | } | |
911 | ||
912 | macb_writel(bp, HRB, mc_filter[0]); | |
913 | macb_writel(bp, HRT, mc_filter[1]); | |
914 | } | |
915 | ||
916 | /* | |
917 | * Enable/Disable promiscuous and multicast modes. | |
918 | */ | |
919 | static void macb_set_rx_mode(struct net_device *dev) | |
920 | { | |
921 | unsigned long cfg; | |
922 | struct macb *bp = netdev_priv(dev); | |
923 | ||
924 | cfg = macb_readl(bp, NCFGR); | |
925 | ||
926 | if (dev->flags & IFF_PROMISC) | |
927 | /* Enable promiscuous mode */ | |
928 | cfg |= MACB_BIT(CAF); | |
929 | else if (dev->flags & (~IFF_PROMISC)) | |
930 | /* Disable promiscuous mode */ | |
931 | cfg &= ~MACB_BIT(CAF); | |
932 | ||
933 | if (dev->flags & IFF_ALLMULTI) { | |
934 | /* Enable all multicast mode */ | |
935 | macb_writel(bp, HRB, -1); | |
936 | macb_writel(bp, HRT, -1); | |
937 | cfg |= MACB_BIT(NCFGR_MTI); | |
4cd24eaf | 938 | } else if (!netdev_mc_empty(dev)) { |
446ebd01 PV |
939 | /* Enable specific multicasts */ |
940 | macb_sethashtable(dev); | |
941 | cfg |= MACB_BIT(NCFGR_MTI); | |
942 | } else if (dev->flags & (~IFF_ALLMULTI)) { | |
943 | /* Disable all multicast mode */ | |
944 | macb_writel(bp, HRB, 0); | |
945 | macb_writel(bp, HRT, 0); | |
946 | cfg &= ~MACB_BIT(NCFGR_MTI); | |
947 | } | |
948 | ||
949 | macb_writel(bp, NCFGR, cfg); | |
950 | } | |
951 | ||
89e5785f HS |
952 | static int macb_open(struct net_device *dev) |
953 | { | |
954 | struct macb *bp = netdev_priv(dev); | |
955 | int err; | |
956 | ||
957 | dev_dbg(&bp->pdev->dev, "open\n"); | |
958 | ||
6c36a707 R |
959 | /* if the phy is not yet register, retry later*/ |
960 | if (!bp->phy_dev) | |
961 | return -EAGAIN; | |
962 | ||
89e5785f HS |
963 | if (!is_valid_ether_addr(dev->dev_addr)) |
964 | return -EADDRNOTAVAIL; | |
965 | ||
966 | err = macb_alloc_consistent(bp); | |
967 | if (err) { | |
968 | printk(KERN_ERR | |
969 | "%s: Unable to allocate DMA memory (error %d)\n", | |
970 | dev->name, err); | |
971 | return err; | |
972 | } | |
973 | ||
bea3348e SH |
974 | napi_enable(&bp->napi); |
975 | ||
89e5785f HS |
976 | macb_init_rings(bp); |
977 | macb_init_hw(bp); | |
89e5785f | 978 | |
6c36a707 R |
979 | /* schedule a link state check */ |
980 | phy_start(bp->phy_dev); | |
89e5785f | 981 | |
6c36a707 | 982 | netif_start_queue(dev); |
89e5785f HS |
983 | |
984 | return 0; | |
985 | } | |
986 | ||
987 | static int macb_close(struct net_device *dev) | |
988 | { | |
989 | struct macb *bp = netdev_priv(dev); | |
990 | unsigned long flags; | |
991 | ||
89e5785f | 992 | netif_stop_queue(dev); |
bea3348e | 993 | napi_disable(&bp->napi); |
89e5785f | 994 | |
6c36a707 R |
995 | if (bp->phy_dev) |
996 | phy_stop(bp->phy_dev); | |
997 | ||
89e5785f HS |
998 | spin_lock_irqsave(&bp->lock, flags); |
999 | macb_reset_hw(bp); | |
1000 | netif_carrier_off(dev); | |
1001 | spin_unlock_irqrestore(&bp->lock, flags); | |
1002 | ||
1003 | macb_free_consistent(bp); | |
1004 | ||
1005 | return 0; | |
1006 | } | |
1007 | ||
1008 | static struct net_device_stats *macb_get_stats(struct net_device *dev) | |
1009 | { | |
1010 | struct macb *bp = netdev_priv(dev); | |
1011 | struct net_device_stats *nstat = &bp->stats; | |
1012 | struct macb_stats *hwstat = &bp->hw_stats; | |
1013 | ||
6c36a707 R |
1014 | /* read stats from hardware */ |
1015 | macb_update_stats(bp); | |
1016 | ||
89e5785f HS |
1017 | /* Convert HW stats into netdevice stats */ |
1018 | nstat->rx_errors = (hwstat->rx_fcs_errors + | |
1019 | hwstat->rx_align_errors + | |
1020 | hwstat->rx_resource_errors + | |
1021 | hwstat->rx_overruns + | |
1022 | hwstat->rx_oversize_pkts + | |
1023 | hwstat->rx_jabbers + | |
1024 | hwstat->rx_undersize_pkts + | |
1025 | hwstat->sqe_test_errors + | |
1026 | hwstat->rx_length_mismatch); | |
1027 | nstat->tx_errors = (hwstat->tx_late_cols + | |
1028 | hwstat->tx_excessive_cols + | |
1029 | hwstat->tx_underruns + | |
1030 | hwstat->tx_carrier_errors); | |
1031 | nstat->collisions = (hwstat->tx_single_cols + | |
1032 | hwstat->tx_multiple_cols + | |
1033 | hwstat->tx_excessive_cols); | |
1034 | nstat->rx_length_errors = (hwstat->rx_oversize_pkts + | |
1035 | hwstat->rx_jabbers + | |
1036 | hwstat->rx_undersize_pkts + | |
1037 | hwstat->rx_length_mismatch); | |
b19f7f71 AS |
1038 | nstat->rx_over_errors = hwstat->rx_resource_errors + |
1039 | hwstat->rx_overruns; | |
89e5785f HS |
1040 | nstat->rx_crc_errors = hwstat->rx_fcs_errors; |
1041 | nstat->rx_frame_errors = hwstat->rx_align_errors; | |
1042 | nstat->rx_fifo_errors = hwstat->rx_overruns; | |
1043 | /* XXX: What does "missed" mean? */ | |
1044 | nstat->tx_aborted_errors = hwstat->tx_excessive_cols; | |
1045 | nstat->tx_carrier_errors = hwstat->tx_carrier_errors; | |
1046 | nstat->tx_fifo_errors = hwstat->tx_underruns; | |
1047 | /* Don't know about heartbeat or window errors... */ | |
1048 | ||
1049 | return nstat; | |
1050 | } | |
1051 | ||
1052 | static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1053 | { | |
1054 | struct macb *bp = netdev_priv(dev); | |
6c36a707 R |
1055 | struct phy_device *phydev = bp->phy_dev; |
1056 | ||
1057 | if (!phydev) | |
1058 | return -ENODEV; | |
89e5785f | 1059 | |
6c36a707 | 1060 | return phy_ethtool_gset(phydev, cmd); |
89e5785f HS |
1061 | } |
1062 | ||
1063 | static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1064 | { | |
1065 | struct macb *bp = netdev_priv(dev); | |
6c36a707 | 1066 | struct phy_device *phydev = bp->phy_dev; |
89e5785f | 1067 | |
6c36a707 R |
1068 | if (!phydev) |
1069 | return -ENODEV; | |
1070 | ||
1071 | return phy_ethtool_sset(phydev, cmd); | |
89e5785f HS |
1072 | } |
1073 | ||
6c36a707 R |
1074 | static void macb_get_drvinfo(struct net_device *dev, |
1075 | struct ethtool_drvinfo *info) | |
89e5785f HS |
1076 | { |
1077 | struct macb *bp = netdev_priv(dev); | |
1078 | ||
1079 | strcpy(info->driver, bp->pdev->dev.driver->name); | |
1080 | strcpy(info->version, "$Revision: 1.14 $"); | |
db1d7bf7 | 1081 | strcpy(info->bus_info, dev_name(&bp->pdev->dev)); |
89e5785f HS |
1082 | } |
1083 | ||
0fc0b732 | 1084 | static const struct ethtool_ops macb_ethtool_ops = { |
89e5785f HS |
1085 | .get_settings = macb_get_settings, |
1086 | .set_settings = macb_set_settings, | |
1087 | .get_drvinfo = macb_get_drvinfo, | |
89e5785f HS |
1088 | .get_link = ethtool_op_get_link, |
1089 | }; | |
1090 | ||
1091 | static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
1092 | { | |
1093 | struct macb *bp = netdev_priv(dev); | |
6c36a707 | 1094 | struct phy_device *phydev = bp->phy_dev; |
89e5785f HS |
1095 | |
1096 | if (!netif_running(dev)) | |
1097 | return -EINVAL; | |
1098 | ||
6c36a707 R |
1099 | if (!phydev) |
1100 | return -ENODEV; | |
89e5785f | 1101 | |
28b04113 | 1102 | return phy_mii_ioctl(phydev, rq, cmd); |
89e5785f HS |
1103 | } |
1104 | ||
5f1fa992 AB |
1105 | static const struct net_device_ops macb_netdev_ops = { |
1106 | .ndo_open = macb_open, | |
1107 | .ndo_stop = macb_close, | |
1108 | .ndo_start_xmit = macb_start_xmit, | |
1109 | .ndo_set_multicast_list = macb_set_rx_mode, | |
1110 | .ndo_get_stats = macb_get_stats, | |
1111 | .ndo_do_ioctl = macb_ioctl, | |
1112 | .ndo_validate_addr = eth_validate_addr, | |
1113 | .ndo_change_mtu = eth_change_mtu, | |
1114 | .ndo_set_mac_address = eth_mac_addr, | |
6e8cf5c0 TP |
1115 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1116 | .ndo_poll_controller = macb_poll_controller, | |
1117 | #endif | |
5f1fa992 AB |
1118 | }; |
1119 | ||
06c3fd6a | 1120 | static int __init macb_probe(struct platform_device *pdev) |
89e5785f HS |
1121 | { |
1122 | struct eth_platform_data *pdata; | |
1123 | struct resource *regs; | |
1124 | struct net_device *dev; | |
1125 | struct macb *bp; | |
6c36a707 | 1126 | struct phy_device *phydev; |
89e5785f HS |
1127 | unsigned long pclk_hz; |
1128 | u32 config; | |
1129 | int err = -ENXIO; | |
1130 | ||
1131 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1132 | if (!regs) { | |
1133 | dev_err(&pdev->dev, "no mmio resource defined\n"); | |
1134 | goto err_out; | |
1135 | } | |
1136 | ||
1137 | err = -ENOMEM; | |
1138 | dev = alloc_etherdev(sizeof(*bp)); | |
1139 | if (!dev) { | |
1140 | dev_err(&pdev->dev, "etherdev alloc failed, aborting.\n"); | |
1141 | goto err_out; | |
1142 | } | |
1143 | ||
89e5785f HS |
1144 | SET_NETDEV_DEV(dev, &pdev->dev); |
1145 | ||
1146 | /* TODO: Actually, we have some interesting features... */ | |
1147 | dev->features |= 0; | |
1148 | ||
1149 | bp = netdev_priv(dev); | |
1150 | bp->pdev = pdev; | |
1151 | bp->dev = dev; | |
1152 | ||
1153 | spin_lock_init(&bp->lock); | |
1154 | ||
0cc8674f AV |
1155 | #if defined(CONFIG_ARCH_AT91) |
1156 | bp->pclk = clk_get(&pdev->dev, "macb_clk"); | |
1157 | if (IS_ERR(bp->pclk)) { | |
1158 | dev_err(&pdev->dev, "failed to get macb_clk\n"); | |
1159 | goto err_out_free_dev; | |
1160 | } | |
1161 | clk_enable(bp->pclk); | |
1162 | #else | |
89e5785f HS |
1163 | bp->pclk = clk_get(&pdev->dev, "pclk"); |
1164 | if (IS_ERR(bp->pclk)) { | |
1165 | dev_err(&pdev->dev, "failed to get pclk\n"); | |
1166 | goto err_out_free_dev; | |
1167 | } | |
1168 | bp->hclk = clk_get(&pdev->dev, "hclk"); | |
1169 | if (IS_ERR(bp->hclk)) { | |
1170 | dev_err(&pdev->dev, "failed to get hclk\n"); | |
1171 | goto err_out_put_pclk; | |
1172 | } | |
1173 | ||
1174 | clk_enable(bp->pclk); | |
1175 | clk_enable(bp->hclk); | |
0cc8674f | 1176 | #endif |
89e5785f | 1177 | |
28f65c11 | 1178 | bp->regs = ioremap(regs->start, resource_size(regs)); |
89e5785f HS |
1179 | if (!bp->regs) { |
1180 | dev_err(&pdev->dev, "failed to map registers, aborting.\n"); | |
1181 | err = -ENOMEM; | |
1182 | goto err_out_disable_clocks; | |
1183 | } | |
1184 | ||
1185 | dev->irq = platform_get_irq(pdev, 0); | |
ab392d2d | 1186 | err = request_irq(dev->irq, macb_interrupt, 0, dev->name, dev); |
89e5785f HS |
1187 | if (err) { |
1188 | printk(KERN_ERR | |
1189 | "%s: Unable to request IRQ %d (error %d)\n", | |
1190 | dev->name, dev->irq, err); | |
1191 | goto err_out_iounmap; | |
1192 | } | |
1193 | ||
5f1fa992 | 1194 | dev->netdev_ops = &macb_netdev_ops; |
bea3348e | 1195 | netif_napi_add(dev, &bp->napi, macb_poll, 64); |
89e5785f HS |
1196 | dev->ethtool_ops = &macb_ethtool_ops; |
1197 | ||
1198 | dev->base_addr = regs->start; | |
1199 | ||
89e5785f HS |
1200 | /* Set MII management clock divider */ |
1201 | pclk_hz = clk_get_rate(bp->pclk); | |
1202 | if (pclk_hz <= 20000000) | |
1203 | config = MACB_BF(CLK, MACB_CLK_DIV8); | |
1204 | else if (pclk_hz <= 40000000) | |
1205 | config = MACB_BF(CLK, MACB_CLK_DIV16); | |
1206 | else if (pclk_hz <= 80000000) | |
1207 | config = MACB_BF(CLK, MACB_CLK_DIV32); | |
1208 | else | |
1209 | config = MACB_BF(CLK, MACB_CLK_DIV64); | |
1210 | macb_writel(bp, NCFGR, config); | |
1211 | ||
89e5785f | 1212 | macb_get_hwaddr(bp); |
89e5785f | 1213 | pdata = pdev->dev.platform_data; |
6c36a707 | 1214 | |
89e5785f | 1215 | if (pdata && pdata->is_rmii) |
0cc8674f AV |
1216 | #if defined(CONFIG_ARCH_AT91) |
1217 | macb_writel(bp, USRIO, (MACB_BIT(RMII) | MACB_BIT(CLKEN)) ); | |
1218 | #else | |
89e5785f | 1219 | macb_writel(bp, USRIO, 0); |
0cc8674f | 1220 | #endif |
89e5785f | 1221 | else |
0cc8674f AV |
1222 | #if defined(CONFIG_ARCH_AT91) |
1223 | macb_writel(bp, USRIO, MACB_BIT(CLKEN)); | |
1224 | #else | |
89e5785f | 1225 | macb_writel(bp, USRIO, MACB_BIT(MII)); |
0cc8674f | 1226 | #endif |
89e5785f HS |
1227 | |
1228 | bp->tx_pending = DEF_TX_RING_PENDING; | |
1229 | ||
1230 | err = register_netdev(dev); | |
1231 | if (err) { | |
1232 | dev_err(&pdev->dev, "Cannot register net device, aborting.\n"); | |
1233 | goto err_out_free_irq; | |
1234 | } | |
1235 | ||
6c36a707 R |
1236 | if (macb_mii_init(bp) != 0) { |
1237 | goto err_out_unregister_netdev; | |
1238 | } | |
89e5785f | 1239 | |
6c36a707 | 1240 | platform_set_drvdata(pdev, dev); |
89e5785f | 1241 | |
e174961c JB |
1242 | printk(KERN_INFO "%s: Atmel MACB at 0x%08lx irq %d (%pM)\n", |
1243 | dev->name, dev->base_addr, dev->irq, dev->dev_addr); | |
89e5785f | 1244 | |
6c36a707 R |
1245 | phydev = bp->phy_dev; |
1246 | printk(KERN_INFO "%s: attached PHY driver [%s] " | |
db1d7bf7 KS |
1247 | "(mii_bus:phy_addr=%s, irq=%d)\n", dev->name, |
1248 | phydev->drv->name, dev_name(&phydev->dev), phydev->irq); | |
6c36a707 | 1249 | |
89e5785f HS |
1250 | return 0; |
1251 | ||
6c36a707 R |
1252 | err_out_unregister_netdev: |
1253 | unregister_netdev(dev); | |
89e5785f HS |
1254 | err_out_free_irq: |
1255 | free_irq(dev->irq, dev); | |
1256 | err_out_iounmap: | |
1257 | iounmap(bp->regs); | |
1258 | err_out_disable_clocks: | |
0cc8674f | 1259 | #ifndef CONFIG_ARCH_AT91 |
89e5785f | 1260 | clk_disable(bp->hclk); |
89e5785f | 1261 | clk_put(bp->hclk); |
0cc8674f AV |
1262 | #endif |
1263 | clk_disable(bp->pclk); | |
6c36a707 | 1264 | #ifndef CONFIG_ARCH_AT91 |
89e5785f | 1265 | err_out_put_pclk: |
6c36a707 | 1266 | #endif |
89e5785f HS |
1267 | clk_put(bp->pclk); |
1268 | err_out_free_dev: | |
1269 | free_netdev(dev); | |
1270 | err_out: | |
1271 | platform_set_drvdata(pdev, NULL); | |
1272 | return err; | |
1273 | } | |
1274 | ||
06c3fd6a | 1275 | static int __exit macb_remove(struct platform_device *pdev) |
89e5785f HS |
1276 | { |
1277 | struct net_device *dev; | |
1278 | struct macb *bp; | |
1279 | ||
1280 | dev = platform_get_drvdata(pdev); | |
1281 | ||
1282 | if (dev) { | |
1283 | bp = netdev_priv(dev); | |
84b7901f AN |
1284 | if (bp->phy_dev) |
1285 | phy_disconnect(bp->phy_dev); | |
298cf9be LB |
1286 | mdiobus_unregister(bp->mii_bus); |
1287 | kfree(bp->mii_bus->irq); | |
1288 | mdiobus_free(bp->mii_bus); | |
89e5785f HS |
1289 | unregister_netdev(dev); |
1290 | free_irq(dev->irq, dev); | |
1291 | iounmap(bp->regs); | |
0cc8674f | 1292 | #ifndef CONFIG_ARCH_AT91 |
89e5785f | 1293 | clk_disable(bp->hclk); |
89e5785f | 1294 | clk_put(bp->hclk); |
0cc8674f AV |
1295 | #endif |
1296 | clk_disable(bp->pclk); | |
89e5785f HS |
1297 | clk_put(bp->pclk); |
1298 | free_netdev(dev); | |
1299 | platform_set_drvdata(pdev, NULL); | |
1300 | } | |
1301 | ||
1302 | return 0; | |
1303 | } | |
1304 | ||
c1f598fd HS |
1305 | #ifdef CONFIG_PM |
1306 | static int macb_suspend(struct platform_device *pdev, pm_message_t state) | |
1307 | { | |
1308 | struct net_device *netdev = platform_get_drvdata(pdev); | |
1309 | struct macb *bp = netdev_priv(netdev); | |
1310 | ||
1311 | netif_device_detach(netdev); | |
1312 | ||
1313 | #ifndef CONFIG_ARCH_AT91 | |
1314 | clk_disable(bp->hclk); | |
1315 | #endif | |
1316 | clk_disable(bp->pclk); | |
1317 | ||
1318 | return 0; | |
1319 | } | |
1320 | ||
1321 | static int macb_resume(struct platform_device *pdev) | |
1322 | { | |
1323 | struct net_device *netdev = platform_get_drvdata(pdev); | |
1324 | struct macb *bp = netdev_priv(netdev); | |
1325 | ||
1326 | clk_enable(bp->pclk); | |
1327 | #ifndef CONFIG_ARCH_AT91 | |
1328 | clk_enable(bp->hclk); | |
1329 | #endif | |
1330 | ||
1331 | netif_device_attach(netdev); | |
1332 | ||
1333 | return 0; | |
1334 | } | |
1335 | #else | |
1336 | #define macb_suspend NULL | |
1337 | #define macb_resume NULL | |
1338 | #endif | |
1339 | ||
89e5785f | 1340 | static struct platform_driver macb_driver = { |
06c3fd6a | 1341 | .remove = __exit_p(macb_remove), |
c1f598fd HS |
1342 | .suspend = macb_suspend, |
1343 | .resume = macb_resume, | |
89e5785f HS |
1344 | .driver = { |
1345 | .name = "macb", | |
72abb461 | 1346 | .owner = THIS_MODULE, |
89e5785f HS |
1347 | }, |
1348 | }; | |
1349 | ||
1350 | static int __init macb_init(void) | |
1351 | { | |
06c3fd6a | 1352 | return platform_driver_probe(&macb_driver, macb_probe); |
89e5785f HS |
1353 | } |
1354 | ||
1355 | static void __exit macb_exit(void) | |
1356 | { | |
1357 | platform_driver_unregister(&macb_driver); | |
1358 | } | |
1359 | ||
1360 | module_init(macb_init); | |
1361 | module_exit(macb_exit); | |
1362 | ||
1363 | MODULE_LICENSE("GPL"); | |
1364 | MODULE_DESCRIPTION("Atmel MACB Ethernet driver"); | |
e05503ef | 1365 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
72abb461 | 1366 | MODULE_ALIAS("platform:macb"); |