Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Driver for the Macintosh 68K onboard MACE controller with PSC | |
3 | * driven DMA. The MACE driver code is derived from mace.c. The | |
4 | * Mac68k theory of operation is courtesy of the MacBSD wizards. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * Copyright (C) 1996 Paul Mackerras. | |
113aa838 | 12 | * Copyright (C) 1998 Alan Cox <alan@lxorguk.ukuu.org.uk> |
1da177e4 LT |
13 | * |
14 | * Modified heavily by Joshua M. Thompson based on Dave Huang's NetBSD driver | |
8b6aaab8 FT |
15 | * |
16 | * Copyright (C) 2007 Finn Thain | |
17 | * | |
18 | * Converted to DMA API, converted to unified driver model, | |
19 | * sync'd some routines with mace.c and fixed various bugs. | |
1da177e4 LT |
20 | */ |
21 | ||
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/netdevice.h> | |
26 | #include <linux/etherdevice.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/string.h> | |
29 | #include <linux/crc32.h> | |
bc63eb9c | 30 | #include <linux/bitrev.h> |
8b6aaab8 FT |
31 | #include <linux/dma-mapping.h> |
32 | #include <linux/platform_device.h> | |
1da177e4 | 33 | #include <asm/io.h> |
1da177e4 LT |
34 | #include <asm/irq.h> |
35 | #include <asm/macintosh.h> | |
36 | #include <asm/macints.h> | |
37 | #include <asm/mac_psc.h> | |
38 | #include <asm/page.h> | |
39 | #include "mace.h" | |
40 | ||
8b6aaab8 | 41 | static char mac_mace_string[] = "macmace"; |
8b6aaab8 FT |
42 | |
43 | #define N_TX_BUFF_ORDER 0 | |
44 | #define N_TX_RING (1 << N_TX_BUFF_ORDER) | |
45 | #define N_RX_BUFF_ORDER 3 | |
46 | #define N_RX_RING (1 << N_RX_BUFF_ORDER) | |
47 | ||
1da177e4 LT |
48 | #define TX_TIMEOUT HZ |
49 | ||
8b6aaab8 FT |
50 | #define MACE_BUFF_SIZE 0x800 |
51 | ||
52 | /* Chip rev needs workaround on HW & multicast addr change */ | |
53 | #define BROKEN_ADDRCHG_REV 0x0941 | |
1da177e4 LT |
54 | |
55 | /* The MACE is simply wired down on a Mac68K box */ | |
56 | ||
57 | #define MACE_BASE (void *)(0x50F1C000) | |
58 | #define MACE_PROM (void *)(0x50F08001) | |
59 | ||
60 | struct mace_data { | |
61 | volatile struct mace *mace; | |
8b6aaab8 FT |
62 | unsigned char *tx_ring; |
63 | dma_addr_t tx_ring_phys; | |
64 | unsigned char *rx_ring; | |
65 | dma_addr_t rx_ring_phys; | |
1da177e4 | 66 | int dma_intr; |
1da177e4 LT |
67 | int rx_slot, rx_tail; |
68 | int tx_slot, tx_sloti, tx_count; | |
8b6aaab8 FT |
69 | int chipid; |
70 | struct device *device; | |
1da177e4 LT |
71 | }; |
72 | ||
73 | struct mace_frame { | |
8b6aaab8 FT |
74 | u8 rcvcnt; |
75 | u8 pad1; | |
76 | u8 rcvsts; | |
77 | u8 pad2; | |
78 | u8 rntpc; | |
79 | u8 pad3; | |
80 | u8 rcvcc; | |
81 | u8 pad4; | |
82 | u32 pad5; | |
83 | u32 pad6; | |
6aa20a22 | 84 | u8 data[1]; |
1da177e4 LT |
85 | /* And frame continues.. */ |
86 | }; | |
87 | ||
88 | #define PRIV_BYTES sizeof(struct mace_data) | |
89 | ||
1da177e4 LT |
90 | static int mace_open(struct net_device *dev); |
91 | static int mace_close(struct net_device *dev); | |
92 | static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev); | |
1da177e4 LT |
93 | static void mace_set_multicast(struct net_device *dev); |
94 | static int mace_set_address(struct net_device *dev, void *addr); | |
8b6aaab8 | 95 | static void mace_reset(struct net_device *dev); |
7d12e780 DH |
96 | static irqreturn_t mace_interrupt(int irq, void *dev_id); |
97 | static irqreturn_t mace_dma_intr(int irq, void *dev_id); | |
1da177e4 | 98 | static void mace_tx_timeout(struct net_device *dev); |
8b6aaab8 | 99 | static void __mace_set_address(struct net_device *dev, void *addr); |
1da177e4 | 100 | |
1da177e4 LT |
101 | /* |
102 | * Load a receive DMA channel with a base address and ring length | |
103 | */ | |
104 | ||
105 | static void mace_load_rxdma_base(struct net_device *dev, int set) | |
106 | { | |
8b6aaab8 | 107 | struct mace_data *mp = netdev_priv(dev); |
1da177e4 LT |
108 | |
109 | psc_write_word(PSC_ENETRD_CMD + set, 0x0100); | |
110 | psc_write_long(PSC_ENETRD_ADDR + set, (u32) mp->rx_ring_phys); | |
111 | psc_write_long(PSC_ENETRD_LEN + set, N_RX_RING); | |
112 | psc_write_word(PSC_ENETRD_CMD + set, 0x9800); | |
113 | mp->rx_tail = 0; | |
114 | } | |
115 | ||
116 | /* | |
117 | * Reset the receive DMA subsystem | |
118 | */ | |
119 | ||
120 | static void mace_rxdma_reset(struct net_device *dev) | |
121 | { | |
8b6aaab8 | 122 | struct mace_data *mp = netdev_priv(dev); |
1da177e4 LT |
123 | volatile struct mace *mace = mp->mace; |
124 | u8 maccc = mace->maccc; | |
6aa20a22 | 125 | |
1da177e4 | 126 | mace->maccc = maccc & ~ENRCV; |
6aa20a22 | 127 | |
1da177e4 LT |
128 | psc_write_word(PSC_ENETRD_CTL, 0x8800); |
129 | mace_load_rxdma_base(dev, 0x00); | |
130 | psc_write_word(PSC_ENETRD_CTL, 0x0400); | |
6aa20a22 | 131 | |
1da177e4 LT |
132 | psc_write_word(PSC_ENETRD_CTL, 0x8800); |
133 | mace_load_rxdma_base(dev, 0x10); | |
134 | psc_write_word(PSC_ENETRD_CTL, 0x0400); | |
6aa20a22 | 135 | |
1da177e4 LT |
136 | mace->maccc = maccc; |
137 | mp->rx_slot = 0; | |
138 | ||
139 | psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x9800); | |
140 | psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x9800); | |
141 | } | |
142 | ||
143 | /* | |
144 | * Reset the transmit DMA subsystem | |
145 | */ | |
6aa20a22 | 146 | |
1da177e4 LT |
147 | static void mace_txdma_reset(struct net_device *dev) |
148 | { | |
8b6aaab8 | 149 | struct mace_data *mp = netdev_priv(dev); |
1da177e4 LT |
150 | volatile struct mace *mace = mp->mace; |
151 | u8 maccc; | |
152 | ||
153 | psc_write_word(PSC_ENETWR_CTL, 0x8800); | |
154 | ||
155 | maccc = mace->maccc; | |
156 | mace->maccc = maccc & ~ENXMT; | |
157 | ||
158 | mp->tx_slot = mp->tx_sloti = 0; | |
159 | mp->tx_count = N_TX_RING; | |
160 | ||
161 | psc_write_word(PSC_ENETWR_CTL, 0x0400); | |
162 | mace->maccc = maccc; | |
163 | } | |
164 | ||
165 | /* | |
166 | * Disable DMA | |
167 | */ | |
6aa20a22 | 168 | |
1da177e4 LT |
169 | static void mace_dma_off(struct net_device *dev) |
170 | { | |
171 | psc_write_word(PSC_ENETRD_CTL, 0x8800); | |
172 | psc_write_word(PSC_ENETRD_CTL, 0x1000); | |
173 | psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x1100); | |
174 | psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x1100); | |
175 | ||
176 | psc_write_word(PSC_ENETWR_CTL, 0x8800); | |
177 | psc_write_word(PSC_ENETWR_CTL, 0x1000); | |
178 | psc_write_word(PSC_ENETWR_CMD + PSC_SET0, 0x1100); | |
179 | psc_write_word(PSC_ENETWR_CMD + PSC_SET1, 0x1100); | |
180 | } | |
181 | ||
0d3936a8 AB |
182 | static const struct net_device_ops mace_netdev_ops = { |
183 | .ndo_open = mace_open, | |
184 | .ndo_stop = mace_close, | |
185 | .ndo_start_xmit = mace_xmit_start, | |
186 | .ndo_tx_timeout = mace_tx_timeout, | |
187 | .ndo_set_multicast_list = mace_set_multicast, | |
188 | .ndo_set_mac_address = mace_set_address, | |
189 | .ndo_change_mtu = eth_change_mtu, | |
190 | .ndo_validate_addr = eth_validate_addr, | |
191 | }; | |
192 | ||
1da177e4 LT |
193 | /* |
194 | * Not really much of a probe. The hardware table tells us if this | |
195 | * model of Macintrash has a MACE (AV macintoshes) | |
196 | */ | |
6aa20a22 | 197 | |
8b6aaab8 | 198 | static int __devinit mace_probe(struct platform_device *pdev) |
1da177e4 LT |
199 | { |
200 | int j; | |
201 | struct mace_data *mp; | |
202 | unsigned char *addr; | |
203 | struct net_device *dev; | |
204 | unsigned char checksum = 0; | |
205 | static int found = 0; | |
206 | int err; | |
6aa20a22 | 207 | |
1da177e4 | 208 | if (found || macintosh_config->ether_type != MAC_ETHER_MACE) |
8b6aaab8 | 209 | return -ENODEV; |
1da177e4 LT |
210 | |
211 | found = 1; /* prevent 'finding' one on every device probe */ | |
212 | ||
213 | dev = alloc_etherdev(PRIV_BYTES); | |
214 | if (!dev) | |
8b6aaab8 | 215 | return -ENOMEM; |
1da177e4 | 216 | |
8b6aaab8 FT |
217 | mp = netdev_priv(dev); |
218 | ||
219 | mp->device = &pdev->dev; | |
220 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1da177e4 | 221 | |
1da177e4 LT |
222 | dev->base_addr = (u32)MACE_BASE; |
223 | mp->mace = (volatile struct mace *) MACE_BASE; | |
6aa20a22 | 224 | |
1da177e4 LT |
225 | dev->irq = IRQ_MAC_MACE; |
226 | mp->dma_intr = IRQ_MAC_MACE_DMA; | |
227 | ||
8b6aaab8 FT |
228 | mp->chipid = mp->mace->chipid_hi << 8 | mp->mace->chipid_lo; |
229 | ||
1da177e4 LT |
230 | /* |
231 | * The PROM contains 8 bytes which total 0xFF when XOR'd | |
232 | * together. Due to the usual peculiar apple brain damage | |
233 | * the bytes are spaced out in a strange boundary and the | |
234 | * bits are reversed. | |
235 | */ | |
236 | ||
237 | addr = (void *)MACE_PROM; | |
6aa20a22 | 238 | |
1da177e4 | 239 | for (j = 0; j < 6; ++j) { |
bc63eb9c | 240 | u8 v = bitrev8(addr[j<<4]); |
1da177e4 LT |
241 | checksum ^= v; |
242 | dev->dev_addr[j] = v; | |
243 | } | |
244 | for (; j < 8; ++j) { | |
bc63eb9c | 245 | checksum ^= bitrev8(addr[j<<4]); |
1da177e4 | 246 | } |
6aa20a22 | 247 | |
1da177e4 LT |
248 | if (checksum != 0xFF) { |
249 | free_netdev(dev); | |
8b6aaab8 | 250 | return -ENODEV; |
1da177e4 LT |
251 | } |
252 | ||
0d3936a8 | 253 | dev->netdev_ops = &mace_netdev_ops; |
1da177e4 | 254 | dev->watchdog_timeo = TX_TIMEOUT; |
1da177e4 | 255 | |
e174961c JB |
256 | printk(KERN_INFO "%s: 68K MACE, hardware address %pM\n", |
257 | dev->name, dev->dev_addr); | |
1da177e4 LT |
258 | |
259 | err = register_netdev(dev); | |
260 | if (!err) | |
8b6aaab8 | 261 | return 0; |
1da177e4 LT |
262 | |
263 | free_netdev(dev); | |
8b6aaab8 FT |
264 | return err; |
265 | } | |
266 | ||
267 | /* | |
268 | * Reset the chip. | |
269 | */ | |
270 | ||
271 | static void mace_reset(struct net_device *dev) | |
272 | { | |
273 | struct mace_data *mp = netdev_priv(dev); | |
274 | volatile struct mace *mb = mp->mace; | |
275 | int i; | |
276 | ||
277 | /* soft-reset the chip */ | |
278 | i = 200; | |
279 | while (--i) { | |
280 | mb->biucc = SWRST; | |
281 | if (mb->biucc & SWRST) { | |
282 | udelay(10); | |
283 | continue; | |
284 | } | |
285 | break; | |
286 | } | |
287 | if (!i) { | |
288 | printk(KERN_ERR "macmace: cannot reset chip!\n"); | |
289 | return; | |
290 | } | |
291 | ||
292 | mb->maccc = 0; /* turn off tx, rx */ | |
293 | mb->imr = 0xFF; /* disable all intrs for now */ | |
294 | i = mb->ir; | |
295 | ||
296 | mb->biucc = XMTSP_64; | |
297 | mb->utr = RTRD; | |
298 | mb->fifocc = XMTFW_8 | RCVFW_64 | XMTFWU | RCVFWU; | |
299 | ||
300 | mb->xmtfc = AUTO_PAD_XMIT; /* auto-pad short frames */ | |
301 | mb->rcvfc = 0; | |
302 | ||
303 | /* load up the hardware address */ | |
304 | __mace_set_address(dev, dev->dev_addr); | |
305 | ||
306 | /* clear the multicast filter */ | |
307 | if (mp->chipid == BROKEN_ADDRCHG_REV) | |
308 | mb->iac = LOGADDR; | |
309 | else { | |
310 | mb->iac = ADDRCHG | LOGADDR; | |
311 | while ((mb->iac & ADDRCHG) != 0) | |
312 | ; | |
313 | } | |
314 | for (i = 0; i < 8; ++i) | |
315 | mb->ladrf = 0; | |
316 | ||
317 | /* done changing address */ | |
318 | if (mp->chipid != BROKEN_ADDRCHG_REV) | |
319 | mb->iac = 0; | |
320 | ||
321 | mb->plscc = PORTSEL_AUI; | |
1da177e4 LT |
322 | } |
323 | ||
324 | /* | |
325 | * Load the address on a mace controller. | |
326 | */ | |
327 | ||
8b6aaab8 | 328 | static void __mace_set_address(struct net_device *dev, void *addr) |
1da177e4 | 329 | { |
8b6aaab8 | 330 | struct mace_data *mp = netdev_priv(dev); |
1da177e4 | 331 | volatile struct mace *mb = mp->mace; |
8b6aaab8 | 332 | unsigned char *p = addr; |
1da177e4 | 333 | int i; |
8b6aaab8 FT |
334 | |
335 | /* load up the hardware address */ | |
336 | if (mp->chipid == BROKEN_ADDRCHG_REV) | |
337 | mb->iac = PHYADDR; | |
338 | else { | |
339 | mb->iac = ADDRCHG | PHYADDR; | |
340 | while ((mb->iac & ADDRCHG) != 0) | |
341 | ; | |
342 | } | |
343 | for (i = 0; i < 6; ++i) | |
344 | mb->padr = dev->dev_addr[i] = p[i]; | |
345 | if (mp->chipid != BROKEN_ADDRCHG_REV) | |
346 | mb->iac = 0; | |
347 | } | |
348 | ||
349 | static int mace_set_address(struct net_device *dev, void *addr) | |
350 | { | |
351 | struct mace_data *mp = netdev_priv(dev); | |
352 | volatile struct mace *mb = mp->mace; | |
1da177e4 LT |
353 | unsigned long flags; |
354 | u8 maccc; | |
355 | ||
356 | local_irq_save(flags); | |
357 | ||
358 | maccc = mb->maccc; | |
359 | ||
8b6aaab8 | 360 | __mace_set_address(dev, addr); |
1da177e4 LT |
361 | |
362 | mb->maccc = maccc; | |
8b6aaab8 | 363 | |
1da177e4 LT |
364 | local_irq_restore(flags); |
365 | ||
366 | return 0; | |
367 | } | |
368 | ||
369 | /* | |
370 | * Open the Macintosh MACE. Most of this is playing with the DMA | |
371 | * engine. The ethernet chip is quite friendly. | |
372 | */ | |
6aa20a22 | 373 | |
1da177e4 LT |
374 | static int mace_open(struct net_device *dev) |
375 | { | |
8b6aaab8 | 376 | struct mace_data *mp = netdev_priv(dev); |
1da177e4 | 377 | volatile struct mace *mb = mp->mace; |
1da177e4 | 378 | |
8b6aaab8 FT |
379 | /* reset the chip */ |
380 | mace_reset(dev); | |
1da177e4 LT |
381 | |
382 | if (request_irq(dev->irq, mace_interrupt, 0, dev->name, dev)) { | |
383 | printk(KERN_ERR "%s: can't get irq %d\n", dev->name, dev->irq); | |
384 | return -EAGAIN; | |
385 | } | |
386 | if (request_irq(mp->dma_intr, mace_dma_intr, 0, dev->name, dev)) { | |
387 | printk(KERN_ERR "%s: can't get irq %d\n", dev->name, mp->dma_intr); | |
388 | free_irq(dev->irq, dev); | |
389 | return -EAGAIN; | |
390 | } | |
391 | ||
392 | /* Allocate the DMA ring buffers */ | |
393 | ||
8b6aaab8 FT |
394 | mp->tx_ring = dma_alloc_coherent(mp->device, |
395 | N_TX_RING * MACE_BUFF_SIZE, | |
396 | &mp->tx_ring_phys, GFP_KERNEL); | |
397 | if (mp->tx_ring == NULL) { | |
398 | printk(KERN_ERR "%s: unable to allocate DMA tx buffers\n", dev->name); | |
399 | goto out1; | |
1da177e4 LT |
400 | } |
401 | ||
8b6aaab8 FT |
402 | mp->rx_ring = dma_alloc_coherent(mp->device, |
403 | N_RX_RING * MACE_BUFF_SIZE, | |
404 | &mp->rx_ring_phys, GFP_KERNEL); | |
405 | if (mp->rx_ring == NULL) { | |
406 | printk(KERN_ERR "%s: unable to allocate DMA rx buffers\n", dev->name); | |
407 | goto out2; | |
408 | } | |
1da177e4 LT |
409 | |
410 | mace_dma_off(dev); | |
411 | ||
412 | /* Not sure what these do */ | |
413 | ||
414 | psc_write_word(PSC_ENETWR_CTL, 0x9000); | |
415 | psc_write_word(PSC_ENETRD_CTL, 0x9000); | |
416 | psc_write_word(PSC_ENETWR_CTL, 0x0400); | |
417 | psc_write_word(PSC_ENETRD_CTL, 0x0400); | |
418 | ||
1da177e4 LT |
419 | mace_rxdma_reset(dev); |
420 | mace_txdma_reset(dev); | |
6aa20a22 | 421 | |
8b6aaab8 FT |
422 | /* turn it on! */ |
423 | mb->maccc = ENXMT | ENRCV; | |
424 | /* enable all interrupts except receive interrupts */ | |
425 | mb->imr = RCVINT; | |
1da177e4 | 426 | return 0; |
8b6aaab8 FT |
427 | |
428 | out2: | |
429 | dma_free_coherent(mp->device, N_TX_RING * MACE_BUFF_SIZE, | |
430 | mp->tx_ring, mp->tx_ring_phys); | |
431 | out1: | |
432 | free_irq(dev->irq, dev); | |
433 | free_irq(mp->dma_intr, dev); | |
434 | return -ENOMEM; | |
1da177e4 LT |
435 | } |
436 | ||
437 | /* | |
438 | * Shut down the mace and its interrupt channel | |
439 | */ | |
6aa20a22 | 440 | |
1da177e4 LT |
441 | static int mace_close(struct net_device *dev) |
442 | { | |
8b6aaab8 | 443 | struct mace_data *mp = netdev_priv(dev); |
1da177e4 LT |
444 | volatile struct mace *mb = mp->mace; |
445 | ||
446 | mb->maccc = 0; /* disable rx and tx */ | |
447 | mb->imr = 0xFF; /* disable all irqs */ | |
448 | mace_dma_off(dev); /* disable rx and tx dma */ | |
449 | ||
1da177e4 LT |
450 | return 0; |
451 | } | |
452 | ||
453 | /* | |
454 | * Transmit a frame | |
455 | */ | |
6aa20a22 | 456 | |
1da177e4 LT |
457 | static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev) |
458 | { | |
8b6aaab8 FT |
459 | struct mace_data *mp = netdev_priv(dev); |
460 | unsigned long flags; | |
1da177e4 | 461 | |
8b6aaab8 | 462 | /* Stop the queue since there's only the one buffer */ |
1da177e4 | 463 | |
8b6aaab8 FT |
464 | local_irq_save(flags); |
465 | netif_stop_queue(dev); | |
1da177e4 | 466 | if (!mp->tx_count) { |
8b6aaab8 FT |
467 | printk(KERN_ERR "macmace: tx queue running but no free buffers.\n"); |
468 | local_irq_restore(flags); | |
469 | return NETDEV_TX_BUSY; | |
1da177e4 LT |
470 | } |
471 | mp->tx_count--; | |
8b6aaab8 | 472 | local_irq_restore(flags); |
6aa20a22 | 473 | |
09f75cd7 JG |
474 | dev->stats.tx_packets++; |
475 | dev->stats.tx_bytes += skb->len; | |
1da177e4 LT |
476 | |
477 | /* We need to copy into our xmit buffer to take care of alignment and caching issues */ | |
d626f62b | 478 | skb_copy_from_linear_data(skb, mp->tx_ring, skb->len); |
1da177e4 LT |
479 | |
480 | /* load the Tx DMA and fire it off */ | |
481 | ||
482 | psc_write_long(PSC_ENETWR_ADDR + mp->tx_slot, (u32) mp->tx_ring_phys); | |
483 | psc_write_long(PSC_ENETWR_LEN + mp->tx_slot, skb->len); | |
484 | psc_write_word(PSC_ENETWR_CMD + mp->tx_slot, 0x9800); | |
485 | ||
486 | mp->tx_slot ^= 0x10; | |
487 | ||
488 | dev_kfree_skb(skb); | |
489 | ||
8b6aaab8 FT |
490 | dev->trans_start = jiffies; |
491 | return NETDEV_TX_OK; | |
1da177e4 LT |
492 | } |
493 | ||
1da177e4 LT |
494 | static void mace_set_multicast(struct net_device *dev) |
495 | { | |
8b6aaab8 | 496 | struct mace_data *mp = netdev_priv(dev); |
1da177e4 | 497 | volatile struct mace *mb = mp->mace; |
f9dcbcc9 | 498 | int i; |
1da177e4 LT |
499 | u32 crc; |
500 | u8 maccc; | |
8b6aaab8 | 501 | unsigned long flags; |
1da177e4 | 502 | |
8b6aaab8 | 503 | local_irq_save(flags); |
1da177e4 LT |
504 | maccc = mb->maccc; |
505 | mb->maccc &= ~PROM; | |
506 | ||
507 | if (dev->flags & IFF_PROMISC) { | |
508 | mb->maccc |= PROM; | |
509 | } else { | |
510 | unsigned char multicast_filter[8]; | |
f9dcbcc9 | 511 | struct dev_mc_list *dmi; |
1da177e4 LT |
512 | |
513 | if (dev->flags & IFF_ALLMULTI) { | |
514 | for (i = 0; i < 8; i++) { | |
515 | multicast_filter[i] = 0xFF; | |
516 | } | |
517 | } else { | |
518 | for (i = 0; i < 8; i++) | |
519 | multicast_filter[i] = 0; | |
f9dcbcc9 | 520 | netdev_for_each_mc_addr(dmi, dev) { |
1da177e4 | 521 | crc = ether_crc_le(6, dmi->dmi_addr); |
f9dcbcc9 JP |
522 | /* bit number in multicast_filter */ |
523 | i = crc >> 26; | |
524 | multicast_filter[i >> 3] |= 1 << (i & 7); | |
1da177e4 LT |
525 | } |
526 | } | |
527 | ||
8b6aaab8 FT |
528 | if (mp->chipid == BROKEN_ADDRCHG_REV) |
529 | mb->iac = LOGADDR; | |
530 | else { | |
531 | mb->iac = ADDRCHG | LOGADDR; | |
532 | while ((mb->iac & ADDRCHG) != 0) | |
533 | ; | |
1da177e4 | 534 | } |
8b6aaab8 FT |
535 | for (i = 0; i < 8; ++i) |
536 | mb->ladrf = multicast_filter[i]; | |
537 | if (mp->chipid != BROKEN_ADDRCHG_REV) | |
538 | mb->iac = 0; | |
1da177e4 LT |
539 | } |
540 | ||
541 | mb->maccc = maccc; | |
8b6aaab8 | 542 | local_irq_restore(flags); |
1da177e4 LT |
543 | } |
544 | ||
3649ba00 | 545 | static void mace_handle_misc_intrs(struct net_device *dev, int intr) |
1da177e4 | 546 | { |
3649ba00 | 547 | struct mace_data *mp = netdev_priv(dev); |
1da177e4 LT |
548 | volatile struct mace *mb = mp->mace; |
549 | static int mace_babbles, mace_jabbers; | |
550 | ||
8b6aaab8 | 551 | if (intr & MPCO) |
09f75cd7 JG |
552 | dev->stats.rx_missed_errors += 256; |
553 | dev->stats.rx_missed_errors += mb->mpc; /* reading clears it */ | |
8b6aaab8 | 554 | if (intr & RNTPCO) |
09f75cd7 JG |
555 | dev->stats.rx_length_errors += 256; |
556 | dev->stats.rx_length_errors += mb->rntpc; /* reading clears it */ | |
8b6aaab8 | 557 | if (intr & CERR) |
09f75cd7 | 558 | ++dev->stats.tx_heartbeat_errors; |
8b6aaab8 FT |
559 | if (intr & BABBLE) |
560 | if (mace_babbles++ < 4) | |
561 | printk(KERN_DEBUG "macmace: babbling transmitter\n"); | |
562 | if (intr & JABBER) | |
563 | if (mace_jabbers++ < 4) | |
564 | printk(KERN_DEBUG "macmace: jabbering transceiver\n"); | |
1da177e4 LT |
565 | } |
566 | ||
8b6aaab8 | 567 | static irqreturn_t mace_interrupt(int irq, void *dev_id) |
1da177e4 | 568 | { |
8b6aaab8 FT |
569 | struct net_device *dev = (struct net_device *) dev_id; |
570 | struct mace_data *mp = netdev_priv(dev); | |
1da177e4 | 571 | volatile struct mace *mb = mp->mace; |
8b6aaab8 | 572 | int intr, fs; |
099575b6 | 573 | unsigned long flags; |
6aa20a22 | 574 | |
8b6aaab8 FT |
575 | /* don't want the dma interrupt handler to fire */ |
576 | local_irq_save(flags); | |
6aa20a22 | 577 | |
8b6aaab8 | 578 | intr = mb->ir; /* read interrupt register */ |
3649ba00 | 579 | mace_handle_misc_intrs(dev, intr); |
8b6aaab8 FT |
580 | |
581 | if (intr & XMTINT) { | |
582 | fs = mb->xmtfs; | |
583 | if ((fs & XMTSV) == 0) { | |
584 | printk(KERN_ERR "macmace: xmtfs not valid! (fs=%x)\n", fs); | |
585 | mace_reset(dev); | |
586 | /* | |
587 | * XXX mace likes to hang the machine after a xmtfs error. | |
588 | * This is hard to reproduce, reseting *may* help | |
589 | */ | |
1da177e4 | 590 | } |
8b6aaab8 FT |
591 | /* dma should have finished */ |
592 | if (!mp->tx_count) { | |
593 | printk(KERN_DEBUG "macmace: tx ring ran out? (fs=%x)\n", fs); | |
594 | } | |
595 | /* Update stats */ | |
596 | if (fs & (UFLO|LCOL|LCAR|RTRY)) { | |
09f75cd7 | 597 | ++dev->stats.tx_errors; |
8b6aaab8 | 598 | if (fs & LCAR) |
09f75cd7 | 599 | ++dev->stats.tx_carrier_errors; |
8b6aaab8 | 600 | else if (fs & (UFLO|LCOL|RTRY)) { |
09f75cd7 | 601 | ++dev->stats.tx_aborted_errors; |
8b6aaab8 FT |
602 | if (mb->xmtfs & UFLO) { |
603 | printk(KERN_ERR "%s: DMA underrun.\n", dev->name); | |
09f75cd7 | 604 | dev->stats.tx_fifo_errors++; |
8b6aaab8 FT |
605 | mace_txdma_reset(dev); |
606 | } | |
607 | } | |
1da177e4 | 608 | } |
6aa20a22 | 609 | } |
1da177e4 | 610 | |
8b6aaab8 FT |
611 | if (mp->tx_count) |
612 | netif_wake_queue(dev); | |
6aa20a22 | 613 | |
8b6aaab8 | 614 | local_irq_restore(flags); |
1da177e4 | 615 | |
8b6aaab8 FT |
616 | return IRQ_HANDLED; |
617 | } | |
6aa20a22 | 618 | |
8b6aaab8 | 619 | static void mace_tx_timeout(struct net_device *dev) |
1da177e4 | 620 | { |
8b6aaab8 | 621 | struct mace_data *mp = netdev_priv(dev); |
1da177e4 | 622 | volatile struct mace *mb = mp->mace; |
8b6aaab8 | 623 | unsigned long flags; |
6aa20a22 | 624 | |
8b6aaab8 | 625 | local_irq_save(flags); |
6aa20a22 | 626 | |
8b6aaab8 FT |
627 | /* turn off both tx and rx and reset the chip */ |
628 | mb->maccc = 0; | |
629 | printk(KERN_ERR "macmace: transmit timeout - resetting\n"); | |
630 | mace_txdma_reset(dev); | |
631 | mace_reset(dev); | |
1da177e4 | 632 | |
8b6aaab8 FT |
633 | /* restart rx dma */ |
634 | mace_rxdma_reset(dev); | |
635 | ||
636 | mp->tx_count = N_TX_RING; | |
637 | netif_wake_queue(dev); | |
638 | ||
639 | /* turn it on! */ | |
640 | mb->maccc = ENXMT | ENRCV; | |
641 | /* enable all interrupts except receive interrupts */ | |
642 | mb->imr = RCVINT; | |
643 | ||
644 | local_irq_restore(flags); | |
1da177e4 LT |
645 | } |
646 | ||
647 | /* | |
648 | * Handle a newly arrived frame | |
649 | */ | |
6aa20a22 | 650 | |
1da177e4 LT |
651 | static void mace_dma_rx_frame(struct net_device *dev, struct mace_frame *mf) |
652 | { | |
1da177e4 | 653 | struct sk_buff *skb; |
8b6aaab8 | 654 | unsigned int frame_status = mf->rcvsts; |
1da177e4 | 655 | |
8b6aaab8 | 656 | if (frame_status & (RS_OFLO | RS_CLSN | RS_FRAMERR | RS_FCSERR)) { |
09f75cd7 | 657 | dev->stats.rx_errors++; |
8b6aaab8 FT |
658 | if (frame_status & RS_OFLO) { |
659 | printk(KERN_DEBUG "%s: fifo overflow.\n", dev->name); | |
09f75cd7 | 660 | dev->stats.rx_fifo_errors++; |
8b6aaab8 FT |
661 | } |
662 | if (frame_status & RS_CLSN) | |
09f75cd7 | 663 | dev->stats.collisions++; |
8b6aaab8 | 664 | if (frame_status & RS_FRAMERR) |
09f75cd7 | 665 | dev->stats.rx_frame_errors++; |
8b6aaab8 | 666 | if (frame_status & RS_FCSERR) |
09f75cd7 | 667 | dev->stats.rx_crc_errors++; |
8b6aaab8 FT |
668 | } else { |
669 | unsigned int frame_length = mf->rcvcnt + ((frame_status & 0x0F) << 8 ); | |
6aa20a22 | 670 | |
8b6aaab8 FT |
671 | skb = dev_alloc_skb(frame_length + 2); |
672 | if (!skb) { | |
09f75cd7 | 673 | dev->stats.rx_dropped++; |
8b6aaab8 FT |
674 | return; |
675 | } | |
676 | skb_reserve(skb, 2); | |
677 | memcpy(skb_put(skb, frame_length), mf->data, frame_length); | |
678 | ||
679 | skb->protocol = eth_type_trans(skb, dev); | |
680 | netif_rx(skb); | |
09f75cd7 JG |
681 | dev->stats.rx_packets++; |
682 | dev->stats.rx_bytes += frame_length; | |
1da177e4 | 683 | } |
1da177e4 LT |
684 | } |
685 | ||
686 | /* | |
687 | * The PSC has passed us a DMA interrupt event. | |
688 | */ | |
6aa20a22 | 689 | |
7d12e780 | 690 | static irqreturn_t mace_dma_intr(int irq, void *dev_id) |
1da177e4 LT |
691 | { |
692 | struct net_device *dev = (struct net_device *) dev_id; | |
8b6aaab8 | 693 | struct mace_data *mp = netdev_priv(dev); |
1da177e4 LT |
694 | int left, head; |
695 | u16 status; | |
696 | u32 baka; | |
697 | ||
698 | /* Not sure what this does */ | |
699 | ||
700 | while ((baka = psc_read_long(PSC_MYSTERY)) != psc_read_long(PSC_MYSTERY)); | |
701 | if (!(baka & 0x60000000)) return IRQ_NONE; | |
702 | ||
703 | /* | |
704 | * Process the read queue | |
705 | */ | |
6aa20a22 | 706 | |
1da177e4 | 707 | status = psc_read_word(PSC_ENETRD_CTL); |
6aa20a22 | 708 | |
1da177e4 LT |
709 | if (status & 0x2000) { |
710 | mace_rxdma_reset(dev); | |
711 | } else if (status & 0x0100) { | |
712 | psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x1100); | |
713 | ||
714 | left = psc_read_long(PSC_ENETRD_LEN + mp->rx_slot); | |
715 | head = N_RX_RING - left; | |
716 | ||
717 | /* Loop through the ring buffer and process new packages */ | |
718 | ||
719 | while (mp->rx_tail < head) { | |
8b6aaab8 FT |
720 | mace_dma_rx_frame(dev, (struct mace_frame*) (mp->rx_ring |
721 | + (mp->rx_tail * MACE_BUFF_SIZE))); | |
1da177e4 LT |
722 | mp->rx_tail++; |
723 | } | |
6aa20a22 | 724 | |
1da177e4 LT |
725 | /* If we're out of buffers in this ring then switch to */ |
726 | /* the other set, otherwise just reactivate this one. */ | |
727 | ||
728 | if (!left) { | |
729 | mace_load_rxdma_base(dev, mp->rx_slot); | |
730 | mp->rx_slot ^= 0x10; | |
731 | } else { | |
732 | psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x9800); | |
733 | } | |
734 | } | |
6aa20a22 | 735 | |
1da177e4 LT |
736 | /* |
737 | * Process the write queue | |
738 | */ | |
739 | ||
740 | status = psc_read_word(PSC_ENETWR_CTL); | |
741 | ||
742 | if (status & 0x2000) { | |
743 | mace_txdma_reset(dev); | |
744 | } else if (status & 0x0100) { | |
745 | psc_write_word(PSC_ENETWR_CMD + mp->tx_sloti, 0x0100); | |
746 | mp->tx_sloti ^= 0x10; | |
747 | mp->tx_count++; | |
1da177e4 LT |
748 | } |
749 | return IRQ_HANDLED; | |
750 | } | |
751 | ||
752 | MODULE_LICENSE("GPL"); | |
8b6aaab8 | 753 | MODULE_DESCRIPTION("Macintosh MACE ethernet driver"); |
eeb9c182 | 754 | MODULE_ALIAS("platform:macmace"); |
8b6aaab8 FT |
755 | |
756 | static int __devexit mac_mace_device_remove (struct platform_device *pdev) | |
757 | { | |
758 | struct net_device *dev = platform_get_drvdata(pdev); | |
759 | struct mace_data *mp = netdev_priv(dev); | |
760 | ||
761 | unregister_netdev(dev); | |
762 | ||
763 | free_irq(dev->irq, dev); | |
764 | free_irq(IRQ_MAC_MACE_DMA, dev); | |
765 | ||
766 | dma_free_coherent(mp->device, N_RX_RING * MACE_BUFF_SIZE, | |
767 | mp->rx_ring, mp->rx_ring_phys); | |
768 | dma_free_coherent(mp->device, N_TX_RING * MACE_BUFF_SIZE, | |
769 | mp->tx_ring, mp->tx_ring_phys); | |
770 | ||
771 | free_netdev(dev); | |
772 | ||
773 | return 0; | |
774 | } | |
775 | ||
776 | static struct platform_driver mac_mace_driver = { | |
777 | .probe = mace_probe, | |
778 | .remove = __devexit_p(mac_mace_device_remove), | |
779 | .driver = { | |
eeb9c182 FT |
780 | .name = mac_mace_string, |
781 | .owner = THIS_MODULE, | |
8b6aaab8 FT |
782 | }, |
783 | }; | |
784 | ||
785 | static int __init mac_mace_init_module(void) | |
786 | { | |
0f734484 GU |
787 | if (!MACH_IS_MAC) |
788 | return -ENODEV; | |
789 | ||
eeb9c182 | 790 | return platform_driver_register(&mac_mace_driver); |
8b6aaab8 FT |
791 | } |
792 | ||
793 | static void __exit mac_mace_cleanup_module(void) | |
794 | { | |
795 | platform_driver_unregister(&mac_mace_driver); | |
8b6aaab8 FT |
796 | } |
797 | ||
798 | module_init(mac_mace_init_module); | |
799 | module_exit(mac_mace_cleanup_module); |