Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Driver for the Macintosh 68K onboard MACE controller with PSC | |
3 | * driven DMA. The MACE driver code is derived from mace.c. The | |
4 | * Mac68k theory of operation is courtesy of the MacBSD wizards. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * Copyright (C) 1996 Paul Mackerras. | |
12 | * Copyright (C) 1998 Alan Cox <alan@redhat.com> | |
13 | * | |
14 | * Modified heavily by Joshua M. Thompson based on Dave Huang's NetBSD driver | |
15 | */ | |
16 | ||
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/netdevice.h> | |
21 | #include <linux/etherdevice.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/string.h> | |
24 | #include <linux/crc32.h> | |
bc63eb9c | 25 | #include <linux/bitrev.h> |
1da177e4 LT |
26 | #include <asm/io.h> |
27 | #include <asm/pgtable.h> | |
28 | #include <asm/irq.h> | |
29 | #include <asm/macintosh.h> | |
30 | #include <asm/macints.h> | |
31 | #include <asm/mac_psc.h> | |
32 | #include <asm/page.h> | |
33 | #include "mace.h" | |
34 | ||
35 | #define N_TX_RING 1 | |
36 | #define N_RX_RING 8 | |
37 | #define N_RX_PAGES ((N_RX_RING * 0x0800 + PAGE_SIZE - 1) / PAGE_SIZE) | |
38 | #define TX_TIMEOUT HZ | |
39 | ||
40 | /* Bits in transmit DMA status */ | |
41 | #define TX_DMA_ERR 0x80 | |
42 | ||
43 | /* The MACE is simply wired down on a Mac68K box */ | |
44 | ||
45 | #define MACE_BASE (void *)(0x50F1C000) | |
46 | #define MACE_PROM (void *)(0x50F08001) | |
47 | ||
48 | struct mace_data { | |
49 | volatile struct mace *mace; | |
50 | volatile unsigned char *tx_ring; | |
51 | volatile unsigned char *tx_ring_phys; | |
52 | volatile unsigned char *rx_ring; | |
53 | volatile unsigned char *rx_ring_phys; | |
54 | int dma_intr; | |
55 | struct net_device_stats stats; | |
56 | int rx_slot, rx_tail; | |
57 | int tx_slot, tx_sloti, tx_count; | |
58 | }; | |
59 | ||
60 | struct mace_frame { | |
61 | u16 len; | |
62 | u16 status; | |
63 | u16 rntpc; | |
64 | u16 rcvcc; | |
65 | u32 pad1; | |
66 | u32 pad2; | |
6aa20a22 | 67 | u8 data[1]; |
1da177e4 LT |
68 | /* And frame continues.. */ |
69 | }; | |
70 | ||
71 | #define PRIV_BYTES sizeof(struct mace_data) | |
72 | ||
73 | extern void psc_debug_dump(void); | |
74 | ||
75 | static int mace_open(struct net_device *dev); | |
76 | static int mace_close(struct net_device *dev); | |
77 | static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev); | |
78 | static struct net_device_stats *mace_stats(struct net_device *dev); | |
79 | static void mace_set_multicast(struct net_device *dev); | |
80 | static int mace_set_address(struct net_device *dev, void *addr); | |
7d12e780 DH |
81 | static irqreturn_t mace_interrupt(int irq, void *dev_id); |
82 | static irqreturn_t mace_dma_intr(int irq, void *dev_id); | |
1da177e4 LT |
83 | static void mace_tx_timeout(struct net_device *dev); |
84 | ||
1da177e4 LT |
85 | /* |
86 | * Load a receive DMA channel with a base address and ring length | |
87 | */ | |
88 | ||
89 | static void mace_load_rxdma_base(struct net_device *dev, int set) | |
90 | { | |
91 | struct mace_data *mp = (struct mace_data *) dev->priv; | |
92 | ||
93 | psc_write_word(PSC_ENETRD_CMD + set, 0x0100); | |
94 | psc_write_long(PSC_ENETRD_ADDR + set, (u32) mp->rx_ring_phys); | |
95 | psc_write_long(PSC_ENETRD_LEN + set, N_RX_RING); | |
96 | psc_write_word(PSC_ENETRD_CMD + set, 0x9800); | |
97 | mp->rx_tail = 0; | |
98 | } | |
99 | ||
100 | /* | |
101 | * Reset the receive DMA subsystem | |
102 | */ | |
103 | ||
104 | static void mace_rxdma_reset(struct net_device *dev) | |
105 | { | |
106 | struct mace_data *mp = (struct mace_data *) dev->priv; | |
107 | volatile struct mace *mace = mp->mace; | |
108 | u8 maccc = mace->maccc; | |
6aa20a22 | 109 | |
1da177e4 | 110 | mace->maccc = maccc & ~ENRCV; |
6aa20a22 | 111 | |
1da177e4 LT |
112 | psc_write_word(PSC_ENETRD_CTL, 0x8800); |
113 | mace_load_rxdma_base(dev, 0x00); | |
114 | psc_write_word(PSC_ENETRD_CTL, 0x0400); | |
6aa20a22 | 115 | |
1da177e4 LT |
116 | psc_write_word(PSC_ENETRD_CTL, 0x8800); |
117 | mace_load_rxdma_base(dev, 0x10); | |
118 | psc_write_word(PSC_ENETRD_CTL, 0x0400); | |
6aa20a22 | 119 | |
1da177e4 LT |
120 | mace->maccc = maccc; |
121 | mp->rx_slot = 0; | |
122 | ||
123 | psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x9800); | |
124 | psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x9800); | |
125 | } | |
126 | ||
127 | /* | |
128 | * Reset the transmit DMA subsystem | |
129 | */ | |
6aa20a22 | 130 | |
1da177e4 LT |
131 | static void mace_txdma_reset(struct net_device *dev) |
132 | { | |
133 | struct mace_data *mp = (struct mace_data *) dev->priv; | |
134 | volatile struct mace *mace = mp->mace; | |
135 | u8 maccc; | |
136 | ||
137 | psc_write_word(PSC_ENETWR_CTL, 0x8800); | |
138 | ||
139 | maccc = mace->maccc; | |
140 | mace->maccc = maccc & ~ENXMT; | |
141 | ||
142 | mp->tx_slot = mp->tx_sloti = 0; | |
143 | mp->tx_count = N_TX_RING; | |
144 | ||
145 | psc_write_word(PSC_ENETWR_CTL, 0x0400); | |
146 | mace->maccc = maccc; | |
147 | } | |
148 | ||
149 | /* | |
150 | * Disable DMA | |
151 | */ | |
6aa20a22 | 152 | |
1da177e4 LT |
153 | static void mace_dma_off(struct net_device *dev) |
154 | { | |
155 | psc_write_word(PSC_ENETRD_CTL, 0x8800); | |
156 | psc_write_word(PSC_ENETRD_CTL, 0x1000); | |
157 | psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x1100); | |
158 | psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x1100); | |
159 | ||
160 | psc_write_word(PSC_ENETWR_CTL, 0x8800); | |
161 | psc_write_word(PSC_ENETWR_CTL, 0x1000); | |
162 | psc_write_word(PSC_ENETWR_CMD + PSC_SET0, 0x1100); | |
163 | psc_write_word(PSC_ENETWR_CMD + PSC_SET1, 0x1100); | |
164 | } | |
165 | ||
166 | /* | |
167 | * Not really much of a probe. The hardware table tells us if this | |
168 | * model of Macintrash has a MACE (AV macintoshes) | |
169 | */ | |
6aa20a22 | 170 | |
1da177e4 LT |
171 | struct net_device *mace_probe(int unit) |
172 | { | |
173 | int j; | |
174 | struct mace_data *mp; | |
175 | unsigned char *addr; | |
176 | struct net_device *dev; | |
177 | unsigned char checksum = 0; | |
178 | static int found = 0; | |
179 | int err; | |
6aa20a22 | 180 | |
1da177e4 LT |
181 | if (found || macintosh_config->ether_type != MAC_ETHER_MACE) |
182 | return ERR_PTR(-ENODEV); | |
183 | ||
184 | found = 1; /* prevent 'finding' one on every device probe */ | |
185 | ||
186 | dev = alloc_etherdev(PRIV_BYTES); | |
187 | if (!dev) | |
188 | return ERR_PTR(-ENOMEM); | |
189 | ||
190 | if (unit >= 0) | |
191 | sprintf(dev->name, "eth%d", unit); | |
192 | ||
193 | mp = (struct mace_data *) dev->priv; | |
194 | dev->base_addr = (u32)MACE_BASE; | |
195 | mp->mace = (volatile struct mace *) MACE_BASE; | |
6aa20a22 | 196 | |
1da177e4 LT |
197 | dev->irq = IRQ_MAC_MACE; |
198 | mp->dma_intr = IRQ_MAC_MACE_DMA; | |
199 | ||
200 | /* | |
201 | * The PROM contains 8 bytes which total 0xFF when XOR'd | |
202 | * together. Due to the usual peculiar apple brain damage | |
203 | * the bytes are spaced out in a strange boundary and the | |
204 | * bits are reversed. | |
205 | */ | |
206 | ||
207 | addr = (void *)MACE_PROM; | |
6aa20a22 | 208 | |
1da177e4 | 209 | for (j = 0; j < 6; ++j) { |
bc63eb9c | 210 | u8 v = bitrev8(addr[j<<4]); |
1da177e4 LT |
211 | checksum ^= v; |
212 | dev->dev_addr[j] = v; | |
213 | } | |
214 | for (; j < 8; ++j) { | |
bc63eb9c | 215 | checksum ^= bitrev8(addr[j<<4]); |
1da177e4 | 216 | } |
6aa20a22 | 217 | |
1da177e4 LT |
218 | if (checksum != 0xFF) { |
219 | free_netdev(dev); | |
220 | return ERR_PTR(-ENODEV); | |
221 | } | |
222 | ||
223 | memset(&mp->stats, 0, sizeof(mp->stats)); | |
224 | ||
225 | dev->open = mace_open; | |
226 | dev->stop = mace_close; | |
227 | dev->hard_start_xmit = mace_xmit_start; | |
228 | dev->tx_timeout = mace_tx_timeout; | |
229 | dev->watchdog_timeo = TX_TIMEOUT; | |
230 | dev->get_stats = mace_stats; | |
231 | dev->set_multicast_list = mace_set_multicast; | |
232 | dev->set_mac_address = mace_set_address; | |
233 | ||
234 | printk(KERN_INFO "%s: 68K MACE, hardware address %.2X", dev->name, dev->dev_addr[0]); | |
235 | for (j = 1 ; j < 6 ; j++) printk(":%.2X", dev->dev_addr[j]); | |
236 | printk("\n"); | |
237 | ||
238 | err = register_netdev(dev); | |
239 | if (!err) | |
240 | return dev; | |
241 | ||
242 | free_netdev(dev); | |
243 | return ERR_PTR(err); | |
244 | } | |
245 | ||
246 | /* | |
247 | * Load the address on a mace controller. | |
248 | */ | |
249 | ||
250 | static int mace_set_address(struct net_device *dev, void *addr) | |
251 | { | |
252 | unsigned char *p = addr; | |
253 | struct mace_data *mp = (struct mace_data *) dev->priv; | |
254 | volatile struct mace *mb = mp->mace; | |
255 | int i; | |
256 | unsigned long flags; | |
257 | u8 maccc; | |
258 | ||
259 | local_irq_save(flags); | |
260 | ||
261 | maccc = mb->maccc; | |
262 | ||
263 | /* load up the hardware address */ | |
264 | mb->iac = ADDRCHG | PHYADDR; | |
265 | while ((mb->iac & ADDRCHG) != 0); | |
6aa20a22 | 266 | |
1da177e4 LT |
267 | for (i = 0; i < 6; ++i) { |
268 | mb->padr = dev->dev_addr[i] = p[i]; | |
269 | } | |
270 | ||
271 | mb->maccc = maccc; | |
272 | local_irq_restore(flags); | |
273 | ||
274 | return 0; | |
275 | } | |
276 | ||
277 | /* | |
278 | * Open the Macintosh MACE. Most of this is playing with the DMA | |
279 | * engine. The ethernet chip is quite friendly. | |
280 | */ | |
6aa20a22 | 281 | |
1da177e4 LT |
282 | static int mace_open(struct net_device *dev) |
283 | { | |
284 | struct mace_data *mp = (struct mace_data *) dev->priv; | |
285 | volatile struct mace *mb = mp->mace; | |
286 | #if 0 | |
287 | int i; | |
288 | ||
289 | i = 200; | |
290 | while (--i) { | |
291 | mb->biucc = SWRST; | |
292 | if (mb->biucc & SWRST) { | |
293 | udelay(10); | |
294 | continue; | |
295 | } | |
296 | break; | |
297 | } | |
298 | if (!i) { | |
299 | printk(KERN_ERR "%s: software reset failed!!\n", dev->name); | |
300 | return -EAGAIN; | |
301 | } | |
302 | #endif | |
303 | ||
304 | mb->biucc = XMTSP_64; | |
305 | mb->fifocc = XMTFW_16 | RCVFW_64 | XMTFWU | RCVFWU | XMTBRST | RCVBRST; | |
306 | mb->xmtfc = AUTO_PAD_XMIT; | |
307 | mb->plscc = PORTSEL_AUI; | |
308 | /* mb->utr = RTRD; */ | |
309 | ||
310 | if (request_irq(dev->irq, mace_interrupt, 0, dev->name, dev)) { | |
311 | printk(KERN_ERR "%s: can't get irq %d\n", dev->name, dev->irq); | |
312 | return -EAGAIN; | |
313 | } | |
314 | if (request_irq(mp->dma_intr, mace_dma_intr, 0, dev->name, dev)) { | |
315 | printk(KERN_ERR "%s: can't get irq %d\n", dev->name, mp->dma_intr); | |
316 | free_irq(dev->irq, dev); | |
317 | return -EAGAIN; | |
318 | } | |
319 | ||
320 | /* Allocate the DMA ring buffers */ | |
321 | ||
322 | mp->rx_ring = (void *) __get_free_pages(GFP_KERNEL | GFP_DMA, N_RX_PAGES); | |
323 | mp->tx_ring = (void *) __get_free_pages(GFP_KERNEL | GFP_DMA, 0); | |
6aa20a22 | 324 | |
1da177e4 LT |
325 | if (mp->tx_ring==NULL || mp->rx_ring==NULL) { |
326 | if (mp->rx_ring) free_pages((u32) mp->rx_ring, N_RX_PAGES); | |
327 | if (mp->tx_ring) free_pages((u32) mp->tx_ring, 0); | |
328 | free_irq(dev->irq, dev); | |
329 | free_irq(mp->dma_intr, dev); | |
330 | printk(KERN_ERR "%s: unable to allocate DMA buffers\n", dev->name); | |
331 | return -ENOMEM; | |
332 | } | |
333 | ||
334 | mp->rx_ring_phys = (unsigned char *) virt_to_bus((void *)mp->rx_ring); | |
335 | mp->tx_ring_phys = (unsigned char *) virt_to_bus((void *)mp->tx_ring); | |
336 | ||
337 | /* We want the Rx buffer to be uncached and the Tx buffer to be writethrough */ | |
338 | ||
6aa20a22 | 339 | kernel_set_cachemode((void *)mp->rx_ring, N_RX_PAGES * PAGE_SIZE, IOMAP_NOCACHE_NONSER); |
1da177e4 LT |
340 | kernel_set_cachemode((void *)mp->tx_ring, PAGE_SIZE, IOMAP_WRITETHROUGH); |
341 | ||
342 | mace_dma_off(dev); | |
343 | ||
344 | /* Not sure what these do */ | |
345 | ||
346 | psc_write_word(PSC_ENETWR_CTL, 0x9000); | |
347 | psc_write_word(PSC_ENETRD_CTL, 0x9000); | |
348 | psc_write_word(PSC_ENETWR_CTL, 0x0400); | |
349 | psc_write_word(PSC_ENETRD_CTL, 0x0400); | |
350 | ||
351 | #if 0 | |
352 | /* load up the hardware address */ | |
6aa20a22 | 353 | |
1da177e4 | 354 | mb->iac = ADDRCHG | PHYADDR; |
6aa20a22 | 355 | |
1da177e4 | 356 | while ((mb->iac & ADDRCHG) != 0); |
6aa20a22 | 357 | |
1da177e4 LT |
358 | for (i = 0; i < 6; ++i) |
359 | mb->padr = dev->dev_addr[i]; | |
360 | ||
361 | /* clear the multicast filter */ | |
362 | mb->iac = ADDRCHG | LOGADDR; | |
363 | ||
364 | while ((mb->iac & ADDRCHG) != 0); | |
6aa20a22 | 365 | |
1da177e4 LT |
366 | for (i = 0; i < 8; ++i) |
367 | mb->ladrf = 0; | |
368 | ||
369 | mb->plscc = PORTSEL_GPSI + ENPLSIO; | |
370 | ||
371 | mb->maccc = ENXMT | ENRCV; | |
372 | mb->imr = RCVINT; | |
373 | #endif | |
374 | ||
375 | mace_rxdma_reset(dev); | |
376 | mace_txdma_reset(dev); | |
6aa20a22 | 377 | |
1da177e4 LT |
378 | return 0; |
379 | } | |
380 | ||
381 | /* | |
382 | * Shut down the mace and its interrupt channel | |
383 | */ | |
6aa20a22 | 384 | |
1da177e4 LT |
385 | static int mace_close(struct net_device *dev) |
386 | { | |
387 | struct mace_data *mp = (struct mace_data *) dev->priv; | |
388 | volatile struct mace *mb = mp->mace; | |
389 | ||
390 | mb->maccc = 0; /* disable rx and tx */ | |
391 | mb->imr = 0xFF; /* disable all irqs */ | |
392 | mace_dma_off(dev); /* disable rx and tx dma */ | |
393 | ||
394 | free_irq(dev->irq, dev); | |
395 | free_irq(IRQ_MAC_MACE_DMA, dev); | |
396 | ||
397 | free_pages((u32) mp->rx_ring, N_RX_PAGES); | |
398 | free_pages((u32) mp->tx_ring, 0); | |
399 | ||
400 | return 0; | |
401 | } | |
402 | ||
403 | /* | |
404 | * Transmit a frame | |
405 | */ | |
6aa20a22 | 406 | |
1da177e4 LT |
407 | static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev) |
408 | { | |
409 | struct mace_data *mp = (struct mace_data *) dev->priv; | |
410 | ||
411 | /* Stop the queue if the buffer is full */ | |
412 | ||
413 | if (!mp->tx_count) { | |
414 | netif_stop_queue(dev); | |
415 | return 1; | |
416 | } | |
417 | mp->tx_count--; | |
6aa20a22 | 418 | |
1da177e4 LT |
419 | mp->stats.tx_packets++; |
420 | mp->stats.tx_bytes += skb->len; | |
421 | ||
422 | /* We need to copy into our xmit buffer to take care of alignment and caching issues */ | |
423 | ||
424 | memcpy((void *) mp->tx_ring, skb->data, skb->len); | |
425 | ||
426 | /* load the Tx DMA and fire it off */ | |
427 | ||
428 | psc_write_long(PSC_ENETWR_ADDR + mp->tx_slot, (u32) mp->tx_ring_phys); | |
429 | psc_write_long(PSC_ENETWR_LEN + mp->tx_slot, skb->len); | |
430 | psc_write_word(PSC_ENETWR_CMD + mp->tx_slot, 0x9800); | |
431 | ||
432 | mp->tx_slot ^= 0x10; | |
433 | ||
434 | dev_kfree_skb(skb); | |
435 | ||
436 | return 0; | |
437 | } | |
438 | ||
439 | static struct net_device_stats *mace_stats(struct net_device *dev) | |
440 | { | |
441 | struct mace_data *p = (struct mace_data *) dev->priv; | |
442 | return &p->stats; | |
443 | } | |
444 | ||
445 | static void mace_set_multicast(struct net_device *dev) | |
446 | { | |
447 | struct mace_data *mp = (struct mace_data *) dev->priv; | |
448 | volatile struct mace *mb = mp->mace; | |
449 | int i, j; | |
450 | u32 crc; | |
451 | u8 maccc; | |
452 | ||
453 | maccc = mb->maccc; | |
454 | mb->maccc &= ~PROM; | |
455 | ||
456 | if (dev->flags & IFF_PROMISC) { | |
457 | mb->maccc |= PROM; | |
458 | } else { | |
459 | unsigned char multicast_filter[8]; | |
460 | struct dev_mc_list *dmi = dev->mc_list; | |
461 | ||
462 | if (dev->flags & IFF_ALLMULTI) { | |
463 | for (i = 0; i < 8; i++) { | |
464 | multicast_filter[i] = 0xFF; | |
465 | } | |
466 | } else { | |
467 | for (i = 0; i < 8; i++) | |
468 | multicast_filter[i] = 0; | |
469 | for (i = 0; i < dev->mc_count; i++) { | |
470 | crc = ether_crc_le(6, dmi->dmi_addr); | |
471 | j = crc >> 26; /* bit number in multicast_filter */ | |
472 | multicast_filter[j >> 3] |= 1 << (j & 7); | |
473 | dmi = dmi->next; | |
474 | } | |
475 | } | |
476 | ||
477 | mb->iac = ADDRCHG | LOGADDR; | |
478 | while (mb->iac & ADDRCHG); | |
6aa20a22 | 479 | |
1da177e4 LT |
480 | for (i = 0; i < 8; ++i) { |
481 | mb->ladrf = multicast_filter[i]; | |
482 | } | |
483 | } | |
484 | ||
485 | mb->maccc = maccc; | |
486 | } | |
487 | ||
488 | /* | |
6aa20a22 | 489 | * Miscellaneous interrupts are handled here. We may end up |
1da177e4 LT |
490 | * having to bash the chip on the head for bad errors |
491 | */ | |
6aa20a22 | 492 | |
1da177e4 LT |
493 | static void mace_handle_misc_intrs(struct mace_data *mp, int intr) |
494 | { | |
495 | volatile struct mace *mb = mp->mace; | |
496 | static int mace_babbles, mace_jabbers; | |
497 | ||
498 | if (intr & MPCO) { | |
499 | mp->stats.rx_missed_errors += 256; | |
500 | } | |
501 | mp->stats.rx_missed_errors += mb->mpc; /* reading clears it */ | |
502 | ||
503 | if (intr & RNTPCO) { | |
504 | mp->stats.rx_length_errors += 256; | |
505 | } | |
506 | mp->stats.rx_length_errors += mb->rntpc; /* reading clears it */ | |
507 | ||
508 | if (intr & CERR) { | |
509 | ++mp->stats.tx_heartbeat_errors; | |
510 | } | |
511 | if (intr & BABBLE) { | |
512 | if (mace_babbles++ < 4) { | |
513 | printk(KERN_DEBUG "mace: babbling transmitter\n"); | |
514 | } | |
515 | } | |
516 | if (intr & JABBER) { | |
517 | if (mace_jabbers++ < 4) { | |
518 | printk(KERN_DEBUG "mace: jabbering transceiver\n"); | |
519 | } | |
520 | } | |
521 | } | |
522 | ||
523 | /* | |
524 | * A transmit error has occurred. (We kick the transmit side from | |
525 | * the DMA completion) | |
526 | */ | |
6aa20a22 | 527 | |
1da177e4 LT |
528 | static void mace_xmit_error(struct net_device *dev) |
529 | { | |
530 | struct mace_data *mp = (struct mace_data *) dev->priv; | |
531 | volatile struct mace *mb = mp->mace; | |
532 | u8 xmtfs, xmtrc; | |
6aa20a22 | 533 | |
1da177e4 LT |
534 | xmtfs = mb->xmtfs; |
535 | xmtrc = mb->xmtrc; | |
6aa20a22 | 536 | |
1da177e4 LT |
537 | if (xmtfs & XMTSV) { |
538 | if (xmtfs & UFLO) { | |
539 | printk("%s: DMA underrun.\n", dev->name); | |
540 | mp->stats.tx_errors++; | |
541 | mp->stats.tx_fifo_errors++; | |
542 | mace_txdma_reset(dev); | |
543 | } | |
544 | if (xmtfs & RTRY) { | |
545 | mp->stats.collisions++; | |
546 | } | |
6aa20a22 | 547 | } |
1da177e4 LT |
548 | } |
549 | ||
550 | /* | |
551 | * A receive interrupt occurred. | |
552 | */ | |
6aa20a22 | 553 | |
1da177e4 LT |
554 | static void mace_recv_interrupt(struct net_device *dev) |
555 | { | |
556 | /* struct mace_data *mp = (struct mace_data *) dev->priv; */ | |
557 | // volatile struct mace *mb = mp->mace; | |
558 | } | |
559 | ||
560 | /* | |
561 | * Process the chip interrupt | |
562 | */ | |
6aa20a22 | 563 | |
7d12e780 | 564 | static irqreturn_t mace_interrupt(int irq, void *dev_id) |
1da177e4 LT |
565 | { |
566 | struct net_device *dev = (struct net_device *) dev_id; | |
567 | struct mace_data *mp = (struct mace_data *) dev->priv; | |
568 | volatile struct mace *mb = mp->mace; | |
569 | u8 ir; | |
6aa20a22 | 570 | |
1da177e4 LT |
571 | ir = mb->ir; |
572 | mace_handle_misc_intrs(mp, ir); | |
6aa20a22 | 573 | |
1da177e4 LT |
574 | if (ir & XMTINT) { |
575 | mace_xmit_error(dev); | |
576 | } | |
577 | if (ir & RCVINT) { | |
578 | mace_recv_interrupt(dev); | |
579 | } | |
580 | return IRQ_HANDLED; | |
581 | } | |
582 | ||
583 | static void mace_tx_timeout(struct net_device *dev) | |
584 | { | |
585 | /* struct mace_data *mp = (struct mace_data *) dev->priv; */ | |
586 | // volatile struct mace *mb = mp->mace; | |
587 | } | |
588 | ||
589 | /* | |
590 | * Handle a newly arrived frame | |
591 | */ | |
6aa20a22 | 592 | |
1da177e4 LT |
593 | static void mace_dma_rx_frame(struct net_device *dev, struct mace_frame *mf) |
594 | { | |
595 | struct mace_data *mp = (struct mace_data *) dev->priv; | |
596 | struct sk_buff *skb; | |
597 | ||
598 | if (mf->status & RS_OFLO) { | |
599 | printk("%s: fifo overflow.\n", dev->name); | |
600 | mp->stats.rx_errors++; | |
601 | mp->stats.rx_fifo_errors++; | |
602 | } | |
603 | if (mf->status&(RS_CLSN|RS_FRAMERR|RS_FCSERR)) | |
604 | mp->stats.rx_errors++; | |
6aa20a22 | 605 | |
1da177e4 LT |
606 | if (mf->status&RS_CLSN) { |
607 | mp->stats.collisions++; | |
608 | } | |
609 | if (mf->status&RS_FRAMERR) { | |
610 | mp->stats.rx_frame_errors++; | |
611 | } | |
612 | if (mf->status&RS_FCSERR) { | |
613 | mp->stats.rx_crc_errors++; | |
614 | } | |
6aa20a22 | 615 | |
1da177e4 LT |
616 | skb = dev_alloc_skb(mf->len+2); |
617 | if (!skb) { | |
618 | mp->stats.rx_dropped++; | |
619 | return; | |
620 | } | |
621 | skb_reserve(skb,2); | |
622 | memcpy(skb_put(skb, mf->len), mf->data, mf->len); | |
6aa20a22 | 623 | |
1da177e4 LT |
624 | skb->dev = dev; |
625 | skb->protocol = eth_type_trans(skb, dev); | |
626 | netif_rx(skb); | |
627 | dev->last_rx = jiffies; | |
628 | mp->stats.rx_packets++; | |
629 | mp->stats.rx_bytes += mf->len; | |
630 | } | |
631 | ||
632 | /* | |
633 | * The PSC has passed us a DMA interrupt event. | |
634 | */ | |
6aa20a22 | 635 | |
7d12e780 | 636 | static irqreturn_t mace_dma_intr(int irq, void *dev_id) |
1da177e4 LT |
637 | { |
638 | struct net_device *dev = (struct net_device *) dev_id; | |
639 | struct mace_data *mp = (struct mace_data *) dev->priv; | |
640 | int left, head; | |
641 | u16 status; | |
642 | u32 baka; | |
643 | ||
644 | /* Not sure what this does */ | |
645 | ||
646 | while ((baka = psc_read_long(PSC_MYSTERY)) != psc_read_long(PSC_MYSTERY)); | |
647 | if (!(baka & 0x60000000)) return IRQ_NONE; | |
648 | ||
649 | /* | |
650 | * Process the read queue | |
651 | */ | |
6aa20a22 | 652 | |
1da177e4 | 653 | status = psc_read_word(PSC_ENETRD_CTL); |
6aa20a22 | 654 | |
1da177e4 LT |
655 | if (status & 0x2000) { |
656 | mace_rxdma_reset(dev); | |
657 | } else if (status & 0x0100) { | |
658 | psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x1100); | |
659 | ||
660 | left = psc_read_long(PSC_ENETRD_LEN + mp->rx_slot); | |
661 | head = N_RX_RING - left; | |
662 | ||
663 | /* Loop through the ring buffer and process new packages */ | |
664 | ||
665 | while (mp->rx_tail < head) { | |
666 | mace_dma_rx_frame(dev, (struct mace_frame *) (mp->rx_ring + (mp->rx_tail * 0x0800))); | |
667 | mp->rx_tail++; | |
668 | } | |
6aa20a22 | 669 | |
1da177e4 LT |
670 | /* If we're out of buffers in this ring then switch to */ |
671 | /* the other set, otherwise just reactivate this one. */ | |
672 | ||
673 | if (!left) { | |
674 | mace_load_rxdma_base(dev, mp->rx_slot); | |
675 | mp->rx_slot ^= 0x10; | |
676 | } else { | |
677 | psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x9800); | |
678 | } | |
679 | } | |
6aa20a22 | 680 | |
1da177e4 LT |
681 | /* |
682 | * Process the write queue | |
683 | */ | |
684 | ||
685 | status = psc_read_word(PSC_ENETWR_CTL); | |
686 | ||
687 | if (status & 0x2000) { | |
688 | mace_txdma_reset(dev); | |
689 | } else if (status & 0x0100) { | |
690 | psc_write_word(PSC_ENETWR_CMD + mp->tx_sloti, 0x0100); | |
691 | mp->tx_sloti ^= 0x10; | |
692 | mp->tx_count++; | |
693 | netif_wake_queue(dev); | |
694 | } | |
695 | return IRQ_HANDLED; | |
696 | } | |
697 | ||
698 | MODULE_LICENSE("GPL"); |