mlx4_en: Giving interface name in debug messages
[deliverable/linux.git] / drivers / net / mlx4 / en_rx.c
CommitLineData
c27a02cd
YP
1/*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#include <linux/mlx4/cq.h>
35#include <linux/mlx4/qp.h>
36#include <linux/skbuff.h>
37#include <linux/if_ether.h>
38#include <linux/if_vlan.h>
39#include <linux/vmalloc.h>
40
41#include "mlx4_en.h"
42
43static void *get_wqe(struct mlx4_en_rx_ring *ring, int n)
44{
45 int offset = n << ring->srq.wqe_shift;
46 return ring->buf + offset;
47}
48
49static void mlx4_en_srq_event(struct mlx4_srq *srq, enum mlx4_event type)
50{
51 return;
52}
53
54static int mlx4_en_get_frag_header(struct skb_frag_struct *frags, void **mac_hdr,
55 void **ip_hdr, void **tcpudp_hdr,
56 u64 *hdr_flags, void *priv)
57{
58 *mac_hdr = page_address(frags->page) + frags->page_offset;
59 *ip_hdr = *mac_hdr + ETH_HLEN;
60 *tcpudp_hdr = (struct tcphdr *)(*ip_hdr + sizeof(struct iphdr));
61 *hdr_flags = LRO_IPV4 | LRO_TCP;
62
63 return 0;
64}
65
66static int mlx4_en_alloc_frag(struct mlx4_en_priv *priv,
67 struct mlx4_en_rx_desc *rx_desc,
68 struct skb_frag_struct *skb_frags,
69 struct mlx4_en_rx_alloc *ring_alloc,
70 int i)
71{
72 struct mlx4_en_dev *mdev = priv->mdev;
73 struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
74 struct mlx4_en_rx_alloc *page_alloc = &ring_alloc[i];
75 struct page *page;
76 dma_addr_t dma;
77
78 if (page_alloc->offset == frag_info->last_offset) {
79 /* Allocate new page */
80 page = alloc_pages(GFP_ATOMIC | __GFP_COMP, MLX4_EN_ALLOC_ORDER);
81 if (!page)
82 return -ENOMEM;
83
84 skb_frags[i].page = page_alloc->page;
85 skb_frags[i].page_offset = page_alloc->offset;
86 page_alloc->page = page;
87 page_alloc->offset = frag_info->frag_align;
88 } else {
89 page = page_alloc->page;
90 get_page(page);
91
92 skb_frags[i].page = page;
93 skb_frags[i].page_offset = page_alloc->offset;
94 page_alloc->offset += frag_info->frag_stride;
95 }
96 dma = pci_map_single(mdev->pdev, page_address(skb_frags[i].page) +
97 skb_frags[i].page_offset, frag_info->frag_size,
98 PCI_DMA_FROMDEVICE);
99 rx_desc->data[i].addr = cpu_to_be64(dma);
100 return 0;
101}
102
103static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
104 struct mlx4_en_rx_ring *ring)
105{
106 struct mlx4_en_rx_alloc *page_alloc;
107 int i;
108
109 for (i = 0; i < priv->num_frags; i++) {
110 page_alloc = &ring->page_alloc[i];
111 page_alloc->page = alloc_pages(GFP_ATOMIC | __GFP_COMP,
112 MLX4_EN_ALLOC_ORDER);
113 if (!page_alloc->page)
114 goto out;
115
116 page_alloc->offset = priv->frag_info[i].frag_align;
453a6082
YP
117 en_dbg(DRV, priv, "Initialized allocator:%d with page:%p\n",
118 i, page_alloc->page);
c27a02cd
YP
119 }
120 return 0;
121
122out:
123 while (i--) {
124 page_alloc = &ring->page_alloc[i];
125 put_page(page_alloc->page);
126 page_alloc->page = NULL;
127 }
128 return -ENOMEM;
129}
130
131static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
132 struct mlx4_en_rx_ring *ring)
133{
134 struct mlx4_en_rx_alloc *page_alloc;
135 int i;
136
137 for (i = 0; i < priv->num_frags; i++) {
138 page_alloc = &ring->page_alloc[i];
453a6082
YP
139 en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
140 i, page_count(page_alloc->page));
c27a02cd
YP
141
142 put_page(page_alloc->page);
143 page_alloc->page = NULL;
144 }
145}
146
147
148static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
149 struct mlx4_en_rx_ring *ring, int index)
150{
151 struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
152 struct skb_frag_struct *skb_frags = ring->rx_info +
153 (index << priv->log_rx_info);
154 int possible_frags;
155 int i;
156
157 /* Pre-link descriptor */
158 rx_desc->next.next_wqe_index = cpu_to_be16((index + 1) & ring->size_mask);
159
160 /* Set size and memtype fields */
161 for (i = 0; i < priv->num_frags; i++) {
162 skb_frags[i].size = priv->frag_info[i].frag_size;
163 rx_desc->data[i].byte_count =
164 cpu_to_be32(priv->frag_info[i].frag_size);
165 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
166 }
167
168 /* If the number of used fragments does not fill up the ring stride,
169 * remaining (unused) fragments must be padded with null address/size
170 * and a special memory key */
171 possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
172 for (i = priv->num_frags; i < possible_frags; i++) {
173 rx_desc->data[i].byte_count = 0;
174 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
175 rx_desc->data[i].addr = 0;
176 }
177}
178
179
180static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
181 struct mlx4_en_rx_ring *ring, int index)
182{
183 struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
184 struct skb_frag_struct *skb_frags = ring->rx_info +
185 (index << priv->log_rx_info);
186 int i;
187
188 for (i = 0; i < priv->num_frags; i++)
189 if (mlx4_en_alloc_frag(priv, rx_desc, skb_frags, ring->page_alloc, i))
190 goto err;
191
192 return 0;
193
194err:
195 while (i--)
196 put_page(skb_frags[i].page);
197 return -ENOMEM;
198}
199
200static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
201{
202 *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
203}
204
38aab07c
YP
205static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
206 struct mlx4_en_rx_ring *ring,
207 int index)
208{
209 struct mlx4_en_dev *mdev = priv->mdev;
210 struct skb_frag_struct *skb_frags;
211 struct mlx4_en_rx_desc *rx_desc = ring->buf + (index << ring->log_stride);
212 dma_addr_t dma;
213 int nr;
214
215 skb_frags = ring->rx_info + (index << priv->log_rx_info);
216 for (nr = 0; nr < priv->num_frags; nr++) {
453a6082 217 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
38aab07c
YP
218 dma = be64_to_cpu(rx_desc->data[nr].addr);
219
453a6082 220 en_dbg(DRV, priv, "Unmaping buffer at dma:0x%llx\n", (u64) dma);
38aab07c
YP
221 pci_unmap_single(mdev->pdev, dma, skb_frags[nr].size,
222 PCI_DMA_FROMDEVICE);
223 put_page(skb_frags[nr].page);
224 }
225}
226
c27a02cd
YP
227static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
228{
c27a02cd
YP
229 struct mlx4_en_rx_ring *ring;
230 int ring_ind;
231 int buf_ind;
38aab07c 232 int new_size;
c27a02cd
YP
233
234 for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
235 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
236 ring = &priv->rx_ring[ring_ind];
237
238 if (mlx4_en_prepare_rx_desc(priv, ring,
239 ring->actual_size)) {
240 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
453a6082
YP
241 en_err(priv, "Failed to allocate "
242 "enough rx buffers\n");
c27a02cd
YP
243 return -ENOMEM;
244 } else {
38aab07c 245 new_size = rounddown_pow_of_two(ring->actual_size);
453a6082
YP
246 en_warn(priv, "Only %d buffers allocated "
247 "reducing ring size to %d",
248 ring->actual_size, new_size);
38aab07c 249 goto reduce_rings;
c27a02cd
YP
250 }
251 }
252 ring->actual_size++;
253 ring->prod++;
254 }
255 }
38aab07c
YP
256 return 0;
257
258reduce_rings:
259 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
260 ring = &priv->rx_ring[ring_ind];
261 while (ring->actual_size > new_size) {
262 ring->actual_size--;
263 ring->prod--;
264 mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
265 }
266 ring->size_mask = ring->actual_size - 1;
267 }
268
c27a02cd
YP
269 return 0;
270}
271
272static int mlx4_en_fill_rx_buf(struct net_device *dev,
273 struct mlx4_en_rx_ring *ring)
274{
275 struct mlx4_en_priv *priv = netdev_priv(dev);
276 int num = 0;
277 int err;
278
279 while ((u32) (ring->prod - ring->cons) < ring->actual_size) {
280 err = mlx4_en_prepare_rx_desc(priv, ring, ring->prod &
281 ring->size_mask);
282 if (err) {
283 if (netif_msg_rx_err(priv))
453a6082 284 en_warn(priv, "Failed preparing rx descriptor\n");
c27a02cd
YP
285 priv->port_stats.rx_alloc_failed++;
286 break;
287 }
288 ++num;
289 ++ring->prod;
290 }
38aab07c 291 if ((u32) (ring->prod - ring->cons) == ring->actual_size)
c27a02cd
YP
292 ring->full = 1;
293
294 return num;
295}
296
297static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
298 struct mlx4_en_rx_ring *ring)
299{
c27a02cd 300 int index;
c27a02cd 301
453a6082
YP
302 en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
303 ring->cons, ring->prod);
c27a02cd
YP
304
305 /* Unmap and free Rx buffers */
38aab07c 306 BUG_ON((u32) (ring->prod - ring->cons) > ring->actual_size);
c27a02cd
YP
307 while (ring->cons != ring->prod) {
308 index = ring->cons & ring->size_mask;
453a6082 309 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
38aab07c 310 mlx4_en_free_rx_desc(priv, ring, index);
c27a02cd
YP
311 ++ring->cons;
312 }
313}
314
315
316void mlx4_en_rx_refill(struct work_struct *work)
317{
bf6aede7 318 struct delayed_work *delay = to_delayed_work(work);
c27a02cd
YP
319 struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
320 refill_task);
321 struct mlx4_en_dev *mdev = priv->mdev;
322 struct net_device *dev = priv->dev;
323 struct mlx4_en_rx_ring *ring;
324 int need_refill = 0;
325 int i;
326
327 mutex_lock(&mdev->state_lock);
328 if (!mdev->device_up || !priv->port_up)
329 goto out;
330
331 /* We only get here if there are no receive buffers, so we can't race
332 * with Rx interrupts while filling buffers */
333 for (i = 0; i < priv->rx_ring_num; i++) {
334 ring = &priv->rx_ring[i];
335 if (ring->need_refill) {
336 if (mlx4_en_fill_rx_buf(dev, ring)) {
337 ring->need_refill = 0;
338 mlx4_en_update_rx_prod_db(ring);
339 } else
340 need_refill = 1;
341 }
342 }
343 if (need_refill)
344 queue_delayed_work(mdev->workqueue, &priv->refill_task, HZ);
345
346out:
347 mutex_unlock(&mdev->state_lock);
348}
349
350
351int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
352 struct mlx4_en_rx_ring *ring, u32 size, u16 stride)
353{
354 struct mlx4_en_dev *mdev = priv->mdev;
355 int err;
356 int tmp;
357
358 /* Sanity check SRQ size before proceeding */
359 if (size >= mdev->dev->caps.max_srq_wqes)
360 return -EINVAL;
361
362 ring->prod = 0;
363 ring->cons = 0;
364 ring->size = size;
365 ring->size_mask = size - 1;
366 ring->stride = stride;
367 ring->log_stride = ffs(ring->stride) - 1;
368 ring->buf_size = ring->size * ring->stride;
369
370 tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
371 sizeof(struct skb_frag_struct));
372 ring->rx_info = vmalloc(tmp);
373 if (!ring->rx_info) {
453a6082 374 en_err(priv, "Failed allocating rx_info ring\n");
c27a02cd
YP
375 return -ENOMEM;
376 }
453a6082 377 en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
c27a02cd
YP
378 ring->rx_info, tmp);
379
380 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres,
381 ring->buf_size, 2 * PAGE_SIZE);
382 if (err)
383 goto err_ring;
384
385 err = mlx4_en_map_buffer(&ring->wqres.buf);
386 if (err) {
453a6082 387 en_err(priv, "Failed to map RX buffer\n");
c27a02cd
YP
388 goto err_hwq;
389 }
390 ring->buf = ring->wqres.buf.direct.buf;
391
392 /* Configure lro mngr */
393 memset(&ring->lro, 0, sizeof(struct net_lro_mgr));
394 ring->lro.dev = priv->dev;
395 ring->lro.features = LRO_F_NAPI;
396 ring->lro.frag_align_pad = NET_IP_ALIGN;
397 ring->lro.ip_summed = CHECKSUM_UNNECESSARY;
398 ring->lro.ip_summed_aggr = CHECKSUM_UNNECESSARY;
399 ring->lro.max_desc = mdev->profile.num_lro;
400 ring->lro.max_aggr = MAX_SKB_FRAGS;
401 ring->lro.lro_arr = kzalloc(mdev->profile.num_lro *
402 sizeof(struct net_lro_desc),
403 GFP_KERNEL);
404 if (!ring->lro.lro_arr) {
453a6082 405 en_err(priv, "Failed to allocate lro array\n");
c27a02cd
YP
406 goto err_map;
407 }
408 ring->lro.get_frag_header = mlx4_en_get_frag_header;
409
410 return 0;
411
412err_map:
413 mlx4_en_unmap_buffer(&ring->wqres.buf);
414err_hwq:
415 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
416err_ring:
417 vfree(ring->rx_info);
418 ring->rx_info = NULL;
419 return err;
420}
421
422int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
423{
424 struct mlx4_en_dev *mdev = priv->mdev;
425 struct mlx4_wqe_srq_next_seg *next;
426 struct mlx4_en_rx_ring *ring;
427 int i;
428 int ring_ind;
429 int err;
430 int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
431 DS_SIZE * priv->num_frags);
432 int max_gs = (stride - sizeof(struct mlx4_wqe_srq_next_seg)) / DS_SIZE;
433
434 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
435 ring = &priv->rx_ring[ring_ind];
436
437 ring->prod = 0;
438 ring->cons = 0;
439 ring->actual_size = 0;
440 ring->cqn = priv->rx_cq[ring_ind].mcq.cqn;
441
442 ring->stride = stride;
443 ring->log_stride = ffs(ring->stride) - 1;
444 ring->buf_size = ring->size * ring->stride;
445
446 memset(ring->buf, 0, ring->buf_size);
447 mlx4_en_update_rx_prod_db(ring);
448
449 /* Initailize all descriptors */
450 for (i = 0; i < ring->size; i++)
451 mlx4_en_init_rx_desc(priv, ring, i);
452
453 /* Initialize page allocators */
454 err = mlx4_en_init_allocator(priv, ring);
455 if (err) {
453a6082 456 en_err(priv, "Failed initializing ring allocator\n");
9a4f92a6
YP
457 ring_ind--;
458 goto err_allocator;
c27a02cd
YP
459 }
460
461 /* Fill Rx buffers */
462 ring->full = 0;
463 }
b58515be
IM
464 err = mlx4_en_fill_rx_buffers(priv);
465 if (err)
c27a02cd
YP
466 goto err_buffers;
467
468 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
469 ring = &priv->rx_ring[ring_ind];
470
471 mlx4_en_update_rx_prod_db(ring);
472
473 /* Configure SRQ representing the ring */
38aab07c 474 ring->srq.max = ring->actual_size;
c27a02cd
YP
475 ring->srq.max_gs = max_gs;
476 ring->srq.wqe_shift = ilog2(ring->stride);
477
478 for (i = 0; i < ring->srq.max; ++i) {
479 next = get_wqe(ring, i);
480 next->next_wqe_index =
481 cpu_to_be16((i + 1) & (ring->srq.max - 1));
482 }
483
484 err = mlx4_srq_alloc(mdev->dev, mdev->priv_pdn, &ring->wqres.mtt,
485 ring->wqres.db.dma, &ring->srq);
486 if (err){
453a6082 487 en_err(priv, "Failed to allocate srq\n");
9a4f92a6 488 ring_ind--;
c27a02cd
YP
489 goto err_srq;
490 }
491 ring->srq.event = mlx4_en_srq_event;
492 }
493
494 return 0;
495
496err_srq:
497 while (ring_ind >= 0) {
498 ring = &priv->rx_ring[ring_ind];
499 mlx4_srq_free(mdev->dev, &ring->srq);
500 ring_ind--;
501 }
502
503err_buffers:
504 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
505 mlx4_en_free_rx_buf(priv, &priv->rx_ring[ring_ind]);
506
507 ring_ind = priv->rx_ring_num - 1;
508err_allocator:
509 while (ring_ind >= 0) {
510 mlx4_en_destroy_allocator(priv, &priv->rx_ring[ring_ind]);
511 ring_ind--;
512 }
513 return err;
514}
515
516void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
517 struct mlx4_en_rx_ring *ring)
518{
519 struct mlx4_en_dev *mdev = priv->mdev;
520
521 kfree(ring->lro.lro_arr);
522 mlx4_en_unmap_buffer(&ring->wqres.buf);
523 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
524 vfree(ring->rx_info);
525 ring->rx_info = NULL;
526}
527
528void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
529 struct mlx4_en_rx_ring *ring)
530{
531 struct mlx4_en_dev *mdev = priv->mdev;
532
533 mlx4_srq_free(mdev->dev, &ring->srq);
534 mlx4_en_free_rx_buf(priv, ring);
535 mlx4_en_destroy_allocator(priv, ring);
536}
537
538
539/* Unmap a completed descriptor and free unused pages */
540static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
541 struct mlx4_en_rx_desc *rx_desc,
542 struct skb_frag_struct *skb_frags,
543 struct skb_frag_struct *skb_frags_rx,
544 struct mlx4_en_rx_alloc *page_alloc,
545 int length)
546{
547 struct mlx4_en_dev *mdev = priv->mdev;
548 struct mlx4_en_frag_info *frag_info;
549 int nr;
550 dma_addr_t dma;
551
552 /* Collect used fragments while replacing them in the HW descirptors */
553 for (nr = 0; nr < priv->num_frags; nr++) {
554 frag_info = &priv->frag_info[nr];
555 if (length <= frag_info->frag_prefix_size)
556 break;
557
558 /* Save page reference in skb */
559 skb_frags_rx[nr].page = skb_frags[nr].page;
560 skb_frags_rx[nr].size = skb_frags[nr].size;
561 skb_frags_rx[nr].page_offset = skb_frags[nr].page_offset;
562 dma = be64_to_cpu(rx_desc->data[nr].addr);
563
564 /* Allocate a replacement page */
565 if (mlx4_en_alloc_frag(priv, rx_desc, skb_frags, page_alloc, nr))
566 goto fail;
567
568 /* Unmap buffer */
569 pci_unmap_single(mdev->pdev, dma, skb_frags[nr].size,
570 PCI_DMA_FROMDEVICE);
571 }
572 /* Adjust size of last fragment to match actual length */
573 skb_frags_rx[nr - 1].size = length -
574 priv->frag_info[nr - 1].frag_prefix_size;
575 return nr;
576
577fail:
578 /* Drop all accumulated fragments (which have already been replaced in
579 * the descriptor) of this packet; remaining fragments are reused... */
580 while (nr > 0) {
581 nr--;
582 put_page(skb_frags_rx[nr].page);
583 }
584 return 0;
585}
586
587
588static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
589 struct mlx4_en_rx_desc *rx_desc,
590 struct skb_frag_struct *skb_frags,
591 struct mlx4_en_rx_alloc *page_alloc,
592 unsigned int length)
593{
594 struct mlx4_en_dev *mdev = priv->mdev;
595 struct sk_buff *skb;
596 void *va;
597 int used_frags;
598 dma_addr_t dma;
599
600 skb = dev_alloc_skb(SMALL_PACKET_SIZE + NET_IP_ALIGN);
601 if (!skb) {
453a6082 602 en_dbg(RX_ERR, priv, "Failed allocating skb\n");
c27a02cd
YP
603 return NULL;
604 }
605 skb->dev = priv->dev;
606 skb_reserve(skb, NET_IP_ALIGN);
607 skb->len = length;
608 skb->truesize = length + sizeof(struct sk_buff);
609
610 /* Get pointer to first fragment so we could copy the headers into the
611 * (linear part of the) skb */
612 va = page_address(skb_frags[0].page) + skb_frags[0].page_offset;
613
614 if (length <= SMALL_PACKET_SIZE) {
615 /* We are copying all relevant data to the skb - temporarily
616 * synch buffers for the copy */
617 dma = be64_to_cpu(rx_desc->data[0].addr);
618 dma_sync_single_range_for_cpu(&mdev->pdev->dev, dma, 0,
619 length, DMA_FROM_DEVICE);
620 skb_copy_to_linear_data(skb, va, length);
621 dma_sync_single_range_for_device(&mdev->pdev->dev, dma, 0,
622 length, DMA_FROM_DEVICE);
623 skb->tail += length;
624 } else {
625
626 /* Move relevant fragments to skb */
627 used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, skb_frags,
628 skb_shinfo(skb)->frags,
629 page_alloc, length);
785a0982
YP
630 if (unlikely(!used_frags)) {
631 kfree_skb(skb);
632 return NULL;
633 }
c27a02cd
YP
634 skb_shinfo(skb)->nr_frags = used_frags;
635
636 /* Copy headers into the skb linear buffer */
637 memcpy(skb->data, va, HEADER_COPY_SIZE);
638 skb->tail += HEADER_COPY_SIZE;
639
640 /* Skip headers in first fragment */
641 skb_shinfo(skb)->frags[0].page_offset += HEADER_COPY_SIZE;
642
643 /* Adjust size of first fragment */
644 skb_shinfo(skb)->frags[0].size -= HEADER_COPY_SIZE;
645 skb->data_len = length - HEADER_COPY_SIZE;
646 }
647 return skb;
648}
649
650static void mlx4_en_copy_desc(struct mlx4_en_priv *priv,
651 struct mlx4_en_rx_ring *ring,
652 int from, int to, int num)
653{
654 struct skb_frag_struct *skb_frags_from;
655 struct skb_frag_struct *skb_frags_to;
656 struct mlx4_en_rx_desc *rx_desc_from;
657 struct mlx4_en_rx_desc *rx_desc_to;
658 int from_index, to_index;
659 int nr, i;
660
661 for (i = 0; i < num; i++) {
662 from_index = (from + i) & ring->size_mask;
663 to_index = (to + i) & ring->size_mask;
664 skb_frags_from = ring->rx_info + (from_index << priv->log_rx_info);
665 skb_frags_to = ring->rx_info + (to_index << priv->log_rx_info);
666 rx_desc_from = ring->buf + (from_index << ring->log_stride);
667 rx_desc_to = ring->buf + (to_index << ring->log_stride);
668
669 for (nr = 0; nr < priv->num_frags; nr++) {
670 skb_frags_to[nr].page = skb_frags_from[nr].page;
671 skb_frags_to[nr].page_offset = skb_frags_from[nr].page_offset;
672 rx_desc_to->data[nr].addr = rx_desc_from->data[nr].addr;
673 }
674 }
675}
676
677
678int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
679{
680 struct mlx4_en_priv *priv = netdev_priv(dev);
c27a02cd
YP
681 struct mlx4_cqe *cqe;
682 struct mlx4_en_rx_ring *ring = &priv->rx_ring[cq->ring];
683 struct skb_frag_struct *skb_frags;
684 struct skb_frag_struct lro_frags[MLX4_EN_MAX_RX_FRAGS];
685 struct mlx4_en_rx_desc *rx_desc;
686 struct sk_buff *skb;
687 int index;
688 int nr;
689 unsigned int length;
690 int polled = 0;
691 int ip_summed;
692
693 if (!priv->port_up)
694 return 0;
695
696 /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
697 * descriptor offset can be deduced from the CQE index instead of
698 * reading 'cqe->index' */
699 index = cq->mcq.cons_index & ring->size_mask;
700 cqe = &cq->buf[index];
701
702 /* Process all completed CQEs */
703 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
704 cq->mcq.cons_index & cq->size)) {
705
706 skb_frags = ring->rx_info + (index << priv->log_rx_info);
707 rx_desc = ring->buf + (index << ring->log_stride);
708
709 /*
710 * make sure we read the CQE after we read the ownership bit
711 */
712 rmb();
713
714 /* Drop packet on bad receive or bad checksum */
715 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
716 MLX4_CQE_OPCODE_ERROR)) {
453a6082 717 en_err(priv, "CQE completed in error - vendor "
c27a02cd
YP
718 "syndrom:%d syndrom:%d\n",
719 ((struct mlx4_err_cqe *) cqe)->vendor_err_syndrome,
720 ((struct mlx4_err_cqe *) cqe)->syndrome);
721 goto next;
722 }
723 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
453a6082 724 en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
c27a02cd
YP
725 goto next;
726 }
727
728 /*
729 * Packet is OK - process it.
730 */
731 length = be32_to_cpu(cqe->byte_cnt);
732 ring->bytes += length;
733 ring->packets++;
734
735 if (likely(priv->rx_csum)) {
736 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
737 (cqe->checksum == cpu_to_be16(0xffff))) {
738 priv->port_stats.rx_chksum_good++;
739 /* This packet is eligible for LRO if it is:
740 * - DIX Ethernet (type interpretation)
741 * - TCP/IP (v4)
742 * - without IP options
743 * - not an IP fragment */
744 if (mlx4_en_can_lro(cqe->status) &&
745 dev->features & NETIF_F_LRO) {
746
747 nr = mlx4_en_complete_rx_desc(
748 priv, rx_desc,
749 skb_frags, lro_frags,
750 ring->page_alloc, length);
751 if (!nr)
752 goto next;
753
754 if (priv->vlgrp && (cqe->vlan_my_qpn &
755 cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK))) {
756 lro_vlan_hwaccel_receive_frags(
757 &ring->lro, lro_frags,
758 length, length,
759 priv->vlgrp,
760 be16_to_cpu(cqe->sl_vid),
761 NULL, 0);
762 } else
763 lro_receive_frags(&ring->lro,
764 lro_frags,
765 length,
766 length,
767 NULL, 0);
768
769 goto next;
770 }
771
772 /* LRO not possible, complete processing here */
773 ip_summed = CHECKSUM_UNNECESSARY;
774 INC_PERF_COUNTER(priv->pstats.lro_misses);
775 } else {
776 ip_summed = CHECKSUM_NONE;
777 priv->port_stats.rx_chksum_none++;
778 }
779 } else {
780 ip_summed = CHECKSUM_NONE;
781 priv->port_stats.rx_chksum_none++;
782 }
783
784 skb = mlx4_en_rx_skb(priv, rx_desc, skb_frags,
785 ring->page_alloc, length);
786 if (!skb) {
787 priv->stats.rx_dropped++;
788 goto next;
789 }
790
791 skb->ip_summed = ip_summed;
792 skb->protocol = eth_type_trans(skb, dev);
0c8dfc83 793 skb_record_rx_queue(skb, cq->ring);
c27a02cd
YP
794
795 /* Push it up the stack */
796 if (priv->vlgrp && (be32_to_cpu(cqe->vlan_my_qpn) &
797 MLX4_CQE_VLAN_PRESENT_MASK)) {
798 vlan_hwaccel_receive_skb(skb, priv->vlgrp,
799 be16_to_cpu(cqe->sl_vid));
800 } else
801 netif_receive_skb(skb);
802
c27a02cd
YP
803next:
804 ++cq->mcq.cons_index;
805 index = (cq->mcq.cons_index) & ring->size_mask;
806 cqe = &cq->buf[index];
807 if (++polled == budget) {
808 /* We are here because we reached the NAPI budget -
809 * flush only pending LRO sessions */
810 lro_flush_all(&ring->lro);
811 goto out;
812 }
813 }
814
815 /* If CQ is empty flush all LRO sessions unconditionally */
816 lro_flush_all(&ring->lro);
817
818out:
819 AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
820 mlx4_cq_set_ci(&cq->mcq);
821 wmb(); /* ensure HW sees CQ consumer before we post new buffers */
822 ring->cons = cq->mcq.cons_index;
823 ring->prod += polled; /* Polled descriptors were realocated in place */
824 if (unlikely(!ring->full)) {
825 mlx4_en_copy_desc(priv, ring, ring->cons - polled,
826 ring->prod - polled, polled);
827 mlx4_en_fill_rx_buf(dev, ring);
828 }
829 mlx4_en_update_rx_prod_db(ring);
830 return polled;
831}
832
833
834void mlx4_en_rx_irq(struct mlx4_cq *mcq)
835{
836 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
837 struct mlx4_en_priv *priv = netdev_priv(cq->dev);
838
839 if (priv->port_up)
288379f0 840 napi_schedule(&cq->napi);
c27a02cd
YP
841 else
842 mlx4_en_arm_cq(priv, cq);
843}
844
845/* Rx CQ polling - called by NAPI */
846int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
847{
848 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
849 struct net_device *dev = cq->dev;
850 struct mlx4_en_priv *priv = netdev_priv(dev);
851 int done;
852
853 done = mlx4_en_process_rx_cq(dev, cq, budget);
854
855 /* If we used up all the quota - we're probably not done yet... */
856 if (done == budget)
857 INC_PERF_COUNTER(priv->pstats.napi_quota);
858 else {
859 /* Done for now */
288379f0 860 napi_complete(napi);
c27a02cd
YP
861 mlx4_en_arm_cq(priv, cq);
862 }
863 return done;
864}
865
866
867/* Calculate the last offset position that accomodates a full fragment
868 * (assuming fagment size = stride-align) */
869static int mlx4_en_last_alloc_offset(struct mlx4_en_priv *priv, u16 stride, u16 align)
870{
871 u16 res = MLX4_EN_ALLOC_SIZE % stride;
872 u16 offset = MLX4_EN_ALLOC_SIZE - stride - res + align;
873
453a6082 874 en_dbg(DRV, priv, "Calculated last offset for stride:%d align:%d "
c27a02cd
YP
875 "res:%d offset:%d\n", stride, align, res, offset);
876 return offset;
877}
878
879
880static int frag_sizes[] = {
881 FRAG_SZ0,
882 FRAG_SZ1,
883 FRAG_SZ2,
884 FRAG_SZ3
885};
886
887void mlx4_en_calc_rx_buf(struct net_device *dev)
888{
889 struct mlx4_en_priv *priv = netdev_priv(dev);
890 int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN + ETH_LLC_SNAP_SIZE;
891 int buf_size = 0;
892 int i = 0;
893
894 while (buf_size < eff_mtu) {
895 priv->frag_info[i].frag_size =
896 (eff_mtu > buf_size + frag_sizes[i]) ?
897 frag_sizes[i] : eff_mtu - buf_size;
898 priv->frag_info[i].frag_prefix_size = buf_size;
899 if (!i) {
900 priv->frag_info[i].frag_align = NET_IP_ALIGN;
901 priv->frag_info[i].frag_stride =
902 ALIGN(frag_sizes[i] + NET_IP_ALIGN, SMP_CACHE_BYTES);
903 } else {
904 priv->frag_info[i].frag_align = 0;
905 priv->frag_info[i].frag_stride =
906 ALIGN(frag_sizes[i], SMP_CACHE_BYTES);
907 }
908 priv->frag_info[i].last_offset = mlx4_en_last_alloc_offset(
909 priv, priv->frag_info[i].frag_stride,
910 priv->frag_info[i].frag_align);
911 buf_size += priv->frag_info[i].frag_size;
912 i++;
913 }
914
915 priv->num_frags = i;
916 priv->rx_skb_size = eff_mtu;
917 priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct skb_frag_struct));
918
453a6082 919 en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d "
c27a02cd
YP
920 "num_frags:%d):\n", eff_mtu, priv->num_frags);
921 for (i = 0; i < priv->num_frags; i++) {
453a6082 922 en_dbg(DRV, priv, " frag:%d - size:%d prefix:%d align:%d "
c27a02cd
YP
923 "stride:%d last_offset:%d\n", i,
924 priv->frag_info[i].frag_size,
925 priv->frag_info[i].frag_prefix_size,
926 priv->frag_info[i].frag_align,
927 priv->frag_info[i].frag_stride,
928 priv->frag_info[i].last_offset);
929 }
930}
931
932/* RSS related functions */
933
934/* Calculate rss size and map each entry in rss table to rx ring */
935void mlx4_en_set_default_rss_map(struct mlx4_en_priv *priv,
936 struct mlx4_en_rss_map *rss_map,
937 int num_entries, int num_rings)
938{
939 int i;
940
941 rss_map->size = roundup_pow_of_two(num_entries);
453a6082
YP
942 en_dbg(DRV, priv, "Setting default RSS map of %d entires\n",
943 rss_map->size);
c27a02cd
YP
944
945 for (i = 0; i < rss_map->size; i++) {
946 rss_map->map[i] = i % num_rings;
453a6082 947 en_dbg(DRV, priv, "Entry %d ---> ring %d\n", i, rss_map->map[i]);
c27a02cd
YP
948 }
949}
950
c27a02cd
YP
951static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv,
952 int qpn, int srqn, int cqn,
953 enum mlx4_qp_state *state,
954 struct mlx4_qp *qp)
955{
956 struct mlx4_en_dev *mdev = priv->mdev;
957 struct mlx4_qp_context *context;
958 int err = 0;
959
960 context = kmalloc(sizeof *context , GFP_KERNEL);
961 if (!context) {
453a6082 962 en_err(priv, "Failed to allocate qp context\n");
c27a02cd
YP
963 return -ENOMEM;
964 }
965
966 err = mlx4_qp_alloc(mdev->dev, qpn, qp);
967 if (err) {
453a6082 968 en_err(priv, "Failed to allocate qp #%x\n", qpn);
c27a02cd 969 goto out;
c27a02cd
YP
970 }
971 qp->event = mlx4_en_sqp_event;
972
973 memset(context, 0, sizeof *context);
974 mlx4_en_fill_qp_context(priv, 0, 0, 0, 0, qpn, cqn, srqn, context);
975
976 err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, context, qp, state);
977 if (err) {
978 mlx4_qp_remove(mdev->dev, qp);
979 mlx4_qp_free(mdev->dev, qp);
980 }
981out:
982 kfree(context);
983 return err;
984}
985
986/* Allocate rx qp's and configure them according to rss map */
987int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
988{
989 struct mlx4_en_dev *mdev = priv->mdev;
990 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
991 struct mlx4_qp_context context;
992 struct mlx4_en_rss_context *rss_context;
993 void *ptr;
994 int rss_xor = mdev->profile.rss_xor;
995 u8 rss_mask = mdev->profile.rss_mask;
996 int i, srqn, qpn, cqn;
997 int err = 0;
998 int good_qps = 0;
999
453a6082 1000 en_dbg(DRV, priv, "Configuring rss steering\n");
c27a02cd
YP
1001 err = mlx4_qp_reserve_range(mdev->dev, rss_map->size,
1002 rss_map->size, &rss_map->base_qpn);
1003 if (err) {
453a6082 1004 en_err(priv, "Failed reserving %d qps\n", rss_map->size);
c27a02cd
YP
1005 return err;
1006 }
1007
1008 for (i = 0; i < rss_map->size; i++) {
1009 cqn = priv->rx_ring[rss_map->map[i]].cqn;
1010 srqn = priv->rx_ring[rss_map->map[i]].srq.srqn;
1011 qpn = rss_map->base_qpn + i;
1012 err = mlx4_en_config_rss_qp(priv, qpn, srqn, cqn,
1013 &rss_map->state[i],
1014 &rss_map->qps[i]);
1015 if (err)
1016 goto rss_err;
1017
1018 ++good_qps;
1019 }
1020
1021 /* Configure RSS indirection qp */
1022 err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &priv->base_qpn);
1023 if (err) {
453a6082
YP
1024 en_err(priv, "Failed to reserve range for RSS "
1025 "indirection qp\n");
c27a02cd
YP
1026 goto rss_err;
1027 }
1028 err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp);
1029 if (err) {
453a6082 1030 en_err(priv, "Failed to allocate RSS indirection QP\n");
c27a02cd
YP
1031 goto reserve_err;
1032 }
1033 rss_map->indir_qp.event = mlx4_en_sqp_event;
1034 mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
1035 priv->rx_ring[0].cqn, 0, &context);
1036
1037 ptr = ((void *) &context) + 0x3c;
1038 rss_context = (struct mlx4_en_rss_context *) ptr;
1039 rss_context->base_qpn = cpu_to_be32(ilog2(rss_map->size) << 24 |
1040 (rss_map->base_qpn));
1041 rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
1042 rss_context->hash_fn = rss_xor & 0x3;
1043 rss_context->flags = rss_mask << 2;
1044
1045 err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
1046 &rss_map->indir_qp, &rss_map->indir_state);
1047 if (err)
1048 goto indir_err;
1049
1050 return 0;
1051
1052indir_err:
1053 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1054 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1055 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1056 mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1057reserve_err:
1058 mlx4_qp_release_range(mdev->dev, priv->base_qpn, 1);
1059rss_err:
1060 for (i = 0; i < good_qps; i++) {
1061 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1062 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1063 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1064 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1065 }
1066 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, rss_map->size);
1067 return err;
1068}
1069
1070void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
1071{
1072 struct mlx4_en_dev *mdev = priv->mdev;
1073 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1074 int i;
1075
1076 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1077 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1078 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1079 mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1080 mlx4_qp_release_range(mdev->dev, priv->base_qpn, 1);
1081
1082 for (i = 0; i < rss_map->size; i++) {
1083 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1084 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1085 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1086 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1087 }
1088 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, rss_map->size);
1089}
1090
1091
1092
1093
1094
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