Commit | Line | Data |
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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
34 | #include <asm/page.h> | |
35 | #include <linux/mlx4/cq.h> | |
5a0e3ad6 | 36 | #include <linux/slab.h> |
c27a02cd YP |
37 | #include <linux/mlx4/qp.h> |
38 | #include <linux/skbuff.h> | |
39 | #include <linux/if_vlan.h> | |
40 | #include <linux/vmalloc.h> | |
fa37a958 | 41 | #include <linux/tcp.h> |
c27a02cd YP |
42 | |
43 | #include "mlx4_en.h" | |
44 | ||
45 | enum { | |
46 | MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */ | |
47 | }; | |
48 | ||
49 | static int inline_thold __read_mostly = MAX_INLINE; | |
50 | ||
51 | module_param_named(inline_thold, inline_thold, int, 0444); | |
af901ca1 | 52 | MODULE_PARM_DESC(inline_thold, "threshold for using inline data"); |
c27a02cd YP |
53 | |
54 | int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, | |
55 | struct mlx4_en_tx_ring *ring, u32 size, | |
56 | u16 stride) | |
57 | { | |
58 | struct mlx4_en_dev *mdev = priv->mdev; | |
59 | int tmp; | |
60 | int err; | |
61 | ||
62 | ring->size = size; | |
63 | ring->size_mask = size - 1; | |
64 | ring->stride = stride; | |
65 | ||
66 | inline_thold = min(inline_thold, MAX_INLINE); | |
67 | ||
68 | spin_lock_init(&ring->comp_lock); | |
69 | ||
70 | tmp = size * sizeof(struct mlx4_en_tx_info); | |
71 | ring->tx_info = vmalloc(tmp); | |
72 | if (!ring->tx_info) { | |
453a6082 | 73 | en_err(priv, "Failed allocating tx_info ring\n"); |
c27a02cd YP |
74 | return -ENOMEM; |
75 | } | |
453a6082 | 76 | en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n", |
c27a02cd YP |
77 | ring->tx_info, tmp); |
78 | ||
79 | ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL); | |
80 | if (!ring->bounce_buf) { | |
453a6082 | 81 | en_err(priv, "Failed allocating bounce buffer\n"); |
c27a02cd YP |
82 | err = -ENOMEM; |
83 | goto err_tx; | |
84 | } | |
85 | ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE); | |
86 | ||
87 | err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size, | |
88 | 2 * PAGE_SIZE); | |
89 | if (err) { | |
453a6082 | 90 | en_err(priv, "Failed allocating hwq resources\n"); |
c27a02cd YP |
91 | goto err_bounce; |
92 | } | |
93 | ||
94 | err = mlx4_en_map_buffer(&ring->wqres.buf); | |
95 | if (err) { | |
453a6082 | 96 | en_err(priv, "Failed to map TX buffer\n"); |
c27a02cd YP |
97 | goto err_hwq_res; |
98 | } | |
99 | ||
100 | ring->buf = ring->wqres.buf.direct.buf; | |
101 | ||
453a6082 YP |
102 | en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d " |
103 | "buf_size:%d dma:%llx\n", ring, ring->buf, ring->size, | |
104 | ring->buf_size, (unsigned long long) ring->wqres.buf.direct.map); | |
c27a02cd YP |
105 | |
106 | err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn); | |
107 | if (err) { | |
453a6082 | 108 | en_err(priv, "Failed reserving qp for tx ring.\n"); |
c27a02cd YP |
109 | goto err_map; |
110 | } | |
111 | ||
112 | err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp); | |
113 | if (err) { | |
453a6082 | 114 | en_err(priv, "Failed allocating qp %d\n", ring->qpn); |
c27a02cd YP |
115 | goto err_reserve; |
116 | } | |
966508f7 | 117 | ring->qp.event = mlx4_en_sqp_event; |
c27a02cd YP |
118 | |
119 | return 0; | |
120 | ||
121 | err_reserve: | |
122 | mlx4_qp_release_range(mdev->dev, ring->qpn, 1); | |
123 | err_map: | |
124 | mlx4_en_unmap_buffer(&ring->wqres.buf); | |
125 | err_hwq_res: | |
126 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); | |
127 | err_bounce: | |
128 | kfree(ring->bounce_buf); | |
129 | ring->bounce_buf = NULL; | |
130 | err_tx: | |
131 | vfree(ring->tx_info); | |
132 | ring->tx_info = NULL; | |
133 | return err; | |
134 | } | |
135 | ||
136 | void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, | |
137 | struct mlx4_en_tx_ring *ring) | |
138 | { | |
139 | struct mlx4_en_dev *mdev = priv->mdev; | |
453a6082 | 140 | en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn); |
c27a02cd YP |
141 | |
142 | mlx4_qp_remove(mdev->dev, &ring->qp); | |
143 | mlx4_qp_free(mdev->dev, &ring->qp); | |
144 | mlx4_qp_release_range(mdev->dev, ring->qpn, 1); | |
145 | mlx4_en_unmap_buffer(&ring->wqres.buf); | |
146 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); | |
147 | kfree(ring->bounce_buf); | |
148 | ring->bounce_buf = NULL; | |
149 | vfree(ring->tx_info); | |
150 | ring->tx_info = NULL; | |
151 | } | |
152 | ||
153 | int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, | |
154 | struct mlx4_en_tx_ring *ring, | |
9f519f68 | 155 | int cq) |
c27a02cd YP |
156 | { |
157 | struct mlx4_en_dev *mdev = priv->mdev; | |
158 | int err; | |
159 | ||
160 | ring->cqn = cq; | |
161 | ring->prod = 0; | |
162 | ring->cons = 0xffffffff; | |
163 | ring->last_nr_txbb = 1; | |
164 | ring->poll_cnt = 0; | |
165 | ring->blocked = 0; | |
166 | memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info)); | |
167 | memset(ring->buf, 0, ring->buf_size); | |
168 | ||
169 | ring->qp_state = MLX4_QP_STATE_RST; | |
170 | ring->doorbell_qpn = swab32(ring->qp.qpn << 8); | |
171 | ||
172 | mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn, | |
9f519f68 | 173 | ring->cqn, &ring->context); |
c27a02cd YP |
174 | |
175 | err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context, | |
176 | &ring->qp, &ring->qp_state); | |
177 | ||
178 | return err; | |
179 | } | |
180 | ||
181 | void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, | |
182 | struct mlx4_en_tx_ring *ring) | |
183 | { | |
184 | struct mlx4_en_dev *mdev = priv->mdev; | |
185 | ||
186 | mlx4_qp_modify(mdev->dev, NULL, ring->qp_state, | |
187 | MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp); | |
188 | } | |
189 | ||
190 | ||
191 | static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, | |
192 | struct mlx4_en_tx_ring *ring, | |
193 | int index, u8 owner) | |
194 | { | |
195 | struct mlx4_en_dev *mdev = priv->mdev; | |
196 | struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; | |
197 | struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; | |
198 | struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset; | |
199 | struct sk_buff *skb = tx_info->skb; | |
200 | struct skb_frag_struct *frag; | |
201 | void *end = ring->buf + ring->buf_size; | |
202 | int frags = skb_shinfo(skb)->nr_frags; | |
203 | int i; | |
204 | __be32 *ptr = (__be32 *)tx_desc; | |
205 | __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT)); | |
206 | ||
207 | /* Optimize the common case when there are no wraparounds */ | |
208 | if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { | |
41efea5a YP |
209 | if (!tx_info->inl) { |
210 | if (tx_info->linear) { | |
211 | pci_unmap_single(mdev->pdev, | |
212 | (dma_addr_t) be64_to_cpu(data->addr), | |
c27a02cd YP |
213 | be32_to_cpu(data->byte_count), |
214 | PCI_DMA_TODEVICE); | |
41efea5a YP |
215 | ++data; |
216 | } | |
c27a02cd | 217 | |
41efea5a YP |
218 | for (i = 0; i < frags; i++) { |
219 | frag = &skb_shinfo(skb)->frags[i]; | |
220 | pci_unmap_page(mdev->pdev, | |
221 | (dma_addr_t) be64_to_cpu(data[i].addr), | |
222 | frag->size, PCI_DMA_TODEVICE); | |
223 | } | |
c27a02cd YP |
224 | } |
225 | /* Stamp the freed descriptor */ | |
226 | for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; i += STAMP_STRIDE) { | |
227 | *ptr = stamp; | |
228 | ptr += STAMP_DWORDS; | |
229 | } | |
230 | ||
231 | } else { | |
41efea5a YP |
232 | if (!tx_info->inl) { |
233 | if ((void *) data >= end) { | |
234 | data = (struct mlx4_wqe_data_seg *) | |
235 | (ring->buf + ((void *) data - end)); | |
236 | } | |
c27a02cd | 237 | |
41efea5a YP |
238 | if (tx_info->linear) { |
239 | pci_unmap_single(mdev->pdev, | |
240 | (dma_addr_t) be64_to_cpu(data->addr), | |
c27a02cd YP |
241 | be32_to_cpu(data->byte_count), |
242 | PCI_DMA_TODEVICE); | |
41efea5a YP |
243 | ++data; |
244 | } | |
c27a02cd | 245 | |
41efea5a YP |
246 | for (i = 0; i < frags; i++) { |
247 | /* Check for wraparound before unmapping */ | |
248 | if ((void *) data >= end) | |
249 | data = (struct mlx4_wqe_data_seg *) ring->buf; | |
250 | frag = &skb_shinfo(skb)->frags[i]; | |
251 | pci_unmap_page(mdev->pdev, | |
c27a02cd YP |
252 | (dma_addr_t) be64_to_cpu(data->addr), |
253 | frag->size, PCI_DMA_TODEVICE); | |
eb4ad826 | 254 | ++data; |
41efea5a | 255 | } |
c27a02cd YP |
256 | } |
257 | /* Stamp the freed descriptor */ | |
258 | for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; i += STAMP_STRIDE) { | |
259 | *ptr = stamp; | |
260 | ptr += STAMP_DWORDS; | |
261 | if ((void *) ptr >= end) { | |
262 | ptr = ring->buf; | |
263 | stamp ^= cpu_to_be32(0x80000000); | |
264 | } | |
265 | } | |
266 | ||
267 | } | |
268 | dev_kfree_skb_any(skb); | |
269 | return tx_info->nr_txbb; | |
270 | } | |
271 | ||
272 | ||
273 | int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring) | |
274 | { | |
275 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
276 | int cnt = 0; | |
277 | ||
278 | /* Skip last polled descriptor */ | |
279 | ring->cons += ring->last_nr_txbb; | |
453a6082 | 280 | en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n", |
c27a02cd YP |
281 | ring->cons, ring->prod); |
282 | ||
283 | if ((u32) (ring->prod - ring->cons) > ring->size) { | |
284 | if (netif_msg_tx_err(priv)) | |
453a6082 | 285 | en_warn(priv, "Tx consumer passed producer!\n"); |
c27a02cd YP |
286 | return 0; |
287 | } | |
288 | ||
289 | while (ring->cons != ring->prod) { | |
290 | ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring, | |
291 | ring->cons & ring->size_mask, | |
292 | !!(ring->cons & ring->size)); | |
293 | ring->cons += ring->last_nr_txbb; | |
294 | cnt++; | |
295 | } | |
296 | ||
297 | if (cnt) | |
453a6082 | 298 | en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt); |
c27a02cd YP |
299 | |
300 | return cnt; | |
301 | } | |
302 | ||
c27a02cd YP |
303 | |
304 | static void mlx4_en_process_tx_cq(struct net_device *dev, struct mlx4_en_cq *cq) | |
305 | { | |
306 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
307 | struct mlx4_cq *mcq = &cq->mcq; | |
308 | struct mlx4_en_tx_ring *ring = &priv->tx_ring[cq->ring]; | |
309 | struct mlx4_cqe *cqe = cq->buf; | |
310 | u16 index; | |
311 | u16 new_index; | |
312 | u32 txbbs_skipped = 0; | |
313 | u32 cq_last_sav; | |
314 | ||
315 | /* index always points to the first TXBB of the last polled descriptor */ | |
316 | index = ring->cons & ring->size_mask; | |
317 | new_index = be16_to_cpu(cqe->wqe_index) & ring->size_mask; | |
318 | if (index == new_index) | |
319 | return; | |
320 | ||
321 | if (!priv->port_up) | |
322 | return; | |
323 | ||
324 | /* | |
325 | * We use a two-stage loop: | |
326 | * - the first samples the HW-updated CQE | |
327 | * - the second frees TXBBs until the last sample | |
328 | * This lets us amortize CQE cache misses, while still polling the CQ | |
329 | * until is quiescent. | |
330 | */ | |
331 | cq_last_sav = mcq->cons_index; | |
332 | do { | |
333 | do { | |
334 | /* Skip over last polled CQE */ | |
335 | index = (index + ring->last_nr_txbb) & ring->size_mask; | |
336 | txbbs_skipped += ring->last_nr_txbb; | |
337 | ||
338 | /* Poll next CQE */ | |
339 | ring->last_nr_txbb = mlx4_en_free_tx_desc( | |
340 | priv, ring, index, | |
341 | !!((ring->cons + txbbs_skipped) & | |
342 | ring->size)); | |
343 | ++mcq->cons_index; | |
344 | ||
345 | } while (index != new_index); | |
346 | ||
347 | new_index = be16_to_cpu(cqe->wqe_index) & ring->size_mask; | |
348 | } while (index != new_index); | |
349 | AVG_PERF_COUNTER(priv->pstats.tx_coal_avg, | |
350 | (u32) (mcq->cons_index - cq_last_sav)); | |
351 | ||
352 | /* | |
353 | * To prevent CQ overflow we first update CQ consumer and only then | |
354 | * the ring consumer. | |
355 | */ | |
356 | mlx4_cq_set_ci(mcq); | |
357 | wmb(); | |
358 | ring->cons += txbbs_skipped; | |
359 | ||
360 | /* Wakeup Tx queue if this ring stopped it */ | |
361 | if (unlikely(ring->blocked)) { | |
c03ea21f YP |
362 | if ((u32) (ring->prod - ring->cons) <= |
363 | ring->size - HEADROOM - MAX_DESC_TXBBS) { | |
c27a02cd | 364 | ring->blocked = 0; |
f813cad8 | 365 | netif_tx_wake_queue(netdev_get_tx_queue(dev, cq->ring)); |
c27a02cd YP |
366 | priv->port_stats.wake_queue++; |
367 | } | |
368 | } | |
369 | } | |
370 | ||
371 | void mlx4_en_tx_irq(struct mlx4_cq *mcq) | |
372 | { | |
373 | struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); | |
374 | struct mlx4_en_priv *priv = netdev_priv(cq->dev); | |
375 | struct mlx4_en_tx_ring *ring = &priv->tx_ring[cq->ring]; | |
376 | ||
48374ddc YP |
377 | if (!spin_trylock(&ring->comp_lock)) |
378 | return; | |
c27a02cd | 379 | mlx4_en_process_tx_cq(cq->dev, cq); |
48374ddc YP |
380 | mod_timer(&cq->timer, jiffies + 1); |
381 | spin_unlock(&ring->comp_lock); | |
c27a02cd YP |
382 | } |
383 | ||
384 | ||
385 | void mlx4_en_poll_tx_cq(unsigned long data) | |
386 | { | |
387 | struct mlx4_en_cq *cq = (struct mlx4_en_cq *) data; | |
388 | struct mlx4_en_priv *priv = netdev_priv(cq->dev); | |
389 | struct mlx4_en_tx_ring *ring = &priv->tx_ring[cq->ring]; | |
390 | u32 inflight; | |
391 | ||
392 | INC_PERF_COUNTER(priv->pstats.tx_poll); | |
393 | ||
465440d2 | 394 | if (!spin_trylock_irq(&ring->comp_lock)) { |
48374ddc YP |
395 | mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT); |
396 | return; | |
397 | } | |
c27a02cd YP |
398 | mlx4_en_process_tx_cq(cq->dev, cq); |
399 | inflight = (u32) (ring->prod - ring->cons - ring->last_nr_txbb); | |
400 | ||
401 | /* If there are still packets in flight and the timer has not already | |
402 | * been scheduled by the Tx routine then schedule it here to guarantee | |
403 | * completion processing of these packets */ | |
404 | if (inflight && priv->port_up) | |
405 | mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT); | |
406 | ||
465440d2 | 407 | spin_unlock_irq(&ring->comp_lock); |
c27a02cd YP |
408 | } |
409 | ||
410 | static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv, | |
411 | struct mlx4_en_tx_ring *ring, | |
412 | u32 index, | |
413 | unsigned int desc_size) | |
414 | { | |
415 | u32 copy = (ring->size - index) * TXBB_SIZE; | |
416 | int i; | |
417 | ||
418 | for (i = desc_size - copy - 4; i >= 0; i -= 4) { | |
419 | if ((i & (TXBB_SIZE - 1)) == 0) | |
420 | wmb(); | |
421 | ||
422 | *((u32 *) (ring->buf + i)) = | |
423 | *((u32 *) (ring->bounce_buf + copy + i)); | |
424 | } | |
425 | ||
426 | for (i = copy - 4; i >= 4 ; i -= 4) { | |
427 | if ((i & (TXBB_SIZE - 1)) == 0) | |
428 | wmb(); | |
429 | ||
430 | *((u32 *) (ring->buf + index * TXBB_SIZE + i)) = | |
431 | *((u32 *) (ring->bounce_buf + i)); | |
432 | } | |
433 | ||
434 | /* Return real descriptor location */ | |
435 | return ring->buf + index * TXBB_SIZE; | |
436 | } | |
437 | ||
438 | static inline void mlx4_en_xmit_poll(struct mlx4_en_priv *priv, int tx_ind) | |
439 | { | |
440 | struct mlx4_en_cq *cq = &priv->tx_cq[tx_ind]; | |
441 | struct mlx4_en_tx_ring *ring = &priv->tx_ring[tx_ind]; | |
4871953c | 442 | unsigned long flags; |
c27a02cd YP |
443 | |
444 | /* If we don't have a pending timer, set one up to catch our recent | |
445 | post in case the interface becomes idle */ | |
446 | if (!timer_pending(&cq->timer)) | |
447 | mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT); | |
448 | ||
449 | /* Poll the CQ every mlx4_en_TX_MODER_POLL packets */ | |
450 | if ((++ring->poll_cnt & (MLX4_EN_TX_POLL_MODER - 1)) == 0) | |
4871953c | 451 | if (spin_trylock_irqsave(&ring->comp_lock, flags)) { |
48374ddc | 452 | mlx4_en_process_tx_cq(priv->dev, cq); |
4871953c | 453 | spin_unlock_irqrestore(&ring->comp_lock, flags); |
48374ddc | 454 | } |
c27a02cd YP |
455 | } |
456 | ||
457 | static void *get_frag_ptr(struct sk_buff *skb) | |
458 | { | |
459 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; | |
460 | struct page *page = frag->page; | |
461 | void *ptr; | |
462 | ||
463 | ptr = page_address(page); | |
464 | if (unlikely(!ptr)) | |
465 | return NULL; | |
466 | ||
467 | return ptr + frag->page_offset; | |
468 | } | |
469 | ||
470 | static int is_inline(struct sk_buff *skb, void **pfrag) | |
471 | { | |
472 | void *ptr; | |
473 | ||
474 | if (inline_thold && !skb_is_gso(skb) && skb->len <= inline_thold) { | |
475 | if (skb_shinfo(skb)->nr_frags == 1) { | |
476 | ptr = get_frag_ptr(skb); | |
477 | if (unlikely(!ptr)) | |
478 | return 0; | |
479 | ||
480 | if (pfrag) | |
481 | *pfrag = ptr; | |
482 | ||
483 | return 1; | |
484 | } else if (unlikely(skb_shinfo(skb)->nr_frags)) | |
485 | return 0; | |
486 | else | |
487 | return 1; | |
488 | } | |
489 | ||
490 | return 0; | |
491 | } | |
492 | ||
493 | static int inline_size(struct sk_buff *skb) | |
494 | { | |
495 | if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg) | |
496 | <= MLX4_INLINE_ALIGN) | |
497 | return ALIGN(skb->len + CTRL_SIZE + | |
498 | sizeof(struct mlx4_wqe_inline_seg), 16); | |
499 | else | |
500 | return ALIGN(skb->len + CTRL_SIZE + 2 * | |
501 | sizeof(struct mlx4_wqe_inline_seg), 16); | |
502 | } | |
503 | ||
504 | static int get_real_size(struct sk_buff *skb, struct net_device *dev, | |
505 | int *lso_header_size) | |
506 | { | |
507 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
c27a02cd YP |
508 | int real_size; |
509 | ||
510 | if (skb_is_gso(skb)) { | |
511 | *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
512 | real_size = CTRL_SIZE + skb_shinfo(skb)->nr_frags * DS_SIZE + | |
513 | ALIGN(*lso_header_size + 4, DS_SIZE); | |
514 | if (unlikely(*lso_header_size != skb_headlen(skb))) { | |
515 | /* We add a segment for the skb linear buffer only if | |
516 | * it contains data */ | |
517 | if (*lso_header_size < skb_headlen(skb)) | |
518 | real_size += DS_SIZE; | |
519 | else { | |
520 | if (netif_msg_tx_err(priv)) | |
453a6082 | 521 | en_warn(priv, "Non-linear headers\n"); |
c27a02cd YP |
522 | return 0; |
523 | } | |
524 | } | |
c27a02cd YP |
525 | } else { |
526 | *lso_header_size = 0; | |
527 | if (!is_inline(skb, NULL)) | |
528 | real_size = CTRL_SIZE + (skb_shinfo(skb)->nr_frags + 1) * DS_SIZE; | |
529 | else | |
530 | real_size = inline_size(skb); | |
531 | } | |
532 | ||
533 | return real_size; | |
534 | } | |
535 | ||
536 | static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, struct sk_buff *skb, | |
537 | int real_size, u16 *vlan_tag, int tx_ind, void *fragptr) | |
538 | { | |
539 | struct mlx4_wqe_inline_seg *inl = &tx_desc->inl; | |
540 | int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl; | |
541 | ||
542 | if (skb->len <= spc) { | |
543 | inl->byte_count = cpu_to_be32(1 << 31 | skb->len); | |
544 | skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb)); | |
545 | if (skb_shinfo(skb)->nr_frags) | |
546 | memcpy(((void *)(inl + 1)) + skb_headlen(skb), fragptr, | |
547 | skb_shinfo(skb)->frags[0].size); | |
548 | ||
549 | } else { | |
550 | inl->byte_count = cpu_to_be32(1 << 31 | spc); | |
551 | if (skb_headlen(skb) <= spc) { | |
552 | skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb)); | |
553 | if (skb_headlen(skb) < spc) { | |
554 | memcpy(((void *)(inl + 1)) + skb_headlen(skb), | |
555 | fragptr, spc - skb_headlen(skb)); | |
556 | fragptr += spc - skb_headlen(skb); | |
557 | } | |
558 | inl = (void *) (inl + 1) + spc; | |
559 | memcpy(((void *)(inl + 1)), fragptr, skb->len - spc); | |
560 | } else { | |
561 | skb_copy_from_linear_data(skb, inl + 1, spc); | |
562 | inl = (void *) (inl + 1) + spc; | |
563 | skb_copy_from_linear_data_offset(skb, spc, inl + 1, | |
564 | skb_headlen(skb) - spc); | |
565 | if (skb_shinfo(skb)->nr_frags) | |
566 | memcpy(((void *)(inl + 1)) + skb_headlen(skb) - spc, | |
567 | fragptr, skb_shinfo(skb)->frags[0].size); | |
568 | } | |
569 | ||
570 | wmb(); | |
571 | inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc)); | |
572 | } | |
573 | tx_desc->ctrl.vlan_tag = cpu_to_be16(*vlan_tag); | |
574 | tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN * !!(*vlan_tag); | |
575 | tx_desc->ctrl.fence_size = (real_size / 16) & 0x3f; | |
576 | } | |
577 | ||
f813cad8 | 578 | u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb) |
c27a02cd | 579 | { |
f813cad8 YP |
580 | struct mlx4_en_priv *priv = netdev_priv(dev); |
581 | u16 vlan_tag = 0; | |
c27a02cd | 582 | |
f813cad8 YP |
583 | /* If we support per priority flow control and the packet contains |
584 | * a vlan tag, send the packet to the TX ring assigned to that priority | |
585 | */ | |
eab6d18d | 586 | if (priv->prof->rx_ppp && vlan_tx_tag_present(skb)) { |
f813cad8 YP |
587 | vlan_tag = vlan_tx_tag_get(skb); |
588 | return MLX4_EN_NUM_TX_RINGS + (vlan_tag >> 13); | |
c27a02cd | 589 | } |
f813cad8 YP |
590 | |
591 | return skb_tx_hash(dev, skb); | |
c27a02cd YP |
592 | } |
593 | ||
61357325 | 594 | netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev) |
c27a02cd YP |
595 | { |
596 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
597 | struct mlx4_en_dev *mdev = priv->mdev; | |
598 | struct mlx4_en_tx_ring *ring; | |
599 | struct mlx4_en_cq *cq; | |
600 | struct mlx4_en_tx_desc *tx_desc; | |
601 | struct mlx4_wqe_data_seg *data; | |
602 | struct skb_frag_struct *frag; | |
603 | struct mlx4_en_tx_info *tx_info; | |
e7c1c2c4 YP |
604 | struct ethhdr *ethh; |
605 | u64 mac; | |
606 | u32 mac_l, mac_h; | |
c27a02cd YP |
607 | int tx_ind = 0; |
608 | int nr_txbb; | |
609 | int desc_size; | |
610 | int real_size; | |
611 | dma_addr_t dma; | |
612 | u32 index; | |
613 | __be32 op_own; | |
f813cad8 | 614 | u16 vlan_tag = 0; |
c27a02cd YP |
615 | int i; |
616 | int lso_header_size; | |
617 | void *fragptr; | |
618 | ||
3005ad40 YP |
619 | if (!priv->port_up) |
620 | goto tx_drop; | |
621 | ||
c27a02cd YP |
622 | real_size = get_real_size(skb, dev, &lso_header_size); |
623 | if (unlikely(!real_size)) | |
7e230913 | 624 | goto tx_drop; |
c27a02cd YP |
625 | |
626 | /* Allign descriptor to TXBB size */ | |
627 | desc_size = ALIGN(real_size, TXBB_SIZE); | |
628 | nr_txbb = desc_size / TXBB_SIZE; | |
629 | if (unlikely(nr_txbb > MAX_DESC_TXBBS)) { | |
630 | if (netif_msg_tx_err(priv)) | |
453a6082 | 631 | en_warn(priv, "Oversized header or SG list\n"); |
7e230913 | 632 | goto tx_drop; |
c27a02cd YP |
633 | } |
634 | ||
f813cad8 | 635 | tx_ind = skb->queue_mapping; |
c27a02cd | 636 | ring = &priv->tx_ring[tx_ind]; |
eab6d18d | 637 | if (vlan_tx_tag_present(skb)) |
f813cad8 | 638 | vlan_tag = vlan_tx_tag_get(skb); |
c27a02cd YP |
639 | |
640 | /* Check available TXBBs And 2K spare for prefetch */ | |
641 | if (unlikely(((int)(ring->prod - ring->cons)) > | |
642 | ring->size - HEADROOM - MAX_DESC_TXBBS)) { | |
f813cad8 YP |
643 | /* every full Tx ring stops queue */ |
644 | netif_tx_stop_queue(netdev_get_tx_queue(dev, tx_ind)); | |
c27a02cd YP |
645 | ring->blocked = 1; |
646 | priv->port_stats.queue_stopped++; | |
647 | ||
648 | /* Use interrupts to find out when queue opened */ | |
649 | cq = &priv->tx_cq[tx_ind]; | |
650 | mlx4_en_arm_cq(priv, cq); | |
651 | return NETDEV_TX_BUSY; | |
652 | } | |
653 | ||
c27a02cd YP |
654 | /* Track current inflight packets for performance analysis */ |
655 | AVG_PERF_COUNTER(priv->pstats.inflight_avg, | |
656 | (u32) (ring->prod - ring->cons - 1)); | |
657 | ||
658 | /* Packet is good - grab an index and transmit it */ | |
659 | index = ring->prod & ring->size_mask; | |
660 | ||
661 | /* See if we have enough space for whole descriptor TXBB for setting | |
662 | * SW ownership on next descriptor; if not, use a bounce buffer. */ | |
663 | if (likely(index + nr_txbb <= ring->size)) | |
664 | tx_desc = ring->buf + index * TXBB_SIZE; | |
665 | else | |
666 | tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf; | |
667 | ||
668 | /* Save skb in tx_info ring */ | |
669 | tx_info = &ring->tx_info[index]; | |
670 | tx_info->skb = skb; | |
671 | tx_info->nr_txbb = nr_txbb; | |
672 | ||
673 | /* Prepare ctrl segement apart opcode+ownership, which depends on | |
674 | * whether LSO is used */ | |
675 | tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag); | |
676 | tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN * !!vlan_tag; | |
677 | tx_desc->ctrl.fence_size = (real_size / 16) & 0x3f; | |
678 | tx_desc->ctrl.srcrb_flags = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE | | |
679 | MLX4_WQE_CTRL_SOLICITED); | |
680 | if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { | |
681 | tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | | |
682 | MLX4_WQE_CTRL_TCP_UDP_CSUM); | |
683 | priv->port_stats.tx_chksum_offload++; | |
684 | } | |
685 | ||
e7c1c2c4 YP |
686 | if (unlikely(priv->validate_loopback)) { |
687 | /* Copy dst mac address to wqe */ | |
688 | skb_reset_mac_header(skb); | |
689 | ethh = eth_hdr(skb); | |
690 | if (ethh && ethh->h_dest) { | |
691 | mac = mlx4_en_mac_to_u64(ethh->h_dest); | |
692 | mac_h = (u32) ((mac & 0xffff00000000ULL) >> 16); | |
693 | mac_l = (u32) (mac & 0xffffffff); | |
694 | tx_desc->ctrl.srcrb_flags |= cpu_to_be32(mac_h); | |
695 | tx_desc->ctrl.imm = cpu_to_be32(mac_l); | |
696 | } | |
697 | } | |
698 | ||
c27a02cd YP |
699 | /* Handle LSO (TSO) packets */ |
700 | if (lso_header_size) { | |
701 | /* Mark opcode as LSO */ | |
702 | op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) | | |
703 | ((ring->prod & ring->size) ? | |
704 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); | |
705 | ||
706 | /* Fill in the LSO prefix */ | |
707 | tx_desc->lso.mss_hdr_size = cpu_to_be32( | |
708 | skb_shinfo(skb)->gso_size << 16 | lso_header_size); | |
709 | ||
710 | /* Copy headers; | |
711 | * note that we already verified that it is linear */ | |
712 | memcpy(tx_desc->lso.header, skb->data, lso_header_size); | |
713 | data = ((void *) &tx_desc->lso + | |
714 | ALIGN(lso_header_size + 4, DS_SIZE)); | |
715 | ||
716 | priv->port_stats.tso_packets++; | |
717 | i = ((skb->len - lso_header_size) / skb_shinfo(skb)->gso_size) + | |
718 | !!((skb->len - lso_header_size) % skb_shinfo(skb)->gso_size); | |
719 | ring->bytes += skb->len + (i - 1) * lso_header_size; | |
720 | ring->packets += i; | |
721 | } else { | |
722 | /* Normal (Non LSO) packet */ | |
723 | op_own = cpu_to_be32(MLX4_OPCODE_SEND) | | |
724 | ((ring->prod & ring->size) ? | |
725 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); | |
726 | data = &tx_desc->data; | |
727 | ring->bytes += max(skb->len, (unsigned int) ETH_ZLEN); | |
728 | ring->packets++; | |
729 | ||
730 | } | |
731 | AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len); | |
732 | ||
733 | ||
734 | /* valid only for none inline segments */ | |
735 | tx_info->data_offset = (void *) data - (void *) tx_desc; | |
736 | ||
737 | tx_info->linear = (lso_header_size < skb_headlen(skb) && !is_inline(skb, NULL)) ? 1 : 0; | |
738 | data += skb_shinfo(skb)->nr_frags + tx_info->linear - 1; | |
739 | ||
740 | if (!is_inline(skb, &fragptr)) { | |
741 | /* Map fragments */ | |
742 | for (i = skb_shinfo(skb)->nr_frags - 1; i >= 0; i--) { | |
743 | frag = &skb_shinfo(skb)->frags[i]; | |
744 | dma = pci_map_page(mdev->dev->pdev, frag->page, frag->page_offset, | |
745 | frag->size, PCI_DMA_TODEVICE); | |
746 | data->addr = cpu_to_be64(dma); | |
747 | data->lkey = cpu_to_be32(mdev->mr.key); | |
748 | wmb(); | |
749 | data->byte_count = cpu_to_be32(frag->size); | |
750 | --data; | |
751 | } | |
752 | ||
753 | /* Map linear part */ | |
754 | if (tx_info->linear) { | |
755 | dma = pci_map_single(mdev->dev->pdev, skb->data + lso_header_size, | |
756 | skb_headlen(skb) - lso_header_size, PCI_DMA_TODEVICE); | |
757 | data->addr = cpu_to_be64(dma); | |
758 | data->lkey = cpu_to_be32(mdev->mr.key); | |
759 | wmb(); | |
760 | data->byte_count = cpu_to_be32(skb_headlen(skb) - lso_header_size); | |
761 | } | |
41efea5a YP |
762 | tx_info->inl = 0; |
763 | } else { | |
c27a02cd | 764 | build_inline_wqe(tx_desc, skb, real_size, &vlan_tag, tx_ind, fragptr); |
41efea5a YP |
765 | tx_info->inl = 1; |
766 | } | |
c27a02cd YP |
767 | |
768 | ring->prod += nr_txbb; | |
769 | ||
770 | /* If we used a bounce buffer then copy descriptor back into place */ | |
771 | if (tx_desc == (struct mlx4_en_tx_desc *) ring->bounce_buf) | |
772 | tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size); | |
773 | ||
774 | /* Run destructor before passing skb to HW */ | |
775 | if (likely(!skb_shared(skb))) | |
776 | skb_orphan(skb); | |
777 | ||
778 | /* Ensure new descirptor hits memory | |
779 | * before setting ownership of this descriptor to HW */ | |
780 | wmb(); | |
781 | tx_desc->ctrl.owner_opcode = op_own; | |
782 | ||
783 | /* Ring doorbell! */ | |
784 | wmb(); | |
785 | writel(ring->doorbell_qpn, mdev->uar_map + MLX4_SEND_DOORBELL); | |
c27a02cd YP |
786 | |
787 | /* Poll CQ here */ | |
788 | mlx4_en_xmit_poll(priv, tx_ind); | |
789 | ||
ec634fe3 | 790 | return NETDEV_TX_OK; |
7e230913 YP |
791 | |
792 | tx_drop: | |
793 | dev_kfree_skb_any(skb); | |
794 | priv->stats.tx_dropped++; | |
795 | return NETDEV_TX_OK; | |
c27a02cd YP |
796 | } |
797 |