[deliverable/linux.git] / drivers / net / mlx4 / mlx4.h

/*
 * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
 * Copyright (c) 2005, 2006, 2007 Cisco Systems.  All rights reserved.
 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef MLX4_H
#define MLX4_H

#include <linux/mutex.h>
#include <linux/radix-tree.h>
#include <linux/timer.h>
#include <linux/semaphore.h>
#include <linux/workqueue.h>

#include <linux/mlx4/device.h>
#include <linux/mlx4/driver.h>
#include <linux/mlx4/doorbell.h>

#define DRV_NAME	"mlx4_core"
#define DRV_VERSION	"0.01"
#define DRV_RELDATE	"May 1, 2007"

enum {
	MLX4_HCR_BASE		= 0x80680,
	MLX4_HCR_SIZE		= 0x0001c,
	MLX4_CLR_INT_SIZE	= 0x00008
};

enum {
	MLX4_MGM_ENTRY_SIZE	=  0x100,
	MLX4_QP_PER_MGM		= 4 * (MLX4_MGM_ENTRY_SIZE / 16 - 2),
	MLX4_MTT_ENTRY_PER_SEG	= 8
};

enum {
	MLX4_NUM_PDS		= 1 << 15
};

enum {
	MLX4_CMPT_TYPE_QP	= 0,
	MLX4_CMPT_TYPE_SRQ	= 1,
	MLX4_CMPT_TYPE_CQ	= 2,
	MLX4_CMPT_TYPE_EQ	= 3,
	MLX4_CMPT_NUM_TYPE
};

enum {
	MLX4_CMPT_SHIFT		= 24,
	MLX4_NUM_CMPTS		= MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
};

#ifdef CONFIG_MLX4_DEBUG
extern int mlx4_debug_level;
#else /* CONFIG_MLX4_DEBUG */
#define mlx4_debug_level	(0)
#endif /* CONFIG_MLX4_DEBUG */

#define mlx4_dbg(mdev, format, arg...)					\
do {									\
	if (mlx4_debug_level)						\
		dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
} while (0)

#define mlx4_err(mdev, format, arg...) \
	dev_err(&mdev->pdev->dev, format, ##arg)
#define mlx4_info(mdev, format, arg...) \
	dev_info(&mdev->pdev->dev, format, ##arg)
#define mlx4_warn(mdev, format, arg...) \
	dev_warn(&mdev->pdev->dev, format, ##arg)

struct mlx4_bitmap {
	u32			last;
	u32			top;
	u32			max;
	u32                     reserved_top;
	u32			mask;
	spinlock_t		lock;
	unsigned long	       *table;
};

struct mlx4_buddy {
	unsigned long	      **bits;
	unsigned int	       *num_free;
	int			max_order;
	spinlock_t		lock;
};

struct mlx4_icm;

struct mlx4_icm_table {
	u64			virt;
	int			num_icm;
	int			num_obj;
	int			obj_size;
	int			lowmem;
	int			coherent;
	struct mutex		mutex;
	struct mlx4_icm	      **icm;
};

struct mlx4_eq {
	struct mlx4_dev	       *dev;
	void __iomem	       *doorbell;
	int			eqn;
	u32			cons_index;
	u16			irq;
	u16			have_irq;
	int			nent;
	struct mlx4_buf_list   *page_list;
	struct mlx4_mtt		mtt;
};

struct mlx4_profile {
	int			num_qp;
	int			rdmarc_per_qp;
	int			num_srq;
	int			num_cq;
	int			num_mcg;
	int			num_mpt;
	int			num_mtt;
};

struct mlx4_fw {
	u64			clr_int_base;
	u64			catas_offset;
	struct mlx4_icm	       *fw_icm;
	struct mlx4_icm	       *aux_icm;
	u32			catas_size;
	u16			fw_pages;
	u8			clr_int_bar;
	u8			catas_bar;
};

#define MGM_QPN_MASK       0x00FFFFFF
#define MGM_BLCK_LB_BIT    30

struct mlx4_promisc_qp {
	struct list_head list;
	u32 qpn;
};

struct mlx4_steer_index {
	struct list_head list;
	unsigned int index;
	struct list_head duplicates;
};

struct mlx4_mgm {
	__be32			next_gid_index;
	__be32			members_count;
	u32			reserved[2];
	u8			gid[16];
	__be32			qp[MLX4_QP_PER_MGM];
};
struct mlx4_cmd {
	struct pci_pool	       *pool;
	void __iomem	       *hcr;
	struct mutex		hcr_mutex;
	struct semaphore	poll_sem;
	struct semaphore	event_sem;
	int			max_cmds;
	spinlock_t		context_lock;
	int			free_head;
	struct mlx4_cmd_context *context;
	u16			token_mask;
	u8			use_events;
	u8			toggle;
};

struct mlx4_uar_table {
	struct mlx4_bitmap	bitmap;
};

struct mlx4_mr_table {
	struct mlx4_bitmap	mpt_bitmap;
	struct mlx4_buddy	mtt_buddy;
	u64			mtt_base;
	u64			mpt_base;
	struct mlx4_icm_table	mtt_table;
	struct mlx4_icm_table	dmpt_table;
};

struct mlx4_cq_table {
	struct mlx4_bitmap	bitmap;
	spinlock_t		lock;
	struct radix_tree_root	tree;
	struct mlx4_icm_table	table;
	struct mlx4_icm_table	cmpt_table;
};

struct mlx4_eq_table {
	struct mlx4_bitmap	bitmap;
	char		       *irq_names;
	void __iomem	       *clr_int;
	void __iomem	      **uar_map;
	u32			clr_mask;
	struct mlx4_eq	       *eq;
	struct mlx4_icm_table	table;
	struct mlx4_icm_table	cmpt_table;
	int			have_irq;
	u8			inta_pin;
};

struct mlx4_srq_table {
	struct mlx4_bitmap	bitmap;
	spinlock_t		lock;
	struct radix_tree_root	tree;
	struct mlx4_icm_table	table;
	struct mlx4_icm_table	cmpt_table;
};

struct mlx4_qp_table {
	struct mlx4_bitmap	bitmap;
	u32			rdmarc_base;
	int			rdmarc_shift;
	spinlock_t		lock;
	struct mlx4_icm_table	qp_table;
	struct mlx4_icm_table	auxc_table;
	struct mlx4_icm_table	altc_table;
	struct mlx4_icm_table	rdmarc_table;
	struct mlx4_icm_table	cmpt_table;
};

struct mlx4_mcg_table {
	struct mutex		mutex;
	struct mlx4_bitmap	bitmap;
	struct mlx4_icm_table	table;
};

struct mlx4_catas_err {
	u32 __iomem	       *map;
	struct timer_list	timer;
	struct list_head	list;
};

#define MLX4_MAX_MAC_NUM	128
#define MLX4_MAC_TABLE_SIZE	(MLX4_MAX_MAC_NUM << 3)

struct mlx4_mac_table {
	__be64			entries[MLX4_MAX_MAC_NUM];
	int			refs[MLX4_MAX_MAC_NUM];
	struct mutex		mutex;
	int			total;
	int			max;
};

#define MLX4_MAX_VLAN_NUM	128
#define MLX4_VLAN_TABLE_SIZE	(MLX4_MAX_VLAN_NUM << 2)

struct mlx4_vlan_table {
	__be32			entries[MLX4_MAX_VLAN_NUM];
	int			refs[MLX4_MAX_VLAN_NUM];
	struct mutex		mutex;
	int			total;
	int			max;
};

struct mlx4_mac_entry {
	u64 mac;
};

struct mlx4_port_info {
	struct mlx4_dev	       *dev;
	int			port;
	char			dev_name[16];
	struct device_attribute port_attr;
	enum mlx4_port_type	tmp_type;
	struct mlx4_mac_table	mac_table;
	struct radix_tree_root	mac_tree;
	struct mlx4_vlan_table	vlan_table;
	int			base_qpn;
};

struct mlx4_sense {
	struct mlx4_dev		*dev;
	u8			do_sense_port[MLX4_MAX_PORTS + 1];
	u8			sense_allowed[MLX4_MAX_PORTS + 1];
	struct delayed_work	sense_poll;
};

struct mlx4_msix_ctl {
	u64		pool_bm;
	spinlock_t	pool_lock;
};

struct mlx4_steer {
	struct list_head promisc_qps[MLX4_NUM_STEERS];
	struct list_head steer_entries[MLX4_NUM_STEERS];
	struct list_head high_prios;
};

struct mlx4_priv {
	struct mlx4_dev		dev;

	struct list_head	dev_list;
	struct list_head	ctx_list;
	spinlock_t		ctx_lock;

	struct list_head        pgdir_list;
	struct mutex            pgdir_mutex;

	struct mlx4_fw		fw;
	struct mlx4_cmd		cmd;

	struct mlx4_bitmap	pd_bitmap;
	struct mlx4_uar_table	uar_table;
	struct mlx4_mr_table	mr_table;
	struct mlx4_cq_table	cq_table;
	struct mlx4_eq_table	eq_table;
	struct mlx4_srq_table	srq_table;
	struct mlx4_qp_table	qp_table;
	struct mlx4_mcg_table	mcg_table;

	struct mlx4_catas_err	catas_err;

	void __iomem	       *clr_base;

	struct mlx4_uar		driver_uar;
	void __iomem	       *kar;
	struct mlx4_port_info	port[MLX4_MAX_PORTS + 1];
	struct mlx4_sense       sense;
	struct mutex		port_mutex;
	struct mlx4_msix_ctl	msix_ctl;
	struct mlx4_steer	*steer;
};

static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
{
	return container_of(dev, struct mlx4_priv, dev);
}

#define MLX4_SENSE_RANGE	(HZ * 3)

extern struct workqueue_struct *mlx4_wq;

u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
		     u32 reserved_bot, u32 resetrved_top);
void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);

int mlx4_reset(struct mlx4_dev *dev);

int mlx4_alloc_eq_table(struct mlx4_dev *dev);
void mlx4_free_eq_table(struct mlx4_dev *dev);

int mlx4_init_pd_table(struct mlx4_dev *dev);
int mlx4_init_uar_table(struct mlx4_dev *dev);
int mlx4_init_mr_table(struct mlx4_dev *dev);
int mlx4_init_eq_table(struct mlx4_dev *dev);
int mlx4_init_cq_table(struct mlx4_dev *dev);
int mlx4_init_qp_table(struct mlx4_dev *dev);
int mlx4_init_srq_table(struct mlx4_dev *dev);
int mlx4_init_mcg_table(struct mlx4_dev *dev);

void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);

void mlx4_start_catas_poll(struct mlx4_dev *dev);
void mlx4_stop_catas_poll(struct mlx4_dev *dev);
void mlx4_catas_init(void);
int mlx4_restart_one(struct pci_dev *pdev);
int mlx4_register_device(struct mlx4_dev *dev);
void mlx4_unregister_device(struct mlx4_dev *dev);
void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, int port);

struct mlx4_dev_cap;
struct mlx4_init_hca_param;

u64 mlx4_make_profile(struct mlx4_dev *dev,
		      struct mlx4_profile *request,
		      struct mlx4_dev_cap *dev_cap,
		      struct mlx4_init_hca_param *init_hca);

int mlx4_cmd_init(struct mlx4_dev *dev);
void mlx4_cmd_cleanup(struct mlx4_dev *dev);
void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
int mlx4_cmd_use_events(struct mlx4_dev *dev);
void mlx4_cmd_use_polling(struct mlx4_dev *dev);

void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);

void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);

void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);

void mlx4_handle_catas_err(struct mlx4_dev *dev);

void mlx4_do_sense_ports(struct mlx4_dev *dev,
			 enum mlx4_port_type *stype,
			 enum mlx4_port_type *defaults);
void mlx4_start_sense(struct mlx4_dev *dev);
void mlx4_stop_sense(struct mlx4_dev *dev);
void mlx4_sense_init(struct mlx4_dev *dev);
int mlx4_check_port_params(struct mlx4_dev *dev,
			   enum mlx4_port_type *port_type);
int mlx4_change_port_types(struct mlx4_dev *dev,
			   enum mlx4_port_type *port_types);

void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);

int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port);
int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);

int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
			  enum mlx4_protocol prot, enum mlx4_steer_type steer);
int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
			  int block_mcast_loopback, enum mlx4_protocol prot,
			  enum mlx4_steer_type steer);
#endif /* MLX4_H */
Commit	Line	Data
225c7b1f RD	1	/*
	2	* Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
	3	* Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
	4	* Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
51a379d0	5	* Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f RD	6	* Copyright (c) 2004 Voltaire, Inc. All rights reserved.
	7	*
	8	* This software is available to you under a choice of one of two
	9	* licenses. You may choose to be licensed under the terms of the GNU
	10	* General Public License (GPL) Version 2, available from the file
	11	* COPYING in the main directory of this source tree, or the
	12	* OpenIB.org BSD license below:
	13	*
	14	* Redistribution and use in source and binary forms, with or
	15	* without modification, are permitted provided that the following
	16	* conditions are met:
	17	*
	18	* - Redistributions of source code must retain the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer.
	21	*
	22	* - Redistributions in binary form must reproduce the above
	23	* copyright notice, this list of conditions and the following
	24	* disclaimer in the documentation and/or other materials
	25	* provided with the distribution.
	26	*
	27	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	28	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	29	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	30	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	31	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	32	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	33	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	34	* SOFTWARE.
	35	*/
	36
	37	#ifndef MLX4_H
	38	#define MLX4_H
	39
525f5f44	40	#include <linux/mutex.h>
225c7b1f	41	#include <linux/radix-tree.h>
ee49bd93	42	#include <linux/timer.h>
3142788b	43	#include <linux/semaphore.h>
27bf91d6	44	#include <linux/workqueue.h>
225c7b1f RD	45
225c7b1f RD	46	#include <linux/mlx4/device.h>
37608eea	47	#include <linux/mlx4/driver.h>
225c7b1f RD	48	#include <linux/mlx4/doorbell.h>
	49
	50	#define DRV_NAME "mlx4_core"
225c7b1f RD	51	#define DRV_VERSION "0.01"
	52	#define DRV_RELDATE "May 1, 2007"
	53
	54	enum {
	55	MLX4_HCR_BASE = 0x80680,
	56	MLX4_HCR_SIZE = 0x0001c,
	57	MLX4_CLR_INT_SIZE = 0x00008
	58	};
	59
225c7b1f	60	enum {
e57ac0c2	61	MLX4_MGM_ENTRY_SIZE = 0x100,
225c7b1f RD	62	MLX4_QP_PER_MGM = 4 * (MLX4_MGM_ENTRY_SIZE / 16 - 2),
	63	MLX4_MTT_ENTRY_PER_SEG = 8
	64	};
	65
225c7b1f RD	66	enum {
	67	MLX4_NUM_PDS = 1 << 15
	68	};
	69
	70	enum {
	71	MLX4_CMPT_TYPE_QP = 0,
	72	MLX4_CMPT_TYPE_SRQ = 1,
	73	MLX4_CMPT_TYPE_CQ = 2,
	74	MLX4_CMPT_TYPE_EQ = 3,
	75	MLX4_CMPT_NUM_TYPE
	76	};
	77
	78	enum {
	79	MLX4_CMPT_SHIFT = 24,
	80	MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
	81	};
	82
	83	#ifdef CONFIG_MLX4_DEBUG
	84	extern int mlx4_debug_level;
7b0f5df4 RD	85	#else /* CONFIG_MLX4_DEBUG */
	86	#define mlx4_debug_level (0)
	87	#endif /* CONFIG_MLX4_DEBUG */
225c7b1f RD	88
225c7b1f RD	89	#define mlx4_dbg(mdev, format, arg...) \
0a645e80 JP	90	do { \
	91	if (mlx4_debug_level) \
	92	dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
	93	} while (0)
225c7b1f	94
225c7b1f	95	#define mlx4_err(mdev, format, arg...) \
0a645e80	96	dev_err(&mdev->pdev->dev, format, ##arg)
225c7b1f	97	#define mlx4_info(mdev, format, arg...) \
0a645e80	98	dev_info(&mdev->pdev->dev, format, ##arg)
225c7b1f	99	#define mlx4_warn(mdev, format, arg...) \
0a645e80	100	dev_warn(&mdev->pdev->dev, format, ##arg)
225c7b1f RD	101
	102	struct mlx4_bitmap {
	103	u32 last;
	104	u32 top;
	105	u32 max;
93fc9e1b	106	u32 reserved_top;
225c7b1f RD	107	u32 mask;
	108	spinlock_t lock;
	109	unsigned long *table;
	110	};
	111
	112	struct mlx4_buddy {
	113	unsigned long **bits;
e4044cfc	114	unsigned int *num_free;
225c7b1f RD	115	int max_order;
	116	spinlock_t lock;
	117	};
	118
	119	struct mlx4_icm;
	120
	121	struct mlx4_icm_table {
	122	u64 virt;
	123	int num_icm;
	124	int num_obj;
	125	int obj_size;
	126	int lowmem;
5b0bf5e2	127	int coherent;
225c7b1f RD	128	struct mutex mutex;
	129	struct mlx4_icm **icm;
	130	};
	131
	132	struct mlx4_eq {
	133	struct mlx4_dev *dev;
	134	void __iomem *doorbell;
	135	int eqn;
	136	u32 cons_index;
	137	u16 irq;
	138	u16 have_irq;
	139	int nent;
	140	struct mlx4_buf_list *page_list;
	141	struct mlx4_mtt mtt;
	142	};
	143
	144	struct mlx4_profile {
	145	int num_qp;
	146	int rdmarc_per_qp;
	147	int num_srq;
	148	int num_cq;
	149	int num_mcg;
	150	int num_mpt;
	151	int num_mtt;
	152	};
	153
	154	struct mlx4_fw {
	155	u64 clr_int_base;
	156	u64 catas_offset;
	157	struct mlx4_icm *fw_icm;
	158	struct mlx4_icm *aux_icm;
	159	u32 catas_size;
	160	u16 fw_pages;
	161	u8 clr_int_bar;
	162	u8 catas_bar;
	163	};
	164
b12d93d6 YP	165	#define MGM_QPN_MASK 0x00FFFFFF
	166	#define MGM_BLCK_LB_BIT 30
	167
	168	struct mlx4_promisc_qp {
	169	struct list_head list;
	170	u32 qpn;
	171	};
	172
	173	struct mlx4_steer_index {
	174	struct list_head list;
	175	unsigned int index;
	176	struct list_head duplicates;
	177	};
	178
	179	struct mlx4_mgm {
	180	__be32 next_gid_index;
	181	__be32 members_count;
	182	u32 reserved[2];
	183	u8 gid[16];
	184	__be32 qp[MLX4_QP_PER_MGM];
	185	};
225c7b1f RD	186	struct mlx4_cmd {
	187	struct pci_pool *pool;
	188	void __iomem *hcr;
	189	struct mutex hcr_mutex;
	190	struct semaphore poll_sem;
	191	struct semaphore event_sem;
	192	int max_cmds;
	193	spinlock_t context_lock;
	194	int free_head;
	195	struct mlx4_cmd_context *context;
	196	u16 token_mask;
	197	u8 use_events;
	198	u8 toggle;
	199	};
	200
	201	struct mlx4_uar_table {
	202	struct mlx4_bitmap bitmap;
	203	};
	204
	205	struct mlx4_mr_table {
	206	struct mlx4_bitmap mpt_bitmap;
	207	struct mlx4_buddy mtt_buddy;
	208	u64 mtt_base;
	209	u64 mpt_base;
	210	struct mlx4_icm_table mtt_table;
	211	struct mlx4_icm_table dmpt_table;
	212	};
	213
	214	struct mlx4_cq_table {
	215	struct mlx4_bitmap bitmap;
	216	spinlock_t lock;
	217	struct radix_tree_root tree;
	218	struct mlx4_icm_table table;
	219	struct mlx4_icm_table cmpt_table;
	220	};
	221
	222	struct mlx4_eq_table {
	223	struct mlx4_bitmap bitmap;
b8dd786f	224	char *irq_names;
225c7b1f	225	void __iomem *clr_int;
b8dd786f	226	void __iomem **uar_map;
225c7b1f	227	u32 clr_mask;
b8dd786f	228	struct mlx4_eq *eq;
fa0681d2	229	struct mlx4_icm_table table;
225c7b1f RD	230	struct mlx4_icm_table cmpt_table;
	231	int have_irq;
	232	u8 inta_pin;
	233	};
	234
	235	struct mlx4_srq_table {
	236	struct mlx4_bitmap bitmap;
	237	spinlock_t lock;
	238	struct radix_tree_root tree;
	239	struct mlx4_icm_table table;
	240	struct mlx4_icm_table cmpt_table;
	241	};
	242
	243	struct mlx4_qp_table {
	244	struct mlx4_bitmap bitmap;
	245	u32 rdmarc_base;
	246	int rdmarc_shift;
	247	spinlock_t lock;
	248	struct mlx4_icm_table qp_table;
	249	struct mlx4_icm_table auxc_table;
	250	struct mlx4_icm_table altc_table;
	251	struct mlx4_icm_table rdmarc_table;
	252	struct mlx4_icm_table cmpt_table;
	253	};
	254
	255	struct mlx4_mcg_table {
	256	struct mutex mutex;
	257	struct mlx4_bitmap bitmap;
	258	struct mlx4_icm_table table;
	259	};
	260
	261	struct mlx4_catas_err {
	262	u32 __iomem *map;
ee49bd93 JM	263	struct timer_list timer;
ee49bd93 JM	264	struct list_head list;
225c7b1f RD	265	};
225c7b1f RD	266
2a2336f8 YP	267	#define MLX4_MAX_MAC_NUM 128
	268	#define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
	269
	270	struct mlx4_mac_table {
	271	__be64 entries[MLX4_MAX_MAC_NUM];
	272	int refs[MLX4_MAX_MAC_NUM];
	273	struct mutex mutex;
	274	int total;
	275	int max;
	276	};
	277
	278	#define MLX4_MAX_VLAN_NUM 128
	279	#define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
	280
	281	struct mlx4_vlan_table {
	282	__be32 entries[MLX4_MAX_VLAN_NUM];
	283	int refs[MLX4_MAX_VLAN_NUM];
	284	struct mutex mutex;
	285	int total;
	286	int max;
	287	};
	288
1679200f YP	289	struct mlx4_mac_entry {
	290	u64 mac;
	291	};
	292
2a2336f8 YP	293	struct mlx4_port_info {
	294	struct mlx4_dev *dev;
	295	int port;
7ff93f8b YP	296	char dev_name[16];
	297	struct device_attribute port_attr;
	298	enum mlx4_port_type tmp_type;
2a2336f8	299	struct mlx4_mac_table mac_table;
1679200f	300	struct radix_tree_root mac_tree;
2a2336f8	301	struct mlx4_vlan_table vlan_table;
1679200f	302	int base_qpn;
2a2336f8 YP	303	};
2a2336f8 YP	304
27bf91d6 YP	305	struct mlx4_sense {
	306	struct mlx4_dev *dev;
	307	u8 do_sense_port[MLX4_MAX_PORTS + 1];
	308	u8 sense_allowed[MLX4_MAX_PORTS + 1];
	309	struct delayed_work sense_poll;
	310	};
	311
0b7ca5a9 YP	312	struct mlx4_msix_ctl {
	313	u64 pool_bm;
	314	spinlock_t pool_lock;
	315	};
	316
b12d93d6 YP	317	struct mlx4_steer {
	318	struct list_head promisc_qps[MLX4_NUM_STEERS];
	319	struct list_head steer_entries[MLX4_NUM_STEERS];
	320	struct list_head high_prios;
	321	};
	322
225c7b1f RD	323	struct mlx4_priv {
	324	struct mlx4_dev dev;
	325
	326	struct list_head dev_list;
	327	struct list_head ctx_list;
	328	spinlock_t ctx_lock;
	329
6296883c YP	330	struct list_head pgdir_list;
	331	struct mutex pgdir_mutex;
	332
225c7b1f RD	333	struct mlx4_fw fw;
	334	struct mlx4_cmd cmd;
	335
	336	struct mlx4_bitmap pd_bitmap;
	337	struct mlx4_uar_table uar_table;
	338	struct mlx4_mr_table mr_table;
	339	struct mlx4_cq_table cq_table;
	340	struct mlx4_eq_table eq_table;
	341	struct mlx4_srq_table srq_table;
	342	struct mlx4_qp_table qp_table;
	343	struct mlx4_mcg_table mcg_table;
	344
	345	struct mlx4_catas_err catas_err;
	346
	347	void __iomem *clr_base;
	348
	349	struct mlx4_uar driver_uar;
	350	void __iomem *kar;
2a2336f8	351	struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
27bf91d6	352	struct mlx4_sense sense;
7ff93f8b	353	struct mutex port_mutex;
0b7ca5a9	354	struct mlx4_msix_ctl msix_ctl;
b12d93d6	355	struct mlx4_steer *steer;
225c7b1f RD	356	};
	357
	358	static inline struct mlx4_priv mlx4_priv(struct mlx4_dev dev)
	359	{
	360	return container_of(dev, struct mlx4_priv, dev);
	361	}
	362
27bf91d6 YP	363	#define MLX4_SENSE_RANGE (HZ * 3)
	364
	365	extern struct workqueue_struct *mlx4_wq;
	366
225c7b1f RD	367	u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
225c7b1f RD	368	void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
a3cdcbfa YP	369	u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
a3cdcbfa YP	370	void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
93fc9e1b YP	371	int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
93fc9e1b YP	372	u32 reserved_bot, u32 resetrved_top);
225c7b1f RD	373	void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
	374
	375	int mlx4_reset(struct mlx4_dev *dev);
	376
b8dd786f YP	377	int mlx4_alloc_eq_table(struct mlx4_dev *dev);
	378	void mlx4_free_eq_table(struct mlx4_dev *dev);
	379
225c7b1f RD	380	int mlx4_init_pd_table(struct mlx4_dev *dev);
	381	int mlx4_init_uar_table(struct mlx4_dev *dev);
	382	int mlx4_init_mr_table(struct mlx4_dev *dev);
	383	int mlx4_init_eq_table(struct mlx4_dev *dev);
	384	int mlx4_init_cq_table(struct mlx4_dev *dev);
	385	int mlx4_init_qp_table(struct mlx4_dev *dev);
	386	int mlx4_init_srq_table(struct mlx4_dev *dev);
	387	int mlx4_init_mcg_table(struct mlx4_dev *dev);
	388
	389	void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
	390	void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
	391	void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
	392	void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
	393	void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
	394	void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
	395	void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
	396	void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
	397
ee49bd93 JM	398	void mlx4_start_catas_poll(struct mlx4_dev *dev);
ee49bd93 JM	399	void mlx4_stop_catas_poll(struct mlx4_dev *dev);
27bf91d6	400	void mlx4_catas_init(void);
ee49bd93	401	int mlx4_restart_one(struct pci_dev *pdev);
225c7b1f RD	402	int mlx4_register_device(struct mlx4_dev *dev);
225c7b1f RD	403	void mlx4_unregister_device(struct mlx4_dev *dev);
37608eea	404	void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, int port);
225c7b1f RD	405
	406	struct mlx4_dev_cap;
	407	struct mlx4_init_hca_param;
	408
	409	u64 mlx4_make_profile(struct mlx4_dev *dev,
	410	struct mlx4_profile *request,
	411	struct mlx4_dev_cap *dev_cap,
	412	struct mlx4_init_hca_param *init_hca);
	413
225c7b1f RD	414	int mlx4_cmd_init(struct mlx4_dev *dev);
	415	void mlx4_cmd_cleanup(struct mlx4_dev *dev);
	416	void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
	417	int mlx4_cmd_use_events(struct mlx4_dev *dev);
	418	void mlx4_cmd_use_polling(struct mlx4_dev *dev);
	419
	420	void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
	421	void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
	422
	423	void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
	424
	425	void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
	426
	427	void mlx4_handle_catas_err(struct mlx4_dev *dev);
	428
27bf91d6 YP	429	void mlx4_do_sense_ports(struct mlx4_dev *dev,
	430	enum mlx4_port_type *stype,
	431	enum mlx4_port_type *defaults);
	432	void mlx4_start_sense(struct mlx4_dev *dev);
	433	void mlx4_stop_sense(struct mlx4_dev *dev);
	434	void mlx4_sense_init(struct mlx4_dev *dev);
	435	int mlx4_check_port_params(struct mlx4_dev *dev,
	436	enum mlx4_port_type *port_type);
	437	int mlx4_change_port_types(struct mlx4_dev *dev,
	438	enum mlx4_port_type *port_types);
	439
2a2336f8 YP	440	void mlx4_init_mac_table(struct mlx4_dev dev, struct mlx4_mac_table table);
	441	void mlx4_init_vlan_table(struct mlx4_dev dev, struct mlx4_vlan_table table);
	442
7ff93f8b	443	int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port);
9a5aa622	444	int mlx4_get_port_ib_caps(struct mlx4_dev dev, u8 port, __be32 caps);
7ff93f8b	445
b12d93d6 YP	446	int mlx4_qp_detach_common(struct mlx4_dev dev, struct mlx4_qp qp, u8 gid[16],
	447	enum mlx4_protocol prot, enum mlx4_steer_type steer);
	448	int mlx4_qp_attach_common(struct mlx4_dev dev, struct mlx4_qp qp, u8 gid[16],
	449	int block_mcast_loopback, enum mlx4_protocol prot,
	450	enum mlx4_steer_type steer);
225c7b1f	451	#endif /* MLX4_H */