[deliverable/linux.git] / drivers / net / mlx4 / mlx4_en.h

/*
 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 */

#ifndef _MLX4_EN_H_
#define _MLX4_EN_H_

#include <linux/compiler.h>
#include <linux/list.h>
#include <linux/mutex.h>
#include <linux/netdevice.h>
#include <linux/inet_lro.h>

#include <linux/mlx4/device.h>
#include <linux/mlx4/qp.h>
#include <linux/mlx4/cq.h>
#include <linux/mlx4/srq.h>
#include <linux/mlx4/doorbell.h>

#include "en_port.h"

#define DRV_NAME	"mlx4_en"
#define DRV_VERSION	"1.4.0"
#define DRV_RELDATE	"Sep 2008"


#define MLX4_EN_MSG_LEVEL	(NETIF_MSG_LINK | NETIF_MSG_IFDOWN)

#define mlx4_dbg(mlevel, priv, format, arg...)	\
	if (NETIF_MSG_##mlevel & priv->msg_enable) \
	printk(KERN_DEBUG "%s %s: " format , DRV_NAME ,\
		(dev_name(&priv->mdev->pdev->dev)) , ## arg)

#define mlx4_err(mdev, format, arg...) \
	printk(KERN_ERR "%s %s: " format , DRV_NAME ,\
		(dev_name(&mdev->pdev->dev)) , ## arg)
#define mlx4_info(mdev, format, arg...) \
	printk(KERN_INFO "%s %s: " format , DRV_NAME ,\
		(dev_name(&mdev->pdev->dev)) , ## arg)
#define mlx4_warn(mdev, format, arg...) \
	printk(KERN_WARNING "%s %s: " format , DRV_NAME ,\
		(dev_name(&mdev->pdev->dev)) , ## arg)

/*
 * Device constants
 */


#define MLX4_EN_PAGE_SHIFT	12
#define MLX4_EN_PAGE_SIZE	(1 << MLX4_EN_PAGE_SHIFT)
#define MAX_TX_RINGS		16
#define MAX_RX_RINGS		16
#define MAX_RSS_MAP_SIZE	64
#define RSS_FACTOR		2
#define TXBB_SIZE		64
#define HEADROOM		(2048 / TXBB_SIZE + 1)
#define MAX_LSO_HDR_SIZE	92
#define STAMP_STRIDE		64
#define STAMP_DWORDS		(STAMP_STRIDE / 4)
#define STAMP_SHIFT		31
#define STAMP_VAL		0x7fffffff
#define STATS_DELAY		(HZ / 4)

/* Typical TSO descriptor with 16 gather entries is 352 bytes... */
#define MAX_DESC_SIZE		512
#define MAX_DESC_TXBBS		(MAX_DESC_SIZE / TXBB_SIZE)

/*
 * OS related constants and tunables
 */

#define MLX4_EN_WATCHDOG_TIMEOUT	(15 * HZ)

#define MLX4_EN_ALLOC_ORDER	2
#define MLX4_EN_ALLOC_SIZE	(PAGE_SIZE << MLX4_EN_ALLOC_ORDER)

#define MLX4_EN_MAX_LRO_DESCRIPTORS	32

/* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
 * and 4K allocations) */
enum {
	FRAG_SZ0 = 512 - NET_IP_ALIGN,
	FRAG_SZ1 = 1024,
	FRAG_SZ2 = 4096,
	FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
};
#define MLX4_EN_MAX_RX_FRAGS	4

/* Minimum ring size for our page-allocation sceme to work */
#define MLX4_EN_MIN_RX_SIZE	(MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
#define MLX4_EN_MIN_TX_SIZE	(4096 / TXBB_SIZE)

#define MLX4_EN_TX_RING_NUM		9
#define MLX4_EN_DEF_TX_RING_SIZE	1024
#define MLX4_EN_DEF_RX_RING_SIZE  	1024

/* Target number of bytes to coalesce with interrupt moderation */
#define MLX4_EN_RX_COAL_TARGET	0x20000
#define MLX4_EN_RX_COAL_TIME	0x10

#define MLX4_EN_TX_COAL_PKTS	5
#define MLX4_EN_TX_COAL_TIME	0x80

#define MLX4_EN_RX_RATE_LOW		400000
#define MLX4_EN_RX_COAL_TIME_LOW	0
#define MLX4_EN_RX_RATE_HIGH		450000
#define MLX4_EN_RX_COAL_TIME_HIGH	128
#define MLX4_EN_RX_SIZE_THRESH		1024
#define MLX4_EN_RX_RATE_THRESH		(1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
#define MLX4_EN_SAMPLE_INTERVAL		0

#define MLX4_EN_AUTO_CONF	0xffff

#define MLX4_EN_DEF_RX_PAUSE	1
#define MLX4_EN_DEF_TX_PAUSE	1

/* Interval between sucessive polls in the Tx routine when polling is used
   instead of interrupts (in per-core Tx rings) - should be power of 2 */
#define MLX4_EN_TX_POLL_MODER	16
#define MLX4_EN_TX_POLL_TIMEOUT	(HZ / 4)

#define ETH_LLC_SNAP_SIZE	8

#define SMALL_PACKET_SIZE      (256 - NET_IP_ALIGN)
#define HEADER_COPY_SIZE       (128 - NET_IP_ALIGN)

#define MLX4_EN_MIN_MTU		46
#define ETH_BCAST		0xffffffffffffULL

#ifdef MLX4_EN_PERF_STAT
/* Number of samples to 'average' */
#define AVG_SIZE			128
#define AVG_FACTOR			1024
#define NUM_PERF_STATS			NUM_PERF_COUNTERS

#define INC_PERF_COUNTER(cnt)		(++(cnt))
#define ADD_PERF_COUNTER(cnt, add)	((cnt) += (add))
#define AVG_PERF_COUNTER(cnt, sample) \
	((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
#define GET_PERF_COUNTER(cnt)		(cnt)
#define GET_AVG_PERF_COUNTER(cnt)	((cnt) / AVG_FACTOR)

#else

#define NUM_PERF_STATS			0
#define INC_PERF_COUNTER(cnt)		do {} while (0)
#define ADD_PERF_COUNTER(cnt, add)	do {} while (0)
#define AVG_PERF_COUNTER(cnt, sample)	do {} while (0)
#define GET_PERF_COUNTER(cnt)		(0)
#define GET_AVG_PERF_COUNTER(cnt)	(0)
#endif /* MLX4_EN_PERF_STAT */

/*
 * Configurables
 */

enum cq_type {
	RX = 0,
	TX = 1,
};


/*
 * Useful macros
 */
#define ROUNDUP_LOG2(x)		ilog2(roundup_pow_of_two(x))
#define XNOR(x, y)		(!(x) == !(y))
#define ILLEGAL_MAC(addr)	(addr == 0xffffffffffffULL || addr == 0x0)


struct mlx4_en_tx_info {
	struct sk_buff *skb;
	u32 nr_txbb;
	u8 linear;
	u8 data_offset;
};


#define MLX4_EN_BIT_DESC_OWN	0x80000000
#define CTRL_SIZE	sizeof(struct mlx4_wqe_ctrl_seg)
#define MLX4_EN_MEMTYPE_PAD	0x100
#define DS_SIZE		sizeof(struct mlx4_wqe_data_seg)


struct mlx4_en_tx_desc {
	struct mlx4_wqe_ctrl_seg ctrl;
	union {
		struct mlx4_wqe_data_seg data; /* at least one data segment */
		struct mlx4_wqe_lso_seg lso;
		struct mlx4_wqe_inline_seg inl;
	};
};

#define MLX4_EN_USE_SRQ		0x01000000

struct mlx4_en_rx_alloc {
	struct page *page;
	u16 offset;
};

struct mlx4_en_tx_ring {
	struct mlx4_hwq_resources wqres;
	u32 size ; /* number of TXBBs */
	u32 size_mask;
	u16 stride;
	u16 cqn;	/* index of port CQ associated with this ring */
	u32 prod;
	u32 cons;
	u32 buf_size;
	u32 doorbell_qpn;
	void *buf;
	u16 poll_cnt;
	int blocked;
	struct mlx4_en_tx_info *tx_info;
	u8 *bounce_buf;
	u32 last_nr_txbb;
	struct mlx4_qp qp;
	struct mlx4_qp_context context;
	int qpn;
	enum mlx4_qp_state qp_state;
	struct mlx4_srq dummy;
	unsigned long bytes;
	unsigned long packets;
	spinlock_t comp_lock;
};

struct mlx4_en_rx_desc {
	struct mlx4_wqe_srq_next_seg next;
	/* actual number of entries depends on rx ring stride */
	struct mlx4_wqe_data_seg data[0];
};

struct mlx4_en_rx_ring {
	struct mlx4_srq srq;
	struct mlx4_hwq_resources wqres;
	struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
	struct net_lro_mgr lro;
	u32 size ;	/* number of Rx descs*/
	u32 actual_size;
	u32 size_mask;
	u16 stride;
	u16 log_stride;
	u16 cqn;	/* index of port CQ associated with this ring */
	u32 prod;
	u32 cons;
	u32 buf_size;
	int need_refill;
	int full;
	void *buf;
	void *rx_info;
	unsigned long bytes;
	unsigned long packets;
};


static inline int mlx4_en_can_lro(__be16 status)
{
	return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4	|
				     MLX4_CQE_STATUS_IPV4F	|
				     MLX4_CQE_STATUS_IPV6	|
				     MLX4_CQE_STATUS_IPV4OPT	|
				     MLX4_CQE_STATUS_TCP	|
				     MLX4_CQE_STATUS_UDP	|
				     MLX4_CQE_STATUS_IPOK)) ==
		cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
			    MLX4_CQE_STATUS_IPOK |
			    MLX4_CQE_STATUS_TCP);
}

struct mlx4_en_cq {
	struct mlx4_cq          mcq;
	struct mlx4_hwq_resources wqres;
	int                     ring;
	spinlock_t              lock;
	struct net_device      *dev;
	struct napi_struct	napi;
	/* Per-core Tx cq processing support */
	struct timer_list timer;
	int size;
	int buf_size;
	unsigned vector;
	enum cq_type is_tx;
	u16 moder_time;
	u16 moder_cnt;
	struct mlx4_cqe *buf;
#define MLX4_EN_OPCODE_ERROR	0x1e
};

struct mlx4_en_port_profile {
	u32 flags;
	u32 tx_ring_num;
	u32 rx_ring_num;
	u32 tx_ring_size;
	u32 rx_ring_size;
	u8 rx_pause;
	u8 rx_ppp;
	u8 tx_pause;
	u8 tx_ppp;
};

struct mlx4_en_profile {
	int rss_xor;
	int num_lro;
	u8 rss_mask;
	u32 active_ports;
	u32 small_pkt_int;
	u8 no_reset;
	struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
};

struct mlx4_en_dev {
	struct mlx4_dev         *dev;
	struct pci_dev		*pdev;
	struct mutex		state_lock;
	struct net_device       *pndev[MLX4_MAX_PORTS + 1];
	u32                     port_cnt;
	bool			device_up;
	struct mlx4_en_profile  profile;
	u32			LSO_support;
	struct workqueue_struct *workqueue;
	struct device           *dma_device;
	void __iomem            *uar_map;
	struct mlx4_uar         priv_uar;
	struct mlx4_mr		mr;
	u32                     priv_pdn;
	spinlock_t              uar_lock;
};


struct mlx4_en_rss_map {
	int size;
	int base_qpn;
	u16 map[MAX_RSS_MAP_SIZE];
	struct mlx4_qp qps[MAX_RSS_MAP_SIZE];
	enum mlx4_qp_state state[MAX_RSS_MAP_SIZE];
	struct mlx4_qp indir_qp;
	enum mlx4_qp_state indir_state;
};

struct mlx4_en_rss_context {
	__be32 base_qpn;
	__be32 default_qpn;
	u16 reserved;
	u8 hash_fn;
	u8 flags;
	__be32 rss_key[10];
};

struct mlx4_en_pkt_stats {
	unsigned long broadcast;
	unsigned long rx_prio[8];
	unsigned long tx_prio[8];
#define NUM_PKT_STATS		17
};

struct mlx4_en_port_stats {
	unsigned long lro_aggregated;
	unsigned long lro_flushed;
	unsigned long lro_no_desc;
	unsigned long tso_packets;
	unsigned long queue_stopped;
	unsigned long wake_queue;
	unsigned long tx_timeout;
	unsigned long rx_alloc_failed;
	unsigned long rx_chksum_good;
	unsigned long rx_chksum_none;
	unsigned long tx_chksum_offload;
#define NUM_PORT_STATS		11
};

struct mlx4_en_perf_stats {
	u32 tx_poll;
	u64 tx_pktsz_avg;
	u32 inflight_avg;
	u16 tx_coal_avg;
	u16 rx_coal_avg;
	u32 napi_quota;
#define NUM_PERF_COUNTERS		6
};

struct mlx4_en_frag_info {
	u16 frag_size;
	u16 frag_prefix_size;
	u16 frag_stride;
	u16 frag_align;
	u16 last_offset;

};

struct mlx4_en_priv {
	struct mlx4_en_dev *mdev;
	struct mlx4_en_port_profile *prof;
	struct net_device *dev;
	struct vlan_group *vlgrp;
	struct net_device_stats stats;
	struct net_device_stats ret_stats;
	spinlock_t stats_lock;

	unsigned long last_moder_packets;
	unsigned long last_moder_tx_packets;
	unsigned long last_moder_bytes;
	unsigned long last_moder_jiffies;
	int last_moder_time;
	u16 rx_usecs;
	u16 rx_frames;
	u16 tx_usecs;
	u16 tx_frames;
	u32 pkt_rate_low;
	u16 rx_usecs_low;
	u32 pkt_rate_high;
	u16 rx_usecs_high;
	u16 sample_interval;
	u16 adaptive_rx_coal;
	u32 msg_enable;

	struct mlx4_hwq_resources res;
	int link_state;
	int last_link_state;
	bool port_up;
	int port;
	int registered;
	int allocated;
	int stride;
	int rx_csum;
	u64 mac;
	int mac_index;
	unsigned max_mtu;
	int base_qpn;

	struct mlx4_en_rss_map rss_map;
	u16 tx_prio_map[8];
	u32 flags;
#define MLX4_EN_FLAG_PROMISC	0x1
	u32 tx_ring_num;
	u32 rx_ring_num;
	u32 rx_skb_size;
	struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
	u16 num_frags;
	u16 log_rx_info;

	struct mlx4_en_tx_ring tx_ring[MAX_TX_RINGS];
	struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
	struct mlx4_en_cq tx_cq[MAX_TX_RINGS];
	struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
	struct work_struct mcast_task;
	struct work_struct mac_task;
	struct delayed_work refill_task;
	struct work_struct watchdog_task;
	struct work_struct linkstate_task;
	struct delayed_work stats_task;
	struct mlx4_en_perf_stats pstats;
	struct mlx4_en_pkt_stats pkstats;
	struct mlx4_en_port_stats port_stats;
	struct dev_mc_list *mc_list;
	struct mlx4_en_stat_out_mbox hw_stats;
};


void mlx4_en_destroy_netdev(struct net_device *dev);
int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
			struct mlx4_en_port_profile *prof);

int mlx4_en_get_profile(struct mlx4_en_dev *mdev);

int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
		      int entries, int ring, enum cq_type mode);
void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);

void mlx4_en_poll_tx_cq(unsigned long data);
void mlx4_en_tx_irq(struct mlx4_cq *mcq);
int mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);

int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring,
			   u32 size, u16 stride);
void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring);
int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
			     struct mlx4_en_tx_ring *ring,
			     int cq, int srqn);
void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
				struct mlx4_en_tx_ring *ring);

int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
			   struct mlx4_en_rx_ring *ring,
			   u32 size, u16 stride);
void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
			     struct mlx4_en_rx_ring *ring);
int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
				struct mlx4_en_rx_ring *ring);
int mlx4_en_process_rx_cq(struct net_device *dev,
			  struct mlx4_en_cq *cq,
			  int budget);
int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
			     int is_tx, int rss, int qpn, int cqn, int srqn,
			     struct mlx4_qp_context *context);
int mlx4_en_map_buffer(struct mlx4_buf *buf);
void mlx4_en_unmap_buffer(struct mlx4_buf *buf);

void mlx4_en_calc_rx_buf(struct net_device *dev);
void mlx4_en_set_default_rss_map(struct mlx4_en_priv *priv,
				 struct mlx4_en_rss_map *rss_map,
				 int num_entries, int num_rings);
void mlx4_en_set_prio_map(struct mlx4_en_priv *priv, u16 *prio_map, u32 ring_num);
int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
void mlx4_en_rx_refill(struct work_struct *work);
void mlx4_en_rx_irq(struct mlx4_cq *mcq);

int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, u8 port, struct vlan_group *grp);
int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
			  u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
			   u8 promisc);

int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);

/*
 * Globals
 */
extern const struct ethtool_ops mlx4_en_ethtool_ops;
#endif
Commit	Line	Data
c27a02cd YP	1	/*
	2	* Copyright (c) 2007 Mellanox Technologies. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*
	32	*/
	33
	34	#ifndef _MLX4_EN_H_
	35	#define _MLX4_EN_H_
	36
	37	#include <linux/compiler.h>
	38	#include <linux/list.h>
	39	#include <linux/mutex.h>
	40	#include <linux/netdevice.h>
	41	#include <linux/inet_lro.h>
	42
	43	#include <linux/mlx4/device.h>
	44	#include <linux/mlx4/qp.h>
	45	#include <linux/mlx4/cq.h>
	46	#include <linux/mlx4/srq.h>
	47	#include <linux/mlx4/doorbell.h>
	48
	49	#include "en_port.h"
	50
	51	#define DRV_NAME "mlx4_en"
	52	#define DRV_VERSION "1.4.0"
	53	#define DRV_RELDATE "Sep 2008"
	54
	55
	56	#define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK \| NETIF_MSG_IFDOWN)
	57
	58	#define mlx4_dbg(mlevel, priv, format, arg...) \
	59	if (NETIF_MSG_##mlevel & priv->msg_enable) \
	60	printk(KERN_DEBUG "%s %s: " format , DRV_NAME ,\
fb28ad35	61	(dev_name(&priv->mdev->pdev->dev)) , ## arg)
c27a02cd YP	62
	63	#define mlx4_err(mdev, format, arg...) \
	64	printk(KERN_ERR "%s %s: " format , DRV_NAME ,\
fb28ad35	65	(dev_name(&mdev->pdev->dev)) , ## arg)
c27a02cd YP	66	#define mlx4_info(mdev, format, arg...) \
c27a02cd YP	67	printk(KERN_INFO "%s %s: " format , DRV_NAME ,\
fb28ad35	68	(dev_name(&mdev->pdev->dev)) , ## arg)
c27a02cd YP	69	#define mlx4_warn(mdev, format, arg...) \
c27a02cd YP	70	printk(KERN_WARNING "%s %s: " format , DRV_NAME ,\
fb28ad35	71	(dev_name(&mdev->pdev->dev)) , ## arg)
c27a02cd YP	72
	73	/*
	74	* Device constants
	75	*/
	76
	77
	78	#define MLX4_EN_PAGE_SHIFT 12
	79	#define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
	80	#define MAX_TX_RINGS 16
	81	#define MAX_RX_RINGS 16
	82	#define MAX_RSS_MAP_SIZE 64
	83	#define RSS_FACTOR 2
	84	#define TXBB_SIZE 64
	85	#define HEADROOM (2048 / TXBB_SIZE + 1)
	86	#define MAX_LSO_HDR_SIZE 92
	87	#define STAMP_STRIDE 64
	88	#define STAMP_DWORDS (STAMP_STRIDE / 4)
	89	#define STAMP_SHIFT 31
	90	#define STAMP_VAL 0x7fffffff
	91	#define STATS_DELAY (HZ / 4)
	92
	93	/* Typical TSO descriptor with 16 gather entries is 352 bytes... */
	94	#define MAX_DESC_SIZE 512
	95	#define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
	96
	97	/*
	98	* OS related constants and tunables
	99	*/
	100
	101	#define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
	102
	103	#define MLX4_EN_ALLOC_ORDER 2
	104	#define MLX4_EN_ALLOC_SIZE (PAGE_SIZE << MLX4_EN_ALLOC_ORDER)
	105
	106	#define MLX4_EN_MAX_LRO_DESCRIPTORS 32
	107
	108	/* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
	109	* and 4K allocations) */
	110	enum {
	111	FRAG_SZ0 = 512 - NET_IP_ALIGN,
	112	FRAG_SZ1 = 1024,
	113	FRAG_SZ2 = 4096,
	114	FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
	115	};
	116	#define MLX4_EN_MAX_RX_FRAGS 4
	117
	118	/* Minimum ring size for our page-allocation sceme to work */
	119	#define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
	120	#define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
	121
	122	#define MLX4_EN_TX_RING_NUM 9
	123	#define MLX4_EN_DEF_TX_RING_SIZE 1024
	124	#define MLX4_EN_DEF_RX_RING_SIZE 1024
	125
	126	/* Target number of bytes to coalesce with interrupt moderation */
	127	#define MLX4_EN_RX_COAL_TARGET 0x20000
	128	#define MLX4_EN_RX_COAL_TIME 0x10
	129
	130	#define MLX4_EN_TX_COAL_PKTS 5
	131	#define MLX4_EN_TX_COAL_TIME 0x80
	132
	133	#define MLX4_EN_RX_RATE_LOW 400000
	134	#define MLX4_EN_RX_COAL_TIME_LOW 0
	135	#define MLX4_EN_RX_RATE_HIGH 450000
136	#define MLX4_EN_RX_COAL_TIME_HIGH 128
137	#define MLX4_EN_RX_SIZE_THRESH 1024
138	#define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
139	#define MLX4_EN_SAMPLE_INTERVAL 0
140
141	#define MLX4_EN_AUTO_CONF 0xffff
142
143	#define MLX4_EN_DEF_RX_PAUSE 1
144	#define MLX4_EN_DEF_TX_PAUSE 1
145
146	/* Interval between sucessive polls in the Tx routine when polling is used
147	instead of interrupts (in per-core Tx rings) - should be power of 2 */
148	#define MLX4_EN_TX_POLL_MODER 16
149	#define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
150
151	#define ETH_LLC_SNAP_SIZE 8
152
153	#define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
154	#define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
155
156	#define MLX4_EN_MIN_MTU 46
157	#define ETH_BCAST 0xffffffffffffULL
158
159	#ifdef MLX4_EN_PERF_STAT
160	/* Number of samples to 'average' */
161	#define AVG_SIZE 128
162	#define AVG_FACTOR 1024
163	#define NUM_PERF_STATS NUM_PERF_COUNTERS
164
165	#define INC_PERF_COUNTER(cnt) (++(cnt))
166	#define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
167	#define AVG_PERF_COUNTER(cnt, sample) \
168	((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
169	#define GET_PERF_COUNTER(cnt) (cnt)
170	#define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
171
172	#else
173
174	#define NUM_PERF_STATS 0
175	#define INC_PERF_COUNTER(cnt) do {} while (0)
176	#define ADD_PERF_COUNTER(cnt, add) do {} while (0)
177	#define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
178	#define GET_PERF_COUNTER(cnt) (0)
179	#define GET_AVG_PERF_COUNTER(cnt) (0)
180	#endif /* MLX4_EN_PERF_STAT */
181
182	/*
183	* Configurables
184	*/
185
186	enum cq_type {
187	RX = 0,
188	TX = 1,
189	};
190
191
192	/*
193	* Useful macros
194	*/
195	#define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
196	#define XNOR(x, y) (!(x) == !(y))
197	#define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL \|\| addr == 0x0)
198
199
200	struct mlx4_en_tx_info {
201	struct sk_buff *skb;
202	u32 nr_txbb;
203	u8 linear;
204	u8 data_offset;
205	};
206
207
208	#define MLX4_EN_BIT_DESC_OWN 0x80000000
209	#define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
210	#define MLX4_EN_MEMTYPE_PAD 0x100
211	#define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
212
213
214	struct mlx4_en_tx_desc {
215	struct mlx4_wqe_ctrl_seg ctrl;
216	union {
217	struct mlx4_wqe_data_seg data; /* at least one data segment */
218	struct mlx4_wqe_lso_seg lso;
219	struct mlx4_wqe_inline_seg inl;
220	};
221	};
222
223	#define MLX4_EN_USE_SRQ 0x01000000
224
225	struct mlx4_en_rx_alloc {
226	struct page *page;
227	u16 offset;
228	};
229
230	struct mlx4_en_tx_ring {
231	struct mlx4_hwq_resources wqres;
232	u32 size ; /* number of TXBBs */
233	u32 size_mask;
234	u16 stride;
235	u16 cqn; /* index of port CQ associated with this ring */
236	u32 prod;
237	u32 cons;
238	u32 buf_size;
239	u32 doorbell_qpn;
240	void *buf;
241	u16 poll_cnt;
242	int blocked;
243	struct mlx4_en_tx_info *tx_info;
244	u8 *bounce_buf;
245	u32 last_nr_txbb;
246	struct mlx4_qp qp;
247	struct mlx4_qp_context context;
248	int qpn;
249	enum mlx4_qp_state qp_state;
250	struct mlx4_srq dummy;
251	unsigned long bytes;
252	unsigned long packets;
253	spinlock_t comp_lock;
254	};
255
256	struct mlx4_en_rx_desc {
257	struct mlx4_wqe_srq_next_seg next;
258	/* actual number of entries depends on rx ring stride */
259	struct mlx4_wqe_data_seg data[0];
260	};
261
262	struct mlx4_en_rx_ring {
263	struct mlx4_srq srq;
264	struct mlx4_hwq_resources wqres;
265	struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
266	struct net_lro_mgr lro;
267	u32 size ; /* number of Rx descs*/
268	u32 actual_size;
269	u32 size_mask;
270	u16 stride;
271	u16 log_stride;
272	u16 cqn; /* index of port CQ associated with this ring */
273	u32 prod;
274	u32 cons;
275	u32 buf_size;
276	int need_refill;
277	int full;
278	void *buf;
279	void *rx_info;
280	unsigned long bytes;
281	unsigned long packets;
282	};
283
284
285	static inline int mlx4_en_can_lro(__be16 status)
286	{
287	return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 \|
288	MLX4_CQE_STATUS_IPV4F \|
289	MLX4_CQE_STATUS_IPV6 \|
290	MLX4_CQE_STATUS_IPV4OPT \|
291	MLX4_CQE_STATUS_TCP \|
292	MLX4_CQE_STATUS_UDP \|
293	MLX4_CQE_STATUS_IPOK)) ==
294	cpu_to_be16(MLX4_CQE_STATUS_IPV4 \|
295	MLX4_CQE_STATUS_IPOK \|
296	MLX4_CQE_STATUS_TCP);
297	}
298
299	struct mlx4_en_cq {
300	struct mlx4_cq mcq;
301	struct mlx4_hwq_resources wqres;
302	int ring;
303	spinlock_t lock;
304	struct net_device *dev;
305	struct napi_struct napi;
306	/* Per-core Tx cq processing support */
307	struct timer_list timer;
308	int size;
309	int buf_size;
310	unsigned vector;
311	enum cq_type is_tx;
312	u16 moder_time;
313	u16 moder_cnt;
c27a02cd YP	314	struct mlx4_cqe *buf;
	315	#define MLX4_EN_OPCODE_ERROR 0x1e
	316	};
	317
	318	struct mlx4_en_port_profile {
	319	u32 flags;
	320	u32 tx_ring_num;
	321	u32 rx_ring_num;
	322	u32 tx_ring_size;
	323	u32 rx_ring_size;
d53b93f2 YP	324	u8 rx_pause;
	325	u8 rx_ppp;
	326	u8 tx_pause;
	327	u8 tx_ppp;
c27a02cd YP	328	};
	329
	330	struct mlx4_en_profile {
	331	int rss_xor;
	332	int num_lro;
	333	u8 rss_mask;
	334	u32 active_ports;
	335	u32 small_pkt_int;
c27a02cd YP	336	u8 no_reset;
	337	struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
	338	};
	339
	340	struct mlx4_en_dev {
	341	struct mlx4_dev *dev;
	342	struct pci_dev *pdev;
	343	struct mutex state_lock;
	344	struct net_device *pndev[MLX4_MAX_PORTS + 1];
	345	u32 port_cnt;
	346	bool device_up;
	347	struct mlx4_en_profile profile;
	348	u32 LSO_support;
	349	struct workqueue_struct *workqueue;
	350	struct device *dma_device;
	351	void __iomem *uar_map;
	352	struct mlx4_uar priv_uar;
	353	struct mlx4_mr mr;
	354	u32 priv_pdn;
	355	spinlock_t uar_lock;
	356	};
	357
	358
	359	struct mlx4_en_rss_map {
	360	int size;
	361	int base_qpn;
	362	u16 map[MAX_RSS_MAP_SIZE];
	363	struct mlx4_qp qps[MAX_RSS_MAP_SIZE];
	364	enum mlx4_qp_state state[MAX_RSS_MAP_SIZE];
	365	struct mlx4_qp indir_qp;
	366	enum mlx4_qp_state indir_state;
	367	};
	368
	369	struct mlx4_en_rss_context {
	370	__be32 base_qpn;
	371	__be32 default_qpn;
	372	u16 reserved;
	373	u8 hash_fn;
	374	u8 flags;
	375	__be32 rss_key[10];
	376	};
	377
	378	struct mlx4_en_pkt_stats {
	379	unsigned long broadcast;
	380	unsigned long rx_prio[8];
	381	unsigned long tx_prio[8];
	382	#define NUM_PKT_STATS 17
	383	};
	384
	385	struct mlx4_en_port_stats {
	386	unsigned long lro_aggregated;
	387	unsigned long lro_flushed;
	388	unsigned long lro_no_desc;
	389	unsigned long tso_packets;
	390	unsigned long queue_stopped;
	391	unsigned long wake_queue;
	392	unsigned long tx_timeout;
	393	unsigned long rx_alloc_failed;
	394	unsigned long rx_chksum_good;
	395	unsigned long rx_chksum_none;
	396	unsigned long tx_chksum_offload;
	397	#define NUM_PORT_STATS 11
	398	};
	399
400	struct mlx4_en_perf_stats {
401	u32 tx_poll;
402	u64 tx_pktsz_avg;
403	u32 inflight_avg;
404	u16 tx_coal_avg;
405	u16 rx_coal_avg;
406	u32 napi_quota;
407	#define NUM_PERF_COUNTERS 6
408	};
409
410	struct mlx4_en_frag_info {
411	u16 frag_size;
412	u16 frag_prefix_size;
413	u16 frag_stride;
414	u16 frag_align;
415	u16 last_offset;
416
417	};
418
419	struct mlx4_en_priv {
420	struct mlx4_en_dev *mdev;
421	struct mlx4_en_port_profile *prof;
422	struct net_device *dev;
423	struct vlan_group *vlgrp;
424	struct net_device_stats stats;
425	struct net_device_stats ret_stats;
426	spinlock_t stats_lock;
427
428	unsigned long last_moder_packets;
429	unsigned long last_moder_tx_packets;
430	unsigned long last_moder_bytes;
431	unsigned long last_moder_jiffies;
432	int last_moder_time;
433	u16 rx_usecs;
434	u16 rx_frames;
435	u16 tx_usecs;
436	u16 tx_frames;
437	u32 pkt_rate_low;
438	u16 rx_usecs_low;
439	u32 pkt_rate_high;
440	u16 rx_usecs_high;
441	u16 sample_interval;
442	u16 adaptive_rx_coal;
443	u32 msg_enable;
444
445	struct mlx4_hwq_resources res;
446	int link_state;
447	int last_link_state;
448	bool port_up;
449	int port;
450	int registered;
451	int allocated;
452	int stride;
453	int rx_csum;
454	u64 mac;
455	int mac_index;
456	unsigned max_mtu;
457	int base_qpn;
458
459	struct mlx4_en_rss_map rss_map;
460	u16 tx_prio_map[8];
461	u32 flags;
462	#define MLX4_EN_FLAG_PROMISC 0x1
463	u32 tx_ring_num;
464	u32 rx_ring_num;
465	u32 rx_skb_size;
466	struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
467	u16 num_frags;
468	u16 log_rx_info;
469
470	struct mlx4_en_tx_ring tx_ring[MAX_TX_RINGS];
471	struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
472	struct mlx4_en_cq tx_cq[MAX_TX_RINGS];
473	struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
474	struct work_struct mcast_task;
475	struct work_struct mac_task;
476	struct delayed_work refill_task;
477	struct work_struct watchdog_task;
478	struct work_struct linkstate_task;
479	struct delayed_work stats_task;
480	struct mlx4_en_perf_stats pstats;
481	struct mlx4_en_pkt_stats pkstats;
482	struct mlx4_en_port_stats port_stats;
483	struct dev_mc_list *mc_list;
484	struct mlx4_en_stat_out_mbox hw_stats;
485	};
486
487
488	void mlx4_en_destroy_netdev(struct net_device *dev);
489	int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
490	struct mlx4_en_port_profile *prof);
491
492	int mlx4_en_get_profile(struct mlx4_en_dev *mdev);
493
494	int mlx4_en_create_cq(struct mlx4_en_priv priv, struct mlx4_en_cq cq,
495	int entries, int ring, enum cq_type mode);
496	void mlx4_en_destroy_cq(struct mlx4_en_priv priv, struct mlx4_en_cq cq);
497	int mlx4_en_activate_cq(struct mlx4_en_priv priv, struct mlx4_en_cq cq);
498	void mlx4_en_deactivate_cq(struct mlx4_en_priv priv, struct mlx4_en_cq cq);
499	int mlx4_en_set_cq_moder(struct mlx4_en_priv priv, struct mlx4_en_cq cq);
500	int mlx4_en_arm_cq(struct mlx4_en_priv priv, struct mlx4_en_cq cq);
501
502	void mlx4_en_poll_tx_cq(unsigned long data);
503	void mlx4_en_tx_irq(struct mlx4_cq *mcq);
504	int mlx4_en_xmit(struct sk_buff skb, struct net_device dev);
505
506	int mlx4_en_create_tx_ring(struct mlx4_en_priv priv, struct mlx4_en_tx_ring ring,
507	u32 size, u16 stride);
508	void mlx4_en_destroy_tx_ring(struct mlx4_en_priv priv, struct mlx4_en_tx_ring ring);
509	int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
510	struct mlx4_en_tx_ring *ring,
511	int cq, int srqn);
512	void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
513	struct mlx4_en_tx_ring *ring);
514
515	int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
516	struct mlx4_en_rx_ring *ring,
517	u32 size, u16 stride);
518	void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
519	struct mlx4_en_rx_ring *ring);
520	int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
521	void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
522	struct mlx4_en_rx_ring *ring);
523	int mlx4_en_process_rx_cq(struct net_device *dev,
524	struct mlx4_en_cq *cq,
525	int budget);
526	int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
527	void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
528	int is_tx, int rss, int qpn, int cqn, int srqn,
529	struct mlx4_qp_context *context);
530	int mlx4_en_map_buffer(struct mlx4_buf *buf);
531	void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
532
533	void mlx4_en_calc_rx_buf(struct net_device *dev);
534	void mlx4_en_set_default_rss_map(struct mlx4_en_priv *priv,
535	struct mlx4_en_rss_map *rss_map,
536	int num_entries, int num_rings);
537	void mlx4_en_set_prio_map(struct mlx4_en_priv priv, u16 prio_map, u32 ring_num);
538	int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
539	void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
540	int mlx4_en_free_tx_buf(struct net_device dev, struct mlx4_en_tx_ring ring);
541	void mlx4_en_rx_refill(struct work_struct *work);
542	void mlx4_en_rx_irq(struct mlx4_cq *mcq);
543
544	int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
545	int mlx4_SET_VLAN_FLTR(struct mlx4_dev dev, u8 port, struct vlan_group grp);
546	int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
547	u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
548	int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
549	u8 promisc);
550
551	int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
552
553	/*
554	* Globals
555	*/
556	extern const struct ethtool_ops mlx4_en_ethtool_ops;
557	#endif