[deliverable/linux.git] / drivers / net / mlx4 / mlx4_en.h

/*
 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 */

#ifndef _MLX4_EN_H_
#define _MLX4_EN_H_

#include <linux/compiler.h>
#include <linux/list.h>
#include <linux/mutex.h>
#include <linux/netdevice.h>
#include <linux/inet_lro.h>

#include <linux/mlx4/device.h>
#include <linux/mlx4/qp.h>
#include <linux/mlx4/cq.h>
#include <linux/mlx4/srq.h>
#include <linux/mlx4/doorbell.h>

#include "en_port.h"

#define DRV_NAME	"mlx4_en"
#define DRV_VERSION	"1.4.0"
#define DRV_RELDATE	"Sep 2008"


#define MLX4_EN_MSG_LEVEL	(NETIF_MSG_LINK | NETIF_MSG_IFDOWN)

#define en_print(level, priv, format, arg...)			\
	{							\
	if ((priv)->registered)					\
		printk(level "%s: %s: " format, DRV_NAME,	\
			(priv->dev)->name, ## arg);		\
	else							\
		printk(level "%s: %s: Port %d: " format,	\
			DRV_NAME, dev_name(&priv->mdev->pdev->dev), \
			(priv)->port, ## arg);			\
	}

#define en_dbg(mlevel, priv, format, arg...)			\
	{							\
	if (NETIF_MSG_##mlevel & priv->msg_enable)		\
		en_print(KERN_DEBUG, priv, format, ## arg)	\
	}
#define en_warn(priv, format, arg...)				\
	en_print(KERN_WARNING, priv, format, ## arg)
#define en_err(priv, format, arg...)				\
	en_print(KERN_ERR, priv, format, ## arg)

#define mlx4_err(mdev, format, arg...) \
	printk(KERN_ERR "%s %s: " format , DRV_NAME ,\
		dev_name(&mdev->pdev->dev) , ## arg)
#define mlx4_info(mdev, format, arg...) \
	printk(KERN_INFO "%s %s: " format , DRV_NAME ,\
		dev_name(&mdev->pdev->dev) , ## arg)
#define mlx4_warn(mdev, format, arg...) \
	printk(KERN_WARNING "%s %s: " format , DRV_NAME ,\
		dev_name(&mdev->pdev->dev) , ## arg)

/*
 * Device constants
 */


#define MLX4_EN_PAGE_SHIFT	12
#define MLX4_EN_PAGE_SIZE	(1 << MLX4_EN_PAGE_SHIFT)
#define MAX_TX_RINGS		16
#define MAX_RX_RINGS		16
#define MAX_RSS_MAP_SIZE	64
#define RSS_FACTOR		2
#define TXBB_SIZE		64
#define HEADROOM		(2048 / TXBB_SIZE + 1)
#define MAX_LSO_HDR_SIZE	92
#define STAMP_STRIDE		64
#define STAMP_DWORDS		(STAMP_STRIDE / 4)
#define STAMP_SHIFT		31
#define STAMP_VAL		0x7fffffff
#define STATS_DELAY		(HZ / 4)

/* Typical TSO descriptor with 16 gather entries is 352 bytes... */
#define MAX_DESC_SIZE		512
#define MAX_DESC_TXBBS		(MAX_DESC_SIZE / TXBB_SIZE)

/*
 * OS related constants and tunables
 */

#define MLX4_EN_WATCHDOG_TIMEOUT	(15 * HZ)

#define MLX4_EN_ALLOC_ORDER	2
#define MLX4_EN_ALLOC_SIZE	(PAGE_SIZE << MLX4_EN_ALLOC_ORDER)

#define MLX4_EN_MAX_LRO_DESCRIPTORS	32

/* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
 * and 4K allocations) */
enum {
	FRAG_SZ0 = 512 - NET_IP_ALIGN,
	FRAG_SZ1 = 1024,
	FRAG_SZ2 = 4096,
	FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
};
#define MLX4_EN_MAX_RX_FRAGS	4

/* Maximum ring sizes */
#define MLX4_EN_MAX_TX_SIZE	8192
#define MLX4_EN_MAX_RX_SIZE	8192

/* Minimum ring size for our page-allocation sceme to work */
#define MLX4_EN_MIN_RX_SIZE	(MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
#define MLX4_EN_MIN_TX_SIZE	(4096 / TXBB_SIZE)

#define MLX4_EN_TX_RING_NUM		9
#define MLX4_EN_DEF_TX_RING_SIZE	1024
#define MLX4_EN_DEF_RX_RING_SIZE  	1024

/* Target number of bytes to coalesce with interrupt moderation */
#define MLX4_EN_RX_COAL_TARGET	0x20000
#define MLX4_EN_RX_COAL_TIME	0x10

#define MLX4_EN_TX_COAL_PKTS	5
#define MLX4_EN_TX_COAL_TIME	0x80

#define MLX4_EN_RX_RATE_LOW		400000
#define MLX4_EN_RX_COAL_TIME_LOW	0
#define MLX4_EN_RX_RATE_HIGH		450000
#define MLX4_EN_RX_COAL_TIME_HIGH	128
#define MLX4_EN_RX_SIZE_THRESH		1024
#define MLX4_EN_RX_RATE_THRESH		(1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
#define MLX4_EN_SAMPLE_INTERVAL		0

#define MLX4_EN_AUTO_CONF	0xffff

#define MLX4_EN_DEF_RX_PAUSE	1
#define MLX4_EN_DEF_TX_PAUSE	1

/* Interval between sucessive polls in the Tx routine when polling is used
   instead of interrupts (in per-core Tx rings) - should be power of 2 */
#define MLX4_EN_TX_POLL_MODER	16
#define MLX4_EN_TX_POLL_TIMEOUT	(HZ / 4)

#define ETH_LLC_SNAP_SIZE	8

#define SMALL_PACKET_SIZE      (256 - NET_IP_ALIGN)
#define HEADER_COPY_SIZE       (128 - NET_IP_ALIGN)

#define MLX4_EN_MIN_MTU		46
#define ETH_BCAST		0xffffffffffffULL

#ifdef MLX4_EN_PERF_STAT
/* Number of samples to 'average' */
#define AVG_SIZE			128
#define AVG_FACTOR			1024
#define NUM_PERF_STATS			NUM_PERF_COUNTERS

#define INC_PERF_COUNTER(cnt)		(++(cnt))
#define ADD_PERF_COUNTER(cnt, add)	((cnt) += (add))
#define AVG_PERF_COUNTER(cnt, sample) \
	((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
#define GET_PERF_COUNTER(cnt)		(cnt)
#define GET_AVG_PERF_COUNTER(cnt)	((cnt) / AVG_FACTOR)

#else

#define NUM_PERF_STATS			0
#define INC_PERF_COUNTER(cnt)		do {} while (0)
#define ADD_PERF_COUNTER(cnt, add)	do {} while (0)
#define AVG_PERF_COUNTER(cnt, sample)	do {} while (0)
#define GET_PERF_COUNTER(cnt)		(0)
#define GET_AVG_PERF_COUNTER(cnt)	(0)
#endif /* MLX4_EN_PERF_STAT */

/*
 * Configurables
 */

enum cq_type {
	RX = 0,
	TX = 1,
};


/*
 * Useful macros
 */
#define ROUNDUP_LOG2(x)		ilog2(roundup_pow_of_two(x))
#define XNOR(x, y)		(!(x) == !(y))
#define ILLEGAL_MAC(addr)	(addr == 0xffffffffffffULL || addr == 0x0)


struct mlx4_en_tx_info {
	struct sk_buff *skb;
	u32 nr_txbb;
	u8 linear;
	u8 data_offset;
	u8 inl;
};


#define MLX4_EN_BIT_DESC_OWN	0x80000000
#define CTRL_SIZE	sizeof(struct mlx4_wqe_ctrl_seg)
#define MLX4_EN_MEMTYPE_PAD	0x100
#define DS_SIZE		sizeof(struct mlx4_wqe_data_seg)


struct mlx4_en_tx_desc {
	struct mlx4_wqe_ctrl_seg ctrl;
	union {
		struct mlx4_wqe_data_seg data; /* at least one data segment */
		struct mlx4_wqe_lso_seg lso;
		struct mlx4_wqe_inline_seg inl;
	};
};

#define MLX4_EN_USE_SRQ		0x01000000

struct mlx4_en_rx_alloc {
	struct page *page;
	u16 offset;
};

struct mlx4_en_tx_ring {
	struct mlx4_hwq_resources wqres;
	u32 size ; /* number of TXBBs */
	u32 size_mask;
	u16 stride;
	u16 cqn;	/* index of port CQ associated with this ring */
	u32 prod;
	u32 cons;
	u32 buf_size;
	u32 doorbell_qpn;
	void *buf;
	u16 poll_cnt;
	int blocked;
	struct mlx4_en_tx_info *tx_info;
	u8 *bounce_buf;
	u32 last_nr_txbb;
	struct mlx4_qp qp;
	struct mlx4_qp_context context;
	int qpn;
	enum mlx4_qp_state qp_state;
	struct mlx4_srq dummy;
	unsigned long bytes;
	unsigned long packets;
	spinlock_t comp_lock;
};

struct mlx4_en_rx_desc {
	struct mlx4_wqe_srq_next_seg next;
	/* actual number of entries depends on rx ring stride */
	struct mlx4_wqe_data_seg data[0];
};

struct mlx4_en_rx_ring {
	struct mlx4_srq srq;
	struct mlx4_hwq_resources wqres;
	struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
	struct net_lro_mgr lro;
	u32 size ;	/* number of Rx descs*/
	u32 actual_size;
	u32 size_mask;
	u16 stride;
	u16 log_stride;
	u16 cqn;	/* index of port CQ associated with this ring */
	u32 prod;
	u32 cons;
	u32 buf_size;
	int need_refill;
	int full;
	void *buf;
	void *rx_info;
	unsigned long bytes;
	unsigned long packets;
};


static inline int mlx4_en_can_lro(__be16 status)
{
	return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4	|
				     MLX4_CQE_STATUS_IPV4F	|
				     MLX4_CQE_STATUS_IPV6	|
				     MLX4_CQE_STATUS_IPV4OPT	|
				     MLX4_CQE_STATUS_TCP	|
				     MLX4_CQE_STATUS_UDP	|
				     MLX4_CQE_STATUS_IPOK)) ==
		cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
			    MLX4_CQE_STATUS_IPOK |
			    MLX4_CQE_STATUS_TCP);
}

struct mlx4_en_cq {
	struct mlx4_cq          mcq;
	struct mlx4_hwq_resources wqres;
	int                     ring;
	spinlock_t              lock;
	struct net_device      *dev;
	struct napi_struct	napi;
	/* Per-core Tx cq processing support */
	struct timer_list timer;
	int size;
	int buf_size;
	unsigned vector;
	enum cq_type is_tx;
	u16 moder_time;
	u16 moder_cnt;
	struct mlx4_cqe *buf;
#define MLX4_EN_OPCODE_ERROR	0x1e
};

struct mlx4_en_port_profile {
	u32 flags;
	u32 tx_ring_num;
	u32 rx_ring_num;
	u32 tx_ring_size;
	u32 rx_ring_size;
	u8 rx_pause;
	u8 rx_ppp;
	u8 tx_pause;
	u8 tx_ppp;
};

struct mlx4_en_profile {
	int rss_xor;
	int num_lro;
	u8 rss_mask;
	u32 active_ports;
	u32 small_pkt_int;
	u8 no_reset;
	struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
};

struct mlx4_en_dev {
	struct mlx4_dev         *dev;
	struct pci_dev		*pdev;
	struct mutex		state_lock;
	struct net_device       *pndev[MLX4_MAX_PORTS + 1];
	u32                     port_cnt;
	bool			device_up;
	struct mlx4_en_profile  profile;
	u32			LSO_support;
	struct workqueue_struct *workqueue;
	struct device           *dma_device;
	void __iomem            *uar_map;
	struct mlx4_uar         priv_uar;
	struct mlx4_mr		mr;
	u32                     priv_pdn;
	spinlock_t              uar_lock;
};


struct mlx4_en_rss_map {
	int size;
	int base_qpn;
	u16 map[MAX_RSS_MAP_SIZE];
	struct mlx4_qp qps[MAX_RSS_MAP_SIZE];
	enum mlx4_qp_state state[MAX_RSS_MAP_SIZE];
	struct mlx4_qp indir_qp;
	enum mlx4_qp_state indir_state;
};

struct mlx4_en_rss_context {
	__be32 base_qpn;
	__be32 default_qpn;
	u16 reserved;
	u8 hash_fn;
	u8 flags;
	__be32 rss_key[10];
};

struct mlx4_en_pkt_stats {
	unsigned long broadcast;
	unsigned long rx_prio[8];
	unsigned long tx_prio[8];
#define NUM_PKT_STATS		17
};

struct mlx4_en_port_stats {
	unsigned long lro_aggregated;
	unsigned long lro_flushed;
	unsigned long lro_no_desc;
	unsigned long tso_packets;
	unsigned long queue_stopped;
	unsigned long wake_queue;
	unsigned long tx_timeout;
	unsigned long rx_alloc_failed;
	unsigned long rx_chksum_good;
	unsigned long rx_chksum_none;
	unsigned long tx_chksum_offload;
#define NUM_PORT_STATS		11
};

struct mlx4_en_perf_stats {
	u32 tx_poll;
	u64 tx_pktsz_avg;
	u32 inflight_avg;
	u16 tx_coal_avg;
	u16 rx_coal_avg;
	u32 napi_quota;
#define NUM_PERF_COUNTERS		6
};

struct mlx4_en_frag_info {
	u16 frag_size;
	u16 frag_prefix_size;
	u16 frag_stride;
	u16 frag_align;
	u16 last_offset;

};

struct mlx4_en_priv {
	struct mlx4_en_dev *mdev;
	struct mlx4_en_port_profile *prof;
	struct net_device *dev;
	struct vlan_group *vlgrp;
	struct net_device_stats stats;
	struct net_device_stats ret_stats;
	spinlock_t stats_lock;

	unsigned long last_moder_packets;
	unsigned long last_moder_tx_packets;
	unsigned long last_moder_bytes;
	unsigned long last_moder_jiffies;
	int last_moder_time;
	u16 rx_usecs;
	u16 rx_frames;
	u16 tx_usecs;
	u16 tx_frames;
	u32 pkt_rate_low;
	u16 rx_usecs_low;
	u32 pkt_rate_high;
	u16 rx_usecs_high;
	u16 sample_interval;
	u16 adaptive_rx_coal;
	u32 msg_enable;

	struct mlx4_hwq_resources res;
	int link_state;
	int last_link_state;
	bool port_up;
	int port;
	int registered;
	int allocated;
	int stride;
	int rx_csum;
	u64 mac;
	int mac_index;
	unsigned max_mtu;
	int base_qpn;

	struct mlx4_en_rss_map rss_map;
	u16 tx_prio_map[8];
	u32 flags;
#define MLX4_EN_FLAG_PROMISC	0x1
	u32 tx_ring_num;
	u32 rx_ring_num;
	u32 rx_skb_size;
	struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
	u16 num_frags;
	u16 log_rx_info;

	struct mlx4_en_tx_ring tx_ring[MAX_TX_RINGS];
	struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
	struct mlx4_en_cq tx_cq[MAX_TX_RINGS];
	struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
	struct work_struct mcast_task;
	struct work_struct mac_task;
	struct delayed_work refill_task;
	struct work_struct watchdog_task;
	struct work_struct linkstate_task;
	struct delayed_work stats_task;
	struct mlx4_en_perf_stats pstats;
	struct mlx4_en_pkt_stats pkstats;
	struct mlx4_en_port_stats port_stats;
	struct dev_mc_list *mc_list;
	struct mlx4_en_stat_out_mbox hw_stats;
};


void mlx4_en_destroy_netdev(struct net_device *dev);
int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
			struct mlx4_en_port_profile *prof);

int mlx4_en_start_port(struct net_device *dev);
void mlx4_en_stop_port(struct net_device *dev);

void mlx4_en_free_resources(struct mlx4_en_priv *priv);
int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);

int mlx4_en_get_profile(struct mlx4_en_dev *mdev);

int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
		      int entries, int ring, enum cq_type mode);
void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);

void mlx4_en_poll_tx_cq(unsigned long data);
void mlx4_en_tx_irq(struct mlx4_cq *mcq);
int mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);

int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring,
			   u32 size, u16 stride);
void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring);
int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
			     struct mlx4_en_tx_ring *ring,
			     int cq, int srqn);
void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
				struct mlx4_en_tx_ring *ring);

int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
			   struct mlx4_en_rx_ring *ring,
			   u32 size, u16 stride);
void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
			     struct mlx4_en_rx_ring *ring);
int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
				struct mlx4_en_rx_ring *ring);
int mlx4_en_process_rx_cq(struct net_device *dev,
			  struct mlx4_en_cq *cq,
			  int budget);
int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
			     int is_tx, int rss, int qpn, int cqn, int srqn,
			     struct mlx4_qp_context *context);
void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
int mlx4_en_map_buffer(struct mlx4_buf *buf);
void mlx4_en_unmap_buffer(struct mlx4_buf *buf);

void mlx4_en_calc_rx_buf(struct net_device *dev);
void mlx4_en_set_default_rss_map(struct mlx4_en_priv *priv,
				 struct mlx4_en_rss_map *rss_map,
				 int num_entries, int num_rings);
void mlx4_en_set_prio_map(struct mlx4_en_priv *priv, u16 *prio_map, u32 ring_num);
int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
void mlx4_en_rx_refill(struct work_struct *work);
void mlx4_en_rx_irq(struct mlx4_cq *mcq);

int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, u8 port, struct vlan_group *grp);
int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
			  u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
			   u8 promisc);

int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);

/*
 * Globals
 */
extern const struct ethtool_ops mlx4_en_ethtool_ops;
#endif
Commit	Line	Data
c27a02cd YP	1	/*
	2	* Copyright (c) 2007 Mellanox Technologies. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*
	32	*/
	33
	34	#ifndef _MLX4_EN_H_
	35	#define _MLX4_EN_H_
	36
	37	#include <linux/compiler.h>
	38	#include <linux/list.h>
	39	#include <linux/mutex.h>
	40	#include <linux/netdevice.h>
	41	#include <linux/inet_lro.h>
	42
	43	#include <linux/mlx4/device.h>
	44	#include <linux/mlx4/qp.h>
	45	#include <linux/mlx4/cq.h>
	46	#include <linux/mlx4/srq.h>
	47	#include <linux/mlx4/doorbell.h>
	48
	49	#include "en_port.h"
	50
	51	#define DRV_NAME "mlx4_en"
	52	#define DRV_VERSION "1.4.0"
	53	#define DRV_RELDATE "Sep 2008"
	54
	55
	56	#define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK \| NETIF_MSG_IFDOWN)
	57
453a6082 YP	58	#define en_print(level, priv, format, arg...) \
	59	{ \
	60	if ((priv)->registered) \
	61	printk(level "%s: %s: " format, DRV_NAME, \
	62	(priv->dev)->name, ## arg); \
	63	else \
	64	printk(level "%s: %s: Port %d: " format, \
	65	DRV_NAME, dev_name(&priv->mdev->pdev->dev), \
	66	(priv)->port, ## arg); \
	67	}
	68
	69	#define en_dbg(mlevel, priv, format, arg...) \
	70	{ \
	71	if (NETIF_MSG_##mlevel & priv->msg_enable) \
	72	en_print(KERN_DEBUG, priv, format, ## arg) \
	73	}
	74	#define en_warn(priv, format, arg...) \
	75	en_print(KERN_WARNING, priv, format, ## arg)
	76	#define en_err(priv, format, arg...) \
	77	en_print(KERN_ERR, priv, format, ## arg)
c27a02cd YP	78
	79	#define mlx4_err(mdev, format, arg...) \
	80	printk(KERN_ERR "%s %s: " format , DRV_NAME ,\
453a6082	81	dev_name(&mdev->pdev->dev) , ## arg)
c27a02cd YP	82	#define mlx4_info(mdev, format, arg...) \
c27a02cd YP	83	printk(KERN_INFO "%s %s: " format , DRV_NAME ,\
453a6082	84	dev_name(&mdev->pdev->dev) , ## arg)
c27a02cd YP	85	#define mlx4_warn(mdev, format, arg...) \
c27a02cd YP	86	printk(KERN_WARNING "%s %s: " format , DRV_NAME ,\
453a6082	87	dev_name(&mdev->pdev->dev) , ## arg)
c27a02cd YP	88
	89	/*
	90	* Device constants
	91	*/
	92
	93
	94	#define MLX4_EN_PAGE_SHIFT 12
	95	#define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
	96	#define MAX_TX_RINGS 16
	97	#define MAX_RX_RINGS 16
	98	#define MAX_RSS_MAP_SIZE 64
	99	#define RSS_FACTOR 2
	100	#define TXBB_SIZE 64
	101	#define HEADROOM (2048 / TXBB_SIZE + 1)
	102	#define MAX_LSO_HDR_SIZE 92
	103	#define STAMP_STRIDE 64
	104	#define STAMP_DWORDS (STAMP_STRIDE / 4)
	105	#define STAMP_SHIFT 31
	106	#define STAMP_VAL 0x7fffffff
	107	#define STATS_DELAY (HZ / 4)
	108
	109	/* Typical TSO descriptor with 16 gather entries is 352 bytes... */
	110	#define MAX_DESC_SIZE 512
	111	#define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
	112
	113	/*
	114	* OS related constants and tunables
	115	*/
	116
	117	#define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
	118
	119	#define MLX4_EN_ALLOC_ORDER 2
	120	#define MLX4_EN_ALLOC_SIZE (PAGE_SIZE << MLX4_EN_ALLOC_ORDER)
	121
	122	#define MLX4_EN_MAX_LRO_DESCRIPTORS 32
	123
	124	/* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
	125	* and 4K allocations) */
	126	enum {
	127	FRAG_SZ0 = 512 - NET_IP_ALIGN,
	128	FRAG_SZ1 = 1024,
	129	FRAG_SZ2 = 4096,
	130	FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
	131	};
	132	#define MLX4_EN_MAX_RX_FRAGS 4
	133
bd531e36 YP	134	/* Maximum ring sizes */
	135	#define MLX4_EN_MAX_TX_SIZE 8192
	136	#define MLX4_EN_MAX_RX_SIZE 8192
	137
c27a02cd YP	138	/* Minimum ring size for our page-allocation sceme to work */
	139	#define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
	140	#define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
	141
	142	#define MLX4_EN_TX_RING_NUM 9
	143	#define MLX4_EN_DEF_TX_RING_SIZE 1024
	144	#define MLX4_EN_DEF_RX_RING_SIZE 1024
	145
	146	/* Target number of bytes to coalesce with interrupt moderation */
	147	#define MLX4_EN_RX_COAL_TARGET 0x20000
	148	#define MLX4_EN_RX_COAL_TIME 0x10
	149
	150	#define MLX4_EN_TX_COAL_PKTS 5
	151	#define MLX4_EN_TX_COAL_TIME 0x80
	152
	153	#define MLX4_EN_RX_RATE_LOW 400000
	154	#define MLX4_EN_RX_COAL_TIME_LOW 0
	155	#define MLX4_EN_RX_RATE_HIGH 450000
	156	#define MLX4_EN_RX_COAL_TIME_HIGH 128
	157	#define MLX4_EN_RX_SIZE_THRESH 1024
	158	#define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
	159	#define MLX4_EN_SAMPLE_INTERVAL 0
	160
	161	#define MLX4_EN_AUTO_CONF 0xffff
	162
	163	#define MLX4_EN_DEF_RX_PAUSE 1
	164	#define MLX4_EN_DEF_TX_PAUSE 1
	165
	166	/* Interval between sucessive polls in the Tx routine when polling is used
	167	instead of interrupts (in per-core Tx rings) - should be power of 2 */
	168	#define MLX4_EN_TX_POLL_MODER 16
	169	#define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
	170
	171	#define ETH_LLC_SNAP_SIZE 8
	172
	173	#define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
	174	#define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
	175
	176	#define MLX4_EN_MIN_MTU 46
	177	#define ETH_BCAST 0xffffffffffffULL
	178
	179	#ifdef MLX4_EN_PERF_STAT
	180	/* Number of samples to 'average' */
	181	#define AVG_SIZE 128
	182	#define AVG_FACTOR 1024
	183	#define NUM_PERF_STATS NUM_PERF_COUNTERS
	184
	185	#define INC_PERF_COUNTER(cnt) (++(cnt))
	186	#define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
	187	#define AVG_PERF_COUNTER(cnt, sample) \
	188	((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
	189	#define GET_PERF_COUNTER(cnt) (cnt)
	190	#define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
	191
	192	#else
	193
	194	#define NUM_PERF_STATS 0
	195	#define INC_PERF_COUNTER(cnt) do {} while (0)
	196	#define ADD_PERF_COUNTER(cnt, add) do {} while (0)
	197	#define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
	198	#define GET_PERF_COUNTER(cnt) (0)
	199	#define GET_AVG_PERF_COUNTER(cnt) (0)
	200	#endif /* MLX4_EN_PERF_STAT */
	201
202	/*
203	* Configurables
204	*/
205
206	enum cq_type {
207	RX = 0,
208	TX = 1,
209	};
210
211
212	/*
213	* Useful macros
214	*/
215	#define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
216	#define XNOR(x, y) (!(x) == !(y))
217	#define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL \|\| addr == 0x0)
218
219
220	struct mlx4_en_tx_info {
221	struct sk_buff *skb;
222	u32 nr_txbb;
223	u8 linear;
224	u8 data_offset;
41efea5a	225	u8 inl;
c27a02cd YP	226	};
	227
	228
	229	#define MLX4_EN_BIT_DESC_OWN 0x80000000
	230	#define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
	231	#define MLX4_EN_MEMTYPE_PAD 0x100
	232	#define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
	233
	234
	235	struct mlx4_en_tx_desc {
	236	struct mlx4_wqe_ctrl_seg ctrl;
	237	union {
	238	struct mlx4_wqe_data_seg data; /* at least one data segment */
	239	struct mlx4_wqe_lso_seg lso;
	240	struct mlx4_wqe_inline_seg inl;
	241	};
	242	};
	243
	244	#define MLX4_EN_USE_SRQ 0x01000000
	245
	246	struct mlx4_en_rx_alloc {
	247	struct page *page;
	248	u16 offset;
	249	};
	250
	251	struct mlx4_en_tx_ring {
	252	struct mlx4_hwq_resources wqres;
	253	u32 size ; /* number of TXBBs */
	254	u32 size_mask;
	255	u16 stride;
	256	u16 cqn; /* index of port CQ associated with this ring */
	257	u32 prod;
	258	u32 cons;
	259	u32 buf_size;
	260	u32 doorbell_qpn;
	261	void *buf;
	262	u16 poll_cnt;
	263	int blocked;
	264	struct mlx4_en_tx_info *tx_info;
	265	u8 *bounce_buf;
	266	u32 last_nr_txbb;
	267	struct mlx4_qp qp;
	268	struct mlx4_qp_context context;
	269	int qpn;
	270	enum mlx4_qp_state qp_state;
	271	struct mlx4_srq dummy;
	272	unsigned long bytes;
	273	unsigned long packets;
	274	spinlock_t comp_lock;
	275	};
	276
	277	struct mlx4_en_rx_desc {
	278	struct mlx4_wqe_srq_next_seg next;
	279	/* actual number of entries depends on rx ring stride */
	280	struct mlx4_wqe_data_seg data[0];
	281	};
	282
	283	struct mlx4_en_rx_ring {
	284	struct mlx4_srq srq;
	285	struct mlx4_hwq_resources wqres;
	286	struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
	287	struct net_lro_mgr lro;
	288	u32 size ; /* number of Rx descs*/
	289	u32 actual_size;
290	u32 size_mask;
291	u16 stride;
292	u16 log_stride;
293	u16 cqn; /* index of port CQ associated with this ring */
294	u32 prod;
295	u32 cons;
296	u32 buf_size;
297	int need_refill;
298	int full;
299	void *buf;
300	void *rx_info;
301	unsigned long bytes;
302	unsigned long packets;
303	};
304
305
306	static inline int mlx4_en_can_lro(__be16 status)
307	{
308	return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 \|
309	MLX4_CQE_STATUS_IPV4F \|
310	MLX4_CQE_STATUS_IPV6 \|
311	MLX4_CQE_STATUS_IPV4OPT \|
312	MLX4_CQE_STATUS_TCP \|
313	MLX4_CQE_STATUS_UDP \|
314	MLX4_CQE_STATUS_IPOK)) ==
315	cpu_to_be16(MLX4_CQE_STATUS_IPV4 \|
316	MLX4_CQE_STATUS_IPOK \|
317	MLX4_CQE_STATUS_TCP);
318	}
319
320	struct mlx4_en_cq {
321	struct mlx4_cq mcq;
322	struct mlx4_hwq_resources wqres;
323	int ring;
324	spinlock_t lock;
325	struct net_device *dev;
326	struct napi_struct napi;
327	/* Per-core Tx cq processing support */
328	struct timer_list timer;
329	int size;
330	int buf_size;
331	unsigned vector;
332	enum cq_type is_tx;
333	u16 moder_time;
334	u16 moder_cnt;
c27a02cd YP	335	struct mlx4_cqe *buf;
	336	#define MLX4_EN_OPCODE_ERROR 0x1e
	337	};
	338
	339	struct mlx4_en_port_profile {
	340	u32 flags;
	341	u32 tx_ring_num;
	342	u32 rx_ring_num;
	343	u32 tx_ring_size;
	344	u32 rx_ring_size;
d53b93f2 YP	345	u8 rx_pause;
	346	u8 rx_ppp;
	347	u8 tx_pause;
	348	u8 tx_ppp;
c27a02cd YP	349	};
	350
	351	struct mlx4_en_profile {
	352	int rss_xor;
	353	int num_lro;
	354	u8 rss_mask;
	355	u32 active_ports;
	356	u32 small_pkt_int;
c27a02cd YP	357	u8 no_reset;
	358	struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
	359	};
	360
	361	struct mlx4_en_dev {
	362	struct mlx4_dev *dev;
	363	struct pci_dev *pdev;
	364	struct mutex state_lock;
	365	struct net_device *pndev[MLX4_MAX_PORTS + 1];
	366	u32 port_cnt;
	367	bool device_up;
	368	struct mlx4_en_profile profile;
	369	u32 LSO_support;
	370	struct workqueue_struct *workqueue;
	371	struct device *dma_device;
	372	void __iomem *uar_map;
	373	struct mlx4_uar priv_uar;
	374	struct mlx4_mr mr;
	375	u32 priv_pdn;
	376	spinlock_t uar_lock;
	377	};
	378
	379
	380	struct mlx4_en_rss_map {
	381	int size;
	382	int base_qpn;
	383	u16 map[MAX_RSS_MAP_SIZE];
	384	struct mlx4_qp qps[MAX_RSS_MAP_SIZE];
	385	enum mlx4_qp_state state[MAX_RSS_MAP_SIZE];
	386	struct mlx4_qp indir_qp;
	387	enum mlx4_qp_state indir_state;
	388	};
	389
	390	struct mlx4_en_rss_context {
	391	__be32 base_qpn;
	392	__be32 default_qpn;
	393	u16 reserved;
	394	u8 hash_fn;
	395	u8 flags;
	396	__be32 rss_key[10];
	397	};
	398
	399	struct mlx4_en_pkt_stats {
	400	unsigned long broadcast;
	401	unsigned long rx_prio[8];
	402	unsigned long tx_prio[8];
	403	#define NUM_PKT_STATS 17
	404	};
	405
	406	struct mlx4_en_port_stats {
	407	unsigned long lro_aggregated;
	408	unsigned long lro_flushed;
	409	unsigned long lro_no_desc;
	410	unsigned long tso_packets;
	411	unsigned long queue_stopped;
	412	unsigned long wake_queue;
	413	unsigned long tx_timeout;
	414	unsigned long rx_alloc_failed;
	415	unsigned long rx_chksum_good;
	416	unsigned long rx_chksum_none;
	417	unsigned long tx_chksum_offload;
	418	#define NUM_PORT_STATS 11
	419	};
	420
421	struct mlx4_en_perf_stats {
422	u32 tx_poll;
423	u64 tx_pktsz_avg;
424	u32 inflight_avg;
425	u16 tx_coal_avg;
426	u16 rx_coal_avg;
427	u32 napi_quota;
428	#define NUM_PERF_COUNTERS 6
429	};
430
431	struct mlx4_en_frag_info {
432	u16 frag_size;
433	u16 frag_prefix_size;
434	u16 frag_stride;
435	u16 frag_align;
436	u16 last_offset;
437
438	};
439
440	struct mlx4_en_priv {
441	struct mlx4_en_dev *mdev;
442	struct mlx4_en_port_profile *prof;
443	struct net_device *dev;
444	struct vlan_group *vlgrp;
445	struct net_device_stats stats;
446	struct net_device_stats ret_stats;
447	spinlock_t stats_lock;
448
449	unsigned long last_moder_packets;
450	unsigned long last_moder_tx_packets;
451	unsigned long last_moder_bytes;
452	unsigned long last_moder_jiffies;
453	int last_moder_time;
454	u16 rx_usecs;
455	u16 rx_frames;
456	u16 tx_usecs;
457	u16 tx_frames;
458	u32 pkt_rate_low;
459	u16 rx_usecs_low;
460	u32 pkt_rate_high;
461	u16 rx_usecs_high;
462	u16 sample_interval;
463	u16 adaptive_rx_coal;
464	u32 msg_enable;
465
466	struct mlx4_hwq_resources res;
467	int link_state;
468	int last_link_state;
469	bool port_up;
470	int port;
471	int registered;
472	int allocated;
473	int stride;
474	int rx_csum;
475	u64 mac;
476	int mac_index;
477	unsigned max_mtu;
478	int base_qpn;
479
480	struct mlx4_en_rss_map rss_map;
481	u16 tx_prio_map[8];
482	u32 flags;
483	#define MLX4_EN_FLAG_PROMISC 0x1
484	u32 tx_ring_num;
485	u32 rx_ring_num;
486	u32 rx_skb_size;
487	struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
488	u16 num_frags;
489	u16 log_rx_info;
490
491	struct mlx4_en_tx_ring tx_ring[MAX_TX_RINGS];
492	struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
493	struct mlx4_en_cq tx_cq[MAX_TX_RINGS];
494	struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
495	struct work_struct mcast_task;
496	struct work_struct mac_task;
497	struct delayed_work refill_task;
498	struct work_struct watchdog_task;
499	struct work_struct linkstate_task;
500	struct delayed_work stats_task;
501	struct mlx4_en_perf_stats pstats;
502	struct mlx4_en_pkt_stats pkstats;
503	struct mlx4_en_port_stats port_stats;
504	struct dev_mc_list *mc_list;
505	struct mlx4_en_stat_out_mbox hw_stats;
506	};
507
508
509	void mlx4_en_destroy_netdev(struct net_device *dev);
510	int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
511	struct mlx4_en_port_profile *prof);
512
18cc42a3 YP	513	int mlx4_en_start_port(struct net_device *dev);
	514	void mlx4_en_stop_port(struct net_device *dev);
	515
	516	void mlx4_en_free_resources(struct mlx4_en_priv *priv);
	517	int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
	518
c27a02cd YP	519	int mlx4_en_get_profile(struct mlx4_en_dev *mdev);
	520
	521	int mlx4_en_create_cq(struct mlx4_en_priv priv, struct mlx4_en_cq cq,
	522	int entries, int ring, enum cq_type mode);
	523	void mlx4_en_destroy_cq(struct mlx4_en_priv priv, struct mlx4_en_cq cq);
	524	int mlx4_en_activate_cq(struct mlx4_en_priv priv, struct mlx4_en_cq cq);
	525	void mlx4_en_deactivate_cq(struct mlx4_en_priv priv, struct mlx4_en_cq cq);
	526	int mlx4_en_set_cq_moder(struct mlx4_en_priv priv, struct mlx4_en_cq cq);
	527	int mlx4_en_arm_cq(struct mlx4_en_priv priv, struct mlx4_en_cq cq);
	528
	529	void mlx4_en_poll_tx_cq(unsigned long data);
	530	void mlx4_en_tx_irq(struct mlx4_cq *mcq);
	531	int mlx4_en_xmit(struct sk_buff skb, struct net_device dev);
	532
	533	int mlx4_en_create_tx_ring(struct mlx4_en_priv priv, struct mlx4_en_tx_ring ring,
	534	u32 size, u16 stride);
	535	void mlx4_en_destroy_tx_ring(struct mlx4_en_priv priv, struct mlx4_en_tx_ring ring);
	536	int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
	537	struct mlx4_en_tx_ring *ring,
	538	int cq, int srqn);
	539	void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
	540	struct mlx4_en_tx_ring *ring);
	541
	542	int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
	543	struct mlx4_en_rx_ring *ring,
	544	u32 size, u16 stride);
	545	void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
	546	struct mlx4_en_rx_ring *ring);
	547	int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
	548	void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
	549	struct mlx4_en_rx_ring *ring);
	550	int mlx4_en_process_rx_cq(struct net_device *dev,
	551	struct mlx4_en_cq *cq,
	552	int budget);
	553	int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
	554	void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
	555	int is_tx, int rss, int qpn, int cqn, int srqn,
	556	struct mlx4_qp_context *context);
966508f7	557	void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
c27a02cd YP	558	int mlx4_en_map_buffer(struct mlx4_buf *buf);
	559	void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
	560
	561	void mlx4_en_calc_rx_buf(struct net_device *dev);
	562	void mlx4_en_set_default_rss_map(struct mlx4_en_priv *priv,
	563	struct mlx4_en_rss_map *rss_map,
	564	int num_entries, int num_rings);
	565	void mlx4_en_set_prio_map(struct mlx4_en_priv priv, u16 prio_map, u32 ring_num);
	566	int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
	567	void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
	568	int mlx4_en_free_tx_buf(struct net_device dev, struct mlx4_en_tx_ring ring);
	569	void mlx4_en_rx_refill(struct work_struct *work);
	570	void mlx4_en_rx_irq(struct mlx4_cq *mcq);
	571
	572	int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
	573	int mlx4_SET_VLAN_FLTR(struct mlx4_dev dev, u8 port, struct vlan_group grp);
	574	int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
	575	u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
	576	int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
	577	u8 promisc);
	578
	579	int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
	580
	581	/*
	582	* Globals
	583	*/
	584	extern const struct ethtool_ops mlx4_en_ethtool_ops;
	585	#endif