Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
9c1bbdfe | 2 | * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports |
1da177e4 LT |
3 | * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com> |
4 | * | |
5 | * Based on the 64360 driver from: | |
4547fa61 LB |
6 | * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il> |
7 | * Rabeeh Khoury <rabeeh@marvell.com> | |
1da177e4 LT |
8 | * |
9 | * Copyright (C) 2003 PMC-Sierra, Inc., | |
3bb8a18a | 10 | * written by Manish Lachwani |
1da177e4 LT |
11 | * |
12 | * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> | |
13 | * | |
c8aaea25 | 14 | * Copyright (C) 2004-2006 MontaVista Software, Inc. |
1da177e4 LT |
15 | * Dale Farnsworth <dale@farnsworth.org> |
16 | * | |
17 | * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com> | |
18 | * <sjhill@realitydiluted.com> | |
19 | * | |
4547fa61 LB |
20 | * Copyright (C) 2007-2008 Marvell Semiconductor |
21 | * Lennert Buytenhek <buytenh@marvell.com> | |
22 | * | |
1da177e4 LT |
23 | * This program is free software; you can redistribute it and/or |
24 | * modify it under the terms of the GNU General Public License | |
25 | * as published by the Free Software Foundation; either version 2 | |
26 | * of the License, or (at your option) any later version. | |
27 | * | |
28 | * This program is distributed in the hope that it will be useful, | |
29 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
30 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
31 | * GNU General Public License for more details. | |
32 | * | |
33 | * You should have received a copy of the GNU General Public License | |
34 | * along with this program; if not, write to the Free Software | |
35 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
36 | */ | |
a779d38c | 37 | |
1da177e4 LT |
38 | #include <linux/init.h> |
39 | #include <linux/dma-mapping.h> | |
b6298c22 | 40 | #include <linux/in.h> |
c3efab8e | 41 | #include <linux/ip.h> |
1da177e4 LT |
42 | #include <linux/tcp.h> |
43 | #include <linux/udp.h> | |
44 | #include <linux/etherdevice.h> | |
1da177e4 LT |
45 | #include <linux/delay.h> |
46 | #include <linux/ethtool.h> | |
d052d1be | 47 | #include <linux/platform_device.h> |
fbd6a754 LB |
48 | #include <linux/module.h> |
49 | #include <linux/kernel.h> | |
50 | #include <linux/spinlock.h> | |
51 | #include <linux/workqueue.h> | |
ed94493f | 52 | #include <linux/phy.h> |
fbd6a754 | 53 | #include <linux/mv643xx_eth.h> |
10a9948d LB |
54 | #include <linux/io.h> |
55 | #include <linux/types.h> | |
eaf5d590 | 56 | #include <linux/inet_lro.h> |
1da177e4 | 57 | #include <asm/system.h> |
fbd6a754 | 58 | |
e5371493 | 59 | static char mv643xx_eth_driver_name[] = "mv643xx_eth"; |
042af53c | 60 | static char mv643xx_eth_driver_version[] = "1.4"; |
c9df406f | 61 | |
fbd6a754 | 62 | |
fbd6a754 LB |
63 | /* |
64 | * Registers shared between all ports. | |
65 | */ | |
3cb4667c LB |
66 | #define PHY_ADDR 0x0000 |
67 | #define SMI_REG 0x0004 | |
45c5d3bc LB |
68 | #define SMI_BUSY 0x10000000 |
69 | #define SMI_READ_VALID 0x08000000 | |
70 | #define SMI_OPCODE_READ 0x04000000 | |
71 | #define SMI_OPCODE_WRITE 0x00000000 | |
72 | #define ERR_INT_CAUSE 0x0080 | |
73 | #define ERR_INT_SMI_DONE 0x00000010 | |
74 | #define ERR_INT_MASK 0x0084 | |
3cb4667c LB |
75 | #define WINDOW_BASE(w) (0x0200 + ((w) << 3)) |
76 | #define WINDOW_SIZE(w) (0x0204 + ((w) << 3)) | |
77 | #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2)) | |
78 | #define WINDOW_BAR_ENABLE 0x0290 | |
79 | #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4)) | |
fbd6a754 LB |
80 | |
81 | /* | |
37a6084f LB |
82 | * Main per-port registers. These live at offset 0x0400 for |
83 | * port #0, 0x0800 for port #1, and 0x0c00 for port #2. | |
fbd6a754 | 84 | */ |
37a6084f | 85 | #define PORT_CONFIG 0x0000 |
d9a073ea | 86 | #define UNICAST_PROMISCUOUS_MODE 0x00000001 |
37a6084f LB |
87 | #define PORT_CONFIG_EXT 0x0004 |
88 | #define MAC_ADDR_LOW 0x0014 | |
89 | #define MAC_ADDR_HIGH 0x0018 | |
90 | #define SDMA_CONFIG 0x001c | |
91 | #define PORT_SERIAL_CONTROL 0x003c | |
92 | #define PORT_STATUS 0x0044 | |
a2a41689 | 93 | #define TX_FIFO_EMPTY 0x00000400 |
ae9ae064 | 94 | #define TX_IN_PROGRESS 0x00000080 |
2f7eb47a LB |
95 | #define PORT_SPEED_MASK 0x00000030 |
96 | #define PORT_SPEED_1000 0x00000010 | |
97 | #define PORT_SPEED_100 0x00000020 | |
98 | #define PORT_SPEED_10 0x00000000 | |
99 | #define FLOW_CONTROL_ENABLED 0x00000008 | |
100 | #define FULL_DUPLEX 0x00000004 | |
81600eea | 101 | #define LINK_UP 0x00000002 |
37a6084f LB |
102 | #define TXQ_COMMAND 0x0048 |
103 | #define TXQ_FIX_PRIO_CONF 0x004c | |
104 | #define TX_BW_RATE 0x0050 | |
105 | #define TX_BW_MTU 0x0058 | |
106 | #define TX_BW_BURST 0x005c | |
107 | #define INT_CAUSE 0x0060 | |
226bb6b7 | 108 | #define INT_TX_END 0x07f80000 |
befefe21 | 109 | #define INT_RX 0x000003fc |
073a345c | 110 | #define INT_EXT 0x00000002 |
37a6084f | 111 | #define INT_CAUSE_EXT 0x0064 |
befefe21 LB |
112 | #define INT_EXT_LINK_PHY 0x00110000 |
113 | #define INT_EXT_TX 0x000000ff | |
37a6084f LB |
114 | #define INT_MASK 0x0068 |
115 | #define INT_MASK_EXT 0x006c | |
116 | #define TX_FIFO_URGENT_THRESHOLD 0x0074 | |
117 | #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc | |
118 | #define TX_BW_RATE_MOVED 0x00e0 | |
119 | #define TX_BW_MTU_MOVED 0x00e8 | |
120 | #define TX_BW_BURST_MOVED 0x00ec | |
121 | #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4)) | |
122 | #define RXQ_COMMAND 0x0280 | |
123 | #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2)) | |
124 | #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4)) | |
125 | #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4)) | |
126 | #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4)) | |
127 | ||
128 | /* | |
129 | * Misc per-port registers. | |
130 | */ | |
3cb4667c LB |
131 | #define MIB_COUNTERS(p) (0x1000 + ((p) << 7)) |
132 | #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10)) | |
133 | #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10)) | |
134 | #define UNICAST_TABLE(p) (0x1600 + ((p) << 10)) | |
fbd6a754 | 135 | |
2679a550 LB |
136 | |
137 | /* | |
138 | * SDMA configuration register. | |
139 | */ | |
e0c6ef93 | 140 | #define RX_BURST_SIZE_4_64BIT (2 << 1) |
cd4ccf76 | 141 | #define RX_BURST_SIZE_16_64BIT (4 << 1) |
fbd6a754 | 142 | #define BLM_RX_NO_SWAP (1 << 4) |
fbd6a754 | 143 | #define BLM_TX_NO_SWAP (1 << 5) |
e0c6ef93 | 144 | #define TX_BURST_SIZE_4_64BIT (2 << 22) |
cd4ccf76 | 145 | #define TX_BURST_SIZE_16_64BIT (4 << 22) |
fbd6a754 LB |
146 | |
147 | #if defined(__BIG_ENDIAN) | |
148 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | |
e0c6ef93 LB |
149 | (RX_BURST_SIZE_4_64BIT | \ |
150 | TX_BURST_SIZE_4_64BIT) | |
fbd6a754 LB |
151 | #elif defined(__LITTLE_ENDIAN) |
152 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | |
e0c6ef93 LB |
153 | (RX_BURST_SIZE_4_64BIT | \ |
154 | BLM_RX_NO_SWAP | \ | |
155 | BLM_TX_NO_SWAP | \ | |
156 | TX_BURST_SIZE_4_64BIT) | |
fbd6a754 LB |
157 | #else |
158 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | |
159 | #endif | |
160 | ||
2beff77b LB |
161 | |
162 | /* | |
163 | * Port serial control register. | |
164 | */ | |
165 | #define SET_MII_SPEED_TO_100 (1 << 24) | |
166 | #define SET_GMII_SPEED_TO_1000 (1 << 23) | |
167 | #define SET_FULL_DUPLEX_MODE (1 << 21) | |
fbd6a754 | 168 | #define MAX_RX_PACKET_9700BYTE (5 << 17) |
2beff77b LB |
169 | #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13) |
170 | #define DO_NOT_FORCE_LINK_FAIL (1 << 10) | |
171 | #define SERIAL_PORT_CONTROL_RESERVED (1 << 9) | |
172 | #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3) | |
173 | #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2) | |
174 | #define FORCE_LINK_PASS (1 << 1) | |
175 | #define SERIAL_PORT_ENABLE (1 << 0) | |
fbd6a754 | 176 | |
2b4a624d LB |
177 | #define DEFAULT_RX_QUEUE_SIZE 128 |
178 | #define DEFAULT_TX_QUEUE_SIZE 256 | |
fbd6a754 | 179 | |
fbd6a754 | 180 | |
7ca72a3b LB |
181 | /* |
182 | * RX/TX descriptors. | |
fbd6a754 LB |
183 | */ |
184 | #if defined(__BIG_ENDIAN) | |
cc9754b3 | 185 | struct rx_desc { |
fbd6a754 LB |
186 | u16 byte_cnt; /* Descriptor buffer byte count */ |
187 | u16 buf_size; /* Buffer size */ | |
188 | u32 cmd_sts; /* Descriptor command status */ | |
189 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
190 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
191 | }; | |
192 | ||
cc9754b3 | 193 | struct tx_desc { |
fbd6a754 LB |
194 | u16 byte_cnt; /* buffer byte count */ |
195 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
196 | u32 cmd_sts; /* Command/status field */ | |
197 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
198 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
199 | }; | |
200 | #elif defined(__LITTLE_ENDIAN) | |
cc9754b3 | 201 | struct rx_desc { |
fbd6a754 LB |
202 | u32 cmd_sts; /* Descriptor command status */ |
203 | u16 buf_size; /* Buffer size */ | |
204 | u16 byte_cnt; /* Descriptor buffer byte count */ | |
205 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
206 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
207 | }; | |
208 | ||
cc9754b3 | 209 | struct tx_desc { |
fbd6a754 LB |
210 | u32 cmd_sts; /* Command/status field */ |
211 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
212 | u16 byte_cnt; /* buffer byte count */ | |
213 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
214 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
215 | }; | |
216 | #else | |
217 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | |
218 | #endif | |
219 | ||
7ca72a3b | 220 | /* RX & TX descriptor command */ |
cc9754b3 | 221 | #define BUFFER_OWNED_BY_DMA 0x80000000 |
7ca72a3b LB |
222 | |
223 | /* RX & TX descriptor status */ | |
cc9754b3 | 224 | #define ERROR_SUMMARY 0x00000001 |
7ca72a3b LB |
225 | |
226 | /* RX descriptor status */ | |
cc9754b3 LB |
227 | #define LAYER_4_CHECKSUM_OK 0x40000000 |
228 | #define RX_ENABLE_INTERRUPT 0x20000000 | |
229 | #define RX_FIRST_DESC 0x08000000 | |
230 | #define RX_LAST_DESC 0x04000000 | |
eaf5d590 LB |
231 | #define RX_IP_HDR_OK 0x02000000 |
232 | #define RX_PKT_IS_IPV4 0x01000000 | |
233 | #define RX_PKT_IS_ETHERNETV2 0x00800000 | |
234 | #define RX_PKT_LAYER4_TYPE_MASK 0x00600000 | |
235 | #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000 | |
236 | #define RX_PKT_IS_VLAN_TAGGED 0x00080000 | |
7ca72a3b LB |
237 | |
238 | /* TX descriptor command */ | |
cc9754b3 LB |
239 | #define TX_ENABLE_INTERRUPT 0x00800000 |
240 | #define GEN_CRC 0x00400000 | |
241 | #define TX_FIRST_DESC 0x00200000 | |
242 | #define TX_LAST_DESC 0x00100000 | |
243 | #define ZERO_PADDING 0x00080000 | |
244 | #define GEN_IP_V4_CHECKSUM 0x00040000 | |
245 | #define GEN_TCP_UDP_CHECKSUM 0x00020000 | |
246 | #define UDP_FRAME 0x00010000 | |
e32b6617 LB |
247 | #define MAC_HDR_EXTRA_4_BYTES 0x00008000 |
248 | #define MAC_HDR_EXTRA_8_BYTES 0x00000200 | |
7ca72a3b | 249 | |
cc9754b3 | 250 | #define TX_IHL_SHIFT 11 |
7ca72a3b LB |
251 | |
252 | ||
c9df406f | 253 | /* global *******************************************************************/ |
e5371493 | 254 | struct mv643xx_eth_shared_private { |
fc32b0e2 LB |
255 | /* |
256 | * Ethernet controller base address. | |
257 | */ | |
cc9754b3 | 258 | void __iomem *base; |
c9df406f | 259 | |
fc0eb9f2 LB |
260 | /* |
261 | * Points at the right SMI instance to use. | |
262 | */ | |
263 | struct mv643xx_eth_shared_private *smi; | |
264 | ||
fc32b0e2 | 265 | /* |
ed94493f | 266 | * Provides access to local SMI interface. |
fc32b0e2 | 267 | */ |
298cf9be | 268 | struct mii_bus *smi_bus; |
c9df406f | 269 | |
45c5d3bc LB |
270 | /* |
271 | * If we have access to the error interrupt pin (which is | |
272 | * somewhat misnamed as it not only reflects internal errors | |
273 | * but also reflects SMI completion), use that to wait for | |
274 | * SMI access completion instead of polling the SMI busy bit. | |
275 | */ | |
276 | int err_interrupt; | |
277 | wait_queue_head_t smi_busy_wait; | |
278 | ||
fc32b0e2 LB |
279 | /* |
280 | * Per-port MBUS window access register value. | |
281 | */ | |
c9df406f LB |
282 | u32 win_protect; |
283 | ||
fc32b0e2 LB |
284 | /* |
285 | * Hardware-specific parameters. | |
286 | */ | |
c9df406f | 287 | unsigned int t_clk; |
773fc3ee | 288 | int extended_rx_coal_limit; |
457b1d5a | 289 | int tx_bw_control; |
c9df406f LB |
290 | }; |
291 | ||
457b1d5a LB |
292 | #define TX_BW_CONTROL_ABSENT 0 |
293 | #define TX_BW_CONTROL_OLD_LAYOUT 1 | |
294 | #define TX_BW_CONTROL_NEW_LAYOUT 2 | |
295 | ||
e7d2f4db LB |
296 | static int mv643xx_eth_open(struct net_device *dev); |
297 | static int mv643xx_eth_stop(struct net_device *dev); | |
298 | ||
c9df406f LB |
299 | |
300 | /* per-port *****************************************************************/ | |
e5371493 | 301 | struct mib_counters { |
fbd6a754 LB |
302 | u64 good_octets_received; |
303 | u32 bad_octets_received; | |
304 | u32 internal_mac_transmit_err; | |
305 | u32 good_frames_received; | |
306 | u32 bad_frames_received; | |
307 | u32 broadcast_frames_received; | |
308 | u32 multicast_frames_received; | |
309 | u32 frames_64_octets; | |
310 | u32 frames_65_to_127_octets; | |
311 | u32 frames_128_to_255_octets; | |
312 | u32 frames_256_to_511_octets; | |
313 | u32 frames_512_to_1023_octets; | |
314 | u32 frames_1024_to_max_octets; | |
315 | u64 good_octets_sent; | |
316 | u32 good_frames_sent; | |
317 | u32 excessive_collision; | |
318 | u32 multicast_frames_sent; | |
319 | u32 broadcast_frames_sent; | |
320 | u32 unrec_mac_control_received; | |
321 | u32 fc_sent; | |
322 | u32 good_fc_received; | |
323 | u32 bad_fc_received; | |
324 | u32 undersize_received; | |
325 | u32 fragments_received; | |
326 | u32 oversize_received; | |
327 | u32 jabber_received; | |
328 | u32 mac_receive_error; | |
329 | u32 bad_crc_event; | |
330 | u32 collision; | |
331 | u32 late_collision; | |
332 | }; | |
333 | ||
eaf5d590 LB |
334 | struct lro_counters { |
335 | u32 lro_aggregated; | |
336 | u32 lro_flushed; | |
337 | u32 lro_no_desc; | |
338 | }; | |
339 | ||
8a578111 | 340 | struct rx_queue { |
64da80a2 LB |
341 | int index; |
342 | ||
8a578111 LB |
343 | int rx_ring_size; |
344 | ||
345 | int rx_desc_count; | |
346 | int rx_curr_desc; | |
347 | int rx_used_desc; | |
348 | ||
349 | struct rx_desc *rx_desc_area; | |
350 | dma_addr_t rx_desc_dma; | |
351 | int rx_desc_area_size; | |
352 | struct sk_buff **rx_skb; | |
eaf5d590 LB |
353 | |
354 | #ifdef CONFIG_MV643XX_ETH_LRO | |
355 | struct net_lro_mgr lro_mgr; | |
356 | struct net_lro_desc lro_arr[8]; | |
357 | #endif | |
8a578111 LB |
358 | }; |
359 | ||
13d64285 | 360 | struct tx_queue { |
3d6b35bc LB |
361 | int index; |
362 | ||
13d64285 | 363 | int tx_ring_size; |
fbd6a754 | 364 | |
13d64285 LB |
365 | int tx_desc_count; |
366 | int tx_curr_desc; | |
367 | int tx_used_desc; | |
fbd6a754 | 368 | |
5daffe94 | 369 | struct tx_desc *tx_desc_area; |
fbd6a754 LB |
370 | dma_addr_t tx_desc_dma; |
371 | int tx_desc_area_size; | |
99ab08e0 LB |
372 | |
373 | struct sk_buff_head tx_skb; | |
8fd89211 LB |
374 | |
375 | unsigned long tx_packets; | |
376 | unsigned long tx_bytes; | |
377 | unsigned long tx_dropped; | |
13d64285 LB |
378 | }; |
379 | ||
380 | struct mv643xx_eth_private { | |
381 | struct mv643xx_eth_shared_private *shared; | |
37a6084f | 382 | void __iomem *base; |
fc32b0e2 | 383 | int port_num; |
13d64285 | 384 | |
fc32b0e2 | 385 | struct net_device *dev; |
fbd6a754 | 386 | |
ed94493f | 387 | struct phy_device *phy; |
fbd6a754 | 388 | |
4ff3495a LB |
389 | struct timer_list mib_counters_timer; |
390 | spinlock_t mib_counters_lock; | |
fc32b0e2 | 391 | struct mib_counters mib_counters; |
4ff3495a | 392 | |
eaf5d590 LB |
393 | struct lro_counters lro_counters; |
394 | ||
fc32b0e2 | 395 | struct work_struct tx_timeout_task; |
8a578111 | 396 | |
1fa38c58 LB |
397 | struct napi_struct napi; |
398 | u8 work_link; | |
399 | u8 work_tx; | |
400 | u8 work_tx_end; | |
401 | u8 work_rx; | |
402 | u8 work_rx_refill; | |
403 | u8 work_rx_oom; | |
404 | ||
2bcb4b0f LB |
405 | int skb_size; |
406 | struct sk_buff_head rx_recycle; | |
407 | ||
8a578111 LB |
408 | /* |
409 | * RX state. | |
410 | */ | |
e7d2f4db | 411 | int rx_ring_size; |
8a578111 LB |
412 | unsigned long rx_desc_sram_addr; |
413 | int rx_desc_sram_size; | |
f7981c1c | 414 | int rxq_count; |
2257e05c | 415 | struct timer_list rx_oom; |
64da80a2 | 416 | struct rx_queue rxq[8]; |
13d64285 LB |
417 | |
418 | /* | |
419 | * TX state. | |
420 | */ | |
e7d2f4db | 421 | int tx_ring_size; |
13d64285 LB |
422 | unsigned long tx_desc_sram_addr; |
423 | int tx_desc_sram_size; | |
f7981c1c | 424 | int txq_count; |
3d6b35bc | 425 | struct tx_queue txq[8]; |
fbd6a754 | 426 | }; |
1da177e4 | 427 | |
fbd6a754 | 428 | |
c9df406f | 429 | /* port register accessors **************************************************/ |
e5371493 | 430 | static inline u32 rdl(struct mv643xx_eth_private *mp, int offset) |
c9df406f | 431 | { |
cc9754b3 | 432 | return readl(mp->shared->base + offset); |
c9df406f | 433 | } |
fbd6a754 | 434 | |
37a6084f LB |
435 | static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset) |
436 | { | |
437 | return readl(mp->base + offset); | |
438 | } | |
439 | ||
e5371493 | 440 | static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data) |
c9df406f | 441 | { |
cc9754b3 | 442 | writel(data, mp->shared->base + offset); |
c9df406f | 443 | } |
fbd6a754 | 444 | |
37a6084f LB |
445 | static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data) |
446 | { | |
447 | writel(data, mp->base + offset); | |
448 | } | |
449 | ||
fbd6a754 | 450 | |
c9df406f | 451 | /* rxq/txq helper functions *************************************************/ |
8a578111 | 452 | static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq) |
c9df406f | 453 | { |
64da80a2 | 454 | return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]); |
c9df406f | 455 | } |
fbd6a754 | 456 | |
13d64285 LB |
457 | static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq) |
458 | { | |
3d6b35bc | 459 | return container_of(txq, struct mv643xx_eth_private, txq[txq->index]); |
13d64285 LB |
460 | } |
461 | ||
8a578111 | 462 | static void rxq_enable(struct rx_queue *rxq) |
c9df406f | 463 | { |
8a578111 | 464 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
37a6084f | 465 | wrlp(mp, RXQ_COMMAND, 1 << rxq->index); |
8a578111 | 466 | } |
1da177e4 | 467 | |
8a578111 LB |
468 | static void rxq_disable(struct rx_queue *rxq) |
469 | { | |
470 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); | |
64da80a2 | 471 | u8 mask = 1 << rxq->index; |
1da177e4 | 472 | |
37a6084f LB |
473 | wrlp(mp, RXQ_COMMAND, mask << 8); |
474 | while (rdlp(mp, RXQ_COMMAND) & mask) | |
8a578111 | 475 | udelay(10); |
c9df406f LB |
476 | } |
477 | ||
6b368f68 LB |
478 | static void txq_reset_hw_ptr(struct tx_queue *txq) |
479 | { | |
480 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
6b368f68 LB |
481 | u32 addr; |
482 | ||
483 | addr = (u32)txq->tx_desc_dma; | |
484 | addr += txq->tx_curr_desc * sizeof(struct tx_desc); | |
37a6084f | 485 | wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr); |
6b368f68 LB |
486 | } |
487 | ||
13d64285 | 488 | static void txq_enable(struct tx_queue *txq) |
1da177e4 | 489 | { |
13d64285 | 490 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
37a6084f | 491 | wrlp(mp, TXQ_COMMAND, 1 << txq->index); |
1da177e4 LT |
492 | } |
493 | ||
13d64285 | 494 | static void txq_disable(struct tx_queue *txq) |
1da177e4 | 495 | { |
13d64285 | 496 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
3d6b35bc | 497 | u8 mask = 1 << txq->index; |
c9df406f | 498 | |
37a6084f LB |
499 | wrlp(mp, TXQ_COMMAND, mask << 8); |
500 | while (rdlp(mp, TXQ_COMMAND) & mask) | |
13d64285 LB |
501 | udelay(10); |
502 | } | |
503 | ||
1fa38c58 | 504 | static void txq_maybe_wake(struct tx_queue *txq) |
13d64285 LB |
505 | { |
506 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
e5ef1de1 | 507 | struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); |
3d6b35bc | 508 | |
8fd89211 LB |
509 | if (netif_tx_queue_stopped(nq)) { |
510 | __netif_tx_lock(nq, smp_processor_id()); | |
511 | if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1) | |
512 | netif_tx_wake_queue(nq); | |
513 | __netif_tx_unlock(nq); | |
514 | } | |
1da177e4 LT |
515 | } |
516 | ||
c9df406f | 517 | |
1fa38c58 | 518 | /* rx napi ******************************************************************/ |
eaf5d590 LB |
519 | #ifdef CONFIG_MV643XX_ETH_LRO |
520 | static int | |
521 | mv643xx_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph, | |
522 | u64 *hdr_flags, void *priv) | |
523 | { | |
524 | unsigned long cmd_sts = (unsigned long)priv; | |
525 | ||
526 | /* | |
527 | * Make sure that this packet is Ethernet II, is not VLAN | |
528 | * tagged, is IPv4, has a valid IP header, and is TCP. | |
529 | */ | |
530 | if ((cmd_sts & (RX_IP_HDR_OK | RX_PKT_IS_IPV4 | | |
531 | RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_MASK | | |
532 | RX_PKT_IS_VLAN_TAGGED)) != | |
533 | (RX_IP_HDR_OK | RX_PKT_IS_IPV4 | | |
534 | RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_TCP_IPV4)) | |
535 | return -1; | |
536 | ||
537 | skb_reset_network_header(skb); | |
538 | skb_set_transport_header(skb, ip_hdrlen(skb)); | |
539 | *iphdr = ip_hdr(skb); | |
540 | *tcph = tcp_hdr(skb); | |
541 | *hdr_flags = LRO_IPV4 | LRO_TCP; | |
542 | ||
543 | return 0; | |
544 | } | |
545 | #endif | |
546 | ||
8a578111 | 547 | static int rxq_process(struct rx_queue *rxq, int budget) |
1da177e4 | 548 | { |
8a578111 LB |
549 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
550 | struct net_device_stats *stats = &mp->dev->stats; | |
eaf5d590 | 551 | int lro_flush_needed; |
8a578111 | 552 | int rx; |
1da177e4 | 553 | |
eaf5d590 | 554 | lro_flush_needed = 0; |
8a578111 | 555 | rx = 0; |
9e1f3772 | 556 | while (rx < budget && rxq->rx_desc_count) { |
fc32b0e2 | 557 | struct rx_desc *rx_desc; |
96587661 | 558 | unsigned int cmd_sts; |
fc32b0e2 | 559 | struct sk_buff *skb; |
6b8f90c2 | 560 | u16 byte_cnt; |
ff561eef | 561 | |
8a578111 | 562 | rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc]; |
1da177e4 | 563 | |
96587661 | 564 | cmd_sts = rx_desc->cmd_sts; |
2257e05c | 565 | if (cmd_sts & BUFFER_OWNED_BY_DMA) |
96587661 | 566 | break; |
96587661 | 567 | rmb(); |
1da177e4 | 568 | |
8a578111 LB |
569 | skb = rxq->rx_skb[rxq->rx_curr_desc]; |
570 | rxq->rx_skb[rxq->rx_curr_desc] = NULL; | |
ff561eef | 571 | |
9da78745 LB |
572 | rxq->rx_curr_desc++; |
573 | if (rxq->rx_curr_desc == rxq->rx_ring_size) | |
574 | rxq->rx_curr_desc = 0; | |
ff561eef | 575 | |
3a499481 | 576 | dma_unmap_single(NULL, rx_desc->buf_ptr, |
abe78717 | 577 | rx_desc->buf_size, DMA_FROM_DEVICE); |
8a578111 LB |
578 | rxq->rx_desc_count--; |
579 | rx++; | |
b1dd9ca1 | 580 | |
1fa38c58 LB |
581 | mp->work_rx_refill |= 1 << rxq->index; |
582 | ||
6b8f90c2 LB |
583 | byte_cnt = rx_desc->byte_cnt; |
584 | ||
468d09f8 DF |
585 | /* |
586 | * Update statistics. | |
fc32b0e2 LB |
587 | * |
588 | * Note that the descriptor byte count includes 2 dummy | |
589 | * bytes automatically inserted by the hardware at the | |
590 | * start of the packet (which we don't count), and a 4 | |
591 | * byte CRC at the end of the packet (which we do count). | |
468d09f8 | 592 | */ |
1da177e4 | 593 | stats->rx_packets++; |
6b8f90c2 | 594 | stats->rx_bytes += byte_cnt - 2; |
96587661 | 595 | |
1da177e4 | 596 | /* |
fc32b0e2 LB |
597 | * In case we received a packet without first / last bits |
598 | * on, or the error summary bit is set, the packet needs | |
599 | * to be dropped. | |
1da177e4 | 600 | */ |
f61e5547 LB |
601 | if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY)) |
602 | != (RX_FIRST_DESC | RX_LAST_DESC)) | |
603 | goto err; | |
604 | ||
605 | /* | |
606 | * The -4 is for the CRC in the trailer of the | |
607 | * received packet | |
608 | */ | |
609 | skb_put(skb, byte_cnt - 2 - 4); | |
610 | ||
611 | if (cmd_sts & LAYER_4_CHECKSUM_OK) | |
612 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
613 | skb->protocol = eth_type_trans(skb, mp->dev); | |
eaf5d590 LB |
614 | |
615 | #ifdef CONFIG_MV643XX_ETH_LRO | |
616 | if (skb->dev->features & NETIF_F_LRO && | |
617 | skb->ip_summed == CHECKSUM_UNNECESSARY) { | |
618 | lro_receive_skb(&rxq->lro_mgr, skb, (void *)cmd_sts); | |
619 | lro_flush_needed = 1; | |
620 | } else | |
621 | #endif | |
622 | netif_receive_skb(skb); | |
f61e5547 LB |
623 | |
624 | continue; | |
625 | ||
626 | err: | |
627 | stats->rx_dropped++; | |
628 | ||
629 | if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != | |
630 | (RX_FIRST_DESC | RX_LAST_DESC)) { | |
631 | if (net_ratelimit()) | |
632 | dev_printk(KERN_ERR, &mp->dev->dev, | |
633 | "received packet spanning " | |
634 | "multiple descriptors\n"); | |
1da177e4 | 635 | } |
f61e5547 LB |
636 | |
637 | if (cmd_sts & ERROR_SUMMARY) | |
638 | stats->rx_errors++; | |
639 | ||
640 | dev_kfree_skb(skb); | |
1da177e4 | 641 | } |
fc32b0e2 | 642 | |
eaf5d590 LB |
643 | #ifdef CONFIG_MV643XX_ETH_LRO |
644 | if (lro_flush_needed) | |
645 | lro_flush_all(&rxq->lro_mgr); | |
646 | #endif | |
647 | ||
1fa38c58 LB |
648 | if (rx < budget) |
649 | mp->work_rx &= ~(1 << rxq->index); | |
650 | ||
8a578111 | 651 | return rx; |
1da177e4 LT |
652 | } |
653 | ||
1fa38c58 | 654 | static int rxq_refill(struct rx_queue *rxq, int budget) |
d0412d96 | 655 | { |
1fa38c58 | 656 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
1fa38c58 | 657 | int refilled; |
8a578111 | 658 | |
1fa38c58 LB |
659 | refilled = 0; |
660 | while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) { | |
661 | struct sk_buff *skb; | |
662 | int unaligned; | |
663 | int rx; | |
53771522 | 664 | struct rx_desc *rx_desc; |
d0412d96 | 665 | |
2bcb4b0f LB |
666 | skb = __skb_dequeue(&mp->rx_recycle); |
667 | if (skb == NULL) | |
668 | skb = dev_alloc_skb(mp->skb_size + | |
669 | dma_get_cache_alignment() - 1); | |
670 | ||
1fa38c58 LB |
671 | if (skb == NULL) { |
672 | mp->work_rx_oom |= 1 << rxq->index; | |
673 | goto oom; | |
674 | } | |
d0412d96 | 675 | |
1fa38c58 LB |
676 | unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1); |
677 | if (unaligned) | |
678 | skb_reserve(skb, dma_get_cache_alignment() - unaligned); | |
2257e05c | 679 | |
1fa38c58 LB |
680 | refilled++; |
681 | rxq->rx_desc_count++; | |
c9df406f | 682 | |
1fa38c58 LB |
683 | rx = rxq->rx_used_desc++; |
684 | if (rxq->rx_used_desc == rxq->rx_ring_size) | |
685 | rxq->rx_used_desc = 0; | |
2257e05c | 686 | |
53771522 LB |
687 | rx_desc = rxq->rx_desc_area + rx; |
688 | ||
689 | rx_desc->buf_ptr = dma_map_single(NULL, skb->data, | |
690 | mp->skb_size, DMA_FROM_DEVICE); | |
691 | rx_desc->buf_size = mp->skb_size; | |
1fa38c58 LB |
692 | rxq->rx_skb[rx] = skb; |
693 | wmb(); | |
53771522 | 694 | rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT; |
1fa38c58 | 695 | wmb(); |
2257e05c | 696 | |
1fa38c58 LB |
697 | /* |
698 | * The hardware automatically prepends 2 bytes of | |
699 | * dummy data to each received packet, so that the | |
700 | * IP header ends up 16-byte aligned. | |
701 | */ | |
702 | skb_reserve(skb, 2); | |
703 | } | |
704 | ||
705 | if (refilled < budget) | |
706 | mp->work_rx_refill &= ~(1 << rxq->index); | |
707 | ||
708 | oom: | |
709 | return refilled; | |
d0412d96 JC |
710 | } |
711 | ||
c9df406f LB |
712 | |
713 | /* tx ***********************************************************************/ | |
c9df406f | 714 | static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) |
1da177e4 | 715 | { |
13d64285 | 716 | int frag; |
1da177e4 | 717 | |
c9df406f | 718 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { |
13d64285 LB |
719 | skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag]; |
720 | if (fragp->size <= 8 && fragp->page_offset & 7) | |
c9df406f | 721 | return 1; |
1da177e4 | 722 | } |
13d64285 | 723 | |
c9df406f LB |
724 | return 0; |
725 | } | |
7303fde8 | 726 | |
13d64285 | 727 | static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb) |
c9df406f | 728 | { |
13d64285 | 729 | int nr_frags = skb_shinfo(skb)->nr_frags; |
c9df406f | 730 | int frag; |
1da177e4 | 731 | |
13d64285 LB |
732 | for (frag = 0; frag < nr_frags; frag++) { |
733 | skb_frag_t *this_frag; | |
734 | int tx_index; | |
735 | struct tx_desc *desc; | |
736 | ||
737 | this_frag = &skb_shinfo(skb)->frags[frag]; | |
66823b92 LB |
738 | tx_index = txq->tx_curr_desc++; |
739 | if (txq->tx_curr_desc == txq->tx_ring_size) | |
740 | txq->tx_curr_desc = 0; | |
13d64285 LB |
741 | desc = &txq->tx_desc_area[tx_index]; |
742 | ||
743 | /* | |
744 | * The last fragment will generate an interrupt | |
745 | * which will free the skb on TX completion. | |
746 | */ | |
747 | if (frag == nr_frags - 1) { | |
748 | desc->cmd_sts = BUFFER_OWNED_BY_DMA | | |
749 | ZERO_PADDING | TX_LAST_DESC | | |
750 | TX_ENABLE_INTERRUPT; | |
13d64285 LB |
751 | } else { |
752 | desc->cmd_sts = BUFFER_OWNED_BY_DMA; | |
13d64285 LB |
753 | } |
754 | ||
c9df406f LB |
755 | desc->l4i_chk = 0; |
756 | desc->byte_cnt = this_frag->size; | |
757 | desc->buf_ptr = dma_map_page(NULL, this_frag->page, | |
758 | this_frag->page_offset, | |
759 | this_frag->size, | |
760 | DMA_TO_DEVICE); | |
761 | } | |
1da177e4 LT |
762 | } |
763 | ||
c9df406f LB |
764 | static inline __be16 sum16_as_be(__sum16 sum) |
765 | { | |
766 | return (__force __be16)sum; | |
767 | } | |
1da177e4 | 768 | |
4df89bd5 | 769 | static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb) |
1da177e4 | 770 | { |
8fa89bf5 | 771 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
13d64285 | 772 | int nr_frags = skb_shinfo(skb)->nr_frags; |
c9df406f | 773 | int tx_index; |
cc9754b3 | 774 | struct tx_desc *desc; |
c9df406f | 775 | u32 cmd_sts; |
4df89bd5 | 776 | u16 l4i_chk; |
c9df406f | 777 | int length; |
1da177e4 | 778 | |
cc9754b3 | 779 | cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA; |
4df89bd5 | 780 | l4i_chk = 0; |
c9df406f LB |
781 | |
782 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
4df89bd5 | 783 | int tag_bytes; |
e32b6617 LB |
784 | |
785 | BUG_ON(skb->protocol != htons(ETH_P_IP) && | |
786 | skb->protocol != htons(ETH_P_8021Q)); | |
c9df406f | 787 | |
4df89bd5 LB |
788 | tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN; |
789 | if (unlikely(tag_bytes & ~12)) { | |
790 | if (skb_checksum_help(skb) == 0) | |
791 | goto no_csum; | |
792 | kfree_skb(skb); | |
793 | return 1; | |
794 | } | |
c9df406f | 795 | |
4df89bd5 | 796 | if (tag_bytes & 4) |
e32b6617 | 797 | cmd_sts |= MAC_HDR_EXTRA_4_BYTES; |
4df89bd5 | 798 | if (tag_bytes & 8) |
e32b6617 | 799 | cmd_sts |= MAC_HDR_EXTRA_8_BYTES; |
4df89bd5 LB |
800 | |
801 | cmd_sts |= GEN_TCP_UDP_CHECKSUM | | |
802 | GEN_IP_V4_CHECKSUM | | |
803 | ip_hdr(skb)->ihl << TX_IHL_SHIFT; | |
e32b6617 | 804 | |
c9df406f LB |
805 | switch (ip_hdr(skb)->protocol) { |
806 | case IPPROTO_UDP: | |
cc9754b3 | 807 | cmd_sts |= UDP_FRAME; |
4df89bd5 | 808 | l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check)); |
c9df406f LB |
809 | break; |
810 | case IPPROTO_TCP: | |
4df89bd5 | 811 | l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check)); |
c9df406f LB |
812 | break; |
813 | default: | |
814 | BUG(); | |
815 | } | |
816 | } else { | |
4df89bd5 | 817 | no_csum: |
c9df406f | 818 | /* Errata BTS #50, IHL must be 5 if no HW checksum */ |
cc9754b3 | 819 | cmd_sts |= 5 << TX_IHL_SHIFT; |
c9df406f LB |
820 | } |
821 | ||
66823b92 LB |
822 | tx_index = txq->tx_curr_desc++; |
823 | if (txq->tx_curr_desc == txq->tx_ring_size) | |
824 | txq->tx_curr_desc = 0; | |
4df89bd5 LB |
825 | desc = &txq->tx_desc_area[tx_index]; |
826 | ||
827 | if (nr_frags) { | |
828 | txq_submit_frag_skb(txq, skb); | |
829 | length = skb_headlen(skb); | |
830 | } else { | |
831 | cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT; | |
832 | length = skb->len; | |
833 | } | |
834 | ||
835 | desc->l4i_chk = l4i_chk; | |
836 | desc->byte_cnt = length; | |
837 | desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE); | |
838 | ||
99ab08e0 LB |
839 | __skb_queue_tail(&txq->tx_skb, skb); |
840 | ||
c9df406f LB |
841 | /* ensure all other descriptors are written before first cmd_sts */ |
842 | wmb(); | |
843 | desc->cmd_sts = cmd_sts; | |
844 | ||
1fa38c58 LB |
845 | /* clear TX_END status */ |
846 | mp->work_tx_end &= ~(1 << txq->index); | |
8fa89bf5 | 847 | |
c9df406f LB |
848 | /* ensure all descriptors are written before poking hardware */ |
849 | wmb(); | |
13d64285 | 850 | txq_enable(txq); |
c9df406f | 851 | |
13d64285 | 852 | txq->tx_desc_count += nr_frags + 1; |
4df89bd5 LB |
853 | |
854 | return 0; | |
1da177e4 | 855 | } |
1da177e4 | 856 | |
fc32b0e2 | 857 | static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 858 | { |
e5371493 | 859 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
e5ef1de1 | 860 | int queue; |
13d64285 | 861 | struct tx_queue *txq; |
e5ef1de1 | 862 | struct netdev_queue *nq; |
afdb57a2 | 863 | |
8fd89211 LB |
864 | queue = skb_get_queue_mapping(skb); |
865 | txq = mp->txq + queue; | |
866 | nq = netdev_get_tx_queue(dev, queue); | |
867 | ||
c9df406f | 868 | if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) { |
8fd89211 | 869 | txq->tx_dropped++; |
fc32b0e2 LB |
870 | dev_printk(KERN_DEBUG, &dev->dev, |
871 | "failed to linearize skb with tiny " | |
872 | "unaligned fragment\n"); | |
c9df406f LB |
873 | return NETDEV_TX_BUSY; |
874 | } | |
875 | ||
17cd0a59 | 876 | if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) { |
e5ef1de1 LB |
877 | if (net_ratelimit()) |
878 | dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n"); | |
3d6b35bc LB |
879 | kfree_skb(skb); |
880 | return NETDEV_TX_OK; | |
c9df406f LB |
881 | } |
882 | ||
4df89bd5 LB |
883 | if (!txq_submit_skb(txq, skb)) { |
884 | int entries_left; | |
885 | ||
886 | txq->tx_bytes += skb->len; | |
887 | txq->tx_packets++; | |
888 | dev->trans_start = jiffies; | |
c9df406f | 889 | |
4df89bd5 LB |
890 | entries_left = txq->tx_ring_size - txq->tx_desc_count; |
891 | if (entries_left < MAX_SKB_FRAGS + 1) | |
892 | netif_tx_stop_queue(nq); | |
893 | } | |
c9df406f | 894 | |
c9df406f | 895 | return NETDEV_TX_OK; |
1da177e4 LT |
896 | } |
897 | ||
c9df406f | 898 | |
1fa38c58 LB |
899 | /* tx napi ******************************************************************/ |
900 | static void txq_kick(struct tx_queue *txq) | |
901 | { | |
902 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
8fd89211 | 903 | struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); |
1fa38c58 LB |
904 | u32 hw_desc_ptr; |
905 | u32 expected_ptr; | |
906 | ||
8fd89211 | 907 | __netif_tx_lock(nq, smp_processor_id()); |
1fa38c58 | 908 | |
37a6084f | 909 | if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index)) |
1fa38c58 LB |
910 | goto out; |
911 | ||
37a6084f | 912 | hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index)); |
1fa38c58 LB |
913 | expected_ptr = (u32)txq->tx_desc_dma + |
914 | txq->tx_curr_desc * sizeof(struct tx_desc); | |
915 | ||
916 | if (hw_desc_ptr != expected_ptr) | |
917 | txq_enable(txq); | |
918 | ||
919 | out: | |
8fd89211 | 920 | __netif_tx_unlock(nq); |
1fa38c58 LB |
921 | |
922 | mp->work_tx_end &= ~(1 << txq->index); | |
923 | } | |
924 | ||
925 | static int txq_reclaim(struct tx_queue *txq, int budget, int force) | |
926 | { | |
927 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
8fd89211 | 928 | struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); |
1fa38c58 LB |
929 | int reclaimed; |
930 | ||
8fd89211 | 931 | __netif_tx_lock(nq, smp_processor_id()); |
1fa38c58 LB |
932 | |
933 | reclaimed = 0; | |
934 | while (reclaimed < budget && txq->tx_desc_count > 0) { | |
935 | int tx_index; | |
936 | struct tx_desc *desc; | |
937 | u32 cmd_sts; | |
938 | struct sk_buff *skb; | |
1fa38c58 LB |
939 | |
940 | tx_index = txq->tx_used_desc; | |
941 | desc = &txq->tx_desc_area[tx_index]; | |
942 | cmd_sts = desc->cmd_sts; | |
943 | ||
944 | if (cmd_sts & BUFFER_OWNED_BY_DMA) { | |
945 | if (!force) | |
946 | break; | |
947 | desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA; | |
948 | } | |
949 | ||
950 | txq->tx_used_desc = tx_index + 1; | |
951 | if (txq->tx_used_desc == txq->tx_ring_size) | |
952 | txq->tx_used_desc = 0; | |
953 | ||
954 | reclaimed++; | |
955 | txq->tx_desc_count--; | |
956 | ||
99ab08e0 LB |
957 | skb = NULL; |
958 | if (cmd_sts & TX_LAST_DESC) | |
959 | skb = __skb_dequeue(&txq->tx_skb); | |
1fa38c58 LB |
960 | |
961 | if (cmd_sts & ERROR_SUMMARY) { | |
962 | dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n"); | |
963 | mp->dev->stats.tx_errors++; | |
964 | } | |
965 | ||
a418950c LB |
966 | if (cmd_sts & TX_FIRST_DESC) { |
967 | dma_unmap_single(NULL, desc->buf_ptr, | |
968 | desc->byte_cnt, DMA_TO_DEVICE); | |
969 | } else { | |
970 | dma_unmap_page(NULL, desc->buf_ptr, | |
971 | desc->byte_cnt, DMA_TO_DEVICE); | |
972 | } | |
1fa38c58 | 973 | |
2bcb4b0f LB |
974 | if (skb != NULL) { |
975 | if (skb_queue_len(&mp->rx_recycle) < | |
e7d2f4db | 976 | mp->rx_ring_size && |
11b4aa03 LB |
977 | skb_recycle_check(skb, mp->skb_size + |
978 | dma_get_cache_alignment() - 1)) | |
2bcb4b0f LB |
979 | __skb_queue_head(&mp->rx_recycle, skb); |
980 | else | |
981 | dev_kfree_skb(skb); | |
982 | } | |
1fa38c58 LB |
983 | } |
984 | ||
8fd89211 LB |
985 | __netif_tx_unlock(nq); |
986 | ||
1fa38c58 LB |
987 | if (reclaimed < budget) |
988 | mp->work_tx &= ~(1 << txq->index); | |
989 | ||
1fa38c58 LB |
990 | return reclaimed; |
991 | } | |
992 | ||
993 | ||
89df5fdc LB |
994 | /* tx rate control **********************************************************/ |
995 | /* | |
996 | * Set total maximum TX rate (shared by all TX queues for this port) | |
997 | * to 'rate' bits per second, with a maximum burst of 'burst' bytes. | |
998 | */ | |
999 | static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst) | |
1000 | { | |
1001 | int token_rate; | |
1002 | int mtu; | |
1003 | int bucket_size; | |
1004 | ||
1005 | token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000); | |
1006 | if (token_rate > 1023) | |
1007 | token_rate = 1023; | |
1008 | ||
1009 | mtu = (mp->dev->mtu + 255) >> 8; | |
1010 | if (mtu > 63) | |
1011 | mtu = 63; | |
1012 | ||
1013 | bucket_size = (burst + 255) >> 8; | |
1014 | if (bucket_size > 65535) | |
1015 | bucket_size = 65535; | |
1016 | ||
457b1d5a LB |
1017 | switch (mp->shared->tx_bw_control) { |
1018 | case TX_BW_CONTROL_OLD_LAYOUT: | |
37a6084f LB |
1019 | wrlp(mp, TX_BW_RATE, token_rate); |
1020 | wrlp(mp, TX_BW_MTU, mtu); | |
1021 | wrlp(mp, TX_BW_BURST, bucket_size); | |
457b1d5a LB |
1022 | break; |
1023 | case TX_BW_CONTROL_NEW_LAYOUT: | |
37a6084f LB |
1024 | wrlp(mp, TX_BW_RATE_MOVED, token_rate); |
1025 | wrlp(mp, TX_BW_MTU_MOVED, mtu); | |
1026 | wrlp(mp, TX_BW_BURST_MOVED, bucket_size); | |
457b1d5a | 1027 | break; |
1e881592 | 1028 | } |
89df5fdc LB |
1029 | } |
1030 | ||
1031 | static void txq_set_rate(struct tx_queue *txq, int rate, int burst) | |
1032 | { | |
1033 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
1034 | int token_rate; | |
1035 | int bucket_size; | |
1036 | ||
1037 | token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000); | |
1038 | if (token_rate > 1023) | |
1039 | token_rate = 1023; | |
1040 | ||
1041 | bucket_size = (burst + 255) >> 8; | |
1042 | if (bucket_size > 65535) | |
1043 | bucket_size = 65535; | |
1044 | ||
37a6084f LB |
1045 | wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14); |
1046 | wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate); | |
89df5fdc LB |
1047 | } |
1048 | ||
1049 | static void txq_set_fixed_prio_mode(struct tx_queue *txq) | |
1050 | { | |
1051 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
1052 | int off; | |
1053 | u32 val; | |
1054 | ||
1055 | /* | |
1056 | * Turn on fixed priority mode. | |
1057 | */ | |
457b1d5a LB |
1058 | off = 0; |
1059 | switch (mp->shared->tx_bw_control) { | |
1060 | case TX_BW_CONTROL_OLD_LAYOUT: | |
37a6084f | 1061 | off = TXQ_FIX_PRIO_CONF; |
457b1d5a LB |
1062 | break; |
1063 | case TX_BW_CONTROL_NEW_LAYOUT: | |
37a6084f | 1064 | off = TXQ_FIX_PRIO_CONF_MOVED; |
457b1d5a LB |
1065 | break; |
1066 | } | |
89df5fdc | 1067 | |
457b1d5a | 1068 | if (off) { |
37a6084f | 1069 | val = rdlp(mp, off); |
457b1d5a | 1070 | val |= 1 << txq->index; |
37a6084f | 1071 | wrlp(mp, off, val); |
457b1d5a | 1072 | } |
89df5fdc LB |
1073 | } |
1074 | ||
1075 | static void txq_set_wrr(struct tx_queue *txq, int weight) | |
1076 | { | |
1077 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
1078 | int off; | |
1079 | u32 val; | |
1080 | ||
1081 | /* | |
1082 | * Turn off fixed priority mode. | |
1083 | */ | |
457b1d5a LB |
1084 | off = 0; |
1085 | switch (mp->shared->tx_bw_control) { | |
1086 | case TX_BW_CONTROL_OLD_LAYOUT: | |
37a6084f | 1087 | off = TXQ_FIX_PRIO_CONF; |
457b1d5a LB |
1088 | break; |
1089 | case TX_BW_CONTROL_NEW_LAYOUT: | |
37a6084f | 1090 | off = TXQ_FIX_PRIO_CONF_MOVED; |
457b1d5a LB |
1091 | break; |
1092 | } | |
89df5fdc | 1093 | |
457b1d5a | 1094 | if (off) { |
37a6084f | 1095 | val = rdlp(mp, off); |
457b1d5a | 1096 | val &= ~(1 << txq->index); |
37a6084f | 1097 | wrlp(mp, off, val); |
89df5fdc | 1098 | |
457b1d5a LB |
1099 | /* |
1100 | * Configure WRR weight for this queue. | |
1101 | */ | |
89df5fdc | 1102 | |
37a6084f | 1103 | val = rdlp(mp, off); |
457b1d5a | 1104 | val = (val & ~0xff) | (weight & 0xff); |
37a6084f | 1105 | wrlp(mp, TXQ_BW_WRR_CONF(txq->index), val); |
457b1d5a | 1106 | } |
89df5fdc LB |
1107 | } |
1108 | ||
1109 | ||
c9df406f | 1110 | /* mii management interface *************************************************/ |
45c5d3bc LB |
1111 | static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id) |
1112 | { | |
1113 | struct mv643xx_eth_shared_private *msp = dev_id; | |
1114 | ||
1115 | if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) { | |
1116 | writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE); | |
1117 | wake_up(&msp->smi_busy_wait); | |
1118 | return IRQ_HANDLED; | |
1119 | } | |
1120 | ||
1121 | return IRQ_NONE; | |
1122 | } | |
c9df406f | 1123 | |
45c5d3bc | 1124 | static int smi_is_done(struct mv643xx_eth_shared_private *msp) |
1da177e4 | 1125 | { |
45c5d3bc LB |
1126 | return !(readl(msp->base + SMI_REG) & SMI_BUSY); |
1127 | } | |
1da177e4 | 1128 | |
45c5d3bc LB |
1129 | static int smi_wait_ready(struct mv643xx_eth_shared_private *msp) |
1130 | { | |
1131 | if (msp->err_interrupt == NO_IRQ) { | |
1132 | int i; | |
c9df406f | 1133 | |
45c5d3bc LB |
1134 | for (i = 0; !smi_is_done(msp); i++) { |
1135 | if (i == 10) | |
1136 | return -ETIMEDOUT; | |
1137 | msleep(10); | |
c9df406f | 1138 | } |
45c5d3bc LB |
1139 | |
1140 | return 0; | |
1141 | } | |
1142 | ||
ee04448d LB |
1143 | if (!smi_is_done(msp)) { |
1144 | wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp), | |
1145 | msecs_to_jiffies(100)); | |
1146 | if (!smi_is_done(msp)) | |
1147 | return -ETIMEDOUT; | |
1148 | } | |
45c5d3bc LB |
1149 | |
1150 | return 0; | |
1151 | } | |
1152 | ||
ed94493f | 1153 | static int smi_bus_read(struct mii_bus *bus, int addr, int reg) |
45c5d3bc | 1154 | { |
ed94493f | 1155 | struct mv643xx_eth_shared_private *msp = bus->priv; |
45c5d3bc LB |
1156 | void __iomem *smi_reg = msp->base + SMI_REG; |
1157 | int ret; | |
1158 | ||
45c5d3bc | 1159 | if (smi_wait_ready(msp)) { |
10a9948d | 1160 | printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n"); |
ed94493f | 1161 | return -ETIMEDOUT; |
1da177e4 LT |
1162 | } |
1163 | ||
fc32b0e2 | 1164 | writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg); |
1da177e4 | 1165 | |
45c5d3bc | 1166 | if (smi_wait_ready(msp)) { |
10a9948d | 1167 | printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n"); |
ed94493f | 1168 | return -ETIMEDOUT; |
45c5d3bc LB |
1169 | } |
1170 | ||
1171 | ret = readl(smi_reg); | |
1172 | if (!(ret & SMI_READ_VALID)) { | |
10a9948d | 1173 | printk(KERN_WARNING "mv643xx_eth: SMI bus read not valid\n"); |
ed94493f | 1174 | return -ENODEV; |
c9df406f LB |
1175 | } |
1176 | ||
ed94493f | 1177 | return ret & 0xffff; |
1da177e4 LT |
1178 | } |
1179 | ||
ed94493f | 1180 | static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val) |
1da177e4 | 1181 | { |
ed94493f | 1182 | struct mv643xx_eth_shared_private *msp = bus->priv; |
45c5d3bc | 1183 | void __iomem *smi_reg = msp->base + SMI_REG; |
1da177e4 | 1184 | |
45c5d3bc | 1185 | if (smi_wait_ready(msp)) { |
10a9948d | 1186 | printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n"); |
45c5d3bc | 1187 | return -ETIMEDOUT; |
1da177e4 LT |
1188 | } |
1189 | ||
fc32b0e2 | 1190 | writel(SMI_OPCODE_WRITE | (reg << 21) | |
ed94493f | 1191 | (addr << 16) | (val & 0xffff), smi_reg); |
45c5d3bc | 1192 | |
ed94493f | 1193 | if (smi_wait_ready(msp)) { |
10a9948d | 1194 | printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n"); |
ed94493f LB |
1195 | return -ETIMEDOUT; |
1196 | } | |
45c5d3bc LB |
1197 | |
1198 | return 0; | |
c9df406f | 1199 | } |
1da177e4 | 1200 | |
c9df406f | 1201 | |
8fd89211 LB |
1202 | /* statistics ***************************************************************/ |
1203 | static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev) | |
1204 | { | |
1205 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1206 | struct net_device_stats *stats = &dev->stats; | |
1207 | unsigned long tx_packets = 0; | |
1208 | unsigned long tx_bytes = 0; | |
1209 | unsigned long tx_dropped = 0; | |
1210 | int i; | |
1211 | ||
1212 | for (i = 0; i < mp->txq_count; i++) { | |
1213 | struct tx_queue *txq = mp->txq + i; | |
1214 | ||
1215 | tx_packets += txq->tx_packets; | |
1216 | tx_bytes += txq->tx_bytes; | |
1217 | tx_dropped += txq->tx_dropped; | |
1218 | } | |
1219 | ||
1220 | stats->tx_packets = tx_packets; | |
1221 | stats->tx_bytes = tx_bytes; | |
1222 | stats->tx_dropped = tx_dropped; | |
1223 | ||
1224 | return stats; | |
1225 | } | |
1226 | ||
eaf5d590 LB |
1227 | static void mv643xx_eth_grab_lro_stats(struct mv643xx_eth_private *mp) |
1228 | { | |
1229 | u32 lro_aggregated = 0; | |
1230 | u32 lro_flushed = 0; | |
1231 | u32 lro_no_desc = 0; | |
1232 | int i; | |
1233 | ||
1234 | #ifdef CONFIG_MV643XX_ETH_LRO | |
1235 | for (i = 0; i < mp->rxq_count; i++) { | |
1236 | struct rx_queue *rxq = mp->rxq + i; | |
1237 | ||
1238 | lro_aggregated += rxq->lro_mgr.stats.aggregated; | |
1239 | lro_flushed += rxq->lro_mgr.stats.flushed; | |
1240 | lro_no_desc += rxq->lro_mgr.stats.no_desc; | |
1241 | } | |
1242 | #endif | |
1243 | ||
1244 | mp->lro_counters.lro_aggregated = lro_aggregated; | |
1245 | mp->lro_counters.lro_flushed = lro_flushed; | |
1246 | mp->lro_counters.lro_no_desc = lro_no_desc; | |
1247 | } | |
1248 | ||
fc32b0e2 | 1249 | static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset) |
c9df406f | 1250 | { |
fc32b0e2 | 1251 | return rdl(mp, MIB_COUNTERS(mp->port_num) + offset); |
1da177e4 LT |
1252 | } |
1253 | ||
fc32b0e2 | 1254 | static void mib_counters_clear(struct mv643xx_eth_private *mp) |
d0412d96 | 1255 | { |
fc32b0e2 LB |
1256 | int i; |
1257 | ||
1258 | for (i = 0; i < 0x80; i += 4) | |
1259 | mib_read(mp, i); | |
c9df406f | 1260 | } |
d0412d96 | 1261 | |
fc32b0e2 | 1262 | static void mib_counters_update(struct mv643xx_eth_private *mp) |
c9df406f | 1263 | { |
e5371493 | 1264 | struct mib_counters *p = &mp->mib_counters; |
4b8e3655 | 1265 | |
4ff3495a | 1266 | spin_lock(&mp->mib_counters_lock); |
fc32b0e2 LB |
1267 | p->good_octets_received += mib_read(mp, 0x00); |
1268 | p->good_octets_received += (u64)mib_read(mp, 0x04) << 32; | |
1269 | p->bad_octets_received += mib_read(mp, 0x08); | |
1270 | p->internal_mac_transmit_err += mib_read(mp, 0x0c); | |
1271 | p->good_frames_received += mib_read(mp, 0x10); | |
1272 | p->bad_frames_received += mib_read(mp, 0x14); | |
1273 | p->broadcast_frames_received += mib_read(mp, 0x18); | |
1274 | p->multicast_frames_received += mib_read(mp, 0x1c); | |
1275 | p->frames_64_octets += mib_read(mp, 0x20); | |
1276 | p->frames_65_to_127_octets += mib_read(mp, 0x24); | |
1277 | p->frames_128_to_255_octets += mib_read(mp, 0x28); | |
1278 | p->frames_256_to_511_octets += mib_read(mp, 0x2c); | |
1279 | p->frames_512_to_1023_octets += mib_read(mp, 0x30); | |
1280 | p->frames_1024_to_max_octets += mib_read(mp, 0x34); | |
1281 | p->good_octets_sent += mib_read(mp, 0x38); | |
1282 | p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32; | |
1283 | p->good_frames_sent += mib_read(mp, 0x40); | |
1284 | p->excessive_collision += mib_read(mp, 0x44); | |
1285 | p->multicast_frames_sent += mib_read(mp, 0x48); | |
1286 | p->broadcast_frames_sent += mib_read(mp, 0x4c); | |
1287 | p->unrec_mac_control_received += mib_read(mp, 0x50); | |
1288 | p->fc_sent += mib_read(mp, 0x54); | |
1289 | p->good_fc_received += mib_read(mp, 0x58); | |
1290 | p->bad_fc_received += mib_read(mp, 0x5c); | |
1291 | p->undersize_received += mib_read(mp, 0x60); | |
1292 | p->fragments_received += mib_read(mp, 0x64); | |
1293 | p->oversize_received += mib_read(mp, 0x68); | |
1294 | p->jabber_received += mib_read(mp, 0x6c); | |
1295 | p->mac_receive_error += mib_read(mp, 0x70); | |
1296 | p->bad_crc_event += mib_read(mp, 0x74); | |
1297 | p->collision += mib_read(mp, 0x78); | |
1298 | p->late_collision += mib_read(mp, 0x7c); | |
4ff3495a LB |
1299 | spin_unlock(&mp->mib_counters_lock); |
1300 | ||
1301 | mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ); | |
1302 | } | |
1303 | ||
1304 | static void mib_counters_timer_wrapper(unsigned long _mp) | |
1305 | { | |
1306 | struct mv643xx_eth_private *mp = (void *)_mp; | |
1307 | ||
1308 | mib_counters_update(mp); | |
d0412d96 JC |
1309 | } |
1310 | ||
c9df406f | 1311 | |
3e508034 LB |
1312 | /* interrupt coalescing *****************************************************/ |
1313 | /* | |
1314 | * Hardware coalescing parameters are set in units of 64 t_clk | |
1315 | * cycles. I.e.: | |
1316 | * | |
1317 | * coal_delay_in_usec = 64000000 * register_value / t_clk_rate | |
1318 | * | |
1319 | * register_value = coal_delay_in_usec * t_clk_rate / 64000000 | |
1320 | * | |
1321 | * In the ->set*() methods, we round the computed register value | |
1322 | * to the nearest integer. | |
1323 | */ | |
1324 | static unsigned int get_rx_coal(struct mv643xx_eth_private *mp) | |
1325 | { | |
1326 | u32 val = rdlp(mp, SDMA_CONFIG); | |
1327 | u64 temp; | |
1328 | ||
1329 | if (mp->shared->extended_rx_coal_limit) | |
1330 | temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7); | |
1331 | else | |
1332 | temp = (val & 0x003fff00) >> 8; | |
1333 | ||
1334 | temp *= 64000000; | |
1335 | do_div(temp, mp->shared->t_clk); | |
1336 | ||
1337 | return (unsigned int)temp; | |
1338 | } | |
1339 | ||
1340 | static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec) | |
1341 | { | |
1342 | u64 temp; | |
1343 | u32 val; | |
1344 | ||
1345 | temp = (u64)usec * mp->shared->t_clk; | |
1346 | temp += 31999999; | |
1347 | do_div(temp, 64000000); | |
1348 | ||
1349 | val = rdlp(mp, SDMA_CONFIG); | |
1350 | if (mp->shared->extended_rx_coal_limit) { | |
1351 | if (temp > 0xffff) | |
1352 | temp = 0xffff; | |
1353 | val &= ~0x023fff80; | |
1354 | val |= (temp & 0x8000) << 10; | |
1355 | val |= (temp & 0x7fff) << 7; | |
1356 | } else { | |
1357 | if (temp > 0x3fff) | |
1358 | temp = 0x3fff; | |
1359 | val &= ~0x003fff00; | |
1360 | val |= (temp & 0x3fff) << 8; | |
1361 | } | |
1362 | wrlp(mp, SDMA_CONFIG, val); | |
1363 | } | |
1364 | ||
1365 | static unsigned int get_tx_coal(struct mv643xx_eth_private *mp) | |
1366 | { | |
1367 | u64 temp; | |
1368 | ||
1369 | temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4; | |
1370 | temp *= 64000000; | |
1371 | do_div(temp, mp->shared->t_clk); | |
1372 | ||
1373 | return (unsigned int)temp; | |
1374 | } | |
1375 | ||
1376 | static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec) | |
1377 | { | |
1378 | u64 temp; | |
1379 | ||
1380 | temp = (u64)usec * mp->shared->t_clk; | |
1381 | temp += 31999999; | |
1382 | do_div(temp, 64000000); | |
1383 | ||
1384 | if (temp > 0x3fff) | |
1385 | temp = 0x3fff; | |
1386 | ||
1387 | wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4); | |
1388 | } | |
1389 | ||
1390 | ||
c9df406f | 1391 | /* ethtool ******************************************************************/ |
e5371493 | 1392 | struct mv643xx_eth_stats { |
c9df406f LB |
1393 | char stat_string[ETH_GSTRING_LEN]; |
1394 | int sizeof_stat; | |
16820054 LB |
1395 | int netdev_off; |
1396 | int mp_off; | |
c9df406f LB |
1397 | }; |
1398 | ||
16820054 LB |
1399 | #define SSTAT(m) \ |
1400 | { #m, FIELD_SIZEOF(struct net_device_stats, m), \ | |
1401 | offsetof(struct net_device, stats.m), -1 } | |
1402 | ||
1403 | #define MIBSTAT(m) \ | |
1404 | { #m, FIELD_SIZEOF(struct mib_counters, m), \ | |
1405 | -1, offsetof(struct mv643xx_eth_private, mib_counters.m) } | |
1406 | ||
eaf5d590 LB |
1407 | #define LROSTAT(m) \ |
1408 | { #m, FIELD_SIZEOF(struct lro_counters, m), \ | |
1409 | -1, offsetof(struct mv643xx_eth_private, lro_counters.m) } | |
1410 | ||
16820054 LB |
1411 | static const struct mv643xx_eth_stats mv643xx_eth_stats[] = { |
1412 | SSTAT(rx_packets), | |
1413 | SSTAT(tx_packets), | |
1414 | SSTAT(rx_bytes), | |
1415 | SSTAT(tx_bytes), | |
1416 | SSTAT(rx_errors), | |
1417 | SSTAT(tx_errors), | |
1418 | SSTAT(rx_dropped), | |
1419 | SSTAT(tx_dropped), | |
1420 | MIBSTAT(good_octets_received), | |
1421 | MIBSTAT(bad_octets_received), | |
1422 | MIBSTAT(internal_mac_transmit_err), | |
1423 | MIBSTAT(good_frames_received), | |
1424 | MIBSTAT(bad_frames_received), | |
1425 | MIBSTAT(broadcast_frames_received), | |
1426 | MIBSTAT(multicast_frames_received), | |
1427 | MIBSTAT(frames_64_octets), | |
1428 | MIBSTAT(frames_65_to_127_octets), | |
1429 | MIBSTAT(frames_128_to_255_octets), | |
1430 | MIBSTAT(frames_256_to_511_octets), | |
1431 | MIBSTAT(frames_512_to_1023_octets), | |
1432 | MIBSTAT(frames_1024_to_max_octets), | |
1433 | MIBSTAT(good_octets_sent), | |
1434 | MIBSTAT(good_frames_sent), | |
1435 | MIBSTAT(excessive_collision), | |
1436 | MIBSTAT(multicast_frames_sent), | |
1437 | MIBSTAT(broadcast_frames_sent), | |
1438 | MIBSTAT(unrec_mac_control_received), | |
1439 | MIBSTAT(fc_sent), | |
1440 | MIBSTAT(good_fc_received), | |
1441 | MIBSTAT(bad_fc_received), | |
1442 | MIBSTAT(undersize_received), | |
1443 | MIBSTAT(fragments_received), | |
1444 | MIBSTAT(oversize_received), | |
1445 | MIBSTAT(jabber_received), | |
1446 | MIBSTAT(mac_receive_error), | |
1447 | MIBSTAT(bad_crc_event), | |
1448 | MIBSTAT(collision), | |
1449 | MIBSTAT(late_collision), | |
eaf5d590 LB |
1450 | LROSTAT(lro_aggregated), |
1451 | LROSTAT(lro_flushed), | |
1452 | LROSTAT(lro_no_desc), | |
c9df406f LB |
1453 | }; |
1454 | ||
10a9948d | 1455 | static int |
6bdf576e LB |
1456 | mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp, |
1457 | struct ethtool_cmd *cmd) | |
d0412d96 | 1458 | { |
d0412d96 JC |
1459 | int err; |
1460 | ||
ed94493f LB |
1461 | err = phy_read_status(mp->phy); |
1462 | if (err == 0) | |
1463 | err = phy_ethtool_gset(mp->phy, cmd); | |
d0412d96 | 1464 | |
fc32b0e2 LB |
1465 | /* |
1466 | * The MAC does not support 1000baseT_Half. | |
1467 | */ | |
d0412d96 JC |
1468 | cmd->supported &= ~SUPPORTED_1000baseT_Half; |
1469 | cmd->advertising &= ~ADVERTISED_1000baseT_Half; | |
1470 | ||
1471 | return err; | |
1472 | } | |
1473 | ||
10a9948d | 1474 | static int |
6bdf576e | 1475 | mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp, |
10a9948d | 1476 | struct ethtool_cmd *cmd) |
bedfe324 | 1477 | { |
81600eea LB |
1478 | u32 port_status; |
1479 | ||
37a6084f | 1480 | port_status = rdlp(mp, PORT_STATUS); |
81600eea | 1481 | |
bedfe324 LB |
1482 | cmd->supported = SUPPORTED_MII; |
1483 | cmd->advertising = ADVERTISED_MII; | |
81600eea LB |
1484 | switch (port_status & PORT_SPEED_MASK) { |
1485 | case PORT_SPEED_10: | |
1486 | cmd->speed = SPEED_10; | |
1487 | break; | |
1488 | case PORT_SPEED_100: | |
1489 | cmd->speed = SPEED_100; | |
1490 | break; | |
1491 | case PORT_SPEED_1000: | |
1492 | cmd->speed = SPEED_1000; | |
1493 | break; | |
1494 | default: | |
1495 | cmd->speed = -1; | |
1496 | break; | |
1497 | } | |
1498 | cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF; | |
bedfe324 LB |
1499 | cmd->port = PORT_MII; |
1500 | cmd->phy_address = 0; | |
1501 | cmd->transceiver = XCVR_INTERNAL; | |
1502 | cmd->autoneg = AUTONEG_DISABLE; | |
1503 | cmd->maxtxpkt = 1; | |
1504 | cmd->maxrxpkt = 1; | |
1505 | ||
1506 | return 0; | |
1507 | } | |
1508 | ||
6bdf576e LB |
1509 | static int |
1510 | mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1511 | { | |
1512 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1513 | ||
1514 | if (mp->phy != NULL) | |
1515 | return mv643xx_eth_get_settings_phy(mp, cmd); | |
1516 | else | |
1517 | return mv643xx_eth_get_settings_phyless(mp, cmd); | |
1518 | } | |
1519 | ||
10a9948d LB |
1520 | static int |
1521 | mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1da177e4 | 1522 | { |
e5371493 | 1523 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
ab4384a6 | 1524 | |
6bdf576e LB |
1525 | if (mp->phy == NULL) |
1526 | return -EINVAL; | |
1527 | ||
fc32b0e2 LB |
1528 | /* |
1529 | * The MAC does not support 1000baseT_Half. | |
1530 | */ | |
1531 | cmd->advertising &= ~ADVERTISED_1000baseT_Half; | |
1532 | ||
ed94493f | 1533 | return phy_ethtool_sset(mp->phy, cmd); |
c9df406f | 1534 | } |
1da177e4 | 1535 | |
fc32b0e2 LB |
1536 | static void mv643xx_eth_get_drvinfo(struct net_device *dev, |
1537 | struct ethtool_drvinfo *drvinfo) | |
c9df406f | 1538 | { |
e5371493 LB |
1539 | strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32); |
1540 | strncpy(drvinfo->version, mv643xx_eth_driver_version, 32); | |
c9df406f | 1541 | strncpy(drvinfo->fw_version, "N/A", 32); |
fc32b0e2 | 1542 | strncpy(drvinfo->bus_info, "platform", 32); |
16820054 | 1543 | drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats); |
c9df406f | 1544 | } |
1da177e4 | 1545 | |
fc32b0e2 | 1546 | static int mv643xx_eth_nway_reset(struct net_device *dev) |
c9df406f | 1547 | { |
e5371493 | 1548 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 1549 | |
6bdf576e LB |
1550 | if (mp->phy == NULL) |
1551 | return -EINVAL; | |
1da177e4 | 1552 | |
6bdf576e | 1553 | return genphy_restart_aneg(mp->phy); |
bedfe324 LB |
1554 | } |
1555 | ||
c9df406f LB |
1556 | static u32 mv643xx_eth_get_link(struct net_device *dev) |
1557 | { | |
ed94493f | 1558 | return !!netif_carrier_ok(dev); |
bedfe324 LB |
1559 | } |
1560 | ||
3e508034 LB |
1561 | static int |
1562 | mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) | |
1563 | { | |
1564 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1565 | ||
1566 | ec->rx_coalesce_usecs = get_rx_coal(mp); | |
1567 | ec->tx_coalesce_usecs = get_tx_coal(mp); | |
1568 | ||
1569 | return 0; | |
1570 | } | |
1571 | ||
1572 | static int | |
1573 | mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) | |
1574 | { | |
1575 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1576 | ||
1577 | set_rx_coal(mp, ec->rx_coalesce_usecs); | |
1578 | set_tx_coal(mp, ec->tx_coalesce_usecs); | |
1579 | ||
1580 | return 0; | |
1581 | } | |
1582 | ||
e7d2f4db LB |
1583 | static void |
1584 | mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er) | |
1585 | { | |
1586 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1587 | ||
1588 | er->rx_max_pending = 4096; | |
1589 | er->tx_max_pending = 4096; | |
1590 | er->rx_mini_max_pending = 0; | |
1591 | er->rx_jumbo_max_pending = 0; | |
1592 | ||
1593 | er->rx_pending = mp->rx_ring_size; | |
1594 | er->tx_pending = mp->tx_ring_size; | |
1595 | er->rx_mini_pending = 0; | |
1596 | er->rx_jumbo_pending = 0; | |
1597 | } | |
1598 | ||
1599 | static int | |
1600 | mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er) | |
1601 | { | |
1602 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1603 | ||
1604 | if (er->rx_mini_pending || er->rx_jumbo_pending) | |
1605 | return -EINVAL; | |
1606 | ||
1607 | mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096; | |
1608 | mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096; | |
1609 | ||
1610 | if (netif_running(dev)) { | |
1611 | mv643xx_eth_stop(dev); | |
1612 | if (mv643xx_eth_open(dev)) { | |
1613 | dev_printk(KERN_ERR, &dev->dev, | |
1614 | "fatal error on re-opening device after " | |
1615 | "ring param change\n"); | |
1616 | return -ENOMEM; | |
1617 | } | |
1618 | } | |
1619 | ||
1620 | return 0; | |
1621 | } | |
1622 | ||
d888b373 LB |
1623 | static u32 |
1624 | mv643xx_eth_get_rx_csum(struct net_device *dev) | |
1625 | { | |
1626 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1627 | ||
1628 | return !!(rdlp(mp, PORT_CONFIG) & 0x02000000); | |
1629 | } | |
1630 | ||
1631 | static int | |
1632 | mv643xx_eth_set_rx_csum(struct net_device *dev, u32 rx_csum) | |
1633 | { | |
1634 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1635 | ||
1636 | wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000); | |
1637 | ||
1638 | return 0; | |
1639 | } | |
1640 | ||
fc32b0e2 LB |
1641 | static void mv643xx_eth_get_strings(struct net_device *dev, |
1642 | uint32_t stringset, uint8_t *data) | |
c9df406f LB |
1643 | { |
1644 | int i; | |
1da177e4 | 1645 | |
fc32b0e2 LB |
1646 | if (stringset == ETH_SS_STATS) { |
1647 | for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { | |
c9df406f | 1648 | memcpy(data + i * ETH_GSTRING_LEN, |
16820054 | 1649 | mv643xx_eth_stats[i].stat_string, |
e5371493 | 1650 | ETH_GSTRING_LEN); |
c9df406f | 1651 | } |
c9df406f LB |
1652 | } |
1653 | } | |
1da177e4 | 1654 | |
fc32b0e2 LB |
1655 | static void mv643xx_eth_get_ethtool_stats(struct net_device *dev, |
1656 | struct ethtool_stats *stats, | |
1657 | uint64_t *data) | |
c9df406f | 1658 | { |
b9873841 | 1659 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f | 1660 | int i; |
1da177e4 | 1661 | |
8fd89211 | 1662 | mv643xx_eth_get_stats(dev); |
fc32b0e2 | 1663 | mib_counters_update(mp); |
eaf5d590 | 1664 | mv643xx_eth_grab_lro_stats(mp); |
1da177e4 | 1665 | |
16820054 LB |
1666 | for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { |
1667 | const struct mv643xx_eth_stats *stat; | |
1668 | void *p; | |
1669 | ||
1670 | stat = mv643xx_eth_stats + i; | |
1671 | ||
1672 | if (stat->netdev_off >= 0) | |
1673 | p = ((void *)mp->dev) + stat->netdev_off; | |
1674 | else | |
1675 | p = ((void *)mp) + stat->mp_off; | |
1676 | ||
1677 | data[i] = (stat->sizeof_stat == 8) ? | |
1678 | *(uint64_t *)p : *(uint32_t *)p; | |
1da177e4 | 1679 | } |
c9df406f | 1680 | } |
1da177e4 | 1681 | |
fc32b0e2 | 1682 | static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset) |
c9df406f | 1683 | { |
fc32b0e2 | 1684 | if (sset == ETH_SS_STATS) |
16820054 | 1685 | return ARRAY_SIZE(mv643xx_eth_stats); |
fc32b0e2 LB |
1686 | |
1687 | return -EOPNOTSUPP; | |
c9df406f | 1688 | } |
1da177e4 | 1689 | |
e5371493 | 1690 | static const struct ethtool_ops mv643xx_eth_ethtool_ops = { |
fc32b0e2 LB |
1691 | .get_settings = mv643xx_eth_get_settings, |
1692 | .set_settings = mv643xx_eth_set_settings, | |
1693 | .get_drvinfo = mv643xx_eth_get_drvinfo, | |
1694 | .nway_reset = mv643xx_eth_nway_reset, | |
1695 | .get_link = mv643xx_eth_get_link, | |
3e508034 LB |
1696 | .get_coalesce = mv643xx_eth_get_coalesce, |
1697 | .set_coalesce = mv643xx_eth_set_coalesce, | |
e7d2f4db LB |
1698 | .get_ringparam = mv643xx_eth_get_ringparam, |
1699 | .set_ringparam = mv643xx_eth_set_ringparam, | |
d888b373 LB |
1700 | .get_rx_csum = mv643xx_eth_get_rx_csum, |
1701 | .set_rx_csum = mv643xx_eth_set_rx_csum, | |
b8df184f | 1702 | .set_tx_csum = ethtool_op_set_tx_csum, |
c9df406f | 1703 | .set_sg = ethtool_op_set_sg, |
fc32b0e2 LB |
1704 | .get_strings = mv643xx_eth_get_strings, |
1705 | .get_ethtool_stats = mv643xx_eth_get_ethtool_stats, | |
eaf5d590 LB |
1706 | .get_flags = ethtool_op_get_flags, |
1707 | .set_flags = ethtool_op_set_flags, | |
e5371493 | 1708 | .get_sset_count = mv643xx_eth_get_sset_count, |
c9df406f | 1709 | }; |
1da177e4 | 1710 | |
bea3348e | 1711 | |
c9df406f | 1712 | /* address handling *********************************************************/ |
5daffe94 | 1713 | static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr) |
c9df406f | 1714 | { |
66e63ffb LB |
1715 | unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH); |
1716 | unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW); | |
1da177e4 | 1717 | |
5daffe94 LB |
1718 | addr[0] = (mac_h >> 24) & 0xff; |
1719 | addr[1] = (mac_h >> 16) & 0xff; | |
1720 | addr[2] = (mac_h >> 8) & 0xff; | |
1721 | addr[3] = mac_h & 0xff; | |
1722 | addr[4] = (mac_l >> 8) & 0xff; | |
1723 | addr[5] = mac_l & 0xff; | |
c9df406f | 1724 | } |
1da177e4 | 1725 | |
66e63ffb | 1726 | static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr) |
c9df406f | 1727 | { |
66e63ffb LB |
1728 | wrlp(mp, MAC_ADDR_HIGH, |
1729 | (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]); | |
1730 | wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]); | |
c9df406f | 1731 | } |
d0412d96 | 1732 | |
66e63ffb | 1733 | static u32 uc_addr_filter_mask(struct net_device *dev) |
c9df406f | 1734 | { |
66e63ffb LB |
1735 | struct dev_addr_list *uc_ptr; |
1736 | u32 nibbles; | |
1da177e4 | 1737 | |
66e63ffb LB |
1738 | if (dev->flags & IFF_PROMISC) |
1739 | return 0; | |
1da177e4 | 1740 | |
66e63ffb LB |
1741 | nibbles = 1 << (dev->dev_addr[5] & 0x0f); |
1742 | for (uc_ptr = dev->uc_list; uc_ptr != NULL; uc_ptr = uc_ptr->next) { | |
1743 | if (memcmp(dev->dev_addr, uc_ptr->da_addr, 5)) | |
1744 | return 0; | |
1745 | if ((dev->dev_addr[5] ^ uc_ptr->da_addr[5]) & 0xf0) | |
1746 | return 0; | |
ff561eef | 1747 | |
66e63ffb LB |
1748 | nibbles |= 1 << (uc_ptr->da_addr[5] & 0x0f); |
1749 | } | |
1da177e4 | 1750 | |
66e63ffb | 1751 | return nibbles; |
1da177e4 LT |
1752 | } |
1753 | ||
66e63ffb | 1754 | static void mv643xx_eth_program_unicast_filter(struct net_device *dev) |
1da177e4 | 1755 | { |
e5371493 | 1756 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
66e63ffb LB |
1757 | u32 port_config; |
1758 | u32 nibbles; | |
1759 | int i; | |
1da177e4 | 1760 | |
cc9754b3 | 1761 | uc_addr_set(mp, dev->dev_addr); |
1da177e4 | 1762 | |
66e63ffb LB |
1763 | port_config = rdlp(mp, PORT_CONFIG); |
1764 | nibbles = uc_addr_filter_mask(dev); | |
1765 | if (!nibbles) { | |
1766 | port_config |= UNICAST_PROMISCUOUS_MODE; | |
1767 | wrlp(mp, PORT_CONFIG, port_config); | |
1768 | return; | |
1769 | } | |
1770 | ||
1771 | for (i = 0; i < 16; i += 4) { | |
1772 | int off = UNICAST_TABLE(mp->port_num) + i; | |
1773 | u32 v; | |
1774 | ||
1775 | v = 0; | |
1776 | if (nibbles & 1) | |
1777 | v |= 0x00000001; | |
1778 | if (nibbles & 2) | |
1779 | v |= 0x00000100; | |
1780 | if (nibbles & 4) | |
1781 | v |= 0x00010000; | |
1782 | if (nibbles & 8) | |
1783 | v |= 0x01000000; | |
1784 | nibbles >>= 4; | |
1785 | ||
1786 | wrl(mp, off, v); | |
1787 | } | |
1788 | ||
1789 | port_config &= ~UNICAST_PROMISCUOUS_MODE; | |
1790 | wrlp(mp, PORT_CONFIG, port_config); | |
1da177e4 LT |
1791 | } |
1792 | ||
69876569 LB |
1793 | static int addr_crc(unsigned char *addr) |
1794 | { | |
1795 | int crc = 0; | |
1796 | int i; | |
1797 | ||
1798 | for (i = 0; i < 6; i++) { | |
1799 | int j; | |
1800 | ||
1801 | crc = (crc ^ addr[i]) << 8; | |
1802 | for (j = 7; j >= 0; j--) { | |
1803 | if (crc & (0x100 << j)) | |
1804 | crc ^= 0x107 << j; | |
1805 | } | |
1806 | } | |
1807 | ||
1808 | return crc; | |
1809 | } | |
1810 | ||
66e63ffb | 1811 | static void mv643xx_eth_program_multicast_filter(struct net_device *dev) |
1da177e4 | 1812 | { |
fc32b0e2 | 1813 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
66e63ffb LB |
1814 | u32 *mc_spec; |
1815 | u32 *mc_other; | |
fc32b0e2 LB |
1816 | struct dev_addr_list *addr; |
1817 | int i; | |
c8aaea25 | 1818 | |
fc32b0e2 | 1819 | if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) { |
66e63ffb LB |
1820 | int port_num; |
1821 | u32 accept; | |
1822 | int i; | |
c8aaea25 | 1823 | |
66e63ffb LB |
1824 | oom: |
1825 | port_num = mp->port_num; | |
1826 | accept = 0x01010101; | |
fc32b0e2 LB |
1827 | for (i = 0; i < 0x100; i += 4) { |
1828 | wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept); | |
1829 | wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept); | |
c9df406f LB |
1830 | } |
1831 | return; | |
1832 | } | |
c8aaea25 | 1833 | |
66e63ffb LB |
1834 | mc_spec = kmalloc(0x200, GFP_KERNEL); |
1835 | if (mc_spec == NULL) | |
1836 | goto oom; | |
1837 | mc_other = mc_spec + (0x100 >> 2); | |
1838 | ||
1839 | memset(mc_spec, 0, 0x100); | |
1840 | memset(mc_other, 0, 0x100); | |
1da177e4 | 1841 | |
fc32b0e2 LB |
1842 | for (addr = dev->mc_list; addr != NULL; addr = addr->next) { |
1843 | u8 *a = addr->da_addr; | |
66e63ffb LB |
1844 | u32 *table; |
1845 | int entry; | |
1da177e4 | 1846 | |
fc32b0e2 | 1847 | if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) { |
66e63ffb LB |
1848 | table = mc_spec; |
1849 | entry = a[5]; | |
fc32b0e2 | 1850 | } else { |
66e63ffb LB |
1851 | table = mc_other; |
1852 | entry = addr_crc(a); | |
fc32b0e2 | 1853 | } |
66e63ffb | 1854 | |
2b448334 | 1855 | table[entry >> 2] |= 1 << (8 * (entry & 3)); |
fc32b0e2 | 1856 | } |
66e63ffb LB |
1857 | |
1858 | for (i = 0; i < 0x100; i += 4) { | |
1859 | wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]); | |
1860 | wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]); | |
1861 | } | |
1862 | ||
1863 | kfree(mc_spec); | |
1864 | } | |
1865 | ||
1866 | static void mv643xx_eth_set_rx_mode(struct net_device *dev) | |
1867 | { | |
1868 | mv643xx_eth_program_unicast_filter(dev); | |
1869 | mv643xx_eth_program_multicast_filter(dev); | |
1870 | } | |
1871 | ||
1872 | static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr) | |
1873 | { | |
1874 | struct sockaddr *sa = addr; | |
1875 | ||
1876 | memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN); | |
1877 | ||
1878 | netif_addr_lock_bh(dev); | |
1879 | mv643xx_eth_program_unicast_filter(dev); | |
1880 | netif_addr_unlock_bh(dev); | |
1881 | ||
1882 | return 0; | |
c9df406f | 1883 | } |
c8aaea25 | 1884 | |
c8aaea25 | 1885 | |
c9df406f | 1886 | /* rx/tx queue initialisation ***********************************************/ |
64da80a2 | 1887 | static int rxq_init(struct mv643xx_eth_private *mp, int index) |
c9df406f | 1888 | { |
64da80a2 | 1889 | struct rx_queue *rxq = mp->rxq + index; |
8a578111 LB |
1890 | struct rx_desc *rx_desc; |
1891 | int size; | |
c9df406f LB |
1892 | int i; |
1893 | ||
64da80a2 LB |
1894 | rxq->index = index; |
1895 | ||
e7d2f4db | 1896 | rxq->rx_ring_size = mp->rx_ring_size; |
8a578111 LB |
1897 | |
1898 | rxq->rx_desc_count = 0; | |
1899 | rxq->rx_curr_desc = 0; | |
1900 | rxq->rx_used_desc = 0; | |
1901 | ||
1902 | size = rxq->rx_ring_size * sizeof(struct rx_desc); | |
1903 | ||
f7981c1c | 1904 | if (index == 0 && size <= mp->rx_desc_sram_size) { |
8a578111 LB |
1905 | rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr, |
1906 | mp->rx_desc_sram_size); | |
1907 | rxq->rx_desc_dma = mp->rx_desc_sram_addr; | |
1908 | } else { | |
1909 | rxq->rx_desc_area = dma_alloc_coherent(NULL, size, | |
1910 | &rxq->rx_desc_dma, | |
1911 | GFP_KERNEL); | |
f7ea3337 PJ |
1912 | } |
1913 | ||
8a578111 LB |
1914 | if (rxq->rx_desc_area == NULL) { |
1915 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1916 | "can't allocate rx ring (%d bytes)\n", size); | |
1917 | goto out; | |
1918 | } | |
1919 | memset(rxq->rx_desc_area, 0, size); | |
1da177e4 | 1920 | |
8a578111 LB |
1921 | rxq->rx_desc_area_size = size; |
1922 | rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb), | |
1923 | GFP_KERNEL); | |
1924 | if (rxq->rx_skb == NULL) { | |
1925 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1926 | "can't allocate rx skb ring\n"); | |
1927 | goto out_free; | |
1928 | } | |
1929 | ||
1930 | rx_desc = (struct rx_desc *)rxq->rx_desc_area; | |
1931 | for (i = 0; i < rxq->rx_ring_size; i++) { | |
9da78745 LB |
1932 | int nexti; |
1933 | ||
1934 | nexti = i + 1; | |
1935 | if (nexti == rxq->rx_ring_size) | |
1936 | nexti = 0; | |
1937 | ||
8a578111 LB |
1938 | rx_desc[i].next_desc_ptr = rxq->rx_desc_dma + |
1939 | nexti * sizeof(struct rx_desc); | |
1940 | } | |
1941 | ||
eaf5d590 LB |
1942 | #ifdef CONFIG_MV643XX_ETH_LRO |
1943 | rxq->lro_mgr.dev = mp->dev; | |
1944 | memset(&rxq->lro_mgr.stats, 0, sizeof(rxq->lro_mgr.stats)); | |
1945 | rxq->lro_mgr.features = LRO_F_NAPI; | |
1946 | rxq->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY; | |
1947 | rxq->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY; | |
1948 | rxq->lro_mgr.max_desc = ARRAY_SIZE(rxq->lro_arr); | |
1949 | rxq->lro_mgr.max_aggr = 32; | |
1950 | rxq->lro_mgr.frag_align_pad = 0; | |
1951 | rxq->lro_mgr.lro_arr = rxq->lro_arr; | |
1952 | rxq->lro_mgr.get_skb_header = mv643xx_get_skb_header; | |
1953 | ||
1954 | memset(&rxq->lro_arr, 0, sizeof(rxq->lro_arr)); | |
1955 | #endif | |
1956 | ||
8a578111 LB |
1957 | return 0; |
1958 | ||
1959 | ||
1960 | out_free: | |
f7981c1c | 1961 | if (index == 0 && size <= mp->rx_desc_sram_size) |
8a578111 LB |
1962 | iounmap(rxq->rx_desc_area); |
1963 | else | |
1964 | dma_free_coherent(NULL, size, | |
1965 | rxq->rx_desc_area, | |
1966 | rxq->rx_desc_dma); | |
1967 | ||
1968 | out: | |
1969 | return -ENOMEM; | |
c9df406f | 1970 | } |
c8aaea25 | 1971 | |
8a578111 | 1972 | static void rxq_deinit(struct rx_queue *rxq) |
c9df406f | 1973 | { |
8a578111 LB |
1974 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
1975 | int i; | |
1976 | ||
1977 | rxq_disable(rxq); | |
c8aaea25 | 1978 | |
8a578111 LB |
1979 | for (i = 0; i < rxq->rx_ring_size; i++) { |
1980 | if (rxq->rx_skb[i]) { | |
1981 | dev_kfree_skb(rxq->rx_skb[i]); | |
1982 | rxq->rx_desc_count--; | |
1da177e4 | 1983 | } |
c8aaea25 | 1984 | } |
1da177e4 | 1985 | |
8a578111 LB |
1986 | if (rxq->rx_desc_count) { |
1987 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1988 | "error freeing rx ring -- %d skbs stuck\n", | |
1989 | rxq->rx_desc_count); | |
1990 | } | |
1991 | ||
f7981c1c | 1992 | if (rxq->index == 0 && |
64da80a2 | 1993 | rxq->rx_desc_area_size <= mp->rx_desc_sram_size) |
8a578111 | 1994 | iounmap(rxq->rx_desc_area); |
c9df406f | 1995 | else |
8a578111 LB |
1996 | dma_free_coherent(NULL, rxq->rx_desc_area_size, |
1997 | rxq->rx_desc_area, rxq->rx_desc_dma); | |
1998 | ||
1999 | kfree(rxq->rx_skb); | |
c9df406f | 2000 | } |
1da177e4 | 2001 | |
3d6b35bc | 2002 | static int txq_init(struct mv643xx_eth_private *mp, int index) |
c9df406f | 2003 | { |
3d6b35bc | 2004 | struct tx_queue *txq = mp->txq + index; |
13d64285 LB |
2005 | struct tx_desc *tx_desc; |
2006 | int size; | |
c9df406f | 2007 | int i; |
1da177e4 | 2008 | |
3d6b35bc LB |
2009 | txq->index = index; |
2010 | ||
e7d2f4db | 2011 | txq->tx_ring_size = mp->tx_ring_size; |
13d64285 LB |
2012 | |
2013 | txq->tx_desc_count = 0; | |
2014 | txq->tx_curr_desc = 0; | |
2015 | txq->tx_used_desc = 0; | |
2016 | ||
2017 | size = txq->tx_ring_size * sizeof(struct tx_desc); | |
2018 | ||
f7981c1c | 2019 | if (index == 0 && size <= mp->tx_desc_sram_size) { |
13d64285 LB |
2020 | txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr, |
2021 | mp->tx_desc_sram_size); | |
2022 | txq->tx_desc_dma = mp->tx_desc_sram_addr; | |
2023 | } else { | |
2024 | txq->tx_desc_area = dma_alloc_coherent(NULL, size, | |
2025 | &txq->tx_desc_dma, | |
2026 | GFP_KERNEL); | |
2027 | } | |
2028 | ||
2029 | if (txq->tx_desc_area == NULL) { | |
2030 | dev_printk(KERN_ERR, &mp->dev->dev, | |
2031 | "can't allocate tx ring (%d bytes)\n", size); | |
99ab08e0 | 2032 | return -ENOMEM; |
c9df406f | 2033 | } |
13d64285 LB |
2034 | memset(txq->tx_desc_area, 0, size); |
2035 | ||
2036 | txq->tx_desc_area_size = size; | |
13d64285 LB |
2037 | |
2038 | tx_desc = (struct tx_desc *)txq->tx_desc_area; | |
2039 | for (i = 0; i < txq->tx_ring_size; i++) { | |
6b368f68 | 2040 | struct tx_desc *txd = tx_desc + i; |
9da78745 LB |
2041 | int nexti; |
2042 | ||
2043 | nexti = i + 1; | |
2044 | if (nexti == txq->tx_ring_size) | |
2045 | nexti = 0; | |
6b368f68 LB |
2046 | |
2047 | txd->cmd_sts = 0; | |
2048 | txd->next_desc_ptr = txq->tx_desc_dma + | |
13d64285 LB |
2049 | nexti * sizeof(struct tx_desc); |
2050 | } | |
2051 | ||
99ab08e0 | 2052 | skb_queue_head_init(&txq->tx_skb); |
c9df406f | 2053 | |
99ab08e0 | 2054 | return 0; |
c8aaea25 | 2055 | } |
1da177e4 | 2056 | |
13d64285 | 2057 | static void txq_deinit(struct tx_queue *txq) |
c9df406f | 2058 | { |
13d64285 | 2059 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
fa3959f4 | 2060 | |
13d64285 | 2061 | txq_disable(txq); |
1fa38c58 | 2062 | txq_reclaim(txq, txq->tx_ring_size, 1); |
1da177e4 | 2063 | |
13d64285 | 2064 | BUG_ON(txq->tx_used_desc != txq->tx_curr_desc); |
1da177e4 | 2065 | |
f7981c1c | 2066 | if (txq->index == 0 && |
3d6b35bc | 2067 | txq->tx_desc_area_size <= mp->tx_desc_sram_size) |
13d64285 | 2068 | iounmap(txq->tx_desc_area); |
c9df406f | 2069 | else |
13d64285 LB |
2070 | dma_free_coherent(NULL, txq->tx_desc_area_size, |
2071 | txq->tx_desc_area, txq->tx_desc_dma); | |
c9df406f | 2072 | } |
1da177e4 | 2073 | |
1da177e4 | 2074 | |
c9df406f | 2075 | /* netdev ops and related ***************************************************/ |
1fa38c58 LB |
2076 | static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp) |
2077 | { | |
2078 | u32 int_cause; | |
2079 | u32 int_cause_ext; | |
2080 | ||
37a6084f | 2081 | int_cause = rdlp(mp, INT_CAUSE) & (INT_TX_END | INT_RX | INT_EXT); |
1fa38c58 LB |
2082 | if (int_cause == 0) |
2083 | return 0; | |
2084 | ||
2085 | int_cause_ext = 0; | |
2086 | if (int_cause & INT_EXT) | |
37a6084f | 2087 | int_cause_ext = rdlp(mp, INT_CAUSE_EXT); |
1fa38c58 LB |
2088 | |
2089 | int_cause &= INT_TX_END | INT_RX; | |
2090 | if (int_cause) { | |
37a6084f | 2091 | wrlp(mp, INT_CAUSE, ~int_cause); |
1fa38c58 | 2092 | mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) & |
37a6084f | 2093 | ~(rdlp(mp, TXQ_COMMAND) & 0xff); |
1fa38c58 LB |
2094 | mp->work_rx |= (int_cause & INT_RX) >> 2; |
2095 | } | |
2096 | ||
2097 | int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX; | |
2098 | if (int_cause_ext) { | |
37a6084f | 2099 | wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext); |
1fa38c58 LB |
2100 | if (int_cause_ext & INT_EXT_LINK_PHY) |
2101 | mp->work_link = 1; | |
2102 | mp->work_tx |= int_cause_ext & INT_EXT_TX; | |
2103 | } | |
2104 | ||
2105 | return 1; | |
2106 | } | |
2107 | ||
2108 | static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id) | |
2109 | { | |
2110 | struct net_device *dev = (struct net_device *)dev_id; | |
2111 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
2112 | ||
2113 | if (unlikely(!mv643xx_eth_collect_events(mp))) | |
2114 | return IRQ_NONE; | |
2115 | ||
37a6084f | 2116 | wrlp(mp, INT_MASK, 0); |
1fa38c58 LB |
2117 | napi_schedule(&mp->napi); |
2118 | ||
2119 | return IRQ_HANDLED; | |
2120 | } | |
2121 | ||
2f7eb47a LB |
2122 | static void handle_link_event(struct mv643xx_eth_private *mp) |
2123 | { | |
2124 | struct net_device *dev = mp->dev; | |
2125 | u32 port_status; | |
2126 | int speed; | |
2127 | int duplex; | |
2128 | int fc; | |
2129 | ||
37a6084f | 2130 | port_status = rdlp(mp, PORT_STATUS); |
2f7eb47a LB |
2131 | if (!(port_status & LINK_UP)) { |
2132 | if (netif_carrier_ok(dev)) { | |
2133 | int i; | |
2134 | ||
2135 | printk(KERN_INFO "%s: link down\n", dev->name); | |
2136 | ||
2137 | netif_carrier_off(dev); | |
2f7eb47a | 2138 | |
f7981c1c | 2139 | for (i = 0; i < mp->txq_count; i++) { |
2f7eb47a LB |
2140 | struct tx_queue *txq = mp->txq + i; |
2141 | ||
1fa38c58 | 2142 | txq_reclaim(txq, txq->tx_ring_size, 1); |
f7981c1c | 2143 | txq_reset_hw_ptr(txq); |
2f7eb47a LB |
2144 | } |
2145 | } | |
2146 | return; | |
2147 | } | |
2148 | ||
2149 | switch (port_status & PORT_SPEED_MASK) { | |
2150 | case PORT_SPEED_10: | |
2151 | speed = 10; | |
2152 | break; | |
2153 | case PORT_SPEED_100: | |
2154 | speed = 100; | |
2155 | break; | |
2156 | case PORT_SPEED_1000: | |
2157 | speed = 1000; | |
2158 | break; | |
2159 | default: | |
2160 | speed = -1; | |
2161 | break; | |
2162 | } | |
2163 | duplex = (port_status & FULL_DUPLEX) ? 1 : 0; | |
2164 | fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0; | |
2165 | ||
2166 | printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, " | |
2167 | "flow control %sabled\n", dev->name, | |
2168 | speed, duplex ? "full" : "half", | |
2169 | fc ? "en" : "dis"); | |
2170 | ||
4fdeca3f | 2171 | if (!netif_carrier_ok(dev)) |
2f7eb47a | 2172 | netif_carrier_on(dev); |
2f7eb47a LB |
2173 | } |
2174 | ||
1fa38c58 | 2175 | static int mv643xx_eth_poll(struct napi_struct *napi, int budget) |
c9df406f | 2176 | { |
1fa38c58 LB |
2177 | struct mv643xx_eth_private *mp; |
2178 | int work_done; | |
ce4e2e45 | 2179 | |
1fa38c58 | 2180 | mp = container_of(napi, struct mv643xx_eth_private, napi); |
fc32b0e2 | 2181 | |
1fa38c58 LB |
2182 | mp->work_rx_refill |= mp->work_rx_oom; |
2183 | mp->work_rx_oom = 0; | |
1da177e4 | 2184 | |
1fa38c58 LB |
2185 | work_done = 0; |
2186 | while (work_done < budget) { | |
2187 | u8 queue_mask; | |
2188 | int queue; | |
2189 | int work_tbd; | |
2190 | ||
2191 | if (mp->work_link) { | |
2192 | mp->work_link = 0; | |
2193 | handle_link_event(mp); | |
2194 | continue; | |
2195 | } | |
1da177e4 | 2196 | |
1fa38c58 LB |
2197 | queue_mask = mp->work_tx | mp->work_tx_end | |
2198 | mp->work_rx | mp->work_rx_refill; | |
2199 | if (!queue_mask) { | |
2200 | if (mv643xx_eth_collect_events(mp)) | |
2201 | continue; | |
2202 | break; | |
2203 | } | |
1da177e4 | 2204 | |
1fa38c58 LB |
2205 | queue = fls(queue_mask) - 1; |
2206 | queue_mask = 1 << queue; | |
2207 | ||
2208 | work_tbd = budget - work_done; | |
2209 | if (work_tbd > 16) | |
2210 | work_tbd = 16; | |
2211 | ||
2212 | if (mp->work_tx_end & queue_mask) { | |
2213 | txq_kick(mp->txq + queue); | |
2214 | } else if (mp->work_tx & queue_mask) { | |
2215 | work_done += txq_reclaim(mp->txq + queue, work_tbd, 0); | |
2216 | txq_maybe_wake(mp->txq + queue); | |
2217 | } else if (mp->work_rx & queue_mask) { | |
2218 | work_done += rxq_process(mp->rxq + queue, work_tbd); | |
2219 | } else if (mp->work_rx_refill & queue_mask) { | |
2220 | work_done += rxq_refill(mp->rxq + queue, work_tbd); | |
2221 | } else { | |
2222 | BUG(); | |
2223 | } | |
84dd619e | 2224 | } |
fc32b0e2 | 2225 | |
1fa38c58 LB |
2226 | if (work_done < budget) { |
2227 | if (mp->work_rx_oom) | |
2228 | mod_timer(&mp->rx_oom, jiffies + (HZ / 10)); | |
2229 | napi_complete(napi); | |
37a6084f | 2230 | wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT); |
226bb6b7 | 2231 | } |
3d6b35bc | 2232 | |
1fa38c58 LB |
2233 | return work_done; |
2234 | } | |
8fa89bf5 | 2235 | |
1fa38c58 LB |
2236 | static inline void oom_timer_wrapper(unsigned long data) |
2237 | { | |
2238 | struct mv643xx_eth_private *mp = (void *)data; | |
1da177e4 | 2239 | |
1fa38c58 | 2240 | napi_schedule(&mp->napi); |
1da177e4 LT |
2241 | } |
2242 | ||
e5371493 | 2243 | static void phy_reset(struct mv643xx_eth_private *mp) |
1da177e4 | 2244 | { |
45c5d3bc LB |
2245 | int data; |
2246 | ||
ed94493f | 2247 | data = phy_read(mp->phy, MII_BMCR); |
45c5d3bc LB |
2248 | if (data < 0) |
2249 | return; | |
1da177e4 | 2250 | |
7f106c1d | 2251 | data |= BMCR_RESET; |
ed94493f | 2252 | if (phy_write(mp->phy, MII_BMCR, data) < 0) |
45c5d3bc | 2253 | return; |
1da177e4 | 2254 | |
c9df406f | 2255 | do { |
ed94493f | 2256 | data = phy_read(mp->phy, MII_BMCR); |
45c5d3bc | 2257 | } while (data >= 0 && data & BMCR_RESET); |
1da177e4 LT |
2258 | } |
2259 | ||
fc32b0e2 | 2260 | static void port_start(struct mv643xx_eth_private *mp) |
1da177e4 | 2261 | { |
d0412d96 | 2262 | u32 pscr; |
8a578111 | 2263 | int i; |
1da177e4 | 2264 | |
bedfe324 LB |
2265 | /* |
2266 | * Perform PHY reset, if there is a PHY. | |
2267 | */ | |
ed94493f | 2268 | if (mp->phy != NULL) { |
bedfe324 LB |
2269 | struct ethtool_cmd cmd; |
2270 | ||
2271 | mv643xx_eth_get_settings(mp->dev, &cmd); | |
2272 | phy_reset(mp); | |
2273 | mv643xx_eth_set_settings(mp->dev, &cmd); | |
2274 | } | |
1da177e4 | 2275 | |
81600eea LB |
2276 | /* |
2277 | * Configure basic link parameters. | |
2278 | */ | |
37a6084f | 2279 | pscr = rdlp(mp, PORT_SERIAL_CONTROL); |
81600eea LB |
2280 | |
2281 | pscr |= SERIAL_PORT_ENABLE; | |
37a6084f | 2282 | wrlp(mp, PORT_SERIAL_CONTROL, pscr); |
81600eea LB |
2283 | |
2284 | pscr |= DO_NOT_FORCE_LINK_FAIL; | |
ed94493f | 2285 | if (mp->phy == NULL) |
81600eea | 2286 | pscr |= FORCE_LINK_PASS; |
37a6084f | 2287 | wrlp(mp, PORT_SERIAL_CONTROL, pscr); |
81600eea | 2288 | |
37a6084f | 2289 | wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE); |
81600eea | 2290 | |
13d64285 LB |
2291 | /* |
2292 | * Configure TX path and queues. | |
2293 | */ | |
89df5fdc | 2294 | tx_set_rate(mp, 1000000000, 16777216); |
f7981c1c | 2295 | for (i = 0; i < mp->txq_count; i++) { |
3d6b35bc | 2296 | struct tx_queue *txq = mp->txq + i; |
13d64285 | 2297 | |
6b368f68 | 2298 | txq_reset_hw_ptr(txq); |
89df5fdc LB |
2299 | txq_set_rate(txq, 1000000000, 16777216); |
2300 | txq_set_fixed_prio_mode(txq); | |
13d64285 LB |
2301 | } |
2302 | ||
fc32b0e2 LB |
2303 | /* |
2304 | * Add configured unicast address to address filter table. | |
2305 | */ | |
66e63ffb | 2306 | mv643xx_eth_program_unicast_filter(mp->dev); |
1da177e4 | 2307 | |
d9a073ea LB |
2308 | /* |
2309 | * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast | |
170e7108 LB |
2310 | * frames to RX queue #0, and include the pseudo-header when |
2311 | * calculating receive checksums. | |
d9a073ea | 2312 | */ |
37a6084f | 2313 | wrlp(mp, PORT_CONFIG, 0x02000000); |
01999873 | 2314 | |
376489a2 LB |
2315 | /* |
2316 | * Treat BPDUs as normal multicasts, and disable partition mode. | |
2317 | */ | |
37a6084f | 2318 | wrlp(mp, PORT_CONFIG_EXT, 0x00000000); |
01999873 | 2319 | |
8a578111 | 2320 | /* |
64da80a2 | 2321 | * Enable the receive queues. |
8a578111 | 2322 | */ |
f7981c1c | 2323 | for (i = 0; i < mp->rxq_count; i++) { |
64da80a2 | 2324 | struct rx_queue *rxq = mp->rxq + i; |
8a578111 | 2325 | u32 addr; |
1da177e4 | 2326 | |
8a578111 LB |
2327 | addr = (u32)rxq->rx_desc_dma; |
2328 | addr += rxq->rx_curr_desc * sizeof(struct rx_desc); | |
37a6084f | 2329 | wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr); |
1da177e4 | 2330 | |
8a578111 LB |
2331 | rxq_enable(rxq); |
2332 | } | |
1da177e4 LT |
2333 | } |
2334 | ||
2bcb4b0f LB |
2335 | static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp) |
2336 | { | |
2337 | int skb_size; | |
2338 | ||
2339 | /* | |
2340 | * Reserve 2+14 bytes for an ethernet header (the hardware | |
2341 | * automatically prepends 2 bytes of dummy data to each | |
2342 | * received packet), 16 bytes for up to four VLAN tags, and | |
2343 | * 4 bytes for the trailing FCS -- 36 bytes total. | |
2344 | */ | |
2345 | skb_size = mp->dev->mtu + 36; | |
2346 | ||
2347 | /* | |
2348 | * Make sure that the skb size is a multiple of 8 bytes, as | |
2349 | * the lower three bits of the receive descriptor's buffer | |
2350 | * size field are ignored by the hardware. | |
2351 | */ | |
2352 | mp->skb_size = (skb_size + 7) & ~7; | |
2353 | } | |
2354 | ||
c9df406f | 2355 | static int mv643xx_eth_open(struct net_device *dev) |
16e03018 | 2356 | { |
e5371493 | 2357 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f | 2358 | int err; |
64da80a2 | 2359 | int i; |
16e03018 | 2360 | |
37a6084f LB |
2361 | wrlp(mp, INT_CAUSE, 0); |
2362 | wrlp(mp, INT_CAUSE_EXT, 0); | |
2363 | rdlp(mp, INT_CAUSE_EXT); | |
c9df406f | 2364 | |
fc32b0e2 | 2365 | err = request_irq(dev->irq, mv643xx_eth_irq, |
2a1867a7 | 2366 | IRQF_SHARED, dev->name, dev); |
c9df406f | 2367 | if (err) { |
fc32b0e2 | 2368 | dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n"); |
c9df406f | 2369 | return -EAGAIN; |
16e03018 DF |
2370 | } |
2371 | ||
2bcb4b0f LB |
2372 | mv643xx_eth_recalc_skb_size(mp); |
2373 | ||
2257e05c LB |
2374 | napi_enable(&mp->napi); |
2375 | ||
2bcb4b0f LB |
2376 | skb_queue_head_init(&mp->rx_recycle); |
2377 | ||
f7981c1c | 2378 | for (i = 0; i < mp->rxq_count; i++) { |
64da80a2 LB |
2379 | err = rxq_init(mp, i); |
2380 | if (err) { | |
2381 | while (--i >= 0) | |
f7981c1c | 2382 | rxq_deinit(mp->rxq + i); |
64da80a2 LB |
2383 | goto out; |
2384 | } | |
2385 | ||
1fa38c58 | 2386 | rxq_refill(mp->rxq + i, INT_MAX); |
2257e05c LB |
2387 | } |
2388 | ||
1fa38c58 | 2389 | if (mp->work_rx_oom) { |
2257e05c LB |
2390 | mp->rx_oom.expires = jiffies + (HZ / 10); |
2391 | add_timer(&mp->rx_oom); | |
64da80a2 | 2392 | } |
8a578111 | 2393 | |
f7981c1c | 2394 | for (i = 0; i < mp->txq_count; i++) { |
3d6b35bc LB |
2395 | err = txq_init(mp, i); |
2396 | if (err) { | |
2397 | while (--i >= 0) | |
f7981c1c | 2398 | txq_deinit(mp->txq + i); |
3d6b35bc LB |
2399 | goto out_free; |
2400 | } | |
2401 | } | |
16e03018 | 2402 | |
2f7eb47a | 2403 | netif_carrier_off(dev); |
2f7eb47a | 2404 | |
fc32b0e2 | 2405 | port_start(mp); |
16e03018 | 2406 | |
ffd86bbe LB |
2407 | set_rx_coal(mp, 0); |
2408 | set_tx_coal(mp, 0); | |
16e03018 | 2409 | |
37a6084f LB |
2410 | wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX); |
2411 | wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT); | |
16e03018 | 2412 | |
c9df406f LB |
2413 | return 0; |
2414 | ||
13d64285 | 2415 | |
fc32b0e2 | 2416 | out_free: |
f7981c1c LB |
2417 | for (i = 0; i < mp->rxq_count; i++) |
2418 | rxq_deinit(mp->rxq + i); | |
fc32b0e2 | 2419 | out: |
c9df406f LB |
2420 | free_irq(dev->irq, dev); |
2421 | ||
2422 | return err; | |
16e03018 DF |
2423 | } |
2424 | ||
e5371493 | 2425 | static void port_reset(struct mv643xx_eth_private *mp) |
1da177e4 | 2426 | { |
fc32b0e2 | 2427 | unsigned int data; |
64da80a2 | 2428 | int i; |
1da177e4 | 2429 | |
f7981c1c LB |
2430 | for (i = 0; i < mp->rxq_count; i++) |
2431 | rxq_disable(mp->rxq + i); | |
2432 | for (i = 0; i < mp->txq_count; i++) | |
2433 | txq_disable(mp->txq + i); | |
ae9ae064 LB |
2434 | |
2435 | while (1) { | |
37a6084f | 2436 | u32 ps = rdlp(mp, PORT_STATUS); |
ae9ae064 LB |
2437 | |
2438 | if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY) | |
2439 | break; | |
13d64285 | 2440 | udelay(10); |
ae9ae064 | 2441 | } |
1da177e4 | 2442 | |
c9df406f | 2443 | /* Reset the Enable bit in the Configuration Register */ |
37a6084f | 2444 | data = rdlp(mp, PORT_SERIAL_CONTROL); |
fc32b0e2 LB |
2445 | data &= ~(SERIAL_PORT_ENABLE | |
2446 | DO_NOT_FORCE_LINK_FAIL | | |
2447 | FORCE_LINK_PASS); | |
37a6084f | 2448 | wrlp(mp, PORT_SERIAL_CONTROL, data); |
1da177e4 LT |
2449 | } |
2450 | ||
c9df406f | 2451 | static int mv643xx_eth_stop(struct net_device *dev) |
1da177e4 | 2452 | { |
e5371493 | 2453 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
64da80a2 | 2454 | int i; |
1da177e4 | 2455 | |
fe65e704 | 2456 | wrlp(mp, INT_MASK_EXT, 0x00000000); |
37a6084f LB |
2457 | wrlp(mp, INT_MASK, 0x00000000); |
2458 | rdlp(mp, INT_MASK); | |
1da177e4 | 2459 | |
4ff3495a LB |
2460 | del_timer_sync(&mp->mib_counters_timer); |
2461 | ||
c9df406f | 2462 | napi_disable(&mp->napi); |
78fff83b | 2463 | |
2257e05c LB |
2464 | del_timer_sync(&mp->rx_oom); |
2465 | ||
c9df406f | 2466 | netif_carrier_off(dev); |
1da177e4 | 2467 | |
fc32b0e2 LB |
2468 | free_irq(dev->irq, dev); |
2469 | ||
cc9754b3 | 2470 | port_reset(mp); |
8fd89211 | 2471 | mv643xx_eth_get_stats(dev); |
fc32b0e2 | 2472 | mib_counters_update(mp); |
1da177e4 | 2473 | |
2bcb4b0f LB |
2474 | skb_queue_purge(&mp->rx_recycle); |
2475 | ||
f7981c1c LB |
2476 | for (i = 0; i < mp->rxq_count; i++) |
2477 | rxq_deinit(mp->rxq + i); | |
2478 | for (i = 0; i < mp->txq_count; i++) | |
2479 | txq_deinit(mp->txq + i); | |
1da177e4 | 2480 | |
c9df406f | 2481 | return 0; |
1da177e4 LT |
2482 | } |
2483 | ||
fc32b0e2 | 2484 | static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
1da177e4 | 2485 | { |
e5371493 | 2486 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 2487 | |
ed94493f LB |
2488 | if (mp->phy != NULL) |
2489 | return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd); | |
bedfe324 LB |
2490 | |
2491 | return -EOPNOTSUPP; | |
1da177e4 LT |
2492 | } |
2493 | ||
c9df406f | 2494 | static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu) |
1da177e4 | 2495 | { |
89df5fdc LB |
2496 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
2497 | ||
fc32b0e2 | 2498 | if (new_mtu < 64 || new_mtu > 9500) |
c9df406f | 2499 | return -EINVAL; |
1da177e4 | 2500 | |
c9df406f | 2501 | dev->mtu = new_mtu; |
2bcb4b0f | 2502 | mv643xx_eth_recalc_skb_size(mp); |
89df5fdc LB |
2503 | tx_set_rate(mp, 1000000000, 16777216); |
2504 | ||
c9df406f LB |
2505 | if (!netif_running(dev)) |
2506 | return 0; | |
1da177e4 | 2507 | |
c9df406f LB |
2508 | /* |
2509 | * Stop and then re-open the interface. This will allocate RX | |
2510 | * skbs of the new MTU. | |
2511 | * There is a possible danger that the open will not succeed, | |
fc32b0e2 | 2512 | * due to memory being full. |
c9df406f LB |
2513 | */ |
2514 | mv643xx_eth_stop(dev); | |
2515 | if (mv643xx_eth_open(dev)) { | |
fc32b0e2 LB |
2516 | dev_printk(KERN_ERR, &dev->dev, |
2517 | "fatal error on re-opening device after " | |
2518 | "MTU change\n"); | |
c9df406f LB |
2519 | } |
2520 | ||
2521 | return 0; | |
1da177e4 LT |
2522 | } |
2523 | ||
fc32b0e2 | 2524 | static void tx_timeout_task(struct work_struct *ugly) |
1da177e4 | 2525 | { |
fc32b0e2 | 2526 | struct mv643xx_eth_private *mp; |
1da177e4 | 2527 | |
fc32b0e2 LB |
2528 | mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task); |
2529 | if (netif_running(mp->dev)) { | |
e5ef1de1 | 2530 | netif_tx_stop_all_queues(mp->dev); |
fc32b0e2 LB |
2531 | port_reset(mp); |
2532 | port_start(mp); | |
e5ef1de1 | 2533 | netif_tx_wake_all_queues(mp->dev); |
fc32b0e2 | 2534 | } |
c9df406f LB |
2535 | } |
2536 | ||
c9df406f | 2537 | static void mv643xx_eth_tx_timeout(struct net_device *dev) |
1da177e4 | 2538 | { |
e5371493 | 2539 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 2540 | |
fc32b0e2 | 2541 | dev_printk(KERN_INFO, &dev->dev, "tx timeout\n"); |
d0412d96 | 2542 | |
c9df406f | 2543 | schedule_work(&mp->tx_timeout_task); |
1da177e4 LT |
2544 | } |
2545 | ||
c9df406f | 2546 | #ifdef CONFIG_NET_POLL_CONTROLLER |
fc32b0e2 | 2547 | static void mv643xx_eth_netpoll(struct net_device *dev) |
9f8dd319 | 2548 | { |
fc32b0e2 | 2549 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f | 2550 | |
37a6084f LB |
2551 | wrlp(mp, INT_MASK, 0x00000000); |
2552 | rdlp(mp, INT_MASK); | |
c9df406f | 2553 | |
fc32b0e2 | 2554 | mv643xx_eth_irq(dev->irq, dev); |
c9df406f | 2555 | |
37a6084f | 2556 | wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT); |
9f8dd319 | 2557 | } |
c9df406f | 2558 | #endif |
9f8dd319 | 2559 | |
9f8dd319 | 2560 | |
c9df406f | 2561 | /* platform glue ************************************************************/ |
e5371493 LB |
2562 | static void |
2563 | mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp, | |
2564 | struct mbus_dram_target_info *dram) | |
c9df406f | 2565 | { |
cc9754b3 | 2566 | void __iomem *base = msp->base; |
c9df406f LB |
2567 | u32 win_enable; |
2568 | u32 win_protect; | |
2569 | int i; | |
9f8dd319 | 2570 | |
c9df406f LB |
2571 | for (i = 0; i < 6; i++) { |
2572 | writel(0, base + WINDOW_BASE(i)); | |
2573 | writel(0, base + WINDOW_SIZE(i)); | |
2574 | if (i < 4) | |
2575 | writel(0, base + WINDOW_REMAP_HIGH(i)); | |
9f8dd319 DF |
2576 | } |
2577 | ||
c9df406f LB |
2578 | win_enable = 0x3f; |
2579 | win_protect = 0; | |
2580 | ||
2581 | for (i = 0; i < dram->num_cs; i++) { | |
2582 | struct mbus_dram_window *cs = dram->cs + i; | |
2583 | ||
2584 | writel((cs->base & 0xffff0000) | | |
2585 | (cs->mbus_attr << 8) | | |
2586 | dram->mbus_dram_target_id, base + WINDOW_BASE(i)); | |
2587 | writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); | |
2588 | ||
2589 | win_enable &= ~(1 << i); | |
2590 | win_protect |= 3 << (2 * i); | |
2591 | } | |
2592 | ||
2593 | writel(win_enable, base + WINDOW_BAR_ENABLE); | |
2594 | msp->win_protect = win_protect; | |
9f8dd319 DF |
2595 | } |
2596 | ||
773fc3ee LB |
2597 | static void infer_hw_params(struct mv643xx_eth_shared_private *msp) |
2598 | { | |
2599 | /* | |
2600 | * Check whether we have a 14-bit coal limit field in bits | |
2601 | * [21:8], or a 16-bit coal limit in bits [25,21:7] of the | |
2602 | * SDMA config register. | |
2603 | */ | |
37a6084f LB |
2604 | writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG); |
2605 | if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000) | |
773fc3ee LB |
2606 | msp->extended_rx_coal_limit = 1; |
2607 | else | |
2608 | msp->extended_rx_coal_limit = 0; | |
1e881592 LB |
2609 | |
2610 | /* | |
457b1d5a LB |
2611 | * Check whether the MAC supports TX rate control, and if |
2612 | * yes, whether its associated registers are in the old or | |
2613 | * the new place. | |
1e881592 | 2614 | */ |
37a6084f LB |
2615 | writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED); |
2616 | if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) { | |
457b1d5a LB |
2617 | msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT; |
2618 | } else { | |
37a6084f LB |
2619 | writel(7, msp->base + 0x0400 + TX_BW_RATE); |
2620 | if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7) | |
457b1d5a LB |
2621 | msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT; |
2622 | else | |
2623 | msp->tx_bw_control = TX_BW_CONTROL_ABSENT; | |
2624 | } | |
773fc3ee LB |
2625 | } |
2626 | ||
c9df406f | 2627 | static int mv643xx_eth_shared_probe(struct platform_device *pdev) |
9f8dd319 | 2628 | { |
10a9948d | 2629 | static int mv643xx_eth_version_printed; |
c9df406f | 2630 | struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data; |
e5371493 | 2631 | struct mv643xx_eth_shared_private *msp; |
c9df406f LB |
2632 | struct resource *res; |
2633 | int ret; | |
9f8dd319 | 2634 | |
e5371493 | 2635 | if (!mv643xx_eth_version_printed++) |
7dde154d LB |
2636 | printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet " |
2637 | "driver version %s\n", mv643xx_eth_driver_version); | |
9f8dd319 | 2638 | |
c9df406f LB |
2639 | ret = -EINVAL; |
2640 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2641 | if (res == NULL) | |
2642 | goto out; | |
9f8dd319 | 2643 | |
c9df406f LB |
2644 | ret = -ENOMEM; |
2645 | msp = kmalloc(sizeof(*msp), GFP_KERNEL); | |
2646 | if (msp == NULL) | |
2647 | goto out; | |
2648 | memset(msp, 0, sizeof(*msp)); | |
2649 | ||
cc9754b3 LB |
2650 | msp->base = ioremap(res->start, res->end - res->start + 1); |
2651 | if (msp->base == NULL) | |
c9df406f LB |
2652 | goto out_free; |
2653 | ||
ed94493f LB |
2654 | /* |
2655 | * Set up and register SMI bus. | |
2656 | */ | |
2657 | if (pd == NULL || pd->shared_smi == NULL) { | |
298cf9be LB |
2658 | msp->smi_bus = mdiobus_alloc(); |
2659 | if (msp->smi_bus == NULL) | |
ed94493f | 2660 | goto out_unmap; |
298cf9be LB |
2661 | |
2662 | msp->smi_bus->priv = msp; | |
2663 | msp->smi_bus->name = "mv643xx_eth smi"; | |
2664 | msp->smi_bus->read = smi_bus_read; | |
2665 | msp->smi_bus->write = smi_bus_write, | |
2666 | snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id); | |
2667 | msp->smi_bus->parent = &pdev->dev; | |
2668 | msp->smi_bus->phy_mask = 0xffffffff; | |
2669 | if (mdiobus_register(msp->smi_bus) < 0) | |
2670 | goto out_free_mii_bus; | |
ed94493f LB |
2671 | msp->smi = msp; |
2672 | } else { | |
fc0eb9f2 | 2673 | msp->smi = platform_get_drvdata(pd->shared_smi); |
ed94493f | 2674 | } |
c9df406f | 2675 | |
45c5d3bc LB |
2676 | msp->err_interrupt = NO_IRQ; |
2677 | init_waitqueue_head(&msp->smi_busy_wait); | |
2678 | ||
2679 | /* | |
2680 | * Check whether the error interrupt is hooked up. | |
2681 | */ | |
2682 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
2683 | if (res != NULL) { | |
2684 | int err; | |
2685 | ||
2686 | err = request_irq(res->start, mv643xx_eth_err_irq, | |
2687 | IRQF_SHARED, "mv643xx_eth", msp); | |
2688 | if (!err) { | |
2689 | writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK); | |
2690 | msp->err_interrupt = res->start; | |
2691 | } | |
2692 | } | |
2693 | ||
c9df406f LB |
2694 | /* |
2695 | * (Re-)program MBUS remapping windows if we are asked to. | |
2696 | */ | |
2697 | if (pd != NULL && pd->dram != NULL) | |
2698 | mv643xx_eth_conf_mbus_windows(msp, pd->dram); | |
2699 | ||
fc32b0e2 LB |
2700 | /* |
2701 | * Detect hardware parameters. | |
2702 | */ | |
2703 | msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000; | |
773fc3ee | 2704 | infer_hw_params(msp); |
fc32b0e2 LB |
2705 | |
2706 | platform_set_drvdata(pdev, msp); | |
2707 | ||
c9df406f LB |
2708 | return 0; |
2709 | ||
298cf9be LB |
2710 | out_free_mii_bus: |
2711 | mdiobus_free(msp->smi_bus); | |
ed94493f LB |
2712 | out_unmap: |
2713 | iounmap(msp->base); | |
c9df406f LB |
2714 | out_free: |
2715 | kfree(msp); | |
2716 | out: | |
2717 | return ret; | |
2718 | } | |
2719 | ||
2720 | static int mv643xx_eth_shared_remove(struct platform_device *pdev) | |
2721 | { | |
e5371493 | 2722 | struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev); |
ed94493f | 2723 | struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data; |
c9df406f | 2724 | |
298cf9be | 2725 | if (pd == NULL || pd->shared_smi == NULL) { |
298cf9be | 2726 | mdiobus_unregister(msp->smi_bus); |
bcb3336c | 2727 | mdiobus_free(msp->smi_bus); |
298cf9be | 2728 | } |
45c5d3bc LB |
2729 | if (msp->err_interrupt != NO_IRQ) |
2730 | free_irq(msp->err_interrupt, msp); | |
cc9754b3 | 2731 | iounmap(msp->base); |
c9df406f LB |
2732 | kfree(msp); |
2733 | ||
2734 | return 0; | |
9f8dd319 DF |
2735 | } |
2736 | ||
c9df406f | 2737 | static struct platform_driver mv643xx_eth_shared_driver = { |
fc32b0e2 LB |
2738 | .probe = mv643xx_eth_shared_probe, |
2739 | .remove = mv643xx_eth_shared_remove, | |
c9df406f | 2740 | .driver = { |
fc32b0e2 | 2741 | .name = MV643XX_ETH_SHARED_NAME, |
c9df406f LB |
2742 | .owner = THIS_MODULE, |
2743 | }, | |
2744 | }; | |
2745 | ||
e5371493 | 2746 | static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr) |
1da177e4 | 2747 | { |
c9df406f | 2748 | int addr_shift = 5 * mp->port_num; |
fc32b0e2 | 2749 | u32 data; |
1da177e4 | 2750 | |
fc32b0e2 LB |
2751 | data = rdl(mp, PHY_ADDR); |
2752 | data &= ~(0x1f << addr_shift); | |
2753 | data |= (phy_addr & 0x1f) << addr_shift; | |
2754 | wrl(mp, PHY_ADDR, data); | |
1da177e4 LT |
2755 | } |
2756 | ||
e5371493 | 2757 | static int phy_addr_get(struct mv643xx_eth_private *mp) |
1da177e4 | 2758 | { |
fc32b0e2 LB |
2759 | unsigned int data; |
2760 | ||
2761 | data = rdl(mp, PHY_ADDR); | |
2762 | ||
2763 | return (data >> (5 * mp->port_num)) & 0x1f; | |
2764 | } | |
2765 | ||
2766 | static void set_params(struct mv643xx_eth_private *mp, | |
2767 | struct mv643xx_eth_platform_data *pd) | |
2768 | { | |
2769 | struct net_device *dev = mp->dev; | |
2770 | ||
2771 | if (is_valid_ether_addr(pd->mac_addr)) | |
2772 | memcpy(dev->dev_addr, pd->mac_addr, 6); | |
2773 | else | |
2774 | uc_addr_get(mp, dev->dev_addr); | |
2775 | ||
e7d2f4db | 2776 | mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE; |
fc32b0e2 | 2777 | if (pd->rx_queue_size) |
e7d2f4db | 2778 | mp->rx_ring_size = pd->rx_queue_size; |
fc32b0e2 LB |
2779 | mp->rx_desc_sram_addr = pd->rx_sram_addr; |
2780 | mp->rx_desc_sram_size = pd->rx_sram_size; | |
1da177e4 | 2781 | |
f7981c1c | 2782 | mp->rxq_count = pd->rx_queue_count ? : 1; |
64da80a2 | 2783 | |
e7d2f4db | 2784 | mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE; |
fc32b0e2 | 2785 | if (pd->tx_queue_size) |
e7d2f4db | 2786 | mp->tx_ring_size = pd->tx_queue_size; |
fc32b0e2 LB |
2787 | mp->tx_desc_sram_addr = pd->tx_sram_addr; |
2788 | mp->tx_desc_sram_size = pd->tx_sram_size; | |
3d6b35bc | 2789 | |
f7981c1c | 2790 | mp->txq_count = pd->tx_queue_count ? : 1; |
1da177e4 LT |
2791 | } |
2792 | ||
ed94493f LB |
2793 | static struct phy_device *phy_scan(struct mv643xx_eth_private *mp, |
2794 | int phy_addr) | |
1da177e4 | 2795 | { |
298cf9be | 2796 | struct mii_bus *bus = mp->shared->smi->smi_bus; |
ed94493f LB |
2797 | struct phy_device *phydev; |
2798 | int start; | |
2799 | int num; | |
2800 | int i; | |
45c5d3bc | 2801 | |
ed94493f LB |
2802 | if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) { |
2803 | start = phy_addr_get(mp) & 0x1f; | |
2804 | num = 32; | |
2805 | } else { | |
2806 | start = phy_addr & 0x1f; | |
2807 | num = 1; | |
2808 | } | |
45c5d3bc | 2809 | |
ed94493f LB |
2810 | phydev = NULL; |
2811 | for (i = 0; i < num; i++) { | |
2812 | int addr = (start + i) & 0x1f; | |
fc32b0e2 | 2813 | |
ed94493f LB |
2814 | if (bus->phy_map[addr] == NULL) |
2815 | mdiobus_scan(bus, addr); | |
1da177e4 | 2816 | |
ed94493f LB |
2817 | if (phydev == NULL) { |
2818 | phydev = bus->phy_map[addr]; | |
2819 | if (phydev != NULL) | |
2820 | phy_addr_set(mp, addr); | |
2821 | } | |
2822 | } | |
1da177e4 | 2823 | |
ed94493f | 2824 | return phydev; |
1da177e4 LT |
2825 | } |
2826 | ||
ed94493f | 2827 | static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex) |
c28a4f89 | 2828 | { |
ed94493f | 2829 | struct phy_device *phy = mp->phy; |
c28a4f89 | 2830 | |
fc32b0e2 LB |
2831 | phy_reset(mp); |
2832 | ||
db1d7bf7 | 2833 | phy_attach(mp->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_GMII); |
ed94493f LB |
2834 | |
2835 | if (speed == 0) { | |
2836 | phy->autoneg = AUTONEG_ENABLE; | |
2837 | phy->speed = 0; | |
2838 | phy->duplex = 0; | |
2839 | phy->advertising = phy->supported | ADVERTISED_Autoneg; | |
c9df406f | 2840 | } else { |
ed94493f LB |
2841 | phy->autoneg = AUTONEG_DISABLE; |
2842 | phy->advertising = 0; | |
2843 | phy->speed = speed; | |
2844 | phy->duplex = duplex; | |
c9df406f | 2845 | } |
ed94493f | 2846 | phy_start_aneg(phy); |
c28a4f89 JC |
2847 | } |
2848 | ||
81600eea LB |
2849 | static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex) |
2850 | { | |
2851 | u32 pscr; | |
2852 | ||
37a6084f | 2853 | pscr = rdlp(mp, PORT_SERIAL_CONTROL); |
81600eea LB |
2854 | if (pscr & SERIAL_PORT_ENABLE) { |
2855 | pscr &= ~SERIAL_PORT_ENABLE; | |
37a6084f | 2856 | wrlp(mp, PORT_SERIAL_CONTROL, pscr); |
81600eea LB |
2857 | } |
2858 | ||
2859 | pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED; | |
ed94493f | 2860 | if (mp->phy == NULL) { |
81600eea LB |
2861 | pscr |= DISABLE_AUTO_NEG_SPEED_GMII; |
2862 | if (speed == SPEED_1000) | |
2863 | pscr |= SET_GMII_SPEED_TO_1000; | |
2864 | else if (speed == SPEED_100) | |
2865 | pscr |= SET_MII_SPEED_TO_100; | |
2866 | ||
2867 | pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL; | |
2868 | ||
2869 | pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX; | |
2870 | if (duplex == DUPLEX_FULL) | |
2871 | pscr |= SET_FULL_DUPLEX_MODE; | |
2872 | } | |
2873 | ||
37a6084f | 2874 | wrlp(mp, PORT_SERIAL_CONTROL, pscr); |
81600eea LB |
2875 | } |
2876 | ||
c9df406f | 2877 | static int mv643xx_eth_probe(struct platform_device *pdev) |
1da177e4 | 2878 | { |
c9df406f | 2879 | struct mv643xx_eth_platform_data *pd; |
e5371493 | 2880 | struct mv643xx_eth_private *mp; |
c9df406f | 2881 | struct net_device *dev; |
c9df406f | 2882 | struct resource *res; |
fc32b0e2 | 2883 | int err; |
1da177e4 | 2884 | |
c9df406f LB |
2885 | pd = pdev->dev.platform_data; |
2886 | if (pd == NULL) { | |
fc32b0e2 LB |
2887 | dev_printk(KERN_ERR, &pdev->dev, |
2888 | "no mv643xx_eth_platform_data\n"); | |
c9df406f LB |
2889 | return -ENODEV; |
2890 | } | |
1da177e4 | 2891 | |
c9df406f | 2892 | if (pd->shared == NULL) { |
fc32b0e2 LB |
2893 | dev_printk(KERN_ERR, &pdev->dev, |
2894 | "no mv643xx_eth_platform_data->shared\n"); | |
c9df406f LB |
2895 | return -ENODEV; |
2896 | } | |
8f518703 | 2897 | |
e5ef1de1 | 2898 | dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8); |
c9df406f LB |
2899 | if (!dev) |
2900 | return -ENOMEM; | |
1da177e4 | 2901 | |
c9df406f | 2902 | mp = netdev_priv(dev); |
fc32b0e2 LB |
2903 | platform_set_drvdata(pdev, mp); |
2904 | ||
2905 | mp->shared = platform_get_drvdata(pd->shared); | |
37a6084f | 2906 | mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10); |
fc32b0e2 LB |
2907 | mp->port_num = pd->port_number; |
2908 | ||
c9df406f | 2909 | mp->dev = dev; |
78fff83b | 2910 | |
fc32b0e2 | 2911 | set_params(mp, pd); |
e5ef1de1 | 2912 | dev->real_num_tx_queues = mp->txq_count; |
fc32b0e2 | 2913 | |
ed94493f LB |
2914 | if (pd->phy_addr != MV643XX_ETH_PHY_NONE) |
2915 | mp->phy = phy_scan(mp, pd->phy_addr); | |
bedfe324 | 2916 | |
6bdf576e | 2917 | if (mp->phy != NULL) |
ed94493f | 2918 | phy_init(mp, pd->speed, pd->duplex); |
6bdf576e LB |
2919 | |
2920 | SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops); | |
ed94493f | 2921 | |
81600eea | 2922 | init_pscr(mp, pd->speed, pd->duplex); |
fc32b0e2 | 2923 | |
4ff3495a LB |
2924 | |
2925 | mib_counters_clear(mp); | |
2926 | ||
2927 | init_timer(&mp->mib_counters_timer); | |
2928 | mp->mib_counters_timer.data = (unsigned long)mp; | |
2929 | mp->mib_counters_timer.function = mib_counters_timer_wrapper; | |
2930 | mp->mib_counters_timer.expires = jiffies + 30 * HZ; | |
2931 | add_timer(&mp->mib_counters_timer); | |
2932 | ||
2933 | spin_lock_init(&mp->mib_counters_lock); | |
2934 | ||
2935 | INIT_WORK(&mp->tx_timeout_task, tx_timeout_task); | |
2936 | ||
2257e05c LB |
2937 | netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128); |
2938 | ||
2939 | init_timer(&mp->rx_oom); | |
2940 | mp->rx_oom.data = (unsigned long)mp; | |
2941 | mp->rx_oom.function = oom_timer_wrapper; | |
2942 | ||
fc32b0e2 | 2943 | |
c9df406f LB |
2944 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
2945 | BUG_ON(!res); | |
2946 | dev->irq = res->start; | |
1da177e4 | 2947 | |
8fd89211 | 2948 | dev->get_stats = mv643xx_eth_get_stats; |
fc32b0e2 | 2949 | dev->hard_start_xmit = mv643xx_eth_xmit; |
c9df406f LB |
2950 | dev->open = mv643xx_eth_open; |
2951 | dev->stop = mv643xx_eth_stop; | |
66e63ffb | 2952 | dev->set_rx_mode = mv643xx_eth_set_rx_mode; |
fc32b0e2 LB |
2953 | dev->set_mac_address = mv643xx_eth_set_mac_address; |
2954 | dev->do_ioctl = mv643xx_eth_ioctl; | |
2955 | dev->change_mtu = mv643xx_eth_change_mtu; | |
c9df406f | 2956 | dev->tx_timeout = mv643xx_eth_tx_timeout; |
c9df406f | 2957 | #ifdef CONFIG_NET_POLL_CONTROLLER |
e5371493 | 2958 | dev->poll_controller = mv643xx_eth_netpoll; |
c9df406f | 2959 | #endif |
c9df406f LB |
2960 | dev->watchdog_timeo = 2 * HZ; |
2961 | dev->base_addr = 0; | |
1da177e4 | 2962 | |
c9df406f | 2963 | dev->features = NETIF_F_SG | NETIF_F_IP_CSUM; |
e32b6617 | 2964 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM; |
1da177e4 | 2965 | |
fc32b0e2 | 2966 | SET_NETDEV_DEV(dev, &pdev->dev); |
8f518703 | 2967 | |
c9df406f | 2968 | if (mp->shared->win_protect) |
fc32b0e2 | 2969 | wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect); |
1da177e4 | 2970 | |
c9df406f LB |
2971 | err = register_netdev(dev); |
2972 | if (err) | |
2973 | goto out; | |
1da177e4 | 2974 | |
e174961c JB |
2975 | dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %pM\n", |
2976 | mp->port_num, dev->dev_addr); | |
1da177e4 | 2977 | |
13d64285 | 2978 | if (mp->tx_desc_sram_size > 0) |
fc32b0e2 | 2979 | dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n"); |
1da177e4 | 2980 | |
c9df406f | 2981 | return 0; |
1da177e4 | 2982 | |
c9df406f LB |
2983 | out: |
2984 | free_netdev(dev); | |
1da177e4 | 2985 | |
c9df406f | 2986 | return err; |
1da177e4 LT |
2987 | } |
2988 | ||
c9df406f | 2989 | static int mv643xx_eth_remove(struct platform_device *pdev) |
1da177e4 | 2990 | { |
fc32b0e2 | 2991 | struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); |
1da177e4 | 2992 | |
fc32b0e2 | 2993 | unregister_netdev(mp->dev); |
ed94493f LB |
2994 | if (mp->phy != NULL) |
2995 | phy_detach(mp->phy); | |
c9df406f | 2996 | flush_scheduled_work(); |
fc32b0e2 | 2997 | free_netdev(mp->dev); |
c9df406f | 2998 | |
c9df406f | 2999 | platform_set_drvdata(pdev, NULL); |
fc32b0e2 | 3000 | |
c9df406f | 3001 | return 0; |
1da177e4 LT |
3002 | } |
3003 | ||
c9df406f | 3004 | static void mv643xx_eth_shutdown(struct platform_device *pdev) |
d0412d96 | 3005 | { |
fc32b0e2 | 3006 | struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); |
d0412d96 | 3007 | |
c9df406f | 3008 | /* Mask all interrupts on ethernet port */ |
37a6084f LB |
3009 | wrlp(mp, INT_MASK, 0); |
3010 | rdlp(mp, INT_MASK); | |
c9df406f | 3011 | |
fc32b0e2 LB |
3012 | if (netif_running(mp->dev)) |
3013 | port_reset(mp); | |
d0412d96 JC |
3014 | } |
3015 | ||
c9df406f | 3016 | static struct platform_driver mv643xx_eth_driver = { |
fc32b0e2 LB |
3017 | .probe = mv643xx_eth_probe, |
3018 | .remove = mv643xx_eth_remove, | |
3019 | .shutdown = mv643xx_eth_shutdown, | |
c9df406f | 3020 | .driver = { |
fc32b0e2 | 3021 | .name = MV643XX_ETH_NAME, |
c9df406f LB |
3022 | .owner = THIS_MODULE, |
3023 | }, | |
3024 | }; | |
3025 | ||
e5371493 | 3026 | static int __init mv643xx_eth_init_module(void) |
d0412d96 | 3027 | { |
c9df406f | 3028 | int rc; |
d0412d96 | 3029 | |
c9df406f LB |
3030 | rc = platform_driver_register(&mv643xx_eth_shared_driver); |
3031 | if (!rc) { | |
3032 | rc = platform_driver_register(&mv643xx_eth_driver); | |
3033 | if (rc) | |
3034 | platform_driver_unregister(&mv643xx_eth_shared_driver); | |
3035 | } | |
fc32b0e2 | 3036 | |
c9df406f | 3037 | return rc; |
d0412d96 | 3038 | } |
fc32b0e2 | 3039 | module_init(mv643xx_eth_init_module); |
d0412d96 | 3040 | |
e5371493 | 3041 | static void __exit mv643xx_eth_cleanup_module(void) |
d0412d96 | 3042 | { |
c9df406f LB |
3043 | platform_driver_unregister(&mv643xx_eth_driver); |
3044 | platform_driver_unregister(&mv643xx_eth_shared_driver); | |
d0412d96 | 3045 | } |
e5371493 | 3046 | module_exit(mv643xx_eth_cleanup_module); |
1da177e4 | 3047 | |
45675bc6 LB |
3048 | MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, " |
3049 | "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek"); | |
c9df406f | 3050 | MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); |
fc32b0e2 | 3051 | MODULE_LICENSE("GPL"); |
c9df406f | 3052 | MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME); |
fc32b0e2 | 3053 | MODULE_ALIAS("platform:" MV643XX_ETH_NAME); |