Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports | |
3 | * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com> | |
4 | * | |
5 | * Based on the 64360 driver from: | |
6 | * Copyright (C) 2002 rabeeh@galileo.co.il | |
7 | * | |
8 | * Copyright (C) 2003 PMC-Sierra, Inc., | |
3bb8a18a | 9 | * written by Manish Lachwani |
1da177e4 LT |
10 | * |
11 | * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> | |
12 | * | |
13 | * Copyright (C) 2004-2005 MontaVista Software, Inc. | |
14 | * Dale Farnsworth <dale@farnsworth.org> | |
15 | * | |
16 | * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com> | |
17 | * <sjhill@realitydiluted.com> | |
18 | * | |
19 | * This program is free software; you can redistribute it and/or | |
20 | * modify it under the terms of the GNU General Public License | |
21 | * as published by the Free Software Foundation; either version 2 | |
22 | * of the License, or (at your option) any later version. | |
23 | * | |
24 | * This program is distributed in the hope that it will be useful, | |
25 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
26 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
27 | * GNU General Public License for more details. | |
28 | * | |
29 | * You should have received a copy of the GNU General Public License | |
30 | * along with this program; if not, write to the Free Software | |
31 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
32 | */ | |
33 | #include <linux/init.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/tcp.h> | |
36 | #include <linux/udp.h> | |
37 | #include <linux/etherdevice.h> | |
78a5e534 OH |
38 | #include <linux/in.h> |
39 | #include <linux/ip.h> | |
1da177e4 LT |
40 | |
41 | #include <linux/bitops.h> | |
42 | #include <linux/delay.h> | |
43 | #include <linux/ethtool.h> | |
d052d1be RK |
44 | #include <linux/platform_device.h> |
45 | ||
1da177e4 LT |
46 | #include <asm/io.h> |
47 | #include <asm/types.h> | |
48 | #include <asm/pgtable.h> | |
49 | #include <asm/system.h> | |
50 | #include <asm/delay.h> | |
51 | #include "mv643xx_eth.h" | |
52 | ||
53 | /* | |
54 | * The first part is the high level driver of the gigE ethernet ports. | |
55 | */ | |
56 | ||
57 | /* Constants */ | |
58 | #define VLAN_HLEN 4 | |
59 | #define FCS_LEN 4 | |
b44cd572 DF |
60 | #define DMA_ALIGN 8 /* hw requires 8-byte alignment */ |
61 | #define HW_IP_ALIGN 2 /* hw aligns IP header */ | |
62 | #define WRAP HW_IP_ALIGN + ETH_HLEN + VLAN_HLEN + FCS_LEN | |
1da177e4 LT |
63 | #define RX_SKB_SIZE ((dev->mtu + WRAP + 7) & ~0x7) |
64 | ||
c2e5b352 DF |
65 | #define INT_UNMASK_ALL 0x0007ffff |
66 | #define INT_UNMASK_ALL_EXT 0x0011ffff | |
67 | #define INT_MASK_ALL 0x00000000 | |
68 | #define INT_MASK_ALL_EXT 0x00000000 | |
1da177e4 LT |
69 | #define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL |
70 | #define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT | |
1da177e4 LT |
71 | |
72 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX | |
73 | #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1) | |
74 | #else | |
75 | #define MAX_DESCS_PER_SKB 1 | |
76 | #endif | |
77 | ||
78 | #define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */ | |
79 | #define PHY_WAIT_MICRO_SECONDS 10 | |
80 | ||
81 | /* Static function declarations */ | |
82 | static int eth_port_link_is_up(unsigned int eth_port_num); | |
83 | static void eth_port_uc_addr_get(struct net_device *dev, | |
84 | unsigned char *MacAddr); | |
16e03018 | 85 | static void eth_port_set_multicast_list(struct net_device *); |
ab4384a6 DF |
86 | static int mv643xx_eth_open(struct net_device *); |
87 | static int mv643xx_eth_stop(struct net_device *); | |
1da177e4 LT |
88 | static int mv643xx_eth_change_mtu(struct net_device *, int); |
89 | static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *); | |
90 | static void eth_port_init_mac_tables(unsigned int eth_port_num); | |
91 | #ifdef MV643XX_NAPI | |
92 | static int mv643xx_poll(struct net_device *dev, int *budget); | |
93 | #endif | |
94 | static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr); | |
95 | static int ethernet_phy_detect(unsigned int eth_port_num); | |
96 | static struct ethtool_ops mv643xx_ethtool_ops; | |
97 | ||
98 | static char mv643xx_driver_name[] = "mv643xx_eth"; | |
99 | static char mv643xx_driver_version[] = "1.0"; | |
100 | ||
101 | static void __iomem *mv643xx_eth_shared_base; | |
102 | ||
103 | /* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */ | |
a9f6a0dd | 104 | static DEFINE_SPINLOCK(mv643xx_eth_phy_lock); |
1da177e4 LT |
105 | |
106 | static inline u32 mv_read(int offset) | |
107 | { | |
dc074a8a | 108 | void __iomem *reg_base; |
1da177e4 LT |
109 | |
110 | reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS; | |
111 | ||
112 | return readl(reg_base + offset); | |
113 | } | |
114 | ||
115 | static inline void mv_write(int offset, u32 data) | |
116 | { | |
dc074a8a | 117 | void __iomem *reg_base; |
1da177e4 LT |
118 | |
119 | reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS; | |
120 | writel(data, reg_base + offset); | |
121 | } | |
122 | ||
123 | /* | |
124 | * Changes MTU (maximum transfer unit) of the gigabit ethenret port | |
125 | * | |
126 | * Input : pointer to ethernet interface network device structure | |
127 | * new mtu size | |
128 | * Output : 0 upon success, -EINVAL upon failure | |
129 | */ | |
130 | static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu) | |
131 | { | |
8f518703 | 132 | if ((new_mtu > 9500) || (new_mtu < 64)) |
1da177e4 | 133 | return -EINVAL; |
1da177e4 LT |
134 | |
135 | dev->mtu = new_mtu; | |
136 | /* | |
137 | * Stop then re-open the interface. This will allocate RX skb's with | |
138 | * the new MTU. | |
139 | * There is a possible danger that the open will not successed, due | |
140 | * to memory is full, which might fail the open function. | |
141 | */ | |
142 | if (netif_running(dev)) { | |
ab4384a6 DF |
143 | mv643xx_eth_stop(dev); |
144 | if (mv643xx_eth_open(dev)) | |
1da177e4 LT |
145 | printk(KERN_ERR |
146 | "%s: Fatal error on opening device\n", | |
147 | dev->name); | |
148 | } | |
149 | ||
1da177e4 LT |
150 | return 0; |
151 | } | |
152 | ||
153 | /* | |
154 | * mv643xx_eth_rx_task | |
155 | * | |
156 | * Fills / refills RX queue on a certain gigabit ethernet port | |
157 | * | |
158 | * Input : pointer to ethernet interface network device structure | |
159 | * Output : N/A | |
160 | */ | |
161 | static void mv643xx_eth_rx_task(void *data) | |
162 | { | |
163 | struct net_device *dev = (struct net_device *)data; | |
164 | struct mv643xx_private *mp = netdev_priv(dev); | |
165 | struct pkt_info pkt_info; | |
166 | struct sk_buff *skb; | |
b44cd572 | 167 | int unaligned; |
1da177e4 LT |
168 | |
169 | if (test_and_set_bit(0, &mp->rx_task_busy)) | |
170 | panic("%s: Error in test_set_bit / clear_bit", dev->name); | |
171 | ||
172 | while (mp->rx_ring_skbs < (mp->rx_ring_size - 5)) { | |
b44cd572 | 173 | skb = dev_alloc_skb(RX_SKB_SIZE + DMA_ALIGN); |
1da177e4 LT |
174 | if (!skb) |
175 | break; | |
176 | mp->rx_ring_skbs++; | |
b44cd572 DF |
177 | unaligned = (u32)skb->data & (DMA_ALIGN - 1); |
178 | if (unaligned) | |
179 | skb_reserve(skb, DMA_ALIGN - unaligned); | |
1da177e4 LT |
180 | pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT; |
181 | pkt_info.byte_cnt = RX_SKB_SIZE; | |
182 | pkt_info.buf_ptr = dma_map_single(NULL, skb->data, RX_SKB_SIZE, | |
183 | DMA_FROM_DEVICE); | |
184 | pkt_info.return_info = skb; | |
185 | if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) { | |
186 | printk(KERN_ERR | |
187 | "%s: Error allocating RX Ring\n", dev->name); | |
188 | break; | |
189 | } | |
b44cd572 | 190 | skb_reserve(skb, HW_IP_ALIGN); |
1da177e4 LT |
191 | } |
192 | clear_bit(0, &mp->rx_task_busy); | |
193 | /* | |
194 | * If RX ring is empty of SKB, set a timer to try allocating | |
195 | * again in a later time . | |
196 | */ | |
197 | if ((mp->rx_ring_skbs == 0) && (mp->rx_timer_flag == 0)) { | |
198 | printk(KERN_INFO "%s: Rx ring is empty\n", dev->name); | |
199 | /* After 100mSec */ | |
200 | mp->timeout.expires = jiffies + (HZ / 10); | |
201 | add_timer(&mp->timeout); | |
202 | mp->rx_timer_flag = 1; | |
203 | } | |
204 | #ifdef MV643XX_RX_QUEUE_FILL_ON_TASK | |
205 | else { | |
206 | /* Return interrupts */ | |
207 | mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(mp->port_num), | |
c2e5b352 | 208 | INT_UNMASK_ALL); |
1da177e4 LT |
209 | } |
210 | #endif | |
211 | } | |
212 | ||
213 | /* | |
214 | * mv643xx_eth_rx_task_timer_wrapper | |
215 | * | |
216 | * Timer routine to wake up RX queue filling task. This function is | |
217 | * used only in case the RX queue is empty, and all alloc_skb has | |
218 | * failed (due to out of memory event). | |
219 | * | |
220 | * Input : pointer to ethernet interface network device structure | |
221 | * Output : N/A | |
222 | */ | |
223 | static void mv643xx_eth_rx_task_timer_wrapper(unsigned long data) | |
224 | { | |
225 | struct net_device *dev = (struct net_device *)data; | |
226 | struct mv643xx_private *mp = netdev_priv(dev); | |
227 | ||
228 | mp->rx_timer_flag = 0; | |
229 | mv643xx_eth_rx_task((void *)data); | |
230 | } | |
231 | ||
232 | /* | |
233 | * mv643xx_eth_update_mac_address | |
234 | * | |
235 | * Update the MAC address of the port in the address table | |
236 | * | |
237 | * Input : pointer to ethernet interface network device structure | |
238 | * Output : N/A | |
239 | */ | |
240 | static void mv643xx_eth_update_mac_address(struct net_device *dev) | |
241 | { | |
242 | struct mv643xx_private *mp = netdev_priv(dev); | |
243 | unsigned int port_num = mp->port_num; | |
244 | ||
245 | eth_port_init_mac_tables(port_num); | |
246 | memcpy(mp->port_mac_addr, dev->dev_addr, 6); | |
247 | eth_port_uc_addr_set(port_num, mp->port_mac_addr); | |
248 | } | |
249 | ||
250 | /* | |
251 | * mv643xx_eth_set_rx_mode | |
252 | * | |
253 | * Change from promiscuos to regular rx mode | |
254 | * | |
255 | * Input : pointer to ethernet interface network device structure | |
256 | * Output : N/A | |
257 | */ | |
258 | static void mv643xx_eth_set_rx_mode(struct net_device *dev) | |
259 | { | |
260 | struct mv643xx_private *mp = netdev_priv(dev); | |
1da177e4 | 261 | |
1da177e4 | 262 | if (dev->flags & IFF_PROMISC) |
7342cd81 | 263 | mp->port_config |= (u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE; |
1da177e4 | 264 | else |
7342cd81 DF |
265 | mp->port_config &= ~(u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE; |
266 | ||
267 | mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num), mp->port_config); | |
16e03018 DF |
268 | |
269 | eth_port_set_multicast_list(dev); | |
1da177e4 LT |
270 | } |
271 | ||
272 | /* | |
273 | * mv643xx_eth_set_mac_address | |
274 | * | |
275 | * Change the interface's mac address. | |
276 | * No special hardware thing should be done because interface is always | |
277 | * put in promiscuous mode. | |
278 | * | |
279 | * Input : pointer to ethernet interface network device structure and | |
280 | * a pointer to the designated entry to be added to the cache. | |
281 | * Output : zero upon success, negative upon failure | |
282 | */ | |
283 | static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr) | |
284 | { | |
285 | int i; | |
286 | ||
287 | for (i = 0; i < 6; i++) | |
288 | /* +2 is for the offset of the HW addr type */ | |
289 | dev->dev_addr[i] = ((unsigned char *)addr)[i + 2]; | |
290 | mv643xx_eth_update_mac_address(dev); | |
291 | return 0; | |
292 | } | |
293 | ||
294 | /* | |
295 | * mv643xx_eth_tx_timeout | |
296 | * | |
297 | * Called upon a timeout on transmitting a packet | |
298 | * | |
299 | * Input : pointer to ethernet interface network device structure. | |
300 | * Output : N/A | |
301 | */ | |
302 | static void mv643xx_eth_tx_timeout(struct net_device *dev) | |
303 | { | |
304 | struct mv643xx_private *mp = netdev_priv(dev); | |
305 | ||
306 | printk(KERN_INFO "%s: TX timeout ", dev->name); | |
307 | ||
308 | /* Do the reset outside of interrupt context */ | |
309 | schedule_work(&mp->tx_timeout_task); | |
310 | } | |
311 | ||
312 | /* | |
313 | * mv643xx_eth_tx_timeout_task | |
314 | * | |
315 | * Actual routine to reset the adapter when a timeout on Tx has occurred | |
316 | */ | |
317 | static void mv643xx_eth_tx_timeout_task(struct net_device *dev) | |
318 | { | |
319 | struct mv643xx_private *mp = netdev_priv(dev); | |
320 | ||
321 | netif_device_detach(dev); | |
322 | eth_port_reset(mp->port_num); | |
323 | eth_port_start(mp); | |
324 | netif_device_attach(dev); | |
325 | } | |
326 | ||
327 | /* | |
328 | * mv643xx_eth_free_tx_queue | |
329 | * | |
330 | * Input : dev - a pointer to the required interface | |
331 | * | |
332 | * Output : 0 if was able to release skb , nonzero otherwise | |
333 | */ | |
334 | static int mv643xx_eth_free_tx_queue(struct net_device *dev, | |
335 | unsigned int eth_int_cause_ext) | |
336 | { | |
337 | struct mv643xx_private *mp = netdev_priv(dev); | |
338 | struct net_device_stats *stats = &mp->stats; | |
339 | struct pkt_info pkt_info; | |
340 | int released = 1; | |
341 | ||
342 | if (!(eth_int_cause_ext & (BIT0 | BIT8))) | |
343 | return released; | |
344 | ||
1da177e4 LT |
345 | /* Check only queue 0 */ |
346 | while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) { | |
347 | if (pkt_info.cmd_sts & BIT0) { | |
348 | printk("%s: Error in TX\n", dev->name); | |
349 | stats->tx_errors++; | |
350 | } | |
351 | ||
cb415d30 PG |
352 | if (pkt_info.cmd_sts & ETH_TX_FIRST_DESC) |
353 | dma_unmap_single(NULL, pkt_info.buf_ptr, | |
354 | pkt_info.byte_cnt, | |
355 | DMA_TO_DEVICE); | |
356 | else | |
357 | dma_unmap_page(NULL, pkt_info.buf_ptr, | |
358 | pkt_info.byte_cnt, | |
359 | DMA_TO_DEVICE); | |
1da177e4 | 360 | |
cb415d30 | 361 | if (pkt_info.return_info) { |
1da177e4 LT |
362 | dev_kfree_skb_irq(pkt_info.return_info); |
363 | released = 0; | |
cb415d30 | 364 | } |
1da177e4 LT |
365 | } |
366 | ||
1da177e4 LT |
367 | return released; |
368 | } | |
369 | ||
370 | /* | |
371 | * mv643xx_eth_receive | |
372 | * | |
373 | * This function is forward packets that are received from the port's | |
374 | * queues toward kernel core or FastRoute them to another interface. | |
375 | * | |
376 | * Input : dev - a pointer to the required interface | |
377 | * max - maximum number to receive (0 means unlimted) | |
378 | * | |
379 | * Output : number of served packets | |
380 | */ | |
381 | #ifdef MV643XX_NAPI | |
382 | static int mv643xx_eth_receive_queue(struct net_device *dev, int budget) | |
383 | #else | |
384 | static int mv643xx_eth_receive_queue(struct net_device *dev) | |
385 | #endif | |
386 | { | |
387 | struct mv643xx_private *mp = netdev_priv(dev); | |
388 | struct net_device_stats *stats = &mp->stats; | |
389 | unsigned int received_packets = 0; | |
390 | struct sk_buff *skb; | |
391 | struct pkt_info pkt_info; | |
392 | ||
393 | #ifdef MV643XX_NAPI | |
b1dd9ca1 | 394 | while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) { |
1da177e4 LT |
395 | #else |
396 | while (eth_port_receive(mp, &pkt_info) == ETH_OK) { | |
397 | #endif | |
398 | mp->rx_ring_skbs--; | |
399 | received_packets++; | |
b1dd9ca1 | 400 | |
1da177e4 LT |
401 | /* Update statistics. Note byte count includes 4 byte CRC count */ |
402 | stats->rx_packets++; | |
403 | stats->rx_bytes += pkt_info.byte_cnt; | |
404 | skb = pkt_info.return_info; | |
405 | /* | |
406 | * In case received a packet without first / last bits on OR | |
407 | * the error summary bit is on, the packets needs to be dropeed. | |
408 | */ | |
409 | if (((pkt_info.cmd_sts | |
410 | & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) != | |
411 | (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) | |
412 | || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) { | |
413 | stats->rx_dropped++; | |
414 | if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC | | |
415 | ETH_RX_LAST_DESC)) != | |
416 | (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) { | |
417 | if (net_ratelimit()) | |
418 | printk(KERN_ERR | |
419 | "%s: Received packet spread " | |
420 | "on multiple descriptors\n", | |
421 | dev->name); | |
422 | } | |
423 | if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) | |
424 | stats->rx_errors++; | |
425 | ||
426 | dev_kfree_skb_irq(skb); | |
427 | } else { | |
428 | /* | |
429 | * The -4 is for the CRC in the trailer of the | |
430 | * received packet | |
431 | */ | |
432 | skb_put(skb, pkt_info.byte_cnt - 4); | |
433 | skb->dev = dev; | |
434 | ||
435 | if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) { | |
436 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
437 | skb->csum = htons( | |
438 | (pkt_info.cmd_sts & 0x0007fff8) >> 3); | |
439 | } | |
440 | skb->protocol = eth_type_trans(skb, dev); | |
441 | #ifdef MV643XX_NAPI | |
442 | netif_receive_skb(skb); | |
443 | #else | |
444 | netif_rx(skb); | |
445 | #endif | |
446 | } | |
12ad74f8 | 447 | dev->last_rx = jiffies; |
1da177e4 LT |
448 | } |
449 | ||
450 | return received_packets; | |
451 | } | |
452 | ||
453 | /* | |
454 | * mv643xx_eth_int_handler | |
455 | * | |
456 | * Main interrupt handler for the gigbit ethernet ports | |
457 | * | |
458 | * Input : irq - irq number (not used) | |
459 | * dev_id - a pointer to the required interface's data structure | |
460 | * regs - not used | |
461 | * Output : N/A | |
462 | */ | |
463 | ||
464 | static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id, | |
465 | struct pt_regs *regs) | |
466 | { | |
467 | struct net_device *dev = (struct net_device *)dev_id; | |
468 | struct mv643xx_private *mp = netdev_priv(dev); | |
469 | u32 eth_int_cause, eth_int_cause_ext = 0; | |
470 | unsigned int port_num = mp->port_num; | |
471 | ||
472 | /* Read interrupt cause registers */ | |
473 | eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) & | |
c2e5b352 | 474 | INT_UNMASK_ALL; |
1da177e4 LT |
475 | |
476 | if (eth_int_cause & BIT1) | |
477 | eth_int_cause_ext = mv_read( | |
478 | MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) & | |
c2e5b352 | 479 | INT_UNMASK_ALL_EXT; |
1da177e4 LT |
480 | |
481 | #ifdef MV643XX_NAPI | |
482 | if (!(eth_int_cause & 0x0007fffd)) { | |
483 | /* Dont ack the Rx interrupt */ | |
484 | #endif | |
485 | /* | |
486 | * Clear specific ethernet port intrerrupt registers by | |
487 | * acknowleding relevant bits. | |
488 | */ | |
489 | mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), | |
490 | ~eth_int_cause); | |
491 | if (eth_int_cause_ext != 0x0) | |
492 | mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG | |
493 | (port_num), ~eth_int_cause_ext); | |
494 | ||
495 | /* UDP change : We may need this */ | |
496 | if ((eth_int_cause_ext & 0x0000ffff) && | |
497 | (mv643xx_eth_free_tx_queue(dev, eth_int_cause_ext) == 0) && | |
498 | (mp->tx_ring_size > mp->tx_ring_skbs + MAX_DESCS_PER_SKB)) | |
499 | netif_wake_queue(dev); | |
500 | #ifdef MV643XX_NAPI | |
501 | } else { | |
502 | if (netif_rx_schedule_prep(dev)) { | |
503 | /* Mask all the interrupts */ | |
c2e5b352 DF |
504 | mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), |
505 | INT_MASK_ALL); | |
506 | /* wait for previous write to complete */ | |
507 | mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num)); | |
1da177e4 LT |
508 | __netif_rx_schedule(dev); |
509 | } | |
510 | #else | |
511 | if (eth_int_cause & (BIT2 | BIT11)) | |
512 | mv643xx_eth_receive_queue(dev, 0); | |
513 | ||
514 | /* | |
515 | * After forwarded received packets to upper layer, add a task | |
516 | * in an interrupts enabled context that refills the RX ring | |
517 | * with skb's. | |
518 | */ | |
519 | #ifdef MV643XX_RX_QUEUE_FILL_ON_TASK | |
c2e5b352 | 520 | /* Mask all interrupts on ethernet port */ |
1da177e4 | 521 | mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), |
c2e5b352 | 522 | INT_MASK_ALL); |
8f518703 DF |
523 | /* wait for previous write to take effect */ |
524 | mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num)); | |
525 | ||
1da177e4 LT |
526 | queue_task(&mp->rx_task, &tq_immediate); |
527 | mark_bh(IMMEDIATE_BH); | |
528 | #else | |
529 | mp->rx_task.func(dev); | |
530 | #endif | |
531 | #endif | |
532 | } | |
533 | /* PHY status changed */ | |
534 | if (eth_int_cause_ext & (BIT16 | BIT20)) { | |
535 | if (eth_port_link_is_up(port_num)) { | |
536 | netif_carrier_on(dev); | |
537 | netif_wake_queue(dev); | |
538 | /* Start TX queue */ | |
539 | mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG | |
540 | (port_num), 1); | |
541 | } else { | |
542 | netif_carrier_off(dev); | |
543 | netif_stop_queue(dev); | |
544 | } | |
545 | } | |
546 | ||
547 | /* | |
548 | * If no real interrupt occured, exit. | |
549 | * This can happen when using gigE interrupt coalescing mechanism. | |
550 | */ | |
551 | if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0)) | |
552 | return IRQ_NONE; | |
553 | ||
554 | return IRQ_HANDLED; | |
555 | } | |
556 | ||
557 | #ifdef MV643XX_COAL | |
558 | ||
559 | /* | |
560 | * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path | |
561 | * | |
562 | * DESCRIPTION: | |
563 | * This routine sets the RX coalescing interrupt mechanism parameter. | |
564 | * This parameter is a timeout counter, that counts in 64 t_clk | |
565 | * chunks ; that when timeout event occurs a maskable interrupt | |
566 | * occurs. | |
567 | * The parameter is calculated using the tClk of the MV-643xx chip | |
568 | * , and the required delay of the interrupt in usec. | |
569 | * | |
570 | * INPUT: | |
571 | * unsigned int eth_port_num Ethernet port number | |
572 | * unsigned int t_clk t_clk of the MV-643xx chip in HZ units | |
573 | * unsigned int delay Delay in usec | |
574 | * | |
575 | * OUTPUT: | |
576 | * Interrupt coalescing mechanism value is set in MV-643xx chip. | |
577 | * | |
578 | * RETURN: | |
579 | * The interrupt coalescing value set in the gigE port. | |
580 | * | |
581 | */ | |
582 | static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num, | |
583 | unsigned int t_clk, unsigned int delay) | |
584 | { | |
585 | unsigned int coal = ((t_clk / 1000000) * delay) / 64; | |
586 | ||
587 | /* Set RX Coalescing mechanism */ | |
588 | mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num), | |
589 | ((coal & 0x3fff) << 8) | | |
590 | (mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num)) | |
591 | & 0xffc000ff)); | |
592 | ||
593 | return coal; | |
594 | } | |
595 | #endif | |
596 | ||
597 | /* | |
598 | * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path | |
599 | * | |
600 | * DESCRIPTION: | |
601 | * This routine sets the TX coalescing interrupt mechanism parameter. | |
602 | * This parameter is a timeout counter, that counts in 64 t_clk | |
603 | * chunks ; that when timeout event occurs a maskable interrupt | |
604 | * occurs. | |
605 | * The parameter is calculated using the t_cLK frequency of the | |
606 | * MV-643xx chip and the required delay in the interrupt in uSec | |
607 | * | |
608 | * INPUT: | |
609 | * unsigned int eth_port_num Ethernet port number | |
610 | * unsigned int t_clk t_clk of the MV-643xx chip in HZ units | |
611 | * unsigned int delay Delay in uSeconds | |
612 | * | |
613 | * OUTPUT: | |
614 | * Interrupt coalescing mechanism value is set in MV-643xx chip. | |
615 | * | |
616 | * RETURN: | |
617 | * The interrupt coalescing value set in the gigE port. | |
618 | * | |
619 | */ | |
620 | static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num, | |
621 | unsigned int t_clk, unsigned int delay) | |
622 | { | |
623 | unsigned int coal; | |
624 | coal = ((t_clk / 1000000) * delay) / 64; | |
625 | /* Set TX Coalescing mechanism */ | |
626 | mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num), | |
627 | coal << 4); | |
628 | return coal; | |
629 | } | |
630 | ||
1da177e4 LT |
631 | /* |
632 | * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. | |
633 | * | |
634 | * DESCRIPTION: | |
635 | * This function prepares a Rx chained list of descriptors and packet | |
636 | * buffers in a form of a ring. The routine must be called after port | |
637 | * initialization routine and before port start routine. | |
638 | * The Ethernet SDMA engine uses CPU bus addresses to access the various | |
639 | * devices in the system (i.e. DRAM). This function uses the ethernet | |
640 | * struct 'virtual to physical' routine (set by the user) to set the ring | |
641 | * with physical addresses. | |
642 | * | |
643 | * INPUT: | |
644 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
645 | * | |
646 | * OUTPUT: | |
647 | * The routine updates the Ethernet port control struct with information | |
648 | * regarding the Rx descriptors and buffers. | |
649 | * | |
650 | * RETURN: | |
651 | * None. | |
652 | */ | |
653 | static void ether_init_rx_desc_ring(struct mv643xx_private *mp) | |
654 | { | |
655 | volatile struct eth_rx_desc *p_rx_desc; | |
656 | int rx_desc_num = mp->rx_ring_size; | |
657 | int i; | |
658 | ||
659 | /* initialize the next_desc_ptr links in the Rx descriptors ring */ | |
660 | p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area; | |
661 | for (i = 0; i < rx_desc_num; i++) { | |
662 | p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma + | |
663 | ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc); | |
664 | } | |
665 | ||
666 | /* Save Rx desc pointer to driver struct. */ | |
667 | mp->rx_curr_desc_q = 0; | |
668 | mp->rx_used_desc_q = 0; | |
669 | ||
670 | mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc); | |
671 | ||
672 | /* Add the queue to the list of RX queues of this port */ | |
673 | mp->port_rx_queue_command |= 1; | |
674 | } | |
675 | ||
676 | /* | |
677 | * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory. | |
678 | * | |
679 | * DESCRIPTION: | |
680 | * This function prepares a Tx chained list of descriptors and packet | |
681 | * buffers in a form of a ring. The routine must be called after port | |
682 | * initialization routine and before port start routine. | |
683 | * The Ethernet SDMA engine uses CPU bus addresses to access the various | |
684 | * devices in the system (i.e. DRAM). This function uses the ethernet | |
685 | * struct 'virtual to physical' routine (set by the user) to set the ring | |
686 | * with physical addresses. | |
687 | * | |
688 | * INPUT: | |
689 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
690 | * | |
691 | * OUTPUT: | |
692 | * The routine updates the Ethernet port control struct with information | |
693 | * regarding the Tx descriptors and buffers. | |
694 | * | |
695 | * RETURN: | |
696 | * None. | |
697 | */ | |
698 | static void ether_init_tx_desc_ring(struct mv643xx_private *mp) | |
699 | { | |
700 | int tx_desc_num = mp->tx_ring_size; | |
701 | struct eth_tx_desc *p_tx_desc; | |
702 | int i; | |
703 | ||
704 | /* Initialize the next_desc_ptr links in the Tx descriptors ring */ | |
705 | p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area; | |
706 | for (i = 0; i < tx_desc_num; i++) { | |
707 | p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma + | |
708 | ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc); | |
709 | } | |
710 | ||
711 | mp->tx_curr_desc_q = 0; | |
712 | mp->tx_used_desc_q = 0; | |
713 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX | |
714 | mp->tx_first_desc_q = 0; | |
715 | #endif | |
716 | ||
717 | mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc); | |
718 | ||
719 | /* Add the queue to the list of Tx queues of this port */ | |
720 | mp->port_tx_queue_command |= 1; | |
721 | } | |
722 | ||
ab4384a6 DF |
723 | /* |
724 | * mv643xx_eth_open | |
725 | * | |
726 | * This function is called when openning the network device. The function | |
727 | * should initialize all the hardware, initialize cyclic Rx/Tx | |
728 | * descriptors chain and buffers and allocate an IRQ to the network | |
729 | * device. | |
730 | * | |
731 | * Input : a pointer to the network device structure | |
732 | * | |
733 | * Output : zero of success , nonzero if fails. | |
734 | */ | |
735 | ||
736 | static int mv643xx_eth_open(struct net_device *dev) | |
1da177e4 LT |
737 | { |
738 | struct mv643xx_private *mp = netdev_priv(dev); | |
739 | unsigned int port_num = mp->port_num; | |
740 | unsigned int size; | |
ab4384a6 DF |
741 | int err; |
742 | ||
743 | err = request_irq(dev->irq, mv643xx_eth_int_handler, | |
744 | SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev); | |
745 | if (err) { | |
746 | printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n", | |
747 | port_num); | |
748 | return -EAGAIN; | |
749 | } | |
1da177e4 LT |
750 | |
751 | /* Stop RX Queues */ | |
752 | mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), 0x0000ff00); | |
753 | ||
1da177e4 LT |
754 | /* Set the MAC Address */ |
755 | memcpy(mp->port_mac_addr, dev->dev_addr, 6); | |
756 | ||
757 | eth_port_init(mp); | |
758 | ||
759 | INIT_WORK(&mp->rx_task, (void (*)(void *))mv643xx_eth_rx_task, dev); | |
760 | ||
761 | memset(&mp->timeout, 0, sizeof(struct timer_list)); | |
762 | mp->timeout.function = mv643xx_eth_rx_task_timer_wrapper; | |
763 | mp->timeout.data = (unsigned long)dev; | |
764 | ||
765 | mp->rx_task_busy = 0; | |
766 | mp->rx_timer_flag = 0; | |
767 | ||
768 | /* Allocate RX and TX skb rings */ | |
769 | mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size, | |
770 | GFP_KERNEL); | |
771 | if (!mp->rx_skb) { | |
772 | printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name); | |
ab4384a6 DF |
773 | err = -ENOMEM; |
774 | goto out_free_irq; | |
1da177e4 LT |
775 | } |
776 | mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size, | |
777 | GFP_KERNEL); | |
778 | if (!mp->tx_skb) { | |
779 | printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name); | |
ab4384a6 DF |
780 | err = -ENOMEM; |
781 | goto out_free_rx_skb; | |
1da177e4 LT |
782 | } |
783 | ||
784 | /* Allocate TX ring */ | |
785 | mp->tx_ring_skbs = 0; | |
786 | size = mp->tx_ring_size * sizeof(struct eth_tx_desc); | |
787 | mp->tx_desc_area_size = size; | |
788 | ||
789 | if (mp->tx_sram_size) { | |
790 | mp->p_tx_desc_area = ioremap(mp->tx_sram_addr, | |
791 | mp->tx_sram_size); | |
792 | mp->tx_desc_dma = mp->tx_sram_addr; | |
793 | } else | |
794 | mp->p_tx_desc_area = dma_alloc_coherent(NULL, size, | |
795 | &mp->tx_desc_dma, | |
796 | GFP_KERNEL); | |
797 | ||
798 | if (!mp->p_tx_desc_area) { | |
799 | printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n", | |
800 | dev->name, size); | |
ab4384a6 DF |
801 | err = -ENOMEM; |
802 | goto out_free_tx_skb; | |
1da177e4 LT |
803 | } |
804 | BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */ | |
805 | memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size); | |
806 | ||
807 | ether_init_tx_desc_ring(mp); | |
808 | ||
809 | /* Allocate RX ring */ | |
810 | mp->rx_ring_skbs = 0; | |
811 | size = mp->rx_ring_size * sizeof(struct eth_rx_desc); | |
812 | mp->rx_desc_area_size = size; | |
813 | ||
814 | if (mp->rx_sram_size) { | |
815 | mp->p_rx_desc_area = ioremap(mp->rx_sram_addr, | |
816 | mp->rx_sram_size); | |
817 | mp->rx_desc_dma = mp->rx_sram_addr; | |
818 | } else | |
819 | mp->p_rx_desc_area = dma_alloc_coherent(NULL, size, | |
820 | &mp->rx_desc_dma, | |
821 | GFP_KERNEL); | |
822 | ||
823 | if (!mp->p_rx_desc_area) { | |
824 | printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n", | |
825 | dev->name, size); | |
826 | printk(KERN_ERR "%s: Freeing previously allocated TX queues...", | |
827 | dev->name); | |
828 | if (mp->rx_sram_size) | |
dd09b1de | 829 | iounmap(mp->p_tx_desc_area); |
1da177e4 LT |
830 | else |
831 | dma_free_coherent(NULL, mp->tx_desc_area_size, | |
832 | mp->p_tx_desc_area, mp->tx_desc_dma); | |
ab4384a6 DF |
833 | err = -ENOMEM; |
834 | goto out_free_tx_skb; | |
1da177e4 LT |
835 | } |
836 | memset((void *)mp->p_rx_desc_area, 0, size); | |
837 | ||
838 | ether_init_rx_desc_ring(mp); | |
839 | ||
840 | mv643xx_eth_rx_task(dev); /* Fill RX ring with skb's */ | |
841 | ||
842 | eth_port_start(mp); | |
843 | ||
844 | /* Interrupt Coalescing */ | |
845 | ||
846 | #ifdef MV643XX_COAL | |
847 | mp->rx_int_coal = | |
848 | eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL); | |
849 | #endif | |
850 | ||
851 | mp->tx_int_coal = | |
852 | eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL); | |
853 | ||
8f518703 DF |
854 | /* Clear any pending ethernet port interrupts */ |
855 | mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0); | |
856 | mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0); | |
857 | ||
858 | /* Unmask phy and link status changes interrupts */ | |
859 | mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num), | |
c2e5b352 | 860 | INT_UNMASK_ALL_EXT); |
1da177e4 | 861 | |
8f518703 | 862 | /* Unmask RX buffer and TX end interrupt */ |
c2e5b352 | 863 | mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_UNMASK_ALL); |
1da177e4 | 864 | return 0; |
ab4384a6 DF |
865 | |
866 | out_free_tx_skb: | |
867 | kfree(mp->tx_skb); | |
868 | out_free_rx_skb: | |
869 | kfree(mp->rx_skb); | |
870 | out_free_irq: | |
871 | free_irq(dev->irq, dev); | |
872 | ||
873 | return err; | |
1da177e4 LT |
874 | } |
875 | ||
876 | static void mv643xx_eth_free_tx_rings(struct net_device *dev) | |
877 | { | |
878 | struct mv643xx_private *mp = netdev_priv(dev); | |
879 | unsigned int port_num = mp->port_num; | |
880 | unsigned int curr; | |
4476e0e4 | 881 | struct sk_buff *skb; |
1da177e4 LT |
882 | |
883 | /* Stop Tx Queues */ | |
884 | mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), 0x0000ff00); | |
885 | ||
886 | /* Free outstanding skb's on TX rings */ | |
887 | for (curr = 0; mp->tx_ring_skbs && curr < mp->tx_ring_size; curr++) { | |
4476e0e4 DF |
888 | skb = mp->tx_skb[curr]; |
889 | if (skb) { | |
890 | mp->tx_ring_skbs -= skb_shinfo(skb)->nr_frags; | |
891 | dev_kfree_skb(skb); | |
1da177e4 LT |
892 | mp->tx_ring_skbs--; |
893 | } | |
894 | } | |
895 | if (mp->tx_ring_skbs) | |
896 | printk("%s: Error on Tx descriptor free - could not free %d" | |
897 | " descriptors\n", dev->name, mp->tx_ring_skbs); | |
898 | ||
899 | /* Free TX ring */ | |
900 | if (mp->tx_sram_size) | |
901 | iounmap(mp->p_tx_desc_area); | |
902 | else | |
903 | dma_free_coherent(NULL, mp->tx_desc_area_size, | |
904 | mp->p_tx_desc_area, mp->tx_desc_dma); | |
905 | } | |
906 | ||
907 | static void mv643xx_eth_free_rx_rings(struct net_device *dev) | |
908 | { | |
909 | struct mv643xx_private *mp = netdev_priv(dev); | |
910 | unsigned int port_num = mp->port_num; | |
911 | int curr; | |
912 | ||
913 | /* Stop RX Queues */ | |
914 | mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), 0x0000ff00); | |
915 | ||
916 | /* Free preallocated skb's on RX rings */ | |
917 | for (curr = 0; mp->rx_ring_skbs && curr < mp->rx_ring_size; curr++) { | |
918 | if (mp->rx_skb[curr]) { | |
919 | dev_kfree_skb(mp->rx_skb[curr]); | |
920 | mp->rx_ring_skbs--; | |
921 | } | |
922 | } | |
923 | ||
924 | if (mp->rx_ring_skbs) | |
925 | printk(KERN_ERR | |
926 | "%s: Error in freeing Rx Ring. %d skb's still" | |
927 | " stuck in RX Ring - ignoring them\n", dev->name, | |
928 | mp->rx_ring_skbs); | |
929 | /* Free RX ring */ | |
930 | if (mp->rx_sram_size) | |
931 | iounmap(mp->p_rx_desc_area); | |
932 | else | |
933 | dma_free_coherent(NULL, mp->rx_desc_area_size, | |
934 | mp->p_rx_desc_area, mp->rx_desc_dma); | |
935 | } | |
936 | ||
937 | /* | |
938 | * mv643xx_eth_stop | |
939 | * | |
940 | * This function is used when closing the network device. | |
941 | * It updates the hardware, | |
942 | * release all memory that holds buffers and descriptors and release the IRQ. | |
943 | * Input : a pointer to the device structure | |
944 | * Output : zero if success , nonzero if fails | |
945 | */ | |
946 | ||
ab4384a6 | 947 | static int mv643xx_eth_stop(struct net_device *dev) |
1da177e4 LT |
948 | { |
949 | struct mv643xx_private *mp = netdev_priv(dev); | |
950 | unsigned int port_num = mp->port_num; | |
951 | ||
c2e5b352 DF |
952 | /* Mask all interrupts on ethernet port */ |
953 | mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_MASK_ALL); | |
954 | /* wait for previous write to complete */ | |
8f518703 DF |
955 | mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num)); |
956 | ||
957 | #ifdef MV643XX_NAPI | |
958 | netif_poll_disable(dev); | |
959 | #endif | |
1da177e4 LT |
960 | netif_carrier_off(dev); |
961 | netif_stop_queue(dev); | |
962 | ||
1da177e4 LT |
963 | eth_port_reset(mp->port_num); |
964 | ||
8f518703 DF |
965 | mv643xx_eth_free_tx_rings(dev); |
966 | mv643xx_eth_free_rx_rings(dev); | |
1da177e4 | 967 | |
8f518703 DF |
968 | #ifdef MV643XX_NAPI |
969 | netif_poll_enable(dev); | |
970 | #endif | |
1da177e4 | 971 | |
1da177e4 | 972 | free_irq(dev->irq, dev); |
1da177e4 LT |
973 | |
974 | return 0; | |
975 | } | |
976 | ||
977 | #ifdef MV643XX_NAPI | |
978 | static void mv643xx_tx(struct net_device *dev) | |
979 | { | |
980 | struct mv643xx_private *mp = netdev_priv(dev); | |
981 | struct pkt_info pkt_info; | |
982 | ||
983 | while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) { | |
cb415d30 PG |
984 | if (pkt_info.cmd_sts & ETH_TX_FIRST_DESC) |
985 | dma_unmap_single(NULL, pkt_info.buf_ptr, | |
986 | pkt_info.byte_cnt, | |
987 | DMA_TO_DEVICE); | |
988 | else | |
989 | dma_unmap_page(NULL, pkt_info.buf_ptr, | |
990 | pkt_info.byte_cnt, | |
991 | DMA_TO_DEVICE); | |
1da177e4 | 992 | |
cb415d30 | 993 | if (pkt_info.return_info) |
1da177e4 | 994 | dev_kfree_skb_irq(pkt_info.return_info); |
1da177e4 LT |
995 | } |
996 | ||
997 | if (netif_queue_stopped(dev) && | |
998 | mp->tx_ring_size > mp->tx_ring_skbs + MAX_DESCS_PER_SKB) | |
999 | netif_wake_queue(dev); | |
1000 | } | |
1001 | ||
1002 | /* | |
1003 | * mv643xx_poll | |
1004 | * | |
1005 | * This function is used in case of NAPI | |
1006 | */ | |
1007 | static int mv643xx_poll(struct net_device *dev, int *budget) | |
1008 | { | |
1009 | struct mv643xx_private *mp = netdev_priv(dev); | |
1010 | int done = 1, orig_budget, work_done; | |
1011 | unsigned int port_num = mp->port_num; | |
1da177e4 LT |
1012 | |
1013 | #ifdef MV643XX_TX_FAST_REFILL | |
1014 | if (++mp->tx_clean_threshold > 5) { | |
1da177e4 LT |
1015 | mv643xx_tx(dev); |
1016 | mp->tx_clean_threshold = 0; | |
1da177e4 LT |
1017 | } |
1018 | #endif | |
1019 | ||
1020 | if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num))) | |
1021 | != (u32) mp->rx_used_desc_q) { | |
1022 | orig_budget = *budget; | |
1023 | if (orig_budget > dev->quota) | |
1024 | orig_budget = dev->quota; | |
1025 | work_done = mv643xx_eth_receive_queue(dev, orig_budget); | |
1026 | mp->rx_task.func(dev); | |
1027 | *budget -= work_done; | |
1028 | dev->quota -= work_done; | |
1029 | if (work_done >= orig_budget) | |
1030 | done = 0; | |
1031 | } | |
1032 | ||
1033 | if (done) { | |
8f518703 | 1034 | netif_rx_complete(dev); |
1da177e4 LT |
1035 | mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0); |
1036 | mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0); | |
1037 | mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), | |
c2e5b352 | 1038 | INT_UNMASK_ALL); |
1da177e4 LT |
1039 | } |
1040 | ||
1041 | return done ? 0 : 1; | |
1042 | } | |
1043 | #endif | |
1044 | ||
f7ea3337 PJ |
1045 | /* Hardware can't handle unaligned fragments smaller than 9 bytes. |
1046 | * This helper function detects that case. | |
1047 | */ | |
1048 | ||
1049 | static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) | |
1050 | { | |
1051 | unsigned int frag; | |
1052 | skb_frag_t *fragp; | |
1053 | ||
1054 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { | |
1055 | fragp = &skb_shinfo(skb)->frags[frag]; | |
1056 | if (fragp->size <= 8 && fragp->page_offset & 0x7) | |
1057 | return 1; | |
1058 | ||
1059 | } | |
1060 | return 0; | |
1061 | } | |
1062 | ||
1063 | ||
1da177e4 LT |
1064 | /* |
1065 | * mv643xx_eth_start_xmit | |
1066 | * | |
1067 | * This function is queues a packet in the Tx descriptor for | |
1068 | * required port. | |
1069 | * | |
1070 | * Input : skb - a pointer to socket buffer | |
1071 | * dev - a pointer to the required port | |
1072 | * | |
1073 | * Output : zero upon success | |
1074 | */ | |
1075 | static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
1076 | { | |
1077 | struct mv643xx_private *mp = netdev_priv(dev); | |
1078 | struct net_device_stats *stats = &mp->stats; | |
1079 | ETH_FUNC_RET_STATUS status; | |
1080 | unsigned long flags; | |
1081 | struct pkt_info pkt_info; | |
1082 | ||
1083 | if (netif_queue_stopped(dev)) { | |
1084 | printk(KERN_ERR | |
1085 | "%s: Tried sending packet when interface is stopped\n", | |
1086 | dev->name); | |
1087 | return 1; | |
1088 | } | |
1089 | ||
1090 | /* This is a hard error, log it. */ | |
1091 | if ((mp->tx_ring_size - mp->tx_ring_skbs) <= | |
1092 | (skb_shinfo(skb)->nr_frags + 1)) { | |
1093 | netif_stop_queue(dev); | |
1094 | printk(KERN_ERR | |
1095 | "%s: Bug in mv643xx_eth - Trying to transmit when" | |
1096 | " queue full !\n", dev->name); | |
1097 | return 1; | |
1098 | } | |
1099 | ||
1100 | /* Paranoid check - this shouldn't happen */ | |
1101 | if (skb == NULL) { | |
1102 | stats->tx_dropped++; | |
1103 | printk(KERN_ERR "mv64320_eth paranoid check failed\n"); | |
1104 | return 1; | |
1105 | } | |
1106 | ||
f7ea3337 PJ |
1107 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX |
1108 | if (has_tiny_unaligned_frags(skb)) { | |
1109 | if ((skb_linearize(skb, GFP_ATOMIC) != 0)) { | |
1110 | stats->tx_dropped++; | |
1111 | printk(KERN_DEBUG "%s: failed to linearize tiny " | |
1112 | "unaligned fragment\n", dev->name); | |
1113 | return 1; | |
1114 | } | |
1115 | } | |
1116 | ||
1da177e4 LT |
1117 | spin_lock_irqsave(&mp->lock, flags); |
1118 | ||
1da177e4 | 1119 | if (!skb_shinfo(skb)->nr_frags) { |
1da177e4 | 1120 | if (skb->ip_summed != CHECKSUM_HW) { |
26006360 | 1121 | /* Errata BTS #50, IHL must be 5 if no HW checksum */ |
1da177e4 | 1122 | pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT | |
26006360 DF |
1123 | ETH_TX_FIRST_DESC | |
1124 | ETH_TX_LAST_DESC | | |
1125 | 5 << ETH_TX_IHL_SHIFT; | |
1da177e4 LT |
1126 | pkt_info.l4i_chk = 0; |
1127 | } else { | |
1da177e4 | 1128 | pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT | |
26006360 DF |
1129 | ETH_TX_FIRST_DESC | |
1130 | ETH_TX_LAST_DESC | | |
1131 | ETH_GEN_TCP_UDP_CHECKSUM | | |
1132 | ETH_GEN_IP_V_4_CHECKSUM | | |
1133 | skb->nh.iph->ihl << ETH_TX_IHL_SHIFT; | |
1da177e4 | 1134 | /* CPU already calculated pseudo header checksum. */ |
63890576 WJ |
1135 | if ((skb->protocol == ETH_P_IP) && |
1136 | (skb->nh.iph->protocol == IPPROTO_UDP) ) { | |
1da177e4 LT |
1137 | pkt_info.cmd_sts |= ETH_UDP_FRAME; |
1138 | pkt_info.l4i_chk = skb->h.uh->check; | |
63890576 WJ |
1139 | } else if ((skb->protocol == ETH_P_IP) && |
1140 | (skb->nh.iph->protocol == IPPROTO_TCP)) | |
1da177e4 LT |
1141 | pkt_info.l4i_chk = skb->h.th->check; |
1142 | else { | |
1143 | printk(KERN_ERR | |
63890576 | 1144 | "%s: chksum proto != IPv4 TCP or UDP\n", |
1da177e4 LT |
1145 | dev->name); |
1146 | spin_unlock_irqrestore(&mp->lock, flags); | |
1147 | return 1; | |
1148 | } | |
1149 | } | |
1150 | pkt_info.byte_cnt = skb->len; | |
1151 | pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len, | |
1152 | DMA_TO_DEVICE); | |
1153 | pkt_info.return_info = skb; | |
1da177e4 LT |
1154 | status = eth_port_send(mp, &pkt_info); |
1155 | if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) | |
1156 | printk(KERN_ERR "%s: Error on transmitting packet\n", | |
1157 | dev->name); | |
1158 | stats->tx_bytes += pkt_info.byte_cnt; | |
1159 | } else { | |
1160 | unsigned int frag; | |
1da177e4 | 1161 | |
1da177e4 LT |
1162 | /* first frag which is skb header */ |
1163 | pkt_info.byte_cnt = skb_headlen(skb); | |
1164 | pkt_info.buf_ptr = dma_map_single(NULL, skb->data, | |
1165 | skb_headlen(skb), | |
1166 | DMA_TO_DEVICE); | |
1167 | pkt_info.l4i_chk = 0; | |
1168 | pkt_info.return_info = 0; | |
1da177e4 | 1169 | |
26006360 DF |
1170 | if (skb->ip_summed != CHECKSUM_HW) |
1171 | /* Errata BTS #50, IHL must be 5 if no HW checksum */ | |
1172 | pkt_info.cmd_sts = ETH_TX_FIRST_DESC | | |
1173 | 5 << ETH_TX_IHL_SHIFT; | |
1174 | else { | |
1175 | pkt_info.cmd_sts = ETH_TX_FIRST_DESC | | |
1176 | ETH_GEN_TCP_UDP_CHECKSUM | | |
1177 | ETH_GEN_IP_V_4_CHECKSUM | | |
1178 | skb->nh.iph->ihl << ETH_TX_IHL_SHIFT; | |
1da177e4 | 1179 | /* CPU already calculated pseudo header checksum. */ |
63890576 WJ |
1180 | if ((skb->protocol == ETH_P_IP) && |
1181 | (skb->nh.iph->protocol == IPPROTO_UDP)) { | |
1da177e4 LT |
1182 | pkt_info.cmd_sts |= ETH_UDP_FRAME; |
1183 | pkt_info.l4i_chk = skb->h.uh->check; | |
63890576 WJ |
1184 | } else if ((skb->protocol == ETH_P_IP) && |
1185 | (skb->nh.iph->protocol == IPPROTO_TCP)) | |
1da177e4 LT |
1186 | pkt_info.l4i_chk = skb->h.th->check; |
1187 | else { | |
1188 | printk(KERN_ERR | |
63890576 | 1189 | "%s: chksum proto != IPv4 TCP or UDP\n", |
1da177e4 LT |
1190 | dev->name); |
1191 | spin_unlock_irqrestore(&mp->lock, flags); | |
1192 | return 1; | |
1193 | } | |
1194 | } | |
1195 | ||
1196 | status = eth_port_send(mp, &pkt_info); | |
1197 | if (status != ETH_OK) { | |
1198 | if ((status == ETH_ERROR)) | |
1199 | printk(KERN_ERR | |
1200 | "%s: Error on transmitting packet\n", | |
1201 | dev->name); | |
1202 | if (status == ETH_QUEUE_FULL) | |
1203 | printk("Error on Queue Full \n"); | |
1204 | if (status == ETH_QUEUE_LAST_RESOURCE) | |
1205 | printk("Tx resource error \n"); | |
1206 | } | |
1207 | stats->tx_bytes += pkt_info.byte_cnt; | |
1208 | ||
1209 | /* Check for the remaining frags */ | |
1210 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { | |
1211 | skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag]; | |
1212 | pkt_info.l4i_chk = 0x0000; | |
1213 | pkt_info.cmd_sts = 0x00000000; | |
1214 | ||
1215 | /* Last Frag enables interrupt and frees the skb */ | |
1216 | if (frag == (skb_shinfo(skb)->nr_frags - 1)) { | |
1217 | pkt_info.cmd_sts |= ETH_TX_ENABLE_INTERRUPT | | |
1218 | ETH_TX_LAST_DESC; | |
1219 | pkt_info.return_info = skb; | |
1da177e4 LT |
1220 | } else { |
1221 | pkt_info.return_info = 0; | |
1222 | } | |
1223 | pkt_info.l4i_chk = 0; | |
1224 | pkt_info.byte_cnt = this_frag->size; | |
1225 | ||
1226 | pkt_info.buf_ptr = dma_map_page(NULL, this_frag->page, | |
1227 | this_frag->page_offset, | |
1228 | this_frag->size, | |
1229 | DMA_TO_DEVICE); | |
1230 | ||
1231 | status = eth_port_send(mp, &pkt_info); | |
1232 | ||
1233 | if (status != ETH_OK) { | |
1234 | if ((status == ETH_ERROR)) | |
1235 | printk(KERN_ERR "%s: Error on " | |
1236 | "transmitting packet\n", | |
1237 | dev->name); | |
1238 | ||
1239 | if (status == ETH_QUEUE_LAST_RESOURCE) | |
1240 | printk("Tx resource error \n"); | |
1241 | ||
1242 | if (status == ETH_QUEUE_FULL) | |
1243 | printk("Queue is full \n"); | |
1244 | } | |
1245 | stats->tx_bytes += pkt_info.byte_cnt; | |
1246 | } | |
1247 | } | |
1248 | #else | |
f7ea3337 PJ |
1249 | spin_lock_irqsave(&mp->lock, flags); |
1250 | ||
1da177e4 LT |
1251 | pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT | ETH_TX_FIRST_DESC | |
1252 | ETH_TX_LAST_DESC; | |
1253 | pkt_info.l4i_chk = 0; | |
1254 | pkt_info.byte_cnt = skb->len; | |
1255 | pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len, | |
1256 | DMA_TO_DEVICE); | |
1257 | pkt_info.return_info = skb; | |
1da177e4 LT |
1258 | status = eth_port_send(mp, &pkt_info); |
1259 | if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) | |
1260 | printk(KERN_ERR "%s: Error on transmitting packet\n", | |
1261 | dev->name); | |
1262 | stats->tx_bytes += pkt_info.byte_cnt; | |
1263 | #endif | |
1264 | ||
1265 | /* Check if TX queue can handle another skb. If not, then | |
1266 | * signal higher layers to stop requesting TX | |
1267 | */ | |
1268 | if (mp->tx_ring_size <= (mp->tx_ring_skbs + MAX_DESCS_PER_SKB)) | |
1269 | /* | |
1270 | * Stop getting skb's from upper layers. | |
1271 | * Getting skb's from upper layers will be enabled again after | |
1272 | * packets are released. | |
1273 | */ | |
1274 | netif_stop_queue(dev); | |
1275 | ||
1276 | /* Update statistics and start of transmittion time */ | |
1277 | stats->tx_packets++; | |
1278 | dev->trans_start = jiffies; | |
1279 | ||
1280 | spin_unlock_irqrestore(&mp->lock, flags); | |
1281 | ||
1282 | return 0; /* success */ | |
1283 | } | |
1284 | ||
1285 | /* | |
1286 | * mv643xx_eth_get_stats | |
1287 | * | |
1288 | * Returns a pointer to the interface statistics. | |
1289 | * | |
1290 | * Input : dev - a pointer to the required interface | |
1291 | * | |
1292 | * Output : a pointer to the interface's statistics | |
1293 | */ | |
1294 | ||
1295 | static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev) | |
1296 | { | |
1297 | struct mv643xx_private *mp = netdev_priv(dev); | |
1298 | ||
1299 | return &mp->stats; | |
1300 | } | |
1301 | ||
63c9e549 | 1302 | #ifdef CONFIG_NET_POLL_CONTROLLER |
63c9e549 DF |
1303 | static void mv643xx_netpoll(struct net_device *netdev) |
1304 | { | |
1305 | struct mv643xx_private *mp = netdev_priv(netdev); | |
c2e5b352 DF |
1306 | int port_num = mp->port_num; |
1307 | ||
1308 | mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_MASK_ALL); | |
1309 | /* wait for previous write to complete */ | |
1310 | mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num)); | |
63c9e549 | 1311 | |
63c9e549 | 1312 | mv643xx_eth_int_handler(netdev->irq, netdev, NULL); |
c2e5b352 DF |
1313 | |
1314 | mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_UNMASK_ALL); | |
63c9e549 DF |
1315 | } |
1316 | #endif | |
1317 | ||
1da177e4 LT |
1318 | /*/ |
1319 | * mv643xx_eth_probe | |
1320 | * | |
1321 | * First function called after registering the network device. | |
1322 | * It's purpose is to initialize the device as an ethernet device, | |
1323 | * fill the ethernet device structure with pointers * to functions, | |
1324 | * and set the MAC address of the interface | |
1325 | * | |
1326 | * Input : struct device * | |
1327 | * Output : -ENOMEM if failed , 0 if success | |
1328 | */ | |
3ae5eaec | 1329 | static int mv643xx_eth_probe(struct platform_device *pdev) |
1da177e4 | 1330 | { |
1da177e4 LT |
1331 | struct mv643xx_eth_platform_data *pd; |
1332 | int port_num = pdev->id; | |
1333 | struct mv643xx_private *mp; | |
1334 | struct net_device *dev; | |
1335 | u8 *p; | |
1336 | struct resource *res; | |
1337 | int err; | |
1338 | ||
1339 | dev = alloc_etherdev(sizeof(struct mv643xx_private)); | |
1340 | if (!dev) | |
1341 | return -ENOMEM; | |
1342 | ||
3ae5eaec | 1343 | platform_set_drvdata(pdev, dev); |
1da177e4 LT |
1344 | |
1345 | mp = netdev_priv(dev); | |
1346 | ||
1347 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1348 | BUG_ON(!res); | |
1349 | dev->irq = res->start; | |
1350 | ||
1351 | mp->port_num = port_num; | |
1352 | ||
1353 | dev->open = mv643xx_eth_open; | |
1354 | dev->stop = mv643xx_eth_stop; | |
1355 | dev->hard_start_xmit = mv643xx_eth_start_xmit; | |
1356 | dev->get_stats = mv643xx_eth_get_stats; | |
1357 | dev->set_mac_address = mv643xx_eth_set_mac_address; | |
1358 | dev->set_multicast_list = mv643xx_eth_set_rx_mode; | |
1359 | ||
1360 | /* No need to Tx Timeout */ | |
1361 | dev->tx_timeout = mv643xx_eth_tx_timeout; | |
1362 | #ifdef MV643XX_NAPI | |
1363 | dev->poll = mv643xx_poll; | |
1364 | dev->weight = 64; | |
1365 | #endif | |
1366 | ||
63c9e549 DF |
1367 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1368 | dev->poll_controller = mv643xx_netpoll; | |
1369 | #endif | |
1370 | ||
1da177e4 LT |
1371 | dev->watchdog_timeo = 2 * HZ; |
1372 | dev->tx_queue_len = mp->tx_ring_size; | |
1373 | dev->base_addr = 0; | |
1374 | dev->change_mtu = mv643xx_eth_change_mtu; | |
1375 | SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops); | |
1376 | ||
1377 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX | |
1378 | #ifdef MAX_SKB_FRAGS | |
1379 | /* | |
1380 | * Zero copy can only work if we use Discovery II memory. Else, we will | |
1381 | * have to map the buffers to ISA memory which is only 16 MB | |
1382 | */ | |
63890576 | 1383 | dev->features = NETIF_F_SG | NETIF_F_IP_CSUM; |
1da177e4 LT |
1384 | #endif |
1385 | #endif | |
1386 | ||
1387 | /* Configure the timeout task */ | |
1388 | INIT_WORK(&mp->tx_timeout_task, | |
1389 | (void (*)(void *))mv643xx_eth_tx_timeout_task, dev); | |
1390 | ||
1391 | spin_lock_init(&mp->lock); | |
1392 | ||
1393 | /* set default config values */ | |
1394 | eth_port_uc_addr_get(dev, dev->dev_addr); | |
1395 | mp->port_config = MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE; | |
1396 | mp->port_config_extend = MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE; | |
1397 | mp->port_sdma_config = MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE; | |
1398 | mp->port_serial_control = MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE; | |
1399 | mp->rx_ring_size = MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE; | |
1400 | mp->tx_ring_size = MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE; | |
1401 | ||
1402 | pd = pdev->dev.platform_data; | |
1403 | if (pd) { | |
1404 | if (pd->mac_addr != NULL) | |
1405 | memcpy(dev->dev_addr, pd->mac_addr, 6); | |
1406 | ||
1407 | if (pd->phy_addr || pd->force_phy_addr) | |
1408 | ethernet_phy_set(port_num, pd->phy_addr); | |
1409 | ||
1410 | if (pd->port_config || pd->force_port_config) | |
1411 | mp->port_config = pd->port_config; | |
1412 | ||
1413 | if (pd->port_config_extend || pd->force_port_config_extend) | |
1414 | mp->port_config_extend = pd->port_config_extend; | |
1415 | ||
1416 | if (pd->port_sdma_config || pd->force_port_sdma_config) | |
1417 | mp->port_sdma_config = pd->port_sdma_config; | |
1418 | ||
1419 | if (pd->port_serial_control || pd->force_port_serial_control) | |
1420 | mp->port_serial_control = pd->port_serial_control; | |
1421 | ||
1422 | if (pd->rx_queue_size) | |
1423 | mp->rx_ring_size = pd->rx_queue_size; | |
1424 | ||
1425 | if (pd->tx_queue_size) | |
1426 | mp->tx_ring_size = pd->tx_queue_size; | |
1427 | ||
1428 | if (pd->tx_sram_size) { | |
1429 | mp->tx_sram_size = pd->tx_sram_size; | |
1430 | mp->tx_sram_addr = pd->tx_sram_addr; | |
1431 | } | |
1432 | ||
1433 | if (pd->rx_sram_size) { | |
1434 | mp->rx_sram_size = pd->rx_sram_size; | |
1435 | mp->rx_sram_addr = pd->rx_sram_addr; | |
1436 | } | |
1437 | } | |
1438 | ||
1439 | err = ethernet_phy_detect(port_num); | |
1440 | if (err) { | |
1441 | pr_debug("MV643xx ethernet port %d: " | |
1442 | "No PHY detected at addr %d\n", | |
1443 | port_num, ethernet_phy_get(port_num)); | |
1444 | return err; | |
1445 | } | |
1446 | ||
1447 | err = register_netdev(dev); | |
1448 | if (err) | |
1449 | goto out; | |
1450 | ||
1451 | p = dev->dev_addr; | |
1452 | printk(KERN_NOTICE | |
1453 | "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n", | |
1454 | dev->name, port_num, p[0], p[1], p[2], p[3], p[4], p[5]); | |
1455 | ||
1456 | if (dev->features & NETIF_F_SG) | |
1457 | printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name); | |
1458 | ||
1459 | if (dev->features & NETIF_F_IP_CSUM) | |
1460 | printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n", | |
1461 | dev->name); | |
1462 | ||
1463 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX | |
1464 | printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name); | |
1465 | #endif | |
1466 | ||
1467 | #ifdef MV643XX_COAL | |
1468 | printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n", | |
1469 | dev->name); | |
1470 | #endif | |
1471 | ||
1472 | #ifdef MV643XX_NAPI | |
1473 | printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name); | |
1474 | #endif | |
1475 | ||
b1529871 ND |
1476 | if (mp->tx_sram_size > 0) |
1477 | printk(KERN_NOTICE "%s: Using SRAM\n", dev->name); | |
1478 | ||
1da177e4 LT |
1479 | return 0; |
1480 | ||
1481 | out: | |
1482 | free_netdev(dev); | |
1483 | ||
1484 | return err; | |
1485 | } | |
1486 | ||
3ae5eaec | 1487 | static int mv643xx_eth_remove(struct platform_device *pdev) |
1da177e4 | 1488 | { |
3ae5eaec | 1489 | struct net_device *dev = platform_get_drvdata(pdev); |
1da177e4 LT |
1490 | |
1491 | unregister_netdev(dev); | |
1492 | flush_scheduled_work(); | |
1493 | ||
1494 | free_netdev(dev); | |
3ae5eaec | 1495 | platform_set_drvdata(pdev, NULL); |
1da177e4 LT |
1496 | return 0; |
1497 | } | |
1498 | ||
3ae5eaec | 1499 | static int mv643xx_eth_shared_probe(struct platform_device *pdev) |
1da177e4 | 1500 | { |
1da177e4 LT |
1501 | struct resource *res; |
1502 | ||
1503 | printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n"); | |
1504 | ||
1505 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1506 | if (res == NULL) | |
1507 | return -ENODEV; | |
1508 | ||
1509 | mv643xx_eth_shared_base = ioremap(res->start, | |
1510 | MV643XX_ETH_SHARED_REGS_SIZE); | |
1511 | if (mv643xx_eth_shared_base == NULL) | |
1512 | return -ENOMEM; | |
1513 | ||
1514 | return 0; | |
1515 | ||
1516 | } | |
1517 | ||
3ae5eaec | 1518 | static int mv643xx_eth_shared_remove(struct platform_device *pdev) |
1da177e4 LT |
1519 | { |
1520 | iounmap(mv643xx_eth_shared_base); | |
1521 | mv643xx_eth_shared_base = NULL; | |
1522 | ||
1523 | return 0; | |
1524 | } | |
1525 | ||
3ae5eaec | 1526 | static struct platform_driver mv643xx_eth_driver = { |
1da177e4 LT |
1527 | .probe = mv643xx_eth_probe, |
1528 | .remove = mv643xx_eth_remove, | |
3ae5eaec RK |
1529 | .driver = { |
1530 | .name = MV643XX_ETH_NAME, | |
1531 | }, | |
1da177e4 LT |
1532 | }; |
1533 | ||
3ae5eaec | 1534 | static struct platform_driver mv643xx_eth_shared_driver = { |
1da177e4 LT |
1535 | .probe = mv643xx_eth_shared_probe, |
1536 | .remove = mv643xx_eth_shared_remove, | |
3ae5eaec RK |
1537 | .driver = { |
1538 | .name = MV643XX_ETH_SHARED_NAME, | |
1539 | }, | |
1da177e4 LT |
1540 | }; |
1541 | ||
1542 | /* | |
1543 | * mv643xx_init_module | |
1544 | * | |
1545 | * Registers the network drivers into the Linux kernel | |
1546 | * | |
1547 | * Input : N/A | |
1548 | * | |
1549 | * Output : N/A | |
1550 | */ | |
1551 | static int __init mv643xx_init_module(void) | |
1552 | { | |
1553 | int rc; | |
1554 | ||
3ae5eaec | 1555 | rc = platform_driver_register(&mv643xx_eth_shared_driver); |
1da177e4 | 1556 | if (!rc) { |
3ae5eaec | 1557 | rc = platform_driver_register(&mv643xx_eth_driver); |
1da177e4 | 1558 | if (rc) |
3ae5eaec | 1559 | platform_driver_unregister(&mv643xx_eth_shared_driver); |
1da177e4 LT |
1560 | } |
1561 | return rc; | |
1562 | } | |
1563 | ||
1564 | /* | |
1565 | * mv643xx_cleanup_module | |
1566 | * | |
1567 | * Registers the network drivers into the Linux kernel | |
1568 | * | |
1569 | * Input : N/A | |
1570 | * | |
1571 | * Output : N/A | |
1572 | */ | |
1573 | static void __exit mv643xx_cleanup_module(void) | |
1574 | { | |
3ae5eaec RK |
1575 | platform_driver_unregister(&mv643xx_eth_driver); |
1576 | platform_driver_unregister(&mv643xx_eth_shared_driver); | |
1da177e4 LT |
1577 | } |
1578 | ||
1579 | module_init(mv643xx_init_module); | |
1580 | module_exit(mv643xx_cleanup_module); | |
1581 | ||
1582 | MODULE_LICENSE("GPL"); | |
1583 | MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani" | |
1584 | " and Dale Farnsworth"); | |
1585 | MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); | |
1586 | ||
1587 | /* | |
1588 | * The second part is the low level driver of the gigE ethernet ports. | |
1589 | */ | |
1590 | ||
1591 | /* | |
1592 | * Marvell's Gigabit Ethernet controller low level driver | |
1593 | * | |
1594 | * DESCRIPTION: | |
1595 | * This file introduce low level API to Marvell's Gigabit Ethernet | |
1596 | * controller. This Gigabit Ethernet Controller driver API controls | |
1597 | * 1) Operations (i.e. port init, start, reset etc'). | |
1598 | * 2) Data flow (i.e. port send, receive etc'). | |
1599 | * Each Gigabit Ethernet port is controlled via | |
1600 | * struct mv643xx_private. | |
1601 | * This struct includes user configuration information as well as | |
1602 | * driver internal data needed for its operations. | |
1603 | * | |
1604 | * Supported Features: | |
1605 | * - This low level driver is OS independent. Allocating memory for | |
1606 | * the descriptor rings and buffers are not within the scope of | |
1607 | * this driver. | |
1608 | * - The user is free from Rx/Tx queue managing. | |
1609 | * - This low level driver introduce functionality API that enable | |
1610 | * the to operate Marvell's Gigabit Ethernet Controller in a | |
1611 | * convenient way. | |
1612 | * - Simple Gigabit Ethernet port operation API. | |
1613 | * - Simple Gigabit Ethernet port data flow API. | |
1614 | * - Data flow and operation API support per queue functionality. | |
1615 | * - Support cached descriptors for better performance. | |
1616 | * - Enable access to all four DRAM banks and internal SRAM memory | |
1617 | * spaces. | |
1618 | * - PHY access and control API. | |
1619 | * - Port control register configuration API. | |
1620 | * - Full control over Unicast and Multicast MAC configurations. | |
1621 | * | |
1622 | * Operation flow: | |
1623 | * | |
1624 | * Initialization phase | |
1625 | * This phase complete the initialization of the the | |
1626 | * mv643xx_private struct. | |
1627 | * User information regarding port configuration has to be set | |
1628 | * prior to calling the port initialization routine. | |
1629 | * | |
1630 | * In this phase any port Tx/Rx activity is halted, MIB counters | |
1631 | * are cleared, PHY address is set according to user parameter and | |
1632 | * access to DRAM and internal SRAM memory spaces. | |
1633 | * | |
1634 | * Driver ring initialization | |
1635 | * Allocating memory for the descriptor rings and buffers is not | |
1636 | * within the scope of this driver. Thus, the user is required to | |
1637 | * allocate memory for the descriptors ring and buffers. Those | |
1638 | * memory parameters are used by the Rx and Tx ring initialization | |
1639 | * routines in order to curve the descriptor linked list in a form | |
1640 | * of a ring. | |
1641 | * Note: Pay special attention to alignment issues when using | |
1642 | * cached descriptors/buffers. In this phase the driver store | |
1643 | * information in the mv643xx_private struct regarding each queue | |
1644 | * ring. | |
1645 | * | |
1646 | * Driver start | |
1647 | * This phase prepares the Ethernet port for Rx and Tx activity. | |
1648 | * It uses the information stored in the mv643xx_private struct to | |
1649 | * initialize the various port registers. | |
1650 | * | |
1651 | * Data flow: | |
1652 | * All packet references to/from the driver are done using | |
1653 | * struct pkt_info. | |
1654 | * This struct is a unified struct used with Rx and Tx operations. | |
1655 | * This way the user is not required to be familiar with neither | |
1656 | * Tx nor Rx descriptors structures. | |
1657 | * The driver's descriptors rings are management by indexes. | |
1658 | * Those indexes controls the ring resources and used to indicate | |
1659 | * a SW resource error: | |
1660 | * 'current' | |
1661 | * This index points to the current available resource for use. For | |
1662 | * example in Rx process this index will point to the descriptor | |
1663 | * that will be passed to the user upon calling the receive | |
1664 | * routine. In Tx process, this index will point to the descriptor | |
1665 | * that will be assigned with the user packet info and transmitted. | |
1666 | * 'used' | |
1667 | * This index points to the descriptor that need to restore its | |
1668 | * resources. For example in Rx process, using the Rx buffer return | |
1669 | * API will attach the buffer returned in packet info to the | |
1670 | * descriptor pointed by 'used'. In Tx process, using the Tx | |
1671 | * descriptor return will merely return the user packet info with | |
1672 | * the command status of the transmitted buffer pointed by the | |
1673 | * 'used' index. Nevertheless, it is essential to use this routine | |
1674 | * to update the 'used' index. | |
1675 | * 'first' | |
1676 | * This index supports Tx Scatter-Gather. It points to the first | |
1677 | * descriptor of a packet assembled of multiple buffers. For | |
1678 | * example when in middle of Such packet we have a Tx resource | |
1679 | * error the 'curr' index get the value of 'first' to indicate | |
1680 | * that the ring returned to its state before trying to transmit | |
1681 | * this packet. | |
1682 | * | |
1683 | * Receive operation: | |
1684 | * The eth_port_receive API set the packet information struct, | |
1685 | * passed by the caller, with received information from the | |
1686 | * 'current' SDMA descriptor. | |
1687 | * It is the user responsibility to return this resource back | |
1688 | * to the Rx descriptor ring to enable the reuse of this source. | |
1689 | * Return Rx resource is done using the eth_rx_return_buff API. | |
1690 | * | |
1691 | * Transmit operation: | |
1692 | * The eth_port_send API supports Scatter-Gather which enables to | |
1693 | * send a packet spanned over multiple buffers. This means that | |
1694 | * for each packet info structure given by the user and put into | |
1695 | * the Tx descriptors ring, will be transmitted only if the 'LAST' | |
1696 | * bit will be set in the packet info command status field. This | |
1697 | * API also consider restriction regarding buffer alignments and | |
1698 | * sizes. | |
1699 | * The user must return a Tx resource after ensuring the buffer | |
1700 | * has been transmitted to enable the Tx ring indexes to update. | |
1701 | * | |
1702 | * BOARD LAYOUT | |
1703 | * This device is on-board. No jumper diagram is necessary. | |
1704 | * | |
1705 | * EXTERNAL INTERFACE | |
1706 | * | |
1707 | * Prior to calling the initialization routine eth_port_init() the user | |
1708 | * must set the following fields under mv643xx_private struct: | |
1709 | * port_num User Ethernet port number. | |
1710 | * port_mac_addr[6] User defined port MAC address. | |
1711 | * port_config User port configuration value. | |
1712 | * port_config_extend User port config extend value. | |
1713 | * port_sdma_config User port SDMA config value. | |
1714 | * port_serial_control User port serial control value. | |
1715 | * | |
1716 | * This driver data flow is done using the struct pkt_info which | |
1717 | * is a unified struct for Rx and Tx operations: | |
1718 | * | |
1719 | * byte_cnt Tx/Rx descriptor buffer byte count. | |
1720 | * l4i_chk CPU provided TCP Checksum. For Tx operation | |
1721 | * only. | |
1722 | * cmd_sts Tx/Rx descriptor command status. | |
1723 | * buf_ptr Tx/Rx descriptor buffer pointer. | |
1724 | * return_info Tx/Rx user resource return information. | |
1725 | */ | |
1726 | ||
1727 | /* defines */ | |
1728 | /* SDMA command macros */ | |
1729 | #define ETH_ENABLE_TX_QUEUE(eth_port) \ | |
1730 | mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), 1) | |
1731 | ||
1732 | /* locals */ | |
1733 | ||
1734 | /* PHY routines */ | |
1735 | static int ethernet_phy_get(unsigned int eth_port_num); | |
1736 | static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr); | |
1737 | ||
1738 | /* Ethernet Port routines */ | |
1739 | static int eth_port_uc_addr(unsigned int eth_port_num, unsigned char uc_nibble, | |
1740 | int option); | |
1741 | ||
1742 | /* | |
1743 | * eth_port_init - Initialize the Ethernet port driver | |
1744 | * | |
1745 | * DESCRIPTION: | |
1746 | * This function prepares the ethernet port to start its activity: | |
1747 | * 1) Completes the ethernet port driver struct initialization toward port | |
1748 | * start routine. | |
1749 | * 2) Resets the device to a quiescent state in case of warm reboot. | |
1750 | * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM. | |
1751 | * 4) Clean MAC tables. The reset status of those tables is unknown. | |
1752 | * 5) Set PHY address. | |
1753 | * Note: Call this routine prior to eth_port_start routine and after | |
1754 | * setting user values in the user fields of Ethernet port control | |
1755 | * struct. | |
1756 | * | |
1757 | * INPUT: | |
1758 | * struct mv643xx_private *mp Ethernet port control struct | |
1759 | * | |
1760 | * OUTPUT: | |
1761 | * See description. | |
1762 | * | |
1763 | * RETURN: | |
1764 | * None. | |
1765 | */ | |
1766 | static void eth_port_init(struct mv643xx_private *mp) | |
1767 | { | |
1768 | mp->port_rx_queue_command = 0; | |
1769 | mp->port_tx_queue_command = 0; | |
1770 | ||
1771 | mp->rx_resource_err = 0; | |
1772 | mp->tx_resource_err = 0; | |
1773 | ||
1774 | eth_port_reset(mp->port_num); | |
1775 | ||
1776 | eth_port_init_mac_tables(mp->port_num); | |
1777 | ||
1778 | ethernet_phy_reset(mp->port_num); | |
1779 | } | |
1780 | ||
1781 | /* | |
1782 | * eth_port_start - Start the Ethernet port activity. | |
1783 | * | |
1784 | * DESCRIPTION: | |
1785 | * This routine prepares the Ethernet port for Rx and Tx activity: | |
1786 | * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that | |
1787 | * has been initialized a descriptor's ring (using | |
1788 | * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx) | |
1789 | * 2. Initialize and enable the Ethernet configuration port by writing to | |
1790 | * the port's configuration and command registers. | |
1791 | * 3. Initialize and enable the SDMA by writing to the SDMA's | |
1792 | * configuration and command registers. After completing these steps, | |
1793 | * the ethernet port SDMA can starts to perform Rx and Tx activities. | |
1794 | * | |
1795 | * Note: Each Rx and Tx queue descriptor's list must be initialized prior | |
1796 | * to calling this function (use ether_init_tx_desc_ring for Tx queues | |
1797 | * and ether_init_rx_desc_ring for Rx queues). | |
1798 | * | |
1799 | * INPUT: | |
1800 | * struct mv643xx_private *mp Ethernet port control struct | |
1801 | * | |
1802 | * OUTPUT: | |
1803 | * Ethernet port is ready to receive and transmit. | |
1804 | * | |
1805 | * RETURN: | |
1806 | * None. | |
1807 | */ | |
1808 | static void eth_port_start(struct mv643xx_private *mp) | |
1809 | { | |
1810 | unsigned int port_num = mp->port_num; | |
1811 | int tx_curr_desc, rx_curr_desc; | |
1812 | ||
1813 | /* Assignment of Tx CTRP of given queue */ | |
1814 | tx_curr_desc = mp->tx_curr_desc_q; | |
1815 | mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num), | |
1816 | (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc)); | |
1817 | ||
1818 | /* Assignment of Rx CRDP of given queue */ | |
1819 | rx_curr_desc = mp->rx_curr_desc_q; | |
1820 | mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num), | |
1821 | (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc)); | |
1822 | ||
1823 | /* Add the assigned Ethernet address to the port's address table */ | |
1824 | eth_port_uc_addr_set(port_num, mp->port_mac_addr); | |
1825 | ||
1826 | /* Assign port configuration and command. */ | |
1827 | mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num), mp->port_config); | |
1828 | ||
1829 | mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num), | |
1830 | mp->port_config_extend); | |
1831 | ||
1832 | ||
1833 | /* Increase the Rx side buffer size if supporting GigE */ | |
1834 | if (mp->port_serial_control & MV643XX_ETH_SET_GMII_SPEED_TO_1000) | |
1835 | mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), | |
1836 | (mp->port_serial_control & 0xfff1ffff) | (0x5 << 17)); | |
1837 | else | |
1838 | mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), | |
1839 | mp->port_serial_control); | |
1840 | ||
1841 | mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), | |
1842 | mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)) | | |
1843 | MV643XX_ETH_SERIAL_PORT_ENABLE); | |
1844 | ||
1845 | /* Assign port SDMA configuration */ | |
1846 | mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num), | |
1847 | mp->port_sdma_config); | |
1848 | ||
1849 | /* Enable port Rx. */ | |
1850 | mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), | |
1851 | mp->port_rx_queue_command); | |
8f543718 DF |
1852 | |
1853 | /* Disable port bandwidth limits by clearing MTU register */ | |
1854 | mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num), 0); | |
1da177e4 LT |
1855 | } |
1856 | ||
1857 | /* | |
1858 | * eth_port_uc_addr_set - This function Set the port Unicast address. | |
1859 | * | |
1860 | * DESCRIPTION: | |
1861 | * This function Set the port Ethernet MAC address. | |
1862 | * | |
1863 | * INPUT: | |
1864 | * unsigned int eth_port_num Port number. | |
1865 | * char * p_addr Address to be set | |
1866 | * | |
1867 | * OUTPUT: | |
1868 | * Set MAC address low and high registers. also calls eth_port_uc_addr() | |
1869 | * To set the unicast table with the proper information. | |
1870 | * | |
1871 | * RETURN: | |
1872 | * N/A. | |
1873 | * | |
1874 | */ | |
1875 | static void eth_port_uc_addr_set(unsigned int eth_port_num, | |
1876 | unsigned char *p_addr) | |
1877 | { | |
1878 | unsigned int mac_h; | |
1879 | unsigned int mac_l; | |
1880 | ||
1881 | mac_l = (p_addr[4] << 8) | (p_addr[5]); | |
1882 | mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) | | |
1883 | (p_addr[3] << 0); | |
1884 | ||
1885 | mv_write(MV643XX_ETH_MAC_ADDR_LOW(eth_port_num), mac_l); | |
1886 | mv_write(MV643XX_ETH_MAC_ADDR_HIGH(eth_port_num), mac_h); | |
1887 | ||
1888 | /* Accept frames of this address */ | |
1889 | eth_port_uc_addr(eth_port_num, p_addr[5], ACCEPT_MAC_ADDR); | |
1890 | ||
1891 | return; | |
1892 | } | |
1893 | ||
1894 | /* | |
1895 | * eth_port_uc_addr_get - This function retrieves the port Unicast address | |
1896 | * (MAC address) from the ethernet hw registers. | |
1897 | * | |
1898 | * DESCRIPTION: | |
1899 | * This function retrieves the port Ethernet MAC address. | |
1900 | * | |
1901 | * INPUT: | |
1902 | * unsigned int eth_port_num Port number. | |
1903 | * char *MacAddr pointer where the MAC address is stored | |
1904 | * | |
1905 | * OUTPUT: | |
1906 | * Copy the MAC address to the location pointed to by MacAddr | |
1907 | * | |
1908 | * RETURN: | |
1909 | * N/A. | |
1910 | * | |
1911 | */ | |
1912 | static void eth_port_uc_addr_get(struct net_device *dev, unsigned char *p_addr) | |
1913 | { | |
1914 | struct mv643xx_private *mp = netdev_priv(dev); | |
1915 | unsigned int mac_h; | |
1916 | unsigned int mac_l; | |
1917 | ||
1918 | mac_h = mv_read(MV643XX_ETH_MAC_ADDR_HIGH(mp->port_num)); | |
1919 | mac_l = mv_read(MV643XX_ETH_MAC_ADDR_LOW(mp->port_num)); | |
1920 | ||
1921 | p_addr[0] = (mac_h >> 24) & 0xff; | |
1922 | p_addr[1] = (mac_h >> 16) & 0xff; | |
1923 | p_addr[2] = (mac_h >> 8) & 0xff; | |
1924 | p_addr[3] = mac_h & 0xff; | |
1925 | p_addr[4] = (mac_l >> 8) & 0xff; | |
1926 | p_addr[5] = mac_l & 0xff; | |
1927 | } | |
1928 | ||
1929 | /* | |
1930 | * eth_port_uc_addr - This function Set the port unicast address table | |
1931 | * | |
1932 | * DESCRIPTION: | |
1933 | * This function locates the proper entry in the Unicast table for the | |
1934 | * specified MAC nibble and sets its properties according to function | |
1935 | * parameters. | |
1936 | * | |
1937 | * INPUT: | |
1938 | * unsigned int eth_port_num Port number. | |
1939 | * unsigned char uc_nibble Unicast MAC Address last nibble. | |
1940 | * int option 0 = Add, 1 = remove address. | |
1941 | * | |
1942 | * OUTPUT: | |
1943 | * This function add/removes MAC addresses from the port unicast address | |
1944 | * table. | |
1945 | * | |
1946 | * RETURN: | |
1947 | * true is output succeeded. | |
1948 | * false if option parameter is invalid. | |
1949 | * | |
1950 | */ | |
1951 | static int eth_port_uc_addr(unsigned int eth_port_num, unsigned char uc_nibble, | |
1952 | int option) | |
1953 | { | |
1954 | unsigned int unicast_reg; | |
1955 | unsigned int tbl_offset; | |
1956 | unsigned int reg_offset; | |
1957 | ||
1958 | /* Locate the Unicast table entry */ | |
1959 | uc_nibble = (0xf & uc_nibble); | |
1960 | tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */ | |
1961 | reg_offset = uc_nibble % 4; /* Entry offset within the above register */ | |
1962 | ||
1963 | switch (option) { | |
1964 | case REJECT_MAC_ADDR: | |
1965 | /* Clear accepts frame bit at given unicast DA table entry */ | |
1966 | unicast_reg = mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE | |
1967 | (eth_port_num) + tbl_offset)); | |
1968 | ||
1969 | unicast_reg &= (0x0E << (8 * reg_offset)); | |
1970 | ||
1971 | mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE | |
1972 | (eth_port_num) + tbl_offset), unicast_reg); | |
1973 | break; | |
1974 | ||
1975 | case ACCEPT_MAC_ADDR: | |
1976 | /* Set accepts frame bit at unicast DA filter table entry */ | |
1977 | unicast_reg = | |
1978 | mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE | |
1979 | (eth_port_num) + tbl_offset)); | |
1980 | ||
1981 | unicast_reg |= (0x01 << (8 * reg_offset)); | |
1982 | ||
1983 | mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE | |
1984 | (eth_port_num) + tbl_offset), unicast_reg); | |
1985 | ||
1986 | break; | |
1987 | ||
1988 | default: | |
1989 | return 0; | |
1990 | } | |
1991 | ||
1992 | return 1; | |
1993 | } | |
1994 | ||
16e03018 DF |
1995 | /* |
1996 | * The entries in each table are indexed by a hash of a packet's MAC | |
1997 | * address. One bit in each entry determines whether the packet is | |
1998 | * accepted. There are 4 entries (each 8 bits wide) in each register | |
1999 | * of the table. The bits in each entry are defined as follows: | |
2000 | * 0 Accept=1, Drop=0 | |
2001 | * 3-1 Queue (ETH_Q0=0) | |
2002 | * 7-4 Reserved = 0; | |
2003 | */ | |
2004 | static void eth_port_set_filter_table_entry(int table, unsigned char entry) | |
2005 | { | |
2006 | unsigned int table_reg; | |
2007 | unsigned int tbl_offset; | |
2008 | unsigned int reg_offset; | |
2009 | ||
2010 | tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */ | |
2011 | reg_offset = entry % 4; /* Entry offset within the register */ | |
2012 | ||
2013 | /* Set "accepts frame bit" at specified table entry */ | |
2014 | table_reg = mv_read(table + tbl_offset); | |
2015 | table_reg |= 0x01 << (8 * reg_offset); | |
2016 | mv_write(table + tbl_offset, table_reg); | |
2017 | } | |
2018 | ||
2019 | /* | |
2020 | * eth_port_mc_addr - Multicast address settings. | |
2021 | * | |
2022 | * The MV device supports multicast using two tables: | |
2023 | * 1) Special Multicast Table for MAC addresses of the form | |
2024 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF). | |
2025 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast | |
2026 | * Table entries in the DA-Filter table. | |
2027 | * 2) Other Multicast Table for multicast of another type. A CRC-8bit | |
2028 | * is used as an index to the Other Multicast Table entries in the | |
2029 | * DA-Filter table. This function calculates the CRC-8bit value. | |
2030 | * In either case, eth_port_set_filter_table_entry() is then called | |
2031 | * to set to set the actual table entry. | |
2032 | */ | |
2033 | static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr) | |
2034 | { | |
2035 | unsigned int mac_h; | |
2036 | unsigned int mac_l; | |
2037 | unsigned char crc_result = 0; | |
2038 | int table; | |
2039 | int mac_array[48]; | |
2040 | int crc[8]; | |
2041 | int i; | |
2042 | ||
2043 | if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) && | |
2044 | (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) { | |
2045 | table = MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE | |
2046 | (eth_port_num); | |
2047 | eth_port_set_filter_table_entry(table, p_addr[5]); | |
2048 | return; | |
2049 | } | |
2050 | ||
2051 | /* Calculate CRC-8 out of the given address */ | |
2052 | mac_h = (p_addr[0] << 8) | (p_addr[1]); | |
2053 | mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) | | |
2054 | (p_addr[4] << 8) | (p_addr[5] << 0); | |
2055 | ||
2056 | for (i = 0; i < 32; i++) | |
2057 | mac_array[i] = (mac_l >> i) & 0x1; | |
2058 | for (i = 32; i < 48; i++) | |
2059 | mac_array[i] = (mac_h >> (i - 32)) & 0x1; | |
2060 | ||
2061 | crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^ | |
2062 | mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^ | |
2063 | mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^ | |
2064 | mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^ | |
2065 | mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0]; | |
2066 | ||
2067 | crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^ | |
2068 | mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^ | |
2069 | mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^ | |
2070 | mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^ | |
2071 | mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^ | |
2072 | mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^ | |
2073 | mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0]; | |
2074 | ||
2075 | crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^ | |
2076 | mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^ | |
2077 | mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^ | |
2078 | mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^ | |
2079 | mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ | |
2080 | mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0]; | |
2081 | ||
2082 | crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^ | |
2083 | mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^ | |
2084 | mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^ | |
2085 | mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ | |
2086 | mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^ | |
2087 | mac_array[3] ^ mac_array[2] ^ mac_array[1]; | |
2088 | ||
2089 | crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^ | |
2090 | mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^ | |
2091 | mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^ | |
2092 | mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^ | |
2093 | mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^ | |
2094 | mac_array[3] ^ mac_array[2]; | |
2095 | ||
2096 | crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^ | |
2097 | mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^ | |
2098 | mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^ | |
2099 | mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^ | |
2100 | mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^ | |
2101 | mac_array[4] ^ mac_array[3]; | |
2102 | ||
2103 | crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^ | |
2104 | mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^ | |
2105 | mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^ | |
2106 | mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^ | |
2107 | mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^ | |
2108 | mac_array[4]; | |
2109 | ||
2110 | crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^ | |
2111 | mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^ | |
2112 | mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^ | |
2113 | mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^ | |
2114 | mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5]; | |
2115 | ||
2116 | for (i = 0; i < 8; i++) | |
2117 | crc_result = crc_result | (crc[i] << i); | |
2118 | ||
2119 | table = MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num); | |
2120 | eth_port_set_filter_table_entry(table, crc_result); | |
2121 | } | |
2122 | ||
2123 | /* | |
2124 | * Set the entire multicast list based on dev->mc_list. | |
2125 | */ | |
2126 | static void eth_port_set_multicast_list(struct net_device *dev) | |
2127 | { | |
2128 | ||
2129 | struct dev_mc_list *mc_list; | |
2130 | int i; | |
2131 | int table_index; | |
2132 | struct mv643xx_private *mp = netdev_priv(dev); | |
2133 | unsigned int eth_port_num = mp->port_num; | |
2134 | ||
2135 | /* If the device is in promiscuous mode or in all multicast mode, | |
2136 | * we will fully populate both multicast tables with accept. | |
2137 | * This is guaranteed to yield a match on all multicast addresses... | |
2138 | */ | |
2139 | if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) { | |
2140 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { | |
2141 | /* Set all entries in DA filter special multicast | |
2142 | * table (Ex_dFSMT) | |
2143 | * Set for ETH_Q0 for now | |
2144 | * Bits | |
2145 | * 0 Accept=1, Drop=0 | |
2146 | * 3-1 Queue ETH_Q0=0 | |
2147 | * 7-4 Reserved = 0; | |
2148 | */ | |
2149 | mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101); | |
2150 | ||
2151 | /* Set all entries in DA filter other multicast | |
2152 | * table (Ex_dFOMT) | |
2153 | * Set for ETH_Q0 for now | |
2154 | * Bits | |
2155 | * 0 Accept=1, Drop=0 | |
2156 | * 3-1 Queue ETH_Q0=0 | |
2157 | * 7-4 Reserved = 0; | |
2158 | */ | |
2159 | mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101); | |
2160 | } | |
2161 | return; | |
2162 | } | |
2163 | ||
2164 | /* We will clear out multicast tables every time we get the list. | |
2165 | * Then add the entire new list... | |
2166 | */ | |
2167 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { | |
2168 | /* Clear DA filter special multicast table (Ex_dFSMT) */ | |
2169 | mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE | |
2170 | (eth_port_num) + table_index, 0); | |
2171 | ||
2172 | /* Clear DA filter other multicast table (Ex_dFOMT) */ | |
2173 | mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE | |
2174 | (eth_port_num) + table_index, 0); | |
2175 | } | |
2176 | ||
2177 | /* Get pointer to net_device multicast list and add each one... */ | |
2178 | for (i = 0, mc_list = dev->mc_list; | |
2179 | (i < 256) && (mc_list != NULL) && (i < dev->mc_count); | |
2180 | i++, mc_list = mc_list->next) | |
2181 | if (mc_list->dmi_addrlen == 6) | |
2182 | eth_port_mc_addr(eth_port_num, mc_list->dmi_addr); | |
2183 | } | |
2184 | ||
1da177e4 LT |
2185 | /* |
2186 | * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables | |
2187 | * | |
2188 | * DESCRIPTION: | |
2189 | * Go through all the DA filter tables (Unicast, Special Multicast & | |
2190 | * Other Multicast) and set each entry to 0. | |
2191 | * | |
2192 | * INPUT: | |
2193 | * unsigned int eth_port_num Ethernet Port number. | |
2194 | * | |
2195 | * OUTPUT: | |
2196 | * Multicast and Unicast packets are rejected. | |
2197 | * | |
2198 | * RETURN: | |
2199 | * None. | |
2200 | */ | |
2201 | static void eth_port_init_mac_tables(unsigned int eth_port_num) | |
2202 | { | |
2203 | int table_index; | |
2204 | ||
2205 | /* Clear DA filter unicast table (Ex_dFUT) */ | |
2206 | for (table_index = 0; table_index <= 0xC; table_index += 4) | |
2207 | mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE | |
2208 | (eth_port_num) + table_index), 0); | |
2209 | ||
2210 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { | |
2211 | /* Clear DA filter special multicast table (Ex_dFSMT) */ | |
16e03018 DF |
2212 | mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE |
2213 | (eth_port_num) + table_index, 0); | |
1da177e4 | 2214 | /* Clear DA filter other multicast table (Ex_dFOMT) */ |
16e03018 DF |
2215 | mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE |
2216 | (eth_port_num) + table_index, 0); | |
1da177e4 LT |
2217 | } |
2218 | } | |
2219 | ||
2220 | /* | |
2221 | * eth_clear_mib_counters - Clear all MIB counters | |
2222 | * | |
2223 | * DESCRIPTION: | |
2224 | * This function clears all MIB counters of a specific ethernet port. | |
2225 | * A read from the MIB counter will reset the counter. | |
2226 | * | |
2227 | * INPUT: | |
2228 | * unsigned int eth_port_num Ethernet Port number. | |
2229 | * | |
2230 | * OUTPUT: | |
2231 | * After reading all MIB counters, the counters resets. | |
2232 | * | |
2233 | * RETURN: | |
2234 | * MIB counter value. | |
2235 | * | |
2236 | */ | |
2237 | static void eth_clear_mib_counters(unsigned int eth_port_num) | |
2238 | { | |
2239 | int i; | |
2240 | ||
2241 | /* Perform dummy reads from MIB counters */ | |
2242 | for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; | |
2243 | i += 4) | |
2244 | mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num) + i); | |
2245 | } | |
2246 | ||
2247 | static inline u32 read_mib(struct mv643xx_private *mp, int offset) | |
2248 | { | |
2249 | return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp->port_num) + offset); | |
2250 | } | |
2251 | ||
2252 | static void eth_update_mib_counters(struct mv643xx_private *mp) | |
2253 | { | |
2254 | struct mv643xx_mib_counters *p = &mp->mib_counters; | |
2255 | int offset; | |
2256 | ||
2257 | p->good_octets_received += | |
2258 | read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW); | |
2259 | p->good_octets_received += | |
2260 | (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32; | |
2261 | ||
2262 | for (offset = ETH_MIB_BAD_OCTETS_RECEIVED; | |
2263 | offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS; | |
2264 | offset += 4) | |
2265 | *(u32 *)((char *)p + offset) = read_mib(mp, offset); | |
2266 | ||
2267 | p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW); | |
2268 | p->good_octets_sent += | |
2269 | (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32; | |
2270 | ||
2271 | for (offset = ETH_MIB_GOOD_FRAMES_SENT; | |
2272 | offset <= ETH_MIB_LATE_COLLISION; | |
2273 | offset += 4) | |
2274 | *(u32 *)((char *)p + offset) = read_mib(mp, offset); | |
2275 | } | |
2276 | ||
2277 | /* | |
2278 | * ethernet_phy_detect - Detect whether a phy is present | |
2279 | * | |
2280 | * DESCRIPTION: | |
2281 | * This function tests whether there is a PHY present on | |
2282 | * the specified port. | |
2283 | * | |
2284 | * INPUT: | |
2285 | * unsigned int eth_port_num Ethernet Port number. | |
2286 | * | |
2287 | * OUTPUT: | |
2288 | * None | |
2289 | * | |
2290 | * RETURN: | |
2291 | * 0 on success | |
2292 | * -ENODEV on failure | |
2293 | * | |
2294 | */ | |
2295 | static int ethernet_phy_detect(unsigned int port_num) | |
2296 | { | |
2297 | unsigned int phy_reg_data0; | |
2298 | int auto_neg; | |
2299 | ||
2300 | eth_port_read_smi_reg(port_num, 0, &phy_reg_data0); | |
2301 | auto_neg = phy_reg_data0 & 0x1000; | |
2302 | phy_reg_data0 ^= 0x1000; /* invert auto_neg */ | |
2303 | eth_port_write_smi_reg(port_num, 0, phy_reg_data0); | |
2304 | ||
2305 | eth_port_read_smi_reg(port_num, 0, &phy_reg_data0); | |
2306 | if ((phy_reg_data0 & 0x1000) == auto_neg) | |
2307 | return -ENODEV; /* change didn't take */ | |
2308 | ||
2309 | phy_reg_data0 ^= 0x1000; | |
2310 | eth_port_write_smi_reg(port_num, 0, phy_reg_data0); | |
2311 | return 0; | |
2312 | } | |
2313 | ||
2314 | /* | |
2315 | * ethernet_phy_get - Get the ethernet port PHY address. | |
2316 | * | |
2317 | * DESCRIPTION: | |
2318 | * This routine returns the given ethernet port PHY address. | |
2319 | * | |
2320 | * INPUT: | |
2321 | * unsigned int eth_port_num Ethernet Port number. | |
2322 | * | |
2323 | * OUTPUT: | |
2324 | * None. | |
2325 | * | |
2326 | * RETURN: | |
2327 | * PHY address. | |
2328 | * | |
2329 | */ | |
2330 | static int ethernet_phy_get(unsigned int eth_port_num) | |
2331 | { | |
2332 | unsigned int reg_data; | |
2333 | ||
2334 | reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG); | |
2335 | ||
2336 | return ((reg_data >> (5 * eth_port_num)) & 0x1f); | |
2337 | } | |
2338 | ||
2339 | /* | |
2340 | * ethernet_phy_set - Set the ethernet port PHY address. | |
2341 | * | |
2342 | * DESCRIPTION: | |
2343 | * This routine sets the given ethernet port PHY address. | |
2344 | * | |
2345 | * INPUT: | |
2346 | * unsigned int eth_port_num Ethernet Port number. | |
2347 | * int phy_addr PHY address. | |
2348 | * | |
2349 | * OUTPUT: | |
2350 | * None. | |
2351 | * | |
2352 | * RETURN: | |
2353 | * None. | |
2354 | * | |
2355 | */ | |
2356 | static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr) | |
2357 | { | |
2358 | u32 reg_data; | |
2359 | int addr_shift = 5 * eth_port_num; | |
2360 | ||
2361 | reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG); | |
2362 | reg_data &= ~(0x1f << addr_shift); | |
2363 | reg_data |= (phy_addr & 0x1f) << addr_shift; | |
2364 | mv_write(MV643XX_ETH_PHY_ADDR_REG, reg_data); | |
2365 | } | |
2366 | ||
2367 | /* | |
2368 | * ethernet_phy_reset - Reset Ethernet port PHY. | |
2369 | * | |
2370 | * DESCRIPTION: | |
2371 | * This routine utilizes the SMI interface to reset the ethernet port PHY. | |
2372 | * | |
2373 | * INPUT: | |
2374 | * unsigned int eth_port_num Ethernet Port number. | |
2375 | * | |
2376 | * OUTPUT: | |
2377 | * The PHY is reset. | |
2378 | * | |
2379 | * RETURN: | |
2380 | * None. | |
2381 | * | |
2382 | */ | |
2383 | static void ethernet_phy_reset(unsigned int eth_port_num) | |
2384 | { | |
2385 | unsigned int phy_reg_data; | |
2386 | ||
2387 | /* Reset the PHY */ | |
2388 | eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data); | |
2389 | phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */ | |
2390 | eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data); | |
2391 | } | |
2392 | ||
2393 | /* | |
2394 | * eth_port_reset - Reset Ethernet port | |
2395 | * | |
2396 | * DESCRIPTION: | |
2397 | * This routine resets the chip by aborting any SDMA engine activity and | |
2398 | * clearing the MIB counters. The Receiver and the Transmit unit are in | |
2399 | * idle state after this command is performed and the port is disabled. | |
2400 | * | |
2401 | * INPUT: | |
2402 | * unsigned int eth_port_num Ethernet Port number. | |
2403 | * | |
2404 | * OUTPUT: | |
2405 | * Channel activity is halted. | |
2406 | * | |
2407 | * RETURN: | |
2408 | * None. | |
2409 | * | |
2410 | */ | |
2411 | static void eth_port_reset(unsigned int port_num) | |
2412 | { | |
2413 | unsigned int reg_data; | |
2414 | ||
2415 | /* Stop Tx port activity. Check port Tx activity. */ | |
2416 | reg_data = mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num)); | |
2417 | ||
2418 | if (reg_data & 0xFF) { | |
2419 | /* Issue stop command for active channels only */ | |
2420 | mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), | |
2421 | (reg_data << 8)); | |
2422 | ||
2423 | /* Wait for all Tx activity to terminate. */ | |
2424 | /* Check port cause register that all Tx queues are stopped */ | |
2425 | while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num)) | |
2426 | & 0xFF) | |
2427 | udelay(10); | |
2428 | } | |
2429 | ||
2430 | /* Stop Rx port activity. Check port Rx activity. */ | |
2431 | reg_data = mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num)); | |
2432 | ||
2433 | if (reg_data & 0xFF) { | |
2434 | /* Issue stop command for active channels only */ | |
2435 | mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), | |
2436 | (reg_data << 8)); | |
2437 | ||
2438 | /* Wait for all Rx activity to terminate. */ | |
2439 | /* Check port cause register that all Rx queues are stopped */ | |
2440 | while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num)) | |
2441 | & 0xFF) | |
2442 | udelay(10); | |
2443 | } | |
2444 | ||
2445 | /* Clear all MIB counters */ | |
2446 | eth_clear_mib_counters(port_num); | |
2447 | ||
2448 | /* Reset the Enable bit in the Configuration Register */ | |
2449 | reg_data = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)); | |
2450 | reg_data &= ~MV643XX_ETH_SERIAL_PORT_ENABLE; | |
2451 | mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), reg_data); | |
2452 | } | |
2453 | ||
1da177e4 LT |
2454 | |
2455 | static int eth_port_autoneg_supported(unsigned int eth_port_num) | |
2456 | { | |
2457 | unsigned int phy_reg_data0; | |
2458 | ||
2459 | eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data0); | |
2460 | ||
2461 | return phy_reg_data0 & 0x1000; | |
2462 | } | |
2463 | ||
2464 | static int eth_port_link_is_up(unsigned int eth_port_num) | |
2465 | { | |
2466 | unsigned int phy_reg_data1; | |
2467 | ||
2468 | eth_port_read_smi_reg(eth_port_num, 1, &phy_reg_data1); | |
2469 | ||
2470 | if (eth_port_autoneg_supported(eth_port_num)) { | |
2471 | if (phy_reg_data1 & 0x20) /* auto-neg complete */ | |
2472 | return 1; | |
2473 | } else if (phy_reg_data1 & 0x4) /* link up */ | |
2474 | return 1; | |
2475 | ||
2476 | return 0; | |
2477 | } | |
2478 | ||
1da177e4 LT |
2479 | /* |
2480 | * eth_port_read_smi_reg - Read PHY registers | |
2481 | * | |
2482 | * DESCRIPTION: | |
2483 | * This routine utilize the SMI interface to interact with the PHY in | |
2484 | * order to perform PHY register read. | |
2485 | * | |
2486 | * INPUT: | |
2487 | * unsigned int port_num Ethernet Port number. | |
2488 | * unsigned int phy_reg PHY register address offset. | |
2489 | * unsigned int *value Register value buffer. | |
2490 | * | |
2491 | * OUTPUT: | |
2492 | * Write the value of a specified PHY register into given buffer. | |
2493 | * | |
2494 | * RETURN: | |
2495 | * false if the PHY is busy or read data is not in valid state. | |
2496 | * true otherwise. | |
2497 | * | |
2498 | */ | |
2499 | static void eth_port_read_smi_reg(unsigned int port_num, | |
2500 | unsigned int phy_reg, unsigned int *value) | |
2501 | { | |
2502 | int phy_addr = ethernet_phy_get(port_num); | |
2503 | unsigned long flags; | |
2504 | int i; | |
2505 | ||
2506 | /* the SMI register is a shared resource */ | |
2507 | spin_lock_irqsave(&mv643xx_eth_phy_lock, flags); | |
2508 | ||
2509 | /* wait for the SMI register to become available */ | |
2510 | for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) { | |
2511 | if (i == PHY_WAIT_ITERATIONS) { | |
2512 | printk("mv643xx PHY busy timeout, port %d\n", port_num); | |
2513 | goto out; | |
2514 | } | |
2515 | udelay(PHY_WAIT_MICRO_SECONDS); | |
2516 | } | |
2517 | ||
2518 | mv_write(MV643XX_ETH_SMI_REG, | |
2519 | (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ); | |
2520 | ||
2521 | /* now wait for the data to be valid */ | |
2522 | for (i = 0; !(mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_READ_VALID); i++) { | |
2523 | if (i == PHY_WAIT_ITERATIONS) { | |
2524 | printk("mv643xx PHY read timeout, port %d\n", port_num); | |
2525 | goto out; | |
2526 | } | |
2527 | udelay(PHY_WAIT_MICRO_SECONDS); | |
2528 | } | |
2529 | ||
2530 | *value = mv_read(MV643XX_ETH_SMI_REG) & 0xffff; | |
2531 | out: | |
2532 | spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags); | |
2533 | } | |
2534 | ||
2535 | /* | |
2536 | * eth_port_write_smi_reg - Write to PHY registers | |
2537 | * | |
2538 | * DESCRIPTION: | |
2539 | * This routine utilize the SMI interface to interact with the PHY in | |
2540 | * order to perform writes to PHY registers. | |
2541 | * | |
2542 | * INPUT: | |
2543 | * unsigned int eth_port_num Ethernet Port number. | |
2544 | * unsigned int phy_reg PHY register address offset. | |
2545 | * unsigned int value Register value. | |
2546 | * | |
2547 | * OUTPUT: | |
2548 | * Write the given value to the specified PHY register. | |
2549 | * | |
2550 | * RETURN: | |
2551 | * false if the PHY is busy. | |
2552 | * true otherwise. | |
2553 | * | |
2554 | */ | |
2555 | static void eth_port_write_smi_reg(unsigned int eth_port_num, | |
2556 | unsigned int phy_reg, unsigned int value) | |
2557 | { | |
2558 | int phy_addr; | |
2559 | int i; | |
2560 | unsigned long flags; | |
2561 | ||
2562 | phy_addr = ethernet_phy_get(eth_port_num); | |
2563 | ||
2564 | /* the SMI register is a shared resource */ | |
2565 | spin_lock_irqsave(&mv643xx_eth_phy_lock, flags); | |
2566 | ||
2567 | /* wait for the SMI register to become available */ | |
2568 | for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) { | |
2569 | if (i == PHY_WAIT_ITERATIONS) { | |
2570 | printk("mv643xx PHY busy timeout, port %d\n", | |
2571 | eth_port_num); | |
2572 | goto out; | |
2573 | } | |
2574 | udelay(PHY_WAIT_MICRO_SECONDS); | |
2575 | } | |
2576 | ||
2577 | mv_write(MV643XX_ETH_SMI_REG, (phy_addr << 16) | (phy_reg << 21) | | |
2578 | ETH_SMI_OPCODE_WRITE | (value & 0xffff)); | |
2579 | out: | |
2580 | spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags); | |
2581 | } | |
2582 | ||
2583 | /* | |
2584 | * eth_port_send - Send an Ethernet packet | |
2585 | * | |
2586 | * DESCRIPTION: | |
2587 | * This routine send a given packet described by p_pktinfo parameter. It | |
2588 | * supports transmitting of a packet spaned over multiple buffers. The | |
2589 | * routine updates 'curr' and 'first' indexes according to the packet | |
2590 | * segment passed to the routine. In case the packet segment is first, | |
2591 | * the 'first' index is update. In any case, the 'curr' index is updated. | |
2592 | * If the routine get into Tx resource error it assigns 'curr' index as | |
2593 | * 'first'. This way the function can abort Tx process of multiple | |
2594 | * descriptors per packet. | |
2595 | * | |
2596 | * INPUT: | |
2597 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
2598 | * struct pkt_info *p_pkt_info User packet buffer. | |
2599 | * | |
2600 | * OUTPUT: | |
2601 | * Tx ring 'curr' and 'first' indexes are updated. | |
2602 | * | |
2603 | * RETURN: | |
2604 | * ETH_QUEUE_FULL in case of Tx resource error. | |
2605 | * ETH_ERROR in case the routine can not access Tx desc ring. | |
2606 | * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource. | |
2607 | * ETH_OK otherwise. | |
2608 | * | |
2609 | */ | |
2610 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX | |
2611 | /* | |
2612 | * Modified to include the first descriptor pointer in case of SG | |
2613 | */ | |
2614 | static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp, | |
2615 | struct pkt_info *p_pkt_info) | |
2616 | { | |
2617 | int tx_desc_curr, tx_desc_used, tx_first_desc, tx_next_desc; | |
2618 | struct eth_tx_desc *current_descriptor; | |
2619 | struct eth_tx_desc *first_descriptor; | |
2620 | u32 command; | |
2621 | ||
2622 | /* Do not process Tx ring in case of Tx ring resource error */ | |
2623 | if (mp->tx_resource_err) | |
2624 | return ETH_QUEUE_FULL; | |
2625 | ||
2626 | /* | |
2627 | * The hardware requires that each buffer that is <= 8 bytes | |
2628 | * in length must be aligned on an 8 byte boundary. | |
2629 | */ | |
2630 | if (p_pkt_info->byte_cnt <= 8 && p_pkt_info->buf_ptr & 0x7) { | |
2631 | printk(KERN_ERR | |
2632 | "mv643xx_eth port %d: packet size <= 8 problem\n", | |
2633 | mp->port_num); | |
2634 | return ETH_ERROR; | |
2635 | } | |
2636 | ||
b111ceb6 DF |
2637 | mp->tx_ring_skbs++; |
2638 | BUG_ON(mp->tx_ring_skbs > mp->tx_ring_size); | |
2639 | ||
1da177e4 LT |
2640 | /* Get the Tx Desc ring indexes */ |
2641 | tx_desc_curr = mp->tx_curr_desc_q; | |
2642 | tx_desc_used = mp->tx_used_desc_q; | |
2643 | ||
2644 | current_descriptor = &mp->p_tx_desc_area[tx_desc_curr]; | |
2645 | ||
2646 | tx_next_desc = (tx_desc_curr + 1) % mp->tx_ring_size; | |
2647 | ||
2648 | current_descriptor->buf_ptr = p_pkt_info->buf_ptr; | |
2649 | current_descriptor->byte_cnt = p_pkt_info->byte_cnt; | |
2650 | current_descriptor->l4i_chk = p_pkt_info->l4i_chk; | |
2651 | mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info; | |
2652 | ||
2653 | command = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC | | |
2654 | ETH_BUFFER_OWNED_BY_DMA; | |
2655 | if (command & ETH_TX_FIRST_DESC) { | |
2656 | tx_first_desc = tx_desc_curr; | |
2657 | mp->tx_first_desc_q = tx_first_desc; | |
2658 | first_descriptor = current_descriptor; | |
2659 | mp->tx_first_command = command; | |
2660 | } else { | |
2661 | tx_first_desc = mp->tx_first_desc_q; | |
2662 | first_descriptor = &mp->p_tx_desc_area[tx_first_desc]; | |
2663 | BUG_ON(first_descriptor == NULL); | |
2664 | current_descriptor->cmd_sts = command; | |
2665 | } | |
2666 | ||
2667 | if (command & ETH_TX_LAST_DESC) { | |
2668 | wmb(); | |
2669 | first_descriptor->cmd_sts = mp->tx_first_command; | |
2670 | ||
2671 | wmb(); | |
2672 | ETH_ENABLE_TX_QUEUE(mp->port_num); | |
2673 | ||
2674 | /* | |
2675 | * Finish Tx packet. Update first desc in case of Tx resource | |
2676 | * error */ | |
2677 | tx_first_desc = tx_next_desc; | |
2678 | mp->tx_first_desc_q = tx_first_desc; | |
2679 | } | |
2680 | ||
2681 | /* Check for ring index overlap in the Tx desc ring */ | |
2682 | if (tx_next_desc == tx_desc_used) { | |
2683 | mp->tx_resource_err = 1; | |
2684 | mp->tx_curr_desc_q = tx_first_desc; | |
2685 | ||
2686 | return ETH_QUEUE_LAST_RESOURCE; | |
2687 | } | |
2688 | ||
2689 | mp->tx_curr_desc_q = tx_next_desc; | |
2690 | ||
2691 | return ETH_OK; | |
2692 | } | |
2693 | #else | |
2694 | static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp, | |
2695 | struct pkt_info *p_pkt_info) | |
2696 | { | |
2697 | int tx_desc_curr; | |
2698 | int tx_desc_used; | |
2699 | struct eth_tx_desc *current_descriptor; | |
2700 | unsigned int command_status; | |
2701 | ||
2702 | /* Do not process Tx ring in case of Tx ring resource error */ | |
2703 | if (mp->tx_resource_err) | |
2704 | return ETH_QUEUE_FULL; | |
2705 | ||
b111ceb6 DF |
2706 | mp->tx_ring_skbs++; |
2707 | BUG_ON(mp->tx_ring_skbs > mp->tx_ring_size); | |
2708 | ||
1da177e4 LT |
2709 | /* Get the Tx Desc ring indexes */ |
2710 | tx_desc_curr = mp->tx_curr_desc_q; | |
2711 | tx_desc_used = mp->tx_used_desc_q; | |
2712 | current_descriptor = &mp->p_tx_desc_area[tx_desc_curr]; | |
2713 | ||
2714 | command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC; | |
2715 | current_descriptor->buf_ptr = p_pkt_info->buf_ptr; | |
2716 | current_descriptor->byte_cnt = p_pkt_info->byte_cnt; | |
2717 | mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info; | |
2718 | ||
2719 | /* Set last desc with DMA ownership and interrupt enable. */ | |
2720 | wmb(); | |
2721 | current_descriptor->cmd_sts = command_status | | |
2722 | ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT; | |
2723 | ||
2724 | wmb(); | |
2725 | ETH_ENABLE_TX_QUEUE(mp->port_num); | |
2726 | ||
2727 | /* Finish Tx packet. Update first desc in case of Tx resource error */ | |
2728 | tx_desc_curr = (tx_desc_curr + 1) % mp->tx_ring_size; | |
2729 | ||
2730 | /* Update the current descriptor */ | |
2731 | mp->tx_curr_desc_q = tx_desc_curr; | |
2732 | ||
2733 | /* Check for ring index overlap in the Tx desc ring */ | |
2734 | if (tx_desc_curr == tx_desc_used) { | |
2735 | mp->tx_resource_err = 1; | |
2736 | return ETH_QUEUE_LAST_RESOURCE; | |
2737 | } | |
2738 | ||
2739 | return ETH_OK; | |
2740 | } | |
2741 | #endif | |
2742 | ||
2743 | /* | |
2744 | * eth_tx_return_desc - Free all used Tx descriptors | |
2745 | * | |
2746 | * DESCRIPTION: | |
2747 | * This routine returns the transmitted packet information to the caller. | |
2748 | * It uses the 'first' index to support Tx desc return in case a transmit | |
2749 | * of a packet spanned over multiple buffer still in process. | |
2750 | * In case the Tx queue was in "resource error" condition, where there are | |
2751 | * no available Tx resources, the function resets the resource error flag. | |
2752 | * | |
2753 | * INPUT: | |
2754 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
2755 | * struct pkt_info *p_pkt_info User packet buffer. | |
2756 | * | |
2757 | * OUTPUT: | |
2758 | * Tx ring 'first' and 'used' indexes are updated. | |
2759 | * | |
2760 | * RETURN: | |
8f518703 DF |
2761 | * ETH_OK on success |
2762 | * ETH_ERROR otherwise. | |
1da177e4 LT |
2763 | * |
2764 | */ | |
2765 | static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv643xx_private *mp, | |
2766 | struct pkt_info *p_pkt_info) | |
2767 | { | |
2768 | int tx_desc_used; | |
8f518703 DF |
2769 | int tx_busy_desc; |
2770 | struct eth_tx_desc *p_tx_desc_used; | |
2771 | unsigned int command_status; | |
2772 | unsigned long flags; | |
2773 | int err = ETH_OK; | |
2774 | ||
2775 | spin_lock_irqsave(&mp->lock, flags); | |
2776 | ||
1da177e4 | 2777 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX |
8f518703 | 2778 | tx_busy_desc = mp->tx_first_desc_q; |
1da177e4 | 2779 | #else |
8f518703 | 2780 | tx_busy_desc = mp->tx_curr_desc_q; |
1da177e4 | 2781 | #endif |
1da177e4 LT |
2782 | |
2783 | /* Get the Tx Desc ring indexes */ | |
2784 | tx_desc_used = mp->tx_used_desc_q; | |
2785 | ||
2786 | p_tx_desc_used = &mp->p_tx_desc_area[tx_desc_used]; | |
2787 | ||
2788 | /* Sanity check */ | |
8f518703 DF |
2789 | if (p_tx_desc_used == NULL) { |
2790 | err = ETH_ERROR; | |
2791 | goto out; | |
2792 | } | |
1da177e4 LT |
2793 | |
2794 | /* Stop release. About to overlap the current available Tx descriptor */ | |
8f518703 DF |
2795 | if (tx_desc_used == tx_busy_desc && !mp->tx_resource_err) { |
2796 | err = ETH_ERROR; | |
2797 | goto out; | |
2798 | } | |
1da177e4 LT |
2799 | |
2800 | command_status = p_tx_desc_used->cmd_sts; | |
2801 | ||
2802 | /* Still transmitting... */ | |
8f518703 DF |
2803 | if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { |
2804 | err = ETH_ERROR; | |
2805 | goto out; | |
2806 | } | |
1da177e4 LT |
2807 | |
2808 | /* Pass the packet information to the caller */ | |
2809 | p_pkt_info->cmd_sts = command_status; | |
2810 | p_pkt_info->return_info = mp->tx_skb[tx_desc_used]; | |
4eaa3cb3 PG |
2811 | p_pkt_info->buf_ptr = p_tx_desc_used->buf_ptr; |
2812 | p_pkt_info->byte_cnt = p_tx_desc_used->byte_cnt; | |
1da177e4 LT |
2813 | mp->tx_skb[tx_desc_used] = NULL; |
2814 | ||
2815 | /* Update the next descriptor to release. */ | |
2816 | mp->tx_used_desc_q = (tx_desc_used + 1) % mp->tx_ring_size; | |
2817 | ||
2818 | /* Any Tx return cancels the Tx resource error status */ | |
2819 | mp->tx_resource_err = 0; | |
2820 | ||
b111ceb6 DF |
2821 | BUG_ON(mp->tx_ring_skbs == 0); |
2822 | mp->tx_ring_skbs--; | |
2823 | ||
8f518703 DF |
2824 | out: |
2825 | spin_unlock_irqrestore(&mp->lock, flags); | |
2826 | ||
2827 | return err; | |
1da177e4 LT |
2828 | } |
2829 | ||
2830 | /* | |
2831 | * eth_port_receive - Get received information from Rx ring. | |
2832 | * | |
2833 | * DESCRIPTION: | |
2834 | * This routine returns the received data to the caller. There is no | |
2835 | * data copying during routine operation. All information is returned | |
2836 | * using pointer to packet information struct passed from the caller. | |
2837 | * If the routine exhausts Rx ring resources then the resource error flag | |
2838 | * is set. | |
2839 | * | |
2840 | * INPUT: | |
2841 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
2842 | * struct pkt_info *p_pkt_info User packet buffer. | |
2843 | * | |
2844 | * OUTPUT: | |
2845 | * Rx ring current and used indexes are updated. | |
2846 | * | |
2847 | * RETURN: | |
2848 | * ETH_ERROR in case the routine can not access Rx desc ring. | |
2849 | * ETH_QUEUE_FULL if Rx ring resources are exhausted. | |
2850 | * ETH_END_OF_JOB if there is no received data. | |
2851 | * ETH_OK otherwise. | |
2852 | */ | |
2853 | static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp, | |
2854 | struct pkt_info *p_pkt_info) | |
2855 | { | |
2856 | int rx_next_curr_desc, rx_curr_desc, rx_used_desc; | |
2857 | volatile struct eth_rx_desc *p_rx_desc; | |
2858 | unsigned int command_status; | |
8f518703 | 2859 | unsigned long flags; |
1da177e4 LT |
2860 | |
2861 | /* Do not process Rx ring in case of Rx ring resource error */ | |
2862 | if (mp->rx_resource_err) | |
2863 | return ETH_QUEUE_FULL; | |
2864 | ||
8f518703 DF |
2865 | spin_lock_irqsave(&mp->lock, flags); |
2866 | ||
1da177e4 LT |
2867 | /* Get the Rx Desc ring 'curr and 'used' indexes */ |
2868 | rx_curr_desc = mp->rx_curr_desc_q; | |
2869 | rx_used_desc = mp->rx_used_desc_q; | |
2870 | ||
2871 | p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc]; | |
2872 | ||
2873 | /* The following parameters are used to save readings from memory */ | |
2874 | command_status = p_rx_desc->cmd_sts; | |
2875 | rmb(); | |
2876 | ||
2877 | /* Nothing to receive... */ | |
8f518703 DF |
2878 | if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { |
2879 | spin_unlock_irqrestore(&mp->lock, flags); | |
1da177e4 | 2880 | return ETH_END_OF_JOB; |
8f518703 | 2881 | } |
1da177e4 LT |
2882 | |
2883 | p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET; | |
2884 | p_pkt_info->cmd_sts = command_status; | |
2885 | p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET; | |
2886 | p_pkt_info->return_info = mp->rx_skb[rx_curr_desc]; | |
2887 | p_pkt_info->l4i_chk = p_rx_desc->buf_size; | |
2888 | ||
2889 | /* Clean the return info field to indicate that the packet has been */ | |
2890 | /* moved to the upper layers */ | |
2891 | mp->rx_skb[rx_curr_desc] = NULL; | |
2892 | ||
2893 | /* Update current index in data structure */ | |
2894 | rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size; | |
2895 | mp->rx_curr_desc_q = rx_next_curr_desc; | |
2896 | ||
2897 | /* Rx descriptors exhausted. Set the Rx ring resource error flag */ | |
2898 | if (rx_next_curr_desc == rx_used_desc) | |
2899 | mp->rx_resource_err = 1; | |
2900 | ||
8f518703 DF |
2901 | spin_unlock_irqrestore(&mp->lock, flags); |
2902 | ||
1da177e4 LT |
2903 | return ETH_OK; |
2904 | } | |
2905 | ||
2906 | /* | |
2907 | * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring. | |
2908 | * | |
2909 | * DESCRIPTION: | |
2910 | * This routine returns a Rx buffer back to the Rx ring. It retrieves the | |
2911 | * next 'used' descriptor and attached the returned buffer to it. | |
2912 | * In case the Rx ring was in "resource error" condition, where there are | |
2913 | * no available Rx resources, the function resets the resource error flag. | |
2914 | * | |
2915 | * INPUT: | |
2916 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
2917 | * struct pkt_info *p_pkt_info Information on returned buffer. | |
2918 | * | |
2919 | * OUTPUT: | |
2920 | * New available Rx resource in Rx descriptor ring. | |
2921 | * | |
2922 | * RETURN: | |
2923 | * ETH_ERROR in case the routine can not access Rx desc ring. | |
2924 | * ETH_OK otherwise. | |
2925 | */ | |
2926 | static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp, | |
2927 | struct pkt_info *p_pkt_info) | |
2928 | { | |
2929 | int used_rx_desc; /* Where to return Rx resource */ | |
2930 | volatile struct eth_rx_desc *p_used_rx_desc; | |
8f518703 DF |
2931 | unsigned long flags; |
2932 | ||
2933 | spin_lock_irqsave(&mp->lock, flags); | |
1da177e4 LT |
2934 | |
2935 | /* Get 'used' Rx descriptor */ | |
2936 | used_rx_desc = mp->rx_used_desc_q; | |
2937 | p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc]; | |
2938 | ||
2939 | p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr; | |
2940 | p_used_rx_desc->buf_size = p_pkt_info->byte_cnt; | |
2941 | mp->rx_skb[used_rx_desc] = p_pkt_info->return_info; | |
2942 | ||
2943 | /* Flush the write pipe */ | |
2944 | ||
2945 | /* Return the descriptor to DMA ownership */ | |
2946 | wmb(); | |
2947 | p_used_rx_desc->cmd_sts = | |
2948 | ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; | |
2949 | wmb(); | |
2950 | ||
2951 | /* Move the used descriptor pointer to the next descriptor */ | |
2952 | mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size; | |
2953 | ||
2954 | /* Any Rx return cancels the Rx resource error status */ | |
2955 | mp->rx_resource_err = 0; | |
2956 | ||
8f518703 DF |
2957 | spin_unlock_irqrestore(&mp->lock, flags); |
2958 | ||
1da177e4 LT |
2959 | return ETH_OK; |
2960 | } | |
2961 | ||
2962 | /************* Begin ethtool support *************************/ | |
2963 | ||
2964 | struct mv643xx_stats { | |
2965 | char stat_string[ETH_GSTRING_LEN]; | |
2966 | int sizeof_stat; | |
2967 | int stat_offset; | |
2968 | }; | |
2969 | ||
2970 | #define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \ | |
2971 | offsetof(struct mv643xx_private, m) | |
2972 | ||
2973 | static const struct mv643xx_stats mv643xx_gstrings_stats[] = { | |
2974 | { "rx_packets", MV643XX_STAT(stats.rx_packets) }, | |
2975 | { "tx_packets", MV643XX_STAT(stats.tx_packets) }, | |
2976 | { "rx_bytes", MV643XX_STAT(stats.rx_bytes) }, | |
2977 | { "tx_bytes", MV643XX_STAT(stats.tx_bytes) }, | |
2978 | { "rx_errors", MV643XX_STAT(stats.rx_errors) }, | |
2979 | { "tx_errors", MV643XX_STAT(stats.tx_errors) }, | |
2980 | { "rx_dropped", MV643XX_STAT(stats.rx_dropped) }, | |
2981 | { "tx_dropped", MV643XX_STAT(stats.tx_dropped) }, | |
2982 | { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) }, | |
2983 | { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) }, | |
2984 | { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) }, | |
2985 | { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) }, | |
2986 | { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) }, | |
2987 | { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) }, | |
2988 | { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) }, | |
2989 | { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) }, | |
2990 | { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) }, | |
2991 | { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) }, | |
2992 | { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) }, | |
2993 | { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) }, | |
2994 | { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) }, | |
2995 | { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) }, | |
2996 | { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) }, | |
2997 | { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) }, | |
2998 | { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) }, | |
2999 | { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) }, | |
3000 | { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) }, | |
3001 | { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) }, | |
3002 | { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) }, | |
3003 | { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) }, | |
3004 | { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) }, | |
3005 | { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) }, | |
3006 | { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) }, | |
3007 | { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) }, | |
3008 | { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) }, | |
3009 | { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) }, | |
3010 | { "collision", MV643XX_STAT(mib_counters.collision) }, | |
3011 | { "late_collision", MV643XX_STAT(mib_counters.late_collision) }, | |
3012 | }; | |
3013 | ||
3014 | #define MV643XX_STATS_LEN \ | |
3015 | sizeof(mv643xx_gstrings_stats) / sizeof(struct mv643xx_stats) | |
3016 | ||
3017 | static int | |
3018 | mv643xx_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) | |
3019 | { | |
3020 | struct mv643xx_private *mp = netdev->priv; | |
3021 | int port_num = mp->port_num; | |
3022 | int autoneg = eth_port_autoneg_supported(port_num); | |
3023 | int mode_10_bit; | |
3024 | int auto_duplex; | |
3025 | int half_duplex = 0; | |
3026 | int full_duplex = 0; | |
3027 | int auto_speed; | |
3028 | int speed_10 = 0; | |
3029 | int speed_100 = 0; | |
3030 | int speed_1000 = 0; | |
3031 | ||
3032 | u32 pcs = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)); | |
3033 | u32 psr = mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num)); | |
3034 | ||
3035 | mode_10_bit = psr & MV643XX_ETH_PORT_STATUS_MODE_10_BIT; | |
3036 | ||
3037 | if (mode_10_bit) { | |
3038 | ecmd->supported = SUPPORTED_10baseT_Half; | |
3039 | } else { | |
3040 | ecmd->supported = (SUPPORTED_10baseT_Half | | |
3041 | SUPPORTED_10baseT_Full | | |
3042 | SUPPORTED_100baseT_Half | | |
3043 | SUPPORTED_100baseT_Full | | |
3044 | SUPPORTED_1000baseT_Full | | |
3045 | (autoneg ? SUPPORTED_Autoneg : 0) | | |
3046 | SUPPORTED_TP); | |
3047 | ||
3048 | auto_duplex = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX); | |
3049 | auto_speed = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII); | |
3050 | ||
3051 | ecmd->advertising = ADVERTISED_TP; | |
3052 | ||
3053 | if (autoneg) { | |
3054 | ecmd->advertising |= ADVERTISED_Autoneg; | |
3055 | ||
3056 | if (auto_duplex) { | |
3057 | half_duplex = 1; | |
3058 | full_duplex = 1; | |
3059 | } else { | |
3060 | if (pcs & MV643XX_ETH_SET_FULL_DUPLEX_MODE) | |
3061 | full_duplex = 1; | |
3062 | else | |
3063 | half_duplex = 1; | |
3064 | } | |
3065 | ||
3066 | if (auto_speed) { | |
3067 | speed_10 = 1; | |
3068 | speed_100 = 1; | |
3069 | speed_1000 = 1; | |
3070 | } else { | |
3071 | if (pcs & MV643XX_ETH_SET_GMII_SPEED_TO_1000) | |
3072 | speed_1000 = 1; | |
3073 | else if (pcs & MV643XX_ETH_SET_MII_SPEED_TO_100) | |
3074 | speed_100 = 1; | |
3075 | else | |
3076 | speed_10 = 1; | |
3077 | } | |
3078 | ||
3079 | if (speed_10 & half_duplex) | |
3080 | ecmd->advertising |= ADVERTISED_10baseT_Half; | |
3081 | if (speed_10 & full_duplex) | |
3082 | ecmd->advertising |= ADVERTISED_10baseT_Full; | |
3083 | if (speed_100 & half_duplex) | |
3084 | ecmd->advertising |= ADVERTISED_100baseT_Half; | |
3085 | if (speed_100 & full_duplex) | |
3086 | ecmd->advertising |= ADVERTISED_100baseT_Full; | |
3087 | if (speed_1000) | |
3088 | ecmd->advertising |= ADVERTISED_1000baseT_Full; | |
3089 | } | |
3090 | } | |
3091 | ||
3092 | ecmd->port = PORT_TP; | |
3093 | ecmd->phy_address = ethernet_phy_get(port_num); | |
3094 | ||
3095 | ecmd->transceiver = XCVR_EXTERNAL; | |
3096 | ||
3097 | if (netif_carrier_ok(netdev)) { | |
3098 | if (mode_10_bit) | |
3099 | ecmd->speed = SPEED_10; | |
3100 | else { | |
3101 | if (psr & MV643XX_ETH_PORT_STATUS_GMII_1000) | |
3102 | ecmd->speed = SPEED_1000; | |
3103 | else if (psr & MV643XX_ETH_PORT_STATUS_MII_100) | |
3104 | ecmd->speed = SPEED_100; | |
3105 | else | |
3106 | ecmd->speed = SPEED_10; | |
3107 | } | |
3108 | ||
3109 | if (psr & MV643XX_ETH_PORT_STATUS_FULL_DUPLEX) | |
3110 | ecmd->duplex = DUPLEX_FULL; | |
3111 | else | |
3112 | ecmd->duplex = DUPLEX_HALF; | |
3113 | } else { | |
3114 | ecmd->speed = -1; | |
3115 | ecmd->duplex = -1; | |
3116 | } | |
3117 | ||
3118 | ecmd->autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE; | |
3119 | return 0; | |
3120 | } | |
3121 | ||
3122 | static void | |
3123 | mv643xx_get_drvinfo(struct net_device *netdev, | |
3124 | struct ethtool_drvinfo *drvinfo) | |
3125 | { | |
3126 | strncpy(drvinfo->driver, mv643xx_driver_name, 32); | |
3127 | strncpy(drvinfo->version, mv643xx_driver_version, 32); | |
3128 | strncpy(drvinfo->fw_version, "N/A", 32); | |
3129 | strncpy(drvinfo->bus_info, "mv643xx", 32); | |
3130 | drvinfo->n_stats = MV643XX_STATS_LEN; | |
3131 | } | |
3132 | ||
3133 | static int | |
3134 | mv643xx_get_stats_count(struct net_device *netdev) | |
3135 | { | |
3136 | return MV643XX_STATS_LEN; | |
3137 | } | |
3138 | ||
3139 | static void | |
3140 | mv643xx_get_ethtool_stats(struct net_device *netdev, | |
3141 | struct ethtool_stats *stats, uint64_t *data) | |
3142 | { | |
3143 | struct mv643xx_private *mp = netdev->priv; | |
3144 | int i; | |
3145 | ||
3146 | eth_update_mib_counters(mp); | |
3147 | ||
3148 | for(i = 0; i < MV643XX_STATS_LEN; i++) { | |
3149 | char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset; | |
3150 | data[i] = (mv643xx_gstrings_stats[i].sizeof_stat == | |
3151 | sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p; | |
3152 | } | |
3153 | } | |
3154 | ||
3155 | static void | |
3156 | mv643xx_get_strings(struct net_device *netdev, uint32_t stringset, uint8_t *data) | |
3157 | { | |
3158 | int i; | |
3159 | ||
3160 | switch(stringset) { | |
3161 | case ETH_SS_STATS: | |
3162 | for (i=0; i < MV643XX_STATS_LEN; i++) { | |
3163 | memcpy(data + i * ETH_GSTRING_LEN, | |
3164 | mv643xx_gstrings_stats[i].stat_string, | |
3165 | ETH_GSTRING_LEN); | |
3166 | } | |
3167 | break; | |
3168 | } | |
3169 | } | |
3170 | ||
3171 | static struct ethtool_ops mv643xx_ethtool_ops = { | |
3172 | .get_settings = mv643xx_get_settings, | |
3173 | .get_drvinfo = mv643xx_get_drvinfo, | |
3174 | .get_link = ethtool_op_get_link, | |
3175 | .get_sg = ethtool_op_get_sg, | |
3176 | .set_sg = ethtool_op_set_sg, | |
3177 | .get_strings = mv643xx_get_strings, | |
3178 | .get_stats_count = mv643xx_get_stats_count, | |
3179 | .get_ethtool_stats = mv643xx_get_ethtool_stats, | |
3180 | }; | |
3181 | ||
3182 | /************* End ethtool support *************************/ |