Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports | |
3 | * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com> | |
4 | * | |
5 | * Based on the 64360 driver from: | |
6 | * Copyright (C) 2002 rabeeh@galileo.co.il | |
7 | * | |
8 | * Copyright (C) 2003 PMC-Sierra, Inc., | |
3bb8a18a | 9 | * written by Manish Lachwani |
1da177e4 LT |
10 | * |
11 | * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> | |
12 | * | |
c8aaea25 | 13 | * Copyright (C) 2004-2006 MontaVista Software, Inc. |
1da177e4 LT |
14 | * Dale Farnsworth <dale@farnsworth.org> |
15 | * | |
16 | * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com> | |
17 | * <sjhill@realitydiluted.com> | |
18 | * | |
19 | * This program is free software; you can redistribute it and/or | |
20 | * modify it under the terms of the GNU General Public License | |
21 | * as published by the Free Software Foundation; either version 2 | |
22 | * of the License, or (at your option) any later version. | |
23 | * | |
24 | * This program is distributed in the hope that it will be useful, | |
25 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
26 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
27 | * GNU General Public License for more details. | |
28 | * | |
29 | * You should have received a copy of the GNU General Public License | |
30 | * along with this program; if not, write to the Free Software | |
31 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
32 | */ | |
33 | #include <linux/init.h> | |
34 | #include <linux/dma-mapping.h> | |
b6298c22 AV |
35 | #include <linux/in.h> |
36 | #include <linux/ip.h> | |
1da177e4 LT |
37 | #include <linux/tcp.h> |
38 | #include <linux/udp.h> | |
39 | #include <linux/etherdevice.h> | |
40 | ||
41 | #include <linux/bitops.h> | |
42 | #include <linux/delay.h> | |
43 | #include <linux/ethtool.h> | |
d052d1be RK |
44 | #include <linux/platform_device.h> |
45 | ||
1da177e4 LT |
46 | #include <asm/io.h> |
47 | #include <asm/types.h> | |
48 | #include <asm/pgtable.h> | |
49 | #include <asm/system.h> | |
50 | #include <asm/delay.h> | |
51 | #include "mv643xx_eth.h" | |
52 | ||
1da177e4 | 53 | /* Static function declarations */ |
144213d7 GP |
54 | static void eth_port_uc_addr_get(unsigned int port_num, unsigned char *p_addr); |
55 | static void eth_port_uc_addr_set(unsigned int port_num, unsigned char *p_addr); | |
16e03018 | 56 | static void eth_port_set_multicast_list(struct net_device *); |
9f8dd319 | 57 | static void mv643xx_eth_port_enable_tx(unsigned int port_num, |
12a87c64 | 58 | unsigned int queues); |
9f8dd319 | 59 | static void mv643xx_eth_port_enable_rx(unsigned int port_num, |
12a87c64 | 60 | unsigned int queues); |
9f8dd319 DF |
61 | static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num); |
62 | static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num); | |
ab4384a6 DF |
63 | static int mv643xx_eth_open(struct net_device *); |
64 | static int mv643xx_eth_stop(struct net_device *); | |
1da177e4 | 65 | static int mv643xx_eth_change_mtu(struct net_device *, int); |
1da177e4 LT |
66 | static void eth_port_init_mac_tables(unsigned int eth_port_num); |
67 | #ifdef MV643XX_NAPI | |
bea3348e | 68 | static int mv643xx_poll(struct napi_struct *napi, int budget); |
1da177e4 | 69 | #endif |
c28a4f89 | 70 | static int ethernet_phy_get(unsigned int eth_port_num); |
1da177e4 LT |
71 | static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr); |
72 | static int ethernet_phy_detect(unsigned int eth_port_num); | |
c28a4f89 JC |
73 | static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location); |
74 | static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val); | |
d0412d96 | 75 | static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); |
7282d491 | 76 | static const struct ethtool_ops mv643xx_ethtool_ops; |
1da177e4 LT |
77 | |
78 | static char mv643xx_driver_name[] = "mv643xx_eth"; | |
79 | static char mv643xx_driver_version[] = "1.0"; | |
80 | ||
81 | static void __iomem *mv643xx_eth_shared_base; | |
82 | ||
83 | /* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */ | |
a9f6a0dd | 84 | static DEFINE_SPINLOCK(mv643xx_eth_phy_lock); |
1da177e4 LT |
85 | |
86 | static inline u32 mv_read(int offset) | |
87 | { | |
dc074a8a | 88 | void __iomem *reg_base; |
1da177e4 LT |
89 | |
90 | reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS; | |
91 | ||
92 | return readl(reg_base + offset); | |
93 | } | |
94 | ||
95 | static inline void mv_write(int offset, u32 data) | |
96 | { | |
dc074a8a | 97 | void __iomem *reg_base; |
1da177e4 LT |
98 | |
99 | reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS; | |
100 | writel(data, reg_base + offset); | |
101 | } | |
102 | ||
103 | /* | |
104 | * Changes MTU (maximum transfer unit) of the gigabit ethenret port | |
105 | * | |
106 | * Input : pointer to ethernet interface network device structure | |
107 | * new mtu size | |
108 | * Output : 0 upon success, -EINVAL upon failure | |
109 | */ | |
110 | static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu) | |
111 | { | |
8f518703 | 112 | if ((new_mtu > 9500) || (new_mtu < 64)) |
1da177e4 | 113 | return -EINVAL; |
1da177e4 LT |
114 | |
115 | dev->mtu = new_mtu; | |
116 | /* | |
117 | * Stop then re-open the interface. This will allocate RX skb's with | |
118 | * the new MTU. | |
119 | * There is a possible danger that the open will not successed, due | |
120 | * to memory is full, which might fail the open function. | |
121 | */ | |
122 | if (netif_running(dev)) { | |
ab4384a6 DF |
123 | mv643xx_eth_stop(dev); |
124 | if (mv643xx_eth_open(dev)) | |
1da177e4 LT |
125 | printk(KERN_ERR |
126 | "%s: Fatal error on opening device\n", | |
127 | dev->name); | |
128 | } | |
129 | ||
1da177e4 LT |
130 | return 0; |
131 | } | |
132 | ||
133 | /* | |
f78fb474 | 134 | * mv643xx_eth_rx_refill_descs |
1da177e4 LT |
135 | * |
136 | * Fills / refills RX queue on a certain gigabit ethernet port | |
137 | * | |
138 | * Input : pointer to ethernet interface network device structure | |
139 | * Output : N/A | |
140 | */ | |
f78fb474 | 141 | static void mv643xx_eth_rx_refill_descs(struct net_device *dev) |
1da177e4 | 142 | { |
1da177e4 LT |
143 | struct mv643xx_private *mp = netdev_priv(dev); |
144 | struct pkt_info pkt_info; | |
145 | struct sk_buff *skb; | |
b44cd572 | 146 | int unaligned; |
1da177e4 | 147 | |
f78fb474 | 148 | while (mp->rx_desc_count < mp->rx_ring_size) { |
908b637f | 149 | skb = dev_alloc_skb(ETH_RX_SKB_SIZE + dma_get_cache_alignment()); |
1da177e4 LT |
150 | if (!skb) |
151 | break; | |
f98e36f1 | 152 | mp->rx_desc_count++; |
908b637f | 153 | unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1); |
b44cd572 | 154 | if (unaligned) |
908b637f | 155 | skb_reserve(skb, dma_get_cache_alignment() - unaligned); |
1da177e4 | 156 | pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT; |
7303fde8 DF |
157 | pkt_info.byte_cnt = ETH_RX_SKB_SIZE; |
158 | pkt_info.buf_ptr = dma_map_single(NULL, skb->data, | |
159 | ETH_RX_SKB_SIZE, DMA_FROM_DEVICE); | |
1da177e4 LT |
160 | pkt_info.return_info = skb; |
161 | if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) { | |
162 | printk(KERN_ERR | |
163 | "%s: Error allocating RX Ring\n", dev->name); | |
164 | break; | |
165 | } | |
7303fde8 | 166 | skb_reserve(skb, ETH_HW_IP_ALIGN); |
1da177e4 | 167 | } |
1da177e4 LT |
168 | /* |
169 | * If RX ring is empty of SKB, set a timer to try allocating | |
f78fb474 | 170 | * again at a later time. |
1da177e4 | 171 | */ |
f78fb474 | 172 | if (mp->rx_desc_count == 0) { |
1da177e4 | 173 | printk(KERN_INFO "%s: Rx ring is empty\n", dev->name); |
f78fb474 | 174 | mp->timeout.expires = jiffies + (HZ / 10); /* 100 mSec */ |
1da177e4 | 175 | add_timer(&mp->timeout); |
1da177e4 | 176 | } |
1da177e4 LT |
177 | } |
178 | ||
179 | /* | |
f78fb474 | 180 | * mv643xx_eth_rx_refill_descs_timer_wrapper |
1da177e4 LT |
181 | * |
182 | * Timer routine to wake up RX queue filling task. This function is | |
183 | * used only in case the RX queue is empty, and all alloc_skb has | |
184 | * failed (due to out of memory event). | |
185 | * | |
186 | * Input : pointer to ethernet interface network device structure | |
187 | * Output : N/A | |
188 | */ | |
f78fb474 | 189 | static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data) |
1da177e4 | 190 | { |
f78fb474 | 191 | mv643xx_eth_rx_refill_descs((struct net_device *)data); |
1da177e4 LT |
192 | } |
193 | ||
194 | /* | |
195 | * mv643xx_eth_update_mac_address | |
196 | * | |
197 | * Update the MAC address of the port in the address table | |
198 | * | |
199 | * Input : pointer to ethernet interface network device structure | |
200 | * Output : N/A | |
201 | */ | |
202 | static void mv643xx_eth_update_mac_address(struct net_device *dev) | |
203 | { | |
204 | struct mv643xx_private *mp = netdev_priv(dev); | |
205 | unsigned int port_num = mp->port_num; | |
206 | ||
207 | eth_port_init_mac_tables(port_num); | |
ed9b5d45 | 208 | eth_port_uc_addr_set(port_num, dev->dev_addr); |
1da177e4 LT |
209 | } |
210 | ||
211 | /* | |
212 | * mv643xx_eth_set_rx_mode | |
213 | * | |
214 | * Change from promiscuos to regular rx mode | |
215 | * | |
216 | * Input : pointer to ethernet interface network device structure | |
217 | * Output : N/A | |
218 | */ | |
219 | static void mv643xx_eth_set_rx_mode(struct net_device *dev) | |
220 | { | |
221 | struct mv643xx_private *mp = netdev_priv(dev); | |
01999873 | 222 | u32 config_reg; |
1da177e4 | 223 | |
01999873 | 224 | config_reg = mv_read(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num)); |
1da177e4 | 225 | if (dev->flags & IFF_PROMISC) |
01999873 | 226 | config_reg |= (u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE; |
1da177e4 | 227 | else |
01999873 DF |
228 | config_reg &= ~(u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE; |
229 | mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num), config_reg); | |
16e03018 DF |
230 | |
231 | eth_port_set_multicast_list(dev); | |
1da177e4 LT |
232 | } |
233 | ||
234 | /* | |
235 | * mv643xx_eth_set_mac_address | |
236 | * | |
237 | * Change the interface's mac address. | |
238 | * No special hardware thing should be done because interface is always | |
239 | * put in promiscuous mode. | |
240 | * | |
241 | * Input : pointer to ethernet interface network device structure and | |
242 | * a pointer to the designated entry to be added to the cache. | |
243 | * Output : zero upon success, negative upon failure | |
244 | */ | |
245 | static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr) | |
246 | { | |
247 | int i; | |
248 | ||
249 | for (i = 0; i < 6; i++) | |
250 | /* +2 is for the offset of the HW addr type */ | |
251 | dev->dev_addr[i] = ((unsigned char *)addr)[i + 2]; | |
252 | mv643xx_eth_update_mac_address(dev); | |
253 | return 0; | |
254 | } | |
255 | ||
256 | /* | |
257 | * mv643xx_eth_tx_timeout | |
258 | * | |
259 | * Called upon a timeout on transmitting a packet | |
260 | * | |
261 | * Input : pointer to ethernet interface network device structure. | |
262 | * Output : N/A | |
263 | */ | |
264 | static void mv643xx_eth_tx_timeout(struct net_device *dev) | |
265 | { | |
266 | struct mv643xx_private *mp = netdev_priv(dev); | |
267 | ||
268 | printk(KERN_INFO "%s: TX timeout ", dev->name); | |
269 | ||
270 | /* Do the reset outside of interrupt context */ | |
271 | schedule_work(&mp->tx_timeout_task); | |
272 | } | |
273 | ||
274 | /* | |
275 | * mv643xx_eth_tx_timeout_task | |
276 | * | |
277 | * Actual routine to reset the adapter when a timeout on Tx has occurred | |
278 | */ | |
91c7c568 | 279 | static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly) |
1da177e4 | 280 | { |
91c7c568 AV |
281 | struct mv643xx_private *mp = container_of(ugly, struct mv643xx_private, |
282 | tx_timeout_task); | |
283 | struct net_device *dev = mp->mii.dev; /* yuck */ | |
1da177e4 | 284 | |
94843566 DF |
285 | if (!netif_running(dev)) |
286 | return; | |
287 | ||
288 | netif_stop_queue(dev); | |
289 | ||
1da177e4 | 290 | eth_port_reset(mp->port_num); |
ed9b5d45 | 291 | eth_port_start(dev); |
94843566 DF |
292 | |
293 | if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB) | |
294 | netif_wake_queue(dev); | |
1da177e4 LT |
295 | } |
296 | ||
ff561eef DF |
297 | /** |
298 | * mv643xx_eth_free_tx_descs - Free the tx desc data for completed descriptors | |
1da177e4 | 299 | * |
ff561eef | 300 | * If force is non-zero, frees uncompleted descriptors as well |
1da177e4 | 301 | */ |
ff561eef | 302 | int mv643xx_eth_free_tx_descs(struct net_device *dev, int force) |
1da177e4 LT |
303 | { |
304 | struct mv643xx_private *mp = netdev_priv(dev); | |
ff561eef DF |
305 | struct eth_tx_desc *desc; |
306 | u32 cmd_sts; | |
307 | struct sk_buff *skb; | |
308 | unsigned long flags; | |
309 | int tx_index; | |
310 | dma_addr_t addr; | |
311 | int count; | |
312 | int released = 0; | |
1da177e4 | 313 | |
ff561eef DF |
314 | while (mp->tx_desc_count > 0) { |
315 | spin_lock_irqsave(&mp->lock, flags); | |
d344bff9 DF |
316 | |
317 | /* tx_desc_count might have changed before acquiring the lock */ | |
318 | if (mp->tx_desc_count <= 0) { | |
319 | spin_unlock_irqrestore(&mp->lock, flags); | |
320 | return released; | |
321 | } | |
322 | ||
ff561eef DF |
323 | tx_index = mp->tx_used_desc_q; |
324 | desc = &mp->p_tx_desc_area[tx_index]; | |
325 | cmd_sts = desc->cmd_sts; | |
326 | ||
327 | if (!force && (cmd_sts & ETH_BUFFER_OWNED_BY_DMA)) { | |
328 | spin_unlock_irqrestore(&mp->lock, flags); | |
329 | return released; | |
330 | } | |
331 | ||
332 | mp->tx_used_desc_q = (tx_index + 1) % mp->tx_ring_size; | |
333 | mp->tx_desc_count--; | |
334 | ||
335 | addr = desc->buf_ptr; | |
336 | count = desc->byte_cnt; | |
337 | skb = mp->tx_skb[tx_index]; | |
338 | if (skb) | |
339 | mp->tx_skb[tx_index] = NULL; | |
340 | ||
7303fde8 | 341 | if (cmd_sts & ETH_ERROR_SUMMARY) { |
1da177e4 | 342 | printk("%s: Error in TX\n", dev->name); |
09f75cd7 | 343 | dev->stats.tx_errors++; |
1da177e4 LT |
344 | } |
345 | ||
d344bff9 DF |
346 | spin_unlock_irqrestore(&mp->lock, flags); |
347 | ||
ff561eef DF |
348 | if (cmd_sts & ETH_TX_FIRST_DESC) |
349 | dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE); | |
cb415d30 | 350 | else |
ff561eef | 351 | dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE); |
1da177e4 | 352 | |
ff561eef DF |
353 | if (skb) |
354 | dev_kfree_skb_irq(skb); | |
355 | ||
356 | released = 1; | |
1da177e4 LT |
357 | } |
358 | ||
1da177e4 LT |
359 | return released; |
360 | } | |
361 | ||
ff561eef DF |
362 | static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev) |
363 | { | |
364 | struct mv643xx_private *mp = netdev_priv(dev); | |
365 | ||
366 | if (mv643xx_eth_free_tx_descs(dev, 0) && | |
367 | mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB) | |
368 | netif_wake_queue(dev); | |
369 | } | |
370 | ||
371 | static void mv643xx_eth_free_all_tx_descs(struct net_device *dev) | |
372 | { | |
373 | mv643xx_eth_free_tx_descs(dev, 1); | |
374 | } | |
375 | ||
1da177e4 LT |
376 | /* |
377 | * mv643xx_eth_receive | |
378 | * | |
379 | * This function is forward packets that are received from the port's | |
380 | * queues toward kernel core or FastRoute them to another interface. | |
381 | * | |
382 | * Input : dev - a pointer to the required interface | |
383 | * max - maximum number to receive (0 means unlimted) | |
384 | * | |
385 | * Output : number of served packets | |
386 | */ | |
1da177e4 | 387 | static int mv643xx_eth_receive_queue(struct net_device *dev, int budget) |
1da177e4 LT |
388 | { |
389 | struct mv643xx_private *mp = netdev_priv(dev); | |
09f75cd7 | 390 | struct net_device_stats *stats = &dev->stats; |
1da177e4 LT |
391 | unsigned int received_packets = 0; |
392 | struct sk_buff *skb; | |
393 | struct pkt_info pkt_info; | |
394 | ||
b1dd9ca1 | 395 | while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) { |
54caf44d | 396 | dma_unmap_single(NULL, pkt_info.buf_ptr, ETH_RX_SKB_SIZE, |
71d28725 | 397 | DMA_FROM_DEVICE); |
f98e36f1 | 398 | mp->rx_desc_count--; |
1da177e4 | 399 | received_packets++; |
b1dd9ca1 | 400 | |
468d09f8 DF |
401 | /* |
402 | * Update statistics. | |
403 | * Note byte count includes 4 byte CRC count | |
404 | */ | |
1da177e4 LT |
405 | stats->rx_packets++; |
406 | stats->rx_bytes += pkt_info.byte_cnt; | |
407 | skb = pkt_info.return_info; | |
408 | /* | |
409 | * In case received a packet without first / last bits on OR | |
410 | * the error summary bit is on, the packets needs to be dropeed. | |
411 | */ | |
412 | if (((pkt_info.cmd_sts | |
413 | & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) != | |
414 | (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) | |
415 | || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) { | |
416 | stats->rx_dropped++; | |
417 | if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC | | |
418 | ETH_RX_LAST_DESC)) != | |
419 | (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) { | |
420 | if (net_ratelimit()) | |
421 | printk(KERN_ERR | |
422 | "%s: Received packet spread " | |
423 | "on multiple descriptors\n", | |
424 | dev->name); | |
425 | } | |
426 | if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) | |
427 | stats->rx_errors++; | |
428 | ||
429 | dev_kfree_skb_irq(skb); | |
430 | } else { | |
431 | /* | |
432 | * The -4 is for the CRC in the trailer of the | |
433 | * received packet | |
434 | */ | |
435 | skb_put(skb, pkt_info.byte_cnt - 4); | |
1da177e4 LT |
436 | |
437 | if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) { | |
438 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
439 | skb->csum = htons( | |
440 | (pkt_info.cmd_sts & 0x0007fff8) >> 3); | |
441 | } | |
442 | skb->protocol = eth_type_trans(skb, dev); | |
443 | #ifdef MV643XX_NAPI | |
444 | netif_receive_skb(skb); | |
445 | #else | |
446 | netif_rx(skb); | |
447 | #endif | |
448 | } | |
12ad74f8 | 449 | dev->last_rx = jiffies; |
1da177e4 | 450 | } |
f78fb474 | 451 | mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */ |
1da177e4 LT |
452 | |
453 | return received_packets; | |
454 | } | |
455 | ||
d0412d96 JC |
456 | /* Set the mv643xx port configuration register for the speed/duplex mode. */ |
457 | static void mv643xx_eth_update_pscr(struct net_device *dev, | |
458 | struct ethtool_cmd *ecmd) | |
459 | { | |
460 | struct mv643xx_private *mp = netdev_priv(dev); | |
461 | int port_num = mp->port_num; | |
462 | u32 o_pscr, n_pscr; | |
12a87c64 | 463 | unsigned int queues; |
d0412d96 JC |
464 | |
465 | o_pscr = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)); | |
466 | n_pscr = o_pscr; | |
467 | ||
468 | /* clear speed, duplex and rx buffer size fields */ | |
469 | n_pscr &= ~(MV643XX_ETH_SET_MII_SPEED_TO_100 | | |
470 | MV643XX_ETH_SET_GMII_SPEED_TO_1000 | | |
471 | MV643XX_ETH_SET_FULL_DUPLEX_MODE | | |
472 | MV643XX_ETH_MAX_RX_PACKET_MASK); | |
473 | ||
474 | if (ecmd->duplex == DUPLEX_FULL) | |
475 | n_pscr |= MV643XX_ETH_SET_FULL_DUPLEX_MODE; | |
476 | ||
477 | if (ecmd->speed == SPEED_1000) | |
478 | n_pscr |= MV643XX_ETH_SET_GMII_SPEED_TO_1000 | | |
479 | MV643XX_ETH_MAX_RX_PACKET_9700BYTE; | |
480 | else { | |
481 | if (ecmd->speed == SPEED_100) | |
482 | n_pscr |= MV643XX_ETH_SET_MII_SPEED_TO_100; | |
483 | n_pscr |= MV643XX_ETH_MAX_RX_PACKET_1522BYTE; | |
484 | } | |
485 | ||
486 | if (n_pscr != o_pscr) { | |
487 | if ((o_pscr & MV643XX_ETH_SERIAL_PORT_ENABLE) == 0) | |
488 | mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), | |
489 | n_pscr); | |
490 | else { | |
12a87c64 | 491 | queues = mv643xx_eth_port_disable_tx(port_num); |
d0412d96 JC |
492 | |
493 | o_pscr &= ~MV643XX_ETH_SERIAL_PORT_ENABLE; | |
494 | mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), | |
495 | o_pscr); | |
496 | mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), | |
497 | n_pscr); | |
498 | mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), | |
499 | n_pscr); | |
12a87c64 DF |
500 | if (queues) |
501 | mv643xx_eth_port_enable_tx(port_num, queues); | |
d0412d96 JC |
502 | } |
503 | } | |
504 | } | |
505 | ||
1da177e4 LT |
506 | /* |
507 | * mv643xx_eth_int_handler | |
508 | * | |
509 | * Main interrupt handler for the gigbit ethernet ports | |
510 | * | |
511 | * Input : irq - irq number (not used) | |
512 | * dev_id - a pointer to the required interface's data structure | |
513 | * regs - not used | |
514 | * Output : N/A | |
515 | */ | |
516 | ||
7d12e780 | 517 | static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id) |
1da177e4 LT |
518 | { |
519 | struct net_device *dev = (struct net_device *)dev_id; | |
520 | struct mv643xx_private *mp = netdev_priv(dev); | |
521 | u32 eth_int_cause, eth_int_cause_ext = 0; | |
522 | unsigned int port_num = mp->port_num; | |
523 | ||
524 | /* Read interrupt cause registers */ | |
525 | eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) & | |
7303fde8 | 526 | ETH_INT_UNMASK_ALL; |
468d09f8 | 527 | if (eth_int_cause & ETH_INT_CAUSE_EXT) { |
1da177e4 LT |
528 | eth_int_cause_ext = mv_read( |
529 | MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) & | |
7303fde8 | 530 | ETH_INT_UNMASK_ALL_EXT; |
468d09f8 DF |
531 | mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), |
532 | ~eth_int_cause_ext); | |
1da177e4 | 533 | } |
7303fde8 | 534 | |
1da177e4 | 535 | /* PHY status changed */ |
2bcff60f | 536 | if (eth_int_cause_ext & (ETH_INT_CAUSE_PHY | ETH_INT_CAUSE_STATE)) { |
d0412d96 JC |
537 | struct ethtool_cmd cmd; |
538 | ||
c28a4f89 | 539 | if (mii_link_ok(&mp->mii)) { |
d0412d96 JC |
540 | mii_ethtool_gset(&mp->mii, &cmd); |
541 | mv643xx_eth_update_pscr(dev, &cmd); | |
ff561eef DF |
542 | mv643xx_eth_port_enable_tx(port_num, |
543 | ETH_TX_QUEUES_ENABLED); | |
c28a4f89 JC |
544 | if (!netif_carrier_ok(dev)) { |
545 | netif_carrier_on(dev); | |
ff561eef DF |
546 | if (mp->tx_ring_size - mp->tx_desc_count >= |
547 | MAX_DESCS_PER_SKB) | |
d0412d96 | 548 | netif_wake_queue(dev); |
c28a4f89 JC |
549 | } |
550 | } else if (netif_carrier_ok(dev)) { | |
1da177e4 | 551 | netif_stop_queue(dev); |
c28a4f89 | 552 | netif_carrier_off(dev); |
1da177e4 LT |
553 | } |
554 | } | |
555 | ||
468d09f8 DF |
556 | #ifdef MV643XX_NAPI |
557 | if (eth_int_cause & ETH_INT_CAUSE_RX) { | |
558 | /* schedule the NAPI poll routine to maintain port */ | |
559 | mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), | |
560 | ETH_INT_MASK_ALL); | |
561 | /* wait for previous write to complete */ | |
562 | mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num)); | |
563 | ||
bea3348e | 564 | netif_rx_schedule(dev, &mp->napi); |
468d09f8 DF |
565 | } |
566 | #else | |
567 | if (eth_int_cause & ETH_INT_CAUSE_RX) | |
568 | mv643xx_eth_receive_queue(dev, INT_MAX); | |
5c537408 | 569 | #endif |
468d09f8 DF |
570 | if (eth_int_cause_ext & ETH_INT_CAUSE_TX) |
571 | mv643xx_eth_free_completed_tx_descs(dev); | |
468d09f8 | 572 | |
1da177e4 LT |
573 | /* |
574 | * If no real interrupt occured, exit. | |
575 | * This can happen when using gigE interrupt coalescing mechanism. | |
576 | */ | |
577 | if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0)) | |
578 | return IRQ_NONE; | |
579 | ||
580 | return IRQ_HANDLED; | |
581 | } | |
582 | ||
583 | #ifdef MV643XX_COAL | |
584 | ||
585 | /* | |
586 | * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path | |
587 | * | |
588 | * DESCRIPTION: | |
589 | * This routine sets the RX coalescing interrupt mechanism parameter. | |
590 | * This parameter is a timeout counter, that counts in 64 t_clk | |
591 | * chunks ; that when timeout event occurs a maskable interrupt | |
592 | * occurs. | |
593 | * The parameter is calculated using the tClk of the MV-643xx chip | |
594 | * , and the required delay of the interrupt in usec. | |
595 | * | |
596 | * INPUT: | |
597 | * unsigned int eth_port_num Ethernet port number | |
598 | * unsigned int t_clk t_clk of the MV-643xx chip in HZ units | |
599 | * unsigned int delay Delay in usec | |
600 | * | |
601 | * OUTPUT: | |
602 | * Interrupt coalescing mechanism value is set in MV-643xx chip. | |
603 | * | |
604 | * RETURN: | |
605 | * The interrupt coalescing value set in the gigE port. | |
606 | * | |
607 | */ | |
608 | static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num, | |
609 | unsigned int t_clk, unsigned int delay) | |
610 | { | |
611 | unsigned int coal = ((t_clk / 1000000) * delay) / 64; | |
612 | ||
613 | /* Set RX Coalescing mechanism */ | |
614 | mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num), | |
615 | ((coal & 0x3fff) << 8) | | |
616 | (mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num)) | |
617 | & 0xffc000ff)); | |
618 | ||
619 | return coal; | |
620 | } | |
621 | #endif | |
622 | ||
623 | /* | |
624 | * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path | |
625 | * | |
626 | * DESCRIPTION: | |
627 | * This routine sets the TX coalescing interrupt mechanism parameter. | |
628 | * This parameter is a timeout counter, that counts in 64 t_clk | |
629 | * chunks ; that when timeout event occurs a maskable interrupt | |
630 | * occurs. | |
631 | * The parameter is calculated using the t_cLK frequency of the | |
632 | * MV-643xx chip and the required delay in the interrupt in uSec | |
633 | * | |
634 | * INPUT: | |
635 | * unsigned int eth_port_num Ethernet port number | |
636 | * unsigned int t_clk t_clk of the MV-643xx chip in HZ units | |
637 | * unsigned int delay Delay in uSeconds | |
638 | * | |
639 | * OUTPUT: | |
640 | * Interrupt coalescing mechanism value is set in MV-643xx chip. | |
641 | * | |
642 | * RETURN: | |
643 | * The interrupt coalescing value set in the gigE port. | |
644 | * | |
645 | */ | |
646 | static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num, | |
647 | unsigned int t_clk, unsigned int delay) | |
648 | { | |
649 | unsigned int coal; | |
650 | coal = ((t_clk / 1000000) * delay) / 64; | |
651 | /* Set TX Coalescing mechanism */ | |
652 | mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num), | |
653 | coal << 4); | |
654 | return coal; | |
655 | } | |
656 | ||
1da177e4 LT |
657 | /* |
658 | * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. | |
659 | * | |
660 | * DESCRIPTION: | |
661 | * This function prepares a Rx chained list of descriptors and packet | |
662 | * buffers in a form of a ring. The routine must be called after port | |
663 | * initialization routine and before port start routine. | |
664 | * The Ethernet SDMA engine uses CPU bus addresses to access the various | |
665 | * devices in the system (i.e. DRAM). This function uses the ethernet | |
666 | * struct 'virtual to physical' routine (set by the user) to set the ring | |
667 | * with physical addresses. | |
668 | * | |
669 | * INPUT: | |
670 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
671 | * | |
672 | * OUTPUT: | |
673 | * The routine updates the Ethernet port control struct with information | |
674 | * regarding the Rx descriptors and buffers. | |
675 | * | |
676 | * RETURN: | |
677 | * None. | |
678 | */ | |
679 | static void ether_init_rx_desc_ring(struct mv643xx_private *mp) | |
680 | { | |
681 | volatile struct eth_rx_desc *p_rx_desc; | |
682 | int rx_desc_num = mp->rx_ring_size; | |
683 | int i; | |
684 | ||
685 | /* initialize the next_desc_ptr links in the Rx descriptors ring */ | |
686 | p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area; | |
687 | for (i = 0; i < rx_desc_num; i++) { | |
688 | p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma + | |
689 | ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc); | |
690 | } | |
691 | ||
692 | /* Save Rx desc pointer to driver struct. */ | |
693 | mp->rx_curr_desc_q = 0; | |
694 | mp->rx_used_desc_q = 0; | |
695 | ||
696 | mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc); | |
1da177e4 LT |
697 | } |
698 | ||
699 | /* | |
700 | * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory. | |
701 | * | |
702 | * DESCRIPTION: | |
703 | * This function prepares a Tx chained list of descriptors and packet | |
704 | * buffers in a form of a ring. The routine must be called after port | |
705 | * initialization routine and before port start routine. | |
706 | * The Ethernet SDMA engine uses CPU bus addresses to access the various | |
707 | * devices in the system (i.e. DRAM). This function uses the ethernet | |
708 | * struct 'virtual to physical' routine (set by the user) to set the ring | |
709 | * with physical addresses. | |
710 | * | |
711 | * INPUT: | |
712 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
713 | * | |
714 | * OUTPUT: | |
715 | * The routine updates the Ethernet port control struct with information | |
716 | * regarding the Tx descriptors and buffers. | |
717 | * | |
718 | * RETURN: | |
719 | * None. | |
720 | */ | |
721 | static void ether_init_tx_desc_ring(struct mv643xx_private *mp) | |
722 | { | |
723 | int tx_desc_num = mp->tx_ring_size; | |
724 | struct eth_tx_desc *p_tx_desc; | |
725 | int i; | |
726 | ||
727 | /* Initialize the next_desc_ptr links in the Tx descriptors ring */ | |
728 | p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area; | |
729 | for (i = 0; i < tx_desc_num; i++) { | |
730 | p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma + | |
731 | ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc); | |
732 | } | |
733 | ||
734 | mp->tx_curr_desc_q = 0; | |
735 | mp->tx_used_desc_q = 0; | |
1da177e4 LT |
736 | |
737 | mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc); | |
1da177e4 LT |
738 | } |
739 | ||
d0412d96 JC |
740 | static int mv643xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
741 | { | |
742 | struct mv643xx_private *mp = netdev_priv(dev); | |
743 | int err; | |
744 | ||
745 | spin_lock_irq(&mp->lock); | |
746 | err = mii_ethtool_sset(&mp->mii, cmd); | |
747 | spin_unlock_irq(&mp->lock); | |
748 | ||
749 | return err; | |
750 | } | |
751 | ||
752 | static int mv643xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
753 | { | |
754 | struct mv643xx_private *mp = netdev_priv(dev); | |
755 | int err; | |
756 | ||
757 | spin_lock_irq(&mp->lock); | |
758 | err = mii_ethtool_gset(&mp->mii, cmd); | |
759 | spin_unlock_irq(&mp->lock); | |
760 | ||
761 | /* The PHY may support 1000baseT_Half, but the mv643xx does not */ | |
762 | cmd->supported &= ~SUPPORTED_1000baseT_Half; | |
763 | cmd->advertising &= ~ADVERTISED_1000baseT_Half; | |
764 | ||
765 | return err; | |
766 | } | |
767 | ||
ab4384a6 DF |
768 | /* |
769 | * mv643xx_eth_open | |
770 | * | |
771 | * This function is called when openning the network device. The function | |
772 | * should initialize all the hardware, initialize cyclic Rx/Tx | |
773 | * descriptors chain and buffers and allocate an IRQ to the network | |
774 | * device. | |
775 | * | |
776 | * Input : a pointer to the network device structure | |
777 | * | |
778 | * Output : zero of success , nonzero if fails. | |
779 | */ | |
780 | ||
781 | static int mv643xx_eth_open(struct net_device *dev) | |
1da177e4 LT |
782 | { |
783 | struct mv643xx_private *mp = netdev_priv(dev); | |
784 | unsigned int port_num = mp->port_num; | |
785 | unsigned int size; | |
ab4384a6 | 786 | int err; |
0795af57 | 787 | DECLARE_MAC_BUF(mac); |
ab4384a6 | 788 | |
85cf572c DF |
789 | /* Clear any pending ethernet port interrupts */ |
790 | mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0); | |
791 | mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0); | |
792 | /* wait for previous write to complete */ | |
793 | mv_read (MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)); | |
794 | ||
ab4384a6 | 795 | err = request_irq(dev->irq, mv643xx_eth_int_handler, |
1fb9df5d | 796 | IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev); |
ab4384a6 DF |
797 | if (err) { |
798 | printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n", | |
799 | port_num); | |
800 | return -EAGAIN; | |
801 | } | |
1da177e4 | 802 | |
1da177e4 LT |
803 | eth_port_init(mp); |
804 | ||
1da177e4 | 805 | memset(&mp->timeout, 0, sizeof(struct timer_list)); |
f78fb474 | 806 | mp->timeout.function = mv643xx_eth_rx_refill_descs_timer_wrapper; |
1da177e4 LT |
807 | mp->timeout.data = (unsigned long)dev; |
808 | ||
1da177e4 LT |
809 | /* Allocate RX and TX skb rings */ |
810 | mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size, | |
811 | GFP_KERNEL); | |
812 | if (!mp->rx_skb) { | |
813 | printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name); | |
ab4384a6 DF |
814 | err = -ENOMEM; |
815 | goto out_free_irq; | |
1da177e4 LT |
816 | } |
817 | mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size, | |
818 | GFP_KERNEL); | |
819 | if (!mp->tx_skb) { | |
820 | printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name); | |
ab4384a6 DF |
821 | err = -ENOMEM; |
822 | goto out_free_rx_skb; | |
1da177e4 LT |
823 | } |
824 | ||
825 | /* Allocate TX ring */ | |
f98e36f1 | 826 | mp->tx_desc_count = 0; |
1da177e4 LT |
827 | size = mp->tx_ring_size * sizeof(struct eth_tx_desc); |
828 | mp->tx_desc_area_size = size; | |
829 | ||
830 | if (mp->tx_sram_size) { | |
831 | mp->p_tx_desc_area = ioremap(mp->tx_sram_addr, | |
832 | mp->tx_sram_size); | |
833 | mp->tx_desc_dma = mp->tx_sram_addr; | |
834 | } else | |
835 | mp->p_tx_desc_area = dma_alloc_coherent(NULL, size, | |
836 | &mp->tx_desc_dma, | |
837 | GFP_KERNEL); | |
838 | ||
839 | if (!mp->p_tx_desc_area) { | |
840 | printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n", | |
841 | dev->name, size); | |
ab4384a6 DF |
842 | err = -ENOMEM; |
843 | goto out_free_tx_skb; | |
1da177e4 LT |
844 | } |
845 | BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */ | |
846 | memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size); | |
847 | ||
848 | ether_init_tx_desc_ring(mp); | |
849 | ||
850 | /* Allocate RX ring */ | |
f98e36f1 | 851 | mp->rx_desc_count = 0; |
1da177e4 LT |
852 | size = mp->rx_ring_size * sizeof(struct eth_rx_desc); |
853 | mp->rx_desc_area_size = size; | |
854 | ||
855 | if (mp->rx_sram_size) { | |
856 | mp->p_rx_desc_area = ioremap(mp->rx_sram_addr, | |
857 | mp->rx_sram_size); | |
858 | mp->rx_desc_dma = mp->rx_sram_addr; | |
859 | } else | |
860 | mp->p_rx_desc_area = dma_alloc_coherent(NULL, size, | |
861 | &mp->rx_desc_dma, | |
862 | GFP_KERNEL); | |
863 | ||
864 | if (!mp->p_rx_desc_area) { | |
865 | printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n", | |
866 | dev->name, size); | |
867 | printk(KERN_ERR "%s: Freeing previously allocated TX queues...", | |
868 | dev->name); | |
869 | if (mp->rx_sram_size) | |
dd09b1de | 870 | iounmap(mp->p_tx_desc_area); |
1da177e4 LT |
871 | else |
872 | dma_free_coherent(NULL, mp->tx_desc_area_size, | |
873 | mp->p_tx_desc_area, mp->tx_desc_dma); | |
ab4384a6 DF |
874 | err = -ENOMEM; |
875 | goto out_free_tx_skb; | |
1da177e4 LT |
876 | } |
877 | memset((void *)mp->p_rx_desc_area, 0, size); | |
878 | ||
879 | ether_init_rx_desc_ring(mp); | |
880 | ||
f78fb474 | 881 | mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */ |
1da177e4 | 882 | |
bea3348e SH |
883 | #ifdef MV643XX_NAPI |
884 | napi_enable(&mp->napi); | |
885 | #endif | |
886 | ||
ed9b5d45 | 887 | eth_port_start(dev); |
1da177e4 LT |
888 | |
889 | /* Interrupt Coalescing */ | |
890 | ||
891 | #ifdef MV643XX_COAL | |
892 | mp->rx_int_coal = | |
893 | eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL); | |
894 | #endif | |
895 | ||
896 | mp->tx_int_coal = | |
897 | eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL); | |
898 | ||
8f518703 DF |
899 | /* Unmask phy and link status changes interrupts */ |
900 | mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num), | |
7303fde8 | 901 | ETH_INT_UNMASK_ALL_EXT); |
1da177e4 | 902 | |
8f518703 | 903 | /* Unmask RX buffer and TX end interrupt */ |
7303fde8 | 904 | mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL); |
d0412d96 | 905 | |
1da177e4 | 906 | return 0; |
ab4384a6 DF |
907 | |
908 | out_free_tx_skb: | |
909 | kfree(mp->tx_skb); | |
910 | out_free_rx_skb: | |
911 | kfree(mp->rx_skb); | |
912 | out_free_irq: | |
913 | free_irq(dev->irq, dev); | |
914 | ||
915 | return err; | |
1da177e4 LT |
916 | } |
917 | ||
918 | static void mv643xx_eth_free_tx_rings(struct net_device *dev) | |
919 | { | |
920 | struct mv643xx_private *mp = netdev_priv(dev); | |
1da177e4 LT |
921 | |
922 | /* Stop Tx Queues */ | |
ff561eef | 923 | mv643xx_eth_port_disable_tx(mp->port_num); |
1da177e4 | 924 | |
ff561eef DF |
925 | /* Free outstanding skb's on TX ring */ |
926 | mv643xx_eth_free_all_tx_descs(dev); | |
927 | ||
928 | BUG_ON(mp->tx_used_desc_q != mp->tx_curr_desc_q); | |
1da177e4 LT |
929 | |
930 | /* Free TX ring */ | |
931 | if (mp->tx_sram_size) | |
932 | iounmap(mp->p_tx_desc_area); | |
933 | else | |
934 | dma_free_coherent(NULL, mp->tx_desc_area_size, | |
935 | mp->p_tx_desc_area, mp->tx_desc_dma); | |
936 | } | |
937 | ||
938 | static void mv643xx_eth_free_rx_rings(struct net_device *dev) | |
939 | { | |
940 | struct mv643xx_private *mp = netdev_priv(dev); | |
941 | unsigned int port_num = mp->port_num; | |
942 | int curr; | |
943 | ||
944 | /* Stop RX Queues */ | |
9f8dd319 | 945 | mv643xx_eth_port_disable_rx(port_num); |
1da177e4 LT |
946 | |
947 | /* Free preallocated skb's on RX rings */ | |
f98e36f1 | 948 | for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) { |
1da177e4 LT |
949 | if (mp->rx_skb[curr]) { |
950 | dev_kfree_skb(mp->rx_skb[curr]); | |
f98e36f1 | 951 | mp->rx_desc_count--; |
1da177e4 LT |
952 | } |
953 | } | |
954 | ||
f98e36f1 | 955 | if (mp->rx_desc_count) |
1da177e4 LT |
956 | printk(KERN_ERR |
957 | "%s: Error in freeing Rx Ring. %d skb's still" | |
958 | " stuck in RX Ring - ignoring them\n", dev->name, | |
f98e36f1 | 959 | mp->rx_desc_count); |
1da177e4 LT |
960 | /* Free RX ring */ |
961 | if (mp->rx_sram_size) | |
962 | iounmap(mp->p_rx_desc_area); | |
963 | else | |
964 | dma_free_coherent(NULL, mp->rx_desc_area_size, | |
965 | mp->p_rx_desc_area, mp->rx_desc_dma); | |
966 | } | |
967 | ||
968 | /* | |
969 | * mv643xx_eth_stop | |
970 | * | |
971 | * This function is used when closing the network device. | |
972 | * It updates the hardware, | |
973 | * release all memory that holds buffers and descriptors and release the IRQ. | |
974 | * Input : a pointer to the device structure | |
975 | * Output : zero if success , nonzero if fails | |
976 | */ | |
977 | ||
ab4384a6 | 978 | static int mv643xx_eth_stop(struct net_device *dev) |
1da177e4 LT |
979 | { |
980 | struct mv643xx_private *mp = netdev_priv(dev); | |
981 | unsigned int port_num = mp->port_num; | |
982 | ||
c2e5b352 | 983 | /* Mask all interrupts on ethernet port */ |
7303fde8 | 984 | mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL); |
c2e5b352 | 985 | /* wait for previous write to complete */ |
8f518703 DF |
986 | mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num)); |
987 | ||
988 | #ifdef MV643XX_NAPI | |
bea3348e | 989 | napi_disable(&mp->napi); |
8f518703 | 990 | #endif |
1da177e4 LT |
991 | netif_carrier_off(dev); |
992 | netif_stop_queue(dev); | |
993 | ||
1da177e4 LT |
994 | eth_port_reset(mp->port_num); |
995 | ||
8f518703 DF |
996 | mv643xx_eth_free_tx_rings(dev); |
997 | mv643xx_eth_free_rx_rings(dev); | |
1da177e4 | 998 | |
1da177e4 | 999 | free_irq(dev->irq, dev); |
1da177e4 LT |
1000 | |
1001 | return 0; | |
1002 | } | |
1003 | ||
1004 | #ifdef MV643XX_NAPI | |
1da177e4 LT |
1005 | /* |
1006 | * mv643xx_poll | |
1007 | * | |
1008 | * This function is used in case of NAPI | |
1009 | */ | |
bea3348e | 1010 | static int mv643xx_poll(struct napi_struct *napi, int budget) |
1da177e4 | 1011 | { |
bea3348e SH |
1012 | struct mv643xx_private *mp = container_of(napi, struct mv643xx_private, napi); |
1013 | struct net_device *dev = mp->dev; | |
1da177e4 | 1014 | unsigned int port_num = mp->port_num; |
bea3348e | 1015 | int work_done; |
1da177e4 LT |
1016 | |
1017 | #ifdef MV643XX_TX_FAST_REFILL | |
1018 | if (++mp->tx_clean_threshold > 5) { | |
ff561eef | 1019 | mv643xx_eth_free_completed_tx_descs(dev); |
1da177e4 | 1020 | mp->tx_clean_threshold = 0; |
1da177e4 LT |
1021 | } |
1022 | #endif | |
1023 | ||
bea3348e | 1024 | work_done = 0; |
1da177e4 | 1025 | if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num))) |
bea3348e SH |
1026 | != (u32) mp->rx_used_desc_q) |
1027 | work_done = mv643xx_eth_receive_queue(dev, budget); | |
1da177e4 | 1028 | |
bea3348e SH |
1029 | if (work_done < budget) { |
1030 | netif_rx_complete(dev, napi); | |
1da177e4 LT |
1031 | mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0); |
1032 | mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0); | |
1033 | mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), | |
7303fde8 | 1034 | ETH_INT_UNMASK_ALL); |
1da177e4 LT |
1035 | } |
1036 | ||
bea3348e | 1037 | return work_done; |
1da177e4 LT |
1038 | } |
1039 | #endif | |
1040 | ||
c8aaea25 DF |
1041 | /** |
1042 | * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments | |
1043 | * | |
1044 | * Hardware can't handle unaligned fragments smaller than 9 bytes. | |
f7ea3337 PJ |
1045 | * This helper function detects that case. |
1046 | */ | |
1047 | ||
1048 | static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) | |
1049 | { | |
b4de9051 DF |
1050 | unsigned int frag; |
1051 | skb_frag_t *fragp; | |
f7ea3337 | 1052 | |
b4de9051 DF |
1053 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { |
1054 | fragp = &skb_shinfo(skb)->frags[frag]; | |
1055 | if (fragp->size <= 8 && fragp->page_offset & 0x7) | |
1056 | return 1; | |
1057 | } | |
1058 | return 0; | |
f7ea3337 PJ |
1059 | } |
1060 | ||
c8aaea25 DF |
1061 | /** |
1062 | * eth_alloc_tx_desc_index - return the index of the next available tx desc | |
1063 | */ | |
1064 | static int eth_alloc_tx_desc_index(struct mv643xx_private *mp) | |
1065 | { | |
1066 | int tx_desc_curr; | |
1067 | ||
c8aaea25 | 1068 | BUG_ON(mp->tx_desc_count >= mp->tx_ring_size); |
c8aaea25 | 1069 | |
ff561eef | 1070 | tx_desc_curr = mp->tx_curr_desc_q; |
c8aaea25 DF |
1071 | mp->tx_curr_desc_q = (tx_desc_curr + 1) % mp->tx_ring_size; |
1072 | ||
1073 | BUG_ON(mp->tx_curr_desc_q == mp->tx_used_desc_q); | |
1074 | ||
1075 | return tx_desc_curr; | |
1076 | } | |
1077 | ||
1078 | /** | |
1079 | * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments. | |
1da177e4 | 1080 | * |
c8aaea25 DF |
1081 | * Ensure the data for each fragment to be transmitted is mapped properly, |
1082 | * then fill in descriptors in the tx hw queue. | |
1da177e4 | 1083 | */ |
c8aaea25 DF |
1084 | static void eth_tx_fill_frag_descs(struct mv643xx_private *mp, |
1085 | struct sk_buff *skb) | |
1da177e4 | 1086 | { |
c8aaea25 DF |
1087 | int frag; |
1088 | int tx_index; | |
1089 | struct eth_tx_desc *desc; | |
1da177e4 | 1090 | |
c8aaea25 DF |
1091 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { |
1092 | skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag]; | |
1093 | ||
1094 | tx_index = eth_alloc_tx_desc_index(mp); | |
1095 | desc = &mp->p_tx_desc_area[tx_index]; | |
1096 | ||
1097 | desc->cmd_sts = ETH_BUFFER_OWNED_BY_DMA; | |
1098 | /* Last Frag enables interrupt and frees the skb */ | |
1099 | if (frag == (skb_shinfo(skb)->nr_frags - 1)) { | |
1100 | desc->cmd_sts |= ETH_ZERO_PADDING | | |
1101 | ETH_TX_LAST_DESC | | |
1102 | ETH_TX_ENABLE_INTERRUPT; | |
1103 | mp->tx_skb[tx_index] = skb; | |
1104 | } else | |
05980775 | 1105 | mp->tx_skb[tx_index] = NULL; |
c8aaea25 DF |
1106 | |
1107 | desc = &mp->p_tx_desc_area[tx_index]; | |
1108 | desc->l4i_chk = 0; | |
1109 | desc->byte_cnt = this_frag->size; | |
1110 | desc->buf_ptr = dma_map_page(NULL, this_frag->page, | |
1111 | this_frag->page_offset, | |
1112 | this_frag->size, | |
1113 | DMA_TO_DEVICE); | |
1da177e4 | 1114 | } |
c8aaea25 | 1115 | } |
1da177e4 | 1116 | |
c8aaea25 DF |
1117 | /** |
1118 | * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw | |
1119 | * | |
1120 | * Ensure the data for an skb to be transmitted is mapped properly, | |
1121 | * then fill in descriptors in the tx hw queue and start the hardware. | |
1122 | */ | |
ff561eef DF |
1123 | static void eth_tx_submit_descs_for_skb(struct mv643xx_private *mp, |
1124 | struct sk_buff *skb) | |
c8aaea25 DF |
1125 | { |
1126 | int tx_index; | |
1127 | struct eth_tx_desc *desc; | |
1128 | u32 cmd_sts; | |
1129 | int length; | |
ff561eef | 1130 | int nr_frags = skb_shinfo(skb)->nr_frags; |
1da177e4 | 1131 | |
c8aaea25 | 1132 | cmd_sts = ETH_TX_FIRST_DESC | ETH_GEN_CRC | ETH_BUFFER_OWNED_BY_DMA; |
1da177e4 | 1133 | |
c8aaea25 DF |
1134 | tx_index = eth_alloc_tx_desc_index(mp); |
1135 | desc = &mp->p_tx_desc_area[tx_index]; | |
1136 | ||
ff561eef | 1137 | if (nr_frags) { |
c8aaea25 DF |
1138 | eth_tx_fill_frag_descs(mp, skb); |
1139 | ||
1140 | length = skb_headlen(skb); | |
05980775 | 1141 | mp->tx_skb[tx_index] = NULL; |
c8aaea25 DF |
1142 | } else { |
1143 | cmd_sts |= ETH_ZERO_PADDING | | |
1144 | ETH_TX_LAST_DESC | | |
1145 | ETH_TX_ENABLE_INTERRUPT; | |
1146 | length = skb->len; | |
1147 | mp->tx_skb[tx_index] = skb; | |
f7ea3337 PJ |
1148 | } |
1149 | ||
c8aaea25 DF |
1150 | desc->byte_cnt = length; |
1151 | desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE); | |
1da177e4 | 1152 | |
84fa7933 | 1153 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
c8aaea25 DF |
1154 | BUG_ON(skb->protocol != ETH_P_IP); |
1155 | ||
1156 | cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM | | |
1157 | ETH_GEN_IP_V_4_CHECKSUM | | |
eddc9ec5 | 1158 | ip_hdr(skb)->ihl << ETH_TX_IHL_SHIFT; |
c8aaea25 | 1159 | |
eddc9ec5 | 1160 | switch (ip_hdr(skb)->protocol) { |
c8aaea25 DF |
1161 | case IPPROTO_UDP: |
1162 | cmd_sts |= ETH_UDP_FRAME; | |
4bedb452 | 1163 | desc->l4i_chk = udp_hdr(skb)->check; |
c8aaea25 DF |
1164 | break; |
1165 | case IPPROTO_TCP: | |
aa8223c7 | 1166 | desc->l4i_chk = tcp_hdr(skb)->check; |
c8aaea25 DF |
1167 | break; |
1168 | default: | |
1169 | BUG(); | |
1da177e4 | 1170 | } |
1da177e4 | 1171 | } else { |
c8aaea25 DF |
1172 | /* Errata BTS #50, IHL must be 5 if no HW checksum */ |
1173 | cmd_sts |= 5 << ETH_TX_IHL_SHIFT; | |
1174 | desc->l4i_chk = 0; | |
1175 | } | |
1da177e4 | 1176 | |
c8aaea25 DF |
1177 | /* ensure all other descriptors are written before first cmd_sts */ |
1178 | wmb(); | |
1179 | desc->cmd_sts = cmd_sts; | |
1da177e4 | 1180 | |
c8aaea25 DF |
1181 | /* ensure all descriptors are written before poking hardware */ |
1182 | wmb(); | |
ff561eef | 1183 | mv643xx_eth_port_enable_tx(mp->port_num, ETH_TX_QUEUES_ENABLED); |
1da177e4 | 1184 | |
ff561eef | 1185 | mp->tx_desc_count += nr_frags + 1; |
c8aaea25 | 1186 | } |
1da177e4 | 1187 | |
c8aaea25 DF |
1188 | /** |
1189 | * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission | |
1190 | * | |
1191 | */ | |
1192 | static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
1193 | { | |
1194 | struct mv643xx_private *mp = netdev_priv(dev); | |
09f75cd7 | 1195 | struct net_device_stats *stats = &dev->stats; |
c8aaea25 | 1196 | unsigned long flags; |
1da177e4 | 1197 | |
c8aaea25 DF |
1198 | BUG_ON(netif_queue_stopped(dev)); |
1199 | BUG_ON(skb == NULL); | |
94843566 DF |
1200 | |
1201 | if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) { | |
1202 | printk(KERN_ERR "%s: transmit with queue full\n", dev->name); | |
1203 | netif_stop_queue(dev); | |
1204 | return 1; | |
1205 | } | |
1da177e4 | 1206 | |
c8aaea25 | 1207 | if (has_tiny_unaligned_frags(skb)) { |
364c6bad | 1208 | if (__skb_linearize(skb)) { |
c8aaea25 DF |
1209 | stats->tx_dropped++; |
1210 | printk(KERN_DEBUG "%s: failed to linearize tiny " | |
1211 | "unaligned fragment\n", dev->name); | |
1212 | return 1; | |
1da177e4 LT |
1213 | } |
1214 | } | |
f7ea3337 | 1215 | |
c8aaea25 | 1216 | spin_lock_irqsave(&mp->lock, flags); |
1da177e4 | 1217 | |
ff561eef | 1218 | eth_tx_submit_descs_for_skb(mp, skb); |
e7e381f6 | 1219 | stats->tx_bytes += skb->len; |
1da177e4 LT |
1220 | stats->tx_packets++; |
1221 | dev->trans_start = jiffies; | |
1222 | ||
c8aaea25 DF |
1223 | if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) |
1224 | netif_stop_queue(dev); | |
1225 | ||
1da177e4 LT |
1226 | spin_unlock_irqrestore(&mp->lock, flags); |
1227 | ||
1228 | return 0; /* success */ | |
1229 | } | |
1230 | ||
63c9e549 | 1231 | #ifdef CONFIG_NET_POLL_CONTROLLER |
63c9e549 DF |
1232 | static void mv643xx_netpoll(struct net_device *netdev) |
1233 | { | |
1234 | struct mv643xx_private *mp = netdev_priv(netdev); | |
c2e5b352 DF |
1235 | int port_num = mp->port_num; |
1236 | ||
7303fde8 | 1237 | mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL); |
c2e5b352 DF |
1238 | /* wait for previous write to complete */ |
1239 | mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num)); | |
63c9e549 | 1240 | |
9da3b1ad | 1241 | mv643xx_eth_int_handler(netdev->irq, netdev); |
c2e5b352 | 1242 | |
7303fde8 | 1243 | mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL); |
63c9e549 DF |
1244 | } |
1245 | #endif | |
1246 | ||
d0412d96 JC |
1247 | static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address, |
1248 | int speed, int duplex, | |
1249 | struct ethtool_cmd *cmd) | |
1250 | { | |
1251 | struct mv643xx_private *mp = netdev_priv(dev); | |
1252 | ||
1253 | memset(cmd, 0, sizeof(*cmd)); | |
1254 | ||
1255 | cmd->port = PORT_MII; | |
1256 | cmd->transceiver = XCVR_INTERNAL; | |
1257 | cmd->phy_address = phy_address; | |
1258 | ||
1259 | if (speed == 0) { | |
1260 | cmd->autoneg = AUTONEG_ENABLE; | |
1261 | /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */ | |
1262 | cmd->speed = SPEED_100; | |
1263 | cmd->advertising = ADVERTISED_10baseT_Half | | |
1264 | ADVERTISED_10baseT_Full | | |
1265 | ADVERTISED_100baseT_Half | | |
1266 | ADVERTISED_100baseT_Full; | |
1267 | if (mp->mii.supports_gmii) | |
1268 | cmd->advertising |= ADVERTISED_1000baseT_Full; | |
1269 | } else { | |
1270 | cmd->autoneg = AUTONEG_DISABLE; | |
1271 | cmd->speed = speed; | |
1272 | cmd->duplex = duplex; | |
1273 | } | |
1274 | } | |
1275 | ||
1da177e4 LT |
1276 | /*/ |
1277 | * mv643xx_eth_probe | |
1278 | * | |
1279 | * First function called after registering the network device. | |
1280 | * It's purpose is to initialize the device as an ethernet device, | |
1281 | * fill the ethernet device structure with pointers * to functions, | |
1282 | * and set the MAC address of the interface | |
1283 | * | |
1284 | * Input : struct device * | |
1285 | * Output : -ENOMEM if failed , 0 if success | |
1286 | */ | |
3ae5eaec | 1287 | static int mv643xx_eth_probe(struct platform_device *pdev) |
1da177e4 | 1288 | { |
1da177e4 | 1289 | struct mv643xx_eth_platform_data *pd; |
84dd619e | 1290 | int port_num; |
1da177e4 LT |
1291 | struct mv643xx_private *mp; |
1292 | struct net_device *dev; | |
1293 | u8 *p; | |
1294 | struct resource *res; | |
1295 | int err; | |
d0412d96 | 1296 | struct ethtool_cmd cmd; |
01999873 DF |
1297 | int duplex = DUPLEX_HALF; |
1298 | int speed = 0; /* default to auto-negotiation */ | |
1da177e4 | 1299 | |
84dd619e DF |
1300 | pd = pdev->dev.platform_data; |
1301 | if (pd == NULL) { | |
1302 | printk(KERN_ERR "No mv643xx_eth_platform_data\n"); | |
1303 | return -ENODEV; | |
1304 | } | |
1305 | ||
1da177e4 LT |
1306 | dev = alloc_etherdev(sizeof(struct mv643xx_private)); |
1307 | if (!dev) | |
1308 | return -ENOMEM; | |
1309 | ||
3ae5eaec | 1310 | platform_set_drvdata(pdev, dev); |
1da177e4 LT |
1311 | |
1312 | mp = netdev_priv(dev); | |
bea3348e SH |
1313 | mp->dev = dev; |
1314 | #ifdef MV643XX_NAPI | |
1315 | netif_napi_add(dev, &mp->napi, mv643xx_poll, 64); | |
1316 | #endif | |
1da177e4 LT |
1317 | |
1318 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1319 | BUG_ON(!res); | |
1320 | dev->irq = res->start; | |
1321 | ||
1da177e4 LT |
1322 | dev->open = mv643xx_eth_open; |
1323 | dev->stop = mv643xx_eth_stop; | |
1324 | dev->hard_start_xmit = mv643xx_eth_start_xmit; | |
1da177e4 LT |
1325 | dev->set_mac_address = mv643xx_eth_set_mac_address; |
1326 | dev->set_multicast_list = mv643xx_eth_set_rx_mode; | |
1327 | ||
1328 | /* No need to Tx Timeout */ | |
1329 | dev->tx_timeout = mv643xx_eth_tx_timeout; | |
1da177e4 | 1330 | |
63c9e549 DF |
1331 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1332 | dev->poll_controller = mv643xx_netpoll; | |
1333 | #endif | |
1334 | ||
1da177e4 | 1335 | dev->watchdog_timeo = 2 * HZ; |
1da177e4 LT |
1336 | dev->base_addr = 0; |
1337 | dev->change_mtu = mv643xx_eth_change_mtu; | |
d0412d96 | 1338 | dev->do_ioctl = mv643xx_eth_do_ioctl; |
1da177e4 LT |
1339 | SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops); |
1340 | ||
1341 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX | |
1342 | #ifdef MAX_SKB_FRAGS | |
1343 | /* | |
1344 | * Zero copy can only work if we use Discovery II memory. Else, we will | |
1345 | * have to map the buffers to ISA memory which is only 16 MB | |
1346 | */ | |
63890576 | 1347 | dev->features = NETIF_F_SG | NETIF_F_IP_CSUM; |
1da177e4 LT |
1348 | #endif |
1349 | #endif | |
1350 | ||
1351 | /* Configure the timeout task */ | |
91c7c568 | 1352 | INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task); |
1da177e4 LT |
1353 | |
1354 | spin_lock_init(&mp->lock); | |
1355 | ||
fadac406 | 1356 | port_num = mp->port_num = pd->port_number; |
84dd619e | 1357 | |
1da177e4 | 1358 | /* set default config values */ |
144213d7 | 1359 | eth_port_uc_addr_get(port_num, dev->dev_addr); |
1da177e4 LT |
1360 | mp->rx_ring_size = MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE; |
1361 | mp->tx_ring_size = MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE; | |
1362 | ||
84dd619e DF |
1363 | if (is_valid_ether_addr(pd->mac_addr)) |
1364 | memcpy(dev->dev_addr, pd->mac_addr, 6); | |
1da177e4 | 1365 | |
84dd619e DF |
1366 | if (pd->phy_addr || pd->force_phy_addr) |
1367 | ethernet_phy_set(port_num, pd->phy_addr); | |
1da177e4 | 1368 | |
84dd619e DF |
1369 | if (pd->rx_queue_size) |
1370 | mp->rx_ring_size = pd->rx_queue_size; | |
1da177e4 | 1371 | |
84dd619e DF |
1372 | if (pd->tx_queue_size) |
1373 | mp->tx_ring_size = pd->tx_queue_size; | |
1da177e4 | 1374 | |
84dd619e DF |
1375 | if (pd->tx_sram_size) { |
1376 | mp->tx_sram_size = pd->tx_sram_size; | |
1377 | mp->tx_sram_addr = pd->tx_sram_addr; | |
1378 | } | |
01999873 | 1379 | |
84dd619e DF |
1380 | if (pd->rx_sram_size) { |
1381 | mp->rx_sram_size = pd->rx_sram_size; | |
1382 | mp->rx_sram_addr = pd->rx_sram_addr; | |
1da177e4 LT |
1383 | } |
1384 | ||
84dd619e DF |
1385 | duplex = pd->duplex; |
1386 | speed = pd->speed; | |
1387 | ||
c28a4f89 JC |
1388 | /* Hook up MII support for ethtool */ |
1389 | mp->mii.dev = dev; | |
1390 | mp->mii.mdio_read = mv643xx_mdio_read; | |
1391 | mp->mii.mdio_write = mv643xx_mdio_write; | |
1392 | mp->mii.phy_id = ethernet_phy_get(port_num); | |
1393 | mp->mii.phy_id_mask = 0x3f; | |
1394 | mp->mii.reg_num_mask = 0x1f; | |
1395 | ||
1da177e4 LT |
1396 | err = ethernet_phy_detect(port_num); |
1397 | if (err) { | |
1398 | pr_debug("MV643xx ethernet port %d: " | |
1399 | "No PHY detected at addr %d\n", | |
1400 | port_num, ethernet_phy_get(port_num)); | |
d0412d96 | 1401 | goto out; |
1da177e4 LT |
1402 | } |
1403 | ||
01999873 | 1404 | ethernet_phy_reset(port_num); |
c28a4f89 | 1405 | mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii); |
d0412d96 JC |
1406 | mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd); |
1407 | mv643xx_eth_update_pscr(dev, &cmd); | |
1408 | mv643xx_set_settings(dev, &cmd); | |
c28a4f89 | 1409 | |
b0b8dab2 | 1410 | SET_NETDEV_DEV(dev, &pdev->dev); |
1da177e4 LT |
1411 | err = register_netdev(dev); |
1412 | if (err) | |
1413 | goto out; | |
1414 | ||
1415 | p = dev->dev_addr; | |
1416 | printk(KERN_NOTICE | |
0795af57 JP |
1417 | "%s: port %d with MAC address %s\n", |
1418 | dev->name, port_num, print_mac(mac, p)); | |
1da177e4 LT |
1419 | |
1420 | if (dev->features & NETIF_F_SG) | |
1421 | printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name); | |
1422 | ||
1423 | if (dev->features & NETIF_F_IP_CSUM) | |
1424 | printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n", | |
1425 | dev->name); | |
1426 | ||
1427 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX | |
1428 | printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name); | |
1429 | #endif | |
1430 | ||
1431 | #ifdef MV643XX_COAL | |
1432 | printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n", | |
1433 | dev->name); | |
1434 | #endif | |
1435 | ||
1436 | #ifdef MV643XX_NAPI | |
1437 | printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name); | |
1438 | #endif | |
1439 | ||
b1529871 ND |
1440 | if (mp->tx_sram_size > 0) |
1441 | printk(KERN_NOTICE "%s: Using SRAM\n", dev->name); | |
1442 | ||
1da177e4 LT |
1443 | return 0; |
1444 | ||
1445 | out: | |
1446 | free_netdev(dev); | |
1447 | ||
1448 | return err; | |
1449 | } | |
1450 | ||
3ae5eaec | 1451 | static int mv643xx_eth_remove(struct platform_device *pdev) |
1da177e4 | 1452 | { |
3ae5eaec | 1453 | struct net_device *dev = platform_get_drvdata(pdev); |
1da177e4 LT |
1454 | |
1455 | unregister_netdev(dev); | |
1456 | flush_scheduled_work(); | |
1457 | ||
1458 | free_netdev(dev); | |
3ae5eaec | 1459 | platform_set_drvdata(pdev, NULL); |
1da177e4 LT |
1460 | return 0; |
1461 | } | |
1462 | ||
3ae5eaec | 1463 | static int mv643xx_eth_shared_probe(struct platform_device *pdev) |
1da177e4 | 1464 | { |
1da177e4 LT |
1465 | struct resource *res; |
1466 | ||
1467 | printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n"); | |
1468 | ||
1469 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1470 | if (res == NULL) | |
1471 | return -ENODEV; | |
1472 | ||
1473 | mv643xx_eth_shared_base = ioremap(res->start, | |
1474 | MV643XX_ETH_SHARED_REGS_SIZE); | |
1475 | if (mv643xx_eth_shared_base == NULL) | |
1476 | return -ENOMEM; | |
1477 | ||
1478 | return 0; | |
1479 | ||
1480 | } | |
1481 | ||
3ae5eaec | 1482 | static int mv643xx_eth_shared_remove(struct platform_device *pdev) |
1da177e4 LT |
1483 | { |
1484 | iounmap(mv643xx_eth_shared_base); | |
1485 | mv643xx_eth_shared_base = NULL; | |
1486 | ||
1487 | return 0; | |
1488 | } | |
1489 | ||
d57ab6fd DF |
1490 | static void mv643xx_eth_shutdown(struct platform_device *pdev) |
1491 | { | |
1492 | struct net_device *dev = platform_get_drvdata(pdev); | |
1493 | struct mv643xx_private *mp = netdev_priv(dev); | |
1494 | unsigned int port_num = mp->port_num; | |
1495 | ||
1496 | /* Mask all interrupts on ethernet port */ | |
1497 | mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0); | |
1498 | mv_read (MV643XX_ETH_INTERRUPT_MASK_REG(port_num)); | |
1499 | ||
1500 | eth_port_reset(port_num); | |
1501 | } | |
1502 | ||
3ae5eaec | 1503 | static struct platform_driver mv643xx_eth_driver = { |
1da177e4 LT |
1504 | .probe = mv643xx_eth_probe, |
1505 | .remove = mv643xx_eth_remove, | |
d57ab6fd | 1506 | .shutdown = mv643xx_eth_shutdown, |
3ae5eaec RK |
1507 | .driver = { |
1508 | .name = MV643XX_ETH_NAME, | |
1509 | }, | |
1da177e4 LT |
1510 | }; |
1511 | ||
3ae5eaec | 1512 | static struct platform_driver mv643xx_eth_shared_driver = { |
1da177e4 LT |
1513 | .probe = mv643xx_eth_shared_probe, |
1514 | .remove = mv643xx_eth_shared_remove, | |
3ae5eaec RK |
1515 | .driver = { |
1516 | .name = MV643XX_ETH_SHARED_NAME, | |
1517 | }, | |
1da177e4 LT |
1518 | }; |
1519 | ||
1520 | /* | |
1521 | * mv643xx_init_module | |
1522 | * | |
1523 | * Registers the network drivers into the Linux kernel | |
1524 | * | |
1525 | * Input : N/A | |
1526 | * | |
1527 | * Output : N/A | |
1528 | */ | |
1529 | static int __init mv643xx_init_module(void) | |
1530 | { | |
1531 | int rc; | |
1532 | ||
3ae5eaec | 1533 | rc = platform_driver_register(&mv643xx_eth_shared_driver); |
1da177e4 | 1534 | if (!rc) { |
3ae5eaec | 1535 | rc = platform_driver_register(&mv643xx_eth_driver); |
1da177e4 | 1536 | if (rc) |
3ae5eaec | 1537 | platform_driver_unregister(&mv643xx_eth_shared_driver); |
1da177e4 LT |
1538 | } |
1539 | return rc; | |
1540 | } | |
1541 | ||
1542 | /* | |
1543 | * mv643xx_cleanup_module | |
1544 | * | |
1545 | * Registers the network drivers into the Linux kernel | |
1546 | * | |
1547 | * Input : N/A | |
1548 | * | |
1549 | * Output : N/A | |
1550 | */ | |
1551 | static void __exit mv643xx_cleanup_module(void) | |
1552 | { | |
3ae5eaec RK |
1553 | platform_driver_unregister(&mv643xx_eth_driver); |
1554 | platform_driver_unregister(&mv643xx_eth_shared_driver); | |
1da177e4 LT |
1555 | } |
1556 | ||
1557 | module_init(mv643xx_init_module); | |
1558 | module_exit(mv643xx_cleanup_module); | |
1559 | ||
1560 | MODULE_LICENSE("GPL"); | |
1561 | MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani" | |
1562 | " and Dale Farnsworth"); | |
1563 | MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); | |
1564 | ||
1565 | /* | |
1566 | * The second part is the low level driver of the gigE ethernet ports. | |
1567 | */ | |
1568 | ||
1569 | /* | |
1570 | * Marvell's Gigabit Ethernet controller low level driver | |
1571 | * | |
1572 | * DESCRIPTION: | |
1573 | * This file introduce low level API to Marvell's Gigabit Ethernet | |
1574 | * controller. This Gigabit Ethernet Controller driver API controls | |
1575 | * 1) Operations (i.e. port init, start, reset etc'). | |
1576 | * 2) Data flow (i.e. port send, receive etc'). | |
1577 | * Each Gigabit Ethernet port is controlled via | |
1578 | * struct mv643xx_private. | |
1579 | * This struct includes user configuration information as well as | |
1580 | * driver internal data needed for its operations. | |
1581 | * | |
1582 | * Supported Features: | |
1583 | * - This low level driver is OS independent. Allocating memory for | |
1584 | * the descriptor rings and buffers are not within the scope of | |
1585 | * this driver. | |
1586 | * - The user is free from Rx/Tx queue managing. | |
1587 | * - This low level driver introduce functionality API that enable | |
1588 | * the to operate Marvell's Gigabit Ethernet Controller in a | |
1589 | * convenient way. | |
1590 | * - Simple Gigabit Ethernet port operation API. | |
1591 | * - Simple Gigabit Ethernet port data flow API. | |
1592 | * - Data flow and operation API support per queue functionality. | |
1593 | * - Support cached descriptors for better performance. | |
1594 | * - Enable access to all four DRAM banks and internal SRAM memory | |
1595 | * spaces. | |
1596 | * - PHY access and control API. | |
1597 | * - Port control register configuration API. | |
1598 | * - Full control over Unicast and Multicast MAC configurations. | |
1599 | * | |
1600 | * Operation flow: | |
1601 | * | |
1602 | * Initialization phase | |
1603 | * This phase complete the initialization of the the | |
1604 | * mv643xx_private struct. | |
1605 | * User information regarding port configuration has to be set | |
1606 | * prior to calling the port initialization routine. | |
1607 | * | |
1608 | * In this phase any port Tx/Rx activity is halted, MIB counters | |
1609 | * are cleared, PHY address is set according to user parameter and | |
1610 | * access to DRAM and internal SRAM memory spaces. | |
1611 | * | |
1612 | * Driver ring initialization | |
1613 | * Allocating memory for the descriptor rings and buffers is not | |
1614 | * within the scope of this driver. Thus, the user is required to | |
1615 | * allocate memory for the descriptors ring and buffers. Those | |
1616 | * memory parameters are used by the Rx and Tx ring initialization | |
1617 | * routines in order to curve the descriptor linked list in a form | |
1618 | * of a ring. | |
1619 | * Note: Pay special attention to alignment issues when using | |
1620 | * cached descriptors/buffers. In this phase the driver store | |
1621 | * information in the mv643xx_private struct regarding each queue | |
1622 | * ring. | |
1623 | * | |
1624 | * Driver start | |
1625 | * This phase prepares the Ethernet port for Rx and Tx activity. | |
1626 | * It uses the information stored in the mv643xx_private struct to | |
1627 | * initialize the various port registers. | |
1628 | * | |
1629 | * Data flow: | |
1630 | * All packet references to/from the driver are done using | |
1631 | * struct pkt_info. | |
1632 | * This struct is a unified struct used with Rx and Tx operations. | |
1633 | * This way the user is not required to be familiar with neither | |
1634 | * Tx nor Rx descriptors structures. | |
1635 | * The driver's descriptors rings are management by indexes. | |
1636 | * Those indexes controls the ring resources and used to indicate | |
1637 | * a SW resource error: | |
1638 | * 'current' | |
1639 | * This index points to the current available resource for use. For | |
1640 | * example in Rx process this index will point to the descriptor | |
1641 | * that will be passed to the user upon calling the receive | |
1642 | * routine. In Tx process, this index will point to the descriptor | |
1643 | * that will be assigned with the user packet info and transmitted. | |
1644 | * 'used' | |
1645 | * This index points to the descriptor that need to restore its | |
1646 | * resources. For example in Rx process, using the Rx buffer return | |
1647 | * API will attach the buffer returned in packet info to the | |
1648 | * descriptor pointed by 'used'. In Tx process, using the Tx | |
1649 | * descriptor return will merely return the user packet info with | |
1650 | * the command status of the transmitted buffer pointed by the | |
1651 | * 'used' index. Nevertheless, it is essential to use this routine | |
1652 | * to update the 'used' index. | |
1653 | * 'first' | |
1654 | * This index supports Tx Scatter-Gather. It points to the first | |
1655 | * descriptor of a packet assembled of multiple buffers. For | |
1656 | * example when in middle of Such packet we have a Tx resource | |
1657 | * error the 'curr' index get the value of 'first' to indicate | |
1658 | * that the ring returned to its state before trying to transmit | |
1659 | * this packet. | |
1660 | * | |
1661 | * Receive operation: | |
1662 | * The eth_port_receive API set the packet information struct, | |
1663 | * passed by the caller, with received information from the | |
1664 | * 'current' SDMA descriptor. | |
1665 | * It is the user responsibility to return this resource back | |
1666 | * to the Rx descriptor ring to enable the reuse of this source. | |
1667 | * Return Rx resource is done using the eth_rx_return_buff API. | |
1668 | * | |
1da177e4 LT |
1669 | * Prior to calling the initialization routine eth_port_init() the user |
1670 | * must set the following fields under mv643xx_private struct: | |
1671 | * port_num User Ethernet port number. | |
1da177e4 LT |
1672 | * port_config User port configuration value. |
1673 | * port_config_extend User port config extend value. | |
1674 | * port_sdma_config User port SDMA config value. | |
1675 | * port_serial_control User port serial control value. | |
1676 | * | |
1677 | * This driver data flow is done using the struct pkt_info which | |
1678 | * is a unified struct for Rx and Tx operations: | |
1679 | * | |
1680 | * byte_cnt Tx/Rx descriptor buffer byte count. | |
1681 | * l4i_chk CPU provided TCP Checksum. For Tx operation | |
1682 | * only. | |
1683 | * cmd_sts Tx/Rx descriptor command status. | |
1684 | * buf_ptr Tx/Rx descriptor buffer pointer. | |
1685 | * return_info Tx/Rx user resource return information. | |
1686 | */ | |
1687 | ||
1da177e4 LT |
1688 | /* PHY routines */ |
1689 | static int ethernet_phy_get(unsigned int eth_port_num); | |
1690 | static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr); | |
1691 | ||
1692 | /* Ethernet Port routines */ | |
cf4086c7 | 1693 | static void eth_port_set_filter_table_entry(int table, unsigned char entry); |
1da177e4 LT |
1694 | |
1695 | /* | |
1696 | * eth_port_init - Initialize the Ethernet port driver | |
1697 | * | |
1698 | * DESCRIPTION: | |
1699 | * This function prepares the ethernet port to start its activity: | |
1700 | * 1) Completes the ethernet port driver struct initialization toward port | |
1701 | * start routine. | |
1702 | * 2) Resets the device to a quiescent state in case of warm reboot. | |
1703 | * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM. | |
1704 | * 4) Clean MAC tables. The reset status of those tables is unknown. | |
1705 | * 5) Set PHY address. | |
1706 | * Note: Call this routine prior to eth_port_start routine and after | |
1707 | * setting user values in the user fields of Ethernet port control | |
1708 | * struct. | |
1709 | * | |
1710 | * INPUT: | |
1711 | * struct mv643xx_private *mp Ethernet port control struct | |
1712 | * | |
1713 | * OUTPUT: | |
1714 | * See description. | |
1715 | * | |
1716 | * RETURN: | |
1717 | * None. | |
1718 | */ | |
1719 | static void eth_port_init(struct mv643xx_private *mp) | |
1720 | { | |
1da177e4 | 1721 | mp->rx_resource_err = 0; |
1da177e4 LT |
1722 | |
1723 | eth_port_reset(mp->port_num); | |
1724 | ||
1725 | eth_port_init_mac_tables(mp->port_num); | |
1da177e4 LT |
1726 | } |
1727 | ||
1728 | /* | |
1729 | * eth_port_start - Start the Ethernet port activity. | |
1730 | * | |
1731 | * DESCRIPTION: | |
1732 | * This routine prepares the Ethernet port for Rx and Tx activity: | |
1733 | * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that | |
1734 | * has been initialized a descriptor's ring (using | |
1735 | * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx) | |
1736 | * 2. Initialize and enable the Ethernet configuration port by writing to | |
1737 | * the port's configuration and command registers. | |
1738 | * 3. Initialize and enable the SDMA by writing to the SDMA's | |
1739 | * configuration and command registers. After completing these steps, | |
1740 | * the ethernet port SDMA can starts to perform Rx and Tx activities. | |
1741 | * | |
1742 | * Note: Each Rx and Tx queue descriptor's list must be initialized prior | |
1743 | * to calling this function (use ether_init_tx_desc_ring for Tx queues | |
1744 | * and ether_init_rx_desc_ring for Rx queues). | |
1745 | * | |
1746 | * INPUT: | |
ed9b5d45 | 1747 | * dev - a pointer to the required interface |
1da177e4 LT |
1748 | * |
1749 | * OUTPUT: | |
1750 | * Ethernet port is ready to receive and transmit. | |
1751 | * | |
1752 | * RETURN: | |
1753 | * None. | |
1754 | */ | |
ed9b5d45 | 1755 | static void eth_port_start(struct net_device *dev) |
1da177e4 | 1756 | { |
ed9b5d45 | 1757 | struct mv643xx_private *mp = netdev_priv(dev); |
1da177e4 LT |
1758 | unsigned int port_num = mp->port_num; |
1759 | int tx_curr_desc, rx_curr_desc; | |
d0412d96 JC |
1760 | u32 pscr; |
1761 | struct ethtool_cmd ethtool_cmd; | |
1da177e4 LT |
1762 | |
1763 | /* Assignment of Tx CTRP of given queue */ | |
1764 | tx_curr_desc = mp->tx_curr_desc_q; | |
1765 | mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num), | |
1766 | (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc)); | |
1767 | ||
1768 | /* Assignment of Rx CRDP of given queue */ | |
1769 | rx_curr_desc = mp->rx_curr_desc_q; | |
1770 | mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num), | |
1771 | (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc)); | |
1772 | ||
1773 | /* Add the assigned Ethernet address to the port's address table */ | |
ed9b5d45 | 1774 | eth_port_uc_addr_set(port_num, dev->dev_addr); |
1da177e4 LT |
1775 | |
1776 | /* Assign port configuration and command. */ | |
01999873 DF |
1777 | mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num), |
1778 | MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE); | |
1779 | ||
1780 | mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num), | |
1781 | MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE); | |
1da177e4 | 1782 | |
d0412d96 | 1783 | pscr = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)); |
01999873 DF |
1784 | |
1785 | pscr &= ~(MV643XX_ETH_SERIAL_PORT_ENABLE | MV643XX_ETH_FORCE_LINK_PASS); | |
d0412d96 | 1786 | mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr); |
1da177e4 | 1787 | |
d0412d96 JC |
1788 | pscr |= MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | |
1789 | MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII | | |
1790 | MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX | | |
1791 | MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL | | |
1792 | MV643XX_ETH_SERIAL_PORT_CONTROL_RESERVED; | |
1da177e4 | 1793 | |
d0412d96 | 1794 | mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr); |
1da177e4 | 1795 | |
d0412d96 JC |
1796 | pscr |= MV643XX_ETH_SERIAL_PORT_ENABLE; |
1797 | mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr); | |
1da177e4 LT |
1798 | |
1799 | /* Assign port SDMA configuration */ | |
01999873 DF |
1800 | mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num), |
1801 | MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE); | |
1da177e4 LT |
1802 | |
1803 | /* Enable port Rx. */ | |
ff561eef | 1804 | mv643xx_eth_port_enable_rx(port_num, ETH_RX_QUEUES_ENABLED); |
8f543718 DF |
1805 | |
1806 | /* Disable port bandwidth limits by clearing MTU register */ | |
1807 | mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num), 0); | |
d0412d96 JC |
1808 | |
1809 | /* save phy settings across reset */ | |
1810 | mv643xx_get_settings(dev, ðtool_cmd); | |
1811 | ethernet_phy_reset(mp->port_num); | |
1812 | mv643xx_set_settings(dev, ðtool_cmd); | |
1da177e4 LT |
1813 | } |
1814 | ||
1815 | /* | |
144213d7 | 1816 | * eth_port_uc_addr_set - Write a MAC address into the port's hw registers |
1da177e4 | 1817 | */ |
144213d7 | 1818 | static void eth_port_uc_addr_set(unsigned int port_num, unsigned char *p_addr) |
1da177e4 LT |
1819 | { |
1820 | unsigned int mac_h; | |
1821 | unsigned int mac_l; | |
cf4086c7 | 1822 | int table; |
1da177e4 LT |
1823 | |
1824 | mac_l = (p_addr[4] << 8) | (p_addr[5]); | |
1825 | mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) | | |
1826 | (p_addr[3] << 0); | |
1827 | ||
144213d7 GP |
1828 | mv_write(MV643XX_ETH_MAC_ADDR_LOW(port_num), mac_l); |
1829 | mv_write(MV643XX_ETH_MAC_ADDR_HIGH(port_num), mac_h); | |
1da177e4 | 1830 | |
144213d7 GP |
1831 | /* Accept frames with this address */ |
1832 | table = MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(port_num); | |
cf4086c7 | 1833 | eth_port_set_filter_table_entry(table, p_addr[5] & 0x0f); |
1da177e4 LT |
1834 | } |
1835 | ||
1836 | /* | |
144213d7 | 1837 | * eth_port_uc_addr_get - Read the MAC address from the port's hw registers |
1da177e4 | 1838 | */ |
144213d7 | 1839 | static void eth_port_uc_addr_get(unsigned int port_num, unsigned char *p_addr) |
1da177e4 | 1840 | { |
1da177e4 LT |
1841 | unsigned int mac_h; |
1842 | unsigned int mac_l; | |
1843 | ||
144213d7 GP |
1844 | mac_h = mv_read(MV643XX_ETH_MAC_ADDR_HIGH(port_num)); |
1845 | mac_l = mv_read(MV643XX_ETH_MAC_ADDR_LOW(port_num)); | |
1da177e4 LT |
1846 | |
1847 | p_addr[0] = (mac_h >> 24) & 0xff; | |
1848 | p_addr[1] = (mac_h >> 16) & 0xff; | |
1849 | p_addr[2] = (mac_h >> 8) & 0xff; | |
1850 | p_addr[3] = mac_h & 0xff; | |
1851 | p_addr[4] = (mac_l >> 8) & 0xff; | |
1852 | p_addr[5] = mac_l & 0xff; | |
1853 | } | |
1854 | ||
16e03018 DF |
1855 | /* |
1856 | * The entries in each table are indexed by a hash of a packet's MAC | |
1857 | * address. One bit in each entry determines whether the packet is | |
1858 | * accepted. There are 4 entries (each 8 bits wide) in each register | |
1859 | * of the table. The bits in each entry are defined as follows: | |
1860 | * 0 Accept=1, Drop=0 | |
1861 | * 3-1 Queue (ETH_Q0=0) | |
1862 | * 7-4 Reserved = 0; | |
1863 | */ | |
1864 | static void eth_port_set_filter_table_entry(int table, unsigned char entry) | |
1865 | { | |
1866 | unsigned int table_reg; | |
1867 | unsigned int tbl_offset; | |
1868 | unsigned int reg_offset; | |
1869 | ||
1870 | tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */ | |
1871 | reg_offset = entry % 4; /* Entry offset within the register */ | |
1872 | ||
1873 | /* Set "accepts frame bit" at specified table entry */ | |
1874 | table_reg = mv_read(table + tbl_offset); | |
1875 | table_reg |= 0x01 << (8 * reg_offset); | |
1876 | mv_write(table + tbl_offset, table_reg); | |
1877 | } | |
1878 | ||
1879 | /* | |
1880 | * eth_port_mc_addr - Multicast address settings. | |
1881 | * | |
1882 | * The MV device supports multicast using two tables: | |
1883 | * 1) Special Multicast Table for MAC addresses of the form | |
1884 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF). | |
1885 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast | |
1886 | * Table entries in the DA-Filter table. | |
1887 | * 2) Other Multicast Table for multicast of another type. A CRC-8bit | |
1888 | * is used as an index to the Other Multicast Table entries in the | |
1889 | * DA-Filter table. This function calculates the CRC-8bit value. | |
1890 | * In either case, eth_port_set_filter_table_entry() is then called | |
1891 | * to set to set the actual table entry. | |
1892 | */ | |
1893 | static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr) | |
1894 | { | |
1895 | unsigned int mac_h; | |
1896 | unsigned int mac_l; | |
1897 | unsigned char crc_result = 0; | |
1898 | int table; | |
1899 | int mac_array[48]; | |
1900 | int crc[8]; | |
1901 | int i; | |
1902 | ||
1903 | if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) && | |
1904 | (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) { | |
1905 | table = MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE | |
1906 | (eth_port_num); | |
1907 | eth_port_set_filter_table_entry(table, p_addr[5]); | |
1908 | return; | |
1909 | } | |
1910 | ||
1911 | /* Calculate CRC-8 out of the given address */ | |
1912 | mac_h = (p_addr[0] << 8) | (p_addr[1]); | |
1913 | mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) | | |
1914 | (p_addr[4] << 8) | (p_addr[5] << 0); | |
1915 | ||
1916 | for (i = 0; i < 32; i++) | |
1917 | mac_array[i] = (mac_l >> i) & 0x1; | |
1918 | for (i = 32; i < 48; i++) | |
1919 | mac_array[i] = (mac_h >> (i - 32)) & 0x1; | |
1920 | ||
1921 | crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^ | |
1922 | mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^ | |
1923 | mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^ | |
1924 | mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^ | |
1925 | mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0]; | |
1926 | ||
1927 | crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^ | |
1928 | mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^ | |
1929 | mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^ | |
1930 | mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^ | |
1931 | mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^ | |
1932 | mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^ | |
1933 | mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0]; | |
1934 | ||
1935 | crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^ | |
1936 | mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^ | |
1937 | mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^ | |
1938 | mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^ | |
1939 | mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ | |
1940 | mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0]; | |
1941 | ||
1942 | crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^ | |
1943 | mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^ | |
1944 | mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^ | |
1945 | mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ | |
1946 | mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^ | |
1947 | mac_array[3] ^ mac_array[2] ^ mac_array[1]; | |
1948 | ||
1949 | crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^ | |
1950 | mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^ | |
1951 | mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^ | |
1952 | mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^ | |
1953 | mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^ | |
1954 | mac_array[3] ^ mac_array[2]; | |
1955 | ||
1956 | crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^ | |
1957 | mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^ | |
1958 | mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^ | |
1959 | mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^ | |
1960 | mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^ | |
1961 | mac_array[4] ^ mac_array[3]; | |
1962 | ||
1963 | crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^ | |
1964 | mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^ | |
1965 | mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^ | |
1966 | mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^ | |
1967 | mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^ | |
1968 | mac_array[4]; | |
1969 | ||
1970 | crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^ | |
1971 | mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^ | |
1972 | mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^ | |
1973 | mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^ | |
1974 | mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5]; | |
1975 | ||
1976 | for (i = 0; i < 8; i++) | |
1977 | crc_result = crc_result | (crc[i] << i); | |
1978 | ||
1979 | table = MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num); | |
1980 | eth_port_set_filter_table_entry(table, crc_result); | |
1981 | } | |
1982 | ||
1983 | /* | |
1984 | * Set the entire multicast list based on dev->mc_list. | |
1985 | */ | |
1986 | static void eth_port_set_multicast_list(struct net_device *dev) | |
1987 | { | |
1988 | ||
1989 | struct dev_mc_list *mc_list; | |
1990 | int i; | |
1991 | int table_index; | |
1992 | struct mv643xx_private *mp = netdev_priv(dev); | |
1993 | unsigned int eth_port_num = mp->port_num; | |
1994 | ||
1995 | /* If the device is in promiscuous mode or in all multicast mode, | |
1996 | * we will fully populate both multicast tables with accept. | |
1997 | * This is guaranteed to yield a match on all multicast addresses... | |
1998 | */ | |
1999 | if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) { | |
2000 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { | |
b4de9051 DF |
2001 | /* Set all entries in DA filter special multicast |
2002 | * table (Ex_dFSMT) | |
2003 | * Set for ETH_Q0 for now | |
2004 | * Bits | |
2005 | * 0 Accept=1, Drop=0 | |
2006 | * 3-1 Queue ETH_Q0=0 | |
2007 | * 7-4 Reserved = 0; | |
2008 | */ | |
2009 | mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101); | |
2010 | ||
2011 | /* Set all entries in DA filter other multicast | |
2012 | * table (Ex_dFOMT) | |
2013 | * Set for ETH_Q0 for now | |
2014 | * Bits | |
2015 | * 0 Accept=1, Drop=0 | |
2016 | * 3-1 Queue ETH_Q0=0 | |
2017 | * 7-4 Reserved = 0; | |
2018 | */ | |
2019 | mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101); | |
2020 | } | |
16e03018 DF |
2021 | return; |
2022 | } | |
2023 | ||
2024 | /* We will clear out multicast tables every time we get the list. | |
2025 | * Then add the entire new list... | |
2026 | */ | |
2027 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { | |
2028 | /* Clear DA filter special multicast table (Ex_dFSMT) */ | |
2029 | mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE | |
2030 | (eth_port_num) + table_index, 0); | |
2031 | ||
2032 | /* Clear DA filter other multicast table (Ex_dFOMT) */ | |
2033 | mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE | |
2034 | (eth_port_num) + table_index, 0); | |
2035 | } | |
2036 | ||
2037 | /* Get pointer to net_device multicast list and add each one... */ | |
2038 | for (i = 0, mc_list = dev->mc_list; | |
2039 | (i < 256) && (mc_list != NULL) && (i < dev->mc_count); | |
2040 | i++, mc_list = mc_list->next) | |
2041 | if (mc_list->dmi_addrlen == 6) | |
2042 | eth_port_mc_addr(eth_port_num, mc_list->dmi_addr); | |
2043 | } | |
2044 | ||
1da177e4 LT |
2045 | /* |
2046 | * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables | |
2047 | * | |
2048 | * DESCRIPTION: | |
2049 | * Go through all the DA filter tables (Unicast, Special Multicast & | |
2050 | * Other Multicast) and set each entry to 0. | |
2051 | * | |
2052 | * INPUT: | |
2053 | * unsigned int eth_port_num Ethernet Port number. | |
2054 | * | |
2055 | * OUTPUT: | |
2056 | * Multicast and Unicast packets are rejected. | |
2057 | * | |
2058 | * RETURN: | |
2059 | * None. | |
2060 | */ | |
2061 | static void eth_port_init_mac_tables(unsigned int eth_port_num) | |
2062 | { | |
2063 | int table_index; | |
2064 | ||
2065 | /* Clear DA filter unicast table (Ex_dFUT) */ | |
2066 | for (table_index = 0; table_index <= 0xC; table_index += 4) | |
cf4086c7 DF |
2067 | mv_write(MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE |
2068 | (eth_port_num) + table_index, 0); | |
1da177e4 LT |
2069 | |
2070 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { | |
2071 | /* Clear DA filter special multicast table (Ex_dFSMT) */ | |
16e03018 DF |
2072 | mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE |
2073 | (eth_port_num) + table_index, 0); | |
1da177e4 | 2074 | /* Clear DA filter other multicast table (Ex_dFOMT) */ |
16e03018 DF |
2075 | mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE |
2076 | (eth_port_num) + table_index, 0); | |
1da177e4 LT |
2077 | } |
2078 | } | |
2079 | ||
2080 | /* | |
2081 | * eth_clear_mib_counters - Clear all MIB counters | |
2082 | * | |
2083 | * DESCRIPTION: | |
2084 | * This function clears all MIB counters of a specific ethernet port. | |
2085 | * A read from the MIB counter will reset the counter. | |
2086 | * | |
2087 | * INPUT: | |
2088 | * unsigned int eth_port_num Ethernet Port number. | |
2089 | * | |
2090 | * OUTPUT: | |
2091 | * After reading all MIB counters, the counters resets. | |
2092 | * | |
2093 | * RETURN: | |
2094 | * MIB counter value. | |
2095 | * | |
2096 | */ | |
2097 | static void eth_clear_mib_counters(unsigned int eth_port_num) | |
2098 | { | |
2099 | int i; | |
2100 | ||
2101 | /* Perform dummy reads from MIB counters */ | |
2102 | for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; | |
2103 | i += 4) | |
2104 | mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num) + i); | |
2105 | } | |
2106 | ||
2107 | static inline u32 read_mib(struct mv643xx_private *mp, int offset) | |
2108 | { | |
2109 | return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp->port_num) + offset); | |
2110 | } | |
2111 | ||
2112 | static void eth_update_mib_counters(struct mv643xx_private *mp) | |
2113 | { | |
2114 | struct mv643xx_mib_counters *p = &mp->mib_counters; | |
2115 | int offset; | |
2116 | ||
2117 | p->good_octets_received += | |
2118 | read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW); | |
2119 | p->good_octets_received += | |
2120 | (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32; | |
2121 | ||
2122 | for (offset = ETH_MIB_BAD_OCTETS_RECEIVED; | |
2123 | offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS; | |
2124 | offset += 4) | |
70fbf327 | 2125 | *(u32 *)((char *)p + offset) += read_mib(mp, offset); |
1da177e4 LT |
2126 | |
2127 | p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW); | |
2128 | p->good_octets_sent += | |
2129 | (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32; | |
2130 | ||
2131 | for (offset = ETH_MIB_GOOD_FRAMES_SENT; | |
2132 | offset <= ETH_MIB_LATE_COLLISION; | |
2133 | offset += 4) | |
70fbf327 | 2134 | *(u32 *)((char *)p + offset) += read_mib(mp, offset); |
1da177e4 LT |
2135 | } |
2136 | ||
2137 | /* | |
2138 | * ethernet_phy_detect - Detect whether a phy is present | |
2139 | * | |
2140 | * DESCRIPTION: | |
2141 | * This function tests whether there is a PHY present on | |
2142 | * the specified port. | |
2143 | * | |
2144 | * INPUT: | |
2145 | * unsigned int eth_port_num Ethernet Port number. | |
2146 | * | |
2147 | * OUTPUT: | |
2148 | * None | |
2149 | * | |
2150 | * RETURN: | |
2151 | * 0 on success | |
2152 | * -ENODEV on failure | |
2153 | * | |
2154 | */ | |
2155 | static int ethernet_phy_detect(unsigned int port_num) | |
2156 | { | |
2157 | unsigned int phy_reg_data0; | |
2158 | int auto_neg; | |
2159 | ||
2160 | eth_port_read_smi_reg(port_num, 0, &phy_reg_data0); | |
2161 | auto_neg = phy_reg_data0 & 0x1000; | |
2162 | phy_reg_data0 ^= 0x1000; /* invert auto_neg */ | |
2163 | eth_port_write_smi_reg(port_num, 0, phy_reg_data0); | |
2164 | ||
2165 | eth_port_read_smi_reg(port_num, 0, &phy_reg_data0); | |
2166 | if ((phy_reg_data0 & 0x1000) == auto_neg) | |
2167 | return -ENODEV; /* change didn't take */ | |
2168 | ||
2169 | phy_reg_data0 ^= 0x1000; | |
2170 | eth_port_write_smi_reg(port_num, 0, phy_reg_data0); | |
2171 | return 0; | |
2172 | } | |
2173 | ||
2174 | /* | |
2175 | * ethernet_phy_get - Get the ethernet port PHY address. | |
2176 | * | |
2177 | * DESCRIPTION: | |
2178 | * This routine returns the given ethernet port PHY address. | |
2179 | * | |
2180 | * INPUT: | |
2181 | * unsigned int eth_port_num Ethernet Port number. | |
2182 | * | |
2183 | * OUTPUT: | |
2184 | * None. | |
2185 | * | |
2186 | * RETURN: | |
2187 | * PHY address. | |
2188 | * | |
2189 | */ | |
2190 | static int ethernet_phy_get(unsigned int eth_port_num) | |
2191 | { | |
2192 | unsigned int reg_data; | |
2193 | ||
2194 | reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG); | |
2195 | ||
2196 | return ((reg_data >> (5 * eth_port_num)) & 0x1f); | |
2197 | } | |
2198 | ||
2199 | /* | |
2200 | * ethernet_phy_set - Set the ethernet port PHY address. | |
2201 | * | |
2202 | * DESCRIPTION: | |
2203 | * This routine sets the given ethernet port PHY address. | |
2204 | * | |
2205 | * INPUT: | |
2206 | * unsigned int eth_port_num Ethernet Port number. | |
2207 | * int phy_addr PHY address. | |
2208 | * | |
2209 | * OUTPUT: | |
2210 | * None. | |
2211 | * | |
2212 | * RETURN: | |
2213 | * None. | |
2214 | * | |
2215 | */ | |
2216 | static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr) | |
2217 | { | |
2218 | u32 reg_data; | |
2219 | int addr_shift = 5 * eth_port_num; | |
2220 | ||
2221 | reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG); | |
2222 | reg_data &= ~(0x1f << addr_shift); | |
2223 | reg_data |= (phy_addr & 0x1f) << addr_shift; | |
2224 | mv_write(MV643XX_ETH_PHY_ADDR_REG, reg_data); | |
2225 | } | |
2226 | ||
2227 | /* | |
2228 | * ethernet_phy_reset - Reset Ethernet port PHY. | |
2229 | * | |
2230 | * DESCRIPTION: | |
2231 | * This routine utilizes the SMI interface to reset the ethernet port PHY. | |
2232 | * | |
2233 | * INPUT: | |
2234 | * unsigned int eth_port_num Ethernet Port number. | |
2235 | * | |
2236 | * OUTPUT: | |
2237 | * The PHY is reset. | |
2238 | * | |
2239 | * RETURN: | |
2240 | * None. | |
2241 | * | |
2242 | */ | |
2243 | static void ethernet_phy_reset(unsigned int eth_port_num) | |
2244 | { | |
2245 | unsigned int phy_reg_data; | |
2246 | ||
2247 | /* Reset the PHY */ | |
2248 | eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data); | |
2249 | phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */ | |
2250 | eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data); | |
d0412d96 JC |
2251 | |
2252 | /* wait for PHY to come out of reset */ | |
2253 | do { | |
2254 | udelay(1); | |
2255 | eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data); | |
2256 | } while (phy_reg_data & 0x8000); | |
1da177e4 LT |
2257 | } |
2258 | ||
9f8dd319 | 2259 | static void mv643xx_eth_port_enable_tx(unsigned int port_num, |
12a87c64 | 2260 | unsigned int queues) |
9f8dd319 | 2261 | { |
12a87c64 | 2262 | mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), queues); |
9f8dd319 DF |
2263 | } |
2264 | ||
2265 | static void mv643xx_eth_port_enable_rx(unsigned int port_num, | |
12a87c64 | 2266 | unsigned int queues) |
9f8dd319 | 2267 | { |
12a87c64 | 2268 | mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), queues); |
9f8dd319 DF |
2269 | } |
2270 | ||
2271 | static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num) | |
2272 | { | |
12a87c64 | 2273 | u32 queues; |
9f8dd319 DF |
2274 | |
2275 | /* Stop Tx port activity. Check port Tx activity. */ | |
12a87c64 | 2276 | queues = mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num)) |
9f8dd319 | 2277 | & 0xFF; |
12a87c64 DF |
2278 | if (queues) { |
2279 | /* Issue stop command for active queues only */ | |
9f8dd319 | 2280 | mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), |
12a87c64 | 2281 | (queues << 8)); |
9f8dd319 DF |
2282 | |
2283 | /* Wait for all Tx activity to terminate. */ | |
2284 | /* Check port cause register that all Tx queues are stopped */ | |
2285 | while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num)) | |
2286 | & 0xFF) | |
2287 | udelay(PHY_WAIT_MICRO_SECONDS); | |
2288 | ||
2289 | /* Wait for Tx FIFO to empty */ | |
2290 | while (mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num)) & | |
2291 | ETH_PORT_TX_FIFO_EMPTY) | |
2292 | udelay(PHY_WAIT_MICRO_SECONDS); | |
2293 | } | |
2294 | ||
12a87c64 | 2295 | return queues; |
9f8dd319 DF |
2296 | } |
2297 | ||
2298 | static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num) | |
2299 | { | |
12a87c64 | 2300 | u32 queues; |
9f8dd319 DF |
2301 | |
2302 | /* Stop Rx port activity. Check port Rx activity. */ | |
12a87c64 | 2303 | queues = mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num)) |
e38fd1a0 | 2304 | & 0xFF; |
12a87c64 DF |
2305 | if (queues) { |
2306 | /* Issue stop command for active queues only */ | |
9f8dd319 | 2307 | mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), |
12a87c64 | 2308 | (queues << 8)); |
9f8dd319 DF |
2309 | |
2310 | /* Wait for all Rx activity to terminate. */ | |
2311 | /* Check port cause register that all Rx queues are stopped */ | |
2312 | while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num)) | |
2313 | & 0xFF) | |
2314 | udelay(PHY_WAIT_MICRO_SECONDS); | |
2315 | } | |
2316 | ||
12a87c64 | 2317 | return queues; |
9f8dd319 DF |
2318 | } |
2319 | ||
1da177e4 LT |
2320 | /* |
2321 | * eth_port_reset - Reset Ethernet port | |
2322 | * | |
2323 | * DESCRIPTION: | |
2324 | * This routine resets the chip by aborting any SDMA engine activity and | |
2325 | * clearing the MIB counters. The Receiver and the Transmit unit are in | |
2326 | * idle state after this command is performed and the port is disabled. | |
2327 | * | |
2328 | * INPUT: | |
2329 | * unsigned int eth_port_num Ethernet Port number. | |
2330 | * | |
2331 | * OUTPUT: | |
2332 | * Channel activity is halted. | |
2333 | * | |
2334 | * RETURN: | |
2335 | * None. | |
2336 | * | |
2337 | */ | |
2338 | static void eth_port_reset(unsigned int port_num) | |
2339 | { | |
2340 | unsigned int reg_data; | |
2341 | ||
9f8dd319 DF |
2342 | mv643xx_eth_port_disable_tx(port_num); |
2343 | mv643xx_eth_port_disable_rx(port_num); | |
1da177e4 LT |
2344 | |
2345 | /* Clear all MIB counters */ | |
2346 | eth_clear_mib_counters(port_num); | |
2347 | ||
2348 | /* Reset the Enable bit in the Configuration Register */ | |
2349 | reg_data = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)); | |
d0412d96 JC |
2350 | reg_data &= ~(MV643XX_ETH_SERIAL_PORT_ENABLE | |
2351 | MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL | | |
2352 | MV643XX_ETH_FORCE_LINK_PASS); | |
1da177e4 LT |
2353 | mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), reg_data); |
2354 | } | |
2355 | ||
1da177e4 | 2356 | |
1da177e4 LT |
2357 | /* |
2358 | * eth_port_read_smi_reg - Read PHY registers | |
2359 | * | |
2360 | * DESCRIPTION: | |
2361 | * This routine utilize the SMI interface to interact with the PHY in | |
2362 | * order to perform PHY register read. | |
2363 | * | |
2364 | * INPUT: | |
2365 | * unsigned int port_num Ethernet Port number. | |
2366 | * unsigned int phy_reg PHY register address offset. | |
2367 | * unsigned int *value Register value buffer. | |
2368 | * | |
2369 | * OUTPUT: | |
2370 | * Write the value of a specified PHY register into given buffer. | |
2371 | * | |
2372 | * RETURN: | |
2373 | * false if the PHY is busy or read data is not in valid state. | |
2374 | * true otherwise. | |
2375 | * | |
2376 | */ | |
2377 | static void eth_port_read_smi_reg(unsigned int port_num, | |
2378 | unsigned int phy_reg, unsigned int *value) | |
2379 | { | |
2380 | int phy_addr = ethernet_phy_get(port_num); | |
2381 | unsigned long flags; | |
2382 | int i; | |
2383 | ||
2384 | /* the SMI register is a shared resource */ | |
2385 | spin_lock_irqsave(&mv643xx_eth_phy_lock, flags); | |
2386 | ||
2387 | /* wait for the SMI register to become available */ | |
2388 | for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) { | |
2389 | if (i == PHY_WAIT_ITERATIONS) { | |
2390 | printk("mv643xx PHY busy timeout, port %d\n", port_num); | |
2391 | goto out; | |
2392 | } | |
2393 | udelay(PHY_WAIT_MICRO_SECONDS); | |
2394 | } | |
2395 | ||
2396 | mv_write(MV643XX_ETH_SMI_REG, | |
2397 | (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ); | |
2398 | ||
2399 | /* now wait for the data to be valid */ | |
2400 | for (i = 0; !(mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_READ_VALID); i++) { | |
2401 | if (i == PHY_WAIT_ITERATIONS) { | |
2402 | printk("mv643xx PHY read timeout, port %d\n", port_num); | |
2403 | goto out; | |
2404 | } | |
2405 | udelay(PHY_WAIT_MICRO_SECONDS); | |
2406 | } | |
2407 | ||
2408 | *value = mv_read(MV643XX_ETH_SMI_REG) & 0xffff; | |
2409 | out: | |
2410 | spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags); | |
2411 | } | |
2412 | ||
2413 | /* | |
2414 | * eth_port_write_smi_reg - Write to PHY registers | |
2415 | * | |
2416 | * DESCRIPTION: | |
2417 | * This routine utilize the SMI interface to interact with the PHY in | |
2418 | * order to perform writes to PHY registers. | |
2419 | * | |
2420 | * INPUT: | |
2421 | * unsigned int eth_port_num Ethernet Port number. | |
2422 | * unsigned int phy_reg PHY register address offset. | |
2423 | * unsigned int value Register value. | |
2424 | * | |
2425 | * OUTPUT: | |
2426 | * Write the given value to the specified PHY register. | |
2427 | * | |
2428 | * RETURN: | |
2429 | * false if the PHY is busy. | |
2430 | * true otherwise. | |
2431 | * | |
2432 | */ | |
2433 | static void eth_port_write_smi_reg(unsigned int eth_port_num, | |
2434 | unsigned int phy_reg, unsigned int value) | |
2435 | { | |
2436 | int phy_addr; | |
2437 | int i; | |
2438 | unsigned long flags; | |
2439 | ||
2440 | phy_addr = ethernet_phy_get(eth_port_num); | |
2441 | ||
2442 | /* the SMI register is a shared resource */ | |
2443 | spin_lock_irqsave(&mv643xx_eth_phy_lock, flags); | |
2444 | ||
2445 | /* wait for the SMI register to become available */ | |
2446 | for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) { | |
2447 | if (i == PHY_WAIT_ITERATIONS) { | |
2448 | printk("mv643xx PHY busy timeout, port %d\n", | |
2449 | eth_port_num); | |
2450 | goto out; | |
2451 | } | |
2452 | udelay(PHY_WAIT_MICRO_SECONDS); | |
2453 | } | |
2454 | ||
2455 | mv_write(MV643XX_ETH_SMI_REG, (phy_addr << 16) | (phy_reg << 21) | | |
2456 | ETH_SMI_OPCODE_WRITE | (value & 0xffff)); | |
2457 | out: | |
2458 | spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags); | |
2459 | } | |
2460 | ||
c28a4f89 JC |
2461 | /* |
2462 | * Wrappers for MII support library. | |
2463 | */ | |
2464 | static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location) | |
2465 | { | |
2466 | int val; | |
2467 | struct mv643xx_private *mp = netdev_priv(dev); | |
2468 | ||
2469 | eth_port_read_smi_reg(mp->port_num, location, &val); | |
2470 | return val; | |
2471 | } | |
2472 | ||
2473 | static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val) | |
2474 | { | |
2475 | struct mv643xx_private *mp = netdev_priv(dev); | |
2476 | eth_port_write_smi_reg(mp->port_num, location, val); | |
2477 | } | |
2478 | ||
1da177e4 LT |
2479 | /* |
2480 | * eth_port_receive - Get received information from Rx ring. | |
2481 | * | |
2482 | * DESCRIPTION: | |
2483 | * This routine returns the received data to the caller. There is no | |
2484 | * data copying during routine operation. All information is returned | |
2485 | * using pointer to packet information struct passed from the caller. | |
2486 | * If the routine exhausts Rx ring resources then the resource error flag | |
2487 | * is set. | |
2488 | * | |
2489 | * INPUT: | |
2490 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
2491 | * struct pkt_info *p_pkt_info User packet buffer. | |
2492 | * | |
2493 | * OUTPUT: | |
2494 | * Rx ring current and used indexes are updated. | |
2495 | * | |
2496 | * RETURN: | |
2497 | * ETH_ERROR in case the routine can not access Rx desc ring. | |
2498 | * ETH_QUEUE_FULL if Rx ring resources are exhausted. | |
2499 | * ETH_END_OF_JOB if there is no received data. | |
2500 | * ETH_OK otherwise. | |
2501 | */ | |
2502 | static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp, | |
2503 | struct pkt_info *p_pkt_info) | |
2504 | { | |
2505 | int rx_next_curr_desc, rx_curr_desc, rx_used_desc; | |
2506 | volatile struct eth_rx_desc *p_rx_desc; | |
2507 | unsigned int command_status; | |
8f518703 | 2508 | unsigned long flags; |
1da177e4 LT |
2509 | |
2510 | /* Do not process Rx ring in case of Rx ring resource error */ | |
2511 | if (mp->rx_resource_err) | |
2512 | return ETH_QUEUE_FULL; | |
2513 | ||
8f518703 DF |
2514 | spin_lock_irqsave(&mp->lock, flags); |
2515 | ||
1da177e4 LT |
2516 | /* Get the Rx Desc ring 'curr and 'used' indexes */ |
2517 | rx_curr_desc = mp->rx_curr_desc_q; | |
2518 | rx_used_desc = mp->rx_used_desc_q; | |
2519 | ||
2520 | p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc]; | |
2521 | ||
2522 | /* The following parameters are used to save readings from memory */ | |
2523 | command_status = p_rx_desc->cmd_sts; | |
2524 | rmb(); | |
2525 | ||
2526 | /* Nothing to receive... */ | |
8f518703 DF |
2527 | if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { |
2528 | spin_unlock_irqrestore(&mp->lock, flags); | |
1da177e4 | 2529 | return ETH_END_OF_JOB; |
8f518703 | 2530 | } |
1da177e4 LT |
2531 | |
2532 | p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET; | |
2533 | p_pkt_info->cmd_sts = command_status; | |
2534 | p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET; | |
2535 | p_pkt_info->return_info = mp->rx_skb[rx_curr_desc]; | |
2536 | p_pkt_info->l4i_chk = p_rx_desc->buf_size; | |
2537 | ||
b4de9051 DF |
2538 | /* |
2539 | * Clean the return info field to indicate that the | |
2540 | * packet has been moved to the upper layers | |
2541 | */ | |
1da177e4 LT |
2542 | mp->rx_skb[rx_curr_desc] = NULL; |
2543 | ||
2544 | /* Update current index in data structure */ | |
2545 | rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size; | |
2546 | mp->rx_curr_desc_q = rx_next_curr_desc; | |
2547 | ||
2548 | /* Rx descriptors exhausted. Set the Rx ring resource error flag */ | |
2549 | if (rx_next_curr_desc == rx_used_desc) | |
2550 | mp->rx_resource_err = 1; | |
2551 | ||
8f518703 DF |
2552 | spin_unlock_irqrestore(&mp->lock, flags); |
2553 | ||
1da177e4 LT |
2554 | return ETH_OK; |
2555 | } | |
2556 | ||
2557 | /* | |
2558 | * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring. | |
2559 | * | |
2560 | * DESCRIPTION: | |
2561 | * This routine returns a Rx buffer back to the Rx ring. It retrieves the | |
2562 | * next 'used' descriptor and attached the returned buffer to it. | |
2563 | * In case the Rx ring was in "resource error" condition, where there are | |
2564 | * no available Rx resources, the function resets the resource error flag. | |
2565 | * | |
2566 | * INPUT: | |
2567 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
2568 | * struct pkt_info *p_pkt_info Information on returned buffer. | |
2569 | * | |
2570 | * OUTPUT: | |
2571 | * New available Rx resource in Rx descriptor ring. | |
2572 | * | |
2573 | * RETURN: | |
2574 | * ETH_ERROR in case the routine can not access Rx desc ring. | |
2575 | * ETH_OK otherwise. | |
2576 | */ | |
2577 | static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp, | |
2578 | struct pkt_info *p_pkt_info) | |
2579 | { | |
2580 | int used_rx_desc; /* Where to return Rx resource */ | |
2581 | volatile struct eth_rx_desc *p_used_rx_desc; | |
8f518703 DF |
2582 | unsigned long flags; |
2583 | ||
2584 | spin_lock_irqsave(&mp->lock, flags); | |
1da177e4 LT |
2585 | |
2586 | /* Get 'used' Rx descriptor */ | |
2587 | used_rx_desc = mp->rx_used_desc_q; | |
2588 | p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc]; | |
2589 | ||
2590 | p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr; | |
2591 | p_used_rx_desc->buf_size = p_pkt_info->byte_cnt; | |
2592 | mp->rx_skb[used_rx_desc] = p_pkt_info->return_info; | |
2593 | ||
2594 | /* Flush the write pipe */ | |
2595 | ||
2596 | /* Return the descriptor to DMA ownership */ | |
2597 | wmb(); | |
2598 | p_used_rx_desc->cmd_sts = | |
2599 | ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; | |
2600 | wmb(); | |
2601 | ||
2602 | /* Move the used descriptor pointer to the next descriptor */ | |
2603 | mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size; | |
2604 | ||
2605 | /* Any Rx return cancels the Rx resource error status */ | |
2606 | mp->rx_resource_err = 0; | |
2607 | ||
8f518703 DF |
2608 | spin_unlock_irqrestore(&mp->lock, flags); |
2609 | ||
1da177e4 LT |
2610 | return ETH_OK; |
2611 | } | |
2612 | ||
2613 | /************* Begin ethtool support *************************/ | |
2614 | ||
2615 | struct mv643xx_stats { | |
2616 | char stat_string[ETH_GSTRING_LEN]; | |
2617 | int sizeof_stat; | |
2618 | int stat_offset; | |
2619 | }; | |
2620 | ||
2621 | #define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \ | |
b4de9051 | 2622 | offsetof(struct mv643xx_private, m) |
1da177e4 LT |
2623 | |
2624 | static const struct mv643xx_stats mv643xx_gstrings_stats[] = { | |
2625 | { "rx_packets", MV643XX_STAT(stats.rx_packets) }, | |
2626 | { "tx_packets", MV643XX_STAT(stats.tx_packets) }, | |
2627 | { "rx_bytes", MV643XX_STAT(stats.rx_bytes) }, | |
2628 | { "tx_bytes", MV643XX_STAT(stats.tx_bytes) }, | |
2629 | { "rx_errors", MV643XX_STAT(stats.rx_errors) }, | |
2630 | { "tx_errors", MV643XX_STAT(stats.tx_errors) }, | |
2631 | { "rx_dropped", MV643XX_STAT(stats.rx_dropped) }, | |
2632 | { "tx_dropped", MV643XX_STAT(stats.tx_dropped) }, | |
2633 | { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) }, | |
2634 | { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) }, | |
2635 | { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) }, | |
2636 | { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) }, | |
2637 | { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) }, | |
2638 | { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) }, | |
2639 | { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) }, | |
2640 | { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) }, | |
2641 | { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) }, | |
2642 | { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) }, | |
2643 | { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) }, | |
2644 | { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) }, | |
2645 | { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) }, | |
2646 | { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) }, | |
2647 | { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) }, | |
2648 | { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) }, | |
2649 | { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) }, | |
2650 | { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) }, | |
2651 | { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) }, | |
2652 | { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) }, | |
2653 | { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) }, | |
2654 | { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) }, | |
2655 | { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) }, | |
2656 | { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) }, | |
2657 | { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) }, | |
2658 | { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) }, | |
2659 | { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) }, | |
2660 | { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) }, | |
2661 | { "collision", MV643XX_STAT(mib_counters.collision) }, | |
2662 | { "late_collision", MV643XX_STAT(mib_counters.late_collision) }, | |
2663 | }; | |
2664 | ||
ff8ac609 | 2665 | #define MV643XX_STATS_LEN ARRAY_SIZE(mv643xx_gstrings_stats) |
1da177e4 | 2666 | |
b4de9051 DF |
2667 | static void mv643xx_get_drvinfo(struct net_device *netdev, |
2668 | struct ethtool_drvinfo *drvinfo) | |
1da177e4 LT |
2669 | { |
2670 | strncpy(drvinfo->driver, mv643xx_driver_name, 32); | |
2671 | strncpy(drvinfo->version, mv643xx_driver_version, 32); | |
2672 | strncpy(drvinfo->fw_version, "N/A", 32); | |
2673 | strncpy(drvinfo->bus_info, "mv643xx", 32); | |
2674 | drvinfo->n_stats = MV643XX_STATS_LEN; | |
2675 | } | |
2676 | ||
b9f2c044 | 2677 | static int mv643xx_get_sset_count(struct net_device *netdev, int sset) |
1da177e4 | 2678 | { |
b9f2c044 JG |
2679 | switch (sset) { |
2680 | case ETH_SS_STATS: | |
2681 | return MV643XX_STATS_LEN; | |
2682 | default: | |
2683 | return -EOPNOTSUPP; | |
2684 | } | |
1da177e4 LT |
2685 | } |
2686 | ||
b4de9051 DF |
2687 | static void mv643xx_get_ethtool_stats(struct net_device *netdev, |
2688 | struct ethtool_stats *stats, uint64_t *data) | |
1da177e4 LT |
2689 | { |
2690 | struct mv643xx_private *mp = netdev->priv; | |
2691 | int i; | |
2692 | ||
2693 | eth_update_mib_counters(mp); | |
2694 | ||
b4de9051 | 2695 | for (i = 0; i < MV643XX_STATS_LEN; i++) { |
6aa20a22 | 2696 | char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset; |
b4de9051 | 2697 | data[i] = (mv643xx_gstrings_stats[i].sizeof_stat == |
1da177e4 LT |
2698 | sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p; |
2699 | } | |
2700 | } | |
2701 | ||
b4de9051 DF |
2702 | static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset, |
2703 | uint8_t *data) | |
1da177e4 LT |
2704 | { |
2705 | int i; | |
2706 | ||
2707 | switch(stringset) { | |
2708 | case ETH_SS_STATS: | |
2709 | for (i=0; i < MV643XX_STATS_LEN; i++) { | |
b4de9051 DF |
2710 | memcpy(data + i * ETH_GSTRING_LEN, |
2711 | mv643xx_gstrings_stats[i].stat_string, | |
2712 | ETH_GSTRING_LEN); | |
1da177e4 LT |
2713 | } |
2714 | break; | |
2715 | } | |
2716 | } | |
2717 | ||
d0412d96 JC |
2718 | static u32 mv643xx_eth_get_link(struct net_device *dev) |
2719 | { | |
2720 | struct mv643xx_private *mp = netdev_priv(dev); | |
2721 | ||
2722 | return mii_link_ok(&mp->mii); | |
2723 | } | |
2724 | ||
2725 | static int mv643xx_eth_nway_restart(struct net_device *dev) | |
2726 | { | |
2727 | struct mv643xx_private *mp = netdev_priv(dev); | |
2728 | ||
2729 | return mii_nway_restart(&mp->mii); | |
2730 | } | |
2731 | ||
2732 | static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
2733 | { | |
2734 | struct mv643xx_private *mp = netdev_priv(dev); | |
2735 | ||
2736 | return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL); | |
2737 | } | |
2738 | ||
7282d491 | 2739 | static const struct ethtool_ops mv643xx_ethtool_ops = { |
1da177e4 | 2740 | .get_settings = mv643xx_get_settings, |
d0412d96 | 2741 | .set_settings = mv643xx_set_settings, |
1da177e4 | 2742 | .get_drvinfo = mv643xx_get_drvinfo, |
d0412d96 | 2743 | .get_link = mv643xx_eth_get_link, |
1da177e4 | 2744 | .set_sg = ethtool_op_set_sg, |
1da177e4 | 2745 | .get_ethtool_stats = mv643xx_get_ethtool_stats, |
d0412d96 | 2746 | .get_strings = mv643xx_get_strings, |
d0412d96 | 2747 | .nway_reset = mv643xx_eth_nway_restart, |
1da177e4 LT |
2748 | }; |
2749 | ||
2750 | /************* End ethtool support *************************/ |