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mv643xx_eth: fix receive checksumming
[deliverable/linux.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
1da177e4
LT		 41#include <linux/tcp.h>
42#include <linux/udp.h>
43#include <linux/etherdevice.h>
1da177e4
LT		 44#include <linux/delay.h>
45#include <linux/ethtool.h>
d052d1be 46#include <linux/platform_device.h>
fbd6a754
LB		 47#include <linux/module.h>
48#include <linux/kernel.h>
49#include <linux/spinlock.h>
50#include <linux/workqueue.h>
51#include <linux/mii.h>
fbd6a754 52#include <linux/mv643xx_eth.h>
1da177e4
LT		 53#include <asm/io.h>
54#include <asm/types.h>
1da177e4 55#include <asm/system.h>
fbd6a754 56
e5371493 57static char mv643xx_eth_driver_name[] = "mv643xx_eth";
c4560318 58static char mv643xx_eth_driver_version[] = "1.3";
c9df406f 59
fbd6a754 60
fbd6a754
LB		 61/*
62 * Registers shared between all ports.
63 */
3cb4667c
LB		 64#define PHY_ADDR 0x0000
65#define SMI_REG 0x0004
45c5d3bc
LB		 66#define SMI_BUSY 0x10000000
67#define SMI_READ_VALID 0x08000000
68#define SMI_OPCODE_READ 0x04000000
69#define SMI_OPCODE_WRITE 0x00000000
70#define ERR_INT_CAUSE 0x0080
71#define ERR_INT_SMI_DONE 0x00000010
72#define ERR_INT_MASK 0x0084
3cb4667c
LB		 73#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
74#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
75#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
76#define WINDOW_BAR_ENABLE 0x0290
77#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 78
79/*
80 * Per-port registers.
81 */
3cb4667c 82#define PORT_CONFIG(p) (0x0400 + ((p) << 10))
d9a073ea 83#define UNICAST_PROMISCUOUS_MODE 0x00000001
3cb4667c
LB		 84#define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
85#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
86#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
87#define SDMA_CONFIG(p) (0x041c + ((p) << 10))
88#define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
89#define PORT_STATUS(p) (0x0444 + ((p) << 10))
a2a41689 90#define TX_FIFO_EMPTY 0x00000400
ae9ae064 91#define TX_IN_PROGRESS 0x00000080
2f7eb47a
LB		 92#define PORT_SPEED_MASK 0x00000030
93#define PORT_SPEED_1000 0x00000010
94#define PORT_SPEED_100 0x00000020
95#define PORT_SPEED_10 0x00000000
96#define FLOW_CONTROL_ENABLED 0x00000008
97#define FULL_DUPLEX 0x00000004
81600eea 98#define LINK_UP 0x00000002
3cb4667c 99#define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
89df5fdc
LB		 100#define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
101#define TX_BW_RATE(p) (0x0450 + ((p) << 10))
3cb4667c 102#define TX_BW_MTU(p) (0x0458 + ((p) << 10))
89df5fdc 103#define TX_BW_BURST(p) (0x045c + ((p) << 10))
3cb4667c 104#define INT_CAUSE(p) (0x0460 + ((p) << 10))
226bb6b7 105#define INT_TX_END 0x07f80000
befefe21 106#define INT_RX 0x000003fc
073a345c 107#define INT_EXT 0x00000002
3cb4667c 108#define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
befefe21
LB		 109#define INT_EXT_LINK_PHY 0x00110000
110#define INT_EXT_TX 0x000000ff
3cb4667c
LB		 111#define INT_MASK(p) (0x0468 + ((p) << 10))
112#define INT_MASK_EXT(p) (0x046c + ((p) << 10))
113#define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
1e881592
LB		 114#define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
115#define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
116#define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
117#define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
64da80a2 118#define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
3cb4667c 119#define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
3d6b35bc
LB		 120#define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
121#define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
122#define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
123#define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
3cb4667c
LB		 124#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
125#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
126#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
127#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 128
2679a550
LB		 129
130/*
131 * SDMA configuration register.
132 */
cd4ccf76 133#define RX_BURST_SIZE_16_64BIT (4 << 1)
fbd6a754 134#define BLM_RX_NO_SWAP (1 << 4)
fbd6a754 135#define BLM_TX_NO_SWAP (1 << 5)
cd4ccf76 136#define TX_BURST_SIZE_16_64BIT (4 << 22)
fbd6a754
LB		 137
138#if defined(__BIG_ENDIAN)
139#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
cd4ccf76
LB		 140 RX_BURST_SIZE_16_64BIT | \
141 TX_BURST_SIZE_16_64BIT
fbd6a754
LB		 142#elif defined(__LITTLE_ENDIAN)
143#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
cd4ccf76 144 RX_BURST_SIZE_16_64BIT | \
fbd6a754
LB		 145 BLM_RX_NO_SWAP | \
146 BLM_TX_NO_SWAP | \
cd4ccf76 147 TX_BURST_SIZE_16_64BIT
fbd6a754
LB		 148#else
149#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
150#endif
151
2beff77b
LB		 152
153/*
154 * Port serial control register.
155 */
156#define SET_MII_SPEED_TO_100 (1 << 24)
157#define SET_GMII_SPEED_TO_1000 (1 << 23)
158#define SET_FULL_DUPLEX_MODE (1 << 21)
fbd6a754 159#define MAX_RX_PACKET_9700BYTE (5 << 17)
2beff77b
LB		 160#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
161#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
162#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
163#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
164#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
165#define FORCE_LINK_PASS (1 << 1)
166#define SERIAL_PORT_ENABLE (1 << 0)
fbd6a754 167
2b4a624d
LB		 168#define DEFAULT_RX_QUEUE_SIZE 128
169#define DEFAULT_TX_QUEUE_SIZE 256
fbd6a754 170
fbd6a754 171
7ca72a3b
LB		 172/*
173 * RX/TX descriptors.
fbd6a754
LB		 174 */
175#if defined(__BIG_ENDIAN)
cc9754b3 176struct rx_desc {
fbd6a754
LB		 177 u16 byte_cnt; /* Descriptor buffer byte count */
178 u16 buf_size; /* Buffer size */
179 u32 cmd_sts; /* Descriptor command status */
180 u32 next_desc_ptr; /* Next descriptor pointer */
181 u32 buf_ptr; /* Descriptor buffer pointer */
182};
183
cc9754b3 184struct tx_desc {
fbd6a754
LB		 185 u16 byte_cnt; /* buffer byte count */
186 u16 l4i_chk; /* CPU provided TCP checksum */
187 u32 cmd_sts; /* Command/status field */
188 u32 next_desc_ptr; /* Pointer to next descriptor */
189 u32 buf_ptr; /* pointer to buffer for this descriptor*/
190};
191#elif defined(__LITTLE_ENDIAN)
cc9754b3 192struct rx_desc {
fbd6a754
LB		 193 u32 cmd_sts; /* Descriptor command status */
194 u16 buf_size; /* Buffer size */
195 u16 byte_cnt; /* Descriptor buffer byte count */
196 u32 buf_ptr; /* Descriptor buffer pointer */
197 u32 next_desc_ptr; /* Next descriptor pointer */
198};
199
cc9754b3 200struct tx_desc {
fbd6a754
LB		 201 u32 cmd_sts; /* Command/status field */
202 u16 l4i_chk; /* CPU provided TCP checksum */
203 u16 byte_cnt; /* buffer byte count */
204 u32 buf_ptr; /* pointer to buffer for this descriptor*/
205 u32 next_desc_ptr; /* Pointer to next descriptor */
206};
207#else
208#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
209#endif
210
7ca72a3b 211/* RX & TX descriptor command */
cc9754b3 212#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 213
214/* RX & TX descriptor status */
cc9754b3 215#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 216
217/* RX descriptor status */
cc9754b3
LB		 218#define LAYER_4_CHECKSUM_OK 0x40000000
219#define RX_ENABLE_INTERRUPT 0x20000000
220#define RX_FIRST_DESC 0x08000000
221#define RX_LAST_DESC 0x04000000
7ca72a3b
LB		 222
223/* TX descriptor command */
cc9754b3
LB		 224#define TX_ENABLE_INTERRUPT 0x00800000
225#define GEN_CRC 0x00400000
226#define TX_FIRST_DESC 0x00200000
227#define TX_LAST_DESC 0x00100000
228#define ZERO_PADDING 0x00080000
229#define GEN_IP_V4_CHECKSUM 0x00040000
230#define GEN_TCP_UDP_CHECKSUM 0x00020000
231#define UDP_FRAME 0x00010000
e32b6617
LB		 232#define MAC_HDR_EXTRA_4_BYTES 0x00008000
233#define MAC_HDR_EXTRA_8_BYTES 0x00000200
7ca72a3b 234
cc9754b3 235#define TX_IHL_SHIFT 11
7ca72a3b
LB		 236
237
c9df406f 238/* global *******************************************************************/
e5371493 239struct mv643xx_eth_shared_private {
fc32b0e2
LB		 240 /*
241 * Ethernet controller base address.
242 */
cc9754b3 243 void __iomem *base;
c9df406f 244
fc0eb9f2
LB		 245 /*
246 * Points at the right SMI instance to use.
247 */
248 struct mv643xx_eth_shared_private *smi;
249
fc32b0e2
LB		 250 /*
251 * Protects access to SMI_REG, which is shared between ports.
252 */
2b3ba0e3 253 struct mutex phy_lock;
c9df406f 254
45c5d3bc
LB		 255 /*
256 * If we have access to the error interrupt pin (which is
257 * somewhat misnamed as it not only reflects internal errors
258 * but also reflects SMI completion), use that to wait for
259 * SMI access completion instead of polling the SMI busy bit.
260 */
261 int err_interrupt;
262 wait_queue_head_t smi_busy_wait;
263
fc32b0e2
LB		 264 /*
265 * Per-port MBUS window access register value.
266 */
c9df406f
LB		 267 u32 win_protect;
268
fc32b0e2
LB		 269 /*
270 * Hardware-specific parameters.
271 */
c9df406f 272 unsigned int t_clk;
773fc3ee 273 int extended_rx_coal_limit;
457b1d5a 274 int tx_bw_control;
c9df406f
LB		 275};
276
457b1d5a
LB		 277#define TX_BW_CONTROL_ABSENT 0
278#define TX_BW_CONTROL_OLD_LAYOUT 1
279#define TX_BW_CONTROL_NEW_LAYOUT 2
280
c9df406f
LB		 281
282/* per-port *****************************************************************/
e5371493 283struct mib_counters {
fbd6a754
LB		 284 u64 good_octets_received;
285 u32 bad_octets_received;
286 u32 internal_mac_transmit_err;
287 u32 good_frames_received;
288 u32 bad_frames_received;
289 u32 broadcast_frames_received;
290 u32 multicast_frames_received;
291 u32 frames_64_octets;
292 u32 frames_65_to_127_octets;
293 u32 frames_128_to_255_octets;
294 u32 frames_256_to_511_octets;
295 u32 frames_512_to_1023_octets;
296 u32 frames_1024_to_max_octets;
297 u64 good_octets_sent;
298 u32 good_frames_sent;
299 u32 excessive_collision;
300 u32 multicast_frames_sent;
301 u32 broadcast_frames_sent;
302 u32 unrec_mac_control_received;
303 u32 fc_sent;
304 u32 good_fc_received;
305 u32 bad_fc_received;
306 u32 undersize_received;
307 u32 fragments_received;
308 u32 oversize_received;
309 u32 jabber_received;
310 u32 mac_receive_error;
311 u32 bad_crc_event;
312 u32 collision;
313 u32 late_collision;
314};
315
8a578111 316struct rx_queue {
64da80a2
LB		 317 int index;
318
8a578111
LB		 319 int rx_ring_size;
320
321 int rx_desc_count;
322 int rx_curr_desc;
323 int rx_used_desc;
324
325 struct rx_desc *rx_desc_area;
326 dma_addr_t rx_desc_dma;
327 int rx_desc_area_size;
328 struct sk_buff **rx_skb;
8a578111
LB		 329};
330
13d64285 331struct tx_queue {
3d6b35bc
LB		 332 int index;
333
13d64285 334 int tx_ring_size;
fbd6a754 335
13d64285
LB		 336 int tx_desc_count;
337 int tx_curr_desc;
338 int tx_used_desc;
fbd6a754 339
5daffe94 340 struct tx_desc *tx_desc_area;
fbd6a754
LB		 341 dma_addr_t tx_desc_dma;
342 int tx_desc_area_size;
99ab08e0
LB		 343
344 struct sk_buff_head tx_skb;
8fd89211
LB		 345
346 unsigned long tx_packets;
347 unsigned long tx_bytes;
348 unsigned long tx_dropped;
13d64285
LB		 349};
350
351struct mv643xx_eth_private {
352 struct mv643xx_eth_shared_private *shared;
fc32b0e2 353 int port_num;
13d64285 354
fc32b0e2 355 struct net_device *dev;
fbd6a754 356
fc32b0e2 357 int phy_addr;
fbd6a754 358
fc32b0e2
LB		 359 struct mib_counters mib_counters;
360 struct work_struct tx_timeout_task;
fbd6a754 361 struct mii_if_info mii;
8a578111 362
1fa38c58
LB		 363 struct napi_struct napi;
364 u8 work_link;
365 u8 work_tx;
366 u8 work_tx_end;
367 u8 work_rx;
368 u8 work_rx_refill;
369 u8 work_rx_oom;
370
8a578111
LB		 371 /*
372 * RX state.
373 */
374 int default_rx_ring_size;
375 unsigned long rx_desc_sram_addr;
376 int rx_desc_sram_size;
f7981c1c 377 int rxq_count;
2257e05c 378 struct timer_list rx_oom;
64da80a2 379 struct rx_queue rxq[8];
13d64285
LB		 380
381 /*
382 * TX state.
383 */
384 int default_tx_ring_size;
385 unsigned long tx_desc_sram_addr;
386 int tx_desc_sram_size;
f7981c1c 387 int txq_count;
3d6b35bc 388 struct tx_queue txq[8];
fbd6a754 389};
1da177e4 390
fbd6a754 391
c9df406f 392/* port register accessors **************************************************/
e5371493 393static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 394{
cc9754b3 395 return readl(mp->shared->base + offset);
c9df406f 396}
fbd6a754 397
e5371493 398static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 399{
cc9754b3 400 writel(data, mp->shared->base + offset);
c9df406f 401}
fbd6a754 402
fbd6a754 403
c9df406f 404/* rxq/txq helper functions *************************************************/
8a578111 405static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 406{
64da80a2 407 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 408}
fbd6a754 409
13d64285
LB		 410static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
411{
3d6b35bc 412 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 413}
414
8a578111 415static void rxq_enable(struct rx_queue *rxq)
c9df406f 416{
8a578111 417 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 418 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
8a578111 419}
1da177e4 420
8a578111
LB		 421static void rxq_disable(struct rx_queue *rxq)
422{
423 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 424 u8 mask = 1 << rxq->index;
1da177e4 425
8a578111
LB		 426 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
427 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
428 udelay(10);
c9df406f
LB		 429}
430
6b368f68
LB		 431static void txq_reset_hw_ptr(struct tx_queue *txq)
432{
433 struct mv643xx_eth_private *mp = txq_to_mp(txq);
434 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
435 u32 addr;
436
437 addr = (u32)txq->tx_desc_dma;
438 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
439 wrl(mp, off, addr);
440}
441
13d64285 442static void txq_enable(struct tx_queue *txq)
1da177e4 443{
13d64285 444 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 445 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
1da177e4
LT		 446}
447
13d64285 448static void txq_disable(struct tx_queue *txq)
1da177e4 449{
13d64285 450 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 451 u8 mask = 1 << txq->index;
c9df406f 452
13d64285
LB		 453 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
454 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
455 udelay(10);
456}
457
1fa38c58 458static void txq_maybe_wake(struct tx_queue *txq)
13d64285
LB		 459{
460 struct mv643xx_eth_private *mp = txq_to_mp(txq);
e5ef1de1 461 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
3d6b35bc 462
8fd89211
LB		 463 if (netif_tx_queue_stopped(nq)) {
464 __netif_tx_lock(nq, smp_processor_id());
465 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
466 netif_tx_wake_queue(nq);
467 __netif_tx_unlock(nq);
468 }
1da177e4
LT		 469}
470
c9df406f 471
1fa38c58 472/* rx napi ******************************************************************/
8a578111 473static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 474{
8a578111
LB		 475 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
476 struct net_device_stats *stats = &mp->dev->stats;
477 int rx;
1da177e4 478
8a578111 479 rx = 0;
9e1f3772 480 while (rx < budget && rxq->rx_desc_count) {
fc32b0e2 481 struct rx_desc *rx_desc;
96587661 482 unsigned int cmd_sts;
fc32b0e2 483 struct sk_buff *skb;
6b8f90c2 484 u16 byte_cnt;
ff561eef 485
8a578111 486 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 487
96587661 488 cmd_sts = rx_desc->cmd_sts;
2257e05c 489 if (cmd_sts & BUFFER_OWNED_BY_DMA)
96587661 490 break;
96587661 491 rmb();
1da177e4 492
8a578111
LB		 493 skb = rxq->rx_skb[rxq->rx_curr_desc];
494 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 495
9da78745
LB		 496 rxq->rx_curr_desc++;
497 if (rxq->rx_curr_desc == rxq->rx_ring_size)
498 rxq->rx_curr_desc = 0;
ff561eef 499
3a499481 500 dma_unmap_single(NULL, rx_desc->buf_ptr,
abe78717 501 rx_desc->buf_size, DMA_FROM_DEVICE);
8a578111
LB		 502 rxq->rx_desc_count--;
503 rx++;
b1dd9ca1 504
1fa38c58
LB		 505 mp->work_rx_refill |= 1 << rxq->index;
506
6b8f90c2
LB		 507 byte_cnt = rx_desc->byte_cnt;
508
468d09f8
DF		 509 /*
510 * Update statistics.
fc32b0e2
LB		 511 *
512 * Note that the descriptor byte count includes 2 dummy
513 * bytes automatically inserted by the hardware at the
514 * start of the packet (which we don't count), and a 4
515 * byte CRC at the end of the packet (which we do count).
468d09f8 516 */
1da177e4 517 stats->rx_packets++;
6b8f90c2 518 stats->rx_bytes += byte_cnt - 2;
96587661 519
1da177e4 520 /*
fc32b0e2
LB		 521 * In case we received a packet without first / last bits
522 * on, or the error summary bit is set, the packet needs
523 * to be dropped.
1da177e4 524 */
96587661 525 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 526 (RX_FIRST_DESC | RX_LAST_DESC))
96587661 527 || (cmd_sts & ERROR_SUMMARY)) {
1da177e4 528 stats->rx_dropped++;
fc32b0e2 529
96587661 530 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 531 (RX_FIRST_DESC | RX_LAST_DESC)) {
1da177e4 532 if (net_ratelimit())
fc32b0e2
LB		 533 dev_printk(KERN_ERR, &mp->dev->dev,
534 "received packet spanning "
535 "multiple descriptors\n");
1da177e4 536 }
fc32b0e2 537
96587661 538 if (cmd_sts & ERROR_SUMMARY)
1da177e4
LT		 539 stats->rx_errors++;
540
78fff83b 541 dev_kfree_skb(skb);
1da177e4
LT		 542 } else {
543 /*
544 * The -4 is for the CRC in the trailer of the
545 * received packet
546 */
6b8f90c2 547 skb_put(skb, byte_cnt - 2 - 4);
1da177e4 548
170e7108 549 if (cmd_sts & LAYER_4_CHECKSUM_OK)
1da177e4 550 skb->ip_summed = CHECKSUM_UNNECESSARY;
8a578111 551 skb->protocol = eth_type_trans(skb, mp->dev);
1da177e4 552 netif_receive_skb(skb);
1da177e4 553 }
fc32b0e2 554
8a578111 555 mp->dev->last_rx = jiffies;
1da177e4 556 }
fc32b0e2 557
1fa38c58
LB		 558 if (rx < budget)
559 mp->work_rx &= ~(1 << rxq->index);
560
8a578111 561 return rx;
1da177e4
LT		 562}
563
1fa38c58 564static int rxq_refill(struct rx_queue *rxq, int budget)
d0412d96 565{
1fa38c58
LB		 566 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
567 int skb_size;
568 int refilled;
8a578111 569
1fa38c58
LB		 570 /*
571 * Reserve 2+14 bytes for an ethernet header (the hardware
572 * automatically prepends 2 bytes of dummy data to each
573 * received packet), 16 bytes for up to four VLAN tags, and
574 * 4 bytes for the trailing FCS -- 36 bytes total.
575 */
576 skb_size = rxq_to_mp(rxq)->dev->mtu + 36;
d0412d96 577
1fa38c58
LB		 578 /*
579 * Make sure that the skb size is a multiple of 8 bytes, as
580 * the lower three bits of the receive descriptor's buffer
581 * size field are ignored by the hardware.
582 */
583 skb_size = (skb_size + 7) & ~7;
4dfc1c87 584
1fa38c58
LB		 585 refilled = 0;
586 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
587 struct sk_buff *skb;
588 int unaligned;
589 int rx;
d0412d96 590
1fa38c58
LB		 591 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
592 if (skb == NULL) {
593 mp->work_rx_oom |= 1 << rxq->index;
594 goto oom;
595 }
d0412d96 596
1fa38c58
LB		 597 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
598 if (unaligned)
599 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
2257e05c 600
1fa38c58
LB		 601 refilled++;
602 rxq->rx_desc_count++;
c9df406f 603
1fa38c58
LB		 604 rx = rxq->rx_used_desc++;
605 if (rxq->rx_used_desc == rxq->rx_ring_size)
606 rxq->rx_used_desc = 0;
2257e05c 607
1fa38c58
LB		 608 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
609 skb_size, DMA_FROM_DEVICE);
610 rxq->rx_desc_area[rx].buf_size = skb_size;
611 rxq->rx_skb[rx] = skb;
612 wmb();
613 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
614 RX_ENABLE_INTERRUPT;
615 wmb();
2257e05c 616
1fa38c58
LB		 617 /*
618 * The hardware automatically prepends 2 bytes of
619 * dummy data to each received packet, so that the
620 * IP header ends up 16-byte aligned.
621 */
622 skb_reserve(skb, 2);
623 }
624
625 if (refilled < budget)
626 mp->work_rx_refill &= ~(1 << rxq->index);
627
628oom:
629 return refilled;
d0412d96
JC		 630}
631
c9df406f
LB		 632
633/* tx ***********************************************************************/
c9df406f 634static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 635{
13d64285 636 int frag;
1da177e4 637
c9df406f 638 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
13d64285
LB		 639 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
640 if (fragp->size <= 8 && fragp->page_offset & 7)
c9df406f 641 return 1;
1da177e4 642 }
13d64285 643
c9df406f
LB		 644 return 0;
645}
7303fde8 646
13d64285 647static int txq_alloc_desc_index(struct tx_queue *txq)
c9df406f
LB		 648{
649 int tx_desc_curr;
d0412d96 650
13d64285 651 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
1da177e4 652
9da78745
LB		 653 tx_desc_curr = txq->tx_curr_desc++;
654 if (txq->tx_curr_desc == txq->tx_ring_size)
655 txq->tx_curr_desc = 0;
e4d00fa9 656
13d64285 657 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
468d09f8 658
c9df406f
LB		 659 return tx_desc_curr;
660}
468d09f8 661
13d64285 662static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 663{
13d64285 664 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 665 int frag;
1da177e4 666
13d64285
LB		 667 for (frag = 0; frag < nr_frags; frag++) {
668 skb_frag_t *this_frag;
669 int tx_index;
670 struct tx_desc *desc;
671
672 this_frag = &skb_shinfo(skb)->frags[frag];
673 tx_index = txq_alloc_desc_index(txq);
674 desc = &txq->tx_desc_area[tx_index];
675
676 /*
677 * The last fragment will generate an interrupt
678 * which will free the skb on TX completion.
679 */
680 if (frag == nr_frags - 1) {
681 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
682 ZERO_PADDING | TX_LAST_DESC |
683 TX_ENABLE_INTERRUPT;
13d64285
LB		 684 } else {
685 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
13d64285
LB		 686 }
687
c9df406f
LB		 688 desc->l4i_chk = 0;
689 desc->byte_cnt = this_frag->size;
690 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
691 this_frag->page_offset,
692 this_frag->size,
693 DMA_TO_DEVICE);
694 }
1da177e4
LT		 695}
696
c9df406f
LB		 697static inline __be16 sum16_as_be(__sum16 sum)
698{
699 return (__force __be16)sum;
700}
1da177e4 701
13d64285 702static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 703{
8fa89bf5 704 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 705 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 706 int tx_index;
cc9754b3 707 struct tx_desc *desc;
c9df406f
LB		 708 u32 cmd_sts;
709 int length;
1da177e4 710
cc9754b3 711 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
1da177e4 712
13d64285
LB		 713 tx_index = txq_alloc_desc_index(txq);
714 desc = &txq->tx_desc_area[tx_index];
c9df406f
LB		 715
716 if (nr_frags) {
13d64285 717 txq_submit_frag_skb(txq, skb);
c9df406f 718 length = skb_headlen(skb);
c9df406f 719 } else {
cc9754b3 720 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
c9df406f 721 length = skb->len;
c9df406f
LB		 722 }
723
724 desc->byte_cnt = length;
725 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
726
727 if (skb->ip_summed == CHECKSUM_PARTIAL) {
e32b6617
LB		 728 int mac_hdr_len;
729
730 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
731 skb->protocol != htons(ETH_P_8021Q));
c9df406f 732
cc9754b3
LB		 733 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
734 GEN_IP_V4_CHECKSUM |
735 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
c9df406f 736
e32b6617
LB		 737 mac_hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
738 switch (mac_hdr_len - ETH_HLEN) {
739 case 0:
740 break;
741 case 4:
742 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
743 break;
744 case 8:
745 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
746 break;
747 case 12:
748 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
749 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
750 break;
751 default:
752 if (net_ratelimit())
753 dev_printk(KERN_ERR, &txq_to_mp(txq)->dev->dev,
754 "mac header length is %d?!\n", mac_hdr_len);
755 break;
756 }
757
c9df406f
LB		 758 switch (ip_hdr(skb)->protocol) {
759 case IPPROTO_UDP:
cc9754b3 760 cmd_sts |= UDP_FRAME;
c9df406f
LB		 761 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
762 break;
763 case IPPROTO_TCP:
764 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
765 break;
766 default:
767 BUG();
768 }
769 } else {
770 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 771 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 772 desc->l4i_chk = 0;
773 }
774
99ab08e0
LB		 775 __skb_queue_tail(&txq->tx_skb, skb);
776
c9df406f
LB		 777 /* ensure all other descriptors are written before first cmd_sts */
778 wmb();
779 desc->cmd_sts = cmd_sts;
780
1fa38c58
LB		 781 /* clear TX_END status */
782 mp->work_tx_end &= ~(1 << txq->index);
8fa89bf5 783
c9df406f
LB		 784 /* ensure all descriptors are written before poking hardware */
785 wmb();
13d64285 786 txq_enable(txq);
c9df406f 787
13d64285 788 txq->tx_desc_count += nr_frags + 1;
1da177e4 789}
1da177e4 790
fc32b0e2 791static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 792{
e5371493 793 struct mv643xx_eth_private *mp = netdev_priv(dev);
e5ef1de1 794 int queue;
13d64285 795 struct tx_queue *txq;
e5ef1de1 796 struct netdev_queue *nq;
e5ef1de1 797 int entries_left;
afdb57a2 798
8fd89211
LB		 799 queue = skb_get_queue_mapping(skb);
800 txq = mp->txq + queue;
801 nq = netdev_get_tx_queue(dev, queue);
802
c9df406f 803 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
8fd89211 804 txq->tx_dropped++;
fc32b0e2
LB		 805 dev_printk(KERN_DEBUG, &dev->dev,
806 "failed to linearize skb with tiny "
807 "unaligned fragment\n");
c9df406f
LB		 808 return NETDEV_TX_BUSY;
809 }
810
17cd0a59 811 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
e5ef1de1
LB		 812 if (net_ratelimit())
813 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
3d6b35bc
LB		 814 kfree_skb(skb);
815 return NETDEV_TX_OK;
c9df406f
LB		 816 }
817
13d64285 818 txq_submit_skb(txq, skb);
8fd89211
LB		 819 txq->tx_bytes += skb->len;
820 txq->tx_packets++;
c9df406f
LB		 821 dev->trans_start = jiffies;
822
e5ef1de1
LB		 823 entries_left = txq->tx_ring_size - txq->tx_desc_count;
824 if (entries_left < MAX_SKB_FRAGS + 1)
825 netif_tx_stop_queue(nq);
c9df406f 826
c9df406f 827 return NETDEV_TX_OK;
1da177e4
LT		 828}
829
c9df406f 830
1fa38c58
LB		 831/* tx napi ******************************************************************/
832static void txq_kick(struct tx_queue *txq)
833{
834 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 835 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 836 u32 hw_desc_ptr;
837 u32 expected_ptr;
838
8fd89211 839 __netif_tx_lock(nq, smp_processor_id());
1fa38c58
LB		 840
841 if (rdl(mp, TXQ_COMMAND(mp->port_num)) & (1 << txq->index))
842 goto out;
843
844 hw_desc_ptr = rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index));
845 expected_ptr = (u32)txq->tx_desc_dma +
846 txq->tx_curr_desc * sizeof(struct tx_desc);
847
848 if (hw_desc_ptr != expected_ptr)
849 txq_enable(txq);
850
851out:
8fd89211 852 __netif_tx_unlock(nq);
1fa38c58
LB		 853
854 mp->work_tx_end &= ~(1 << txq->index);
855}
856
857static int txq_reclaim(struct tx_queue *txq, int budget, int force)
858{
859 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 860 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 861 int reclaimed;
862
8fd89211 863 __netif_tx_lock(nq, smp_processor_id());
1fa38c58
LB		 864
865 reclaimed = 0;
866 while (reclaimed < budget && txq->tx_desc_count > 0) {
867 int tx_index;
868 struct tx_desc *desc;
869 u32 cmd_sts;
870 struct sk_buff *skb;
1fa38c58
LB		 871
872 tx_index = txq->tx_used_desc;
873 desc = &txq->tx_desc_area[tx_index];
874 cmd_sts = desc->cmd_sts;
875
876 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
877 if (!force)
878 break;
879 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
880 }
881
882 txq->tx_used_desc = tx_index + 1;
883 if (txq->tx_used_desc == txq->tx_ring_size)
884 txq->tx_used_desc = 0;
885
886 reclaimed++;
887 txq->tx_desc_count--;
888
99ab08e0
LB		 889 skb = NULL;
890 if (cmd_sts & TX_LAST_DESC)
891 skb = __skb_dequeue(&txq->tx_skb);
1fa38c58
LB		 892
893 if (cmd_sts & ERROR_SUMMARY) {
894 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
895 mp->dev->stats.tx_errors++;
896 }
897
a418950c
LB		 898 if (cmd_sts & TX_FIRST_DESC) {
899 dma_unmap_single(NULL, desc->buf_ptr,
900 desc->byte_cnt, DMA_TO_DEVICE);
901 } else {
902 dma_unmap_page(NULL, desc->buf_ptr,
903 desc->byte_cnt, DMA_TO_DEVICE);
904 }
1fa38c58
LB		 905
906 if (skb)
907 dev_kfree_skb(skb);
1fa38c58
LB		 908 }
909
8fd89211
LB		 910 __netif_tx_unlock(nq);
911
1fa38c58
LB		 912 if (reclaimed < budget)
913 mp->work_tx &= ~(1 << txq->index);
914
1fa38c58
LB		 915 return reclaimed;
916}
917
918
89df5fdc
LB		 919/* tx rate control **********************************************************/
920/*
921 * Set total maximum TX rate (shared by all TX queues for this port)
922 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
923 */
924static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
925{
926 int token_rate;
927 int mtu;
928 int bucket_size;
929
930 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
931 if (token_rate > 1023)
932 token_rate = 1023;
933
934 mtu = (mp->dev->mtu + 255) >> 8;
935 if (mtu > 63)
936 mtu = 63;
937
938 bucket_size = (burst + 255) >> 8;
939 if (bucket_size > 65535)
940 bucket_size = 65535;
941
457b1d5a
LB		 942 switch (mp->shared->tx_bw_control) {
943 case TX_BW_CONTROL_OLD_LAYOUT:
1e881592
LB		 944 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
945 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
946 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
457b1d5a
LB		 947 break;
948 case TX_BW_CONTROL_NEW_LAYOUT:
949 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
950 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
951 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
952 break;
1e881592 953 }
89df5fdc
LB		 954}
955
956static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
957{
958 struct mv643xx_eth_private *mp = txq_to_mp(txq);
959 int token_rate;
960 int bucket_size;
961
962 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
963 if (token_rate > 1023)
964 token_rate = 1023;
965
966 bucket_size = (burst + 255) >> 8;
967 if (bucket_size > 65535)
968 bucket_size = 65535;
969
3d6b35bc
LB		 970 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
971 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
89df5fdc
LB		 972 (bucket_size << 10) | token_rate);
973}
974
975static void txq_set_fixed_prio_mode(struct tx_queue *txq)
976{
977 struct mv643xx_eth_private *mp = txq_to_mp(txq);
978 int off;
979 u32 val;
980
981 /*
982 * Turn on fixed priority mode.
983 */
457b1d5a
LB		 984 off = 0;
985 switch (mp->shared->tx_bw_control) {
986 case TX_BW_CONTROL_OLD_LAYOUT:
1e881592 987 off = TXQ_FIX_PRIO_CONF(mp->port_num);
457b1d5a
LB		 988 break;
989 case TX_BW_CONTROL_NEW_LAYOUT:
990 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
991 break;
992 }
89df5fdc 993
457b1d5a
LB		 994 if (off) {
995 val = rdl(mp, off);
996 val |= 1 << txq->index;
997 wrl(mp, off, val);
998 }
89df5fdc
LB		 999}
1000
1001static void txq_set_wrr(struct tx_queue *txq, int weight)
1002{
1003 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1004 int off;
1005 u32 val;
1006
1007 /*
1008 * Turn off fixed priority mode.
1009 */
457b1d5a
LB		 1010 off = 0;
1011 switch (mp->shared->tx_bw_control) {
1012 case TX_BW_CONTROL_OLD_LAYOUT:
1e881592 1013 off = TXQ_FIX_PRIO_CONF(mp->port_num);
457b1d5a
LB		 1014 break;
1015 case TX_BW_CONTROL_NEW_LAYOUT:
1016 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
1017 break;
1018 }
89df5fdc 1019
457b1d5a
LB		 1020 if (off) {
1021 val = rdl(mp, off);
1022 val &= ~(1 << txq->index);
1023 wrl(mp, off, val);
89df5fdc 1024
457b1d5a
LB		 1025 /*
1026 * Configure WRR weight for this queue.
1027 */
1028 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
89df5fdc 1029
457b1d5a
LB		 1030 val = rdl(mp, off);
1031 val = (val & ~0xff) | (weight & 0xff);
1032 wrl(mp, off, val);
1033 }
89df5fdc
LB		 1034}
1035
1036
c9df406f 1037/* mii management interface *************************************************/
45c5d3bc
LB		 1038static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1039{
1040 struct mv643xx_eth_shared_private *msp = dev_id;
1041
1042 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1043 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1044 wake_up(&msp->smi_busy_wait);
1045 return IRQ_HANDLED;
1046 }
1047
1048 return IRQ_NONE;
1049}
c9df406f 1050
45c5d3bc 1051static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1da177e4 1052{
45c5d3bc
LB		 1053 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1054}
1da177e4 1055
45c5d3bc
LB		 1056static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1057{
1058 if (msp->err_interrupt == NO_IRQ) {
1059 int i;
c9df406f 1060
45c5d3bc
LB		 1061 for (i = 0; !smi_is_done(msp); i++) {
1062 if (i == 10)
1063 return -ETIMEDOUT;
1064 msleep(10);
c9df406f 1065 }
45c5d3bc
LB		 1066
1067 return 0;
1068 }
1069
1070 if (!wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1071 msecs_to_jiffies(100)))
1072 return -ETIMEDOUT;
1073
1074 return 0;
1075}
1076
1077static int smi_reg_read(struct mv643xx_eth_private *mp,
1078 unsigned int addr, unsigned int reg)
1079{
fc0eb9f2 1080 struct mv643xx_eth_shared_private *msp = mp->shared->smi;
45c5d3bc
LB		 1081 void __iomem *smi_reg = msp->base + SMI_REG;
1082 int ret;
1083
1084 mutex_lock(&msp->phy_lock);
1085
1086 if (smi_wait_ready(msp)) {
1087 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1088 ret = -ETIMEDOUT;
1089 goto out;
1da177e4
LT		 1090 }
1091
fc32b0e2 1092 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 1093
45c5d3bc
LB		 1094 if (smi_wait_ready(msp)) {
1095 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1096 ret = -ETIMEDOUT;
1097 goto out;
1098 }
1099
1100 ret = readl(smi_reg);
1101 if (!(ret & SMI_READ_VALID)) {
1102 printk("%s: SMI bus read not valid\n", mp->dev->name);
1103 ret = -ENODEV;
1104 goto out;
c9df406f
LB		 1105 }
1106
45c5d3bc
LB		 1107 ret &= 0xffff;
1108
c9df406f 1109out:
45c5d3bc
LB		 1110 mutex_unlock(&msp->phy_lock);
1111
1112 return ret;
1da177e4
LT		 1113}
1114
45c5d3bc
LB		 1115static int smi_reg_write(struct mv643xx_eth_private *mp, unsigned int addr,
1116 unsigned int reg, unsigned int value)
1da177e4 1117{
fc0eb9f2 1118 struct mv643xx_eth_shared_private *msp = mp->shared->smi;
45c5d3bc 1119 void __iomem *smi_reg = msp->base + SMI_REG;
1da177e4 1120
45c5d3bc 1121 mutex_lock(&msp->phy_lock);
c9df406f 1122
45c5d3bc
LB		 1123 if (smi_wait_ready(msp)) {
1124 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1125 mutex_unlock(&msp->phy_lock);
1126 return -ETIMEDOUT;
1da177e4
LT		 1127 }
1128
fc32b0e2
LB		 1129 writel(SMI_OPCODE_WRITE | (reg << 21) |
1130 (addr << 16) | (value & 0xffff), smi_reg);
45c5d3bc
LB		 1131
1132 mutex_unlock(&msp->phy_lock);
1133
1134 return 0;
c9df406f 1135}
1da177e4 1136
c9df406f 1137
8fd89211
LB		 1138/* statistics ***************************************************************/
1139static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1140{
1141 struct mv643xx_eth_private *mp = netdev_priv(dev);
1142 struct net_device_stats *stats = &dev->stats;
1143 unsigned long tx_packets = 0;
1144 unsigned long tx_bytes = 0;
1145 unsigned long tx_dropped = 0;
1146 int i;
1147
1148 for (i = 0; i < mp->txq_count; i++) {
1149 struct tx_queue *txq = mp->txq + i;
1150
1151 tx_packets += txq->tx_packets;
1152 tx_bytes += txq->tx_bytes;
1153 tx_dropped += txq->tx_dropped;
1154 }
1155
1156 stats->tx_packets = tx_packets;
1157 stats->tx_bytes = tx_bytes;
1158 stats->tx_dropped = tx_dropped;
1159
1160 return stats;
1161}
1162
fc32b0e2 1163static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 1164{
fc32b0e2 1165 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 1166}
1167
fc32b0e2 1168static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 1169{
fc32b0e2
LB		 1170 int i;
1171
1172 for (i = 0; i < 0x80; i += 4)
1173 mib_read(mp, i);
c9df406f 1174}
d0412d96 1175
fc32b0e2 1176static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 1177{
e5371493 1178 struct mib_counters *p = &mp->mib_counters;
4b8e3655 1179
fc32b0e2
LB		 1180 p->good_octets_received += mib_read(mp, 0x00);
1181 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1182 p->bad_octets_received += mib_read(mp, 0x08);
1183 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1184 p->good_frames_received += mib_read(mp, 0x10);
1185 p->bad_frames_received += mib_read(mp, 0x14);
1186 p->broadcast_frames_received += mib_read(mp, 0x18);
1187 p->multicast_frames_received += mib_read(mp, 0x1c);
1188 p->frames_64_octets += mib_read(mp, 0x20);
1189 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1190 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1191 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1192 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1193 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1194 p->good_octets_sent += mib_read(mp, 0x38);
1195 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1196 p->good_frames_sent += mib_read(mp, 0x40);
1197 p->excessive_collision += mib_read(mp, 0x44);
1198 p->multicast_frames_sent += mib_read(mp, 0x48);
1199 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1200 p->unrec_mac_control_received += mib_read(mp, 0x50);
1201 p->fc_sent += mib_read(mp, 0x54);
1202 p->good_fc_received += mib_read(mp, 0x58);
1203 p->bad_fc_received += mib_read(mp, 0x5c);
1204 p->undersize_received += mib_read(mp, 0x60);
1205 p->fragments_received += mib_read(mp, 0x64);
1206 p->oversize_received += mib_read(mp, 0x68);
1207 p->jabber_received += mib_read(mp, 0x6c);
1208 p->mac_receive_error += mib_read(mp, 0x70);
1209 p->bad_crc_event += mib_read(mp, 0x74);
1210 p->collision += mib_read(mp, 0x78);
1211 p->late_collision += mib_read(mp, 0x7c);
d0412d96
JC		 1212}
1213
c9df406f
LB		 1214
1215/* ethtool ******************************************************************/
e5371493 1216struct mv643xx_eth_stats {
c9df406f
LB		 1217 char stat_string[ETH_GSTRING_LEN];
1218 int sizeof_stat;
16820054
LB		 1219 int netdev_off;
1220 int mp_off;
c9df406f
LB		 1221};
1222
16820054
LB		 1223#define SSTAT(m) \
1224 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1225 offsetof(struct net_device, stats.m), -1 }
1226
1227#define MIBSTAT(m) \
1228 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1229 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1230
1231static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1232 SSTAT(rx_packets),
1233 SSTAT(tx_packets),
1234 SSTAT(rx_bytes),
1235 SSTAT(tx_bytes),
1236 SSTAT(rx_errors),
1237 SSTAT(tx_errors),
1238 SSTAT(rx_dropped),
1239 SSTAT(tx_dropped),
1240 MIBSTAT(good_octets_received),
1241 MIBSTAT(bad_octets_received),
1242 MIBSTAT(internal_mac_transmit_err),
1243 MIBSTAT(good_frames_received),
1244 MIBSTAT(bad_frames_received),
1245 MIBSTAT(broadcast_frames_received),
1246 MIBSTAT(multicast_frames_received),
1247 MIBSTAT(frames_64_octets),
1248 MIBSTAT(frames_65_to_127_octets),
1249 MIBSTAT(frames_128_to_255_octets),
1250 MIBSTAT(frames_256_to_511_octets),
1251 MIBSTAT(frames_512_to_1023_octets),
1252 MIBSTAT(frames_1024_to_max_octets),
1253 MIBSTAT(good_octets_sent),
1254 MIBSTAT(good_frames_sent),
1255 MIBSTAT(excessive_collision),
1256 MIBSTAT(multicast_frames_sent),
1257 MIBSTAT(broadcast_frames_sent),
1258 MIBSTAT(unrec_mac_control_received),
1259 MIBSTAT(fc_sent),
1260 MIBSTAT(good_fc_received),
1261 MIBSTAT(bad_fc_received),
1262 MIBSTAT(undersize_received),
1263 MIBSTAT(fragments_received),
1264 MIBSTAT(oversize_received),
1265 MIBSTAT(jabber_received),
1266 MIBSTAT(mac_receive_error),
1267 MIBSTAT(bad_crc_event),
1268 MIBSTAT(collision),
1269 MIBSTAT(late_collision),
c9df406f
LB		 1270};
1271
e5371493 1272static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
d0412d96 1273{
e5371493 1274 struct mv643xx_eth_private *mp = netdev_priv(dev);
d0412d96
JC		 1275 int err;
1276
d0412d96 1277 err = mii_ethtool_gset(&mp->mii, cmd);
d0412d96 1278
fc32b0e2
LB		 1279 /*
1280 * The MAC does not support 1000baseT_Half.
1281 */
d0412d96
JC		 1282 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1283 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1284
1285 return err;
1286}
1287
bedfe324
LB		 1288static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1289{
81600eea
LB		 1290 struct mv643xx_eth_private *mp = netdev_priv(dev);
1291 u32 port_status;
1292
1293 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1294
bedfe324
LB		 1295 cmd->supported = SUPPORTED_MII;
1296 cmd->advertising = ADVERTISED_MII;
81600eea
LB		 1297 switch (port_status & PORT_SPEED_MASK) {
1298 case PORT_SPEED_10:
1299 cmd->speed = SPEED_10;
1300 break;
1301 case PORT_SPEED_100:
1302 cmd->speed = SPEED_100;
1303 break;
1304 case PORT_SPEED_1000:
1305 cmd->speed = SPEED_1000;
1306 break;
1307 default:
1308 cmd->speed = -1;
1309 break;
1310 }
1311 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
bedfe324
LB		 1312 cmd->port = PORT_MII;
1313 cmd->phy_address = 0;
1314 cmd->transceiver = XCVR_INTERNAL;
1315 cmd->autoneg = AUTONEG_DISABLE;
1316 cmd->maxtxpkt = 1;
1317 cmd->maxrxpkt = 1;
1318
1319 return 0;
1320}
1321
e5371493 1322static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1323{
e5371493 1324 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6 1325
fc32b0e2
LB		 1326 /*
1327 * The MAC does not support 1000baseT_Half.
1328 */
1329 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1330
2b3ba0e3 1331 return mii_ethtool_sset(&mp->mii, cmd);
c9df406f 1332}
1da177e4 1333
bedfe324
LB		 1334static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1335{
1336 return -EINVAL;
1337}
1338
fc32b0e2
LB		 1339static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1340 struct ethtool_drvinfo *drvinfo)
c9df406f 1341{
e5371493
LB		 1342 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1343 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 1344 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 1345 strncpy(drvinfo->bus_info, "platform", 32);
16820054 1346 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1347}
1da177e4 1348
fc32b0e2 1349static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1350{
e5371493 1351 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1352
c9df406f
LB		 1353 return mii_nway_restart(&mp->mii);
1354}
1da177e4 1355
bedfe324
LB		 1356static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1357{
1358 return -EINVAL;
1359}
1360
c9df406f
LB		 1361static u32 mv643xx_eth_get_link(struct net_device *dev)
1362{
e5371493 1363 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1364
c9df406f
LB		 1365 return mii_link_ok(&mp->mii);
1366}
1da177e4 1367
bedfe324
LB		 1368static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1369{
1370 return 1;
1371}
1372
fc32b0e2
LB		 1373static void mv643xx_eth_get_strings(struct net_device *dev,
1374 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1375{
1376 int i;
1da177e4 1377
fc32b0e2
LB		 1378 if (stringset == ETH_SS_STATS) {
1379 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1380 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1381 mv643xx_eth_stats[i].stat_string,
e5371493 1382 ETH_GSTRING_LEN);
c9df406f 1383 }
c9df406f
LB		 1384 }
1385}
1da177e4 1386
fc32b0e2
LB		 1387static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1388 struct ethtool_stats *stats,
1389 uint64_t *data)
c9df406f 1390{
b9873841 1391 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1392 int i;
1da177e4 1393
8fd89211 1394 mv643xx_eth_get_stats(dev);
fc32b0e2 1395 mib_counters_update(mp);
1da177e4 1396
16820054
LB		 1397 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1398 const struct mv643xx_eth_stats *stat;
1399 void *p;
1400
1401 stat = mv643xx_eth_stats + i;
1402
1403 if (stat->netdev_off >= 0)
1404 p = ((void *)mp->dev) + stat->netdev_off;
1405 else
1406 p = ((void *)mp) + stat->mp_off;
1407
1408 data[i] = (stat->sizeof_stat == 8) ?
1409 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1410 }
c9df406f 1411}
1da177e4 1412
fc32b0e2 1413static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1414{
fc32b0e2 1415 if (sset == ETH_SS_STATS)
16820054 1416 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1417
1418 return -EOPNOTSUPP;
c9df406f 1419}
1da177e4 1420
e5371493 1421static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1422 .get_settings = mv643xx_eth_get_settings,
1423 .set_settings = mv643xx_eth_set_settings,
1424 .get_drvinfo = mv643xx_eth_get_drvinfo,
1425 .nway_reset = mv643xx_eth_nway_reset,
1426 .get_link = mv643xx_eth_get_link,
c9df406f 1427 .set_sg = ethtool_op_set_sg,
fc32b0e2
LB		 1428 .get_strings = mv643xx_eth_get_strings,
1429 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
e5371493 1430 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1431};
1da177e4 1432
bedfe324
LB		 1433static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1434 .get_settings = mv643xx_eth_get_settings_phyless,
1435 .set_settings = mv643xx_eth_set_settings_phyless,
1436 .get_drvinfo = mv643xx_eth_get_drvinfo,
1437 .nway_reset = mv643xx_eth_nway_reset_phyless,
1438 .get_link = mv643xx_eth_get_link_phyless,
1439 .set_sg = ethtool_op_set_sg,
1440 .get_strings = mv643xx_eth_get_strings,
1441 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1442 .get_sset_count = mv643xx_eth_get_sset_count,
1443};
1444
bea3348e 1445
c9df406f 1446/* address handling *********************************************************/
5daffe94 1447static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1448{
c9df406f
LB		 1449 unsigned int mac_h;
1450 unsigned int mac_l;
1da177e4 1451
fc32b0e2
LB		 1452 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1453 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1da177e4 1454
5daffe94
LB		 1455 addr[0] = (mac_h >> 24) & 0xff;
1456 addr[1] = (mac_h >> 16) & 0xff;
1457 addr[2] = (mac_h >> 8) & 0xff;
1458 addr[3] = mac_h & 0xff;
1459 addr[4] = (mac_l >> 8) & 0xff;
1460 addr[5] = mac_l & 0xff;
c9df406f 1461}
1da177e4 1462
e5371493 1463static void init_mac_tables(struct mv643xx_eth_private *mp)
c9df406f 1464{
fc32b0e2 1465 int i;
1da177e4 1466
fc32b0e2
LB		 1467 for (i = 0; i < 0x100; i += 4) {
1468 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1469 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
c9df406f 1470 }
fc32b0e2
LB		 1471
1472 for (i = 0; i < 0x10; i += 4)
1473 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
c9df406f 1474}
d0412d96 1475
e5371493 1476static void set_filter_table_entry(struct mv643xx_eth_private *mp,
fc32b0e2 1477 int table, unsigned char entry)
c9df406f
LB		 1478{
1479 unsigned int table_reg;
ab4384a6 1480
c9df406f 1481 /* Set "accepts frame bit" at specified table entry */
fc32b0e2
LB		 1482 table_reg = rdl(mp, table + (entry & 0xfc));
1483 table_reg |= 0x01 << (8 * (entry & 3));
1484 wrl(mp, table + (entry & 0xfc), table_reg);
1da177e4
LT		 1485}
1486
5daffe94 1487static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1da177e4 1488{
c9df406f
LB		 1489 unsigned int mac_h;
1490 unsigned int mac_l;
1491 int table;
1da177e4 1492
fc32b0e2
LB		 1493 mac_l = (addr[4] << 8) | addr[5];
1494 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
ff561eef 1495
fc32b0e2
LB		 1496 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1497 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1da177e4 1498
fc32b0e2 1499 table = UNICAST_TABLE(mp->port_num);
5daffe94 1500 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1da177e4
LT		 1501}
1502
fc32b0e2 1503static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1da177e4 1504{
e5371493 1505 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1506
fc32b0e2
LB		 1507 /* +2 is for the offset of the HW addr type */
1508 memcpy(dev->dev_addr, addr + 2, 6);
1509
cc9754b3
LB		 1510 init_mac_tables(mp);
1511 uc_addr_set(mp, dev->dev_addr);
1da177e4
LT		 1512
1513 return 0;
1514}
1515
69876569
LB		 1516static int addr_crc(unsigned char *addr)
1517{
1518 int crc = 0;
1519 int i;
1520
1521 for (i = 0; i < 6; i++) {
1522 int j;
1523
1524 crc = (crc ^ addr[i]) << 8;
1525 for (j = 7; j >= 0; j--) {
1526 if (crc & (0x100 << j))
1527 crc ^= 0x107 << j;
1528 }
1529 }
1530
1531 return crc;
1532}
1533
fc32b0e2 1534static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1da177e4 1535{
fc32b0e2
LB		 1536 struct mv643xx_eth_private *mp = netdev_priv(dev);
1537 u32 port_config;
1538 struct dev_addr_list *addr;
1539 int i;
c8aaea25 1540
fc32b0e2
LB		 1541 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1542 if (dev->flags & IFF_PROMISC)
1543 port_config |= UNICAST_PROMISCUOUS_MODE;
1544 else
1545 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1546 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1da177e4 1547
fc32b0e2
LB		 1548 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1549 int port_num = mp->port_num;
1550 u32 accept = 0x01010101;
c8aaea25 1551
fc32b0e2
LB		 1552 for (i = 0; i < 0x100; i += 4) {
1553 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1554 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1555 }
1556 return;
1557 }
c8aaea25 1558
fc32b0e2
LB		 1559 for (i = 0; i < 0x100; i += 4) {
1560 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1561 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1da177e4
LT		 1562 }
1563
fc32b0e2
LB		 1564 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1565 u8 *a = addr->da_addr;
1566 int table;
324ff2c1 1567
fc32b0e2
LB		 1568 if (addr->da_addrlen != 6)
1569 continue;
1da177e4 1570
fc32b0e2
LB		 1571 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1572 table = SPECIAL_MCAST_TABLE(mp->port_num);
1573 set_filter_table_entry(mp, table, a[5]);
1574 } else {
1575 int crc = addr_crc(a);
1da177e4 1576
fc32b0e2
LB		 1577 table = OTHER_MCAST_TABLE(mp->port_num);
1578 set_filter_table_entry(mp, table, crc);
1579 }
1580 }
c9df406f 1581}
c8aaea25 1582
c8aaea25 1583
c9df406f 1584/* rx/tx queue initialisation ***********************************************/
64da80a2 1585static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1586{
64da80a2 1587 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1588 struct rx_desc *rx_desc;
1589 int size;
c9df406f
LB		 1590 int i;
1591
64da80a2
LB		 1592 rxq->index = index;
1593
8a578111
LB		 1594 rxq->rx_ring_size = mp->default_rx_ring_size;
1595
1596 rxq->rx_desc_count = 0;
1597 rxq->rx_curr_desc = 0;
1598 rxq->rx_used_desc = 0;
1599
1600 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1601
f7981c1c 1602 if (index == 0 && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1603 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1604 mp->rx_desc_sram_size);
1605 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1606 } else {
1607 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1608 &rxq->rx_desc_dma,
1609 GFP_KERNEL);
f7ea3337
PJ		 1610 }
1611
8a578111
LB		 1612 if (rxq->rx_desc_area == NULL) {
1613 dev_printk(KERN_ERR, &mp->dev->dev,
1614 "can't allocate rx ring (%d bytes)\n", size);
1615 goto out;
1616 }
1617 memset(rxq->rx_desc_area, 0, size);
1da177e4 1618
8a578111
LB		 1619 rxq->rx_desc_area_size = size;
1620 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1621 GFP_KERNEL);
1622 if (rxq->rx_skb == NULL) {
1623 dev_printk(KERN_ERR, &mp->dev->dev,
1624 "can't allocate rx skb ring\n");
1625 goto out_free;
1626 }
1627
1628 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1629 for (i = 0; i < rxq->rx_ring_size; i++) {
9da78745
LB		 1630 int nexti;
1631
1632 nexti = i + 1;
1633 if (nexti == rxq->rx_ring_size)
1634 nexti = 0;
1635
8a578111
LB		 1636 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1637 nexti * sizeof(struct rx_desc);
1638 }
1639
8a578111
LB		 1640 return 0;
1641
1642
1643out_free:
f7981c1c 1644 if (index == 0 && size <= mp->rx_desc_sram_size)
8a578111
LB		 1645 iounmap(rxq->rx_desc_area);
1646 else
1647 dma_free_coherent(NULL, size,
1648 rxq->rx_desc_area,
1649 rxq->rx_desc_dma);
1650
1651out:
1652 return -ENOMEM;
c9df406f 1653}
c8aaea25 1654
8a578111 1655static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1656{
8a578111
LB		 1657 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1658 int i;
1659
1660 rxq_disable(rxq);
c8aaea25 1661
8a578111
LB		 1662 for (i = 0; i < rxq->rx_ring_size; i++) {
1663 if (rxq->rx_skb[i]) {
1664 dev_kfree_skb(rxq->rx_skb[i]);
1665 rxq->rx_desc_count--;
1da177e4 1666 }
c8aaea25 1667 }
1da177e4 1668
8a578111
LB		 1669 if (rxq->rx_desc_count) {
1670 dev_printk(KERN_ERR, &mp->dev->dev,
1671 "error freeing rx ring -- %d skbs stuck\n",
1672 rxq->rx_desc_count);
1673 }
1674
f7981c1c 1675 if (rxq->index == 0 &&
64da80a2 1676 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1677 iounmap(rxq->rx_desc_area);
c9df406f 1678 else
8a578111
LB		 1679 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1680 rxq->rx_desc_area, rxq->rx_desc_dma);
1681
1682 kfree(rxq->rx_skb);
c9df406f 1683}
1da177e4 1684
3d6b35bc 1685static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1686{
3d6b35bc 1687 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1688 struct tx_desc *tx_desc;
1689 int size;
c9df406f 1690 int i;
1da177e4 1691
3d6b35bc
LB		 1692 txq->index = index;
1693
13d64285
LB		 1694 txq->tx_ring_size = mp->default_tx_ring_size;
1695
1696 txq->tx_desc_count = 0;
1697 txq->tx_curr_desc = 0;
1698 txq->tx_used_desc = 0;
1699
1700 size = txq->tx_ring_size * sizeof(struct tx_desc);
1701
f7981c1c 1702 if (index == 0 && size <= mp->tx_desc_sram_size) {
13d64285
LB		 1703 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1704 mp->tx_desc_sram_size);
1705 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1706 } else {
1707 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1708 &txq->tx_desc_dma,
1709 GFP_KERNEL);
1710 }
1711
1712 if (txq->tx_desc_area == NULL) {
1713 dev_printk(KERN_ERR, &mp->dev->dev,
1714 "can't allocate tx ring (%d bytes)\n", size);
99ab08e0 1715 return -ENOMEM;
c9df406f 1716 }
13d64285
LB		 1717 memset(txq->tx_desc_area, 0, size);
1718
1719 txq->tx_desc_area_size = size;
13d64285
LB		 1720
1721 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1722 for (i = 0; i < txq->tx_ring_size; i++) {
6b368f68 1723 struct tx_desc *txd = tx_desc + i;
9da78745
LB		 1724 int nexti;
1725
1726 nexti = i + 1;
1727 if (nexti == txq->tx_ring_size)
1728 nexti = 0;
6b368f68
LB		 1729
1730 txd->cmd_sts = 0;
1731 txd->next_desc_ptr = txq->tx_desc_dma +
13d64285
LB		 1732 nexti * sizeof(struct tx_desc);
1733 }
1734
99ab08e0 1735 skb_queue_head_init(&txq->tx_skb);
c9df406f 1736
99ab08e0 1737 return 0;
c8aaea25 1738}
1da177e4 1739
13d64285 1740static void txq_deinit(struct tx_queue *txq)
c9df406f 1741{
13d64285 1742 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 1743
13d64285 1744 txq_disable(txq);
1fa38c58 1745 txq_reclaim(txq, txq->tx_ring_size, 1);
1da177e4 1746
13d64285 1747 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 1748
f7981c1c 1749 if (txq->index == 0 &&
3d6b35bc 1750 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 1751 iounmap(txq->tx_desc_area);
c9df406f 1752 else
13d64285
LB		 1753 dma_free_coherent(NULL, txq->tx_desc_area_size,
1754 txq->tx_desc_area, txq->tx_desc_dma);
c9df406f 1755}
1da177e4 1756
1da177e4 1757
c9df406f 1758/* netdev ops and related ***************************************************/
1fa38c58
LB		 1759static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1760{
1761 u32 int_cause;
1762 u32 int_cause_ext;
1763
1764 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1765 (INT_TX_END | INT_RX | INT_EXT);
1766 if (int_cause == 0)
1767 return 0;
1768
1769 int_cause_ext = 0;
1770 if (int_cause & INT_EXT)
1771 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num));
1772
1773 int_cause &= INT_TX_END | INT_RX;
1774 if (int_cause) {
1775 wrl(mp, INT_CAUSE(mp->port_num), ~int_cause);
1776 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
1777 ~(rdl(mp, TXQ_COMMAND(mp->port_num)) & 0xff);
1778 mp->work_rx |= (int_cause & INT_RX) >> 2;
1779 }
1780
1781 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
1782 if (int_cause_ext) {
1783 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1784 if (int_cause_ext & INT_EXT_LINK_PHY)
1785 mp->work_link = 1;
1786 mp->work_tx |= int_cause_ext & INT_EXT_TX;
1787 }
1788
1789 return 1;
1790}
1791
1792static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1793{
1794 struct net_device *dev = (struct net_device *)dev_id;
1795 struct mv643xx_eth_private *mp = netdev_priv(dev);
1796
1797 if (unlikely(!mv643xx_eth_collect_events(mp)))
1798 return IRQ_NONE;
1799
1800 wrl(mp, INT_MASK(mp->port_num), 0);
1801 napi_schedule(&mp->napi);
1802
1803 return IRQ_HANDLED;
1804}
1805
2f7eb47a
LB		 1806static void handle_link_event(struct mv643xx_eth_private *mp)
1807{
1808 struct net_device *dev = mp->dev;
1809 u32 port_status;
1810 int speed;
1811 int duplex;
1812 int fc;
1813
1814 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1815 if (!(port_status & LINK_UP)) {
1816 if (netif_carrier_ok(dev)) {
1817 int i;
1818
1819 printk(KERN_INFO "%s: link down\n", dev->name);
1820
1821 netif_carrier_off(dev);
2f7eb47a 1822
f7981c1c 1823 for (i = 0; i < mp->txq_count; i++) {
2f7eb47a
LB		 1824 struct tx_queue *txq = mp->txq + i;
1825
1fa38c58 1826 txq_reclaim(txq, txq->tx_ring_size, 1);
f7981c1c 1827 txq_reset_hw_ptr(txq);
2f7eb47a
LB		 1828 }
1829 }
1830 return;
1831 }
1832
1833 switch (port_status & PORT_SPEED_MASK) {
1834 case PORT_SPEED_10:
1835 speed = 10;
1836 break;
1837 case PORT_SPEED_100:
1838 speed = 100;
1839 break;
1840 case PORT_SPEED_1000:
1841 speed = 1000;
1842 break;
1843 default:
1844 speed = -1;
1845 break;
1846 }
1847 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1848 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1849
1850 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1851 "flow control %sabled\n", dev->name,
1852 speed, duplex ? "full" : "half",
1853 fc ? "en" : "dis");
1854
4fdeca3f 1855 if (!netif_carrier_ok(dev))
2f7eb47a 1856 netif_carrier_on(dev);
2f7eb47a
LB		 1857}
1858
1fa38c58 1859static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
c9df406f 1860{
1fa38c58
LB		 1861 struct mv643xx_eth_private *mp;
1862 int work_done;
ce4e2e45 1863
1fa38c58 1864 mp = container_of(napi, struct mv643xx_eth_private, napi);
fc32b0e2 1865
1fa38c58
LB		 1866 mp->work_rx_refill |= mp->work_rx_oom;
1867 mp->work_rx_oom = 0;
1da177e4 1868
1fa38c58
LB		 1869 work_done = 0;
1870 while (work_done < budget) {
1871 u8 queue_mask;
1872 int queue;
1873 int work_tbd;
1874
1875 if (mp->work_link) {
1876 mp->work_link = 0;
1877 handle_link_event(mp);
1878 continue;
1879 }
1da177e4 1880
1fa38c58
LB		 1881 queue_mask = mp->work_tx | mp->work_tx_end |
1882 mp->work_rx | mp->work_rx_refill;
1883 if (!queue_mask) {
1884 if (mv643xx_eth_collect_events(mp))
1885 continue;
1886 break;
1887 }
1da177e4 1888
1fa38c58
LB		 1889 queue = fls(queue_mask) - 1;
1890 queue_mask = 1 << queue;
1891
1892 work_tbd = budget - work_done;
1893 if (work_tbd > 16)
1894 work_tbd = 16;
1895
1896 if (mp->work_tx_end & queue_mask) {
1897 txq_kick(mp->txq + queue);
1898 } else if (mp->work_tx & queue_mask) {
1899 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
1900 txq_maybe_wake(mp->txq + queue);
1901 } else if (mp->work_rx & queue_mask) {
1902 work_done += rxq_process(mp->rxq + queue, work_tbd);
1903 } else if (mp->work_rx_refill & queue_mask) {
1904 work_done += rxq_refill(mp->rxq + queue, work_tbd);
1905 } else {
1906 BUG();
1907 }
84dd619e 1908 }
fc32b0e2 1909
1fa38c58
LB		 1910 if (work_done < budget) {
1911 if (mp->work_rx_oom)
1912 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
1913 napi_complete(napi);
1914 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
226bb6b7 1915 }
3d6b35bc 1916
1fa38c58
LB		 1917 return work_done;
1918}
8fa89bf5 1919
1fa38c58
LB		 1920static inline void oom_timer_wrapper(unsigned long data)
1921{
1922 struct mv643xx_eth_private *mp = (void *)data;
1da177e4 1923
1fa38c58 1924 napi_schedule(&mp->napi);
1da177e4
LT		 1925}
1926
e5371493 1927static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 1928{
45c5d3bc
LB		 1929 int data;
1930
1931 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1932 if (data < 0)
1933 return;
1da177e4 1934
7f106c1d 1935 data |= BMCR_RESET;
45c5d3bc
LB		 1936 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data) < 0)
1937 return;
1da177e4 1938
c9df406f 1939 do {
45c5d3bc
LB		 1940 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1941 } while (data >= 0 && data & BMCR_RESET);
1da177e4
LT		 1942}
1943
fc32b0e2 1944static void port_start(struct mv643xx_eth_private *mp)
1da177e4 1945{
d0412d96 1946 u32 pscr;
8a578111 1947 int i;
1da177e4 1948
bedfe324
LB		 1949 /*
1950 * Perform PHY reset, if there is a PHY.
1951 */
1952 if (mp->phy_addr != -1) {
1953 struct ethtool_cmd cmd;
1954
1955 mv643xx_eth_get_settings(mp->dev, &cmd);
1956 phy_reset(mp);
1957 mv643xx_eth_set_settings(mp->dev, &cmd);
1958 }
1da177e4 1959
81600eea
LB		 1960 /*
1961 * Configure basic link parameters.
1962 */
1963 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1964
1965 pscr |= SERIAL_PORT_ENABLE;
1966 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1967
1968 pscr |= DO_NOT_FORCE_LINK_FAIL;
1969 if (mp->phy_addr == -1)
1970 pscr |= FORCE_LINK_PASS;
1971 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1972
1973 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1974
13d64285
LB		 1975 /*
1976 * Configure TX path and queues.
1977 */
89df5fdc 1978 tx_set_rate(mp, 1000000000, 16777216);
f7981c1c 1979 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc 1980 struct tx_queue *txq = mp->txq + i;
13d64285 1981
6b368f68 1982 txq_reset_hw_ptr(txq);
89df5fdc
LB		 1983 txq_set_rate(txq, 1000000000, 16777216);
1984 txq_set_fixed_prio_mode(txq);
13d64285
LB		 1985 }
1986
fc32b0e2
LB		 1987 /*
1988 * Add configured unicast address to address filter table.
1989 */
1990 uc_addr_set(mp, mp->dev->dev_addr);
1da177e4 1991
d9a073ea
LB		 1992 /*
1993 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
170e7108
LB		 1994 * frames to RX queue #0, and include the pseudo-header when
1995 * calculating receive checksums.
d9a073ea 1996 */
170e7108 1997 wrl(mp, PORT_CONFIG(mp->port_num), 0x02000000);
01999873 1998
376489a2
LB		 1999 /*
2000 * Treat BPDUs as normal multicasts, and disable partition mode.
2001 */
8a578111 2002 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
01999873 2003
8a578111 2004 /*
64da80a2 2005 * Enable the receive queues.
8a578111 2006 */
f7981c1c 2007 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 2008 struct rx_queue *rxq = mp->rxq + i;
2009 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
8a578111 2010 u32 addr;
1da177e4 2011
8a578111
LB		 2012 addr = (u32)rxq->rx_desc_dma;
2013 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2014 wrl(mp, off, addr);
1da177e4 2015
8a578111
LB		 2016 rxq_enable(rxq);
2017 }
1da177e4
LT		 2018}
2019
ffd86bbe 2020static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 2021{
c9df406f 2022 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
773fc3ee 2023 u32 val;
1da177e4 2024
773fc3ee
LB		 2025 val = rdl(mp, SDMA_CONFIG(mp->port_num));
2026 if (mp->shared->extended_rx_coal_limit) {
2027 if (coal > 0xffff)
2028 coal = 0xffff;
2029 val &= ~0x023fff80;
2030 val |= (coal & 0x8000) << 10;
2031 val |= (coal & 0x7fff) << 7;
2032 } else {
2033 if (coal > 0x3fff)
2034 coal = 0x3fff;
2035 val &= ~0x003fff00;
2036 val |= (coal & 0x3fff) << 8;
2037 }
2038 wrl(mp, SDMA_CONFIG(mp->port_num), val);
1da177e4
LT		 2039}
2040
ffd86bbe 2041static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 2042{
c9df406f 2043 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 2044
fc32b0e2
LB		 2045 if (coal > 0x3fff)
2046 coal = 0x3fff;
2047 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
16e03018
DF		 2048}
2049
c9df406f 2050static int mv643xx_eth_open(struct net_device *dev)
16e03018 2051{
e5371493 2052 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2053 int err;
64da80a2 2054 int i;
16e03018 2055
fc32b0e2
LB		 2056 wrl(mp, INT_CAUSE(mp->port_num), 0);
2057 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
2058 rdl(mp, INT_CAUSE_EXT(mp->port_num));
c9df406f 2059
fc32b0e2 2060 err = request_irq(dev->irq, mv643xx_eth_irq,
2a1867a7 2061 IRQF_SHARED, dev->name, dev);
c9df406f 2062 if (err) {
fc32b0e2 2063 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
c9df406f 2064 return -EAGAIN;
16e03018
DF		 2065 }
2066
fc32b0e2 2067 init_mac_tables(mp);
16e03018 2068
2257e05c
LB		 2069 napi_enable(&mp->napi);
2070
f7981c1c 2071 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 2072 err = rxq_init(mp, i);
2073 if (err) {
2074 while (--i >= 0)
f7981c1c 2075 rxq_deinit(mp->rxq + i);
64da80a2
LB		 2076 goto out;
2077 }
2078
1fa38c58 2079 rxq_refill(mp->rxq + i, INT_MAX);
2257e05c
LB		 2080 }
2081
1fa38c58 2082 if (mp->work_rx_oom) {
2257e05c
LB		 2083 mp->rx_oom.expires = jiffies + (HZ / 10);
2084 add_timer(&mp->rx_oom);
64da80a2 2085 }
8a578111 2086
f7981c1c 2087 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc
LB		 2088 err = txq_init(mp, i);
2089 if (err) {
2090 while (--i >= 0)
f7981c1c 2091 txq_deinit(mp->txq + i);
3d6b35bc
LB		 2092 goto out_free;
2093 }
2094 }
16e03018 2095
2f7eb47a 2096 netif_carrier_off(dev);
2f7eb47a 2097
fc32b0e2 2098 port_start(mp);
16e03018 2099
ffd86bbe
LB		 2100 set_rx_coal(mp, 0);
2101 set_tx_coal(mp, 0);
16e03018 2102
befefe21 2103 wrl(mp, INT_MASK_EXT(mp->port_num), INT_EXT_LINK_PHY | INT_EXT_TX);
226bb6b7 2104 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
16e03018 2105
c9df406f
LB		 2106 return 0;
2107
13d64285 2108
fc32b0e2 2109out_free:
f7981c1c
LB		 2110 for (i = 0; i < mp->rxq_count; i++)
2111 rxq_deinit(mp->rxq + i);
fc32b0e2 2112out:
c9df406f
LB		 2113 free_irq(dev->irq, dev);
2114
2115 return err;
16e03018
DF		 2116}
2117
e5371493 2118static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 2119{
fc32b0e2 2120 unsigned int data;
64da80a2 2121 int i;
1da177e4 2122
f7981c1c
LB		 2123 for (i = 0; i < mp->rxq_count; i++)
2124 rxq_disable(mp->rxq + i);
2125 for (i = 0; i < mp->txq_count; i++)
2126 txq_disable(mp->txq + i);
ae9ae064
LB		 2127
2128 while (1) {
2129 u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
2130
2131 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2132 break;
13d64285 2133 udelay(10);
ae9ae064 2134 }
1da177e4 2135
c9df406f 2136 /* Reset the Enable bit in the Configuration Register */
fc32b0e2
LB		 2137 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2138 data &= ~(SERIAL_PORT_ENABLE |
2139 DO_NOT_FORCE_LINK_FAIL |
2140 FORCE_LINK_PASS);
2141 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
1da177e4
LT		 2142}
2143
c9df406f 2144static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 2145{
e5371493 2146 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 2147 int i;
1da177e4 2148
fc32b0e2
LB		 2149 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2150 rdl(mp, INT_MASK(mp->port_num));
1da177e4 2151
c9df406f 2152 napi_disable(&mp->napi);
78fff83b 2153
2257e05c
LB		 2154 del_timer_sync(&mp->rx_oom);
2155
c9df406f 2156 netif_carrier_off(dev);
1da177e4 2157
fc32b0e2
LB		 2158 free_irq(dev->irq, dev);
2159
cc9754b3 2160 port_reset(mp);
8fd89211 2161 mv643xx_eth_get_stats(dev);
fc32b0e2 2162 mib_counters_update(mp);
1da177e4 2163
f7981c1c
LB		 2164 for (i = 0; i < mp->rxq_count; i++)
2165 rxq_deinit(mp->rxq + i);
2166 for (i = 0; i < mp->txq_count; i++)
2167 txq_deinit(mp->txq + i);
1da177e4 2168
c9df406f 2169 return 0;
1da177e4
LT		 2170}
2171
fc32b0e2 2172static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 2173{
e5371493 2174 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2175
bedfe324
LB		 2176 if (mp->phy_addr != -1)
2177 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2178
2179 return -EOPNOTSUPP;
1da177e4
LT		 2180}
2181
c9df406f 2182static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 2183{
89df5fdc
LB		 2184 struct mv643xx_eth_private *mp = netdev_priv(dev);
2185
fc32b0e2 2186 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 2187 return -EINVAL;
1da177e4 2188
c9df406f 2189 dev->mtu = new_mtu;
89df5fdc
LB		 2190 tx_set_rate(mp, 1000000000, 16777216);
2191
c9df406f
LB		 2192 if (!netif_running(dev))
2193 return 0;
1da177e4 2194
c9df406f
LB		 2195 /*
2196 * Stop and then re-open the interface. This will allocate RX
2197 * skbs of the new MTU.
2198 * There is a possible danger that the open will not succeed,
fc32b0e2 2199 * due to memory being full.
c9df406f
LB		 2200 */
2201 mv643xx_eth_stop(dev);
2202 if (mv643xx_eth_open(dev)) {
fc32b0e2
LB		 2203 dev_printk(KERN_ERR, &dev->dev,
2204 "fatal error on re-opening device after "
2205 "MTU change\n");
c9df406f
LB		 2206 }
2207
2208 return 0;
1da177e4
LT		 2209}
2210
fc32b0e2 2211static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2212{
fc32b0e2 2213 struct mv643xx_eth_private *mp;
1da177e4 2214
fc32b0e2
LB		 2215 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2216 if (netif_running(mp->dev)) {
e5ef1de1 2217 netif_tx_stop_all_queues(mp->dev);
fc32b0e2
LB		 2218 port_reset(mp);
2219 port_start(mp);
e5ef1de1 2220 netif_tx_wake_all_queues(mp->dev);
fc32b0e2 2221 }
c9df406f
LB		 2222}
2223
c9df406f 2224static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2225{
e5371493 2226 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2227
fc32b0e2 2228 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
d0412d96 2229
c9df406f 2230 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2231}
2232
c9df406f 2233#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2234static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2235{
fc32b0e2 2236 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2237
fc32b0e2
LB		 2238 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2239 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2240
fc32b0e2 2241 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2242
f2ca60f2 2243 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
9f8dd319 2244}
c9df406f 2245#endif
9f8dd319 2246
fc32b0e2 2247static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
9f8dd319 2248{
e5371493 2249 struct mv643xx_eth_private *mp = netdev_priv(dev);
45c5d3bc 2250 return smi_reg_read(mp, addr, reg);
9f8dd319
DF		 2251}
2252
fc32b0e2 2253static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
9f8dd319 2254{
e5371493 2255 struct mv643xx_eth_private *mp = netdev_priv(dev);
fc32b0e2 2256 smi_reg_write(mp, addr, reg, val);
c9df406f 2257}
9f8dd319 2258
9f8dd319 2259
c9df406f 2260/* platform glue ************************************************************/
e5371493
LB		 2261static void
2262mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2263 struct mbus_dram_target_info *dram)
c9df406f 2264{
cc9754b3 2265 void __iomem *base = msp->base;
c9df406f
LB		 2266 u32 win_enable;
2267 u32 win_protect;
2268 int i;
9f8dd319 2269
c9df406f
LB		 2270 for (i = 0; i < 6; i++) {
2271 writel(0, base + WINDOW_BASE(i));
2272 writel(0, base + WINDOW_SIZE(i));
2273 if (i < 4)
2274 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2275 }
2276
c9df406f
LB		 2277 win_enable = 0x3f;
2278 win_protect = 0;
2279
2280 for (i = 0; i < dram->num_cs; i++) {
2281 struct mbus_dram_window *cs = dram->cs + i;
2282
2283 writel((cs->base & 0xffff0000) |
2284 (cs->mbus_attr << 8) |
2285 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2286 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2287
2288 win_enable &= ~(1 << i);
2289 win_protect |= 3 << (2 * i);
2290 }
2291
2292 writel(win_enable, base + WINDOW_BAR_ENABLE);
2293 msp->win_protect = win_protect;
9f8dd319
DF		 2294}
2295
773fc3ee
LB		 2296static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2297{
2298 /*
2299 * Check whether we have a 14-bit coal limit field in bits
2300 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2301 * SDMA config register.
2302 */
2303 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2304 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2305 msp->extended_rx_coal_limit = 1;
2306 else
2307 msp->extended_rx_coal_limit = 0;
1e881592
LB		 2308
2309 /*
457b1d5a
LB		 2310 * Check whether the MAC supports TX rate control, and if
2311 * yes, whether its associated registers are in the old or
2312 * the new place.
1e881592
LB		 2313 */
2314 writel(1, msp->base + TX_BW_MTU_MOVED(0));
457b1d5a
LB		 2315 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1) {
2316 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2317 } else {
2318 writel(7, msp->base + TX_BW_RATE(0));
2319 if (readl(msp->base + TX_BW_RATE(0)) & 7)
2320 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2321 else
2322 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2323 }
773fc3ee
LB		 2324}
2325
c9df406f 2326static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2327{
e5371493 2328 static int mv643xx_eth_version_printed = 0;
c9df406f 2329 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2330 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 2331 struct resource *res;
2332 int ret;
9f8dd319 2333
e5371493 2334 if (!mv643xx_eth_version_printed++)
7dde154d
LB		 2335 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2336 "driver version %s\n", mv643xx_eth_driver_version);
9f8dd319 2337
c9df406f
LB		 2338 ret = -EINVAL;
2339 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2340 if (res == NULL)
2341 goto out;
9f8dd319 2342
c9df406f
LB		 2343 ret = -ENOMEM;
2344 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2345 if (msp == NULL)
2346 goto out;
2347 memset(msp, 0, sizeof(*msp));
2348
cc9754b3
LB		 2349 msp->base = ioremap(res->start, res->end - res->start + 1);
2350 if (msp->base == NULL)
c9df406f
LB		 2351 goto out_free;
2352
fc0eb9f2
LB		 2353 msp->smi = msp;
2354 if (pd != NULL && pd->shared_smi != NULL)
2355 msp->smi = platform_get_drvdata(pd->shared_smi);
2356
2b3ba0e3 2357 mutex_init(&msp->phy_lock);
c9df406f 2358
45c5d3bc
LB		 2359 msp->err_interrupt = NO_IRQ;
2360 init_waitqueue_head(&msp->smi_busy_wait);
2361
2362 /*
2363 * Check whether the error interrupt is hooked up.
2364 */
2365 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2366 if (res != NULL) {
2367 int err;
2368
2369 err = request_irq(res->start, mv643xx_eth_err_irq,
2370 IRQF_SHARED, "mv643xx_eth", msp);
2371 if (!err) {
2372 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2373 msp->err_interrupt = res->start;
2374 }
2375 }
2376
c9df406f
LB		 2377 /*
2378 * (Re-)program MBUS remapping windows if we are asked to.
2379 */
2380 if (pd != NULL && pd->dram != NULL)
2381 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2382
fc32b0e2
LB		 2383 /*
2384 * Detect hardware parameters.
2385 */
2386 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
773fc3ee 2387 infer_hw_params(msp);
fc32b0e2
LB		 2388
2389 platform_set_drvdata(pdev, msp);
2390
c9df406f
LB		 2391 return 0;
2392
2393out_free:
2394 kfree(msp);
2395out:
2396 return ret;
2397}
2398
2399static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2400{
e5371493 2401 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
c9df406f 2402
45c5d3bc
LB		 2403 if (msp->err_interrupt != NO_IRQ)
2404 free_irq(msp->err_interrupt, msp);
cc9754b3 2405 iounmap(msp->base);
c9df406f
LB		 2406 kfree(msp);
2407
2408 return 0;
9f8dd319
DF		 2409}
2410
c9df406f 2411static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2412 .probe = mv643xx_eth_shared_probe,
2413 .remove = mv643xx_eth_shared_remove,
c9df406f 2414 .driver = {
fc32b0e2 2415 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2416 .owner = THIS_MODULE,
2417 },
2418};
2419
e5371493 2420static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2421{
c9df406f 2422 int addr_shift = 5 * mp->port_num;
fc32b0e2 2423 u32 data;
1da177e4 2424
fc32b0e2
LB		 2425 data = rdl(mp, PHY_ADDR);
2426 data &= ~(0x1f << addr_shift);
2427 data |= (phy_addr & 0x1f) << addr_shift;
2428 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2429}
2430
e5371493 2431static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2432{
fc32b0e2
LB		 2433 unsigned int data;
2434
2435 data = rdl(mp, PHY_ADDR);
2436
2437 return (data >> (5 * mp->port_num)) & 0x1f;
2438}
2439
2440static void set_params(struct mv643xx_eth_private *mp,
2441 struct mv643xx_eth_platform_data *pd)
2442{
2443 struct net_device *dev = mp->dev;
2444
2445 if (is_valid_ether_addr(pd->mac_addr))
2446 memcpy(dev->dev_addr, pd->mac_addr, 6);
2447 else
2448 uc_addr_get(mp, dev->dev_addr);
2449
ac840605 2450 if (pd->phy_addr == MV643XX_ETH_PHY_NONE) {
fc32b0e2
LB		 2451 mp->phy_addr = -1;
2452 } else {
ac840605 2453 if (pd->phy_addr != MV643XX_ETH_PHY_ADDR_DEFAULT) {
fc32b0e2
LB		 2454 mp->phy_addr = pd->phy_addr & 0x3f;
2455 phy_addr_set(mp, mp->phy_addr);
2456 } else {
2457 mp->phy_addr = phy_addr_get(mp);
2458 }
2459 }
1da177e4 2460
fc32b0e2
LB		 2461 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2462 if (pd->rx_queue_size)
2463 mp->default_rx_ring_size = pd->rx_queue_size;
2464 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2465 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2466
f7981c1c 2467 mp->rxq_count = pd->rx_queue_count ? : 1;
64da80a2 2468
fc32b0e2
LB		 2469 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2470 if (pd->tx_queue_size)
2471 mp->default_tx_ring_size = pd->tx_queue_size;
2472 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2473 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc 2474
f7981c1c 2475 mp->txq_count = pd->tx_queue_count ? : 1;
1da177e4
LT		 2476}
2477
e5371493 2478static int phy_detect(struct mv643xx_eth_private *mp)
1da177e4 2479{
45c5d3bc
LB		 2480 int data;
2481 int data2;
2482
2483 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2484 if (data < 0)
2485 return -ENODEV;
2486
2487 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data ^ BMCR_ANENABLE) < 0)
2488 return -ENODEV;
fc32b0e2 2489
45c5d3bc
LB		 2490 data2 = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2491 if (data2 < 0)
2492 return -ENODEV;
1da177e4 2493
7f106c1d 2494 if (((data ^ data2) & BMCR_ANENABLE) == 0)
fc32b0e2 2495 return -ENODEV;
1da177e4 2496
7f106c1d 2497 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
1da177e4 2498
c9df406f 2499 return 0;
1da177e4
LT		 2500}
2501
fc32b0e2
LB		 2502static int phy_init(struct mv643xx_eth_private *mp,
2503 struct mv643xx_eth_platform_data *pd)
c28a4f89 2504{
fc32b0e2
LB		 2505 struct ethtool_cmd cmd;
2506 int err;
c28a4f89 2507
fc32b0e2
LB		 2508 err = phy_detect(mp);
2509 if (err) {
2510 dev_printk(KERN_INFO, &mp->dev->dev,
2511 "no PHY detected at addr %d\n", mp->phy_addr);
2512 return err;
2513 }
2514 phy_reset(mp);
2515
2516 mp->mii.phy_id = mp->phy_addr;
2517 mp->mii.phy_id_mask = 0x3f;
2518 mp->mii.reg_num_mask = 0x1f;
2519 mp->mii.dev = mp->dev;
2520 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2521 mp->mii.mdio_write = mv643xx_eth_mdio_write;
c28a4f89 2522
fc32b0e2 2523 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
c9df406f 2524
fc32b0e2
LB		 2525 memset(&cmd, 0, sizeof(cmd));
2526
2527 cmd.port = PORT_MII;
2528 cmd.transceiver = XCVR_INTERNAL;
2529 cmd.phy_address = mp->phy_addr;
2530 if (pd->speed == 0) {
2531 cmd.autoneg = AUTONEG_ENABLE;
2532 cmd.speed = SPEED_100;
2533 cmd.advertising = ADVERTISED_10baseT_Half |
2534 ADVERTISED_10baseT_Full |
2535 ADVERTISED_100baseT_Half |
2536 ADVERTISED_100baseT_Full;
c9df406f 2537 if (mp->mii.supports_gmii)
fc32b0e2 2538 cmd.advertising |= ADVERTISED_1000baseT_Full;
c9df406f 2539 } else {
fc32b0e2
LB		 2540 cmd.autoneg = AUTONEG_DISABLE;
2541 cmd.speed = pd->speed;
2542 cmd.duplex = pd->duplex;
c9df406f 2543 }
fc32b0e2 2544
fc32b0e2
LB		 2545 mv643xx_eth_set_settings(mp->dev, &cmd);
2546
2547 return 0;
c28a4f89
JC		 2548}
2549
81600eea
LB		 2550static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2551{
2552 u32 pscr;
2553
2554 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2555 if (pscr & SERIAL_PORT_ENABLE) {
2556 pscr &= ~SERIAL_PORT_ENABLE;
2557 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2558 }
2559
2560 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2561 if (mp->phy_addr == -1) {
2562 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2563 if (speed == SPEED_1000)
2564 pscr |= SET_GMII_SPEED_TO_1000;
2565 else if (speed == SPEED_100)
2566 pscr |= SET_MII_SPEED_TO_100;
2567
2568 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2569
2570 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2571 if (duplex == DUPLEX_FULL)
2572 pscr |= SET_FULL_DUPLEX_MODE;
2573 }
2574
2575 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2576}
2577
c9df406f 2578static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2579{
c9df406f 2580 struct mv643xx_eth_platform_data *pd;
e5371493 2581 struct mv643xx_eth_private *mp;
c9df406f 2582 struct net_device *dev;
c9df406f 2583 struct resource *res;
c9df406f 2584 DECLARE_MAC_BUF(mac);
fc32b0e2 2585 int err;
1da177e4 2586
c9df406f
LB		 2587 pd = pdev->dev.platform_data;
2588 if (pd == NULL) {
fc32b0e2
LB		 2589 dev_printk(KERN_ERR, &pdev->dev,
2590 "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2591 return -ENODEV;
2592 }
1da177e4 2593
c9df406f 2594 if (pd->shared == NULL) {
fc32b0e2
LB		 2595 dev_printk(KERN_ERR, &pdev->dev,
2596 "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2597 return -ENODEV;
2598 }
8f518703 2599
e5ef1de1 2600 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
c9df406f
LB		 2601 if (!dev)
2602 return -ENOMEM;
1da177e4 2603
c9df406f 2604 mp = netdev_priv(dev);
fc32b0e2
LB		 2605 platform_set_drvdata(pdev, mp);
2606
2607 mp->shared = platform_get_drvdata(pd->shared);
2608 mp->port_num = pd->port_number;
2609
c9df406f 2610 mp->dev = dev;
78fff83b 2611
fc32b0e2 2612 set_params(mp, pd);
e5ef1de1 2613 dev->real_num_tx_queues = mp->txq_count;
fc32b0e2 2614
fc32b0e2
LB		 2615 mib_counters_clear(mp);
2616 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2617
bedfe324
LB		 2618 if (mp->phy_addr != -1) {
2619 err = phy_init(mp, pd);
2620 if (err)
2621 goto out;
2622
2623 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2624 } else {
2625 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2626 }
81600eea 2627 init_pscr(mp, pd->speed, pd->duplex);
fc32b0e2 2628
2257e05c
LB		 2629 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2630
2631 init_timer(&mp->rx_oom);
2632 mp->rx_oom.data = (unsigned long)mp;
2633 mp->rx_oom.function = oom_timer_wrapper;
2634
fc32b0e2 2635
c9df406f
LB		 2636 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2637 BUG_ON(!res);
2638 dev->irq = res->start;
1da177e4 2639
8fd89211 2640 dev->get_stats = mv643xx_eth_get_stats;
fc32b0e2 2641 dev->hard_start_xmit = mv643xx_eth_xmit;
c9df406f
LB		 2642 dev->open = mv643xx_eth_open;
2643 dev->stop = mv643xx_eth_stop;
c9df406f 2644 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
fc32b0e2
LB		 2645 dev->set_mac_address = mv643xx_eth_set_mac_address;
2646 dev->do_ioctl = mv643xx_eth_ioctl;
2647 dev->change_mtu = mv643xx_eth_change_mtu;
c9df406f 2648 dev->tx_timeout = mv643xx_eth_tx_timeout;
c9df406f 2649#ifdef CONFIG_NET_POLL_CONTROLLER
e5371493 2650 dev->poll_controller = mv643xx_eth_netpoll;
c9df406f 2651#endif
c9df406f
LB		 2652 dev->watchdog_timeo = 2 * HZ;
2653 dev->base_addr = 0;
1da177e4 2654
c9df406f 2655 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
e32b6617 2656 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4 2657
fc32b0e2 2658 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2659
c9df406f 2660 if (mp->shared->win_protect)
fc32b0e2 2661 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2662
c9df406f
LB		 2663 err = register_netdev(dev);
2664 if (err)
2665 goto out;
1da177e4 2666
fc32b0e2
LB		 2667 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2668 mp->port_num, print_mac(mac, dev->dev_addr));
1da177e4 2669
13d64285 2670 if (mp->tx_desc_sram_size > 0)
fc32b0e2 2671 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
1da177e4 2672
c9df406f 2673 return 0;
1da177e4 2674
c9df406f
LB		 2675out:
2676 free_netdev(dev);
1da177e4 2677
c9df406f 2678 return err;
1da177e4
LT		 2679}
2680
c9df406f 2681static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2682{
fc32b0e2 2683 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2684
fc32b0e2 2685 unregister_netdev(mp->dev);
c9df406f 2686 flush_scheduled_work();
fc32b0e2 2687 free_netdev(mp->dev);
c9df406f 2688
c9df406f 2689 platform_set_drvdata(pdev, NULL);
fc32b0e2 2690
c9df406f 2691 return 0;
1da177e4
LT		 2692}
2693
c9df406f 2694static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2695{
fc32b0e2 2696 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 2697
c9df406f 2698 /* Mask all interrupts on ethernet port */
fc32b0e2
LB		 2699 wrl(mp, INT_MASK(mp->port_num), 0);
2700 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2701
fc32b0e2
LB		 2702 if (netif_running(mp->dev))
2703 port_reset(mp);
d0412d96
JC		 2704}
2705
c9df406f 2706static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 2707 .probe = mv643xx_eth_probe,
2708 .remove = mv643xx_eth_remove,
2709 .shutdown = mv643xx_eth_shutdown,
c9df406f 2710 .driver = {
fc32b0e2 2711 .name = MV643XX_ETH_NAME,
c9df406f
LB		 2712 .owner = THIS_MODULE,
2713 },
2714};
2715
e5371493 2716static int __init mv643xx_eth_init_module(void)
d0412d96 2717{
c9df406f 2718 int rc;
d0412d96 2719
c9df406f
LB		 2720 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2721 if (!rc) {
2722 rc = platform_driver_register(&mv643xx_eth_driver);
2723 if (rc)
2724 platform_driver_unregister(&mv643xx_eth_shared_driver);
2725 }
fc32b0e2 2726
c9df406f 2727 return rc;
d0412d96 2728}
fc32b0e2 2729module_init(mv643xx_eth_init_module);
d0412d96 2730
e5371493 2731static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 2732{
c9df406f
LB		 2733 platform_driver_unregister(&mv643xx_eth_driver);
2734 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 2735}
e5371493 2736module_exit(mv643xx_eth_cleanup_module);
1da177e4 2737
45675bc6
LB		 2738MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2739 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
c9df406f 2740MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 2741MODULE_LICENSE("GPL");
c9df406f 2742MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 2743MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux kernel - Deliverables
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