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mv643xx_eth: print message on link status change
[deliverable/linux.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
1da177e4
LT		 41#include <linux/tcp.h>
42#include <linux/udp.h>
43#include <linux/etherdevice.h>
1da177e4
LT		 44#include <linux/delay.h>
45#include <linux/ethtool.h>
d052d1be 46#include <linux/platform_device.h>
fbd6a754
LB		 47#include <linux/module.h>
48#include <linux/kernel.h>
49#include <linux/spinlock.h>
50#include <linux/workqueue.h>
51#include <linux/mii.h>
fbd6a754 52#include <linux/mv643xx_eth.h>
1da177e4
LT		 53#include <asm/io.h>
54#include <asm/types.h>
1da177e4 55#include <asm/system.h>
fbd6a754 56
e5371493 57static char mv643xx_eth_driver_name[] = "mv643xx_eth";
45675bc6 58static char mv643xx_eth_driver_version[] = "1.1";
c9df406f 59
e5371493
LB		 60#define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61#define MV643XX_ETH_NAPI
62#define MV643XX_ETH_TX_FAST_REFILL
fbd6a754 63
e5371493 64#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
fbd6a754
LB		 65#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
66#else
67#define MAX_DESCS_PER_SKB 1
68#endif
69
fbd6a754
LB		 70/*
71 * Registers shared between all ports.
72 */
3cb4667c
LB		 73#define PHY_ADDR 0x0000
74#define SMI_REG 0x0004
75#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78#define WINDOW_BAR_ENABLE 0x0290
79#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 80
81/*
82 * Per-port registers.
83 */
3cb4667c 84#define PORT_CONFIG(p) (0x0400 + ((p) << 10))
d9a073ea 85#define UNICAST_PROMISCUOUS_MODE 0x00000001
3cb4667c
LB		 86#define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
87#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
88#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
89#define SDMA_CONFIG(p) (0x041c + ((p) << 10))
90#define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
91#define PORT_STATUS(p) (0x0444 + ((p) << 10))
a2a41689 92#define TX_FIFO_EMPTY 0x00000400
ae9ae064 93#define TX_IN_PROGRESS 0x00000080
2f7eb47a
LB		 94#define PORT_SPEED_MASK 0x00000030
95#define PORT_SPEED_1000 0x00000010
96#define PORT_SPEED_100 0x00000020
97#define PORT_SPEED_10 0x00000000
98#define FLOW_CONTROL_ENABLED 0x00000008
99#define FULL_DUPLEX 0x00000004
81600eea 100#define LINK_UP 0x00000002
3cb4667c 101#define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
89df5fdc
LB		 102#define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
103#define TX_BW_RATE(p) (0x0450 + ((p) << 10))
3cb4667c 104#define TX_BW_MTU(p) (0x0458 + ((p) << 10))
89df5fdc 105#define TX_BW_BURST(p) (0x045c + ((p) << 10))
3cb4667c 106#define INT_CAUSE(p) (0x0460 + ((p) << 10))
8fa89bf5 107#define INT_TX_END_0 0x00080000
226bb6b7 108#define INT_TX_END 0x07f80000
64da80a2 109#define INT_RX 0x0007fbfc
073a345c 110#define INT_EXT 0x00000002
3cb4667c 111#define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
073a345c
LB		 112#define INT_EXT_LINK 0x00100000
113#define INT_EXT_PHY 0x00010000
114#define INT_EXT_TX_ERROR_0 0x00000100
115#define INT_EXT_TX_0 0x00000001
3d6b35bc 116#define INT_EXT_TX 0x0000ffff
3cb4667c
LB		 117#define INT_MASK(p) (0x0468 + ((p) << 10))
118#define INT_MASK_EXT(p) (0x046c + ((p) << 10))
119#define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
1e881592
LB		 120#define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
121#define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
122#define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
123#define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
64da80a2 124#define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
3cb4667c 125#define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
3d6b35bc
LB		 126#define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
127#define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
128#define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
129#define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
3cb4667c
LB		 130#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
131#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
132#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
133#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 134
2679a550
LB		 135
136/*
137 * SDMA configuration register.
138 */
cd4ccf76 139#define RX_BURST_SIZE_16_64BIT (4 << 1)
fbd6a754 140#define BLM_RX_NO_SWAP (1 << 4)
fbd6a754 141#define BLM_TX_NO_SWAP (1 << 5)
cd4ccf76 142#define TX_BURST_SIZE_16_64BIT (4 << 22)
fbd6a754
LB		 143
144#if defined(__BIG_ENDIAN)
145#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
cd4ccf76
LB		 146 RX_BURST_SIZE_16_64BIT | \
147 TX_BURST_SIZE_16_64BIT
fbd6a754
LB		 148#elif defined(__LITTLE_ENDIAN)
149#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
cd4ccf76 150 RX_BURST_SIZE_16_64BIT | \
fbd6a754
LB		 151 BLM_RX_NO_SWAP | \
152 BLM_TX_NO_SWAP | \
cd4ccf76 153 TX_BURST_SIZE_16_64BIT
fbd6a754
LB		 154#else
155#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
156#endif
157
2beff77b
LB		 158
159/*
160 * Port serial control register.
161 */
162#define SET_MII_SPEED_TO_100 (1 << 24)
163#define SET_GMII_SPEED_TO_1000 (1 << 23)
164#define SET_FULL_DUPLEX_MODE (1 << 21)
fbd6a754 165#define MAX_RX_PACKET_9700BYTE (5 << 17)
2beff77b
LB		 166#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
167#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
168#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
169#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
170#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
171#define FORCE_LINK_PASS (1 << 1)
172#define SERIAL_PORT_ENABLE (1 << 0)
fbd6a754 173
cc9754b3
LB		 174#define DEFAULT_RX_QUEUE_SIZE 400
175#define DEFAULT_TX_QUEUE_SIZE 800
fbd6a754 176
fbd6a754 177
7ca72a3b
LB		 178/*
179 * RX/TX descriptors.
fbd6a754
LB		 180 */
181#if defined(__BIG_ENDIAN)
cc9754b3 182struct rx_desc {
fbd6a754
LB		 183 u16 byte_cnt; /* Descriptor buffer byte count */
184 u16 buf_size; /* Buffer size */
185 u32 cmd_sts; /* Descriptor command status */
186 u32 next_desc_ptr; /* Next descriptor pointer */
187 u32 buf_ptr; /* Descriptor buffer pointer */
188};
189
cc9754b3 190struct tx_desc {
fbd6a754
LB		 191 u16 byte_cnt; /* buffer byte count */
192 u16 l4i_chk; /* CPU provided TCP checksum */
193 u32 cmd_sts; /* Command/status field */
194 u32 next_desc_ptr; /* Pointer to next descriptor */
195 u32 buf_ptr; /* pointer to buffer for this descriptor*/
196};
197#elif defined(__LITTLE_ENDIAN)
cc9754b3 198struct rx_desc {
fbd6a754
LB		 199 u32 cmd_sts; /* Descriptor command status */
200 u16 buf_size; /* Buffer size */
201 u16 byte_cnt; /* Descriptor buffer byte count */
202 u32 buf_ptr; /* Descriptor buffer pointer */
203 u32 next_desc_ptr; /* Next descriptor pointer */
204};
205
cc9754b3 206struct tx_desc {
fbd6a754
LB		 207 u32 cmd_sts; /* Command/status field */
208 u16 l4i_chk; /* CPU provided TCP checksum */
209 u16 byte_cnt; /* buffer byte count */
210 u32 buf_ptr; /* pointer to buffer for this descriptor*/
211 u32 next_desc_ptr; /* Pointer to next descriptor */
212};
213#else
214#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
215#endif
216
7ca72a3b 217/* RX & TX descriptor command */
cc9754b3 218#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 219
220/* RX & TX descriptor status */
cc9754b3 221#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 222
223/* RX descriptor status */
cc9754b3
LB		 224#define LAYER_4_CHECKSUM_OK 0x40000000
225#define RX_ENABLE_INTERRUPT 0x20000000
226#define RX_FIRST_DESC 0x08000000
227#define RX_LAST_DESC 0x04000000
7ca72a3b
LB		 228
229/* TX descriptor command */
cc9754b3
LB		 230#define TX_ENABLE_INTERRUPT 0x00800000
231#define GEN_CRC 0x00400000
232#define TX_FIRST_DESC 0x00200000
233#define TX_LAST_DESC 0x00100000
234#define ZERO_PADDING 0x00080000
235#define GEN_IP_V4_CHECKSUM 0x00040000
236#define GEN_TCP_UDP_CHECKSUM 0x00020000
237#define UDP_FRAME 0x00010000
7ca72a3b 238
cc9754b3 239#define TX_IHL_SHIFT 11
7ca72a3b
LB		 240
241
c9df406f 242/* global *******************************************************************/
e5371493 243struct mv643xx_eth_shared_private {
fc32b0e2
LB		 244 /*
245 * Ethernet controller base address.
246 */
cc9754b3 247 void __iomem *base;
c9df406f 248
fc32b0e2
LB		 249 /*
250 * Protects access to SMI_REG, which is shared between ports.
251 */
c9df406f
LB		 252 spinlock_t phy_lock;
253
fc32b0e2
LB		 254 /*
255 * Per-port MBUS window access register value.
256 */
c9df406f
LB		 257 u32 win_protect;
258
fc32b0e2
LB		 259 /*
260 * Hardware-specific parameters.
261 */
c9df406f 262 unsigned int t_clk;
773fc3ee 263 int extended_rx_coal_limit;
1e881592 264 int tx_bw_control_moved;
c9df406f
LB		 265};
266
267
268/* per-port *****************************************************************/
e5371493 269struct mib_counters {
fbd6a754
LB		 270 u64 good_octets_received;
271 u32 bad_octets_received;
272 u32 internal_mac_transmit_err;
273 u32 good_frames_received;
274 u32 bad_frames_received;
275 u32 broadcast_frames_received;
276 u32 multicast_frames_received;
277 u32 frames_64_octets;
278 u32 frames_65_to_127_octets;
279 u32 frames_128_to_255_octets;
280 u32 frames_256_to_511_octets;
281 u32 frames_512_to_1023_octets;
282 u32 frames_1024_to_max_octets;
283 u64 good_octets_sent;
284 u32 good_frames_sent;
285 u32 excessive_collision;
286 u32 multicast_frames_sent;
287 u32 broadcast_frames_sent;
288 u32 unrec_mac_control_received;
289 u32 fc_sent;
290 u32 good_fc_received;
291 u32 bad_fc_received;
292 u32 undersize_received;
293 u32 fragments_received;
294 u32 oversize_received;
295 u32 jabber_received;
296 u32 mac_receive_error;
297 u32 bad_crc_event;
298 u32 collision;
299 u32 late_collision;
300};
301
8a578111 302struct rx_queue {
64da80a2
LB		 303 int index;
304
8a578111
LB		 305 int rx_ring_size;
306
307 int rx_desc_count;
308 int rx_curr_desc;
309 int rx_used_desc;
310
311 struct rx_desc *rx_desc_area;
312 dma_addr_t rx_desc_dma;
313 int rx_desc_area_size;
314 struct sk_buff **rx_skb;
315
316 struct timer_list rx_oom;
317};
318
13d64285 319struct tx_queue {
3d6b35bc
LB		 320 int index;
321
13d64285 322 int tx_ring_size;
fbd6a754 323
13d64285
LB		 324 int tx_desc_count;
325 int tx_curr_desc;
326 int tx_used_desc;
fbd6a754 327
5daffe94 328 struct tx_desc *tx_desc_area;
fbd6a754
LB		 329 dma_addr_t tx_desc_dma;
330 int tx_desc_area_size;
331 struct sk_buff **tx_skb;
13d64285
LB		 332};
333
334struct mv643xx_eth_private {
335 struct mv643xx_eth_shared_private *shared;
fc32b0e2 336 int port_num;
13d64285 337
fc32b0e2 338 struct net_device *dev;
fbd6a754 339
fc32b0e2
LB		 340 struct mv643xx_eth_shared_private *shared_smi;
341 int phy_addr;
fbd6a754 342
fbd6a754 343 spinlock_t lock;
fbd6a754 344
fc32b0e2
LB		 345 struct mib_counters mib_counters;
346 struct work_struct tx_timeout_task;
fbd6a754 347 struct mii_if_info mii;
8a578111
LB		 348
349 /*
350 * RX state.
351 */
352 int default_rx_ring_size;
353 unsigned long rx_desc_sram_addr;
354 int rx_desc_sram_size;
64da80a2
LB		 355 u8 rxq_mask;
356 int rxq_primary;
8a578111 357 struct napi_struct napi;
64da80a2 358 struct rx_queue rxq[8];
13d64285
LB		 359
360 /*
361 * TX state.
362 */
363 int default_tx_ring_size;
364 unsigned long tx_desc_sram_addr;
365 int tx_desc_sram_size;
3d6b35bc
LB		 366 u8 txq_mask;
367 int txq_primary;
368 struct tx_queue txq[8];
13d64285
LB		 369#ifdef MV643XX_ETH_TX_FAST_REFILL
370 int tx_clean_threshold;
371#endif
fbd6a754 372};
1da177e4 373
fbd6a754 374
c9df406f 375/* port register accessors **************************************************/
e5371493 376static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 377{
cc9754b3 378 return readl(mp->shared->base + offset);
c9df406f 379}
fbd6a754 380
e5371493 381static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 382{
cc9754b3 383 writel(data, mp->shared->base + offset);
c9df406f 384}
fbd6a754 385
fbd6a754 386
c9df406f 387/* rxq/txq helper functions *************************************************/
8a578111 388static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 389{
64da80a2 390 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 391}
fbd6a754 392
13d64285
LB		 393static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
394{
3d6b35bc 395 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 396}
397
8a578111 398static void rxq_enable(struct rx_queue *rxq)
c9df406f 399{
8a578111 400 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 401 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
8a578111 402}
1da177e4 403
8a578111
LB		 404static void rxq_disable(struct rx_queue *rxq)
405{
406 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 407 u8 mask = 1 << rxq->index;
1da177e4 408
8a578111
LB		 409 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
410 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
411 udelay(10);
c9df406f
LB		 412}
413
6b368f68
LB		 414static void txq_reset_hw_ptr(struct tx_queue *txq)
415{
416 struct mv643xx_eth_private *mp = txq_to_mp(txq);
417 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
418 u32 addr;
419
420 addr = (u32)txq->tx_desc_dma;
421 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
422 wrl(mp, off, addr);
423}
424
13d64285 425static void txq_enable(struct tx_queue *txq)
1da177e4 426{
13d64285 427 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 428 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
1da177e4
LT		 429}
430
13d64285 431static void txq_disable(struct tx_queue *txq)
1da177e4 432{
13d64285 433 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 434 u8 mask = 1 << txq->index;
c9df406f 435
13d64285
LB		 436 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
437 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
438 udelay(10);
439}
440
441static void __txq_maybe_wake(struct tx_queue *txq)
442{
443 struct mv643xx_eth_private *mp = txq_to_mp(txq);
444
3d6b35bc
LB		 445 /*
446 * netif_{stop,wake}_queue() flow control only applies to
447 * the primary queue.
448 */
449 BUG_ON(txq->index != mp->txq_primary);
450
13d64285
LB		 451 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB)
452 netif_wake_queue(mp->dev);
1da177e4
LT		 453}
454
c9df406f
LB		 455
456/* rx ***********************************************************************/
13d64285 457static void txq_reclaim(struct tx_queue *txq, int force);
c9df406f 458
8a578111 459static void rxq_refill(struct rx_queue *rxq)
1da177e4 460{
8a578111 461 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
c9df406f 462 unsigned long flags;
1da177e4 463
c9df406f 464 spin_lock_irqsave(&mp->lock, flags);
c0d0f2ca 465
8a578111
LB		 466 while (rxq->rx_desc_count < rxq->rx_ring_size) {
467 int skb_size;
de34f225
LB		 468 struct sk_buff *skb;
469 int unaligned;
470 int rx;
471
8a578111
LB		 472 /*
473 * Reserve 2+14 bytes for an ethernet header (the
474 * hardware automatically prepends 2 bytes of dummy
475 * data to each received packet), 4 bytes for a VLAN
476 * header, and 4 bytes for the trailing FCS -- 24
477 * bytes total.
478 */
479 skb_size = mp->dev->mtu + 24;
480
481 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
de34f225 482 if (skb == NULL)
1da177e4 483 break;
de34f225 484
908b637f 485 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
b44cd572 486 if (unaligned)
908b637f 487 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
de34f225 488
8a578111
LB		 489 rxq->rx_desc_count++;
490 rx = rxq->rx_used_desc;
491 rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size;
de34f225 492
8a578111
LB		 493 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
494 skb_size, DMA_FROM_DEVICE);
495 rxq->rx_desc_area[rx].buf_size = skb_size;
496 rxq->rx_skb[rx] = skb;
de34f225 497 wmb();
8a578111 498 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
de34f225
LB		 499 RX_ENABLE_INTERRUPT;
500 wmb();
501
fc32b0e2
LB		 502 /*
503 * The hardware automatically prepends 2 bytes of
504 * dummy data to each received packet, so that the
505 * IP header ends up 16-byte aligned.
506 */
507 skb_reserve(skb, 2);
1da177e4 508 }
de34f225 509
12e4ab79 510 if (rxq->rx_desc_count != rxq->rx_ring_size) {
8a578111
LB		 511 rxq->rx_oom.expires = jiffies + (HZ / 10);
512 add_timer(&rxq->rx_oom);
1da177e4 513 }
de34f225
LB		 514
515 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4
LT		 516}
517
8a578111 518static inline void rxq_refill_timer_wrapper(unsigned long data)
1da177e4 519{
8a578111 520 rxq_refill((struct rx_queue *)data);
1da177e4
LT		 521}
522
8a578111 523static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 524{
8a578111
LB		 525 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
526 struct net_device_stats *stats = &mp->dev->stats;
527 int rx;
1da177e4 528
8a578111
LB		 529 rx = 0;
530 while (rx < budget) {
fc32b0e2 531 struct rx_desc *rx_desc;
96587661 532 unsigned int cmd_sts;
fc32b0e2 533 struct sk_buff *skb;
96587661 534 unsigned long flags;
d344bff9 535
96587661 536 spin_lock_irqsave(&mp->lock, flags);
ff561eef 537
8a578111 538 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 539
96587661
LB		 540 cmd_sts = rx_desc->cmd_sts;
541 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
542 spin_unlock_irqrestore(&mp->lock, flags);
543 break;
544 }
545 rmb();
1da177e4 546
8a578111
LB		 547 skb = rxq->rx_skb[rxq->rx_curr_desc];
548 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 549
8a578111 550 rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size;
ff561eef 551
96587661 552 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 553
fc32b0e2
LB		 554 dma_unmap_single(NULL, rx_desc->buf_ptr + 2,
555 mp->dev->mtu + 24, DMA_FROM_DEVICE);
8a578111
LB		 556 rxq->rx_desc_count--;
557 rx++;
b1dd9ca1 558
468d09f8
DF		 559 /*
560 * Update statistics.
fc32b0e2
LB		 561 *
562 * Note that the descriptor byte count includes 2 dummy
563 * bytes automatically inserted by the hardware at the
564 * start of the packet (which we don't count), and a 4
565 * byte CRC at the end of the packet (which we do count).
468d09f8 566 */
1da177e4 567 stats->rx_packets++;
fc32b0e2 568 stats->rx_bytes += rx_desc->byte_cnt - 2;
96587661 569
1da177e4 570 /*
fc32b0e2
LB		 571 * In case we received a packet without first / last bits
572 * on, or the error summary bit is set, the packet needs
573 * to be dropped.
1da177e4 574 */
96587661 575 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 576 (RX_FIRST_DESC | RX_LAST_DESC))
96587661 577 || (cmd_sts & ERROR_SUMMARY)) {
1da177e4 578 stats->rx_dropped++;
fc32b0e2 579
96587661 580 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 581 (RX_FIRST_DESC | RX_LAST_DESC)) {
1da177e4 582 if (net_ratelimit())
fc32b0e2
LB		 583 dev_printk(KERN_ERR, &mp->dev->dev,
584 "received packet spanning "
585 "multiple descriptors\n");
1da177e4 586 }
fc32b0e2 587
96587661 588 if (cmd_sts & ERROR_SUMMARY)
1da177e4
LT		 589 stats->rx_errors++;
590
591 dev_kfree_skb_irq(skb);
592 } else {
593 /*
594 * The -4 is for the CRC in the trailer of the
595 * received packet
596 */
fc32b0e2 597 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
1da177e4 598
96587661 599 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
1da177e4
LT		 600 skb->ip_summed = CHECKSUM_UNNECESSARY;
601 skb->csum = htons(
96587661 602 (cmd_sts & 0x0007fff8) >> 3);
1da177e4 603 }
8a578111 604 skb->protocol = eth_type_trans(skb, mp->dev);
e5371493 605#ifdef MV643XX_ETH_NAPI
1da177e4
LT		 606 netif_receive_skb(skb);
607#else
608 netif_rx(skb);
609#endif
610 }
fc32b0e2 611
8a578111 612 mp->dev->last_rx = jiffies;
1da177e4 613 }
fc32b0e2 614
8a578111 615 rxq_refill(rxq);
1da177e4 616
8a578111 617 return rx;
1da177e4
LT		 618}
619
e5371493 620#ifdef MV643XX_ETH_NAPI
e5371493 621static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
d0412d96 622{
8a578111
LB		 623 struct mv643xx_eth_private *mp;
624 int rx;
64da80a2 625 int i;
8a578111
LB		 626
627 mp = container_of(napi, struct mv643xx_eth_private, napi);
d0412d96 628
e5371493 629#ifdef MV643XX_ETH_TX_FAST_REFILL
c9df406f 630 if (++mp->tx_clean_threshold > 5) {
c9df406f 631 mp->tx_clean_threshold = 0;
3d6b35bc
LB		 632 for (i = 0; i < 8; i++)
633 if (mp->txq_mask & (1 << i))
634 txq_reclaim(mp->txq + i, 0);
4dfc1c87
LB		 635
636 if (netif_carrier_ok(mp->dev)) {
637 spin_lock(&mp->lock);
638 __txq_maybe_wake(mp->txq + mp->txq_primary);
639 spin_unlock(&mp->lock);
640 }
d0412d96 641 }
c9df406f 642#endif
d0412d96 643
64da80a2
LB		 644 rx = 0;
645 for (i = 7; rx < budget && i >= 0; i--)
646 if (mp->rxq_mask & (1 << i))
647 rx += rxq_process(mp->rxq + i, budget - rx);
d0412d96 648
8a578111
LB		 649 if (rx < budget) {
650 netif_rx_complete(mp->dev, napi);
651 wrl(mp, INT_CAUSE(mp->port_num), 0);
652 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
226bb6b7 653 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
d0412d96 654 }
c9df406f 655
8a578111 656 return rx;
d0412d96 657}
c9df406f 658#endif
d0412d96 659
c9df406f
LB		 660
661/* tx ***********************************************************************/
c9df406f 662static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 663{
13d64285 664 int frag;
1da177e4 665
c9df406f 666 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
13d64285
LB		 667 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
668 if (fragp->size <= 8 && fragp->page_offset & 7)
c9df406f 669 return 1;
1da177e4 670 }
13d64285 671
c9df406f
LB		 672 return 0;
673}
7303fde8 674
13d64285 675static int txq_alloc_desc_index(struct tx_queue *txq)
c9df406f
LB		 676{
677 int tx_desc_curr;
d0412d96 678
13d64285 679 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
1da177e4 680
13d64285
LB		 681 tx_desc_curr = txq->tx_curr_desc;
682 txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size;
e4d00fa9 683
13d64285 684 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
468d09f8 685
c9df406f
LB		 686 return tx_desc_curr;
687}
468d09f8 688
13d64285 689static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 690{
13d64285 691 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 692 int frag;
1da177e4 693
13d64285
LB		 694 for (frag = 0; frag < nr_frags; frag++) {
695 skb_frag_t *this_frag;
696 int tx_index;
697 struct tx_desc *desc;
698
699 this_frag = &skb_shinfo(skb)->frags[frag];
700 tx_index = txq_alloc_desc_index(txq);
701 desc = &txq->tx_desc_area[tx_index];
702
703 /*
704 * The last fragment will generate an interrupt
705 * which will free the skb on TX completion.
706 */
707 if (frag == nr_frags - 1) {
708 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
709 ZERO_PADDING | TX_LAST_DESC |
710 TX_ENABLE_INTERRUPT;
711 txq->tx_skb[tx_index] = skb;
712 } else {
713 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
714 txq->tx_skb[tx_index] = NULL;
715 }
716
c9df406f
LB		 717 desc->l4i_chk = 0;
718 desc->byte_cnt = this_frag->size;
719 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
720 this_frag->page_offset,
721 this_frag->size,
722 DMA_TO_DEVICE);
723 }
1da177e4
LT		 724}
725
c9df406f
LB		 726static inline __be16 sum16_as_be(__sum16 sum)
727{
728 return (__force __be16)sum;
729}
1da177e4 730
13d64285 731static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 732{
8fa89bf5 733 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 734 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 735 int tx_index;
cc9754b3 736 struct tx_desc *desc;
c9df406f
LB		 737 u32 cmd_sts;
738 int length;
1da177e4 739
cc9754b3 740 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
1da177e4 741
13d64285
LB		 742 tx_index = txq_alloc_desc_index(txq);
743 desc = &txq->tx_desc_area[tx_index];
c9df406f
LB		 744
745 if (nr_frags) {
13d64285 746 txq_submit_frag_skb(txq, skb);
c9df406f
LB		 747
748 length = skb_headlen(skb);
13d64285 749 txq->tx_skb[tx_index] = NULL;
c9df406f 750 } else {
cc9754b3 751 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
c9df406f 752 length = skb->len;
13d64285 753 txq->tx_skb[tx_index] = skb;
c9df406f
LB		 754 }
755
756 desc->byte_cnt = length;
757 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
758
759 if (skb->ip_summed == CHECKSUM_PARTIAL) {
760 BUG_ON(skb->protocol != htons(ETH_P_IP));
761
cc9754b3
LB		 762 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
763 GEN_IP_V4_CHECKSUM |
764 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
c9df406f
LB		 765
766 switch (ip_hdr(skb)->protocol) {
767 case IPPROTO_UDP:
cc9754b3 768 cmd_sts |= UDP_FRAME;
c9df406f
LB		 769 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
770 break;
771 case IPPROTO_TCP:
772 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
773 break;
774 default:
775 BUG();
776 }
777 } else {
778 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 779 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 780 desc->l4i_chk = 0;
781 }
782
783 /* ensure all other descriptors are written before first cmd_sts */
784 wmb();
785 desc->cmd_sts = cmd_sts;
786
8fa89bf5
LB		 787 /* clear TX_END interrupt status */
788 wrl(mp, INT_CAUSE(mp->port_num), ~(INT_TX_END_0 << txq->index));
789 rdl(mp, INT_CAUSE(mp->port_num));
790
c9df406f
LB		 791 /* ensure all descriptors are written before poking hardware */
792 wmb();
13d64285 793 txq_enable(txq);
c9df406f 794
13d64285 795 txq->tx_desc_count += nr_frags + 1;
1da177e4 796}
1da177e4 797
fc32b0e2 798static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 799{
e5371493 800 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 801 struct net_device_stats *stats = &dev->stats;
13d64285 802 struct tx_queue *txq;
c9df406f 803 unsigned long flags;
afdb57a2 804
c9df406f
LB		 805 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
806 stats->tx_dropped++;
fc32b0e2
LB		 807 dev_printk(KERN_DEBUG, &dev->dev,
808 "failed to linearize skb with tiny "
809 "unaligned fragment\n");
c9df406f
LB		 810 return NETDEV_TX_BUSY;
811 }
812
813 spin_lock_irqsave(&mp->lock, flags);
814
3d6b35bc 815 txq = mp->txq + mp->txq_primary;
13d64285
LB		 816
817 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) {
c9df406f 818 spin_unlock_irqrestore(&mp->lock, flags);
3d6b35bc
LB		 819 if (txq->index == mp->txq_primary && net_ratelimit())
820 dev_printk(KERN_ERR, &dev->dev,
821 "primary tx queue full?!\n");
822 kfree_skb(skb);
823 return NETDEV_TX_OK;
c9df406f
LB		 824 }
825
13d64285 826 txq_submit_skb(txq, skb);
c9df406f
LB		 827 stats->tx_bytes += skb->len;
828 stats->tx_packets++;
829 dev->trans_start = jiffies;
830
3d6b35bc
LB		 831 if (txq->index == mp->txq_primary) {
832 int entries_left;
833
834 entries_left = txq->tx_ring_size - txq->tx_desc_count;
835 if (entries_left < MAX_DESCS_PER_SKB)
836 netif_stop_queue(dev);
837 }
c9df406f
LB		 838
839 spin_unlock_irqrestore(&mp->lock, flags);
840
841 return NETDEV_TX_OK;
1da177e4
LT		 842}
843
c9df406f 844
89df5fdc
LB		 845/* tx rate control **********************************************************/
846/*
847 * Set total maximum TX rate (shared by all TX queues for this port)
848 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
849 */
850static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
851{
852 int token_rate;
853 int mtu;
854 int bucket_size;
855
856 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
857 if (token_rate > 1023)
858 token_rate = 1023;
859
860 mtu = (mp->dev->mtu + 255) >> 8;
861 if (mtu > 63)
862 mtu = 63;
863
864 bucket_size = (burst + 255) >> 8;
865 if (bucket_size > 65535)
866 bucket_size = 65535;
867
1e881592
LB		 868 if (mp->shared->tx_bw_control_moved) {
869 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
870 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
871 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
872 } else {
873 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
874 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
875 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
876 }
89df5fdc
LB		 877}
878
879static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
880{
881 struct mv643xx_eth_private *mp = txq_to_mp(txq);
882 int token_rate;
883 int bucket_size;
884
885 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
886 if (token_rate > 1023)
887 token_rate = 1023;
888
889 bucket_size = (burst + 255) >> 8;
890 if (bucket_size > 65535)
891 bucket_size = 65535;
892
3d6b35bc
LB		 893 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
894 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
89df5fdc
LB		 895 (bucket_size << 10) | token_rate);
896}
897
898static void txq_set_fixed_prio_mode(struct tx_queue *txq)
899{
900 struct mv643xx_eth_private *mp = txq_to_mp(txq);
901 int off;
902 u32 val;
903
904 /*
905 * Turn on fixed priority mode.
906 */
1e881592
LB		 907 if (mp->shared->tx_bw_control_moved)
908 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
909 else
910 off = TXQ_FIX_PRIO_CONF(mp->port_num);
89df5fdc
LB		 911
912 val = rdl(mp, off);
3d6b35bc 913 val |= 1 << txq->index;
89df5fdc
LB		 914 wrl(mp, off, val);
915}
916
917static void txq_set_wrr(struct tx_queue *txq, int weight)
918{
919 struct mv643xx_eth_private *mp = txq_to_mp(txq);
920 int off;
921 u32 val;
922
923 /*
924 * Turn off fixed priority mode.
925 */
1e881592
LB		 926 if (mp->shared->tx_bw_control_moved)
927 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
928 else
929 off = TXQ_FIX_PRIO_CONF(mp->port_num);
89df5fdc
LB		 930
931 val = rdl(mp, off);
3d6b35bc 932 val &= ~(1 << txq->index);
89df5fdc
LB		 933 wrl(mp, off, val);
934
935 /*
936 * Configure WRR weight for this queue.
937 */
3d6b35bc 938 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
89df5fdc
LB		 939
940 val = rdl(mp, off);
941 val = (val & ~0xff) | (weight & 0xff);
942 wrl(mp, off, val);
943}
944
945
c9df406f 946/* mii management interface *************************************************/
fc32b0e2
LB		 947#define SMI_BUSY 0x10000000
948#define SMI_READ_VALID 0x08000000
949#define SMI_OPCODE_READ 0x04000000
950#define SMI_OPCODE_WRITE 0x00000000
c9df406f 951
fc32b0e2
LB		 952static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr,
953 unsigned int reg, unsigned int *value)
1da177e4 954{
cc9754b3 955 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
c9df406f 956 unsigned long flags;
1da177e4
LT		 957 int i;
958
c9df406f
LB		 959 /* the SMI register is a shared resource */
960 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
961
962 /* wait for the SMI register to become available */
cc9754b3 963 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
e1bea50a 964 if (i == 1000) {
c9df406f
LB		 965 printk("%s: PHY busy timeout\n", mp->dev->name);
966 goto out;
967 }
e1bea50a 968 udelay(10);
1da177e4
LT		 969 }
970
fc32b0e2 971 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 972
c9df406f 973 /* now wait for the data to be valid */
cc9754b3 974 for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
e1bea50a 975 if (i == 1000) {
c9df406f
LB		 976 printk("%s: PHY read timeout\n", mp->dev->name);
977 goto out;
978 }
e1bea50a 979 udelay(10);
c9df406f
LB		 980 }
981
982 *value = readl(smi_reg) & 0xffff;
983out:
984 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1da177e4
LT		 985}
986
fc32b0e2
LB		 987static void smi_reg_write(struct mv643xx_eth_private *mp,
988 unsigned int addr,
989 unsigned int reg, unsigned int value)
1da177e4 990{
cc9754b3 991 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
c9df406f 992 unsigned long flags;
1da177e4
LT		 993 int i;
994
c9df406f
LB		 995 /* the SMI register is a shared resource */
996 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
997
998 /* wait for the SMI register to become available */
cc9754b3 999 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
e1bea50a 1000 if (i == 1000) {
c9df406f
LB		 1001 printk("%s: PHY busy timeout\n", mp->dev->name);
1002 goto out;
1003 }
e1bea50a 1004 udelay(10);
1da177e4
LT		 1005 }
1006
fc32b0e2
LB		 1007 writel(SMI_OPCODE_WRITE | (reg << 21) |
1008 (addr << 16) | (value & 0xffff), smi_reg);
c9df406f
LB		 1009out:
1010 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1011}
1da177e4 1012
c9df406f
LB		 1013
1014/* mib counters *************************************************************/
fc32b0e2 1015static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 1016{
fc32b0e2 1017 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 1018}
1019
fc32b0e2 1020static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 1021{
fc32b0e2
LB		 1022 int i;
1023
1024 for (i = 0; i < 0x80; i += 4)
1025 mib_read(mp, i);
c9df406f 1026}
d0412d96 1027
fc32b0e2 1028static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 1029{
e5371493 1030 struct mib_counters *p = &mp->mib_counters;
4b8e3655 1031
fc32b0e2
LB		 1032 p->good_octets_received += mib_read(mp, 0x00);
1033 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1034 p->bad_octets_received += mib_read(mp, 0x08);
1035 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1036 p->good_frames_received += mib_read(mp, 0x10);
1037 p->bad_frames_received += mib_read(mp, 0x14);
1038 p->broadcast_frames_received += mib_read(mp, 0x18);
1039 p->multicast_frames_received += mib_read(mp, 0x1c);
1040 p->frames_64_octets += mib_read(mp, 0x20);
1041 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1042 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1043 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1044 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1045 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1046 p->good_octets_sent += mib_read(mp, 0x38);
1047 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1048 p->good_frames_sent += mib_read(mp, 0x40);
1049 p->excessive_collision += mib_read(mp, 0x44);
1050 p->multicast_frames_sent += mib_read(mp, 0x48);
1051 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1052 p->unrec_mac_control_received += mib_read(mp, 0x50);
1053 p->fc_sent += mib_read(mp, 0x54);
1054 p->good_fc_received += mib_read(mp, 0x58);
1055 p->bad_fc_received += mib_read(mp, 0x5c);
1056 p->undersize_received += mib_read(mp, 0x60);
1057 p->fragments_received += mib_read(mp, 0x64);
1058 p->oversize_received += mib_read(mp, 0x68);
1059 p->jabber_received += mib_read(mp, 0x6c);
1060 p->mac_receive_error += mib_read(mp, 0x70);
1061 p->bad_crc_event += mib_read(mp, 0x74);
1062 p->collision += mib_read(mp, 0x78);
1063 p->late_collision += mib_read(mp, 0x7c);
d0412d96
JC		 1064}
1065
c9df406f
LB		 1066
1067/* ethtool ******************************************************************/
e5371493 1068struct mv643xx_eth_stats {
c9df406f
LB		 1069 char stat_string[ETH_GSTRING_LEN];
1070 int sizeof_stat;
16820054
LB		 1071 int netdev_off;
1072 int mp_off;
c9df406f
LB		 1073};
1074
16820054
LB		 1075#define SSTAT(m) \
1076 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1077 offsetof(struct net_device, stats.m), -1 }
1078
1079#define MIBSTAT(m) \
1080 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1081 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1082
1083static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1084 SSTAT(rx_packets),
1085 SSTAT(tx_packets),
1086 SSTAT(rx_bytes),
1087 SSTAT(tx_bytes),
1088 SSTAT(rx_errors),
1089 SSTAT(tx_errors),
1090 SSTAT(rx_dropped),
1091 SSTAT(tx_dropped),
1092 MIBSTAT(good_octets_received),
1093 MIBSTAT(bad_octets_received),
1094 MIBSTAT(internal_mac_transmit_err),
1095 MIBSTAT(good_frames_received),
1096 MIBSTAT(bad_frames_received),
1097 MIBSTAT(broadcast_frames_received),
1098 MIBSTAT(multicast_frames_received),
1099 MIBSTAT(frames_64_octets),
1100 MIBSTAT(frames_65_to_127_octets),
1101 MIBSTAT(frames_128_to_255_octets),
1102 MIBSTAT(frames_256_to_511_octets),
1103 MIBSTAT(frames_512_to_1023_octets),
1104 MIBSTAT(frames_1024_to_max_octets),
1105 MIBSTAT(good_octets_sent),
1106 MIBSTAT(good_frames_sent),
1107 MIBSTAT(excessive_collision),
1108 MIBSTAT(multicast_frames_sent),
1109 MIBSTAT(broadcast_frames_sent),
1110 MIBSTAT(unrec_mac_control_received),
1111 MIBSTAT(fc_sent),
1112 MIBSTAT(good_fc_received),
1113 MIBSTAT(bad_fc_received),
1114 MIBSTAT(undersize_received),
1115 MIBSTAT(fragments_received),
1116 MIBSTAT(oversize_received),
1117 MIBSTAT(jabber_received),
1118 MIBSTAT(mac_receive_error),
1119 MIBSTAT(bad_crc_event),
1120 MIBSTAT(collision),
1121 MIBSTAT(late_collision),
c9df406f
LB		 1122};
1123
e5371493 1124static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
d0412d96 1125{
e5371493 1126 struct mv643xx_eth_private *mp = netdev_priv(dev);
d0412d96
JC		 1127 int err;
1128
1129 spin_lock_irq(&mp->lock);
1130 err = mii_ethtool_gset(&mp->mii, cmd);
1131 spin_unlock_irq(&mp->lock);
1132
fc32b0e2
LB		 1133 /*
1134 * The MAC does not support 1000baseT_Half.
1135 */
d0412d96
JC		 1136 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1137 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1138
1139 return err;
1140}
1141
bedfe324
LB		 1142static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1143{
81600eea
LB		 1144 struct mv643xx_eth_private *mp = netdev_priv(dev);
1145 u32 port_status;
1146
1147 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1148
bedfe324
LB		 1149 cmd->supported = SUPPORTED_MII;
1150 cmd->advertising = ADVERTISED_MII;
81600eea
LB		 1151 switch (port_status & PORT_SPEED_MASK) {
1152 case PORT_SPEED_10:
1153 cmd->speed = SPEED_10;
1154 break;
1155 case PORT_SPEED_100:
1156 cmd->speed = SPEED_100;
1157 break;
1158 case PORT_SPEED_1000:
1159 cmd->speed = SPEED_1000;
1160 break;
1161 default:
1162 cmd->speed = -1;
1163 break;
1164 }
1165 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
bedfe324
LB		 1166 cmd->port = PORT_MII;
1167 cmd->phy_address = 0;
1168 cmd->transceiver = XCVR_INTERNAL;
1169 cmd->autoneg = AUTONEG_DISABLE;
1170 cmd->maxtxpkt = 1;
1171 cmd->maxrxpkt = 1;
1172
1173 return 0;
1174}
1175
e5371493 1176static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1177{
e5371493 1178 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6
DF		 1179 int err;
1180
fc32b0e2
LB		 1181 /*
1182 * The MAC does not support 1000baseT_Half.
1183 */
1184 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1185
c9df406f
LB		 1186 spin_lock_irq(&mp->lock);
1187 err = mii_ethtool_sset(&mp->mii, cmd);
1188 spin_unlock_irq(&mp->lock);
85cf572c 1189
c9df406f
LB		 1190 return err;
1191}
1da177e4 1192
bedfe324
LB		 1193static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1194{
1195 return -EINVAL;
1196}
1197
fc32b0e2
LB		 1198static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1199 struct ethtool_drvinfo *drvinfo)
c9df406f 1200{
e5371493
LB		 1201 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1202 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 1203 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 1204 strncpy(drvinfo->bus_info, "platform", 32);
16820054 1205 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1206}
1da177e4 1207
fc32b0e2 1208static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1209{
e5371493 1210 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1211
c9df406f
LB		 1212 return mii_nway_restart(&mp->mii);
1213}
1da177e4 1214
bedfe324
LB		 1215static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1216{
1217 return -EINVAL;
1218}
1219
c9df406f
LB		 1220static u32 mv643xx_eth_get_link(struct net_device *dev)
1221{
e5371493 1222 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1223
c9df406f
LB		 1224 return mii_link_ok(&mp->mii);
1225}
1da177e4 1226
bedfe324
LB		 1227static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1228{
1229 return 1;
1230}
1231
fc32b0e2
LB		 1232static void mv643xx_eth_get_strings(struct net_device *dev,
1233 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1234{
1235 int i;
1da177e4 1236
fc32b0e2
LB		 1237 if (stringset == ETH_SS_STATS) {
1238 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1239 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1240 mv643xx_eth_stats[i].stat_string,
e5371493 1241 ETH_GSTRING_LEN);
c9df406f 1242 }
c9df406f
LB		 1243 }
1244}
1da177e4 1245
fc32b0e2
LB		 1246static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1247 struct ethtool_stats *stats,
1248 uint64_t *data)
c9df406f 1249{
fc32b0e2 1250 struct mv643xx_eth_private *mp = dev->priv;
c9df406f 1251 int i;
1da177e4 1252
fc32b0e2 1253 mib_counters_update(mp);
1da177e4 1254
16820054
LB		 1255 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1256 const struct mv643xx_eth_stats *stat;
1257 void *p;
1258
1259 stat = mv643xx_eth_stats + i;
1260
1261 if (stat->netdev_off >= 0)
1262 p = ((void *)mp->dev) + stat->netdev_off;
1263 else
1264 p = ((void *)mp) + stat->mp_off;
1265
1266 data[i] = (stat->sizeof_stat == 8) ?
1267 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1268 }
c9df406f 1269}
1da177e4 1270
fc32b0e2 1271static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1272{
fc32b0e2 1273 if (sset == ETH_SS_STATS)
16820054 1274 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1275
1276 return -EOPNOTSUPP;
c9df406f 1277}
1da177e4 1278
e5371493 1279static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1280 .get_settings = mv643xx_eth_get_settings,
1281 .set_settings = mv643xx_eth_set_settings,
1282 .get_drvinfo = mv643xx_eth_get_drvinfo,
1283 .nway_reset = mv643xx_eth_nway_reset,
1284 .get_link = mv643xx_eth_get_link,
c9df406f 1285 .set_sg = ethtool_op_set_sg,
fc32b0e2
LB		 1286 .get_strings = mv643xx_eth_get_strings,
1287 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
e5371493 1288 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1289};
1da177e4 1290
bedfe324
LB		 1291static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1292 .get_settings = mv643xx_eth_get_settings_phyless,
1293 .set_settings = mv643xx_eth_set_settings_phyless,
1294 .get_drvinfo = mv643xx_eth_get_drvinfo,
1295 .nway_reset = mv643xx_eth_nway_reset_phyless,
1296 .get_link = mv643xx_eth_get_link_phyless,
1297 .set_sg = ethtool_op_set_sg,
1298 .get_strings = mv643xx_eth_get_strings,
1299 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1300 .get_sset_count = mv643xx_eth_get_sset_count,
1301};
1302
bea3348e 1303
c9df406f 1304/* address handling *********************************************************/
5daffe94 1305static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1306{
c9df406f
LB		 1307 unsigned int mac_h;
1308 unsigned int mac_l;
1da177e4 1309
fc32b0e2
LB		 1310 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1311 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1da177e4 1312
5daffe94
LB		 1313 addr[0] = (mac_h >> 24) & 0xff;
1314 addr[1] = (mac_h >> 16) & 0xff;
1315 addr[2] = (mac_h >> 8) & 0xff;
1316 addr[3] = mac_h & 0xff;
1317 addr[4] = (mac_l >> 8) & 0xff;
1318 addr[5] = mac_l & 0xff;
c9df406f 1319}
1da177e4 1320
e5371493 1321static void init_mac_tables(struct mv643xx_eth_private *mp)
c9df406f 1322{
fc32b0e2 1323 int i;
1da177e4 1324
fc32b0e2
LB		 1325 for (i = 0; i < 0x100; i += 4) {
1326 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1327 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
c9df406f 1328 }
fc32b0e2
LB		 1329
1330 for (i = 0; i < 0x10; i += 4)
1331 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
c9df406f 1332}
d0412d96 1333
e5371493 1334static void set_filter_table_entry(struct mv643xx_eth_private *mp,
fc32b0e2 1335 int table, unsigned char entry)
c9df406f
LB		 1336{
1337 unsigned int table_reg;
ab4384a6 1338
c9df406f 1339 /* Set "accepts frame bit" at specified table entry */
fc32b0e2
LB		 1340 table_reg = rdl(mp, table + (entry & 0xfc));
1341 table_reg |= 0x01 << (8 * (entry & 3));
1342 wrl(mp, table + (entry & 0xfc), table_reg);
1da177e4
LT		 1343}
1344
5daffe94 1345static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1da177e4 1346{
c9df406f
LB		 1347 unsigned int mac_h;
1348 unsigned int mac_l;
1349 int table;
1da177e4 1350
fc32b0e2
LB		 1351 mac_l = (addr[4] << 8) | addr[5];
1352 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
ff561eef 1353
fc32b0e2
LB		 1354 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1355 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1da177e4 1356
fc32b0e2 1357 table = UNICAST_TABLE(mp->port_num);
5daffe94 1358 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1da177e4
LT		 1359}
1360
fc32b0e2 1361static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1da177e4 1362{
e5371493 1363 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1364
fc32b0e2
LB		 1365 /* +2 is for the offset of the HW addr type */
1366 memcpy(dev->dev_addr, addr + 2, 6);
1367
cc9754b3
LB		 1368 init_mac_tables(mp);
1369 uc_addr_set(mp, dev->dev_addr);
1da177e4
LT		 1370
1371 return 0;
1372}
1373
69876569
LB		 1374static int addr_crc(unsigned char *addr)
1375{
1376 int crc = 0;
1377 int i;
1378
1379 for (i = 0; i < 6; i++) {
1380 int j;
1381
1382 crc = (crc ^ addr[i]) << 8;
1383 for (j = 7; j >= 0; j--) {
1384 if (crc & (0x100 << j))
1385 crc ^= 0x107 << j;
1386 }
1387 }
1388
1389 return crc;
1390}
1391
fc32b0e2 1392static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1da177e4 1393{
fc32b0e2
LB		 1394 struct mv643xx_eth_private *mp = netdev_priv(dev);
1395 u32 port_config;
1396 struct dev_addr_list *addr;
1397 int i;
c8aaea25 1398
fc32b0e2
LB		 1399 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1400 if (dev->flags & IFF_PROMISC)
1401 port_config |= UNICAST_PROMISCUOUS_MODE;
1402 else
1403 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1404 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1da177e4 1405
fc32b0e2
LB		 1406 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1407 int port_num = mp->port_num;
1408 u32 accept = 0x01010101;
c8aaea25 1409
fc32b0e2
LB		 1410 for (i = 0; i < 0x100; i += 4) {
1411 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1412 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1413 }
1414 return;
1415 }
c8aaea25 1416
fc32b0e2
LB		 1417 for (i = 0; i < 0x100; i += 4) {
1418 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1419 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1da177e4
LT		 1420 }
1421
fc32b0e2
LB		 1422 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1423 u8 *a = addr->da_addr;
1424 int table;
324ff2c1 1425
fc32b0e2
LB		 1426 if (addr->da_addrlen != 6)
1427 continue;
1da177e4 1428
fc32b0e2
LB		 1429 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1430 table = SPECIAL_MCAST_TABLE(mp->port_num);
1431 set_filter_table_entry(mp, table, a[5]);
1432 } else {
1433 int crc = addr_crc(a);
1da177e4 1434
fc32b0e2
LB		 1435 table = OTHER_MCAST_TABLE(mp->port_num);
1436 set_filter_table_entry(mp, table, crc);
1437 }
1438 }
c9df406f 1439}
c8aaea25 1440
c8aaea25 1441
c9df406f 1442/* rx/tx queue initialisation ***********************************************/
64da80a2 1443static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1444{
64da80a2 1445 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1446 struct rx_desc *rx_desc;
1447 int size;
c9df406f
LB		 1448 int i;
1449
64da80a2
LB		 1450 rxq->index = index;
1451
8a578111
LB		 1452 rxq->rx_ring_size = mp->default_rx_ring_size;
1453
1454 rxq->rx_desc_count = 0;
1455 rxq->rx_curr_desc = 0;
1456 rxq->rx_used_desc = 0;
1457
1458 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1459
64da80a2 1460 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1461 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1462 mp->rx_desc_sram_size);
1463 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1464 } else {
1465 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1466 &rxq->rx_desc_dma,
1467 GFP_KERNEL);
f7ea3337
PJ		 1468 }
1469
8a578111
LB		 1470 if (rxq->rx_desc_area == NULL) {
1471 dev_printk(KERN_ERR, &mp->dev->dev,
1472 "can't allocate rx ring (%d bytes)\n", size);
1473 goto out;
1474 }
1475 memset(rxq->rx_desc_area, 0, size);
1da177e4 1476
8a578111
LB		 1477 rxq->rx_desc_area_size = size;
1478 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1479 GFP_KERNEL);
1480 if (rxq->rx_skb == NULL) {
1481 dev_printk(KERN_ERR, &mp->dev->dev,
1482 "can't allocate rx skb ring\n");
1483 goto out_free;
1484 }
1485
1486 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1487 for (i = 0; i < rxq->rx_ring_size; i++) {
1488 int nexti = (i + 1) % rxq->rx_ring_size;
1489 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1490 nexti * sizeof(struct rx_desc);
1491 }
1492
1493 init_timer(&rxq->rx_oom);
1494 rxq->rx_oom.data = (unsigned long)rxq;
1495 rxq->rx_oom.function = rxq_refill_timer_wrapper;
1496
1497 return 0;
1498
1499
1500out_free:
64da80a2 1501 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size)
8a578111
LB		 1502 iounmap(rxq->rx_desc_area);
1503 else
1504 dma_free_coherent(NULL, size,
1505 rxq->rx_desc_area,
1506 rxq->rx_desc_dma);
1507
1508out:
1509 return -ENOMEM;
c9df406f 1510}
c8aaea25 1511
8a578111 1512static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1513{
8a578111
LB		 1514 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1515 int i;
1516
1517 rxq_disable(rxq);
c8aaea25 1518
8a578111 1519 del_timer_sync(&rxq->rx_oom);
c9df406f 1520
8a578111
LB		 1521 for (i = 0; i < rxq->rx_ring_size; i++) {
1522 if (rxq->rx_skb[i]) {
1523 dev_kfree_skb(rxq->rx_skb[i]);
1524 rxq->rx_desc_count--;
1da177e4 1525 }
c8aaea25 1526 }
1da177e4 1527
8a578111
LB		 1528 if (rxq->rx_desc_count) {
1529 dev_printk(KERN_ERR, &mp->dev->dev,
1530 "error freeing rx ring -- %d skbs stuck\n",
1531 rxq->rx_desc_count);
1532 }
1533
64da80a2
LB		 1534 if (rxq->index == mp->rxq_primary &&
1535 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1536 iounmap(rxq->rx_desc_area);
c9df406f 1537 else
8a578111
LB		 1538 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1539 rxq->rx_desc_area, rxq->rx_desc_dma);
1540
1541 kfree(rxq->rx_skb);
c9df406f 1542}
1da177e4 1543
3d6b35bc 1544static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1545{
3d6b35bc 1546 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1547 struct tx_desc *tx_desc;
1548 int size;
c9df406f 1549 int i;
1da177e4 1550
3d6b35bc
LB		 1551 txq->index = index;
1552
13d64285
LB		 1553 txq->tx_ring_size = mp->default_tx_ring_size;
1554
1555 txq->tx_desc_count = 0;
1556 txq->tx_curr_desc = 0;
1557 txq->tx_used_desc = 0;
1558
1559 size = txq->tx_ring_size * sizeof(struct tx_desc);
1560
3d6b35bc 1561 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) {
13d64285
LB		 1562 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1563 mp->tx_desc_sram_size);
1564 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1565 } else {
1566 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1567 &txq->tx_desc_dma,
1568 GFP_KERNEL);
1569 }
1570
1571 if (txq->tx_desc_area == NULL) {
1572 dev_printk(KERN_ERR, &mp->dev->dev,
1573 "can't allocate tx ring (%d bytes)\n", size);
1574 goto out;
c9df406f 1575 }
13d64285
LB		 1576 memset(txq->tx_desc_area, 0, size);
1577
1578 txq->tx_desc_area_size = size;
1579 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1580 GFP_KERNEL);
1581 if (txq->tx_skb == NULL) {
1582 dev_printk(KERN_ERR, &mp->dev->dev,
1583 "can't allocate tx skb ring\n");
1584 goto out_free;
1585 }
1586
1587 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1588 for (i = 0; i < txq->tx_ring_size; i++) {
6b368f68 1589 struct tx_desc *txd = tx_desc + i;
13d64285 1590 int nexti = (i + 1) % txq->tx_ring_size;
6b368f68
LB		 1591
1592 txd->cmd_sts = 0;
1593 txd->next_desc_ptr = txq->tx_desc_dma +
13d64285
LB		 1594 nexti * sizeof(struct tx_desc);
1595 }
1596
1597 return 0;
1598
c9df406f 1599
13d64285 1600out_free:
3d6b35bc 1601 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size)
13d64285
LB		 1602 iounmap(txq->tx_desc_area);
1603 else
1604 dma_free_coherent(NULL, size,
1605 txq->tx_desc_area,
1606 txq->tx_desc_dma);
c9df406f 1607
13d64285
LB		 1608out:
1609 return -ENOMEM;
c8aaea25 1610}
1da177e4 1611
13d64285 1612static void txq_reclaim(struct tx_queue *txq, int force)
c8aaea25 1613{
13d64285 1614 struct mv643xx_eth_private *mp = txq_to_mp(txq);
c8aaea25 1615 unsigned long flags;
1da177e4 1616
13d64285
LB		 1617 spin_lock_irqsave(&mp->lock, flags);
1618 while (txq->tx_desc_count > 0) {
1619 int tx_index;
1620 struct tx_desc *desc;
1621 u32 cmd_sts;
1622 struct sk_buff *skb;
1623 dma_addr_t addr;
1624 int count;
4d64e718 1625
13d64285
LB		 1626 tx_index = txq->tx_used_desc;
1627 desc = &txq->tx_desc_area[tx_index];
c9df406f 1628 cmd_sts = desc->cmd_sts;
4d64e718 1629
6b368f68
LB		 1630 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1631 if (!force)
1632 break;
1633 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1634 }
1da177e4 1635
13d64285
LB		 1636 txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size;
1637 txq->tx_desc_count--;
1da177e4 1638
c9df406f
LB		 1639 addr = desc->buf_ptr;
1640 count = desc->byte_cnt;
13d64285
LB		 1641 skb = txq->tx_skb[tx_index];
1642 txq->tx_skb[tx_index] = NULL;
c8aaea25 1643
cc9754b3 1644 if (cmd_sts & ERROR_SUMMARY) {
13d64285
LB		 1645 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1646 mp->dev->stats.tx_errors++;
c9df406f 1647 }
1da177e4 1648
13d64285
LB		 1649 /*
1650 * Drop mp->lock while we free the skb.
1651 */
c9df406f 1652 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 1653
cc9754b3 1654 if (cmd_sts & TX_FIRST_DESC)
c9df406f
LB		 1655 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1656 else
1657 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
c2e5b352 1658
c9df406f
LB		 1659 if (skb)
1660 dev_kfree_skb_irq(skb);
63c9e549 1661
13d64285 1662 spin_lock_irqsave(&mp->lock, flags);
c9df406f 1663 }
13d64285 1664 spin_unlock_irqrestore(&mp->lock, flags);
c9df406f 1665}
1da177e4 1666
13d64285 1667static void txq_deinit(struct tx_queue *txq)
c9df406f 1668{
13d64285 1669 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 1670
13d64285
LB		 1671 txq_disable(txq);
1672 txq_reclaim(txq, 1);
1da177e4 1673
13d64285 1674 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 1675
3d6b35bc
LB		 1676 if (txq->index == mp->txq_primary &&
1677 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 1678 iounmap(txq->tx_desc_area);
c9df406f 1679 else
13d64285
LB		 1680 dma_free_coherent(NULL, txq->tx_desc_area_size,
1681 txq->tx_desc_area, txq->tx_desc_dma);
1682
1683 kfree(txq->tx_skb);
c9df406f 1684}
1da177e4 1685
1da177e4 1686
c9df406f 1687/* netdev ops and related ***************************************************/
2f7eb47a
LB		 1688static void handle_link_event(struct mv643xx_eth_private *mp)
1689{
1690 struct net_device *dev = mp->dev;
1691 u32 port_status;
1692 int speed;
1693 int duplex;
1694 int fc;
1695
1696 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1697 if (!(port_status & LINK_UP)) {
1698 if (netif_carrier_ok(dev)) {
1699 int i;
1700
1701 printk(KERN_INFO "%s: link down\n", dev->name);
1702
1703 netif_carrier_off(dev);
1704 netif_stop_queue(dev);
1705
1706 for (i = 0; i < 8; i++) {
1707 struct tx_queue *txq = mp->txq + i;
1708
1709 if (mp->txq_mask & (1 << i)) {
1710 txq_reclaim(txq, 1);
1711 txq_reset_hw_ptr(txq);
1712 }
1713 }
1714 }
1715 return;
1716 }
1717
1718 switch (port_status & PORT_SPEED_MASK) {
1719 case PORT_SPEED_10:
1720 speed = 10;
1721 break;
1722 case PORT_SPEED_100:
1723 speed = 100;
1724 break;
1725 case PORT_SPEED_1000:
1726 speed = 1000;
1727 break;
1728 default:
1729 speed = -1;
1730 break;
1731 }
1732 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1733 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1734
1735 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1736 "flow control %sabled\n", dev->name,
1737 speed, duplex ? "full" : "half",
1738 fc ? "en" : "dis");
1739
1740 if (!netif_carrier_ok(dev)) {
1741 netif_carrier_on(dev);
1742 netif_wake_queue(dev);
1743 }
1744}
1745
fc32b0e2 1746static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
c9df406f
LB		 1747{
1748 struct net_device *dev = (struct net_device *)dev_id;
e5371493 1749 struct mv643xx_eth_private *mp = netdev_priv(dev);
fc32b0e2
LB		 1750 u32 int_cause;
1751 u32 int_cause_ext;
ce4e2e45 1752
226bb6b7
LB		 1753 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1754 (INT_TX_END | INT_RX | INT_EXT);
fc32b0e2
LB		 1755 if (int_cause == 0)
1756 return IRQ_NONE;
1757
1758 int_cause_ext = 0;
cc9754b3 1759 if (int_cause & INT_EXT) {
13d64285 1760 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
073a345c 1761 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
13d64285 1762 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
c9df406f 1763 }
1da177e4 1764
2f7eb47a
LB		 1765 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK))
1766 handle_link_event(mp);
1da177e4 1767
64da80a2
LB		 1768 /*
1769 * RxBuffer or RxError set for any of the 8 queues?
1770 */
e5371493 1771#ifdef MV643XX_ETH_NAPI
cc9754b3 1772 if (int_cause & INT_RX) {
13d64285 1773 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
13d64285 1774 rdl(mp, INT_MASK(mp->port_num));
1da177e4 1775
c9df406f 1776 netif_rx_schedule(dev, &mp->napi);
84dd619e 1777 }
c9df406f 1778#else
64da80a2
LB		 1779 if (int_cause & INT_RX) {
1780 int i;
1781
1782 for (i = 7; i >= 0; i--)
1783 if (mp->rxq_mask & (1 << i))
1784 rxq_process(mp->rxq + i, INT_MAX);
1785 }
c9df406f 1786#endif
fc32b0e2 1787
3d6b35bc
LB		 1788 /*
1789 * TxBuffer or TxError set for any of the 8 queues?
1790 */
13d64285 1791 if (int_cause_ext & INT_EXT_TX) {
3d6b35bc
LB		 1792 int i;
1793
1794 for (i = 0; i < 8; i++)
1795 if (mp->txq_mask & (1 << i))
1796 txq_reclaim(mp->txq + i, 0);
8fa89bf5
LB		 1797
1798 /*
1799 * Enough space again in the primary TX queue for a
1800 * full packet?
1801 */
6b368f68
LB		 1802 if (netif_carrier_ok(dev)) {
1803 spin_lock(&mp->lock);
1804 __txq_maybe_wake(mp->txq + mp->txq_primary);
1805 spin_unlock(&mp->lock);
1806 }
226bb6b7 1807 }
3d6b35bc 1808
226bb6b7
LB		 1809 /*
1810 * Any TxEnd interrupts?
1811 */
1812 if (int_cause & INT_TX_END) {
1813 int i;
1814
1815 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
8fa89bf5
LB		 1816
1817 spin_lock(&mp->lock);
226bb6b7
LB		 1818 for (i = 0; i < 8; i++) {
1819 struct tx_queue *txq = mp->txq + i;
8fa89bf5
LB		 1820 u32 hw_desc_ptr;
1821 u32 expected_ptr;
1822
1823 if ((int_cause & (INT_TX_END_0 << i)) == 0)
1824 continue;
1825
1826 hw_desc_ptr =
1827 rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, i));
1828 expected_ptr = (u32)txq->tx_desc_dma +
1829 txq->tx_curr_desc * sizeof(struct tx_desc);
1830
1831 if (hw_desc_ptr != expected_ptr)
226bb6b7
LB		 1832 txq_enable(txq);
1833 }
8fa89bf5 1834 spin_unlock(&mp->lock);
13d64285 1835 }
1da177e4 1836
c9df406f 1837 return IRQ_HANDLED;
1da177e4
LT		 1838}
1839
e5371493 1840static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 1841{
fc32b0e2 1842 unsigned int data;
1da177e4 1843
7f106c1d
LB		 1844 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data);
1845 data |= BMCR_RESET;
1846 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
1da177e4 1847
c9df406f
LB		 1848 do {
1849 udelay(1);
7f106c1d
LB		 1850 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data);
1851 } while (data & BMCR_RESET);
1da177e4
LT		 1852}
1853
fc32b0e2 1854static void port_start(struct mv643xx_eth_private *mp)
1da177e4 1855{
d0412d96 1856 u32 pscr;
8a578111 1857 int i;
1da177e4 1858
bedfe324
LB		 1859 /*
1860 * Perform PHY reset, if there is a PHY.
1861 */
1862 if (mp->phy_addr != -1) {
1863 struct ethtool_cmd cmd;
1864
1865 mv643xx_eth_get_settings(mp->dev, &cmd);
1866 phy_reset(mp);
1867 mv643xx_eth_set_settings(mp->dev, &cmd);
1868 }
1da177e4 1869
81600eea
LB		 1870 /*
1871 * Configure basic link parameters.
1872 */
1873 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1874
1875 pscr |= SERIAL_PORT_ENABLE;
1876 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1877
1878 pscr |= DO_NOT_FORCE_LINK_FAIL;
1879 if (mp->phy_addr == -1)
1880 pscr |= FORCE_LINK_PASS;
1881 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1882
1883 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1884
13d64285
LB		 1885 /*
1886 * Configure TX path and queues.
1887 */
89df5fdc 1888 tx_set_rate(mp, 1000000000, 16777216);
3d6b35bc
LB		 1889 for (i = 0; i < 8; i++) {
1890 struct tx_queue *txq = mp->txq + i;
13d64285 1891
3d6b35bc
LB		 1892 if ((mp->txq_mask & (1 << i)) == 0)
1893 continue;
1894
6b368f68 1895 txq_reset_hw_ptr(txq);
89df5fdc
LB		 1896 txq_set_rate(txq, 1000000000, 16777216);
1897 txq_set_fixed_prio_mode(txq);
13d64285
LB		 1898 }
1899
fc32b0e2
LB		 1900 /*
1901 * Add configured unicast address to address filter table.
1902 */
1903 uc_addr_set(mp, mp->dev->dev_addr);
1da177e4 1904
d9a073ea
LB		 1905 /*
1906 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1907 * frames to RX queue #0.
1908 */
8a578111 1909 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
01999873 1910
376489a2
LB		 1911 /*
1912 * Treat BPDUs as normal multicasts, and disable partition mode.
1913 */
8a578111 1914 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
01999873 1915
8a578111 1916 /*
64da80a2 1917 * Enable the receive queues.
8a578111 1918 */
64da80a2
LB		 1919 for (i = 0; i < 8; i++) {
1920 struct rx_queue *rxq = mp->rxq + i;
1921 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
8a578111 1922 u32 addr;
1da177e4 1923
64da80a2
LB		 1924 if ((mp->rxq_mask & (1 << i)) == 0)
1925 continue;
1926
8a578111
LB		 1927 addr = (u32)rxq->rx_desc_dma;
1928 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1929 wrl(mp, off, addr);
1da177e4 1930
8a578111
LB		 1931 rxq_enable(rxq);
1932 }
1da177e4
LT		 1933}
1934
ffd86bbe 1935static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 1936{
c9df406f 1937 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
773fc3ee 1938 u32 val;
1da177e4 1939
773fc3ee
LB		 1940 val = rdl(mp, SDMA_CONFIG(mp->port_num));
1941 if (mp->shared->extended_rx_coal_limit) {
1942 if (coal > 0xffff)
1943 coal = 0xffff;
1944 val &= ~0x023fff80;
1945 val |= (coal & 0x8000) << 10;
1946 val |= (coal & 0x7fff) << 7;
1947 } else {
1948 if (coal > 0x3fff)
1949 coal = 0x3fff;
1950 val &= ~0x003fff00;
1951 val |= (coal & 0x3fff) << 8;
1952 }
1953 wrl(mp, SDMA_CONFIG(mp->port_num), val);
1da177e4
LT		 1954}
1955
ffd86bbe 1956static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 1957{
c9df406f 1958 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 1959
fc32b0e2
LB		 1960 if (coal > 0x3fff)
1961 coal = 0x3fff;
1962 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
16e03018
DF		 1963}
1964
c9df406f 1965static int mv643xx_eth_open(struct net_device *dev)
16e03018 1966{
e5371493 1967 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1968 int err;
64da80a2 1969 int i;
16e03018 1970
fc32b0e2
LB		 1971 wrl(mp, INT_CAUSE(mp->port_num), 0);
1972 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
1973 rdl(mp, INT_CAUSE_EXT(mp->port_num));
c9df406f 1974
fc32b0e2
LB		 1975 err = request_irq(dev->irq, mv643xx_eth_irq,
1976 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
1977 dev->name, dev);
c9df406f 1978 if (err) {
fc32b0e2 1979 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
c9df406f 1980 return -EAGAIN;
16e03018
DF		 1981 }
1982
fc32b0e2 1983 init_mac_tables(mp);
16e03018 1984
64da80a2
LB		 1985 for (i = 0; i < 8; i++) {
1986 if ((mp->rxq_mask & (1 << i)) == 0)
1987 continue;
1988
1989 err = rxq_init(mp, i);
1990 if (err) {
1991 while (--i >= 0)
1992 if (mp->rxq_mask & (1 << i))
1993 rxq_deinit(mp->rxq + i);
1994 goto out;
1995 }
1996
1997 rxq_refill(mp->rxq + i);
1998 }
8a578111 1999
3d6b35bc
LB		 2000 for (i = 0; i < 8; i++) {
2001 if ((mp->txq_mask & (1 << i)) == 0)
2002 continue;
2003
2004 err = txq_init(mp, i);
2005 if (err) {
2006 while (--i >= 0)
2007 if (mp->txq_mask & (1 << i))
2008 txq_deinit(mp->txq + i);
2009 goto out_free;
2010 }
2011 }
16e03018 2012
e5371493 2013#ifdef MV643XX_ETH_NAPI
c9df406f
LB		 2014 napi_enable(&mp->napi);
2015#endif
16e03018 2016
2f7eb47a
LB		 2017 netif_carrier_off(dev);
2018 netif_stop_queue(dev);
2019
fc32b0e2 2020 port_start(mp);
16e03018 2021
ffd86bbe
LB		 2022 set_rx_coal(mp, 0);
2023 set_tx_coal(mp, 0);
16e03018 2024
fc32b0e2
LB		 2025 wrl(mp, INT_MASK_EXT(mp->port_num),
2026 INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
16e03018 2027
226bb6b7 2028 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
16e03018 2029
c9df406f
LB		 2030 return 0;
2031
13d64285 2032
fc32b0e2 2033out_free:
64da80a2
LB		 2034 for (i = 0; i < 8; i++)
2035 if (mp->rxq_mask & (1 << i))
2036 rxq_deinit(mp->rxq + i);
fc32b0e2 2037out:
c9df406f
LB		 2038 free_irq(dev->irq, dev);
2039
2040 return err;
16e03018
DF		 2041}
2042
e5371493 2043static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 2044{
fc32b0e2 2045 unsigned int data;
64da80a2 2046 int i;
1da177e4 2047
64da80a2
LB		 2048 for (i = 0; i < 8; i++) {
2049 if (mp->rxq_mask & (1 << i))
2050 rxq_disable(mp->rxq + i);
3d6b35bc
LB		 2051 if (mp->txq_mask & (1 << i))
2052 txq_disable(mp->txq + i);
64da80a2 2053 }
ae9ae064
LB		 2054
2055 while (1) {
2056 u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
2057
2058 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2059 break;
13d64285 2060 udelay(10);
ae9ae064 2061 }
1da177e4 2062
c9df406f 2063 /* Reset the Enable bit in the Configuration Register */
fc32b0e2
LB		 2064 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2065 data &= ~(SERIAL_PORT_ENABLE |
2066 DO_NOT_FORCE_LINK_FAIL |
2067 FORCE_LINK_PASS);
2068 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
1da177e4
LT		 2069}
2070
c9df406f 2071static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 2072{
e5371493 2073 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 2074 int i;
1da177e4 2075
fc32b0e2
LB		 2076 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2077 rdl(mp, INT_MASK(mp->port_num));
1da177e4 2078
e5371493 2079#ifdef MV643XX_ETH_NAPI
c9df406f
LB		 2080 napi_disable(&mp->napi);
2081#endif
2082 netif_carrier_off(dev);
2083 netif_stop_queue(dev);
1da177e4 2084
fc32b0e2
LB		 2085 free_irq(dev->irq, dev);
2086
cc9754b3 2087 port_reset(mp);
fc32b0e2 2088 mib_counters_update(mp);
1da177e4 2089
64da80a2
LB		 2090 for (i = 0; i < 8; i++) {
2091 if (mp->rxq_mask & (1 << i))
2092 rxq_deinit(mp->rxq + i);
3d6b35bc
LB		 2093 if (mp->txq_mask & (1 << i))
2094 txq_deinit(mp->txq + i);
64da80a2 2095 }
1da177e4 2096
c9df406f 2097 return 0;
1da177e4
LT		 2098}
2099
fc32b0e2 2100static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 2101{
e5371493 2102 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2103
bedfe324
LB		 2104 if (mp->phy_addr != -1)
2105 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2106
2107 return -EOPNOTSUPP;
1da177e4
LT		 2108}
2109
c9df406f 2110static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 2111{
89df5fdc
LB		 2112 struct mv643xx_eth_private *mp = netdev_priv(dev);
2113
fc32b0e2 2114 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 2115 return -EINVAL;
1da177e4 2116
c9df406f 2117 dev->mtu = new_mtu;
89df5fdc
LB		 2118 tx_set_rate(mp, 1000000000, 16777216);
2119
c9df406f
LB		 2120 if (!netif_running(dev))
2121 return 0;
1da177e4 2122
c9df406f
LB		 2123 /*
2124 * Stop and then re-open the interface. This will allocate RX
2125 * skbs of the new MTU.
2126 * There is a possible danger that the open will not succeed,
fc32b0e2 2127 * due to memory being full.
c9df406f
LB		 2128 */
2129 mv643xx_eth_stop(dev);
2130 if (mv643xx_eth_open(dev)) {
fc32b0e2
LB		 2131 dev_printk(KERN_ERR, &dev->dev,
2132 "fatal error on re-opening device after "
2133 "MTU change\n");
c9df406f
LB		 2134 }
2135
2136 return 0;
1da177e4
LT		 2137}
2138
fc32b0e2 2139static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2140{
fc32b0e2 2141 struct mv643xx_eth_private *mp;
1da177e4 2142
fc32b0e2
LB		 2143 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2144 if (netif_running(mp->dev)) {
2145 netif_stop_queue(mp->dev);
c9df406f 2146
fc32b0e2
LB		 2147 port_reset(mp);
2148 port_start(mp);
c9df406f 2149
3d6b35bc 2150 __txq_maybe_wake(mp->txq + mp->txq_primary);
fc32b0e2 2151 }
c9df406f
LB		 2152}
2153
c9df406f 2154static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2155{
e5371493 2156 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2157
fc32b0e2 2158 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
d0412d96 2159
c9df406f 2160 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2161}
2162
c9df406f 2163#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2164static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2165{
fc32b0e2 2166 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2167
fc32b0e2
LB		 2168 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2169 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2170
fc32b0e2 2171 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2172
f2ca60f2 2173 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
9f8dd319 2174}
c9df406f 2175#endif
9f8dd319 2176
fc32b0e2 2177static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
9f8dd319 2178{
e5371493 2179 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f
LB		 2180 int val;
2181
fc32b0e2
LB		 2182 smi_reg_read(mp, addr, reg, &val);
2183
c9df406f 2184 return val;
9f8dd319
DF		 2185}
2186
fc32b0e2 2187static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
9f8dd319 2188{
e5371493 2189 struct mv643xx_eth_private *mp = netdev_priv(dev);
fc32b0e2 2190 smi_reg_write(mp, addr, reg, val);
c9df406f 2191}
9f8dd319 2192
9f8dd319 2193
c9df406f 2194/* platform glue ************************************************************/
e5371493
LB		 2195static void
2196mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2197 struct mbus_dram_target_info *dram)
c9df406f 2198{
cc9754b3 2199 void __iomem *base = msp->base;
c9df406f
LB		 2200 u32 win_enable;
2201 u32 win_protect;
2202 int i;
9f8dd319 2203
c9df406f
LB		 2204 for (i = 0; i < 6; i++) {
2205 writel(0, base + WINDOW_BASE(i));
2206 writel(0, base + WINDOW_SIZE(i));
2207 if (i < 4)
2208 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2209 }
2210
c9df406f
LB		 2211 win_enable = 0x3f;
2212 win_protect = 0;
2213
2214 for (i = 0; i < dram->num_cs; i++) {
2215 struct mbus_dram_window *cs = dram->cs + i;
2216
2217 writel((cs->base & 0xffff0000) |
2218 (cs->mbus_attr << 8) |
2219 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2220 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2221
2222 win_enable &= ~(1 << i);
2223 win_protect |= 3 << (2 * i);
2224 }
2225
2226 writel(win_enable, base + WINDOW_BAR_ENABLE);
2227 msp->win_protect = win_protect;
9f8dd319
DF		 2228}
2229
773fc3ee
LB		 2230static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2231{
2232 /*
2233 * Check whether we have a 14-bit coal limit field in bits
2234 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2235 * SDMA config register.
2236 */
2237 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2238 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2239 msp->extended_rx_coal_limit = 1;
2240 else
2241 msp->extended_rx_coal_limit = 0;
1e881592
LB		 2242
2243 /*
2244 * Check whether the TX rate control registers are in the
2245 * old or the new place.
2246 */
2247 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2248 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
2249 msp->tx_bw_control_moved = 1;
2250 else
2251 msp->tx_bw_control_moved = 0;
773fc3ee
LB		 2252}
2253
c9df406f 2254static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2255{
e5371493 2256 static int mv643xx_eth_version_printed = 0;
c9df406f 2257 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2258 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 2259 struct resource *res;
2260 int ret;
9f8dd319 2261
e5371493 2262 if (!mv643xx_eth_version_printed++)
7dde154d
LB		 2263 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2264 "driver version %s\n", mv643xx_eth_driver_version);
9f8dd319 2265
c9df406f
LB		 2266 ret = -EINVAL;
2267 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2268 if (res == NULL)
2269 goto out;
9f8dd319 2270
c9df406f
LB		 2271 ret = -ENOMEM;
2272 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2273 if (msp == NULL)
2274 goto out;
2275 memset(msp, 0, sizeof(*msp));
2276
cc9754b3
LB		 2277 msp->base = ioremap(res->start, res->end - res->start + 1);
2278 if (msp->base == NULL)
c9df406f
LB		 2279 goto out_free;
2280
2281 spin_lock_init(&msp->phy_lock);
c9df406f
LB		 2282
2283 /*
2284 * (Re-)program MBUS remapping windows if we are asked to.
2285 */
2286 if (pd != NULL && pd->dram != NULL)
2287 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2288
fc32b0e2
LB		 2289 /*
2290 * Detect hardware parameters.
2291 */
2292 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
773fc3ee 2293 infer_hw_params(msp);
fc32b0e2
LB		 2294
2295 platform_set_drvdata(pdev, msp);
2296
c9df406f
LB		 2297 return 0;
2298
2299out_free:
2300 kfree(msp);
2301out:
2302 return ret;
2303}
2304
2305static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2306{
e5371493 2307 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
c9df406f 2308
cc9754b3 2309 iounmap(msp->base);
c9df406f
LB		 2310 kfree(msp);
2311
2312 return 0;
9f8dd319
DF		 2313}
2314
c9df406f 2315static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2316 .probe = mv643xx_eth_shared_probe,
2317 .remove = mv643xx_eth_shared_remove,
c9df406f 2318 .driver = {
fc32b0e2 2319 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2320 .owner = THIS_MODULE,
2321 },
2322};
2323
e5371493 2324static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2325{
c9df406f 2326 int addr_shift = 5 * mp->port_num;
fc32b0e2 2327 u32 data;
1da177e4 2328
fc32b0e2
LB		 2329 data = rdl(mp, PHY_ADDR);
2330 data &= ~(0x1f << addr_shift);
2331 data |= (phy_addr & 0x1f) << addr_shift;
2332 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2333}
2334
e5371493 2335static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2336{
fc32b0e2
LB		 2337 unsigned int data;
2338
2339 data = rdl(mp, PHY_ADDR);
2340
2341 return (data >> (5 * mp->port_num)) & 0x1f;
2342}
2343
2344static void set_params(struct mv643xx_eth_private *mp,
2345 struct mv643xx_eth_platform_data *pd)
2346{
2347 struct net_device *dev = mp->dev;
2348
2349 if (is_valid_ether_addr(pd->mac_addr))
2350 memcpy(dev->dev_addr, pd->mac_addr, 6);
2351 else
2352 uc_addr_get(mp, dev->dev_addr);
2353
2354 if (pd->phy_addr == -1) {
2355 mp->shared_smi = NULL;
2356 mp->phy_addr = -1;
2357 } else {
2358 mp->shared_smi = mp->shared;
2359 if (pd->shared_smi != NULL)
2360 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2361
2362 if (pd->force_phy_addr || pd->phy_addr) {
2363 mp->phy_addr = pd->phy_addr & 0x3f;
2364 phy_addr_set(mp, mp->phy_addr);
2365 } else {
2366 mp->phy_addr = phy_addr_get(mp);
2367 }
2368 }
1da177e4 2369
fc32b0e2
LB		 2370 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2371 if (pd->rx_queue_size)
2372 mp->default_rx_ring_size = pd->rx_queue_size;
2373 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2374 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2375
64da80a2
LB		 2376 if (pd->rx_queue_mask)
2377 mp->rxq_mask = pd->rx_queue_mask;
2378 else
2379 mp->rxq_mask = 0x01;
2380 mp->rxq_primary = fls(mp->rxq_mask) - 1;
2381
fc32b0e2
LB		 2382 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2383 if (pd->tx_queue_size)
2384 mp->default_tx_ring_size = pd->tx_queue_size;
2385 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2386 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc
LB		 2387
2388 if (pd->tx_queue_mask)
2389 mp->txq_mask = pd->tx_queue_mask;
2390 else
2391 mp->txq_mask = 0x01;
2392 mp->txq_primary = fls(mp->txq_mask) - 1;
1da177e4
LT		 2393}
2394
e5371493 2395static int phy_detect(struct mv643xx_eth_private *mp)
1da177e4 2396{
fc32b0e2
LB		 2397 unsigned int data;
2398 unsigned int data2;
2399
7f106c1d
LB		 2400 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data);
2401 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data ^ BMCR_ANENABLE);
1da177e4 2402
7f106c1d
LB		 2403 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data2);
2404 if (((data ^ data2) & BMCR_ANENABLE) == 0)
fc32b0e2 2405 return -ENODEV;
1da177e4 2406
7f106c1d 2407 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
1da177e4 2408
c9df406f 2409 return 0;
1da177e4
LT		 2410}
2411
fc32b0e2
LB		 2412static int phy_init(struct mv643xx_eth_private *mp,
2413 struct mv643xx_eth_platform_data *pd)
c28a4f89 2414{
fc32b0e2
LB		 2415 struct ethtool_cmd cmd;
2416 int err;
c28a4f89 2417
fc32b0e2
LB		 2418 err = phy_detect(mp);
2419 if (err) {
2420 dev_printk(KERN_INFO, &mp->dev->dev,
2421 "no PHY detected at addr %d\n", mp->phy_addr);
2422 return err;
2423 }
2424 phy_reset(mp);
2425
2426 mp->mii.phy_id = mp->phy_addr;
2427 mp->mii.phy_id_mask = 0x3f;
2428 mp->mii.reg_num_mask = 0x1f;
2429 mp->mii.dev = mp->dev;
2430 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2431 mp->mii.mdio_write = mv643xx_eth_mdio_write;
c28a4f89 2432
fc32b0e2 2433 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
c9df406f 2434
fc32b0e2
LB		 2435 memset(&cmd, 0, sizeof(cmd));
2436
2437 cmd.port = PORT_MII;
2438 cmd.transceiver = XCVR_INTERNAL;
2439 cmd.phy_address = mp->phy_addr;
2440 if (pd->speed == 0) {
2441 cmd.autoneg = AUTONEG_ENABLE;
2442 cmd.speed = SPEED_100;
2443 cmd.advertising = ADVERTISED_10baseT_Half |
2444 ADVERTISED_10baseT_Full |
2445 ADVERTISED_100baseT_Half |
2446 ADVERTISED_100baseT_Full;
c9df406f 2447 if (mp->mii.supports_gmii)
fc32b0e2 2448 cmd.advertising |= ADVERTISED_1000baseT_Full;
c9df406f 2449 } else {
fc32b0e2
LB		 2450 cmd.autoneg = AUTONEG_DISABLE;
2451 cmd.speed = pd->speed;
2452 cmd.duplex = pd->duplex;
c9df406f 2453 }
fc32b0e2 2454
fc32b0e2
LB		 2455 mv643xx_eth_set_settings(mp->dev, &cmd);
2456
2457 return 0;
c28a4f89
JC		 2458}
2459
81600eea
LB		 2460static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2461{
2462 u32 pscr;
2463
2464 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2465 if (pscr & SERIAL_PORT_ENABLE) {
2466 pscr &= ~SERIAL_PORT_ENABLE;
2467 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2468 }
2469
2470 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2471 if (mp->phy_addr == -1) {
2472 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2473 if (speed == SPEED_1000)
2474 pscr |= SET_GMII_SPEED_TO_1000;
2475 else if (speed == SPEED_100)
2476 pscr |= SET_MII_SPEED_TO_100;
2477
2478 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2479
2480 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2481 if (duplex == DUPLEX_FULL)
2482 pscr |= SET_FULL_DUPLEX_MODE;
2483 }
2484
2485 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2486}
2487
c9df406f 2488static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2489{
c9df406f 2490 struct mv643xx_eth_platform_data *pd;
e5371493 2491 struct mv643xx_eth_private *mp;
c9df406f 2492 struct net_device *dev;
c9df406f 2493 struct resource *res;
c9df406f 2494 DECLARE_MAC_BUF(mac);
fc32b0e2 2495 int err;
1da177e4 2496
c9df406f
LB		 2497 pd = pdev->dev.platform_data;
2498 if (pd == NULL) {
fc32b0e2
LB		 2499 dev_printk(KERN_ERR, &pdev->dev,
2500 "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2501 return -ENODEV;
2502 }
1da177e4 2503
c9df406f 2504 if (pd->shared == NULL) {
fc32b0e2
LB		 2505 dev_printk(KERN_ERR, &pdev->dev,
2506 "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2507 return -ENODEV;
2508 }
8f518703 2509
e5371493 2510 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
c9df406f
LB		 2511 if (!dev)
2512 return -ENOMEM;
1da177e4 2513
c9df406f 2514 mp = netdev_priv(dev);
fc32b0e2
LB		 2515 platform_set_drvdata(pdev, mp);
2516
2517 mp->shared = platform_get_drvdata(pd->shared);
2518 mp->port_num = pd->port_number;
2519
c9df406f 2520 mp->dev = dev;
e5371493
LB		 2521#ifdef MV643XX_ETH_NAPI
2522 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
c9df406f 2523#endif
1da177e4 2524
fc32b0e2
LB		 2525 set_params(mp, pd);
2526
2527 spin_lock_init(&mp->lock);
2528
2529 mib_counters_clear(mp);
2530 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2531
bedfe324
LB		 2532 if (mp->phy_addr != -1) {
2533 err = phy_init(mp, pd);
2534 if (err)
2535 goto out;
2536
2537 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2538 } else {
2539 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2540 }
81600eea 2541 init_pscr(mp, pd->speed, pd->duplex);
fc32b0e2
LB		 2542
2543
c9df406f
LB		 2544 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2545 BUG_ON(!res);
2546 dev->irq = res->start;
1da177e4 2547
fc32b0e2 2548 dev->hard_start_xmit = mv643xx_eth_xmit;
c9df406f
LB		 2549 dev->open = mv643xx_eth_open;
2550 dev->stop = mv643xx_eth_stop;
c9df406f 2551 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
fc32b0e2
LB		 2552 dev->set_mac_address = mv643xx_eth_set_mac_address;
2553 dev->do_ioctl = mv643xx_eth_ioctl;
2554 dev->change_mtu = mv643xx_eth_change_mtu;
c9df406f 2555 dev->tx_timeout = mv643xx_eth_tx_timeout;
c9df406f 2556#ifdef CONFIG_NET_POLL_CONTROLLER
e5371493 2557 dev->poll_controller = mv643xx_eth_netpoll;
c9df406f 2558#endif
c9df406f
LB		 2559 dev->watchdog_timeo = 2 * HZ;
2560 dev->base_addr = 0;
1da177e4 2561
e5371493 2562#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
b4de9051 2563 /*
c9df406f
LB		 2564 * Zero copy can only work if we use Discovery II memory. Else, we will
2565 * have to map the buffers to ISA memory which is only 16 MB
b4de9051 2566 */
c9df406f 2567 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
c9df406f 2568#endif
1da177e4 2569
fc32b0e2 2570 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2571
c9df406f 2572 if (mp->shared->win_protect)
fc32b0e2 2573 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2574
c9df406f
LB		 2575 err = register_netdev(dev);
2576 if (err)
2577 goto out;
1da177e4 2578
fc32b0e2
LB		 2579 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2580 mp->port_num, print_mac(mac, dev->dev_addr));
1da177e4 2581
c9df406f 2582 if (dev->features & NETIF_F_SG)
fc32b0e2 2583 dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n");
1da177e4 2584
c9df406f 2585 if (dev->features & NETIF_F_IP_CSUM)
fc32b0e2 2586 dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n");
1da177e4 2587
e5371493 2588#ifdef MV643XX_ETH_NAPI
fc32b0e2 2589 dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n");
c9df406f 2590#endif
1da177e4 2591
13d64285 2592 if (mp->tx_desc_sram_size > 0)
fc32b0e2 2593 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
1da177e4 2594
c9df406f 2595 return 0;
1da177e4 2596
c9df406f
LB		 2597out:
2598 free_netdev(dev);
1da177e4 2599
c9df406f 2600 return err;
1da177e4
LT		 2601}
2602
c9df406f 2603static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2604{
fc32b0e2 2605 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2606
fc32b0e2 2607 unregister_netdev(mp->dev);
c9df406f 2608 flush_scheduled_work();
fc32b0e2 2609 free_netdev(mp->dev);
c9df406f 2610
c9df406f 2611 platform_set_drvdata(pdev, NULL);
fc32b0e2 2612
c9df406f 2613 return 0;
1da177e4
LT		 2614}
2615
c9df406f 2616static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2617{
fc32b0e2 2618 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 2619
c9df406f 2620 /* Mask all interrupts on ethernet port */
fc32b0e2
LB		 2621 wrl(mp, INT_MASK(mp->port_num), 0);
2622 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2623
fc32b0e2
LB		 2624 if (netif_running(mp->dev))
2625 port_reset(mp);
d0412d96
JC		 2626}
2627
c9df406f 2628static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 2629 .probe = mv643xx_eth_probe,
2630 .remove = mv643xx_eth_remove,
2631 .shutdown = mv643xx_eth_shutdown,
c9df406f 2632 .driver = {
fc32b0e2 2633 .name = MV643XX_ETH_NAME,
c9df406f
LB		 2634 .owner = THIS_MODULE,
2635 },
2636};
2637
e5371493 2638static int __init mv643xx_eth_init_module(void)
d0412d96 2639{
c9df406f 2640 int rc;
d0412d96 2641
c9df406f
LB		 2642 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2643 if (!rc) {
2644 rc = platform_driver_register(&mv643xx_eth_driver);
2645 if (rc)
2646 platform_driver_unregister(&mv643xx_eth_shared_driver);
2647 }
fc32b0e2 2648
c9df406f 2649 return rc;
d0412d96 2650}
fc32b0e2 2651module_init(mv643xx_eth_init_module);
d0412d96 2652
e5371493 2653static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 2654{
c9df406f
LB		 2655 platform_driver_unregister(&mv643xx_eth_driver);
2656 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 2657}
e5371493 2658module_exit(mv643xx_eth_cleanup_module);
1da177e4 2659
45675bc6
LB		 2660MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2661 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
c9df406f 2662MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 2663MODULE_LICENSE("GPL");
c9df406f 2664MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 2665MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux kernel - Deliverables
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