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[deliverable/linux.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
c3efab8e 41#include <linux/ip.h>
1da177e4
LT		 42#include <linux/tcp.h>
43#include <linux/udp.h>
44#include <linux/etherdevice.h>
1da177e4
LT		 45#include <linux/delay.h>
46#include <linux/ethtool.h>
d052d1be 47#include <linux/platform_device.h>
fbd6a754
LB		 48#include <linux/module.h>
49#include <linux/kernel.h>
50#include <linux/spinlock.h>
51#include <linux/workqueue.h>
ed94493f 52#include <linux/phy.h>
fbd6a754 53#include <linux/mv643xx_eth.h>
10a9948d
LB		 54#include <linux/io.h>
55#include <linux/types.h>
eaf5d590 56#include <linux/inet_lro.h>
1da177e4 57#include <asm/system.h>
ccffad25 58#include <linux/list.h>
fbd6a754 59
e5371493 60static char mv643xx_eth_driver_name[] = "mv643xx_eth";
042af53c 61static char mv643xx_eth_driver_version[] = "1.4";
c9df406f 62
fbd6a754 63
fbd6a754
LB		 64/*
65 * Registers shared between all ports.
66 */
3cb4667c
LB		 67#define PHY_ADDR 0x0000
68#define SMI_REG 0x0004
45c5d3bc
LB		 69#define SMI_BUSY 0x10000000
70#define SMI_READ_VALID 0x08000000
71#define SMI_OPCODE_READ 0x04000000
72#define SMI_OPCODE_WRITE 0x00000000
73#define ERR_INT_CAUSE 0x0080
74#define ERR_INT_SMI_DONE 0x00000010
75#define ERR_INT_MASK 0x0084
3cb4667c
LB		 76#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
77#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
78#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
79#define WINDOW_BAR_ENABLE 0x0290
80#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 81
82/*
37a6084f
LB		 83 * Main per-port registers. These live at offset 0x0400 for
84 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
fbd6a754 85 */
37a6084f 86#define PORT_CONFIG 0x0000
d9a073ea 87#define UNICAST_PROMISCUOUS_MODE 0x00000001
37a6084f
LB		 88#define PORT_CONFIG_EXT 0x0004
89#define MAC_ADDR_LOW 0x0014
90#define MAC_ADDR_HIGH 0x0018
91#define SDMA_CONFIG 0x001c
becfad97
LB		 92#define TX_BURST_SIZE_16_64BIT 0x01000000
93#define TX_BURST_SIZE_4_64BIT 0x00800000
94#define BLM_TX_NO_SWAP 0x00000020
95#define BLM_RX_NO_SWAP 0x00000010
96#define RX_BURST_SIZE_16_64BIT 0x00000008
97#define RX_BURST_SIZE_4_64BIT 0x00000004
37a6084f 98#define PORT_SERIAL_CONTROL 0x003c
becfad97
LB		 99#define SET_MII_SPEED_TO_100 0x01000000
100#define SET_GMII_SPEED_TO_1000 0x00800000
101#define SET_FULL_DUPLEX_MODE 0x00200000
102#define MAX_RX_PACKET_9700BYTE 0x000a0000
103#define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
104#define DO_NOT_FORCE_LINK_FAIL 0x00000400
105#define SERIAL_PORT_CONTROL_RESERVED 0x00000200
106#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
107#define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
108#define FORCE_LINK_PASS 0x00000002
109#define SERIAL_PORT_ENABLE 0x00000001
37a6084f 110#define PORT_STATUS 0x0044
a2a41689 111#define TX_FIFO_EMPTY 0x00000400
ae9ae064 112#define TX_IN_PROGRESS 0x00000080
2f7eb47a
LB		 113#define PORT_SPEED_MASK 0x00000030
114#define PORT_SPEED_1000 0x00000010
115#define PORT_SPEED_100 0x00000020
116#define PORT_SPEED_10 0x00000000
117#define FLOW_CONTROL_ENABLED 0x00000008
118#define FULL_DUPLEX 0x00000004
81600eea 119#define LINK_UP 0x00000002
37a6084f
LB		 120#define TXQ_COMMAND 0x0048
121#define TXQ_FIX_PRIO_CONF 0x004c
122#define TX_BW_RATE 0x0050
123#define TX_BW_MTU 0x0058
124#define TX_BW_BURST 0x005c
125#define INT_CAUSE 0x0060
226bb6b7 126#define INT_TX_END 0x07f80000
e0ca8410 127#define INT_TX_END_0 0x00080000
befefe21 128#define INT_RX 0x000003fc
e0ca8410 129#define INT_RX_0 0x00000004
073a345c 130#define INT_EXT 0x00000002
37a6084f 131#define INT_CAUSE_EXT 0x0064
befefe21
LB		 132#define INT_EXT_LINK_PHY 0x00110000
133#define INT_EXT_TX 0x000000ff
37a6084f
LB		 134#define INT_MASK 0x0068
135#define INT_MASK_EXT 0x006c
136#define TX_FIFO_URGENT_THRESHOLD 0x0074
137#define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
138#define TX_BW_RATE_MOVED 0x00e0
139#define TX_BW_MTU_MOVED 0x00e8
140#define TX_BW_BURST_MOVED 0x00ec
141#define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
142#define RXQ_COMMAND 0x0280
143#define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
144#define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
145#define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
146#define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
147
148/*
149 * Misc per-port registers.
150 */
3cb4667c
LB		 151#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
152#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
153#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
154#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 155
2679a550
LB		 156
157/*
becfad97 158 * SDMA configuration register default value.
2679a550 159 */
fbd6a754
LB		 160#if defined(__BIG_ENDIAN)
161#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
e0c6ef93
LB		 162 (RX_BURST_SIZE_4_64BIT | \
163 TX_BURST_SIZE_4_64BIT)
fbd6a754
LB		 164#elif defined(__LITTLE_ENDIAN)
165#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
e0c6ef93
LB		 166 (RX_BURST_SIZE_4_64BIT | \
167 BLM_RX_NO_SWAP | \
168 BLM_TX_NO_SWAP | \
169 TX_BURST_SIZE_4_64BIT)
fbd6a754
LB		 170#else
171#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
172#endif
173
2beff77b
LB		 174
175/*
becfad97 176 * Misc definitions.
2beff77b 177 */
becfad97
LB		 178#define DEFAULT_RX_QUEUE_SIZE 128
179#define DEFAULT_TX_QUEUE_SIZE 256
7fd96ce4 180#define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
fbd6a754 181
fbd6a754 182
7ca72a3b
LB		 183/*
184 * RX/TX descriptors.
fbd6a754
LB		 185 */
186#if defined(__BIG_ENDIAN)
cc9754b3 187struct rx_desc {
fbd6a754
LB		 188 u16 byte_cnt; /* Descriptor buffer byte count */
189 u16 buf_size; /* Buffer size */
190 u32 cmd_sts; /* Descriptor command status */
191 u32 next_desc_ptr; /* Next descriptor pointer */
192 u32 buf_ptr; /* Descriptor buffer pointer */
193};
194
cc9754b3 195struct tx_desc {
fbd6a754
LB		 196 u16 byte_cnt; /* buffer byte count */
197 u16 l4i_chk; /* CPU provided TCP checksum */
198 u32 cmd_sts; /* Command/status field */
199 u32 next_desc_ptr; /* Pointer to next descriptor */
200 u32 buf_ptr; /* pointer to buffer for this descriptor*/
201};
202#elif defined(__LITTLE_ENDIAN)
cc9754b3 203struct rx_desc {
fbd6a754
LB		 204 u32 cmd_sts; /* Descriptor command status */
205 u16 buf_size; /* Buffer size */
206 u16 byte_cnt; /* Descriptor buffer byte count */
207 u32 buf_ptr; /* Descriptor buffer pointer */
208 u32 next_desc_ptr; /* Next descriptor pointer */
209};
210
cc9754b3 211struct tx_desc {
fbd6a754
LB		 212 u32 cmd_sts; /* Command/status field */
213 u16 l4i_chk; /* CPU provided TCP checksum */
214 u16 byte_cnt; /* buffer byte count */
215 u32 buf_ptr; /* pointer to buffer for this descriptor*/
216 u32 next_desc_ptr; /* Pointer to next descriptor */
217};
218#else
219#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
220#endif
221
7ca72a3b 222/* RX & TX descriptor command */
cc9754b3 223#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 224
225/* RX & TX descriptor status */
cc9754b3 226#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 227
228/* RX descriptor status */
cc9754b3
LB		 229#define LAYER_4_CHECKSUM_OK 0x40000000
230#define RX_ENABLE_INTERRUPT 0x20000000
231#define RX_FIRST_DESC 0x08000000
232#define RX_LAST_DESC 0x04000000
eaf5d590
LB		 233#define RX_IP_HDR_OK 0x02000000
234#define RX_PKT_IS_IPV4 0x01000000
235#define RX_PKT_IS_ETHERNETV2 0x00800000
236#define RX_PKT_LAYER4_TYPE_MASK 0x00600000
237#define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
238#define RX_PKT_IS_VLAN_TAGGED 0x00080000
7ca72a3b
LB		 239
240/* TX descriptor command */
cc9754b3
LB		 241#define TX_ENABLE_INTERRUPT 0x00800000
242#define GEN_CRC 0x00400000
243#define TX_FIRST_DESC 0x00200000
244#define TX_LAST_DESC 0x00100000
245#define ZERO_PADDING 0x00080000
246#define GEN_IP_V4_CHECKSUM 0x00040000
247#define GEN_TCP_UDP_CHECKSUM 0x00020000
248#define UDP_FRAME 0x00010000
e32b6617
LB		 249#define MAC_HDR_EXTRA_4_BYTES 0x00008000
250#define MAC_HDR_EXTRA_8_BYTES 0x00000200
7ca72a3b 251
cc9754b3 252#define TX_IHL_SHIFT 11
7ca72a3b
LB		 253
254
c9df406f 255/* global *******************************************************************/
e5371493 256struct mv643xx_eth_shared_private {
fc32b0e2
LB		 257 /*
258 * Ethernet controller base address.
259 */
cc9754b3 260 void __iomem *base;
c9df406f 261
fc0eb9f2
LB		 262 /*
263 * Points at the right SMI instance to use.
264 */
265 struct mv643xx_eth_shared_private *smi;
266
fc32b0e2 267 /*
ed94493f 268 * Provides access to local SMI interface.
fc32b0e2 269 */
298cf9be 270 struct mii_bus *smi_bus;
c9df406f 271
45c5d3bc
LB		 272 /*
273 * If we have access to the error interrupt pin (which is
274 * somewhat misnamed as it not only reflects internal errors
275 * but also reflects SMI completion), use that to wait for
276 * SMI access completion instead of polling the SMI busy bit.
277 */
278 int err_interrupt;
279 wait_queue_head_t smi_busy_wait;
280
fc32b0e2
LB		 281 /*
282 * Per-port MBUS window access register value.
283 */
c9df406f
LB		 284 u32 win_protect;
285
fc32b0e2
LB		 286 /*
287 * Hardware-specific parameters.
288 */
c9df406f 289 unsigned int t_clk;
773fc3ee 290 int extended_rx_coal_limit;
457b1d5a 291 int tx_bw_control;
c9df406f
LB		 292};
293
457b1d5a
LB		 294#define TX_BW_CONTROL_ABSENT 0
295#define TX_BW_CONTROL_OLD_LAYOUT 1
296#define TX_BW_CONTROL_NEW_LAYOUT 2
297
e7d2f4db
LB		 298static int mv643xx_eth_open(struct net_device *dev);
299static int mv643xx_eth_stop(struct net_device *dev);
300
c9df406f
LB		 301
302/* per-port *****************************************************************/
e5371493 303struct mib_counters {
fbd6a754
LB		 304 u64 good_octets_received;
305 u32 bad_octets_received;
306 u32 internal_mac_transmit_err;
307 u32 good_frames_received;
308 u32 bad_frames_received;
309 u32 broadcast_frames_received;
310 u32 multicast_frames_received;
311 u32 frames_64_octets;
312 u32 frames_65_to_127_octets;
313 u32 frames_128_to_255_octets;
314 u32 frames_256_to_511_octets;
315 u32 frames_512_to_1023_octets;
316 u32 frames_1024_to_max_octets;
317 u64 good_octets_sent;
318 u32 good_frames_sent;
319 u32 excessive_collision;
320 u32 multicast_frames_sent;
321 u32 broadcast_frames_sent;
322 u32 unrec_mac_control_received;
323 u32 fc_sent;
324 u32 good_fc_received;
325 u32 bad_fc_received;
326 u32 undersize_received;
327 u32 fragments_received;
328 u32 oversize_received;
329 u32 jabber_received;
330 u32 mac_receive_error;
331 u32 bad_crc_event;
332 u32 collision;
333 u32 late_collision;
334};
335
eaf5d590
LB		 336struct lro_counters {
337 u32 lro_aggregated;
338 u32 lro_flushed;
339 u32 lro_no_desc;
340};
341
8a578111 342struct rx_queue {
64da80a2
LB		 343 int index;
344
8a578111
LB		 345 int rx_ring_size;
346
347 int rx_desc_count;
348 int rx_curr_desc;
349 int rx_used_desc;
350
351 struct rx_desc *rx_desc_area;
352 dma_addr_t rx_desc_dma;
353 int rx_desc_area_size;
354 struct sk_buff **rx_skb;
eaf5d590 355
eaf5d590
LB		 356 struct net_lro_mgr lro_mgr;
357 struct net_lro_desc lro_arr[8];
8a578111
LB		 358};
359
13d64285 360struct tx_queue {
3d6b35bc
LB		 361 int index;
362
13d64285 363 int tx_ring_size;
fbd6a754 364
13d64285
LB		 365 int tx_desc_count;
366 int tx_curr_desc;
367 int tx_used_desc;
fbd6a754 368
5daffe94 369 struct tx_desc *tx_desc_area;
fbd6a754
LB		 370 dma_addr_t tx_desc_dma;
371 int tx_desc_area_size;
99ab08e0
LB		 372
373 struct sk_buff_head tx_skb;
8fd89211
LB		 374
375 unsigned long tx_packets;
376 unsigned long tx_bytes;
377 unsigned long tx_dropped;
13d64285
LB		 378};
379
380struct mv643xx_eth_private {
381 struct mv643xx_eth_shared_private *shared;
37a6084f 382 void __iomem *base;
fc32b0e2 383 int port_num;
13d64285 384
fc32b0e2 385 struct net_device *dev;
fbd6a754 386
ed94493f 387 struct phy_device *phy;
fbd6a754 388
4ff3495a
LB		 389 struct timer_list mib_counters_timer;
390 spinlock_t mib_counters_lock;
fc32b0e2 391 struct mib_counters mib_counters;
4ff3495a 392
eaf5d590
LB		 393 struct lro_counters lro_counters;
394
fc32b0e2 395 struct work_struct tx_timeout_task;
8a578111 396
1fa38c58 397 struct napi_struct napi;
e0ca8410 398 u32 int_mask;
1319ebad 399 u8 oom;
1fa38c58
LB		 400 u8 work_link;
401 u8 work_tx;
402 u8 work_tx_end;
403 u8 work_rx;
404 u8 work_rx_refill;
1fa38c58 405
2bcb4b0f
LB		 406 int skb_size;
407 struct sk_buff_head rx_recycle;
408
8a578111
LB		 409 /*
410 * RX state.
411 */
e7d2f4db 412 int rx_ring_size;
8a578111
LB		 413 unsigned long rx_desc_sram_addr;
414 int rx_desc_sram_size;
f7981c1c 415 int rxq_count;
2257e05c 416 struct timer_list rx_oom;
64da80a2 417 struct rx_queue rxq[8];
13d64285
LB		 418
419 /*
420 * TX state.
421 */
e7d2f4db 422 int tx_ring_size;
13d64285
LB		 423 unsigned long tx_desc_sram_addr;
424 int tx_desc_sram_size;
f7981c1c 425 int txq_count;
3d6b35bc 426 struct tx_queue txq[8];
fbd6a754 427};
1da177e4 428
fbd6a754 429
c9df406f 430/* port register accessors **************************************************/
e5371493 431static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 432{
cc9754b3 433 return readl(mp->shared->base + offset);
c9df406f 434}
fbd6a754 435
37a6084f
LB		 436static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
437{
438 return readl(mp->base + offset);
439}
440
e5371493 441static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 442{
cc9754b3 443 writel(data, mp->shared->base + offset);
c9df406f 444}
fbd6a754 445
37a6084f
LB		 446static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
447{
448 writel(data, mp->base + offset);
449}
450
fbd6a754 451
c9df406f 452/* rxq/txq helper functions *************************************************/
8a578111 453static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 454{
64da80a2 455 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 456}
fbd6a754 457
13d64285
LB		 458static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
459{
3d6b35bc 460 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 461}
462
8a578111 463static void rxq_enable(struct rx_queue *rxq)
c9df406f 464{
8a578111 465 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
37a6084f 466 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
8a578111 467}
1da177e4 468
8a578111
LB		 469static void rxq_disable(struct rx_queue *rxq)
470{
471 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 472 u8 mask = 1 << rxq->index;
1da177e4 473
37a6084f
LB		 474 wrlp(mp, RXQ_COMMAND, mask << 8);
475 while (rdlp(mp, RXQ_COMMAND) & mask)
8a578111 476 udelay(10);
c9df406f
LB		 477}
478
6b368f68
LB		 479static void txq_reset_hw_ptr(struct tx_queue *txq)
480{
481 struct mv643xx_eth_private *mp = txq_to_mp(txq);
6b368f68
LB		 482 u32 addr;
483
484 addr = (u32)txq->tx_desc_dma;
485 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
37a6084f 486 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
6b368f68
LB		 487}
488
13d64285 489static void txq_enable(struct tx_queue *txq)
1da177e4 490{
13d64285 491 struct mv643xx_eth_private *mp = txq_to_mp(txq);
37a6084f 492 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
1da177e4
LT		 493}
494
13d64285 495static void txq_disable(struct tx_queue *txq)
1da177e4 496{
13d64285 497 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 498 u8 mask = 1 << txq->index;
c9df406f 499
37a6084f
LB		 500 wrlp(mp, TXQ_COMMAND, mask << 8);
501 while (rdlp(mp, TXQ_COMMAND) & mask)
13d64285
LB		 502 udelay(10);
503}
504
1fa38c58 505static void txq_maybe_wake(struct tx_queue *txq)
13d64285
LB		 506{
507 struct mv643xx_eth_private *mp = txq_to_mp(txq);
e5ef1de1 508 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
3d6b35bc 509
8fd89211
LB		 510 if (netif_tx_queue_stopped(nq)) {
511 __netif_tx_lock(nq, smp_processor_id());
512 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
513 netif_tx_wake_queue(nq);
514 __netif_tx_unlock(nq);
515 }
1da177e4
LT		 516}
517
c9df406f 518
1fa38c58 519/* rx napi ******************************************************************/
eaf5d590
LB		 520static int
521mv643xx_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph,
522 u64 *hdr_flags, void *priv)
523{
524 unsigned long cmd_sts = (unsigned long)priv;
525
526 /*
527 * Make sure that this packet is Ethernet II, is not VLAN
528 * tagged, is IPv4, has a valid IP header, and is TCP.
529 */
530 if ((cmd_sts & (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
531 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_MASK |
532 RX_PKT_IS_VLAN_TAGGED)) !=
533 (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
534 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_TCP_IPV4))
535 return -1;
536
537 skb_reset_network_header(skb);
538 skb_set_transport_header(skb, ip_hdrlen(skb));
539 *iphdr = ip_hdr(skb);
540 *tcph = tcp_hdr(skb);
541 *hdr_flags = LRO_IPV4 | LRO_TCP;
542
543 return 0;
544}
eaf5d590 545
8a578111 546static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 547{
8a578111
LB		 548 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
549 struct net_device_stats *stats = &mp->dev->stats;
eaf5d590 550 int lro_flush_needed;
8a578111 551 int rx;
1da177e4 552
eaf5d590 553 lro_flush_needed = 0;
8a578111 554 rx = 0;
9e1f3772 555 while (rx < budget && rxq->rx_desc_count) {
fc32b0e2 556 struct rx_desc *rx_desc;
96587661 557 unsigned int cmd_sts;
fc32b0e2 558 struct sk_buff *skb;
6b8f90c2 559 u16 byte_cnt;
ff561eef 560
8a578111 561 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 562
96587661 563 cmd_sts = rx_desc->cmd_sts;
2257e05c 564 if (cmd_sts & BUFFER_OWNED_BY_DMA)
96587661 565 break;
96587661 566 rmb();
1da177e4 567
8a578111
LB		 568 skb = rxq->rx_skb[rxq->rx_curr_desc];
569 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 570
9da78745
LB		 571 rxq->rx_curr_desc++;
572 if (rxq->rx_curr_desc == rxq->rx_ring_size)
573 rxq->rx_curr_desc = 0;
ff561eef 574
eb0519b5 575 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
abe78717 576 rx_desc->buf_size, DMA_FROM_DEVICE);
8a578111
LB		 577 rxq->rx_desc_count--;
578 rx++;
b1dd9ca1 579
1fa38c58
LB		 580 mp->work_rx_refill |= 1 << rxq->index;
581
6b8f90c2
LB		 582 byte_cnt = rx_desc->byte_cnt;
583
468d09f8
DF		 584 /*
585 * Update statistics.
fc32b0e2
LB		 586 *
587 * Note that the descriptor byte count includes 2 dummy
588 * bytes automatically inserted by the hardware at the
589 * start of the packet (which we don't count), and a 4
590 * byte CRC at the end of the packet (which we do count).
468d09f8 591 */
1da177e4 592 stats->rx_packets++;
6b8f90c2 593 stats->rx_bytes += byte_cnt - 2;
96587661 594
1da177e4 595 /*
fc32b0e2
LB		 596 * In case we received a packet without first / last bits
597 * on, or the error summary bit is set, the packet needs
598 * to be dropped.
1da177e4 599 */
f61e5547
LB		 600 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
601 != (RX_FIRST_DESC | RX_LAST_DESC))
602 goto err;
603
604 /*
605 * The -4 is for the CRC in the trailer of the
606 * received packet
607 */
608 skb_put(skb, byte_cnt - 2 - 4);
609
610 if (cmd_sts & LAYER_4_CHECKSUM_OK)
611 skb->ip_summed = CHECKSUM_UNNECESSARY;
612 skb->protocol = eth_type_trans(skb, mp->dev);
eaf5d590 613
eaf5d590
LB		 614 if (skb->dev->features & NETIF_F_LRO &&
615 skb->ip_summed == CHECKSUM_UNNECESSARY) {
616 lro_receive_skb(&rxq->lro_mgr, skb, (void *)cmd_sts);
617 lro_flush_needed = 1;
618 } else
eaf5d590 619 netif_receive_skb(skb);
f61e5547
LB		 620
621 continue;
622
623err:
624 stats->rx_dropped++;
625
626 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
627 (RX_FIRST_DESC | RX_LAST_DESC)) {
628 if (net_ratelimit())
629 dev_printk(KERN_ERR, &mp->dev->dev,
630 "received packet spanning "
631 "multiple descriptors\n");
1da177e4 632 }
f61e5547
LB		 633
634 if (cmd_sts & ERROR_SUMMARY)
635 stats->rx_errors++;
636
637 dev_kfree_skb(skb);
1da177e4 638 }
fc32b0e2 639
eaf5d590
LB		 640 if (lro_flush_needed)
641 lro_flush_all(&rxq->lro_mgr);
eaf5d590 642
1fa38c58
LB		 643 if (rx < budget)
644 mp->work_rx &= ~(1 << rxq->index);
645
8a578111 646 return rx;
1da177e4
LT		 647}
648
1fa38c58 649static int rxq_refill(struct rx_queue *rxq, int budget)
d0412d96 650{
1fa38c58 651 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1fa38c58 652 int refilled;
8a578111 653
1fa38c58
LB		 654 refilled = 0;
655 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
656 struct sk_buff *skb;
1fa38c58 657 int rx;
53771522 658 struct rx_desc *rx_desc;
d0412d96 659
2bcb4b0f
LB		 660 skb = __skb_dequeue(&mp->rx_recycle);
661 if (skb == NULL)
7fd96ce4 662 skb = dev_alloc_skb(mp->skb_size);
2bcb4b0f 663
1fa38c58 664 if (skb == NULL) {
1319ebad 665 mp->oom = 1;
1fa38c58
LB		 666 goto oom;
667 }
d0412d96 668
7fd96ce4
LB		 669 if (SKB_DMA_REALIGN)
670 skb_reserve(skb, SKB_DMA_REALIGN);
2257e05c 671
1fa38c58
LB		 672 refilled++;
673 rxq->rx_desc_count++;
c9df406f 674
1fa38c58
LB		 675 rx = rxq->rx_used_desc++;
676 if (rxq->rx_used_desc == rxq->rx_ring_size)
677 rxq->rx_used_desc = 0;
2257e05c 678
53771522
LB		 679 rx_desc = rxq->rx_desc_area + rx;
680
eb0519b5
GP		 681 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
682 skb->data, mp->skb_size,
683 DMA_FROM_DEVICE);
53771522 684 rx_desc->buf_size = mp->skb_size;
1fa38c58
LB		 685 rxq->rx_skb[rx] = skb;
686 wmb();
53771522 687 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
1fa38c58 688 wmb();
2257e05c 689
1fa38c58
LB		 690 /*
691 * The hardware automatically prepends 2 bytes of
692 * dummy data to each received packet, so that the
693 * IP header ends up 16-byte aligned.
694 */
695 skb_reserve(skb, 2);
696 }
697
698 if (refilled < budget)
699 mp->work_rx_refill &= ~(1 << rxq->index);
700
701oom:
702 return refilled;
d0412d96
JC		 703}
704
c9df406f
LB		 705
706/* tx ***********************************************************************/
c9df406f 707static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 708{
13d64285 709 int frag;
1da177e4 710
c9df406f 711 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
13d64285
LB		 712 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
713 if (fragp->size <= 8 && fragp->page_offset & 7)
c9df406f 714 return 1;
1da177e4 715 }
13d64285 716
c9df406f
LB		 717 return 0;
718}
7303fde8 719
13d64285 720static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 721{
eb0519b5 722 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 723 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 724 int frag;
1da177e4 725
13d64285
LB		 726 for (frag = 0; frag < nr_frags; frag++) {
727 skb_frag_t *this_frag;
728 int tx_index;
729 struct tx_desc *desc;
730
731 this_frag = &skb_shinfo(skb)->frags[frag];
66823b92
LB		 732 tx_index = txq->tx_curr_desc++;
733 if (txq->tx_curr_desc == txq->tx_ring_size)
734 txq->tx_curr_desc = 0;
13d64285
LB		 735 desc = &txq->tx_desc_area[tx_index];
736
737 /*
738 * The last fragment will generate an interrupt
739 * which will free the skb on TX completion.
740 */
741 if (frag == nr_frags - 1) {
742 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
743 ZERO_PADDING | TX_LAST_DESC |
744 TX_ENABLE_INTERRUPT;
13d64285
LB		 745 } else {
746 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
13d64285
LB		 747 }
748
c9df406f
LB		 749 desc->l4i_chk = 0;
750 desc->byte_cnt = this_frag->size;
eb0519b5
GP		 751 desc->buf_ptr = dma_map_page(mp->dev->dev.parent,
752 this_frag->page,
753 this_frag->page_offset,
754 this_frag->size, DMA_TO_DEVICE);
c9df406f 755 }
1da177e4
LT		 756}
757
c9df406f
LB		 758static inline __be16 sum16_as_be(__sum16 sum)
759{
760 return (__force __be16)sum;
761}
1da177e4 762
4df89bd5 763static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 764{
8fa89bf5 765 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 766 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 767 int tx_index;
cc9754b3 768 struct tx_desc *desc;
c9df406f 769 u32 cmd_sts;
4df89bd5 770 u16 l4i_chk;
c9df406f 771 int length;
1da177e4 772
cc9754b3 773 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
4df89bd5 774 l4i_chk = 0;
c9df406f
LB		 775
776 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4df89bd5 777 int tag_bytes;
e32b6617
LB		 778
779 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
780 skb->protocol != htons(ETH_P_8021Q));
c9df406f 781
4df89bd5
LB		 782 tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN;
783 if (unlikely(tag_bytes & ~12)) {
784 if (skb_checksum_help(skb) == 0)
785 goto no_csum;
786 kfree_skb(skb);
787 return 1;
788 }
c9df406f 789
4df89bd5 790 if (tag_bytes & 4)
e32b6617 791 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
4df89bd5 792 if (tag_bytes & 8)
e32b6617 793 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
4df89bd5
LB		 794
795 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
796 GEN_IP_V4_CHECKSUM |
797 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
e32b6617 798
c9df406f
LB		 799 switch (ip_hdr(skb)->protocol) {
800 case IPPROTO_UDP:
cc9754b3 801 cmd_sts |= UDP_FRAME;
4df89bd5 802 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
c9df406f
LB		 803 break;
804 case IPPROTO_TCP:
4df89bd5 805 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
c9df406f
LB		 806 break;
807 default:
808 BUG();
809 }
810 } else {
4df89bd5 811no_csum:
c9df406f 812 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 813 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 814 }
815
66823b92
LB		 816 tx_index = txq->tx_curr_desc++;
817 if (txq->tx_curr_desc == txq->tx_ring_size)
818 txq->tx_curr_desc = 0;
4df89bd5
LB		 819 desc = &txq->tx_desc_area[tx_index];
820
821 if (nr_frags) {
822 txq_submit_frag_skb(txq, skb);
823 length = skb_headlen(skb);
824 } else {
825 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
826 length = skb->len;
827 }
828
829 desc->l4i_chk = l4i_chk;
830 desc->byte_cnt = length;
eb0519b5
GP		 831 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
832 length, DMA_TO_DEVICE);
4df89bd5 833
99ab08e0
LB		 834 __skb_queue_tail(&txq->tx_skb, skb);
835
c9df406f
LB		 836 /* ensure all other descriptors are written before first cmd_sts */
837 wmb();
838 desc->cmd_sts = cmd_sts;
839
1fa38c58
LB		 840 /* clear TX_END status */
841 mp->work_tx_end &= ~(1 << txq->index);
8fa89bf5 842
c9df406f
LB		 843 /* ensure all descriptors are written before poking hardware */
844 wmb();
13d64285 845 txq_enable(txq);
c9df406f 846
13d64285 847 txq->tx_desc_count += nr_frags + 1;
4df89bd5
LB		 848
849 return 0;
1da177e4 850}
1da177e4 851
fc32b0e2 852static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 853{
e5371493 854 struct mv643xx_eth_private *mp = netdev_priv(dev);
e5ef1de1 855 int queue;
13d64285 856 struct tx_queue *txq;
e5ef1de1 857 struct netdev_queue *nq;
afdb57a2 858
8fd89211
LB		 859 queue = skb_get_queue_mapping(skb);
860 txq = mp->txq + queue;
861 nq = netdev_get_tx_queue(dev, queue);
862
c9df406f 863 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
8fd89211 864 txq->tx_dropped++;
fc32b0e2
LB		 865 dev_printk(KERN_DEBUG, &dev->dev,
866 "failed to linearize skb with tiny "
867 "unaligned fragment\n");
c9df406f
LB		 868 return NETDEV_TX_BUSY;
869 }
870
17cd0a59 871 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
e5ef1de1
LB		 872 if (net_ratelimit())
873 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
3d6b35bc
LB		 874 kfree_skb(skb);
875 return NETDEV_TX_OK;
c9df406f
LB		 876 }
877
4df89bd5
LB		 878 if (!txq_submit_skb(txq, skb)) {
879 int entries_left;
880
881 txq->tx_bytes += skb->len;
882 txq->tx_packets++;
883 dev->trans_start = jiffies;
c9df406f 884
4df89bd5
LB		 885 entries_left = txq->tx_ring_size - txq->tx_desc_count;
886 if (entries_left < MAX_SKB_FRAGS + 1)
887 netif_tx_stop_queue(nq);
888 }
c9df406f 889
c9df406f 890 return NETDEV_TX_OK;
1da177e4
LT		 891}
892
c9df406f 893
1fa38c58
LB		 894/* tx napi ******************************************************************/
895static void txq_kick(struct tx_queue *txq)
896{
897 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 898 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 899 u32 hw_desc_ptr;
900 u32 expected_ptr;
901
8fd89211 902 __netif_tx_lock(nq, smp_processor_id());
1fa38c58 903
37a6084f 904 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
1fa38c58
LB		 905 goto out;
906
37a6084f 907 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
1fa38c58
LB		 908 expected_ptr = (u32)txq->tx_desc_dma +
909 txq->tx_curr_desc * sizeof(struct tx_desc);
910
911 if (hw_desc_ptr != expected_ptr)
912 txq_enable(txq);
913
914out:
8fd89211 915 __netif_tx_unlock(nq);
1fa38c58
LB		 916
917 mp->work_tx_end &= ~(1 << txq->index);
918}
919
920static int txq_reclaim(struct tx_queue *txq, int budget, int force)
921{
922 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 923 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 924 int reclaimed;
925
8fd89211 926 __netif_tx_lock(nq, smp_processor_id());
1fa38c58
LB		 927
928 reclaimed = 0;
929 while (reclaimed < budget && txq->tx_desc_count > 0) {
930 int tx_index;
931 struct tx_desc *desc;
932 u32 cmd_sts;
933 struct sk_buff *skb;
1fa38c58
LB		 934
935 tx_index = txq->tx_used_desc;
936 desc = &txq->tx_desc_area[tx_index];
937 cmd_sts = desc->cmd_sts;
938
939 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
940 if (!force)
941 break;
942 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
943 }
944
945 txq->tx_used_desc = tx_index + 1;
946 if (txq->tx_used_desc == txq->tx_ring_size)
947 txq->tx_used_desc = 0;
948
949 reclaimed++;
950 txq->tx_desc_count--;
951
99ab08e0
LB		 952 skb = NULL;
953 if (cmd_sts & TX_LAST_DESC)
954 skb = __skb_dequeue(&txq->tx_skb);
1fa38c58
LB		 955
956 if (cmd_sts & ERROR_SUMMARY) {
957 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
958 mp->dev->stats.tx_errors++;
959 }
960
a418950c 961 if (cmd_sts & TX_FIRST_DESC) {
eb0519b5 962 dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr,
a418950c
LB		 963 desc->byte_cnt, DMA_TO_DEVICE);
964 } else {
eb0519b5 965 dma_unmap_page(mp->dev->dev.parent, desc->buf_ptr,
a418950c
LB		 966 desc->byte_cnt, DMA_TO_DEVICE);
967 }
1fa38c58 968
2bcb4b0f
LB		 969 if (skb != NULL) {
970 if (skb_queue_len(&mp->rx_recycle) <
e7d2f4db 971 mp->rx_ring_size &&
7fd96ce4 972 skb_recycle_check(skb, mp->skb_size))
2bcb4b0f
LB		 973 __skb_queue_head(&mp->rx_recycle, skb);
974 else
975 dev_kfree_skb(skb);
976 }
1fa38c58
LB		 977 }
978
8fd89211
LB		 979 __netif_tx_unlock(nq);
980
1fa38c58
LB		 981 if (reclaimed < budget)
982 mp->work_tx &= ~(1 << txq->index);
983
1fa38c58
LB		 984 return reclaimed;
985}
986
987
89df5fdc
LB		 988/* tx rate control **********************************************************/
989/*
990 * Set total maximum TX rate (shared by all TX queues for this port)
991 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
992 */
993static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
994{
995 int token_rate;
996 int mtu;
997 int bucket_size;
998
999 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
1000 if (token_rate > 1023)
1001 token_rate = 1023;
1002
1003 mtu = (mp->dev->mtu + 255) >> 8;
1004 if (mtu > 63)
1005 mtu = 63;
1006
1007 bucket_size = (burst + 255) >> 8;
1008 if (bucket_size > 65535)
1009 bucket_size = 65535;
1010
457b1d5a
LB		 1011 switch (mp->shared->tx_bw_control) {
1012 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f
LB		 1013 wrlp(mp, TX_BW_RATE, token_rate);
1014 wrlp(mp, TX_BW_MTU, mtu);
1015 wrlp(mp, TX_BW_BURST, bucket_size);
457b1d5a
LB		 1016 break;
1017 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f
LB		 1018 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1019 wrlp(mp, TX_BW_MTU_MOVED, mtu);
1020 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
457b1d5a 1021 break;
1e881592 1022 }
89df5fdc
LB		 1023}
1024
1025static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1026{
1027 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1028 int token_rate;
1029 int bucket_size;
1030
1031 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
1032 if (token_rate > 1023)
1033 token_rate = 1023;
1034
1035 bucket_size = (burst + 255) >> 8;
1036 if (bucket_size > 65535)
1037 bucket_size = 65535;
1038
37a6084f
LB		 1039 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1040 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
89df5fdc
LB		 1041}
1042
1043static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1044{
1045 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1046 int off;
1047 u32 val;
1048
1049 /*
1050 * Turn on fixed priority mode.
1051 */
457b1d5a
LB		 1052 off = 0;
1053 switch (mp->shared->tx_bw_control) {
1054 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f 1055 off = TXQ_FIX_PRIO_CONF;
457b1d5a
LB		 1056 break;
1057 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f 1058 off = TXQ_FIX_PRIO_CONF_MOVED;
457b1d5a
LB		 1059 break;
1060 }
89df5fdc 1061
457b1d5a 1062 if (off) {
37a6084f 1063 val = rdlp(mp, off);
457b1d5a 1064 val |= 1 << txq->index;
37a6084f 1065 wrlp(mp, off, val);
457b1d5a 1066 }
89df5fdc
LB		 1067}
1068
1069static void txq_set_wrr(struct tx_queue *txq, int weight)
1070{
1071 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1072 int off;
1073 u32 val;
1074
1075 /*
1076 * Turn off fixed priority mode.
1077 */
457b1d5a
LB		 1078 off = 0;
1079 switch (mp->shared->tx_bw_control) {
1080 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f 1081 off = TXQ_FIX_PRIO_CONF;
457b1d5a
LB		 1082 break;
1083 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f 1084 off = TXQ_FIX_PRIO_CONF_MOVED;
457b1d5a
LB		 1085 break;
1086 }
89df5fdc 1087
457b1d5a 1088 if (off) {
37a6084f 1089 val = rdlp(mp, off);
457b1d5a 1090 val &= ~(1 << txq->index);
37a6084f 1091 wrlp(mp, off, val);
89df5fdc 1092
457b1d5a
LB		 1093 /*
1094 * Configure WRR weight for this queue.
1095 */
89df5fdc 1096
37a6084f 1097 val = rdlp(mp, off);
457b1d5a 1098 val = (val & ~0xff) | (weight & 0xff);
37a6084f 1099 wrlp(mp, TXQ_BW_WRR_CONF(txq->index), val);
457b1d5a 1100 }
89df5fdc
LB		 1101}
1102
1103
c9df406f 1104/* mii management interface *************************************************/
45c5d3bc
LB		 1105static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1106{
1107 struct mv643xx_eth_shared_private *msp = dev_id;
1108
1109 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1110 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1111 wake_up(&msp->smi_busy_wait);
1112 return IRQ_HANDLED;
1113 }
1114
1115 return IRQ_NONE;
1116}
c9df406f 1117
45c5d3bc 1118static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1da177e4 1119{
45c5d3bc
LB		 1120 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1121}
1da177e4 1122
45c5d3bc
LB		 1123static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1124{
1125 if (msp->err_interrupt == NO_IRQ) {
1126 int i;
c9df406f 1127
45c5d3bc
LB		 1128 for (i = 0; !smi_is_done(msp); i++) {
1129 if (i == 10)
1130 return -ETIMEDOUT;
1131 msleep(10);
c9df406f 1132 }
45c5d3bc
LB		 1133
1134 return 0;
1135 }
1136
ee04448d
LB		 1137 if (!smi_is_done(msp)) {
1138 wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1139 msecs_to_jiffies(100));
1140 if (!smi_is_done(msp))
1141 return -ETIMEDOUT;
1142 }
45c5d3bc
LB		 1143
1144 return 0;
1145}
1146
ed94493f 1147static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
45c5d3bc 1148{
ed94493f 1149 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc
LB		 1150 void __iomem *smi_reg = msp->base + SMI_REG;
1151 int ret;
1152
45c5d3bc 1153 if (smi_wait_ready(msp)) {
10a9948d 1154 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f 1155 return -ETIMEDOUT;
1da177e4
LT		 1156 }
1157
fc32b0e2 1158 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 1159
45c5d3bc 1160 if (smi_wait_ready(msp)) {
10a9948d 1161 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f 1162 return -ETIMEDOUT;
45c5d3bc
LB		 1163 }
1164
1165 ret = readl(smi_reg);
1166 if (!(ret & SMI_READ_VALID)) {
10a9948d 1167 printk(KERN_WARNING "mv643xx_eth: SMI bus read not valid\n");
ed94493f 1168 return -ENODEV;
c9df406f
LB		 1169 }
1170
ed94493f 1171 return ret & 0xffff;
1da177e4
LT		 1172}
1173
ed94493f 1174static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
1da177e4 1175{
ed94493f 1176 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc 1177 void __iomem *smi_reg = msp->base + SMI_REG;
1da177e4 1178
45c5d3bc 1179 if (smi_wait_ready(msp)) {
10a9948d 1180 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
45c5d3bc 1181 return -ETIMEDOUT;
1da177e4
LT		 1182 }
1183
fc32b0e2 1184 writel(SMI_OPCODE_WRITE | (reg << 21) |
ed94493f 1185 (addr << 16) | (val & 0xffff), smi_reg);
45c5d3bc 1186
ed94493f 1187 if (smi_wait_ready(msp)) {
10a9948d 1188 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f
LB		 1189 return -ETIMEDOUT;
1190 }
45c5d3bc
LB		 1191
1192 return 0;
c9df406f 1193}
1da177e4 1194
c9df406f 1195
8fd89211
LB		 1196/* statistics ***************************************************************/
1197static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1198{
1199 struct mv643xx_eth_private *mp = netdev_priv(dev);
1200 struct net_device_stats *stats = &dev->stats;
1201 unsigned long tx_packets = 0;
1202 unsigned long tx_bytes = 0;
1203 unsigned long tx_dropped = 0;
1204 int i;
1205
1206 for (i = 0; i < mp->txq_count; i++) {
1207 struct tx_queue *txq = mp->txq + i;
1208
1209 tx_packets += txq->tx_packets;
1210 tx_bytes += txq->tx_bytes;
1211 tx_dropped += txq->tx_dropped;
1212 }
1213
1214 stats->tx_packets = tx_packets;
1215 stats->tx_bytes = tx_bytes;
1216 stats->tx_dropped = tx_dropped;
1217
1218 return stats;
1219}
1220
eaf5d590
LB		 1221static void mv643xx_eth_grab_lro_stats(struct mv643xx_eth_private *mp)
1222{
1223 u32 lro_aggregated = 0;
1224 u32 lro_flushed = 0;
1225 u32 lro_no_desc = 0;
1226 int i;
1227
eaf5d590
LB		 1228 for (i = 0; i < mp->rxq_count; i++) {
1229 struct rx_queue *rxq = mp->rxq + i;
1230
1231 lro_aggregated += rxq->lro_mgr.stats.aggregated;
1232 lro_flushed += rxq->lro_mgr.stats.flushed;
1233 lro_no_desc += rxq->lro_mgr.stats.no_desc;
1234 }
eaf5d590
LB		 1235
1236 mp->lro_counters.lro_aggregated = lro_aggregated;
1237 mp->lro_counters.lro_flushed = lro_flushed;
1238 mp->lro_counters.lro_no_desc = lro_no_desc;
1239}
1240
fc32b0e2 1241static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 1242{
fc32b0e2 1243 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 1244}
1245
fc32b0e2 1246static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 1247{
fc32b0e2
LB		 1248 int i;
1249
1250 for (i = 0; i < 0x80; i += 4)
1251 mib_read(mp, i);
c9df406f 1252}
d0412d96 1253
fc32b0e2 1254static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 1255{
e5371493 1256 struct mib_counters *p = &mp->mib_counters;
4b8e3655 1257
57e8f26a 1258 spin_lock_bh(&mp->mib_counters_lock);
fc32b0e2 1259 p->good_octets_received += mib_read(mp, 0x00);
fc32b0e2
LB		 1260 p->bad_octets_received += mib_read(mp, 0x08);
1261 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1262 p->good_frames_received += mib_read(mp, 0x10);
1263 p->bad_frames_received += mib_read(mp, 0x14);
1264 p->broadcast_frames_received += mib_read(mp, 0x18);
1265 p->multicast_frames_received += mib_read(mp, 0x1c);
1266 p->frames_64_octets += mib_read(mp, 0x20);
1267 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1268 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1269 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1270 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1271 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1272 p->good_octets_sent += mib_read(mp, 0x38);
fc32b0e2
LB		 1273 p->good_frames_sent += mib_read(mp, 0x40);
1274 p->excessive_collision += mib_read(mp, 0x44);
1275 p->multicast_frames_sent += mib_read(mp, 0x48);
1276 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1277 p->unrec_mac_control_received += mib_read(mp, 0x50);
1278 p->fc_sent += mib_read(mp, 0x54);
1279 p->good_fc_received += mib_read(mp, 0x58);
1280 p->bad_fc_received += mib_read(mp, 0x5c);
1281 p->undersize_received += mib_read(mp, 0x60);
1282 p->fragments_received += mib_read(mp, 0x64);
1283 p->oversize_received += mib_read(mp, 0x68);
1284 p->jabber_received += mib_read(mp, 0x6c);
1285 p->mac_receive_error += mib_read(mp, 0x70);
1286 p->bad_crc_event += mib_read(mp, 0x74);
1287 p->collision += mib_read(mp, 0x78);
1288 p->late_collision += mib_read(mp, 0x7c);
57e8f26a 1289 spin_unlock_bh(&mp->mib_counters_lock);
4ff3495a
LB		 1290
1291 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1292}
1293
1294static void mib_counters_timer_wrapper(unsigned long _mp)
1295{
1296 struct mv643xx_eth_private *mp = (void *)_mp;
1297
1298 mib_counters_update(mp);
d0412d96
JC		 1299}
1300
c9df406f 1301
3e508034
LB		 1302/* interrupt coalescing *****************************************************/
1303/*
1304 * Hardware coalescing parameters are set in units of 64 t_clk
1305 * cycles. I.e.:
1306 *
1307 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1308 *
1309 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1310 *
1311 * In the ->set*() methods, we round the computed register value
1312 * to the nearest integer.
1313 */
1314static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1315{
1316 u32 val = rdlp(mp, SDMA_CONFIG);
1317 u64 temp;
1318
1319 if (mp->shared->extended_rx_coal_limit)
1320 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1321 else
1322 temp = (val & 0x003fff00) >> 8;
1323
1324 temp *= 64000000;
1325 do_div(temp, mp->shared->t_clk);
1326
1327 return (unsigned int)temp;
1328}
1329
1330static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1331{
1332 u64 temp;
1333 u32 val;
1334
1335 temp = (u64)usec * mp->shared->t_clk;
1336 temp += 31999999;
1337 do_div(temp, 64000000);
1338
1339 val = rdlp(mp, SDMA_CONFIG);
1340 if (mp->shared->extended_rx_coal_limit) {
1341 if (temp > 0xffff)
1342 temp = 0xffff;
1343 val &= ~0x023fff80;
1344 val |= (temp & 0x8000) << 10;
1345 val |= (temp & 0x7fff) << 7;
1346 } else {
1347 if (temp > 0x3fff)
1348 temp = 0x3fff;
1349 val &= ~0x003fff00;
1350 val |= (temp & 0x3fff) << 8;
1351 }
1352 wrlp(mp, SDMA_CONFIG, val);
1353}
1354
1355static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1356{
1357 u64 temp;
1358
1359 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1360 temp *= 64000000;
1361 do_div(temp, mp->shared->t_clk);
1362
1363 return (unsigned int)temp;
1364}
1365
1366static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1367{
1368 u64 temp;
1369
1370 temp = (u64)usec * mp->shared->t_clk;
1371 temp += 31999999;
1372 do_div(temp, 64000000);
1373
1374 if (temp > 0x3fff)
1375 temp = 0x3fff;
1376
1377 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1378}
1379
1380
c9df406f 1381/* ethtool ******************************************************************/
e5371493 1382struct mv643xx_eth_stats {
c9df406f
LB		 1383 char stat_string[ETH_GSTRING_LEN];
1384 int sizeof_stat;
16820054
LB		 1385 int netdev_off;
1386 int mp_off;
c9df406f
LB		 1387};
1388
16820054
LB		 1389#define SSTAT(m) \
1390 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1391 offsetof(struct net_device, stats.m), -1 }
1392
1393#define MIBSTAT(m) \
1394 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1395 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1396
eaf5d590
LB		 1397#define LROSTAT(m) \
1398 { #m, FIELD_SIZEOF(struct lro_counters, m), \
1399 -1, offsetof(struct mv643xx_eth_private, lro_counters.m) }
1400
16820054
LB		 1401static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1402 SSTAT(rx_packets),
1403 SSTAT(tx_packets),
1404 SSTAT(rx_bytes),
1405 SSTAT(tx_bytes),
1406 SSTAT(rx_errors),
1407 SSTAT(tx_errors),
1408 SSTAT(rx_dropped),
1409 SSTAT(tx_dropped),
1410 MIBSTAT(good_octets_received),
1411 MIBSTAT(bad_octets_received),
1412 MIBSTAT(internal_mac_transmit_err),
1413 MIBSTAT(good_frames_received),
1414 MIBSTAT(bad_frames_received),
1415 MIBSTAT(broadcast_frames_received),
1416 MIBSTAT(multicast_frames_received),
1417 MIBSTAT(frames_64_octets),
1418 MIBSTAT(frames_65_to_127_octets),
1419 MIBSTAT(frames_128_to_255_octets),
1420 MIBSTAT(frames_256_to_511_octets),
1421 MIBSTAT(frames_512_to_1023_octets),
1422 MIBSTAT(frames_1024_to_max_octets),
1423 MIBSTAT(good_octets_sent),
1424 MIBSTAT(good_frames_sent),
1425 MIBSTAT(excessive_collision),
1426 MIBSTAT(multicast_frames_sent),
1427 MIBSTAT(broadcast_frames_sent),
1428 MIBSTAT(unrec_mac_control_received),
1429 MIBSTAT(fc_sent),
1430 MIBSTAT(good_fc_received),
1431 MIBSTAT(bad_fc_received),
1432 MIBSTAT(undersize_received),
1433 MIBSTAT(fragments_received),
1434 MIBSTAT(oversize_received),
1435 MIBSTAT(jabber_received),
1436 MIBSTAT(mac_receive_error),
1437 MIBSTAT(bad_crc_event),
1438 MIBSTAT(collision),
1439 MIBSTAT(late_collision),
eaf5d590
LB		 1440 LROSTAT(lro_aggregated),
1441 LROSTAT(lro_flushed),
1442 LROSTAT(lro_no_desc),
c9df406f
LB		 1443};
1444
10a9948d 1445static int
6bdf576e
LB		 1446mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1447 struct ethtool_cmd *cmd)
d0412d96 1448{
d0412d96
JC		 1449 int err;
1450
ed94493f
LB		 1451 err = phy_read_status(mp->phy);
1452 if (err == 0)
1453 err = phy_ethtool_gset(mp->phy, cmd);
d0412d96 1454
fc32b0e2
LB		 1455 /*
1456 * The MAC does not support 1000baseT_Half.
1457 */
d0412d96
JC		 1458 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1459 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1460
1461 return err;
1462}
1463
10a9948d 1464static int
6bdf576e 1465mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
10a9948d 1466 struct ethtool_cmd *cmd)
bedfe324 1467{
81600eea
LB		 1468 u32 port_status;
1469
37a6084f 1470 port_status = rdlp(mp, PORT_STATUS);
81600eea 1471
bedfe324
LB		 1472 cmd->supported = SUPPORTED_MII;
1473 cmd->advertising = ADVERTISED_MII;
81600eea
LB		 1474 switch (port_status & PORT_SPEED_MASK) {
1475 case PORT_SPEED_10:
1476 cmd->speed = SPEED_10;
1477 break;
1478 case PORT_SPEED_100:
1479 cmd->speed = SPEED_100;
1480 break;
1481 case PORT_SPEED_1000:
1482 cmd->speed = SPEED_1000;
1483 break;
1484 default:
1485 cmd->speed = -1;
1486 break;
1487 }
1488 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
bedfe324
LB		 1489 cmd->port = PORT_MII;
1490 cmd->phy_address = 0;
1491 cmd->transceiver = XCVR_INTERNAL;
1492 cmd->autoneg = AUTONEG_DISABLE;
1493 cmd->maxtxpkt = 1;
1494 cmd->maxrxpkt = 1;
1495
1496 return 0;
1497}
1498
6bdf576e
LB		 1499static int
1500mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1501{
1502 struct mv643xx_eth_private *mp = netdev_priv(dev);
1503
1504 if (mp->phy != NULL)
1505 return mv643xx_eth_get_settings_phy(mp, cmd);
1506 else
1507 return mv643xx_eth_get_settings_phyless(mp, cmd);
1508}
1509
10a9948d
LB		 1510static int
1511mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1512{
e5371493 1513 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6 1514
6bdf576e
LB		 1515 if (mp->phy == NULL)
1516 return -EINVAL;
1517
fc32b0e2
LB		 1518 /*
1519 * The MAC does not support 1000baseT_Half.
1520 */
1521 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1522
ed94493f 1523 return phy_ethtool_sset(mp->phy, cmd);
c9df406f 1524}
1da177e4 1525
fc32b0e2
LB		 1526static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1527 struct ethtool_drvinfo *drvinfo)
c9df406f 1528{
e5371493
LB		 1529 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1530 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 1531 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 1532 strncpy(drvinfo->bus_info, "platform", 32);
16820054 1533 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1534}
1da177e4 1535
fc32b0e2 1536static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1537{
e5371493 1538 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1539
6bdf576e
LB		 1540 if (mp->phy == NULL)
1541 return -EINVAL;
1da177e4 1542
6bdf576e 1543 return genphy_restart_aneg(mp->phy);
bedfe324
LB		 1544}
1545
c9df406f
LB		 1546static u32 mv643xx_eth_get_link(struct net_device *dev)
1547{
ed94493f 1548 return !!netif_carrier_ok(dev);
bedfe324
LB		 1549}
1550
3e508034
LB		 1551static int
1552mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1553{
1554 struct mv643xx_eth_private *mp = netdev_priv(dev);
1555
1556 ec->rx_coalesce_usecs = get_rx_coal(mp);
1557 ec->tx_coalesce_usecs = get_tx_coal(mp);
1558
1559 return 0;
1560}
1561
1562static int
1563mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1564{
1565 struct mv643xx_eth_private *mp = netdev_priv(dev);
1566
1567 set_rx_coal(mp, ec->rx_coalesce_usecs);
1568 set_tx_coal(mp, ec->tx_coalesce_usecs);
1569
1570 return 0;
1571}
1572
e7d2f4db
LB		 1573static void
1574mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1575{
1576 struct mv643xx_eth_private *mp = netdev_priv(dev);
1577
1578 er->rx_max_pending = 4096;
1579 er->tx_max_pending = 4096;
1580 er->rx_mini_max_pending = 0;
1581 er->rx_jumbo_max_pending = 0;
1582
1583 er->rx_pending = mp->rx_ring_size;
1584 er->tx_pending = mp->tx_ring_size;
1585 er->rx_mini_pending = 0;
1586 er->rx_jumbo_pending = 0;
1587}
1588
1589static int
1590mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1591{
1592 struct mv643xx_eth_private *mp = netdev_priv(dev);
1593
1594 if (er->rx_mini_pending || er->rx_jumbo_pending)
1595 return -EINVAL;
1596
1597 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1598 mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096;
1599
1600 if (netif_running(dev)) {
1601 mv643xx_eth_stop(dev);
1602 if (mv643xx_eth_open(dev)) {
1603 dev_printk(KERN_ERR, &dev->dev,
1604 "fatal error on re-opening device after "
1605 "ring param change\n");
1606 return -ENOMEM;
1607 }
1608 }
1609
1610 return 0;
1611}
1612
d888b373
LB		 1613static u32
1614mv643xx_eth_get_rx_csum(struct net_device *dev)
1615{
1616 struct mv643xx_eth_private *mp = netdev_priv(dev);
1617
1618 return !!(rdlp(mp, PORT_CONFIG) & 0x02000000);
1619}
1620
1621static int
1622mv643xx_eth_set_rx_csum(struct net_device *dev, u32 rx_csum)
1623{
1624 struct mv643xx_eth_private *mp = netdev_priv(dev);
1625
1626 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1627
1628 return 0;
1629}
1630
fc32b0e2
LB		 1631static void mv643xx_eth_get_strings(struct net_device *dev,
1632 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1633{
1634 int i;
1da177e4 1635
fc32b0e2
LB		 1636 if (stringset == ETH_SS_STATS) {
1637 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1638 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1639 mv643xx_eth_stats[i].stat_string,
e5371493 1640 ETH_GSTRING_LEN);
c9df406f 1641 }
c9df406f
LB		 1642 }
1643}
1da177e4 1644
fc32b0e2
LB		 1645static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1646 struct ethtool_stats *stats,
1647 uint64_t *data)
c9df406f 1648{
b9873841 1649 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1650 int i;
1da177e4 1651
8fd89211 1652 mv643xx_eth_get_stats(dev);
fc32b0e2 1653 mib_counters_update(mp);
eaf5d590 1654 mv643xx_eth_grab_lro_stats(mp);
1da177e4 1655
16820054
LB		 1656 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1657 const struct mv643xx_eth_stats *stat;
1658 void *p;
1659
1660 stat = mv643xx_eth_stats + i;
1661
1662 if (stat->netdev_off >= 0)
1663 p = ((void *)mp->dev) + stat->netdev_off;
1664 else
1665 p = ((void *)mp) + stat->mp_off;
1666
1667 data[i] = (stat->sizeof_stat == 8) ?
1668 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1669 }
c9df406f 1670}
1da177e4 1671
fc32b0e2 1672static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1673{
fc32b0e2 1674 if (sset == ETH_SS_STATS)
16820054 1675 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1676
1677 return -EOPNOTSUPP;
c9df406f 1678}
1da177e4 1679
e5371493 1680static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1681 .get_settings = mv643xx_eth_get_settings,
1682 .set_settings = mv643xx_eth_set_settings,
1683 .get_drvinfo = mv643xx_eth_get_drvinfo,
1684 .nway_reset = mv643xx_eth_nway_reset,
1685 .get_link = mv643xx_eth_get_link,
3e508034
LB		 1686 .get_coalesce = mv643xx_eth_get_coalesce,
1687 .set_coalesce = mv643xx_eth_set_coalesce,
e7d2f4db
LB		 1688 .get_ringparam = mv643xx_eth_get_ringparam,
1689 .set_ringparam = mv643xx_eth_set_ringparam,
d888b373
LB		 1690 .get_rx_csum = mv643xx_eth_get_rx_csum,
1691 .set_rx_csum = mv643xx_eth_set_rx_csum,
b8df184f 1692 .set_tx_csum = ethtool_op_set_tx_csum,
c9df406f 1693 .set_sg = ethtool_op_set_sg,
fc32b0e2
LB		 1694 .get_strings = mv643xx_eth_get_strings,
1695 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
eaf5d590
LB		 1696 .get_flags = ethtool_op_get_flags,
1697 .set_flags = ethtool_op_set_flags,
e5371493 1698 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1699};
1da177e4 1700
bea3348e 1701
c9df406f 1702/* address handling *********************************************************/
5daffe94 1703static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1704{
66e63ffb
LB		 1705 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1706 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1da177e4 1707
5daffe94
LB		 1708 addr[0] = (mac_h >> 24) & 0xff;
1709 addr[1] = (mac_h >> 16) & 0xff;
1710 addr[2] = (mac_h >> 8) & 0xff;
1711 addr[3] = mac_h & 0xff;
1712 addr[4] = (mac_l >> 8) & 0xff;
1713 addr[5] = mac_l & 0xff;
c9df406f 1714}
1da177e4 1715
66e63ffb 1716static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1717{
66e63ffb
LB		 1718 wrlp(mp, MAC_ADDR_HIGH,
1719 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1720 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
c9df406f 1721}
d0412d96 1722
66e63ffb 1723static u32 uc_addr_filter_mask(struct net_device *dev)
c9df406f 1724{
ccffad25 1725 struct netdev_hw_addr *ha;
66e63ffb 1726 u32 nibbles;
1da177e4 1727
66e63ffb
LB		 1728 if (dev->flags & IFF_PROMISC)
1729 return 0;
1da177e4 1730
66e63ffb 1731 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
31278e71 1732 list_for_each_entry(ha, &dev->uc.list, list) {
ccffad25 1733 if (memcmp(dev->dev_addr, ha->addr, 5))
66e63ffb 1734 return 0;
ccffad25 1735 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
66e63ffb 1736 return 0;
ff561eef 1737
ccffad25 1738 nibbles |= 1 << (ha->addr[5] & 0x0f);
66e63ffb 1739 }
1da177e4 1740
66e63ffb 1741 return nibbles;
1da177e4
LT		 1742}
1743
66e63ffb 1744static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1da177e4 1745{
e5371493 1746 struct mv643xx_eth_private *mp = netdev_priv(dev);
66e63ffb
LB		 1747 u32 port_config;
1748 u32 nibbles;
1749 int i;
1da177e4 1750
cc9754b3 1751 uc_addr_set(mp, dev->dev_addr);
1da177e4 1752
66e63ffb
LB		 1753 port_config = rdlp(mp, PORT_CONFIG);
1754 nibbles = uc_addr_filter_mask(dev);
1755 if (!nibbles) {
1756 port_config |= UNICAST_PROMISCUOUS_MODE;
1757 wrlp(mp, PORT_CONFIG, port_config);
1758 return;
1759 }
1760
1761 for (i = 0; i < 16; i += 4) {
1762 int off = UNICAST_TABLE(mp->port_num) + i;
1763 u32 v;
1764
1765 v = 0;
1766 if (nibbles & 1)
1767 v |= 0x00000001;
1768 if (nibbles & 2)
1769 v |= 0x00000100;
1770 if (nibbles & 4)
1771 v |= 0x00010000;
1772 if (nibbles & 8)
1773 v |= 0x01000000;
1774 nibbles >>= 4;
1775
1776 wrl(mp, off, v);
1777 }
1778
1779 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1780 wrlp(mp, PORT_CONFIG, port_config);
1da177e4
LT		 1781}
1782
69876569
LB		 1783static int addr_crc(unsigned char *addr)
1784{
1785 int crc = 0;
1786 int i;
1787
1788 for (i = 0; i < 6; i++) {
1789 int j;
1790
1791 crc = (crc ^ addr[i]) << 8;
1792 for (j = 7; j >= 0; j--) {
1793 if (crc & (0x100 << j))
1794 crc ^= 0x107 << j;
1795 }
1796 }
1797
1798 return crc;
1799}
1800
66e63ffb 1801static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1da177e4 1802{
fc32b0e2 1803 struct mv643xx_eth_private *mp = netdev_priv(dev);
66e63ffb
LB		 1804 u32 *mc_spec;
1805 u32 *mc_other;
fc32b0e2
LB		 1806 struct dev_addr_list *addr;
1807 int i;
c8aaea25 1808
fc32b0e2 1809 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
66e63ffb
LB		 1810 int port_num;
1811 u32 accept;
c8aaea25 1812
66e63ffb
LB		 1813oom:
1814 port_num = mp->port_num;
1815 accept = 0x01010101;
fc32b0e2
LB		 1816 for (i = 0; i < 0x100; i += 4) {
1817 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1818 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1819 }
1820 return;
1821 }
c8aaea25 1822
82a5bd6a 1823 mc_spec = kmalloc(0x200, GFP_ATOMIC);
66e63ffb
LB		 1824 if (mc_spec == NULL)
1825 goto oom;
1826 mc_other = mc_spec + (0x100 >> 2);
1827
1828 memset(mc_spec, 0, 0x100);
1829 memset(mc_other, 0, 0x100);
1da177e4 1830
fc32b0e2
LB		 1831 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1832 u8 *a = addr->da_addr;
66e63ffb
LB		 1833 u32 *table;
1834 int entry;
1da177e4 1835
fc32b0e2 1836 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
66e63ffb
LB		 1837 table = mc_spec;
1838 entry = a[5];
fc32b0e2 1839 } else {
66e63ffb
LB		 1840 table = mc_other;
1841 entry = addr_crc(a);
fc32b0e2 1842 }
66e63ffb 1843
2b448334 1844 table[entry >> 2] |= 1 << (8 * (entry & 3));
fc32b0e2 1845 }
66e63ffb
LB		 1846
1847 for (i = 0; i < 0x100; i += 4) {
1848 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1849 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1850 }
1851
1852 kfree(mc_spec);
1853}
1854
1855static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1856{
1857 mv643xx_eth_program_unicast_filter(dev);
1858 mv643xx_eth_program_multicast_filter(dev);
1859}
1860
1861static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1862{
1863 struct sockaddr *sa = addr;
1864
1865 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1866
1867 netif_addr_lock_bh(dev);
1868 mv643xx_eth_program_unicast_filter(dev);
1869 netif_addr_unlock_bh(dev);
1870
1871 return 0;
c9df406f 1872}
c8aaea25 1873
c8aaea25 1874
c9df406f 1875/* rx/tx queue initialisation ***********************************************/
64da80a2 1876static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1877{
64da80a2 1878 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1879 struct rx_desc *rx_desc;
1880 int size;
c9df406f
LB		 1881 int i;
1882
64da80a2
LB		 1883 rxq->index = index;
1884
e7d2f4db 1885 rxq->rx_ring_size = mp->rx_ring_size;
8a578111
LB		 1886
1887 rxq->rx_desc_count = 0;
1888 rxq->rx_curr_desc = 0;
1889 rxq->rx_used_desc = 0;
1890
1891 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1892
f7981c1c 1893 if (index == 0 && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1894 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1895 mp->rx_desc_sram_size);
1896 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1897 } else {
eb0519b5
GP		 1898 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1899 size, &rxq->rx_desc_dma,
1900 GFP_KERNEL);
f7ea3337
PJ		 1901 }
1902
8a578111
LB		 1903 if (rxq->rx_desc_area == NULL) {
1904 dev_printk(KERN_ERR, &mp->dev->dev,
1905 "can't allocate rx ring (%d bytes)\n", size);
1906 goto out;
1907 }
1908 memset(rxq->rx_desc_area, 0, size);
1da177e4 1909
8a578111
LB		 1910 rxq->rx_desc_area_size = size;
1911 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1912 GFP_KERNEL);
1913 if (rxq->rx_skb == NULL) {
1914 dev_printk(KERN_ERR, &mp->dev->dev,
1915 "can't allocate rx skb ring\n");
1916 goto out_free;
1917 }
1918
1919 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1920 for (i = 0; i < rxq->rx_ring_size; i++) {
9da78745
LB		 1921 int nexti;
1922
1923 nexti = i + 1;
1924 if (nexti == rxq->rx_ring_size)
1925 nexti = 0;
1926
8a578111
LB		 1927 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1928 nexti * sizeof(struct rx_desc);
1929 }
1930
eaf5d590
LB		 1931 rxq->lro_mgr.dev = mp->dev;
1932 memset(&rxq->lro_mgr.stats, 0, sizeof(rxq->lro_mgr.stats));
1933 rxq->lro_mgr.features = LRO_F_NAPI;
1934 rxq->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1935 rxq->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1936 rxq->lro_mgr.max_desc = ARRAY_SIZE(rxq->lro_arr);
1937 rxq->lro_mgr.max_aggr = 32;
1938 rxq->lro_mgr.frag_align_pad = 0;
1939 rxq->lro_mgr.lro_arr = rxq->lro_arr;
1940 rxq->lro_mgr.get_skb_header = mv643xx_get_skb_header;
1941
1942 memset(&rxq->lro_arr, 0, sizeof(rxq->lro_arr));
eaf5d590 1943
8a578111
LB		 1944 return 0;
1945
1946
1947out_free:
f7981c1c 1948 if (index == 0 && size <= mp->rx_desc_sram_size)
8a578111
LB		 1949 iounmap(rxq->rx_desc_area);
1950 else
eb0519b5 1951 dma_free_coherent(mp->dev->dev.parent, size,
8a578111
LB		 1952 rxq->rx_desc_area,
1953 rxq->rx_desc_dma);
1954
1955out:
1956 return -ENOMEM;
c9df406f 1957}
c8aaea25 1958
8a578111 1959static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1960{
8a578111
LB		 1961 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1962 int i;
1963
1964 rxq_disable(rxq);
c8aaea25 1965
8a578111
LB		 1966 for (i = 0; i < rxq->rx_ring_size; i++) {
1967 if (rxq->rx_skb[i]) {
1968 dev_kfree_skb(rxq->rx_skb[i]);
1969 rxq->rx_desc_count--;
1da177e4 1970 }
c8aaea25 1971 }
1da177e4 1972
8a578111
LB		 1973 if (rxq->rx_desc_count) {
1974 dev_printk(KERN_ERR, &mp->dev->dev,
1975 "error freeing rx ring -- %d skbs stuck\n",
1976 rxq->rx_desc_count);
1977 }
1978
f7981c1c 1979 if (rxq->index == 0 &&
64da80a2 1980 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1981 iounmap(rxq->rx_desc_area);
c9df406f 1982 else
eb0519b5 1983 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
8a578111
LB		 1984 rxq->rx_desc_area, rxq->rx_desc_dma);
1985
1986 kfree(rxq->rx_skb);
c9df406f 1987}
1da177e4 1988
3d6b35bc 1989static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1990{
3d6b35bc 1991 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1992 struct tx_desc *tx_desc;
1993 int size;
c9df406f 1994 int i;
1da177e4 1995
3d6b35bc
LB		 1996 txq->index = index;
1997
e7d2f4db 1998 txq->tx_ring_size = mp->tx_ring_size;
13d64285
LB		 1999
2000 txq->tx_desc_count = 0;
2001 txq->tx_curr_desc = 0;
2002 txq->tx_used_desc = 0;
2003
2004 size = txq->tx_ring_size * sizeof(struct tx_desc);
2005
f7981c1c 2006 if (index == 0 && size <= mp->tx_desc_sram_size) {
13d64285
LB		 2007 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
2008 mp->tx_desc_sram_size);
2009 txq->tx_desc_dma = mp->tx_desc_sram_addr;
2010 } else {
eb0519b5
GP		 2011 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
2012 size, &txq->tx_desc_dma,
2013 GFP_KERNEL);
13d64285
LB		 2014 }
2015
2016 if (txq->tx_desc_area == NULL) {
2017 dev_printk(KERN_ERR, &mp->dev->dev,
2018 "can't allocate tx ring (%d bytes)\n", size);
99ab08e0 2019 return -ENOMEM;
c9df406f 2020 }
13d64285
LB		 2021 memset(txq->tx_desc_area, 0, size);
2022
2023 txq->tx_desc_area_size = size;
13d64285
LB		 2024
2025 tx_desc = (struct tx_desc *)txq->tx_desc_area;
2026 for (i = 0; i < txq->tx_ring_size; i++) {
6b368f68 2027 struct tx_desc *txd = tx_desc + i;
9da78745
LB		 2028 int nexti;
2029
2030 nexti = i + 1;
2031 if (nexti == txq->tx_ring_size)
2032 nexti = 0;
6b368f68
LB		 2033
2034 txd->cmd_sts = 0;
2035 txd->next_desc_ptr = txq->tx_desc_dma +
13d64285
LB		 2036 nexti * sizeof(struct tx_desc);
2037 }
2038
99ab08e0 2039 skb_queue_head_init(&txq->tx_skb);
c9df406f 2040
99ab08e0 2041 return 0;
c8aaea25 2042}
1da177e4 2043
13d64285 2044static void txq_deinit(struct tx_queue *txq)
c9df406f 2045{
13d64285 2046 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 2047
13d64285 2048 txq_disable(txq);
1fa38c58 2049 txq_reclaim(txq, txq->tx_ring_size, 1);
1da177e4 2050
13d64285 2051 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 2052
f7981c1c 2053 if (txq->index == 0 &&
3d6b35bc 2054 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 2055 iounmap(txq->tx_desc_area);
c9df406f 2056 else
eb0519b5 2057 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
13d64285 2058 txq->tx_desc_area, txq->tx_desc_dma);
c9df406f 2059}
1da177e4 2060
1da177e4 2061
c9df406f 2062/* netdev ops and related ***************************************************/
1fa38c58
LB		 2063static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
2064{
2065 u32 int_cause;
2066 u32 int_cause_ext;
2067
e0ca8410 2068 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
1fa38c58
LB		 2069 if (int_cause == 0)
2070 return 0;
2071
2072 int_cause_ext = 0;
e0ca8410
SB		 2073 if (int_cause & INT_EXT) {
2074 int_cause &= ~INT_EXT;
37a6084f 2075 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
e0ca8410 2076 }
1fa38c58 2077
1fa38c58 2078 if (int_cause) {
37a6084f 2079 wrlp(mp, INT_CAUSE, ~int_cause);
1fa38c58 2080 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
37a6084f 2081 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
1fa38c58
LB		 2082 mp->work_rx |= (int_cause & INT_RX) >> 2;
2083 }
2084
2085 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2086 if (int_cause_ext) {
37a6084f 2087 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
1fa38c58
LB		 2088 if (int_cause_ext & INT_EXT_LINK_PHY)
2089 mp->work_link = 1;
2090 mp->work_tx |= int_cause_ext & INT_EXT_TX;
2091 }
2092
2093 return 1;
2094}
2095
2096static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2097{
2098 struct net_device *dev = (struct net_device *)dev_id;
2099 struct mv643xx_eth_private *mp = netdev_priv(dev);
2100
2101 if (unlikely(!mv643xx_eth_collect_events(mp)))
2102 return IRQ_NONE;
2103
37a6084f 2104 wrlp(mp, INT_MASK, 0);
1fa38c58
LB		 2105 napi_schedule(&mp->napi);
2106
2107 return IRQ_HANDLED;
2108}
2109
2f7eb47a
LB		 2110static void handle_link_event(struct mv643xx_eth_private *mp)
2111{
2112 struct net_device *dev = mp->dev;
2113 u32 port_status;
2114 int speed;
2115 int duplex;
2116 int fc;
2117
37a6084f 2118 port_status = rdlp(mp, PORT_STATUS);
2f7eb47a
LB		 2119 if (!(port_status & LINK_UP)) {
2120 if (netif_carrier_ok(dev)) {
2121 int i;
2122
2123 printk(KERN_INFO "%s: link down\n", dev->name);
2124
2125 netif_carrier_off(dev);
2f7eb47a 2126
f7981c1c 2127 for (i = 0; i < mp->txq_count; i++) {
2f7eb47a
LB		 2128 struct tx_queue *txq = mp->txq + i;
2129
1fa38c58 2130 txq_reclaim(txq, txq->tx_ring_size, 1);
f7981c1c 2131 txq_reset_hw_ptr(txq);
2f7eb47a
LB		 2132 }
2133 }
2134 return;
2135 }
2136
2137 switch (port_status & PORT_SPEED_MASK) {
2138 case PORT_SPEED_10:
2139 speed = 10;
2140 break;
2141 case PORT_SPEED_100:
2142 speed = 100;
2143 break;
2144 case PORT_SPEED_1000:
2145 speed = 1000;
2146 break;
2147 default:
2148 speed = -1;
2149 break;
2150 }
2151 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2152 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2153
2154 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
2155 "flow control %sabled\n", dev->name,
2156 speed, duplex ? "full" : "half",
2157 fc ? "en" : "dis");
2158
4fdeca3f 2159 if (!netif_carrier_ok(dev))
2f7eb47a 2160 netif_carrier_on(dev);
2f7eb47a
LB		 2161}
2162
1fa38c58 2163static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
c9df406f 2164{
1fa38c58
LB		 2165 struct mv643xx_eth_private *mp;
2166 int work_done;
ce4e2e45 2167
1fa38c58 2168 mp = container_of(napi, struct mv643xx_eth_private, napi);
fc32b0e2 2169
1319ebad
LB		 2170 if (unlikely(mp->oom)) {
2171 mp->oom = 0;
2172 del_timer(&mp->rx_oom);
2173 }
1da177e4 2174
1fa38c58
LB		 2175 work_done = 0;
2176 while (work_done < budget) {
2177 u8 queue_mask;
2178 int queue;
2179 int work_tbd;
2180
2181 if (mp->work_link) {
2182 mp->work_link = 0;
2183 handle_link_event(mp);
26ef1f17 2184 work_done++;
1fa38c58
LB		 2185 continue;
2186 }
1da177e4 2187
1319ebad
LB		 2188 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2189 if (likely(!mp->oom))
2190 queue_mask |= mp->work_rx_refill;
2191
1fa38c58
LB		 2192 if (!queue_mask) {
2193 if (mv643xx_eth_collect_events(mp))
2194 continue;
2195 break;
2196 }
1da177e4 2197
1fa38c58
LB		 2198 queue = fls(queue_mask) - 1;
2199 queue_mask = 1 << queue;
2200
2201 work_tbd = budget - work_done;
2202 if (work_tbd > 16)
2203 work_tbd = 16;
2204
2205 if (mp->work_tx_end & queue_mask) {
2206 txq_kick(mp->txq + queue);
2207 } else if (mp->work_tx & queue_mask) {
2208 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2209 txq_maybe_wake(mp->txq + queue);
2210 } else if (mp->work_rx & queue_mask) {
2211 work_done += rxq_process(mp->rxq + queue, work_tbd);
1319ebad 2212 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
1fa38c58
LB		 2213 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2214 } else {
2215 BUG();
2216 }
84dd619e 2217 }
fc32b0e2 2218
1fa38c58 2219 if (work_done < budget) {
1319ebad 2220 if (mp->oom)
1fa38c58
LB		 2221 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2222 napi_complete(napi);
e0ca8410 2223 wrlp(mp, INT_MASK, mp->int_mask);
226bb6b7 2224 }
3d6b35bc 2225
1fa38c58
LB		 2226 return work_done;
2227}
8fa89bf5 2228
1fa38c58
LB		 2229static inline void oom_timer_wrapper(unsigned long data)
2230{
2231 struct mv643xx_eth_private *mp = (void *)data;
1da177e4 2232
1fa38c58 2233 napi_schedule(&mp->napi);
1da177e4
LT		 2234}
2235
e5371493 2236static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 2237{
45c5d3bc
LB		 2238 int data;
2239
ed94493f 2240 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc
LB		 2241 if (data < 0)
2242 return;
1da177e4 2243
7f106c1d 2244 data |= BMCR_RESET;
ed94493f 2245 if (phy_write(mp->phy, MII_BMCR, data) < 0)
45c5d3bc 2246 return;
1da177e4 2247
c9df406f 2248 do {
ed94493f 2249 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc 2250 } while (data >= 0 && data & BMCR_RESET);
1da177e4
LT		 2251}
2252
fc32b0e2 2253static void port_start(struct mv643xx_eth_private *mp)
1da177e4 2254{
d0412d96 2255 u32 pscr;
8a578111 2256 int i;
1da177e4 2257
bedfe324
LB		 2258 /*
2259 * Perform PHY reset, if there is a PHY.
2260 */
ed94493f 2261 if (mp->phy != NULL) {
bedfe324
LB		 2262 struct ethtool_cmd cmd;
2263
2264 mv643xx_eth_get_settings(mp->dev, &cmd);
2265 phy_reset(mp);
2266 mv643xx_eth_set_settings(mp->dev, &cmd);
2267 }
1da177e4 2268
81600eea
LB		 2269 /*
2270 * Configure basic link parameters.
2271 */
37a6084f 2272 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 2273
2274 pscr |= SERIAL_PORT_ENABLE;
37a6084f 2275 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2276
2277 pscr |= DO_NOT_FORCE_LINK_FAIL;
ed94493f 2278 if (mp->phy == NULL)
81600eea 2279 pscr |= FORCE_LINK_PASS;
37a6084f 2280 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea 2281
13d64285
LB		 2282 /*
2283 * Configure TX path and queues.
2284 */
89df5fdc 2285 tx_set_rate(mp, 1000000000, 16777216);
f7981c1c 2286 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc 2287 struct tx_queue *txq = mp->txq + i;
13d64285 2288
6b368f68 2289 txq_reset_hw_ptr(txq);
89df5fdc
LB		 2290 txq_set_rate(txq, 1000000000, 16777216);
2291 txq_set_fixed_prio_mode(txq);
13d64285
LB		 2292 }
2293
d9a073ea
LB		 2294 /*
2295 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
170e7108
LB		 2296 * frames to RX queue #0, and include the pseudo-header when
2297 * calculating receive checksums.
d9a073ea 2298 */
37a6084f 2299 wrlp(mp, PORT_CONFIG, 0x02000000);
01999873 2300
376489a2
LB		 2301 /*
2302 * Treat BPDUs as normal multicasts, and disable partition mode.
2303 */
37a6084f 2304 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
01999873 2305
5a893922
LB		 2306 /*
2307 * Add configured unicast addresses to address filter table.
2308 */
2309 mv643xx_eth_program_unicast_filter(mp->dev);
2310
8a578111 2311 /*
64da80a2 2312 * Enable the receive queues.
8a578111 2313 */
f7981c1c 2314 for (i = 0; i < mp->rxq_count; i++) {
64da80a2 2315 struct rx_queue *rxq = mp->rxq + i;
8a578111 2316 u32 addr;
1da177e4 2317
8a578111
LB		 2318 addr = (u32)rxq->rx_desc_dma;
2319 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
37a6084f 2320 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
1da177e4 2321
8a578111
LB		 2322 rxq_enable(rxq);
2323 }
1da177e4
LT		 2324}
2325
2bcb4b0f
LB		 2326static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2327{
2328 int skb_size;
2329
2330 /*
2331 * Reserve 2+14 bytes for an ethernet header (the hardware
2332 * automatically prepends 2 bytes of dummy data to each
2333 * received packet), 16 bytes for up to four VLAN tags, and
2334 * 4 bytes for the trailing FCS -- 36 bytes total.
2335 */
2336 skb_size = mp->dev->mtu + 36;
2337
2338 /*
2339 * Make sure that the skb size is a multiple of 8 bytes, as
2340 * the lower three bits of the receive descriptor's buffer
2341 * size field are ignored by the hardware.
2342 */
2343 mp->skb_size = (skb_size + 7) & ~7;
7fd96ce4
LB		 2344
2345 /*
2346 * If NET_SKB_PAD is smaller than a cache line,
2347 * netdev_alloc_skb() will cause skb->data to be misaligned
2348 * to a cache line boundary. If this is the case, include
2349 * some extra space to allow re-aligning the data area.
2350 */
2351 mp->skb_size += SKB_DMA_REALIGN;
2bcb4b0f
LB		 2352}
2353
c9df406f 2354static int mv643xx_eth_open(struct net_device *dev)
16e03018 2355{
e5371493 2356 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2357 int err;
64da80a2 2358 int i;
16e03018 2359
37a6084f
LB		 2360 wrlp(mp, INT_CAUSE, 0);
2361 wrlp(mp, INT_CAUSE_EXT, 0);
2362 rdlp(mp, INT_CAUSE_EXT);
c9df406f 2363
fc32b0e2 2364 err = request_irq(dev->irq, mv643xx_eth_irq,
2a1867a7 2365 IRQF_SHARED, dev->name, dev);
c9df406f 2366 if (err) {
fc32b0e2 2367 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
c9df406f 2368 return -EAGAIN;
16e03018
DF		 2369 }
2370
2bcb4b0f
LB		 2371 mv643xx_eth_recalc_skb_size(mp);
2372
2257e05c
LB		 2373 napi_enable(&mp->napi);
2374
2bcb4b0f
LB		 2375 skb_queue_head_init(&mp->rx_recycle);
2376
e0ca8410
SB		 2377 mp->int_mask = INT_EXT;
2378
f7981c1c 2379 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 2380 err = rxq_init(mp, i);
2381 if (err) {
2382 while (--i >= 0)
f7981c1c 2383 rxq_deinit(mp->rxq + i);
64da80a2
LB		 2384 goto out;
2385 }
2386
1fa38c58 2387 rxq_refill(mp->rxq + i, INT_MAX);
e0ca8410 2388 mp->int_mask |= INT_RX_0 << i;
2257e05c
LB		 2389 }
2390
1319ebad 2391 if (mp->oom) {
2257e05c
LB		 2392 mp->rx_oom.expires = jiffies + (HZ / 10);
2393 add_timer(&mp->rx_oom);
64da80a2 2394 }
8a578111 2395
f7981c1c 2396 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc
LB		 2397 err = txq_init(mp, i);
2398 if (err) {
2399 while (--i >= 0)
f7981c1c 2400 txq_deinit(mp->txq + i);
3d6b35bc
LB		 2401 goto out_free;
2402 }
e0ca8410 2403 mp->int_mask |= INT_TX_END_0 << i;
3d6b35bc 2404 }
16e03018 2405
fc32b0e2 2406 port_start(mp);
16e03018 2407
37a6084f 2408 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
e0ca8410 2409 wrlp(mp, INT_MASK, mp->int_mask);
16e03018 2410
c9df406f
LB		 2411 return 0;
2412
13d64285 2413
fc32b0e2 2414out_free:
f7981c1c
LB		 2415 for (i = 0; i < mp->rxq_count; i++)
2416 rxq_deinit(mp->rxq + i);
fc32b0e2 2417out:
c9df406f
LB		 2418 free_irq(dev->irq, dev);
2419
2420 return err;
16e03018
DF		 2421}
2422
e5371493 2423static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 2424{
fc32b0e2 2425 unsigned int data;
64da80a2 2426 int i;
1da177e4 2427
f7981c1c
LB		 2428 for (i = 0; i < mp->rxq_count; i++)
2429 rxq_disable(mp->rxq + i);
2430 for (i = 0; i < mp->txq_count; i++)
2431 txq_disable(mp->txq + i);
ae9ae064
LB		 2432
2433 while (1) {
37a6084f 2434 u32 ps = rdlp(mp, PORT_STATUS);
ae9ae064
LB		 2435
2436 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2437 break;
13d64285 2438 udelay(10);
ae9ae064 2439 }
1da177e4 2440
c9df406f 2441 /* Reset the Enable bit in the Configuration Register */
37a6084f 2442 data = rdlp(mp, PORT_SERIAL_CONTROL);
fc32b0e2
LB		 2443 data &= ~(SERIAL_PORT_ENABLE |
2444 DO_NOT_FORCE_LINK_FAIL |
2445 FORCE_LINK_PASS);
37a6084f 2446 wrlp(mp, PORT_SERIAL_CONTROL, data);
1da177e4
LT		 2447}
2448
c9df406f 2449static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 2450{
e5371493 2451 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 2452 int i;
1da177e4 2453
fe65e704 2454 wrlp(mp, INT_MASK_EXT, 0x00000000);
37a6084f
LB		 2455 wrlp(mp, INT_MASK, 0x00000000);
2456 rdlp(mp, INT_MASK);
1da177e4 2457
c9df406f 2458 napi_disable(&mp->napi);
78fff83b 2459
2257e05c
LB		 2460 del_timer_sync(&mp->rx_oom);
2461
c9df406f 2462 netif_carrier_off(dev);
1da177e4 2463
fc32b0e2
LB		 2464 free_irq(dev->irq, dev);
2465
cc9754b3 2466 port_reset(mp);
8fd89211 2467 mv643xx_eth_get_stats(dev);
fc32b0e2 2468 mib_counters_update(mp);
57e8f26a 2469 del_timer_sync(&mp->mib_counters_timer);
1da177e4 2470
2bcb4b0f
LB		 2471 skb_queue_purge(&mp->rx_recycle);
2472
f7981c1c
LB		 2473 for (i = 0; i < mp->rxq_count; i++)
2474 rxq_deinit(mp->rxq + i);
2475 for (i = 0; i < mp->txq_count; i++)
2476 txq_deinit(mp->txq + i);
1da177e4 2477
c9df406f 2478 return 0;
1da177e4
LT		 2479}
2480
fc32b0e2 2481static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 2482{
e5371493 2483 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2484
ed94493f
LB		 2485 if (mp->phy != NULL)
2486 return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd);
bedfe324
LB		 2487
2488 return -EOPNOTSUPP;
1da177e4
LT		 2489}
2490
c9df406f 2491static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 2492{
89df5fdc
LB		 2493 struct mv643xx_eth_private *mp = netdev_priv(dev);
2494
fc32b0e2 2495 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 2496 return -EINVAL;
1da177e4 2497
c9df406f 2498 dev->mtu = new_mtu;
2bcb4b0f 2499 mv643xx_eth_recalc_skb_size(mp);
89df5fdc
LB		 2500 tx_set_rate(mp, 1000000000, 16777216);
2501
c9df406f
LB		 2502 if (!netif_running(dev))
2503 return 0;
1da177e4 2504
c9df406f
LB		 2505 /*
2506 * Stop and then re-open the interface. This will allocate RX
2507 * skbs of the new MTU.
2508 * There is a possible danger that the open will not succeed,
fc32b0e2 2509 * due to memory being full.
c9df406f
LB		 2510 */
2511 mv643xx_eth_stop(dev);
2512 if (mv643xx_eth_open(dev)) {
fc32b0e2
LB		 2513 dev_printk(KERN_ERR, &dev->dev,
2514 "fatal error on re-opening device after "
2515 "MTU change\n");
c9df406f
LB		 2516 }
2517
2518 return 0;
1da177e4
LT		 2519}
2520
fc32b0e2 2521static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2522{
fc32b0e2 2523 struct mv643xx_eth_private *mp;
1da177e4 2524
fc32b0e2
LB		 2525 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2526 if (netif_running(mp->dev)) {
e5ef1de1 2527 netif_tx_stop_all_queues(mp->dev);
fc32b0e2
LB		 2528 port_reset(mp);
2529 port_start(mp);
e5ef1de1 2530 netif_tx_wake_all_queues(mp->dev);
fc32b0e2 2531 }
c9df406f
LB		 2532}
2533
c9df406f 2534static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2535{
e5371493 2536 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2537
fc32b0e2 2538 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
d0412d96 2539
c9df406f 2540 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2541}
2542
c9df406f 2543#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2544static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2545{
fc32b0e2 2546 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2547
37a6084f
LB		 2548 wrlp(mp, INT_MASK, 0x00000000);
2549 rdlp(mp, INT_MASK);
c9df406f 2550
fc32b0e2 2551 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2552
e0ca8410 2553 wrlp(mp, INT_MASK, mp->int_mask);
9f8dd319 2554}
c9df406f 2555#endif
9f8dd319 2556
9f8dd319 2557
c9df406f 2558/* platform glue ************************************************************/
e5371493
LB		 2559static void
2560mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2561 struct mbus_dram_target_info *dram)
c9df406f 2562{
cc9754b3 2563 void __iomem *base = msp->base;
c9df406f
LB		 2564 u32 win_enable;
2565 u32 win_protect;
2566 int i;
9f8dd319 2567
c9df406f
LB		 2568 for (i = 0; i < 6; i++) {
2569 writel(0, base + WINDOW_BASE(i));
2570 writel(0, base + WINDOW_SIZE(i));
2571 if (i < 4)
2572 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2573 }
2574
c9df406f
LB		 2575 win_enable = 0x3f;
2576 win_protect = 0;
2577
2578 for (i = 0; i < dram->num_cs; i++) {
2579 struct mbus_dram_window *cs = dram->cs + i;
2580
2581 writel((cs->base & 0xffff0000) |
2582 (cs->mbus_attr << 8) |
2583 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2584 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2585
2586 win_enable &= ~(1 << i);
2587 win_protect |= 3 << (2 * i);
2588 }
2589
2590 writel(win_enable, base + WINDOW_BAR_ENABLE);
2591 msp->win_protect = win_protect;
9f8dd319
DF		 2592}
2593
773fc3ee
LB		 2594static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2595{
2596 /*
2597 * Check whether we have a 14-bit coal limit field in bits
2598 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2599 * SDMA config register.
2600 */
37a6084f
LB		 2601 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2602 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
773fc3ee
LB		 2603 msp->extended_rx_coal_limit = 1;
2604 else
2605 msp->extended_rx_coal_limit = 0;
1e881592
LB		 2606
2607 /*
457b1d5a
LB		 2608 * Check whether the MAC supports TX rate control, and if
2609 * yes, whether its associated registers are in the old or
2610 * the new place.
1e881592 2611 */
37a6084f
LB		 2612 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2613 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
457b1d5a
LB		 2614 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2615 } else {
37a6084f
LB		 2616 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2617 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
457b1d5a
LB		 2618 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2619 else
2620 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2621 }
773fc3ee
LB		 2622}
2623
c9df406f 2624static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2625{
10a9948d 2626 static int mv643xx_eth_version_printed;
c9df406f 2627 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2628 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 2629 struct resource *res;
2630 int ret;
9f8dd319 2631
e5371493 2632 if (!mv643xx_eth_version_printed++)
7dde154d
LB		 2633 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2634 "driver version %s\n", mv643xx_eth_driver_version);
9f8dd319 2635
c9df406f
LB		 2636 ret = -EINVAL;
2637 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2638 if (res == NULL)
2639 goto out;
9f8dd319 2640
c9df406f
LB		 2641 ret = -ENOMEM;
2642 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2643 if (msp == NULL)
2644 goto out;
2645 memset(msp, 0, sizeof(*msp));
2646
cc9754b3
LB		 2647 msp->base = ioremap(res->start, res->end - res->start + 1);
2648 if (msp->base == NULL)
c9df406f
LB		 2649 goto out_free;
2650
ed94493f
LB		 2651 /*
2652 * Set up and register SMI bus.
2653 */
2654 if (pd == NULL || pd->shared_smi == NULL) {
298cf9be
LB		 2655 msp->smi_bus = mdiobus_alloc();
2656 if (msp->smi_bus == NULL)
ed94493f 2657 goto out_unmap;
298cf9be
LB		 2658
2659 msp->smi_bus->priv = msp;
2660 msp->smi_bus->name = "mv643xx_eth smi";
2661 msp->smi_bus->read = smi_bus_read;
2662 msp->smi_bus->write = smi_bus_write,
2663 snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
2664 msp->smi_bus->parent = &pdev->dev;
2665 msp->smi_bus->phy_mask = 0xffffffff;
2666 if (mdiobus_register(msp->smi_bus) < 0)
2667 goto out_free_mii_bus;
ed94493f
LB		 2668 msp->smi = msp;
2669 } else {
fc0eb9f2 2670 msp->smi = platform_get_drvdata(pd->shared_smi);
ed94493f 2671 }
c9df406f 2672
45c5d3bc
LB		 2673 msp->err_interrupt = NO_IRQ;
2674 init_waitqueue_head(&msp->smi_busy_wait);
2675
2676 /*
2677 * Check whether the error interrupt is hooked up.
2678 */
2679 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2680 if (res != NULL) {
2681 int err;
2682
2683 err = request_irq(res->start, mv643xx_eth_err_irq,
2684 IRQF_SHARED, "mv643xx_eth", msp);
2685 if (!err) {
2686 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2687 msp->err_interrupt = res->start;
2688 }
2689 }
2690
c9df406f
LB		 2691 /*
2692 * (Re-)program MBUS remapping windows if we are asked to.
2693 */
2694 if (pd != NULL && pd->dram != NULL)
2695 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2696
fc32b0e2
LB		 2697 /*
2698 * Detect hardware parameters.
2699 */
2700 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
773fc3ee 2701 infer_hw_params(msp);
fc32b0e2
LB		 2702
2703 platform_set_drvdata(pdev, msp);
2704
c9df406f
LB		 2705 return 0;
2706
298cf9be
LB		 2707out_free_mii_bus:
2708 mdiobus_free(msp->smi_bus);
ed94493f
LB		 2709out_unmap:
2710 iounmap(msp->base);
c9df406f
LB		 2711out_free:
2712 kfree(msp);
2713out:
2714 return ret;
2715}
2716
2717static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2718{
e5371493 2719 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
ed94493f 2720 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
c9df406f 2721
298cf9be 2722 if (pd == NULL || pd->shared_smi == NULL) {
298cf9be 2723 mdiobus_unregister(msp->smi_bus);
bcb3336c 2724 mdiobus_free(msp->smi_bus);
298cf9be 2725 }
45c5d3bc
LB		 2726 if (msp->err_interrupt != NO_IRQ)
2727 free_irq(msp->err_interrupt, msp);
cc9754b3 2728 iounmap(msp->base);
c9df406f
LB		 2729 kfree(msp);
2730
2731 return 0;
9f8dd319
DF		 2732}
2733
c9df406f 2734static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2735 .probe = mv643xx_eth_shared_probe,
2736 .remove = mv643xx_eth_shared_remove,
c9df406f 2737 .driver = {
fc32b0e2 2738 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2739 .owner = THIS_MODULE,
2740 },
2741};
2742
e5371493 2743static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2744{
c9df406f 2745 int addr_shift = 5 * mp->port_num;
fc32b0e2 2746 u32 data;
1da177e4 2747
fc32b0e2
LB		 2748 data = rdl(mp, PHY_ADDR);
2749 data &= ~(0x1f << addr_shift);
2750 data |= (phy_addr & 0x1f) << addr_shift;
2751 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2752}
2753
e5371493 2754static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2755{
fc32b0e2
LB		 2756 unsigned int data;
2757
2758 data = rdl(mp, PHY_ADDR);
2759
2760 return (data >> (5 * mp->port_num)) & 0x1f;
2761}
2762
2763static void set_params(struct mv643xx_eth_private *mp,
2764 struct mv643xx_eth_platform_data *pd)
2765{
2766 struct net_device *dev = mp->dev;
2767
2768 if (is_valid_ether_addr(pd->mac_addr))
2769 memcpy(dev->dev_addr, pd->mac_addr, 6);
2770 else
2771 uc_addr_get(mp, dev->dev_addr);
2772
e7d2f4db 2773 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
fc32b0e2 2774 if (pd->rx_queue_size)
e7d2f4db 2775 mp->rx_ring_size = pd->rx_queue_size;
fc32b0e2
LB		 2776 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2777 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2778
f7981c1c 2779 mp->rxq_count = pd->rx_queue_count ? : 1;
64da80a2 2780
e7d2f4db 2781 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
fc32b0e2 2782 if (pd->tx_queue_size)
e7d2f4db 2783 mp->tx_ring_size = pd->tx_queue_size;
fc32b0e2
LB		 2784 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2785 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc 2786
f7981c1c 2787 mp->txq_count = pd->tx_queue_count ? : 1;
1da177e4
LT		 2788}
2789
ed94493f
LB		 2790static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2791 int phy_addr)
1da177e4 2792{
298cf9be 2793 struct mii_bus *bus = mp->shared->smi->smi_bus;
ed94493f
LB		 2794 struct phy_device *phydev;
2795 int start;
2796 int num;
2797 int i;
45c5d3bc 2798
ed94493f
LB		 2799 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2800 start = phy_addr_get(mp) & 0x1f;
2801 num = 32;
2802 } else {
2803 start = phy_addr & 0x1f;
2804 num = 1;
2805 }
45c5d3bc 2806
ed94493f
LB		 2807 phydev = NULL;
2808 for (i = 0; i < num; i++) {
2809 int addr = (start + i) & 0x1f;
fc32b0e2 2810
ed94493f
LB		 2811 if (bus->phy_map[addr] == NULL)
2812 mdiobus_scan(bus, addr);
1da177e4 2813
ed94493f
LB		 2814 if (phydev == NULL) {
2815 phydev = bus->phy_map[addr];
2816 if (phydev != NULL)
2817 phy_addr_set(mp, addr);
2818 }
2819 }
1da177e4 2820
ed94493f 2821 return phydev;
1da177e4
LT		 2822}
2823
ed94493f 2824static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
c28a4f89 2825{
ed94493f 2826 struct phy_device *phy = mp->phy;
c28a4f89 2827
fc32b0e2
LB		 2828 phy_reset(mp);
2829
db1d7bf7 2830 phy_attach(mp->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_GMII);
ed94493f
LB		 2831
2832 if (speed == 0) {
2833 phy->autoneg = AUTONEG_ENABLE;
2834 phy->speed = 0;
2835 phy->duplex = 0;
2836 phy->advertising = phy->supported | ADVERTISED_Autoneg;
c9df406f 2837 } else {
ed94493f
LB		 2838 phy->autoneg = AUTONEG_DISABLE;
2839 phy->advertising = 0;
2840 phy->speed = speed;
2841 phy->duplex = duplex;
c9df406f 2842 }
ed94493f 2843 phy_start_aneg(phy);
c28a4f89
JC		 2844}
2845
81600eea
LB		 2846static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2847{
2848 u32 pscr;
2849
37a6084f 2850 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 2851 if (pscr & SERIAL_PORT_ENABLE) {
2852 pscr &= ~SERIAL_PORT_ENABLE;
37a6084f 2853 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2854 }
2855
2856 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
ed94493f 2857 if (mp->phy == NULL) {
81600eea
LB		 2858 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2859 if (speed == SPEED_1000)
2860 pscr |= SET_GMII_SPEED_TO_1000;
2861 else if (speed == SPEED_100)
2862 pscr |= SET_MII_SPEED_TO_100;
2863
2864 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2865
2866 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2867 if (duplex == DUPLEX_FULL)
2868 pscr |= SET_FULL_DUPLEX_MODE;
2869 }
2870
37a6084f 2871 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2872}
2873
ea8a8642
LB		 2874static const struct net_device_ops mv643xx_eth_netdev_ops = {
2875 .ndo_open = mv643xx_eth_open,
2876 .ndo_stop = mv643xx_eth_stop,
2877 .ndo_start_xmit = mv643xx_eth_xmit,
2878 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
2879 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
2880 .ndo_do_ioctl = mv643xx_eth_ioctl,
2881 .ndo_change_mtu = mv643xx_eth_change_mtu,
2882 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
2883 .ndo_get_stats = mv643xx_eth_get_stats,
2884#ifdef CONFIG_NET_POLL_CONTROLLER
2885 .ndo_poll_controller = mv643xx_eth_netpoll,
2886#endif
2887};
2888
c9df406f 2889static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2890{
c9df406f 2891 struct mv643xx_eth_platform_data *pd;
e5371493 2892 struct mv643xx_eth_private *mp;
c9df406f 2893 struct net_device *dev;
c9df406f 2894 struct resource *res;
fc32b0e2 2895 int err;
1da177e4 2896
c9df406f
LB		 2897 pd = pdev->dev.platform_data;
2898 if (pd == NULL) {
fc32b0e2
LB		 2899 dev_printk(KERN_ERR, &pdev->dev,
2900 "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2901 return -ENODEV;
2902 }
1da177e4 2903
c9df406f 2904 if (pd->shared == NULL) {
fc32b0e2
LB		 2905 dev_printk(KERN_ERR, &pdev->dev,
2906 "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2907 return -ENODEV;
2908 }
8f518703 2909
e5ef1de1 2910 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
c9df406f
LB		 2911 if (!dev)
2912 return -ENOMEM;
1da177e4 2913
c9df406f 2914 mp = netdev_priv(dev);
fc32b0e2
LB		 2915 platform_set_drvdata(pdev, mp);
2916
2917 mp->shared = platform_get_drvdata(pd->shared);
37a6084f 2918 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
fc32b0e2
LB		 2919 mp->port_num = pd->port_number;
2920
c9df406f 2921 mp->dev = dev;
78fff83b 2922
fc32b0e2 2923 set_params(mp, pd);
e5ef1de1 2924 dev->real_num_tx_queues = mp->txq_count;
fc32b0e2 2925
ed94493f
LB		 2926 if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2927 mp->phy = phy_scan(mp, pd->phy_addr);
bedfe324 2928
6bdf576e 2929 if (mp->phy != NULL)
ed94493f 2930 phy_init(mp, pd->speed, pd->duplex);
6bdf576e
LB		 2931
2932 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
ed94493f 2933
81600eea 2934 init_pscr(mp, pd->speed, pd->duplex);
fc32b0e2 2935
4ff3495a
LB		 2936
2937 mib_counters_clear(mp);
2938
2939 init_timer(&mp->mib_counters_timer);
2940 mp->mib_counters_timer.data = (unsigned long)mp;
2941 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2942 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2943 add_timer(&mp->mib_counters_timer);
2944
2945 spin_lock_init(&mp->mib_counters_lock);
2946
2947 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2948
2257e05c
LB		 2949 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2950
2951 init_timer(&mp->rx_oom);
2952 mp->rx_oom.data = (unsigned long)mp;
2953 mp->rx_oom.function = oom_timer_wrapper;
2954
fc32b0e2 2955
c9df406f
LB		 2956 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2957 BUG_ON(!res);
2958 dev->irq = res->start;
1da177e4 2959
ea8a8642
LB		 2960 dev->netdev_ops = &mv643xx_eth_netdev_ops;
2961
c9df406f
LB		 2962 dev->watchdog_timeo = 2 * HZ;
2963 dev->base_addr = 0;
1da177e4 2964
c9df406f 2965 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
e32b6617 2966 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4 2967
fc32b0e2 2968 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2969
c9df406f 2970 if (mp->shared->win_protect)
fc32b0e2 2971 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2972
a5fe3616
LB		 2973 netif_carrier_off(dev);
2974
b5e86db4
LB		 2975 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
2976
4fb0a54a 2977 set_rx_coal(mp, 250);
a5fe3616
LB		 2978 set_tx_coal(mp, 0);
2979
c9df406f
LB		 2980 err = register_netdev(dev);
2981 if (err)
2982 goto out;
1da177e4 2983
e174961c
JB		 2984 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %pM\n",
2985 mp->port_num, dev->dev_addr);
1da177e4 2986
13d64285 2987 if (mp->tx_desc_sram_size > 0)
fc32b0e2 2988 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
1da177e4 2989
c9df406f 2990 return 0;
1da177e4 2991
c9df406f
LB		 2992out:
2993 free_netdev(dev);
1da177e4 2994
c9df406f 2995 return err;
1da177e4
LT		 2996}
2997
c9df406f 2998static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2999{
fc32b0e2 3000 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 3001
fc32b0e2 3002 unregister_netdev(mp->dev);
ed94493f
LB		 3003 if (mp->phy != NULL)
3004 phy_detach(mp->phy);
c9df406f 3005 flush_scheduled_work();
fc32b0e2 3006 free_netdev(mp->dev);
c9df406f 3007
c9df406f 3008 platform_set_drvdata(pdev, NULL);
fc32b0e2 3009
c9df406f 3010 return 0;
1da177e4
LT		 3011}
3012
c9df406f 3013static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 3014{
fc32b0e2 3015 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 3016
c9df406f 3017 /* Mask all interrupts on ethernet port */
37a6084f
LB		 3018 wrlp(mp, INT_MASK, 0);
3019 rdlp(mp, INT_MASK);
c9df406f 3020
fc32b0e2
LB		 3021 if (netif_running(mp->dev))
3022 port_reset(mp);
d0412d96
JC		 3023}
3024
c9df406f 3025static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 3026 .probe = mv643xx_eth_probe,
3027 .remove = mv643xx_eth_remove,
3028 .shutdown = mv643xx_eth_shutdown,
c9df406f 3029 .driver = {
fc32b0e2 3030 .name = MV643XX_ETH_NAME,
c9df406f
LB		 3031 .owner = THIS_MODULE,
3032 },
3033};
3034
e5371493 3035static int __init mv643xx_eth_init_module(void)
d0412d96 3036{
c9df406f 3037 int rc;
d0412d96 3038
c9df406f
LB		 3039 rc = platform_driver_register(&mv643xx_eth_shared_driver);
3040 if (!rc) {
3041 rc = platform_driver_register(&mv643xx_eth_driver);
3042 if (rc)
3043 platform_driver_unregister(&mv643xx_eth_shared_driver);
3044 }
fc32b0e2 3045
c9df406f 3046 return rc;
d0412d96 3047}
fc32b0e2 3048module_init(mv643xx_eth_init_module);
d0412d96 3049
e5371493 3050static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 3051{
c9df406f
LB		 3052 platform_driver_unregister(&mv643xx_eth_driver);
3053 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 3054}
e5371493 3055module_exit(mv643xx_eth_cleanup_module);
1da177e4 3056
45675bc6
LB		 3057MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3058 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
c9df406f 3059MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 3060MODULE_LICENSE("GPL");
c9df406f 3061MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 3062MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux kernel - Deliverables
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