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[PATCH] e1000: Fix invalid memory reference
[deliverable/linux.git] / drivers / net / mv643xx_eth.c
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1da177e4
LT		 1/*
2 * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 rabeeh@galileo.co.il
7 *
8 * Copyright (C) 2003 PMC-Sierra, Inc.,
9 * written by Manish Lachwani (lachwani@pmc-sierra.com)
10 *
11 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
12 *
13 * Copyright (C) 2004-2005 MontaVista Software, Inc.
14 * Dale Farnsworth <dale@farnsworth.org>
15 *
16 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
17 * <sjhill@realitydiluted.com>
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version 2
22 * of the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 */
33#include <linux/init.h>
34#include <linux/dma-mapping.h>
35#include <linux/tcp.h>
36#include <linux/udp.h>
37#include <linux/etherdevice.h>
38
39#include <linux/bitops.h>
40#include <linux/delay.h>
41#include <linux/ethtool.h>
d052d1be
RK		 42#include <linux/platform_device.h>
43
1da177e4
LT		 44#include <asm/io.h>
45#include <asm/types.h>
46#include <asm/pgtable.h>
47#include <asm/system.h>
48#include <asm/delay.h>
49#include "mv643xx_eth.h"
50
51/*
52 * The first part is the high level driver of the gigE ethernet ports.
53 */
54
55/* Constants */
56#define VLAN_HLEN 4
57#define FCS_LEN 4
58#define WRAP NET_IP_ALIGN + ETH_HLEN + VLAN_HLEN + FCS_LEN
59#define RX_SKB_SIZE ((dev->mtu + WRAP + 7) & ~0x7)
60
61#define INT_CAUSE_UNMASK_ALL 0x0007ffff
62#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
1da177e4 63#define INT_CAUSE_MASK_ALL 0x00000000
63c9e549 64#define INT_CAUSE_MASK_ALL_EXT 0x00000000
1da177e4
LT		 65#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
66#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
1da177e4
LT		 67
68#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
69#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
70#else
71#define MAX_DESCS_PER_SKB 1
72#endif
73
74#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
75#define PHY_WAIT_MICRO_SECONDS 10
76
77/* Static function declarations */
78static int eth_port_link_is_up(unsigned int eth_port_num);
79static void eth_port_uc_addr_get(struct net_device *dev,
80 unsigned char *MacAddr);
81static int mv643xx_eth_real_open(struct net_device *);
82static int mv643xx_eth_real_stop(struct net_device *);
83static int mv643xx_eth_change_mtu(struct net_device *, int);
84static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *);
85static void eth_port_init_mac_tables(unsigned int eth_port_num);
86#ifdef MV643XX_NAPI
87static int mv643xx_poll(struct net_device *dev, int *budget);
88#endif
89static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
90static int ethernet_phy_detect(unsigned int eth_port_num);
91static struct ethtool_ops mv643xx_ethtool_ops;
92
93static char mv643xx_driver_name[] = "mv643xx_eth";
94static char mv643xx_driver_version[] = "1.0";
95
96static void __iomem *mv643xx_eth_shared_base;
97
98/* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */
a9f6a0dd 99static DEFINE_SPINLOCK(mv643xx_eth_phy_lock);
1da177e4
LT		 100
101static inline u32 mv_read(int offset)
102{
dc074a8a 103 void __iomem *reg_base;
1da177e4
LT		 104
105 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
106
107 return readl(reg_base + offset);
108}
109
110static inline void mv_write(int offset, u32 data)
111{
dc074a8a 112 void __iomem *reg_base;
1da177e4
LT		 113
114 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
115 writel(data, reg_base + offset);
116}
117
118/*
119 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
120 *
121 * Input : pointer to ethernet interface network device structure
122 * new mtu size
123 * Output : 0 upon success, -EINVAL upon failure
124 */
125static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
126{
127 struct mv643xx_private *mp = netdev_priv(dev);
128 unsigned long flags;
129
130 spin_lock_irqsave(&mp->lock, flags);
131
132 if ((new_mtu > 9500) || (new_mtu < 64)) {
133 spin_unlock_irqrestore(&mp->lock, flags);
134 return -EINVAL;
135 }
136
137 dev->mtu = new_mtu;
138 /*
139 * Stop then re-open the interface. This will allocate RX skb's with
140 * the new MTU.
141 * There is a possible danger that the open will not successed, due
142 * to memory is full, which might fail the open function.
143 */
144 if (netif_running(dev)) {
145 if (mv643xx_eth_real_stop(dev))
146 printk(KERN_ERR
147 "%s: Fatal error on stopping device\n",
148 dev->name);
149 if (mv643xx_eth_real_open(dev))
150 printk(KERN_ERR
151 "%s: Fatal error on opening device\n",
152 dev->name);
153 }
154
155 spin_unlock_irqrestore(&mp->lock, flags);
156 return 0;
157}
158
159/*
160 * mv643xx_eth_rx_task
161 *
162 * Fills / refills RX queue on a certain gigabit ethernet port
163 *
164 * Input : pointer to ethernet interface network device structure
165 * Output : N/A
166 */
167static void mv643xx_eth_rx_task(void *data)
168{
169 struct net_device *dev = (struct net_device *)data;
170 struct mv643xx_private *mp = netdev_priv(dev);
171 struct pkt_info pkt_info;
172 struct sk_buff *skb;
173
174 if (test_and_set_bit(0, &mp->rx_task_busy))
175 panic("%s: Error in test_set_bit / clear_bit", dev->name);
176
177 while (mp->rx_ring_skbs < (mp->rx_ring_size - 5)) {
178 skb = dev_alloc_skb(RX_SKB_SIZE);
179 if (!skb)
180 break;
181 mp->rx_ring_skbs++;
182 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
183 pkt_info.byte_cnt = RX_SKB_SIZE;
184 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, RX_SKB_SIZE,
185 DMA_FROM_DEVICE);
186 pkt_info.return_info = skb;
187 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
188 printk(KERN_ERR
189 "%s: Error allocating RX Ring\n", dev->name);
190 break;
191 }
192 skb_reserve(skb, 2);
193 }
194 clear_bit(0, &mp->rx_task_busy);
195 /*
196 * If RX ring is empty of SKB, set a timer to try allocating
197 * again in a later time .
198 */
199 if ((mp->rx_ring_skbs == 0) && (mp->rx_timer_flag == 0)) {
200 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
201 /* After 100mSec */
202 mp->timeout.expires = jiffies + (HZ / 10);
203 add_timer(&mp->timeout);
204 mp->rx_timer_flag = 1;
205 }
206#ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
207 else {
208 /* Return interrupts */
209 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(mp->port_num),
210 INT_CAUSE_UNMASK_ALL);
211 }
212#endif
213}
214
215/*
216 * mv643xx_eth_rx_task_timer_wrapper
217 *
218 * Timer routine to wake up RX queue filling task. This function is
219 * used only in case the RX queue is empty, and all alloc_skb has
220 * failed (due to out of memory event).
221 *
222 * Input : pointer to ethernet interface network device structure
223 * Output : N/A
224 */
225static void mv643xx_eth_rx_task_timer_wrapper(unsigned long data)
226{
227 struct net_device *dev = (struct net_device *)data;
228 struct mv643xx_private *mp = netdev_priv(dev);
229
230 mp->rx_timer_flag = 0;
231 mv643xx_eth_rx_task((void *)data);
232}
233
234/*
235 * mv643xx_eth_update_mac_address
236 *
237 * Update the MAC address of the port in the address table
238 *
239 * Input : pointer to ethernet interface network device structure
240 * Output : N/A
241 */
242static void mv643xx_eth_update_mac_address(struct net_device *dev)
243{
244 struct mv643xx_private *mp = netdev_priv(dev);
245 unsigned int port_num = mp->port_num;
246
247 eth_port_init_mac_tables(port_num);
248 memcpy(mp->port_mac_addr, dev->dev_addr, 6);
249 eth_port_uc_addr_set(port_num, mp->port_mac_addr);
250}
251
252/*
253 * mv643xx_eth_set_rx_mode
254 *
255 * Change from promiscuos to regular rx mode
256 *
257 * Input : pointer to ethernet interface network device structure
258 * Output : N/A
259 */
260static void mv643xx_eth_set_rx_mode(struct net_device *dev)
261{
262 struct mv643xx_private *mp = netdev_priv(dev);
1da177e4 263
1da177e4 264 if (dev->flags & IFF_PROMISC)
7342cd81 265 mp->port_config |= (u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
1da177e4 266 else
7342cd81
DF		 267 mp->port_config &= ~(u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
268
269 mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num), mp->port_config);
1da177e4
LT		 270}
271
272/*
273 * mv643xx_eth_set_mac_address
274 *
275 * Change the interface's mac address.
276 * No special hardware thing should be done because interface is always
277 * put in promiscuous mode.
278 *
279 * Input : pointer to ethernet interface network device structure and
280 * a pointer to the designated entry to be added to the cache.
281 * Output : zero upon success, negative upon failure
282 */
283static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
284{
285 int i;
286
287 for (i = 0; i < 6; i++)
288 /* +2 is for the offset of the HW addr type */
289 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
290 mv643xx_eth_update_mac_address(dev);
291 return 0;
292}
293
294/*
295 * mv643xx_eth_tx_timeout
296 *
297 * Called upon a timeout on transmitting a packet
298 *
299 * Input : pointer to ethernet interface network device structure.
300 * Output : N/A
301 */
302static void mv643xx_eth_tx_timeout(struct net_device *dev)
303{
304 struct mv643xx_private *mp = netdev_priv(dev);
305
306 printk(KERN_INFO "%s: TX timeout ", dev->name);
307
308 /* Do the reset outside of interrupt context */
309 schedule_work(&mp->tx_timeout_task);
310}
311
312/*
313 * mv643xx_eth_tx_timeout_task
314 *
315 * Actual routine to reset the adapter when a timeout on Tx has occurred
316 */
317static void mv643xx_eth_tx_timeout_task(struct net_device *dev)
318{
319 struct mv643xx_private *mp = netdev_priv(dev);
320
321 netif_device_detach(dev);
322 eth_port_reset(mp->port_num);
323 eth_port_start(mp);
324 netif_device_attach(dev);
325}
326
327/*
328 * mv643xx_eth_free_tx_queue
329 *
330 * Input : dev - a pointer to the required interface
331 *
332 * Output : 0 if was able to release skb , nonzero otherwise
333 */
334static int mv643xx_eth_free_tx_queue(struct net_device *dev,
335 unsigned int eth_int_cause_ext)
336{
337 struct mv643xx_private *mp = netdev_priv(dev);
338 struct net_device_stats *stats = &mp->stats;
339 struct pkt_info pkt_info;
340 int released = 1;
341
342 if (!(eth_int_cause_ext & (BIT0 | BIT8)))
343 return released;
344
345 spin_lock(&mp->lock);
346
347 /* Check only queue 0 */
348 while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
349 if (pkt_info.cmd_sts & BIT0) {
350 printk("%s: Error in TX\n", dev->name);
351 stats->tx_errors++;
352 }
353
354 /*
355 * If return_info is different than 0, release the skb.
356 * The case where return_info is not 0 is only in case
357 * when transmitted a scatter/gather packet, where only
358 * last skb releases the whole chain.
359 */
360 if (pkt_info.return_info) {
361 if (skb_shinfo(pkt_info.return_info)->nr_frags)
362 dma_unmap_page(NULL, pkt_info.buf_ptr,
363 pkt_info.byte_cnt,
364 DMA_TO_DEVICE);
365 else
366 dma_unmap_single(NULL, pkt_info.buf_ptr,
367 pkt_info.byte_cnt,
368 DMA_TO_DEVICE);
369
370 dev_kfree_skb_irq(pkt_info.return_info);
371 released = 0;
1da177e4
LT		 372 } else
373 dma_unmap_page(NULL, pkt_info.buf_ptr,
374 pkt_info.byte_cnt, DMA_TO_DEVICE);
375 }
376
377 spin_unlock(&mp->lock);
378
379 return released;
380}
381
382/*
383 * mv643xx_eth_receive
384 *
385 * This function is forward packets that are received from the port's
386 * queues toward kernel core or FastRoute them to another interface.
387 *
388 * Input : dev - a pointer to the required interface
389 * max - maximum number to receive (0 means unlimted)
390 *
391 * Output : number of served packets
392 */
393#ifdef MV643XX_NAPI
394static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
395#else
396static int mv643xx_eth_receive_queue(struct net_device *dev)
397#endif
398{
399 struct mv643xx_private *mp = netdev_priv(dev);
400 struct net_device_stats *stats = &mp->stats;
401 unsigned int received_packets = 0;
402 struct sk_buff *skb;
403 struct pkt_info pkt_info;
404
405#ifdef MV643XX_NAPI
b1dd9ca1 406 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
1da177e4
LT		 407#else
408 while (eth_port_receive(mp, &pkt_info) == ETH_OK) {
409#endif
410 mp->rx_ring_skbs--;
411 received_packets++;
b1dd9ca1 412
1da177e4
LT		 413 /* Update statistics. Note byte count includes 4 byte CRC count */
414 stats->rx_packets++;
415 stats->rx_bytes += pkt_info.byte_cnt;
416 skb = pkt_info.return_info;
417 /*
418 * In case received a packet without first / last bits on OR
419 * the error summary bit is on, the packets needs to be dropeed.
420 */
421 if (((pkt_info.cmd_sts
422 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
423 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
424 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
425 stats->rx_dropped++;
426 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
427 ETH_RX_LAST_DESC)) !=
428 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
429 if (net_ratelimit())
430 printk(KERN_ERR
431 "%s: Received packet spread "
432 "on multiple descriptors\n",
433 dev->name);
434 }
435 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
436 stats->rx_errors++;
437
438 dev_kfree_skb_irq(skb);
439 } else {
440 /*
441 * The -4 is for the CRC in the trailer of the
442 * received packet
443 */
444 skb_put(skb, pkt_info.byte_cnt - 4);
445 skb->dev = dev;
446
447 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
448 skb->ip_summed = CHECKSUM_UNNECESSARY;
449 skb->csum = htons(
450 (pkt_info.cmd_sts & 0x0007fff8) >> 3);
451 }
452 skb->protocol = eth_type_trans(skb, dev);
453#ifdef MV643XX_NAPI
454 netif_receive_skb(skb);
455#else
456 netif_rx(skb);
457#endif
458 }
459 }
460
461 return received_packets;
462}
463
464/*
465 * mv643xx_eth_int_handler
466 *
467 * Main interrupt handler for the gigbit ethernet ports
468 *
469 * Input : irq - irq number (not used)
470 * dev_id - a pointer to the required interface's data structure
471 * regs - not used
472 * Output : N/A
473 */
474
475static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id,
476 struct pt_regs *regs)
477{
478 struct net_device *dev = (struct net_device *)dev_id;
479 struct mv643xx_private *mp = netdev_priv(dev);
480 u32 eth_int_cause, eth_int_cause_ext = 0;
481 unsigned int port_num = mp->port_num;
482
483 /* Read interrupt cause registers */
484 eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) &
485 INT_CAUSE_UNMASK_ALL;
486
487 if (eth_int_cause & BIT1)
488 eth_int_cause_ext = mv_read(
489 MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
490 INT_CAUSE_UNMASK_ALL_EXT;
491
492#ifdef MV643XX_NAPI
493 if (!(eth_int_cause & 0x0007fffd)) {
494 /* Dont ack the Rx interrupt */
495#endif
496 /*
497 * Clear specific ethernet port intrerrupt registers by
498 * acknowleding relevant bits.
499 */
500 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num),
501 ~eth_int_cause);
502 if (eth_int_cause_ext != 0x0)
503 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG
504 (port_num), ~eth_int_cause_ext);
505
506 /* UDP change : We may need this */
507 if ((eth_int_cause_ext & 0x0000ffff) &&
508 (mv643xx_eth_free_tx_queue(dev, eth_int_cause_ext) == 0) &&
509 (mp->tx_ring_size > mp->tx_ring_skbs + MAX_DESCS_PER_SKB))
510 netif_wake_queue(dev);
511#ifdef MV643XX_NAPI
512 } else {
513 if (netif_rx_schedule_prep(dev)) {
514 /* Mask all the interrupts */
515 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0);
516 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG
517 (port_num), 0);
518 __netif_rx_schedule(dev);
519 }
520#else
521 if (eth_int_cause & (BIT2 | BIT11))
522 mv643xx_eth_receive_queue(dev, 0);
523
524 /*
525 * After forwarded received packets to upper layer, add a task
526 * in an interrupts enabled context that refills the RX ring
527 * with skb's.
528 */
529#ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
530 /* Unmask all interrupts on ethernet port */
531 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
532 INT_CAUSE_MASK_ALL);
533 queue_task(&mp->rx_task, &tq_immediate);
534 mark_bh(IMMEDIATE_BH);
535#else
536 mp->rx_task.func(dev);
537#endif
538#endif
539 }
540 /* PHY status changed */
541 if (eth_int_cause_ext & (BIT16 | BIT20)) {
542 if (eth_port_link_is_up(port_num)) {
543 netif_carrier_on(dev);
544 netif_wake_queue(dev);
545 /* Start TX queue */
546 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG
547 (port_num), 1);
548 } else {
549 netif_carrier_off(dev);
550 netif_stop_queue(dev);
551 }
552 }
553
554 /*
555 * If no real interrupt occured, exit.
556 * This can happen when using gigE interrupt coalescing mechanism.
557 */
558 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
559 return IRQ_NONE;
560
561 return IRQ_HANDLED;
562}
563
564#ifdef MV643XX_COAL
565
566/*
567 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
568 *
569 * DESCRIPTION:
570 * This routine sets the RX coalescing interrupt mechanism parameter.
571 * This parameter is a timeout counter, that counts in 64 t_clk
572 * chunks ; that when timeout event occurs a maskable interrupt
573 * occurs.
574 * The parameter is calculated using the tClk of the MV-643xx chip
575 * , and the required delay of the interrupt in usec.
576 *
577 * INPUT:
578 * unsigned int eth_port_num Ethernet port number
579 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
580 * unsigned int delay Delay in usec
581 *
582 * OUTPUT:
583 * Interrupt coalescing mechanism value is set in MV-643xx chip.
584 *
585 * RETURN:
586 * The interrupt coalescing value set in the gigE port.
587 *
588 */
589static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
590 unsigned int t_clk, unsigned int delay)
591{
592 unsigned int coal = ((t_clk / 1000000) * delay) / 64;
593
594 /* Set RX Coalescing mechanism */
595 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num),
596 ((coal & 0x3fff) << 8) |
597 (mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num))
598 & 0xffc000ff));
599
600 return coal;
601}
602#endif
603
604/*
605 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
606 *
607 * DESCRIPTION:
608 * This routine sets the TX coalescing interrupt mechanism parameter.
609 * This parameter is a timeout counter, that counts in 64 t_clk
610 * chunks ; that when timeout event occurs a maskable interrupt
611 * occurs.
612 * The parameter is calculated using the t_cLK frequency of the
613 * MV-643xx chip and the required delay in the interrupt in uSec
614 *
615 * INPUT:
616 * unsigned int eth_port_num Ethernet port number
617 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
618 * unsigned int delay Delay in uSeconds
619 *
620 * OUTPUT:
621 * Interrupt coalescing mechanism value is set in MV-643xx chip.
622 *
623 * RETURN:
624 * The interrupt coalescing value set in the gigE port.
625 *
626 */
627static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num,
628 unsigned int t_clk, unsigned int delay)
629{
630 unsigned int coal;
631 coal = ((t_clk / 1000000) * delay) / 64;
632 /* Set TX Coalescing mechanism */
633 mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num),
634 coal << 4);
635 return coal;
636}
637
638/*
639 * mv643xx_eth_open
640 *
641 * This function is called when openning the network device. The function
642 * should initialize all the hardware, initialize cyclic Rx/Tx
643 * descriptors chain and buffers and allocate an IRQ to the network
644 * device.
645 *
646 * Input : a pointer to the network device structure
647 *
648 * Output : zero of success , nonzero if fails.
649 */
650
651static int mv643xx_eth_open(struct net_device *dev)
652{
653 struct mv643xx_private *mp = netdev_priv(dev);
654 unsigned int port_num = mp->port_num;
655 int err;
656
657 spin_lock_irq(&mp->lock);
658
659 err = request_irq(dev->irq, mv643xx_eth_int_handler,
16b81757 660 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
1da177e4
LT		 661
662 if (err) {
663 printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n",
664 port_num);
665 err = -EAGAIN;
666 goto out;
667 }
668
669 if (mv643xx_eth_real_open(dev)) {
670 printk("%s: Error opening interface\n", dev->name);
671 err = -EBUSY;
672 goto out_free;
673 }
674
675 spin_unlock_irq(&mp->lock);
676
677 return 0;
678
679out_free:
680 free_irq(dev->irq, dev);
681
682out:
683 spin_unlock_irq(&mp->lock);
684
685 return err;
686}
687
688/*
689 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
690 *
691 * DESCRIPTION:
692 * This function prepares a Rx chained list of descriptors and packet
693 * buffers in a form of a ring. The routine must be called after port
694 * initialization routine and before port start routine.
695 * The Ethernet SDMA engine uses CPU bus addresses to access the various
696 * devices in the system (i.e. DRAM). This function uses the ethernet
697 * struct 'virtual to physical' routine (set by the user) to set the ring
698 * with physical addresses.
699 *
700 * INPUT:
701 * struct mv643xx_private *mp Ethernet Port Control srtuct.
702 *
703 * OUTPUT:
704 * The routine updates the Ethernet port control struct with information
705 * regarding the Rx descriptors and buffers.
706 *
707 * RETURN:
708 * None.
709 */
710static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
711{
712 volatile struct eth_rx_desc *p_rx_desc;
713 int rx_desc_num = mp->rx_ring_size;
714 int i;
715
716 /* initialize the next_desc_ptr links in the Rx descriptors ring */
717 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
718 for (i = 0; i < rx_desc_num; i++) {
719 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
720 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
721 }
722
723 /* Save Rx desc pointer to driver struct. */
724 mp->rx_curr_desc_q = 0;
725 mp->rx_used_desc_q = 0;
726
727 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
728
729 /* Add the queue to the list of RX queues of this port */
730 mp->port_rx_queue_command |= 1;
731}
732
733/*
734 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
735 *
736 * DESCRIPTION:
737 * This function prepares a Tx chained list of descriptors and packet
738 * buffers in a form of a ring. The routine must be called after port
739 * initialization routine and before port start routine.
740 * The Ethernet SDMA engine uses CPU bus addresses to access the various
741 * devices in the system (i.e. DRAM). This function uses the ethernet
742 * struct 'virtual to physical' routine (set by the user) to set the ring
743 * with physical addresses.
744 *
745 * INPUT:
746 * struct mv643xx_private *mp Ethernet Port Control srtuct.
747 *
748 * OUTPUT:
749 * The routine updates the Ethernet port control struct with information
750 * regarding the Tx descriptors and buffers.
751 *
752 * RETURN:
753 * None.
754 */
755static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
756{
757 int tx_desc_num = mp->tx_ring_size;
758 struct eth_tx_desc *p_tx_desc;
759 int i;
760
761 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
762 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
763 for (i = 0; i < tx_desc_num; i++) {
764 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
765 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
766 }
767
768 mp->tx_curr_desc_q = 0;
769 mp->tx_used_desc_q = 0;
770#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
771 mp->tx_first_desc_q = 0;
772#endif
773
774 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
775
776 /* Add the queue to the list of Tx queues of this port */
777 mp->port_tx_queue_command |= 1;
778}
779
780/* Helper function for mv643xx_eth_open */
781static int mv643xx_eth_real_open(struct net_device *dev)
782{
783 struct mv643xx_private *mp = netdev_priv(dev);
784 unsigned int port_num = mp->port_num;
785 unsigned int size;
786
787 /* Stop RX Queues */
788 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
789
790 /* Clear the ethernet port interrupts */
791 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
792 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
793
794 /* Unmask RX buffer and TX end interrupt */
795 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
796 INT_CAUSE_UNMASK_ALL);
797
798 /* Unmask phy and link status changes interrupts */
799 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
800 INT_CAUSE_UNMASK_ALL_EXT);
801
802 /* Set the MAC Address */
803 memcpy(mp->port_mac_addr, dev->dev_addr, 6);
804
805 eth_port_init(mp);
806
807 INIT_WORK(&mp->rx_task, (void (*)(void *))mv643xx_eth_rx_task, dev);
808
809 memset(&mp->timeout, 0, sizeof(struct timer_list));
810 mp->timeout.function = mv643xx_eth_rx_task_timer_wrapper;
811 mp->timeout.data = (unsigned long)dev;
812
813 mp->rx_task_busy = 0;
814 mp->rx_timer_flag = 0;
815
816 /* Allocate RX and TX skb rings */
817 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
818 GFP_KERNEL);
819 if (!mp->rx_skb) {
820 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
821 return -ENOMEM;
822 }
823 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
824 GFP_KERNEL);
825 if (!mp->tx_skb) {
826 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
827 kfree(mp->rx_skb);
828 return -ENOMEM;
829 }
830
831 /* Allocate TX ring */
832 mp->tx_ring_skbs = 0;
833 size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
834 mp->tx_desc_area_size = size;
835
836 if (mp->tx_sram_size) {
837 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
838 mp->tx_sram_size);
839 mp->tx_desc_dma = mp->tx_sram_addr;
840 } else
841 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
842 &mp->tx_desc_dma,
843 GFP_KERNEL);
844
845 if (!mp->p_tx_desc_area) {
846 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
847 dev->name, size);
848 kfree(mp->rx_skb);
849 kfree(mp->tx_skb);
850 return -ENOMEM;
851 }
852 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
853 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
854
855 ether_init_tx_desc_ring(mp);
856
857 /* Allocate RX ring */
858 mp->rx_ring_skbs = 0;
859 size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
860 mp->rx_desc_area_size = size;
861
862 if (mp->rx_sram_size) {
863 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
864 mp->rx_sram_size);
865 mp->rx_desc_dma = mp->rx_sram_addr;
866 } else
867 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
868 &mp->rx_desc_dma,
869 GFP_KERNEL);
870
871 if (!mp->p_rx_desc_area) {
872 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
873 dev->name, size);
874 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
875 dev->name);
876 if (mp->rx_sram_size)
877 iounmap(mp->p_rx_desc_area);
878 else
879 dma_free_coherent(NULL, mp->tx_desc_area_size,
880 mp->p_tx_desc_area, mp->tx_desc_dma);
881 kfree(mp->rx_skb);
882 kfree(mp->tx_skb);
883 return -ENOMEM;
884 }
885 memset((void *)mp->p_rx_desc_area, 0, size);
886
887 ether_init_rx_desc_ring(mp);
888
889 mv643xx_eth_rx_task(dev); /* Fill RX ring with skb's */
890
891 eth_port_start(mp);
892
893 /* Interrupt Coalescing */
894
895#ifdef MV643XX_COAL
896 mp->rx_int_coal =
897 eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL);
898#endif
899
900 mp->tx_int_coal =
901 eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL);
902
903 netif_start_queue(dev);
904
905 return 0;
906}
907
908static void mv643xx_eth_free_tx_rings(struct net_device *dev)
909{
910 struct mv643xx_private *mp = netdev_priv(dev);
911 unsigned int port_num = mp->port_num;
912 unsigned int curr;
913
914 /* Stop Tx Queues */
915 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
916
917 /* Free outstanding skb's on TX rings */
918 for (curr = 0; mp->tx_ring_skbs && curr < mp->tx_ring_size; curr++) {
919 if (mp->tx_skb[curr]) {
920 dev_kfree_skb(mp->tx_skb[curr]);
921 mp->tx_ring_skbs--;
922 }
923 }
924 if (mp->tx_ring_skbs)
925 printk("%s: Error on Tx descriptor free - could not free %d"
926 " descriptors\n", dev->name, mp->tx_ring_skbs);
927
928 /* Free TX ring */
929 if (mp->tx_sram_size)
930 iounmap(mp->p_tx_desc_area);
931 else
932 dma_free_coherent(NULL, mp->tx_desc_area_size,
933 mp->p_tx_desc_area, mp->tx_desc_dma);
934}
935
936static void mv643xx_eth_free_rx_rings(struct net_device *dev)
937{
938 struct mv643xx_private *mp = netdev_priv(dev);
939 unsigned int port_num = mp->port_num;
940 int curr;
941
942 /* Stop RX Queues */
943 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
944
945 /* Free preallocated skb's on RX rings */
946 for (curr = 0; mp->rx_ring_skbs && curr < mp->rx_ring_size; curr++) {
947 if (mp->rx_skb[curr]) {
948 dev_kfree_skb(mp->rx_skb[curr]);
949 mp->rx_ring_skbs--;
950 }
951 }
952
953 if (mp->rx_ring_skbs)
954 printk(KERN_ERR
955 "%s: Error in freeing Rx Ring. %d skb's still"
956 " stuck in RX Ring - ignoring them\n", dev->name,
957 mp->rx_ring_skbs);
958 /* Free RX ring */
959 if (mp->rx_sram_size)
960 iounmap(mp->p_rx_desc_area);
961 else
962 dma_free_coherent(NULL, mp->rx_desc_area_size,
963 mp->p_rx_desc_area, mp->rx_desc_dma);
964}
965
966/*
967 * mv643xx_eth_stop
968 *
969 * This function is used when closing the network device.
970 * It updates the hardware,
971 * release all memory that holds buffers and descriptors and release the IRQ.
972 * Input : a pointer to the device structure
973 * Output : zero if success , nonzero if fails
974 */
975
976/* Helper function for mv643xx_eth_stop */
977
978static int mv643xx_eth_real_stop(struct net_device *dev)
979{
980 struct mv643xx_private *mp = netdev_priv(dev);
981 unsigned int port_num = mp->port_num;
982
983 netif_carrier_off(dev);
984 netif_stop_queue(dev);
985
986 mv643xx_eth_free_tx_rings(dev);
987 mv643xx_eth_free_rx_rings(dev);
988
989 eth_port_reset(mp->port_num);
990
991 /* Disable ethernet port interrupts */
992 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
993 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
994
995 /* Mask RX buffer and TX end interrupt */
996 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0);
997
998 /* Mask phy and link status changes interrupts */
999 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num), 0);
1000
1001 return 0;
1002}
1003
1004static int mv643xx_eth_stop(struct net_device *dev)
1005{
1006 struct mv643xx_private *mp = netdev_priv(dev);
1007
1008 spin_lock_irq(&mp->lock);
1009
1010 mv643xx_eth_real_stop(dev);
1011
1012 free_irq(dev->irq, dev);
1013 spin_unlock_irq(&mp->lock);
1014
1015 return 0;
1016}
1017
1018#ifdef MV643XX_NAPI
1019static void mv643xx_tx(struct net_device *dev)
1020{
1021 struct mv643xx_private *mp = netdev_priv(dev);
1022 struct pkt_info pkt_info;
1023
1024 while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
1025 if (pkt_info.return_info) {
1026 if (skb_shinfo(pkt_info.return_info)->nr_frags)
1027 dma_unmap_page(NULL, pkt_info.buf_ptr,
1028 pkt_info.byte_cnt,
1029 DMA_TO_DEVICE);
1030 else
1031 dma_unmap_single(NULL, pkt_info.buf_ptr,
1032 pkt_info.byte_cnt,
1033 DMA_TO_DEVICE);
1034
1035 dev_kfree_skb_irq(pkt_info.return_info);
1da177e4
LT		 1036 } else
1037 dma_unmap_page(NULL, pkt_info.buf_ptr,
1038 pkt_info.byte_cnt, DMA_TO_DEVICE);
1039 }
1040
1041 if (netif_queue_stopped(dev) &&
1042 mp->tx_ring_size > mp->tx_ring_skbs + MAX_DESCS_PER_SKB)
1043 netif_wake_queue(dev);
1044}
1045
1046/*
1047 * mv643xx_poll
1048 *
1049 * This function is used in case of NAPI
1050 */
1051static int mv643xx_poll(struct net_device *dev, int *budget)
1052{
1053 struct mv643xx_private *mp = netdev_priv(dev);
1054 int done = 1, orig_budget, work_done;
1055 unsigned int port_num = mp->port_num;
1056 unsigned long flags;
1057
1058#ifdef MV643XX_TX_FAST_REFILL
1059 if (++mp->tx_clean_threshold > 5) {
1060 spin_lock_irqsave(&mp->lock, flags);
1061 mv643xx_tx(dev);
1062 mp->tx_clean_threshold = 0;
1063 spin_unlock_irqrestore(&mp->lock, flags);
1064 }
1065#endif
1066
1067 if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
1068 != (u32) mp->rx_used_desc_q) {
1069 orig_budget = *budget;
1070 if (orig_budget > dev->quota)
1071 orig_budget = dev->quota;
1072 work_done = mv643xx_eth_receive_queue(dev, orig_budget);
1073 mp->rx_task.func(dev);
1074 *budget -= work_done;
1075 dev->quota -= work_done;
1076 if (work_done >= orig_budget)
1077 done = 0;
1078 }
1079
1080 if (done) {
1081 spin_lock_irqsave(&mp->lock, flags);
1082 __netif_rx_complete(dev);
1083 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
1084 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1085 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1086 INT_CAUSE_UNMASK_ALL);
1087 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
1088 INT_CAUSE_UNMASK_ALL_EXT);
1089 spin_unlock_irqrestore(&mp->lock, flags);
1090 }
1091
1092 return done ? 0 : 1;
1093}
1094#endif
1095
1096/*
1097 * mv643xx_eth_start_xmit
1098 *
1099 * This function is queues a packet in the Tx descriptor for
1100 * required port.
1101 *
1102 * Input : skb - a pointer to socket buffer
1103 * dev - a pointer to the required port
1104 *
1105 * Output : zero upon success
1106 */
1107static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1108{
1109 struct mv643xx_private *mp = netdev_priv(dev);
1110 struct net_device_stats *stats = &mp->stats;
1111 ETH_FUNC_RET_STATUS status;
1112 unsigned long flags;
1113 struct pkt_info pkt_info;
1114
1115 if (netif_queue_stopped(dev)) {
1116 printk(KERN_ERR
1117 "%s: Tried sending packet when interface is stopped\n",
1118 dev->name);
1119 return 1;
1120 }
1121
1122 /* This is a hard error, log it. */
1123 if ((mp->tx_ring_size - mp->tx_ring_skbs) <=
1124 (skb_shinfo(skb)->nr_frags + 1)) {
1125 netif_stop_queue(dev);
1126 printk(KERN_ERR
1127 "%s: Bug in mv643xx_eth - Trying to transmit when"
1128 " queue full !\n", dev->name);
1129 return 1;
1130 }
1131
1132 /* Paranoid check - this shouldn't happen */
1133 if (skb == NULL) {
1134 stats->tx_dropped++;
1135 printk(KERN_ERR "mv64320_eth paranoid check failed\n");
1136 return 1;
1137 }
1138
1139 spin_lock_irqsave(&mp->lock, flags);
1140
1141 /* Update packet info data structure -- DMA owned, first last */
1142#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1143 if (!skb_shinfo(skb)->nr_frags) {
1144linear:
1145 if (skb->ip_summed != CHECKSUM_HW) {
26006360 1146 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1da177e4 1147 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
26006360
DF		 1148 ETH_TX_FIRST_DESC |
1149 ETH_TX_LAST_DESC |
1150 5 << ETH_TX_IHL_SHIFT;
1da177e4
LT		 1151 pkt_info.l4i_chk = 0;
1152 } else {
1da177e4
LT		 1153
1154 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
26006360
DF		 1155 ETH_TX_FIRST_DESC |
1156 ETH_TX_LAST_DESC |
1157 ETH_GEN_TCP_UDP_CHECKSUM |
1158 ETH_GEN_IP_V_4_CHECKSUM |
1159 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
1da177e4
LT		 1160 /* CPU already calculated pseudo header checksum. */
1161 if (skb->nh.iph->protocol == IPPROTO_UDP) {
1162 pkt_info.cmd_sts |= ETH_UDP_FRAME;
1163 pkt_info.l4i_chk = skb->h.uh->check;
1164 } else if (skb->nh.iph->protocol == IPPROTO_TCP)
1165 pkt_info.l4i_chk = skb->h.th->check;
1166 else {
1167 printk(KERN_ERR
1168 "%s: chksum proto != TCP or UDP\n",
1169 dev->name);
1170 spin_unlock_irqrestore(&mp->lock, flags);
1171 return 1;
1172 }
1173 }
1174 pkt_info.byte_cnt = skb->len;
1175 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len,
1176 DMA_TO_DEVICE);
1177 pkt_info.return_info = skb;
1da177e4
LT		 1178 status = eth_port_send(mp, &pkt_info);
1179 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL))
1180 printk(KERN_ERR "%s: Error on transmitting packet\n",
1181 dev->name);
1182 stats->tx_bytes += pkt_info.byte_cnt;
1183 } else {
1184 unsigned int frag;
1da177e4
LT		 1185
1186 /* Since hardware can't handle unaligned fragments smaller
1187 * than 9 bytes, if we find any, we linearize the skb
1188 * and start again. When I've seen it, it's always been
1189 * the first frag (probably near the end of the page),
1190 * but we check all frags to be safe.
1191 */
1192 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1193 skb_frag_t *fragp;
1194
1195 fragp = &skb_shinfo(skb)->frags[frag];
1196 if (fragp->size <= 8 && fragp->page_offset & 0x7) {
1197 skb_linearize(skb, GFP_ATOMIC);
1198 printk(KERN_DEBUG "%s: unaligned tiny fragment"
1199 "%d of %d, fixed\n",
1200 dev->name, frag,
1201 skb_shinfo(skb)->nr_frags);
1202 goto linear;
1203 }
1204 }
1205
1206 /* first frag which is skb header */
1207 pkt_info.byte_cnt = skb_headlen(skb);
1208 pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
1209 skb_headlen(skb),
1210 DMA_TO_DEVICE);
1211 pkt_info.l4i_chk = 0;
1212 pkt_info.return_info = 0;
1da177e4 1213
26006360
DF		 1214 if (skb->ip_summed != CHECKSUM_HW)
1215 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1216 pkt_info.cmd_sts = ETH_TX_FIRST_DESC |
1217 5 << ETH_TX_IHL_SHIFT;
1218 else {
1219 pkt_info.cmd_sts = ETH_TX_FIRST_DESC |
1220 ETH_GEN_TCP_UDP_CHECKSUM |
1221 ETH_GEN_IP_V_4_CHECKSUM |
1222 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
1da177e4
LT		 1223 /* CPU already calculated pseudo header checksum. */
1224 if (skb->nh.iph->protocol == IPPROTO_UDP) {
1225 pkt_info.cmd_sts |= ETH_UDP_FRAME;
1226 pkt_info.l4i_chk = skb->h.uh->check;
1227 } else if (skb->nh.iph->protocol == IPPROTO_TCP)
1228 pkt_info.l4i_chk = skb->h.th->check;
1229 else {
1230 printk(KERN_ERR
1231 "%s: chksum proto != TCP or UDP\n",
1232 dev->name);
1233 spin_unlock_irqrestore(&mp->lock, flags);
1234 return 1;
1235 }
1236 }
1237
1238 status = eth_port_send(mp, &pkt_info);
1239 if (status != ETH_OK) {
1240 if ((status == ETH_ERROR))
1241 printk(KERN_ERR
1242 "%s: Error on transmitting packet\n",
1243 dev->name);
1244 if (status == ETH_QUEUE_FULL)
1245 printk("Error on Queue Full \n");
1246 if (status == ETH_QUEUE_LAST_RESOURCE)
1247 printk("Tx resource error \n");
1248 }
1249 stats->tx_bytes += pkt_info.byte_cnt;
1250
1251 /* Check for the remaining frags */
1252 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1253 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1254 pkt_info.l4i_chk = 0x0000;
1255 pkt_info.cmd_sts = 0x00000000;
1256
1257 /* Last Frag enables interrupt and frees the skb */
1258 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
1259 pkt_info.cmd_sts |= ETH_TX_ENABLE_INTERRUPT |
1260 ETH_TX_LAST_DESC;
1261 pkt_info.return_info = skb;
1da177e4
LT		 1262 } else {
1263 pkt_info.return_info = 0;
1264 }
1265 pkt_info.l4i_chk = 0;
1266 pkt_info.byte_cnt = this_frag->size;
1267
1268 pkt_info.buf_ptr = dma_map_page(NULL, this_frag->page,
1269 this_frag->page_offset,
1270 this_frag->size,
1271 DMA_TO_DEVICE);
1272
1273 status = eth_port_send(mp, &pkt_info);
1274
1275 if (status != ETH_OK) {
1276 if ((status == ETH_ERROR))
1277 printk(KERN_ERR "%s: Error on "
1278 "transmitting packet\n",
1279 dev->name);
1280
1281 if (status == ETH_QUEUE_LAST_RESOURCE)
1282 printk("Tx resource error \n");
1283
1284 if (status == ETH_QUEUE_FULL)
1285 printk("Queue is full \n");
1286 }
1287 stats->tx_bytes += pkt_info.byte_cnt;
1288 }
1289 }
1290#else
1291 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT | ETH_TX_FIRST_DESC |
1292 ETH_TX_LAST_DESC;
1293 pkt_info.l4i_chk = 0;
1294 pkt_info.byte_cnt = skb->len;
1295 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len,
1296 DMA_TO_DEVICE);
1297 pkt_info.return_info = skb;
1da177e4
LT		 1298 status = eth_port_send(mp, &pkt_info);
1299 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL))
1300 printk(KERN_ERR "%s: Error on transmitting packet\n",
1301 dev->name);
1302 stats->tx_bytes += pkt_info.byte_cnt;
1303#endif
1304
1305 /* Check if TX queue can handle another skb. If not, then
1306 * signal higher layers to stop requesting TX
1307 */
1308 if (mp->tx_ring_size <= (mp->tx_ring_skbs + MAX_DESCS_PER_SKB))
1309 /*
1310 * Stop getting skb's from upper layers.
1311 * Getting skb's from upper layers will be enabled again after
1312 * packets are released.
1313 */
1314 netif_stop_queue(dev);
1315
1316 /* Update statistics and start of transmittion time */
1317 stats->tx_packets++;
1318 dev->trans_start = jiffies;
1319
1320 spin_unlock_irqrestore(&mp->lock, flags);
1321
1322 return 0; /* success */
1323}
1324
1325/*
1326 * mv643xx_eth_get_stats
1327 *
1328 * Returns a pointer to the interface statistics.
1329 *
1330 * Input : dev - a pointer to the required interface
1331 *
1332 * Output : a pointer to the interface's statistics
1333 */
1334
1335static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1336{
1337 struct mv643xx_private *mp = netdev_priv(dev);
1338
1339 return &mp->stats;
1340}
1341
63c9e549
DF		 1342#ifdef CONFIG_NET_POLL_CONTROLLER
1343static inline void mv643xx_enable_irq(struct mv643xx_private *mp)
1344{
1345 int port_num = mp->port_num;
1346 unsigned long flags;
1347
1348 spin_lock_irqsave(&mp->lock, flags);
1349 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1350 INT_CAUSE_UNMASK_ALL);
1351 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
1352 INT_CAUSE_UNMASK_ALL_EXT);
1353 spin_unlock_irqrestore(&mp->lock, flags);
1354}
1355
1356static inline void mv643xx_disable_irq(struct mv643xx_private *mp)
1357{
1358 int port_num = mp->port_num;
1359 unsigned long flags;
1360
1361 spin_lock_irqsave(&mp->lock, flags);
1362 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1363 INT_CAUSE_MASK_ALL);
1364 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
1365 INT_CAUSE_MASK_ALL_EXT);
1366 spin_unlock_irqrestore(&mp->lock, flags);
1367}
1368
1369static void mv643xx_netpoll(struct net_device *netdev)
1370{
1371 struct mv643xx_private *mp = netdev_priv(netdev);
1372
1373 mv643xx_disable_irq(mp);
1374 mv643xx_eth_int_handler(netdev->irq, netdev, NULL);
1375 mv643xx_enable_irq(mp);
1376}
1377#endif
1378
1da177e4
LT		 1379/*/
1380 * mv643xx_eth_probe
1381 *
1382 * First function called after registering the network device.
1383 * It's purpose is to initialize the device as an ethernet device,
1384 * fill the ethernet device structure with pointers * to functions,
1385 * and set the MAC address of the interface
1386 *
1387 * Input : struct device *
1388 * Output : -ENOMEM if failed , 0 if success
1389 */
3ae5eaec 1390static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 1391{
1da177e4
LT		 1392 struct mv643xx_eth_platform_data *pd;
1393 int port_num = pdev->id;
1394 struct mv643xx_private *mp;
1395 struct net_device *dev;
1396 u8 *p;
1397 struct resource *res;
1398 int err;
1399
1400 dev = alloc_etherdev(sizeof(struct mv643xx_private));
1401 if (!dev)
1402 return -ENOMEM;
1403
3ae5eaec 1404 platform_set_drvdata(pdev, dev);
1da177e4
LT		 1405
1406 mp = netdev_priv(dev);
1407
1408 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1409 BUG_ON(!res);
1410 dev->irq = res->start;
1411
1412 mp->port_num = port_num;
1413
1414 dev->open = mv643xx_eth_open;
1415 dev->stop = mv643xx_eth_stop;
1416 dev->hard_start_xmit = mv643xx_eth_start_xmit;
1417 dev->get_stats = mv643xx_eth_get_stats;
1418 dev->set_mac_address = mv643xx_eth_set_mac_address;
1419 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
1420
1421 /* No need to Tx Timeout */
1422 dev->tx_timeout = mv643xx_eth_tx_timeout;
1423#ifdef MV643XX_NAPI
1424 dev->poll = mv643xx_poll;
1425 dev->weight = 64;
1426#endif
1427
63c9e549
DF		 1428#ifdef CONFIG_NET_POLL_CONTROLLER
1429 dev->poll_controller = mv643xx_netpoll;
1430#endif
1431
1da177e4
LT		 1432 dev->watchdog_timeo = 2 * HZ;
1433 dev->tx_queue_len = mp->tx_ring_size;
1434 dev->base_addr = 0;
1435 dev->change_mtu = mv643xx_eth_change_mtu;
1436 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
1437
1438#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1439#ifdef MAX_SKB_FRAGS
1440 /*
1441 * Zero copy can only work if we use Discovery II memory. Else, we will
1442 * have to map the buffers to ISA memory which is only 16 MB
1443 */
1444 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_HW_CSUM;
1445#endif
1446#endif
1447
1448 /* Configure the timeout task */
1449 INIT_WORK(&mp->tx_timeout_task,
1450 (void (*)(void *))mv643xx_eth_tx_timeout_task, dev);
1451
1452 spin_lock_init(&mp->lock);
1453
1454 /* set default config values */
1455 eth_port_uc_addr_get(dev, dev->dev_addr);
1456 mp->port_config = MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE;
1457 mp->port_config_extend = MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE;
1458 mp->port_sdma_config = MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE;
1459 mp->port_serial_control = MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE;
1460 mp->rx_ring_size = MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
1461 mp->tx_ring_size = MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
1462
1463 pd = pdev->dev.platform_data;
1464 if (pd) {
1465 if (pd->mac_addr != NULL)
1466 memcpy(dev->dev_addr, pd->mac_addr, 6);
1467
1468 if (pd->phy_addr || pd->force_phy_addr)
1469 ethernet_phy_set(port_num, pd->phy_addr);
1470
1471 if (pd->port_config || pd->force_port_config)
1472 mp->port_config = pd->port_config;
1473
1474 if (pd->port_config_extend || pd->force_port_config_extend)
1475 mp->port_config_extend = pd->port_config_extend;
1476
1477 if (pd->port_sdma_config || pd->force_port_sdma_config)
1478 mp->port_sdma_config = pd->port_sdma_config;
1479
1480 if (pd->port_serial_control || pd->force_port_serial_control)
1481 mp->port_serial_control = pd->port_serial_control;
1482
1483 if (pd->rx_queue_size)
1484 mp->rx_ring_size = pd->rx_queue_size;
1485
1486 if (pd->tx_queue_size)
1487 mp->tx_ring_size = pd->tx_queue_size;
1488
1489 if (pd->tx_sram_size) {
1490 mp->tx_sram_size = pd->tx_sram_size;
1491 mp->tx_sram_addr = pd->tx_sram_addr;
1492 }
1493
1494 if (pd->rx_sram_size) {
1495 mp->rx_sram_size = pd->rx_sram_size;
1496 mp->rx_sram_addr = pd->rx_sram_addr;
1497 }
1498 }
1499
1500 err = ethernet_phy_detect(port_num);
1501 if (err) {
1502 pr_debug("MV643xx ethernet port %d: "
1503 "No PHY detected at addr %d\n",
1504 port_num, ethernet_phy_get(port_num));
1505 return err;
1506 }
1507
1508 err = register_netdev(dev);
1509 if (err)
1510 goto out;
1511
1512 p = dev->dev_addr;
1513 printk(KERN_NOTICE
1514 "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
1515 dev->name, port_num, p[0], p[1], p[2], p[3], p[4], p[5]);
1516
1517 if (dev->features & NETIF_F_SG)
1518 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
1519
1520 if (dev->features & NETIF_F_IP_CSUM)
1521 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
1522 dev->name);
1523
1524#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1525 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
1526#endif
1527
1528#ifdef MV643XX_COAL
1529 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
1530 dev->name);
1531#endif
1532
1533#ifdef MV643XX_NAPI
1534 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
1535#endif
1536
b1529871
ND		 1537 if (mp->tx_sram_size > 0)
1538 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
1539
1da177e4
LT		 1540 return 0;
1541
1542out:
1543 free_netdev(dev);
1544
1545 return err;
1546}
1547
3ae5eaec 1548static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 1549{
3ae5eaec 1550 struct net_device *dev = platform_get_drvdata(pdev);
1da177e4
LT		 1551
1552 unregister_netdev(dev);
1553 flush_scheduled_work();
1554
1555 free_netdev(dev);
3ae5eaec 1556 platform_set_drvdata(pdev, NULL);
1da177e4
LT		 1557 return 0;
1558}
1559
3ae5eaec 1560static int mv643xx_eth_shared_probe(struct platform_device *pdev)
1da177e4 1561{
1da177e4
LT		 1562 struct resource *res;
1563
1564 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
1565
1566 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1567 if (res == NULL)
1568 return -ENODEV;
1569
1570 mv643xx_eth_shared_base = ioremap(res->start,
1571 MV643XX_ETH_SHARED_REGS_SIZE);
1572 if (mv643xx_eth_shared_base == NULL)
1573 return -ENOMEM;
1574
1575 return 0;
1576
1577}
1578
3ae5eaec 1579static int mv643xx_eth_shared_remove(struct platform_device *pdev)
1da177e4
LT		 1580{
1581 iounmap(mv643xx_eth_shared_base);
1582 mv643xx_eth_shared_base = NULL;
1583
1584 return 0;
1585}
1586
3ae5eaec 1587static struct platform_driver mv643xx_eth_driver = {
1da177e4
LT		 1588 .probe = mv643xx_eth_probe,
1589 .remove = mv643xx_eth_remove,
3ae5eaec
RK		 1590 .driver = {
1591 .name = MV643XX_ETH_NAME,
1592 },
1da177e4
LT		 1593};
1594
3ae5eaec 1595static struct platform_driver mv643xx_eth_shared_driver = {
1da177e4
LT		 1596 .probe = mv643xx_eth_shared_probe,
1597 .remove = mv643xx_eth_shared_remove,
3ae5eaec
RK		 1598 .driver = {
1599 .name = MV643XX_ETH_SHARED_NAME,
1600 },
1da177e4
LT		 1601};
1602
1603/*
1604 * mv643xx_init_module
1605 *
1606 * Registers the network drivers into the Linux kernel
1607 *
1608 * Input : N/A
1609 *
1610 * Output : N/A
1611 */
1612static int __init mv643xx_init_module(void)
1613{
1614 int rc;
1615
3ae5eaec 1616 rc = platform_driver_register(&mv643xx_eth_shared_driver);
1da177e4 1617 if (!rc) {
3ae5eaec 1618 rc = platform_driver_register(&mv643xx_eth_driver);
1da177e4 1619 if (rc)
3ae5eaec 1620 platform_driver_unregister(&mv643xx_eth_shared_driver);
1da177e4
LT		 1621 }
1622 return rc;
1623}
1624
1625/*
1626 * mv643xx_cleanup_module
1627 *
1628 * Registers the network drivers into the Linux kernel
1629 *
1630 * Input : N/A
1631 *
1632 * Output : N/A
1633 */
1634static void __exit mv643xx_cleanup_module(void)
1635{
3ae5eaec
RK		 1636 platform_driver_unregister(&mv643xx_eth_driver);
1637 platform_driver_unregister(&mv643xx_eth_shared_driver);
1da177e4
LT		 1638}
1639
1640module_init(mv643xx_init_module);
1641module_exit(mv643xx_cleanup_module);
1642
1643MODULE_LICENSE("GPL");
1644MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
1645 " and Dale Farnsworth");
1646MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
1647
1648/*
1649 * The second part is the low level driver of the gigE ethernet ports.
1650 */
1651
1652/*
1653 * Marvell's Gigabit Ethernet controller low level driver
1654 *
1655 * DESCRIPTION:
1656 * This file introduce low level API to Marvell's Gigabit Ethernet
1657 * controller. This Gigabit Ethernet Controller driver API controls
1658 * 1) Operations (i.e. port init, start, reset etc').
1659 * 2) Data flow (i.e. port send, receive etc').
1660 * Each Gigabit Ethernet port is controlled via
1661 * struct mv643xx_private.
1662 * This struct includes user configuration information as well as
1663 * driver internal data needed for its operations.
1664 *
1665 * Supported Features:
1666 * - This low level driver is OS independent. Allocating memory for
1667 * the descriptor rings and buffers are not within the scope of
1668 * this driver.
1669 * - The user is free from Rx/Tx queue managing.
1670 * - This low level driver introduce functionality API that enable
1671 * the to operate Marvell's Gigabit Ethernet Controller in a
1672 * convenient way.
1673 * - Simple Gigabit Ethernet port operation API.
1674 * - Simple Gigabit Ethernet port data flow API.
1675 * - Data flow and operation API support per queue functionality.
1676 * - Support cached descriptors for better performance.
1677 * - Enable access to all four DRAM banks and internal SRAM memory
1678 * spaces.
1679 * - PHY access and control API.
1680 * - Port control register configuration API.
1681 * - Full control over Unicast and Multicast MAC configurations.
1682 *
1683 * Operation flow:
1684 *
1685 * Initialization phase
1686 * This phase complete the initialization of the the
1687 * mv643xx_private struct.
1688 * User information regarding port configuration has to be set
1689 * prior to calling the port initialization routine.
1690 *
1691 * In this phase any port Tx/Rx activity is halted, MIB counters
1692 * are cleared, PHY address is set according to user parameter and
1693 * access to DRAM and internal SRAM memory spaces.
1694 *
1695 * Driver ring initialization
1696 * Allocating memory for the descriptor rings and buffers is not
1697 * within the scope of this driver. Thus, the user is required to
1698 * allocate memory for the descriptors ring and buffers. Those
1699 * memory parameters are used by the Rx and Tx ring initialization
1700 * routines in order to curve the descriptor linked list in a form
1701 * of a ring.
1702 * Note: Pay special attention to alignment issues when using
1703 * cached descriptors/buffers. In this phase the driver store
1704 * information in the mv643xx_private struct regarding each queue
1705 * ring.
1706 *
1707 * Driver start
1708 * This phase prepares the Ethernet port for Rx and Tx activity.
1709 * It uses the information stored in the mv643xx_private struct to
1710 * initialize the various port registers.
1711 *
1712 * Data flow:
1713 * All packet references to/from the driver are done using
1714 * struct pkt_info.
1715 * This struct is a unified struct used with Rx and Tx operations.
1716 * This way the user is not required to be familiar with neither
1717 * Tx nor Rx descriptors structures.
1718 * The driver's descriptors rings are management by indexes.
1719 * Those indexes controls the ring resources and used to indicate
1720 * a SW resource error:
1721 * 'current'
1722 * This index points to the current available resource for use. For
1723 * example in Rx process this index will point to the descriptor
1724 * that will be passed to the user upon calling the receive
1725 * routine. In Tx process, this index will point to the descriptor
1726 * that will be assigned with the user packet info and transmitted.
1727 * 'used'
1728 * This index points to the descriptor that need to restore its
1729 * resources. For example in Rx process, using the Rx buffer return
1730 * API will attach the buffer returned in packet info to the
1731 * descriptor pointed by 'used'. In Tx process, using the Tx
1732 * descriptor return will merely return the user packet info with
1733 * the command status of the transmitted buffer pointed by the
1734 * 'used' index. Nevertheless, it is essential to use this routine
1735 * to update the 'used' index.
1736 * 'first'
1737 * This index supports Tx Scatter-Gather. It points to the first
1738 * descriptor of a packet assembled of multiple buffers. For
1739 * example when in middle of Such packet we have a Tx resource
1740 * error the 'curr' index get the value of 'first' to indicate
1741 * that the ring returned to its state before trying to transmit
1742 * this packet.
1743 *
1744 * Receive operation:
1745 * The eth_port_receive API set the packet information struct,
1746 * passed by the caller, with received information from the
1747 * 'current' SDMA descriptor.
1748 * It is the user responsibility to return this resource back
1749 * to the Rx descriptor ring to enable the reuse of this source.
1750 * Return Rx resource is done using the eth_rx_return_buff API.
1751 *
1752 * Transmit operation:
1753 * The eth_port_send API supports Scatter-Gather which enables to
1754 * send a packet spanned over multiple buffers. This means that
1755 * for each packet info structure given by the user and put into
1756 * the Tx descriptors ring, will be transmitted only if the 'LAST'
1757 * bit will be set in the packet info command status field. This
1758 * API also consider restriction regarding buffer alignments and
1759 * sizes.
1760 * The user must return a Tx resource after ensuring the buffer
1761 * has been transmitted to enable the Tx ring indexes to update.
1762 *
1763 * BOARD LAYOUT
1764 * This device is on-board. No jumper diagram is necessary.
1765 *
1766 * EXTERNAL INTERFACE
1767 *
1768 * Prior to calling the initialization routine eth_port_init() the user
1769 * must set the following fields under mv643xx_private struct:
1770 * port_num User Ethernet port number.
1771 * port_mac_addr[6] User defined port MAC address.
1772 * port_config User port configuration value.
1773 * port_config_extend User port config extend value.
1774 * port_sdma_config User port SDMA config value.
1775 * port_serial_control User port serial control value.
1776 *
1777 * This driver data flow is done using the struct pkt_info which
1778 * is a unified struct for Rx and Tx operations:
1779 *
1780 * byte_cnt Tx/Rx descriptor buffer byte count.
1781 * l4i_chk CPU provided TCP Checksum. For Tx operation
1782 * only.
1783 * cmd_sts Tx/Rx descriptor command status.
1784 * buf_ptr Tx/Rx descriptor buffer pointer.
1785 * return_info Tx/Rx user resource return information.
1786 */
1787
1788/* defines */
1789/* SDMA command macros */
1790#define ETH_ENABLE_TX_QUEUE(eth_port) \
1791 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), 1)
1792
1793/* locals */
1794
1795/* PHY routines */
1796static int ethernet_phy_get(unsigned int eth_port_num);
1797static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
1798
1799/* Ethernet Port routines */
1800static int eth_port_uc_addr(unsigned int eth_port_num, unsigned char uc_nibble,
1801 int option);
1802
1803/*
1804 * eth_port_init - Initialize the Ethernet port driver
1805 *
1806 * DESCRIPTION:
1807 * This function prepares the ethernet port to start its activity:
1808 * 1) Completes the ethernet port driver struct initialization toward port
1809 * start routine.
1810 * 2) Resets the device to a quiescent state in case of warm reboot.
1811 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1812 * 4) Clean MAC tables. The reset status of those tables is unknown.
1813 * 5) Set PHY address.
1814 * Note: Call this routine prior to eth_port_start routine and after
1815 * setting user values in the user fields of Ethernet port control
1816 * struct.
1817 *
1818 * INPUT:
1819 * struct mv643xx_private *mp Ethernet port control struct
1820 *
1821 * OUTPUT:
1822 * See description.
1823 *
1824 * RETURN:
1825 * None.
1826 */
1827static void eth_port_init(struct mv643xx_private *mp)
1828{
1829 mp->port_rx_queue_command = 0;
1830 mp->port_tx_queue_command = 0;
1831
1832 mp->rx_resource_err = 0;
1833 mp->tx_resource_err = 0;
1834
1835 eth_port_reset(mp->port_num);
1836
1837 eth_port_init_mac_tables(mp->port_num);
1838
1839 ethernet_phy_reset(mp->port_num);
1840}
1841
1842/*
1843 * eth_port_start - Start the Ethernet port activity.
1844 *
1845 * DESCRIPTION:
1846 * This routine prepares the Ethernet port for Rx and Tx activity:
1847 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1848 * has been initialized a descriptor's ring (using
1849 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
1850 * 2. Initialize and enable the Ethernet configuration port by writing to
1851 * the port's configuration and command registers.
1852 * 3. Initialize and enable the SDMA by writing to the SDMA's
1853 * configuration and command registers. After completing these steps,
1854 * the ethernet port SDMA can starts to perform Rx and Tx activities.
1855 *
1856 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1857 * to calling this function (use ether_init_tx_desc_ring for Tx queues
1858 * and ether_init_rx_desc_ring for Rx queues).
1859 *
1860 * INPUT:
1861 * struct mv643xx_private *mp Ethernet port control struct
1862 *
1863 * OUTPUT:
1864 * Ethernet port is ready to receive and transmit.
1865 *
1866 * RETURN:
1867 * None.
1868 */
1869static void eth_port_start(struct mv643xx_private *mp)
1870{
1871 unsigned int port_num = mp->port_num;
1872 int tx_curr_desc, rx_curr_desc;
1873
1874 /* Assignment of Tx CTRP of given queue */
1875 tx_curr_desc = mp->tx_curr_desc_q;
1876 mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1877 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
1878
1879 /* Assignment of Rx CRDP of given queue */
1880 rx_curr_desc = mp->rx_curr_desc_q;
1881 mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1882 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
1883
1884 /* Add the assigned Ethernet address to the port's address table */
1885 eth_port_uc_addr_set(port_num, mp->port_mac_addr);
1886
1887 /* Assign port configuration and command. */
1888 mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num), mp->port_config);
1889
1890 mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num),
1891 mp->port_config_extend);
1892
1893
1894 /* Increase the Rx side buffer size if supporting GigE */
1895 if (mp->port_serial_control & MV643XX_ETH_SET_GMII_SPEED_TO_1000)
1896 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1897 (mp->port_serial_control & 0xfff1ffff) | (0x5 << 17));
1898 else
1899 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1900 mp->port_serial_control);
1901
1902 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1903 mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)) |
1904 MV643XX_ETH_SERIAL_PORT_ENABLE);
1905
1906 /* Assign port SDMA configuration */
1907 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num),
1908 mp->port_sdma_config);
1909
1910 /* Enable port Rx. */
1911 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
1912 mp->port_rx_queue_command);
8f543718
DF		 1913
1914 /* Disable port bandwidth limits by clearing MTU register */
1915 mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num), 0);
1da177e4
LT		 1916}
1917
1918/*
1919 * eth_port_uc_addr_set - This function Set the port Unicast address.
1920 *
1921 * DESCRIPTION:
1922 * This function Set the port Ethernet MAC address.
1923 *
1924 * INPUT:
1925 * unsigned int eth_port_num Port number.
1926 * char * p_addr Address to be set
1927 *
1928 * OUTPUT:
1929 * Set MAC address low and high registers. also calls eth_port_uc_addr()
1930 * To set the unicast table with the proper information.
1931 *
1932 * RETURN:
1933 * N/A.
1934 *
1935 */
1936static void eth_port_uc_addr_set(unsigned int eth_port_num,
1937 unsigned char *p_addr)
1938{
1939 unsigned int mac_h;
1940 unsigned int mac_l;
1941
1942 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1943 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
1944 (p_addr[3] << 0);
1945
1946 mv_write(MV643XX_ETH_MAC_ADDR_LOW(eth_port_num), mac_l);
1947 mv_write(MV643XX_ETH_MAC_ADDR_HIGH(eth_port_num), mac_h);
1948
1949 /* Accept frames of this address */
1950 eth_port_uc_addr(eth_port_num, p_addr[5], ACCEPT_MAC_ADDR);
1951
1952 return;
1953}
1954
1955/*
1956 * eth_port_uc_addr_get - This function retrieves the port Unicast address
1957 * (MAC address) from the ethernet hw registers.
1958 *
1959 * DESCRIPTION:
1960 * This function retrieves the port Ethernet MAC address.
1961 *
1962 * INPUT:
1963 * unsigned int eth_port_num Port number.
1964 * char *MacAddr pointer where the MAC address is stored
1965 *
1966 * OUTPUT:
1967 * Copy the MAC address to the location pointed to by MacAddr
1968 *
1969 * RETURN:
1970 * N/A.
1971 *
1972 */
1973static void eth_port_uc_addr_get(struct net_device *dev, unsigned char *p_addr)
1974{
1975 struct mv643xx_private *mp = netdev_priv(dev);
1976 unsigned int mac_h;
1977 unsigned int mac_l;
1978
1979 mac_h = mv_read(MV643XX_ETH_MAC_ADDR_HIGH(mp->port_num));
1980 mac_l = mv_read(MV643XX_ETH_MAC_ADDR_LOW(mp->port_num));
1981
1982 p_addr[0] = (mac_h >> 24) & 0xff;
1983 p_addr[1] = (mac_h >> 16) & 0xff;
1984 p_addr[2] = (mac_h >> 8) & 0xff;
1985 p_addr[3] = mac_h & 0xff;
1986 p_addr[4] = (mac_l >> 8) & 0xff;
1987 p_addr[5] = mac_l & 0xff;
1988}
1989
1990/*
1991 * eth_port_uc_addr - This function Set the port unicast address table
1992 *
1993 * DESCRIPTION:
1994 * This function locates the proper entry in the Unicast table for the
1995 * specified MAC nibble and sets its properties according to function
1996 * parameters.
1997 *
1998 * INPUT:
1999 * unsigned int eth_port_num Port number.
2000 * unsigned char uc_nibble Unicast MAC Address last nibble.
2001 * int option 0 = Add, 1 = remove address.
2002 *
2003 * OUTPUT:
2004 * This function add/removes MAC addresses from the port unicast address
2005 * table.
2006 *
2007 * RETURN:
2008 * true is output succeeded.
2009 * false if option parameter is invalid.
2010 *
2011 */
2012static int eth_port_uc_addr(unsigned int eth_port_num, unsigned char uc_nibble,
2013 int option)
2014{
2015 unsigned int unicast_reg;
2016 unsigned int tbl_offset;
2017 unsigned int reg_offset;
2018
2019 /* Locate the Unicast table entry */
2020 uc_nibble = (0xf & uc_nibble);
2021 tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */
2022 reg_offset = uc_nibble % 4; /* Entry offset within the above register */
2023
2024 switch (option) {
2025 case REJECT_MAC_ADDR:
2026 /* Clear accepts frame bit at given unicast DA table entry */
2027 unicast_reg = mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2028 (eth_port_num) + tbl_offset));
2029
2030 unicast_reg &= (0x0E << (8 * reg_offset));
2031
2032 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2033 (eth_port_num) + tbl_offset), unicast_reg);
2034 break;
2035
2036 case ACCEPT_MAC_ADDR:
2037 /* Set accepts frame bit at unicast DA filter table entry */
2038 unicast_reg =
2039 mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2040 (eth_port_num) + tbl_offset));
2041
2042 unicast_reg |= (0x01 << (8 * reg_offset));
2043
2044 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2045 (eth_port_num) + tbl_offset), unicast_reg);
2046
2047 break;
2048
2049 default:
2050 return 0;
2051 }
2052
2053 return 1;
2054}
2055
2056/*
2057 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2058 *
2059 * DESCRIPTION:
2060 * Go through all the DA filter tables (Unicast, Special Multicast &
2061 * Other Multicast) and set each entry to 0.
2062 *
2063 * INPUT:
2064 * unsigned int eth_port_num Ethernet Port number.
2065 *
2066 * OUTPUT:
2067 * Multicast and Unicast packets are rejected.
2068 *
2069 * RETURN:
2070 * None.
2071 */
2072static void eth_port_init_mac_tables(unsigned int eth_port_num)
2073{
2074 int table_index;
2075
2076 /* Clear DA filter unicast table (Ex_dFUT) */
2077 for (table_index = 0; table_index <= 0xC; table_index += 4)
2078 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2079 (eth_port_num) + table_index), 0);
2080
2081 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2082 /* Clear DA filter special multicast table (Ex_dFSMT) */
2083 mv_write((MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2084 (eth_port_num) + table_index), 0);
2085 /* Clear DA filter other multicast table (Ex_dFOMT) */
2086 mv_write((MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2087 (eth_port_num) + table_index), 0);
2088 }
2089}
2090
2091/*
2092 * eth_clear_mib_counters - Clear all MIB counters
2093 *
2094 * DESCRIPTION:
2095 * This function clears all MIB counters of a specific ethernet port.
2096 * A read from the MIB counter will reset the counter.
2097 *
2098 * INPUT:
2099 * unsigned int eth_port_num Ethernet Port number.
2100 *
2101 * OUTPUT:
2102 * After reading all MIB counters, the counters resets.
2103 *
2104 * RETURN:
2105 * MIB counter value.
2106 *
2107 */
2108static void eth_clear_mib_counters(unsigned int eth_port_num)
2109{
2110 int i;
2111
2112 /* Perform dummy reads from MIB counters */
2113 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2114 i += 4)
2115 mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num) + i);
2116}
2117
2118static inline u32 read_mib(struct mv643xx_private *mp, int offset)
2119{
2120 return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp->port_num) + offset);
2121}
2122
2123static void eth_update_mib_counters(struct mv643xx_private *mp)
2124{
2125 struct mv643xx_mib_counters *p = &mp->mib_counters;
2126 int offset;
2127
2128 p->good_octets_received +=
2129 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
2130 p->good_octets_received +=
2131 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
2132
2133 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
2134 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
2135 offset += 4)
2136 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2137
2138 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
2139 p->good_octets_sent +=
2140 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
2141
2142 for (offset = ETH_MIB_GOOD_FRAMES_SENT;
2143 offset <= ETH_MIB_LATE_COLLISION;
2144 offset += 4)
2145 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2146}
2147
2148/*
2149 * ethernet_phy_detect - Detect whether a phy is present
2150 *
2151 * DESCRIPTION:
2152 * This function tests whether there is a PHY present on
2153 * the specified port.
2154 *
2155 * INPUT:
2156 * unsigned int eth_port_num Ethernet Port number.
2157 *
2158 * OUTPUT:
2159 * None
2160 *
2161 * RETURN:
2162 * 0 on success
2163 * -ENODEV on failure
2164 *
2165 */
2166static int ethernet_phy_detect(unsigned int port_num)
2167{
2168 unsigned int phy_reg_data0;
2169 int auto_neg;
2170
2171 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2172 auto_neg = phy_reg_data0 & 0x1000;
2173 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2174 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2175
2176 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2177 if ((phy_reg_data0 & 0x1000) == auto_neg)
2178 return -ENODEV; /* change didn't take */
2179
2180 phy_reg_data0 ^= 0x1000;
2181 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2182 return 0;
2183}
2184
2185/*
2186 * ethernet_phy_get - Get the ethernet port PHY address.
2187 *
2188 * DESCRIPTION:
2189 * This routine returns the given ethernet port PHY address.
2190 *
2191 * INPUT:
2192 * unsigned int eth_port_num Ethernet Port number.
2193 *
2194 * OUTPUT:
2195 * None.
2196 *
2197 * RETURN:
2198 * PHY address.
2199 *
2200 */
2201static int ethernet_phy_get(unsigned int eth_port_num)
2202{
2203 unsigned int reg_data;
2204
2205 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2206
2207 return ((reg_data >> (5 * eth_port_num)) & 0x1f);
2208}
2209
2210/*
2211 * ethernet_phy_set - Set the ethernet port PHY address.
2212 *
2213 * DESCRIPTION:
2214 * This routine sets the given ethernet port PHY address.
2215 *
2216 * INPUT:
2217 * unsigned int eth_port_num Ethernet Port number.
2218 * int phy_addr PHY address.
2219 *
2220 * OUTPUT:
2221 * None.
2222 *
2223 * RETURN:
2224 * None.
2225 *
2226 */
2227static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr)
2228{
2229 u32 reg_data;
2230 int addr_shift = 5 * eth_port_num;
2231
2232 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2233 reg_data &= ~(0x1f << addr_shift);
2234 reg_data |= (phy_addr & 0x1f) << addr_shift;
2235 mv_write(MV643XX_ETH_PHY_ADDR_REG, reg_data);
2236}
2237
2238/*
2239 * ethernet_phy_reset - Reset Ethernet port PHY.
2240 *
2241 * DESCRIPTION:
2242 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2243 *
2244 * INPUT:
2245 * unsigned int eth_port_num Ethernet Port number.
2246 *
2247 * OUTPUT:
2248 * The PHY is reset.
2249 *
2250 * RETURN:
2251 * None.
2252 *
2253 */
2254static void ethernet_phy_reset(unsigned int eth_port_num)
2255{
2256 unsigned int phy_reg_data;
2257
2258 /* Reset the PHY */
2259 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
2260 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2261 eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data);
2262}
2263
2264/*
2265 * eth_port_reset - Reset Ethernet port
2266 *
2267 * DESCRIPTION:
2268 * This routine resets the chip by aborting any SDMA engine activity and
2269 * clearing the MIB counters. The Receiver and the Transmit unit are in
2270 * idle state after this command is performed and the port is disabled.
2271 *
2272 * INPUT:
2273 * unsigned int eth_port_num Ethernet Port number.
2274 *
2275 * OUTPUT:
2276 * Channel activity is halted.
2277 *
2278 * RETURN:
2279 * None.
2280 *
2281 */
2282static void eth_port_reset(unsigned int port_num)
2283{
2284 unsigned int reg_data;
2285
2286 /* Stop Tx port activity. Check port Tx activity. */
2287 reg_data = mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num));
2288
2289 if (reg_data & 0xFF) {
2290 /* Issue stop command for active channels only */
2291 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num),
2292 (reg_data << 8));
2293
2294 /* Wait for all Tx activity to terminate. */
2295 /* Check port cause register that all Tx queues are stopped */
2296 while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
2297 & 0xFF)
2298 udelay(10);
2299 }
2300
2301 /* Stop Rx port activity. Check port Rx activity. */
2302 reg_data = mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num));
2303
2304 if (reg_data & 0xFF) {
2305 /* Issue stop command for active channels only */
2306 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
2307 (reg_data << 8));
2308
2309 /* Wait for all Rx activity to terminate. */
2310 /* Check port cause register that all Rx queues are stopped */
2311 while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
2312 & 0xFF)
2313 udelay(10);
2314 }
2315
2316 /* Clear all MIB counters */
2317 eth_clear_mib_counters(port_num);
2318
2319 /* Reset the Enable bit in the Configuration Register */
2320 reg_data = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
2321 reg_data &= ~MV643XX_ETH_SERIAL_PORT_ENABLE;
2322 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), reg_data);
2323}
2324
1da177e4
LT		 2325
2326static int eth_port_autoneg_supported(unsigned int eth_port_num)
2327{
2328 unsigned int phy_reg_data0;
2329
2330 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data0);
2331
2332 return phy_reg_data0 & 0x1000;
2333}
2334
2335static int eth_port_link_is_up(unsigned int eth_port_num)
2336{
2337 unsigned int phy_reg_data1;
2338
2339 eth_port_read_smi_reg(eth_port_num, 1, &phy_reg_data1);
2340
2341 if (eth_port_autoneg_supported(eth_port_num)) {
2342 if (phy_reg_data1 & 0x20) /* auto-neg complete */
2343 return 1;
2344 } else if (phy_reg_data1 & 0x4) /* link up */
2345 return 1;
2346
2347 return 0;
2348}
2349
1da177e4
LT		 2350/*
2351 * eth_port_read_smi_reg - Read PHY registers
2352 *
2353 * DESCRIPTION:
2354 * This routine utilize the SMI interface to interact with the PHY in
2355 * order to perform PHY register read.
2356 *
2357 * INPUT:
2358 * unsigned int port_num Ethernet Port number.
2359 * unsigned int phy_reg PHY register address offset.
2360 * unsigned int *value Register value buffer.
2361 *
2362 * OUTPUT:
2363 * Write the value of a specified PHY register into given buffer.
2364 *
2365 * RETURN:
2366 * false if the PHY is busy or read data is not in valid state.
2367 * true otherwise.
2368 *
2369 */
2370static void eth_port_read_smi_reg(unsigned int port_num,
2371 unsigned int phy_reg, unsigned int *value)
2372{
2373 int phy_addr = ethernet_phy_get(port_num);
2374 unsigned long flags;
2375 int i;
2376
2377 /* the SMI register is a shared resource */
2378 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2379
2380 /* wait for the SMI register to become available */
2381 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2382 if (i == PHY_WAIT_ITERATIONS) {
2383 printk("mv643xx PHY busy timeout, port %d\n", port_num);
2384 goto out;
2385 }
2386 udelay(PHY_WAIT_MICRO_SECONDS);
2387 }
2388
2389 mv_write(MV643XX_ETH_SMI_REG,
2390 (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);
2391
2392 /* now wait for the data to be valid */
2393 for (i = 0; !(mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_READ_VALID); i++) {
2394 if (i == PHY_WAIT_ITERATIONS) {
2395 printk("mv643xx PHY read timeout, port %d\n", port_num);
2396 goto out;
2397 }
2398 udelay(PHY_WAIT_MICRO_SECONDS);
2399 }
2400
2401 *value = mv_read(MV643XX_ETH_SMI_REG) & 0xffff;
2402out:
2403 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2404}
2405
2406/*
2407 * eth_port_write_smi_reg - Write to PHY registers
2408 *
2409 * DESCRIPTION:
2410 * This routine utilize the SMI interface to interact with the PHY in
2411 * order to perform writes to PHY registers.
2412 *
2413 * INPUT:
2414 * unsigned int eth_port_num Ethernet Port number.
2415 * unsigned int phy_reg PHY register address offset.
2416 * unsigned int value Register value.
2417 *
2418 * OUTPUT:
2419 * Write the given value to the specified PHY register.
2420 *
2421 * RETURN:
2422 * false if the PHY is busy.
2423 * true otherwise.
2424 *
2425 */
2426static void eth_port_write_smi_reg(unsigned int eth_port_num,
2427 unsigned int phy_reg, unsigned int value)
2428{
2429 int phy_addr;
2430 int i;
2431 unsigned long flags;
2432
2433 phy_addr = ethernet_phy_get(eth_port_num);
2434
2435 /* the SMI register is a shared resource */
2436 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2437
2438 /* wait for the SMI register to become available */
2439 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2440 if (i == PHY_WAIT_ITERATIONS) {
2441 printk("mv643xx PHY busy timeout, port %d\n",
2442 eth_port_num);
2443 goto out;
2444 }
2445 udelay(PHY_WAIT_MICRO_SECONDS);
2446 }
2447
2448 mv_write(MV643XX_ETH_SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
2449 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2450out:
2451 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2452}
2453
2454/*
2455 * eth_port_send - Send an Ethernet packet
2456 *
2457 * DESCRIPTION:
2458 * This routine send a given packet described by p_pktinfo parameter. It
2459 * supports transmitting of a packet spaned over multiple buffers. The
2460 * routine updates 'curr' and 'first' indexes according to the packet
2461 * segment passed to the routine. In case the packet segment is first,
2462 * the 'first' index is update. In any case, the 'curr' index is updated.
2463 * If the routine get into Tx resource error it assigns 'curr' index as
2464 * 'first'. This way the function can abort Tx process of multiple
2465 * descriptors per packet.
2466 *
2467 * INPUT:
2468 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2469 * struct pkt_info *p_pkt_info User packet buffer.
2470 *
2471 * OUTPUT:
2472 * Tx ring 'curr' and 'first' indexes are updated.
2473 *
2474 * RETURN:
2475 * ETH_QUEUE_FULL in case of Tx resource error.
2476 * ETH_ERROR in case the routine can not access Tx desc ring.
2477 * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
2478 * ETH_OK otherwise.
2479 *
2480 */
2481#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2482/*
2483 * Modified to include the first descriptor pointer in case of SG
2484 */
2485static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
2486 struct pkt_info *p_pkt_info)
2487{
2488 int tx_desc_curr, tx_desc_used, tx_first_desc, tx_next_desc;
2489 struct eth_tx_desc *current_descriptor;
2490 struct eth_tx_desc *first_descriptor;
2491 u32 command;
2492
2493 /* Do not process Tx ring in case of Tx ring resource error */
2494 if (mp->tx_resource_err)
2495 return ETH_QUEUE_FULL;
2496
2497 /*
2498 * The hardware requires that each buffer that is <= 8 bytes
2499 * in length must be aligned on an 8 byte boundary.
2500 */
2501 if (p_pkt_info->byte_cnt <= 8 && p_pkt_info->buf_ptr & 0x7) {
2502 printk(KERN_ERR
2503 "mv643xx_eth port %d: packet size <= 8 problem\n",
2504 mp->port_num);
2505 return ETH_ERROR;
2506 }
2507
b111ceb6
DF		 2508 mp->tx_ring_skbs++;
2509 BUG_ON(mp->tx_ring_skbs > mp->tx_ring_size);
2510
1da177e4
LT		 2511 /* Get the Tx Desc ring indexes */
2512 tx_desc_curr = mp->tx_curr_desc_q;
2513 tx_desc_used = mp->tx_used_desc_q;
2514
2515 current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
2516
2517 tx_next_desc = (tx_desc_curr + 1) % mp->tx_ring_size;
2518
2519 current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
2520 current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
2521 current_descriptor->l4i_chk = p_pkt_info->l4i_chk;
2522 mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info;
2523
2524 command = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC |
2525 ETH_BUFFER_OWNED_BY_DMA;
2526 if (command & ETH_TX_FIRST_DESC) {
2527 tx_first_desc = tx_desc_curr;
2528 mp->tx_first_desc_q = tx_first_desc;
2529 first_descriptor = current_descriptor;
2530 mp->tx_first_command = command;
2531 } else {
2532 tx_first_desc = mp->tx_first_desc_q;
2533 first_descriptor = &mp->p_tx_desc_area[tx_first_desc];
2534 BUG_ON(first_descriptor == NULL);
2535 current_descriptor->cmd_sts = command;
2536 }
2537
2538 if (command & ETH_TX_LAST_DESC) {
2539 wmb();
2540 first_descriptor->cmd_sts = mp->tx_first_command;
2541
2542 wmb();
2543 ETH_ENABLE_TX_QUEUE(mp->port_num);
2544
2545 /*
2546 * Finish Tx packet. Update first desc in case of Tx resource
2547 * error */
2548 tx_first_desc = tx_next_desc;
2549 mp->tx_first_desc_q = tx_first_desc;
2550 }
2551
2552 /* Check for ring index overlap in the Tx desc ring */
2553 if (tx_next_desc == tx_desc_used) {
2554 mp->tx_resource_err = 1;
2555 mp->tx_curr_desc_q = tx_first_desc;
2556
2557 return ETH_QUEUE_LAST_RESOURCE;
2558 }
2559
2560 mp->tx_curr_desc_q = tx_next_desc;
2561
2562 return ETH_OK;
2563}
2564#else
2565static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
2566 struct pkt_info *p_pkt_info)
2567{
2568 int tx_desc_curr;
2569 int tx_desc_used;
2570 struct eth_tx_desc *current_descriptor;
2571 unsigned int command_status;
2572
2573 /* Do not process Tx ring in case of Tx ring resource error */
2574 if (mp->tx_resource_err)
2575 return ETH_QUEUE_FULL;
2576
b111ceb6
DF		 2577 mp->tx_ring_skbs++;
2578 BUG_ON(mp->tx_ring_skbs > mp->tx_ring_size);
2579
1da177e4
LT		 2580 /* Get the Tx Desc ring indexes */
2581 tx_desc_curr = mp->tx_curr_desc_q;
2582 tx_desc_used = mp->tx_used_desc_q;
2583 current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
2584
2585 command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
2586 current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
2587 current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
2588 mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info;
2589
2590 /* Set last desc with DMA ownership and interrupt enable. */
2591 wmb();
2592 current_descriptor->cmd_sts = command_status |
2593 ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
2594
2595 wmb();
2596 ETH_ENABLE_TX_QUEUE(mp->port_num);
2597
2598 /* Finish Tx packet. Update first desc in case of Tx resource error */
2599 tx_desc_curr = (tx_desc_curr + 1) % mp->tx_ring_size;
2600
2601 /* Update the current descriptor */
2602 mp->tx_curr_desc_q = tx_desc_curr;
2603
2604 /* Check for ring index overlap in the Tx desc ring */
2605 if (tx_desc_curr == tx_desc_used) {
2606 mp->tx_resource_err = 1;
2607 return ETH_QUEUE_LAST_RESOURCE;
2608 }
2609
2610 return ETH_OK;
2611}
2612#endif
2613
2614/*
2615 * eth_tx_return_desc - Free all used Tx descriptors
2616 *
2617 * DESCRIPTION:
2618 * This routine returns the transmitted packet information to the caller.
2619 * It uses the 'first' index to support Tx desc return in case a transmit
2620 * of a packet spanned over multiple buffer still in process.
2621 * In case the Tx queue was in "resource error" condition, where there are
2622 * no available Tx resources, the function resets the resource error flag.
2623 *
2624 * INPUT:
2625 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2626 * struct pkt_info *p_pkt_info User packet buffer.
2627 *
2628 * OUTPUT:
2629 * Tx ring 'first' and 'used' indexes are updated.
2630 *
2631 * RETURN:
2632 * ETH_ERROR in case the routine can not access Tx desc ring.
2633 * ETH_RETRY in case there is transmission in process.
2634 * ETH_END_OF_JOB if the routine has nothing to release.
2635 * ETH_OK otherwise.
2636 *
2637 */
2638static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv643xx_private *mp,
2639 struct pkt_info *p_pkt_info)
2640{
2641 int tx_desc_used;
2642#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2643 int tx_busy_desc = mp->tx_first_desc_q;
2644#else
2645 int tx_busy_desc = mp->tx_curr_desc_q;
2646#endif
2647 struct eth_tx_desc *p_tx_desc_used;
2648 unsigned int command_status;
2649
2650 /* Get the Tx Desc ring indexes */
2651 tx_desc_used = mp->tx_used_desc_q;
2652
2653 p_tx_desc_used = &mp->p_tx_desc_area[tx_desc_used];
2654
2655 /* Sanity check */
2656 if (p_tx_desc_used == NULL)
2657 return ETH_ERROR;
2658
2659 /* Stop release. About to overlap the current available Tx descriptor */
2660 if (tx_desc_used == tx_busy_desc && !mp->tx_resource_err)
2661 return ETH_END_OF_JOB;
2662
2663 command_status = p_tx_desc_used->cmd_sts;
2664
2665 /* Still transmitting... */
2666 if (command_status & (ETH_BUFFER_OWNED_BY_DMA))
2667 return ETH_RETRY;
2668
2669 /* Pass the packet information to the caller */
2670 p_pkt_info->cmd_sts = command_status;
2671 p_pkt_info->return_info = mp->tx_skb[tx_desc_used];
2672 mp->tx_skb[tx_desc_used] = NULL;
2673
2674 /* Update the next descriptor to release. */
2675 mp->tx_used_desc_q = (tx_desc_used + 1) % mp->tx_ring_size;
2676
2677 /* Any Tx return cancels the Tx resource error status */
2678 mp->tx_resource_err = 0;
2679
b111ceb6
DF		 2680 BUG_ON(mp->tx_ring_skbs == 0);
2681 mp->tx_ring_skbs--;
2682
1da177e4
LT		 2683 return ETH_OK;
2684}
2685
2686/*
2687 * eth_port_receive - Get received information from Rx ring.
2688 *
2689 * DESCRIPTION:
2690 * This routine returns the received data to the caller. There is no
2691 * data copying during routine operation. All information is returned
2692 * using pointer to packet information struct passed from the caller.
2693 * If the routine exhausts Rx ring resources then the resource error flag
2694 * is set.
2695 *
2696 * INPUT:
2697 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2698 * struct pkt_info *p_pkt_info User packet buffer.
2699 *
2700 * OUTPUT:
2701 * Rx ring current and used indexes are updated.
2702 *
2703 * RETURN:
2704 * ETH_ERROR in case the routine can not access Rx desc ring.
2705 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
2706 * ETH_END_OF_JOB if there is no received data.
2707 * ETH_OK otherwise.
2708 */
2709static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
2710 struct pkt_info *p_pkt_info)
2711{
2712 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
2713 volatile struct eth_rx_desc *p_rx_desc;
2714 unsigned int command_status;
2715
2716 /* Do not process Rx ring in case of Rx ring resource error */
2717 if (mp->rx_resource_err)
2718 return ETH_QUEUE_FULL;
2719
2720 /* Get the Rx Desc ring 'curr and 'used' indexes */
2721 rx_curr_desc = mp->rx_curr_desc_q;
2722 rx_used_desc = mp->rx_used_desc_q;
2723
2724 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];
2725
2726 /* The following parameters are used to save readings from memory */
2727 command_status = p_rx_desc->cmd_sts;
2728 rmb();
2729
2730 /* Nothing to receive... */
2731 if (command_status & (ETH_BUFFER_OWNED_BY_DMA))
2732 return ETH_END_OF_JOB;
2733
2734 p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET;
2735 p_pkt_info->cmd_sts = command_status;
2736 p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET;
2737 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
2738 p_pkt_info->l4i_chk = p_rx_desc->buf_size;
2739
2740 /* Clean the return info field to indicate that the packet has been */
2741 /* moved to the upper layers */
2742 mp->rx_skb[rx_curr_desc] = NULL;
2743
2744 /* Update current index in data structure */
2745 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
2746 mp->rx_curr_desc_q = rx_next_curr_desc;
2747
2748 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
2749 if (rx_next_curr_desc == rx_used_desc)
2750 mp->rx_resource_err = 1;
2751
2752 return ETH_OK;
2753}
2754
2755/*
2756 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
2757 *
2758 * DESCRIPTION:
2759 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
2760 * next 'used' descriptor and attached the returned buffer to it.
2761 * In case the Rx ring was in "resource error" condition, where there are
2762 * no available Rx resources, the function resets the resource error flag.
2763 *
2764 * INPUT:
2765 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2766 * struct pkt_info *p_pkt_info Information on returned buffer.
2767 *
2768 * OUTPUT:
2769 * New available Rx resource in Rx descriptor ring.
2770 *
2771 * RETURN:
2772 * ETH_ERROR in case the routine can not access Rx desc ring.
2773 * ETH_OK otherwise.
2774 */
2775static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
2776 struct pkt_info *p_pkt_info)
2777{
2778 int used_rx_desc; /* Where to return Rx resource */
2779 volatile struct eth_rx_desc *p_used_rx_desc;
2780
2781 /* Get 'used' Rx descriptor */
2782 used_rx_desc = mp->rx_used_desc_q;
2783 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];
2784
2785 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
2786 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
2787 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
2788
2789 /* Flush the write pipe */
2790
2791 /* Return the descriptor to DMA ownership */
2792 wmb();
2793 p_used_rx_desc->cmd_sts =
2794 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
2795 wmb();
2796
2797 /* Move the used descriptor pointer to the next descriptor */
2798 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;
2799
2800 /* Any Rx return cancels the Rx resource error status */
2801 mp->rx_resource_err = 0;
2802
2803 return ETH_OK;
2804}
2805
2806/************* Begin ethtool support *************************/
2807
2808struct mv643xx_stats {
2809 char stat_string[ETH_GSTRING_LEN];
2810 int sizeof_stat;
2811 int stat_offset;
2812};
2813
2814#define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \
2815 offsetof(struct mv643xx_private, m)
2816
2817static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
2818 { "rx_packets", MV643XX_STAT(stats.rx_packets) },
2819 { "tx_packets", MV643XX_STAT(stats.tx_packets) },
2820 { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
2821 { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
2822 { "rx_errors", MV643XX_STAT(stats.rx_errors) },
2823 { "tx_errors", MV643XX_STAT(stats.tx_errors) },
2824 { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
2825 { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
2826 { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
2827 { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
2828 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
2829 { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
2830 { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
2831 { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
2832 { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
2833 { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
2834 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
2835 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
2836 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
2837 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
2838 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
2839 { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
2840 { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
2841 { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
2842 { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
2843 { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
2844 { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
2845 { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
2846 { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
2847 { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
2848 { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
2849 { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
2850 { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
2851 { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
2852 { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
2853 { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
2854 { "collision", MV643XX_STAT(mib_counters.collision) },
2855 { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
2856};
2857
2858#define MV643XX_STATS_LEN \
2859 sizeof(mv643xx_gstrings_stats) / sizeof(struct mv643xx_stats)
2860
2861static int
2862mv643xx_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
2863{
2864 struct mv643xx_private *mp = netdev->priv;
2865 int port_num = mp->port_num;
2866 int autoneg = eth_port_autoneg_supported(port_num);
2867 int mode_10_bit;
2868 int auto_duplex;
2869 int half_duplex = 0;
2870 int full_duplex = 0;
2871 int auto_speed;
2872 int speed_10 = 0;
2873 int speed_100 = 0;
2874 int speed_1000 = 0;
2875
2876 u32 pcs = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
2877 u32 psr = mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num));
2878
2879 mode_10_bit = psr & MV643XX_ETH_PORT_STATUS_MODE_10_BIT;
2880
2881 if (mode_10_bit) {
2882 ecmd->supported = SUPPORTED_10baseT_Half;
2883 } else {
2884 ecmd->supported = (SUPPORTED_10baseT_Half |
2885 SUPPORTED_10baseT_Full |
2886 SUPPORTED_100baseT_Half |
2887 SUPPORTED_100baseT_Full |
2888 SUPPORTED_1000baseT_Full |
2889 (autoneg ? SUPPORTED_Autoneg : 0) |
2890 SUPPORTED_TP);
2891
2892 auto_duplex = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX);
2893 auto_speed = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII);
2894
2895 ecmd->advertising = ADVERTISED_TP;
2896
2897 if (autoneg) {
2898 ecmd->advertising |= ADVERTISED_Autoneg;
2899
2900 if (auto_duplex) {
2901 half_duplex = 1;
2902 full_duplex = 1;
2903 } else {
2904 if (pcs & MV643XX_ETH_SET_FULL_DUPLEX_MODE)
2905 full_duplex = 1;
2906 else
2907 half_duplex = 1;
2908 }
2909
2910 if (auto_speed) {
2911 speed_10 = 1;
2912 speed_100 = 1;
2913 speed_1000 = 1;
2914 } else {
2915 if (pcs & MV643XX_ETH_SET_GMII_SPEED_TO_1000)
2916 speed_1000 = 1;
2917 else if (pcs & MV643XX_ETH_SET_MII_SPEED_TO_100)
2918 speed_100 = 1;
2919 else
2920 speed_10 = 1;
2921 }
2922
2923 if (speed_10 & half_duplex)
2924 ecmd->advertising |= ADVERTISED_10baseT_Half;
2925 if (speed_10 & full_duplex)
2926 ecmd->advertising |= ADVERTISED_10baseT_Full;
2927 if (speed_100 & half_duplex)
2928 ecmd->advertising |= ADVERTISED_100baseT_Half;
2929 if (speed_100 & full_duplex)
2930 ecmd->advertising |= ADVERTISED_100baseT_Full;
2931 if (speed_1000)
2932 ecmd->advertising |= ADVERTISED_1000baseT_Full;
2933 }
2934 }
2935
2936 ecmd->port = PORT_TP;
2937 ecmd->phy_address = ethernet_phy_get(port_num);
2938
2939 ecmd->transceiver = XCVR_EXTERNAL;
2940
2941 if (netif_carrier_ok(netdev)) {
2942 if (mode_10_bit)
2943 ecmd->speed = SPEED_10;
2944 else {
2945 if (psr & MV643XX_ETH_PORT_STATUS_GMII_1000)
2946 ecmd->speed = SPEED_1000;
2947 else if (psr & MV643XX_ETH_PORT_STATUS_MII_100)
2948 ecmd->speed = SPEED_100;
2949 else
2950 ecmd->speed = SPEED_10;
2951 }
2952
2953 if (psr & MV643XX_ETH_PORT_STATUS_FULL_DUPLEX)
2954 ecmd->duplex = DUPLEX_FULL;
2955 else
2956 ecmd->duplex = DUPLEX_HALF;
2957 } else {
2958 ecmd->speed = -1;
2959 ecmd->duplex = -1;
2960 }
2961
2962 ecmd->autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2963 return 0;
2964}
2965
2966static void
2967mv643xx_get_drvinfo(struct net_device *netdev,
2968 struct ethtool_drvinfo *drvinfo)
2969{
2970 strncpy(drvinfo->driver, mv643xx_driver_name, 32);
2971 strncpy(drvinfo->version, mv643xx_driver_version, 32);
2972 strncpy(drvinfo->fw_version, "N/A", 32);
2973 strncpy(drvinfo->bus_info, "mv643xx", 32);
2974 drvinfo->n_stats = MV643XX_STATS_LEN;
2975}
2976
2977static int
2978mv643xx_get_stats_count(struct net_device *netdev)
2979{
2980 return MV643XX_STATS_LEN;
2981}
2982
2983static void
2984mv643xx_get_ethtool_stats(struct net_device *netdev,
2985 struct ethtool_stats *stats, uint64_t *data)
2986{
2987 struct mv643xx_private *mp = netdev->priv;
2988 int i;
2989
2990 eth_update_mib_counters(mp);
2991
2992 for(i = 0; i < MV643XX_STATS_LEN; i++) {
2993 char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset;
2994 data[i] = (mv643xx_gstrings_stats[i].sizeof_stat ==
2995 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
2996 }
2997}
2998
2999static void
3000mv643xx_get_strings(struct net_device *netdev, uint32_t stringset, uint8_t *data)
3001{
3002 int i;
3003
3004 switch(stringset) {
3005 case ETH_SS_STATS:
3006 for (i=0; i < MV643XX_STATS_LEN; i++) {
3007 memcpy(data + i * ETH_GSTRING_LEN,
3008 mv643xx_gstrings_stats[i].stat_string,
3009 ETH_GSTRING_LEN);
3010 }
3011 break;
3012 }
3013}
3014
3015static struct ethtool_ops mv643xx_ethtool_ops = {
3016 .get_settings = mv643xx_get_settings,
3017 .get_drvinfo = mv643xx_get_drvinfo,
3018 .get_link = ethtool_op_get_link,
3019 .get_sg = ethtool_op_get_sg,
3020 .set_sg = ethtool_op_set_sg,
3021 .get_strings = mv643xx_get_strings,
3022 .get_stats_count = mv643xx_get_stats_count,
3023 .get_ethtool_stats = mv643xx_get_ethtool_stats,
3024};
3025
3026/************* End ethtool support *************************/
Linux kernel - Deliverables
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