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mv643xx_eth: allow multiple TX queues
[deliverable/linux.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
1da177e4
LT		 41#include <linux/tcp.h>
42#include <linux/udp.h>
43#include <linux/etherdevice.h>
1da177e4
LT		 44#include <linux/delay.h>
45#include <linux/ethtool.h>
d052d1be 46#include <linux/platform_device.h>
fbd6a754
LB		 47#include <linux/module.h>
48#include <linux/kernel.h>
49#include <linux/spinlock.h>
50#include <linux/workqueue.h>
51#include <linux/mii.h>
fbd6a754 52#include <linux/mv643xx_eth.h>
1da177e4
LT		 53#include <asm/io.h>
54#include <asm/types.h>
1da177e4 55#include <asm/system.h>
fbd6a754 56
e5371493
LB		 57static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58static char mv643xx_eth_driver_version[] = "1.0";
c9df406f 59
e5371493
LB		 60#define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61#define MV643XX_ETH_NAPI
62#define MV643XX_ETH_TX_FAST_REFILL
fbd6a754 63
e5371493 64#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
fbd6a754
LB		 65#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
66#else
67#define MAX_DESCS_PER_SKB 1
68#endif
69
fbd6a754
LB		 70/*
71 * Registers shared between all ports.
72 */
3cb4667c
LB		 73#define PHY_ADDR 0x0000
74#define SMI_REG 0x0004
75#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78#define WINDOW_BAR_ENABLE 0x0290
79#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 80
81/*
82 * Per-port registers.
83 */
3cb4667c 84#define PORT_CONFIG(p) (0x0400 + ((p) << 10))
d9a073ea 85#define UNICAST_PROMISCUOUS_MODE 0x00000001
3cb4667c
LB		 86#define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
87#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
88#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
89#define SDMA_CONFIG(p) (0x041c + ((p) << 10))
90#define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
91#define PORT_STATUS(p) (0x0444 + ((p) << 10))
a2a41689 92#define TX_FIFO_EMPTY 0x00000400
3cb4667c 93#define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
89df5fdc
LB		 94#define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
95#define TX_BW_RATE(p) (0x0450 + ((p) << 10))
3cb4667c 96#define TX_BW_MTU(p) (0x0458 + ((p) << 10))
89df5fdc 97#define TX_BW_BURST(p) (0x045c + ((p) << 10))
3cb4667c 98#define INT_CAUSE(p) (0x0460 + ((p) << 10))
64da80a2 99#define INT_RX 0x0007fbfc
073a345c 100#define INT_EXT 0x00000002
3cb4667c 101#define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
073a345c
LB		 102#define INT_EXT_LINK 0x00100000
103#define INT_EXT_PHY 0x00010000
104#define INT_EXT_TX_ERROR_0 0x00000100
105#define INT_EXT_TX_0 0x00000001
3d6b35bc 106#define INT_EXT_TX 0x0000ffff
3cb4667c
LB		 107#define INT_MASK(p) (0x0468 + ((p) << 10))
108#define INT_MASK_EXT(p) (0x046c + ((p) << 10))
109#define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
64da80a2 110#define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
3cb4667c 111#define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
3d6b35bc
LB		 112#define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
113#define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
114#define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
115#define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
3cb4667c
LB		 116#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
117#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
118#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
119#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 120
2679a550
LB		 121
122/*
123 * SDMA configuration register.
124 */
fbd6a754 125#define RX_BURST_SIZE_4_64BIT (2 << 1)
fbd6a754 126#define BLM_RX_NO_SWAP (1 << 4)
fbd6a754 127#define BLM_TX_NO_SWAP (1 << 5)
fbd6a754 128#define TX_BURST_SIZE_4_64BIT (2 << 22)
fbd6a754
LB		 129
130#if defined(__BIG_ENDIAN)
131#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
132 RX_BURST_SIZE_4_64BIT | \
fbd6a754
LB		 133 TX_BURST_SIZE_4_64BIT
134#elif defined(__LITTLE_ENDIAN)
135#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
136 RX_BURST_SIZE_4_64BIT | \
137 BLM_RX_NO_SWAP | \
138 BLM_TX_NO_SWAP | \
fbd6a754
LB		 139 TX_BURST_SIZE_4_64BIT
140#else
141#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
142#endif
143
2beff77b
LB		 144
145/*
146 * Port serial control register.
147 */
148#define SET_MII_SPEED_TO_100 (1 << 24)
149#define SET_GMII_SPEED_TO_1000 (1 << 23)
150#define SET_FULL_DUPLEX_MODE (1 << 21)
fbd6a754 151#define MAX_RX_PACKET_1522BYTE (1 << 17)
fbd6a754
LB		 152#define MAX_RX_PACKET_9700BYTE (5 << 17)
153#define MAX_RX_PACKET_MASK (7 << 17)
2beff77b
LB		 154#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
155#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
156#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
157#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
158#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
159#define FORCE_LINK_PASS (1 << 1)
160#define SERIAL_PORT_ENABLE (1 << 0)
fbd6a754 161
cc9754b3
LB		 162#define DEFAULT_RX_QUEUE_SIZE 400
163#define DEFAULT_TX_QUEUE_SIZE 800
fbd6a754 164
fbd6a754 165
7ca72a3b
LB		 166/*
167 * RX/TX descriptors.
fbd6a754
LB		 168 */
169#if defined(__BIG_ENDIAN)
cc9754b3 170struct rx_desc {
fbd6a754
LB		 171 u16 byte_cnt; /* Descriptor buffer byte count */
172 u16 buf_size; /* Buffer size */
173 u32 cmd_sts; /* Descriptor command status */
174 u32 next_desc_ptr; /* Next descriptor pointer */
175 u32 buf_ptr; /* Descriptor buffer pointer */
176};
177
cc9754b3 178struct tx_desc {
fbd6a754
LB		 179 u16 byte_cnt; /* buffer byte count */
180 u16 l4i_chk; /* CPU provided TCP checksum */
181 u32 cmd_sts; /* Command/status field */
182 u32 next_desc_ptr; /* Pointer to next descriptor */
183 u32 buf_ptr; /* pointer to buffer for this descriptor*/
184};
185#elif defined(__LITTLE_ENDIAN)
cc9754b3 186struct rx_desc {
fbd6a754
LB		 187 u32 cmd_sts; /* Descriptor command status */
188 u16 buf_size; /* Buffer size */
189 u16 byte_cnt; /* Descriptor buffer byte count */
190 u32 buf_ptr; /* Descriptor buffer pointer */
191 u32 next_desc_ptr; /* Next descriptor pointer */
192};
193
cc9754b3 194struct tx_desc {
fbd6a754
LB		 195 u32 cmd_sts; /* Command/status field */
196 u16 l4i_chk; /* CPU provided TCP checksum */
197 u16 byte_cnt; /* buffer byte count */
198 u32 buf_ptr; /* pointer to buffer for this descriptor*/
199 u32 next_desc_ptr; /* Pointer to next descriptor */
200};
201#else
202#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
203#endif
204
7ca72a3b 205/* RX & TX descriptor command */
cc9754b3 206#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 207
208/* RX & TX descriptor status */
cc9754b3 209#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 210
211/* RX descriptor status */
cc9754b3
LB		 212#define LAYER_4_CHECKSUM_OK 0x40000000
213#define RX_ENABLE_INTERRUPT 0x20000000
214#define RX_FIRST_DESC 0x08000000
215#define RX_LAST_DESC 0x04000000
7ca72a3b
LB		 216
217/* TX descriptor command */
cc9754b3
LB		 218#define TX_ENABLE_INTERRUPT 0x00800000
219#define GEN_CRC 0x00400000
220#define TX_FIRST_DESC 0x00200000
221#define TX_LAST_DESC 0x00100000
222#define ZERO_PADDING 0x00080000
223#define GEN_IP_V4_CHECKSUM 0x00040000
224#define GEN_TCP_UDP_CHECKSUM 0x00020000
225#define UDP_FRAME 0x00010000
7ca72a3b 226
cc9754b3 227#define TX_IHL_SHIFT 11
7ca72a3b
LB		 228
229
c9df406f 230/* global *******************************************************************/
e5371493 231struct mv643xx_eth_shared_private {
fc32b0e2
LB		 232 /*
233 * Ethernet controller base address.
234 */
cc9754b3 235 void __iomem *base;
c9df406f 236
fc32b0e2
LB		 237 /*
238 * Protects access to SMI_REG, which is shared between ports.
239 */
c9df406f
LB		 240 spinlock_t phy_lock;
241
fc32b0e2
LB		 242 /*
243 * Per-port MBUS window access register value.
244 */
c9df406f
LB		 245 u32 win_protect;
246
fc32b0e2
LB		 247 /*
248 * Hardware-specific parameters.
249 */
c9df406f
LB		 250 unsigned int t_clk;
251};
252
253
254/* per-port *****************************************************************/
e5371493 255struct mib_counters {
fbd6a754
LB		 256 u64 good_octets_received;
257 u32 bad_octets_received;
258 u32 internal_mac_transmit_err;
259 u32 good_frames_received;
260 u32 bad_frames_received;
261 u32 broadcast_frames_received;
262 u32 multicast_frames_received;
263 u32 frames_64_octets;
264 u32 frames_65_to_127_octets;
265 u32 frames_128_to_255_octets;
266 u32 frames_256_to_511_octets;
267 u32 frames_512_to_1023_octets;
268 u32 frames_1024_to_max_octets;
269 u64 good_octets_sent;
270 u32 good_frames_sent;
271 u32 excessive_collision;
272 u32 multicast_frames_sent;
273 u32 broadcast_frames_sent;
274 u32 unrec_mac_control_received;
275 u32 fc_sent;
276 u32 good_fc_received;
277 u32 bad_fc_received;
278 u32 undersize_received;
279 u32 fragments_received;
280 u32 oversize_received;
281 u32 jabber_received;
282 u32 mac_receive_error;
283 u32 bad_crc_event;
284 u32 collision;
285 u32 late_collision;
286};
287
8a578111 288struct rx_queue {
64da80a2
LB		 289 int index;
290
8a578111
LB		 291 int rx_ring_size;
292
293 int rx_desc_count;
294 int rx_curr_desc;
295 int rx_used_desc;
296
297 struct rx_desc *rx_desc_area;
298 dma_addr_t rx_desc_dma;
299 int rx_desc_area_size;
300 struct sk_buff **rx_skb;
301
302 struct timer_list rx_oom;
303};
304
13d64285 305struct tx_queue {
3d6b35bc
LB		 306 int index;
307
13d64285 308 int tx_ring_size;
fbd6a754 309
13d64285
LB		 310 int tx_desc_count;
311 int tx_curr_desc;
312 int tx_used_desc;
fbd6a754 313
5daffe94 314 struct tx_desc *tx_desc_area;
fbd6a754
LB		 315 dma_addr_t tx_desc_dma;
316 int tx_desc_area_size;
317 struct sk_buff **tx_skb;
13d64285
LB		 318};
319
320struct mv643xx_eth_private {
321 struct mv643xx_eth_shared_private *shared;
fc32b0e2 322 int port_num;
13d64285 323
fc32b0e2 324 struct net_device *dev;
fbd6a754 325
fc32b0e2
LB		 326 struct mv643xx_eth_shared_private *shared_smi;
327 int phy_addr;
fbd6a754 328
fbd6a754 329 spinlock_t lock;
fbd6a754 330
fc32b0e2
LB		 331 struct mib_counters mib_counters;
332 struct work_struct tx_timeout_task;
fbd6a754 333 struct mii_if_info mii;
8a578111
LB		 334
335 /*
336 * RX state.
337 */
338 int default_rx_ring_size;
339 unsigned long rx_desc_sram_addr;
340 int rx_desc_sram_size;
64da80a2
LB		 341 u8 rxq_mask;
342 int rxq_primary;
8a578111 343 struct napi_struct napi;
64da80a2 344 struct rx_queue rxq[8];
13d64285
LB		 345
346 /*
347 * TX state.
348 */
349 int default_tx_ring_size;
350 unsigned long tx_desc_sram_addr;
351 int tx_desc_sram_size;
3d6b35bc
LB		 352 u8 txq_mask;
353 int txq_primary;
354 struct tx_queue txq[8];
13d64285
LB		 355#ifdef MV643XX_ETH_TX_FAST_REFILL
356 int tx_clean_threshold;
357#endif
fbd6a754 358};
1da177e4 359
fbd6a754 360
c9df406f 361/* port register accessors **************************************************/
e5371493 362static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 363{
cc9754b3 364 return readl(mp->shared->base + offset);
c9df406f 365}
fbd6a754 366
e5371493 367static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 368{
cc9754b3 369 writel(data, mp->shared->base + offset);
c9df406f 370}
fbd6a754 371
fbd6a754 372
c9df406f 373/* rxq/txq helper functions *************************************************/
8a578111 374static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 375{
64da80a2 376 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 377}
fbd6a754 378
13d64285
LB		 379static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
380{
3d6b35bc 381 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 382}
383
8a578111 384static void rxq_enable(struct rx_queue *rxq)
c9df406f 385{
8a578111 386 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 387 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
8a578111 388}
1da177e4 389
8a578111
LB		 390static void rxq_disable(struct rx_queue *rxq)
391{
392 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 393 u8 mask = 1 << rxq->index;
1da177e4 394
8a578111
LB		 395 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
396 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
397 udelay(10);
c9df406f
LB		 398}
399
13d64285 400static void txq_enable(struct tx_queue *txq)
1da177e4 401{
13d64285 402 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 403 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
1da177e4
LT		 404}
405
13d64285 406static void txq_disable(struct tx_queue *txq)
1da177e4 407{
13d64285 408 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 409 u8 mask = 1 << txq->index;
c9df406f 410
13d64285
LB		 411 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
412 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
413 udelay(10);
414}
415
416static void __txq_maybe_wake(struct tx_queue *txq)
417{
418 struct mv643xx_eth_private *mp = txq_to_mp(txq);
419
3d6b35bc
LB		 420 /*
421 * netif_{stop,wake}_queue() flow control only applies to
422 * the primary queue.
423 */
424 BUG_ON(txq->index != mp->txq_primary);
425
13d64285
LB		 426 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB)
427 netif_wake_queue(mp->dev);
1da177e4
LT		 428}
429
c9df406f
LB		 430
431/* rx ***********************************************************************/
13d64285 432static void txq_reclaim(struct tx_queue *txq, int force);
c9df406f 433
8a578111 434static void rxq_refill(struct rx_queue *rxq)
1da177e4 435{
8a578111 436 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
c9df406f 437 unsigned long flags;
1da177e4 438
c9df406f 439 spin_lock_irqsave(&mp->lock, flags);
c0d0f2ca 440
8a578111
LB		 441 while (rxq->rx_desc_count < rxq->rx_ring_size) {
442 int skb_size;
de34f225
LB		 443 struct sk_buff *skb;
444 int unaligned;
445 int rx;
446
8a578111
LB		 447 /*
448 * Reserve 2+14 bytes for an ethernet header (the
449 * hardware automatically prepends 2 bytes of dummy
450 * data to each received packet), 4 bytes for a VLAN
451 * header, and 4 bytes for the trailing FCS -- 24
452 * bytes total.
453 */
454 skb_size = mp->dev->mtu + 24;
455
456 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
de34f225 457 if (skb == NULL)
1da177e4 458 break;
de34f225 459
908b637f 460 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
b44cd572 461 if (unaligned)
908b637f 462 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
de34f225 463
8a578111
LB		 464 rxq->rx_desc_count++;
465 rx = rxq->rx_used_desc;
466 rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size;
de34f225 467
8a578111
LB		 468 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
469 skb_size, DMA_FROM_DEVICE);
470 rxq->rx_desc_area[rx].buf_size = skb_size;
471 rxq->rx_skb[rx] = skb;
de34f225 472 wmb();
8a578111 473 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
de34f225
LB		 474 RX_ENABLE_INTERRUPT;
475 wmb();
476
fc32b0e2
LB		 477 /*
478 * The hardware automatically prepends 2 bytes of
479 * dummy data to each received packet, so that the
480 * IP header ends up 16-byte aligned.
481 */
482 skb_reserve(skb, 2);
1da177e4 483 }
de34f225 484
8a578111
LB		 485 if (rxq->rx_desc_count == 0) {
486 rxq->rx_oom.expires = jiffies + (HZ / 10);
487 add_timer(&rxq->rx_oom);
1da177e4 488 }
de34f225
LB		 489
490 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4
LT		 491}
492
8a578111 493static inline void rxq_refill_timer_wrapper(unsigned long data)
1da177e4 494{
8a578111 495 rxq_refill((struct rx_queue *)data);
1da177e4
LT		 496}
497
8a578111 498static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 499{
8a578111
LB		 500 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
501 struct net_device_stats *stats = &mp->dev->stats;
502 int rx;
1da177e4 503
8a578111
LB		 504 rx = 0;
505 while (rx < budget) {
fc32b0e2 506 struct rx_desc *rx_desc;
96587661 507 unsigned int cmd_sts;
fc32b0e2 508 struct sk_buff *skb;
96587661 509 unsigned long flags;
d344bff9 510
96587661 511 spin_lock_irqsave(&mp->lock, flags);
ff561eef 512
8a578111 513 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 514
96587661
LB		 515 cmd_sts = rx_desc->cmd_sts;
516 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
517 spin_unlock_irqrestore(&mp->lock, flags);
518 break;
519 }
520 rmb();
1da177e4 521
8a578111
LB		 522 skb = rxq->rx_skb[rxq->rx_curr_desc];
523 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 524
8a578111 525 rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size;
ff561eef 526
96587661 527 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 528
fc32b0e2
LB		 529 dma_unmap_single(NULL, rx_desc->buf_ptr + 2,
530 mp->dev->mtu + 24, DMA_FROM_DEVICE);
8a578111
LB		 531 rxq->rx_desc_count--;
532 rx++;
b1dd9ca1 533
468d09f8
DF		 534 /*
535 * Update statistics.
fc32b0e2
LB		 536 *
537 * Note that the descriptor byte count includes 2 dummy
538 * bytes automatically inserted by the hardware at the
539 * start of the packet (which we don't count), and a 4
540 * byte CRC at the end of the packet (which we do count).
468d09f8 541 */
1da177e4 542 stats->rx_packets++;
fc32b0e2 543 stats->rx_bytes += rx_desc->byte_cnt - 2;
96587661 544
1da177e4 545 /*
fc32b0e2
LB		 546 * In case we received a packet without first / last bits
547 * on, or the error summary bit is set, the packet needs
548 * to be dropped.
1da177e4 549 */
96587661 550 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 551 (RX_FIRST_DESC | RX_LAST_DESC))
96587661 552 || (cmd_sts & ERROR_SUMMARY)) {
1da177e4 553 stats->rx_dropped++;
fc32b0e2 554
96587661 555 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 556 (RX_FIRST_DESC | RX_LAST_DESC)) {
1da177e4 557 if (net_ratelimit())
fc32b0e2
LB		 558 dev_printk(KERN_ERR, &mp->dev->dev,
559 "received packet spanning "
560 "multiple descriptors\n");
1da177e4 561 }
fc32b0e2 562
96587661 563 if (cmd_sts & ERROR_SUMMARY)
1da177e4
LT		 564 stats->rx_errors++;
565
566 dev_kfree_skb_irq(skb);
567 } else {
568 /*
569 * The -4 is for the CRC in the trailer of the
570 * received packet
571 */
fc32b0e2 572 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
1da177e4 573
96587661 574 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
1da177e4
LT		 575 skb->ip_summed = CHECKSUM_UNNECESSARY;
576 skb->csum = htons(
96587661 577 (cmd_sts & 0x0007fff8) >> 3);
1da177e4 578 }
8a578111 579 skb->protocol = eth_type_trans(skb, mp->dev);
e5371493 580#ifdef MV643XX_ETH_NAPI
1da177e4
LT		 581 netif_receive_skb(skb);
582#else
583 netif_rx(skb);
584#endif
585 }
fc32b0e2 586
8a578111 587 mp->dev->last_rx = jiffies;
1da177e4 588 }
fc32b0e2 589
8a578111 590 rxq_refill(rxq);
1da177e4 591
8a578111 592 return rx;
1da177e4
LT		 593}
594
e5371493 595#ifdef MV643XX_ETH_NAPI
e5371493 596static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
d0412d96 597{
8a578111
LB		 598 struct mv643xx_eth_private *mp;
599 int rx;
64da80a2 600 int i;
8a578111
LB		 601
602 mp = container_of(napi, struct mv643xx_eth_private, napi);
d0412d96 603
e5371493 604#ifdef MV643XX_ETH_TX_FAST_REFILL
c9df406f 605 if (++mp->tx_clean_threshold > 5) {
c9df406f 606 mp->tx_clean_threshold = 0;
3d6b35bc
LB		 607 for (i = 0; i < 8; i++)
608 if (mp->txq_mask & (1 << i))
609 txq_reclaim(mp->txq + i, 0);
d0412d96 610 }
c9df406f 611#endif
d0412d96 612
64da80a2
LB		 613 rx = 0;
614 for (i = 7; rx < budget && i >= 0; i--)
615 if (mp->rxq_mask & (1 << i))
616 rx += rxq_process(mp->rxq + i, budget - rx);
d0412d96 617
8a578111
LB		 618 if (rx < budget) {
619 netif_rx_complete(mp->dev, napi);
620 wrl(mp, INT_CAUSE(mp->port_num), 0);
621 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
622 wrl(mp, INT_MASK(mp->port_num), INT_RX | INT_EXT);
d0412d96 623 }
c9df406f 624
8a578111 625 return rx;
d0412d96 626}
c9df406f 627#endif
d0412d96 628
c9df406f
LB		 629
630/* tx ***********************************************************************/
c9df406f 631static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 632{
13d64285 633 int frag;
1da177e4 634
c9df406f 635 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
13d64285
LB		 636 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
637 if (fragp->size <= 8 && fragp->page_offset & 7)
c9df406f 638 return 1;
1da177e4 639 }
13d64285 640
c9df406f
LB		 641 return 0;
642}
7303fde8 643
13d64285 644static int txq_alloc_desc_index(struct tx_queue *txq)
c9df406f
LB		 645{
646 int tx_desc_curr;
d0412d96 647
13d64285 648 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
1da177e4 649
13d64285
LB		 650 tx_desc_curr = txq->tx_curr_desc;
651 txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size;
e4d00fa9 652
13d64285 653 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
468d09f8 654
c9df406f
LB		 655 return tx_desc_curr;
656}
468d09f8 657
13d64285 658static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 659{
13d64285 660 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 661 int frag;
1da177e4 662
13d64285
LB		 663 for (frag = 0; frag < nr_frags; frag++) {
664 skb_frag_t *this_frag;
665 int tx_index;
666 struct tx_desc *desc;
667
668 this_frag = &skb_shinfo(skb)->frags[frag];
669 tx_index = txq_alloc_desc_index(txq);
670 desc = &txq->tx_desc_area[tx_index];
671
672 /*
673 * The last fragment will generate an interrupt
674 * which will free the skb on TX completion.
675 */
676 if (frag == nr_frags - 1) {
677 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
678 ZERO_PADDING | TX_LAST_DESC |
679 TX_ENABLE_INTERRUPT;
680 txq->tx_skb[tx_index] = skb;
681 } else {
682 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
683 txq->tx_skb[tx_index] = NULL;
684 }
685
c9df406f
LB		 686 desc->l4i_chk = 0;
687 desc->byte_cnt = this_frag->size;
688 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
689 this_frag->page_offset,
690 this_frag->size,
691 DMA_TO_DEVICE);
692 }
1da177e4
LT		 693}
694
c9df406f
LB		 695static inline __be16 sum16_as_be(__sum16 sum)
696{
697 return (__force __be16)sum;
698}
1da177e4 699
13d64285 700static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 701{
13d64285 702 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 703 int tx_index;
cc9754b3 704 struct tx_desc *desc;
c9df406f
LB		 705 u32 cmd_sts;
706 int length;
1da177e4 707
cc9754b3 708 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
1da177e4 709
13d64285
LB		 710 tx_index = txq_alloc_desc_index(txq);
711 desc = &txq->tx_desc_area[tx_index];
c9df406f
LB		 712
713 if (nr_frags) {
13d64285 714 txq_submit_frag_skb(txq, skb);
c9df406f
LB		 715
716 length = skb_headlen(skb);
13d64285 717 txq->tx_skb[tx_index] = NULL;
c9df406f 718 } else {
cc9754b3 719 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
c9df406f 720 length = skb->len;
13d64285 721 txq->tx_skb[tx_index] = skb;
c9df406f
LB		 722 }
723
724 desc->byte_cnt = length;
725 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
726
727 if (skb->ip_summed == CHECKSUM_PARTIAL) {
728 BUG_ON(skb->protocol != htons(ETH_P_IP));
729
cc9754b3
LB		 730 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
731 GEN_IP_V4_CHECKSUM |
732 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
c9df406f
LB		 733
734 switch (ip_hdr(skb)->protocol) {
735 case IPPROTO_UDP:
cc9754b3 736 cmd_sts |= UDP_FRAME;
c9df406f
LB		 737 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
738 break;
739 case IPPROTO_TCP:
740 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
741 break;
742 default:
743 BUG();
744 }
745 } else {
746 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 747 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 748 desc->l4i_chk = 0;
749 }
750
751 /* ensure all other descriptors are written before first cmd_sts */
752 wmb();
753 desc->cmd_sts = cmd_sts;
754
755 /* ensure all descriptors are written before poking hardware */
756 wmb();
13d64285 757 txq_enable(txq);
c9df406f 758
13d64285 759 txq->tx_desc_count += nr_frags + 1;
1da177e4 760}
1da177e4 761
fc32b0e2 762static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 763{
e5371493 764 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 765 struct net_device_stats *stats = &dev->stats;
13d64285 766 struct tx_queue *txq;
c9df406f 767 unsigned long flags;
afdb57a2 768
c9df406f
LB		 769 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
770 stats->tx_dropped++;
fc32b0e2
LB		 771 dev_printk(KERN_DEBUG, &dev->dev,
772 "failed to linearize skb with tiny "
773 "unaligned fragment\n");
c9df406f
LB		 774 return NETDEV_TX_BUSY;
775 }
776
777 spin_lock_irqsave(&mp->lock, flags);
778
3d6b35bc 779 txq = mp->txq + mp->txq_primary;
13d64285
LB		 780
781 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) {
c9df406f 782 spin_unlock_irqrestore(&mp->lock, flags);
3d6b35bc
LB		 783 if (txq->index == mp->txq_primary && net_ratelimit())
784 dev_printk(KERN_ERR, &dev->dev,
785 "primary tx queue full?!\n");
786 kfree_skb(skb);
787 return NETDEV_TX_OK;
c9df406f
LB		 788 }
789
13d64285 790 txq_submit_skb(txq, skb);
c9df406f
LB		 791 stats->tx_bytes += skb->len;
792 stats->tx_packets++;
793 dev->trans_start = jiffies;
794
3d6b35bc
LB		 795 if (txq->index == mp->txq_primary) {
796 int entries_left;
797
798 entries_left = txq->tx_ring_size - txq->tx_desc_count;
799 if (entries_left < MAX_DESCS_PER_SKB)
800 netif_stop_queue(dev);
801 }
c9df406f
LB		 802
803 spin_unlock_irqrestore(&mp->lock, flags);
804
805 return NETDEV_TX_OK;
1da177e4
LT		 806}
807
c9df406f 808
89df5fdc
LB		 809/* tx rate control **********************************************************/
810/*
811 * Set total maximum TX rate (shared by all TX queues for this port)
812 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
813 */
814static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
815{
816 int token_rate;
817 int mtu;
818 int bucket_size;
819
820 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
821 if (token_rate > 1023)
822 token_rate = 1023;
823
824 mtu = (mp->dev->mtu + 255) >> 8;
825 if (mtu > 63)
826 mtu = 63;
827
828 bucket_size = (burst + 255) >> 8;
829 if (bucket_size > 65535)
830 bucket_size = 65535;
831
832 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
833 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
834 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
835}
836
837static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
838{
839 struct mv643xx_eth_private *mp = txq_to_mp(txq);
840 int token_rate;
841 int bucket_size;
842
843 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
844 if (token_rate > 1023)
845 token_rate = 1023;
846
847 bucket_size = (burst + 255) >> 8;
848 if (bucket_size > 65535)
849 bucket_size = 65535;
850
3d6b35bc
LB		 851 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
852 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
89df5fdc
LB		 853 (bucket_size << 10) | token_rate);
854}
855
856static void txq_set_fixed_prio_mode(struct tx_queue *txq)
857{
858 struct mv643xx_eth_private *mp = txq_to_mp(txq);
859 int off;
860 u32 val;
861
862 /*
863 * Turn on fixed priority mode.
864 */
865 off = TXQ_FIX_PRIO_CONF(mp->port_num);
866
867 val = rdl(mp, off);
3d6b35bc 868 val |= 1 << txq->index;
89df5fdc
LB		 869 wrl(mp, off, val);
870}
871
872static void txq_set_wrr(struct tx_queue *txq, int weight)
873{
874 struct mv643xx_eth_private *mp = txq_to_mp(txq);
875 int off;
876 u32 val;
877
878 /*
879 * Turn off fixed priority mode.
880 */
881 off = TXQ_FIX_PRIO_CONF(mp->port_num);
882
883 val = rdl(mp, off);
3d6b35bc 884 val &= ~(1 << txq->index);
89df5fdc
LB		 885 wrl(mp, off, val);
886
887 /*
888 * Configure WRR weight for this queue.
889 */
3d6b35bc 890 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
89df5fdc
LB		 891
892 val = rdl(mp, off);
893 val = (val & ~0xff) | (weight & 0xff);
894 wrl(mp, off, val);
895}
896
897
c9df406f 898/* mii management interface *************************************************/
fc32b0e2
LB		 899#define SMI_BUSY 0x10000000
900#define SMI_READ_VALID 0x08000000
901#define SMI_OPCODE_READ 0x04000000
902#define SMI_OPCODE_WRITE 0x00000000
c9df406f 903
fc32b0e2
LB		 904static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr,
905 unsigned int reg, unsigned int *value)
1da177e4 906{
cc9754b3 907 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
c9df406f 908 unsigned long flags;
1da177e4
LT		 909 int i;
910
c9df406f
LB		 911 /* the SMI register is a shared resource */
912 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
913
914 /* wait for the SMI register to become available */
cc9754b3 915 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
e1bea50a 916 if (i == 1000) {
c9df406f
LB		 917 printk("%s: PHY busy timeout\n", mp->dev->name);
918 goto out;
919 }
e1bea50a 920 udelay(10);
1da177e4
LT		 921 }
922
fc32b0e2 923 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 924
c9df406f 925 /* now wait for the data to be valid */
cc9754b3 926 for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
e1bea50a 927 if (i == 1000) {
c9df406f
LB		 928 printk("%s: PHY read timeout\n", mp->dev->name);
929 goto out;
930 }
e1bea50a 931 udelay(10);
c9df406f
LB		 932 }
933
934 *value = readl(smi_reg) & 0xffff;
935out:
936 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1da177e4
LT		 937}
938
fc32b0e2
LB		 939static void smi_reg_write(struct mv643xx_eth_private *mp,
940 unsigned int addr,
941 unsigned int reg, unsigned int value)
1da177e4 942{
cc9754b3 943 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
c9df406f 944 unsigned long flags;
1da177e4
LT		 945 int i;
946
c9df406f
LB		 947 /* the SMI register is a shared resource */
948 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
949
950 /* wait for the SMI register to become available */
cc9754b3 951 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
e1bea50a 952 if (i == 1000) {
c9df406f
LB		 953 printk("%s: PHY busy timeout\n", mp->dev->name);
954 goto out;
955 }
e1bea50a 956 udelay(10);
1da177e4
LT		 957 }
958
fc32b0e2
LB		 959 writel(SMI_OPCODE_WRITE | (reg << 21) |
960 (addr << 16) | (value & 0xffff), smi_reg);
c9df406f
LB		 961out:
962 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
963}
1da177e4 964
c9df406f
LB		 965
966/* mib counters *************************************************************/
fc32b0e2 967static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 968{
fc32b0e2 969 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 970}
971
fc32b0e2 972static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 973{
fc32b0e2
LB		 974 int i;
975
976 for (i = 0; i < 0x80; i += 4)
977 mib_read(mp, i);
c9df406f 978}
d0412d96 979
fc32b0e2 980static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 981{
e5371493 982 struct mib_counters *p = &mp->mib_counters;
4b8e3655 983
fc32b0e2
LB		 984 p->good_octets_received += mib_read(mp, 0x00);
985 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
986 p->bad_octets_received += mib_read(mp, 0x08);
987 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
988 p->good_frames_received += mib_read(mp, 0x10);
989 p->bad_frames_received += mib_read(mp, 0x14);
990 p->broadcast_frames_received += mib_read(mp, 0x18);
991 p->multicast_frames_received += mib_read(mp, 0x1c);
992 p->frames_64_octets += mib_read(mp, 0x20);
993 p->frames_65_to_127_octets += mib_read(mp, 0x24);
994 p->frames_128_to_255_octets += mib_read(mp, 0x28);
995 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
996 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
997 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
998 p->good_octets_sent += mib_read(mp, 0x38);
999 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1000 p->good_frames_sent += mib_read(mp, 0x40);
1001 p->excessive_collision += mib_read(mp, 0x44);
1002 p->multicast_frames_sent += mib_read(mp, 0x48);
1003 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1004 p->unrec_mac_control_received += mib_read(mp, 0x50);
1005 p->fc_sent += mib_read(mp, 0x54);
1006 p->good_fc_received += mib_read(mp, 0x58);
1007 p->bad_fc_received += mib_read(mp, 0x5c);
1008 p->undersize_received += mib_read(mp, 0x60);
1009 p->fragments_received += mib_read(mp, 0x64);
1010 p->oversize_received += mib_read(mp, 0x68);
1011 p->jabber_received += mib_read(mp, 0x6c);
1012 p->mac_receive_error += mib_read(mp, 0x70);
1013 p->bad_crc_event += mib_read(mp, 0x74);
1014 p->collision += mib_read(mp, 0x78);
1015 p->late_collision += mib_read(mp, 0x7c);
d0412d96
JC		 1016}
1017
c9df406f
LB		 1018
1019/* ethtool ******************************************************************/
e5371493 1020struct mv643xx_eth_stats {
c9df406f
LB		 1021 char stat_string[ETH_GSTRING_LEN];
1022 int sizeof_stat;
16820054
LB		 1023 int netdev_off;
1024 int mp_off;
c9df406f
LB		 1025};
1026
16820054
LB		 1027#define SSTAT(m) \
1028 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1029 offsetof(struct net_device, stats.m), -1 }
1030
1031#define MIBSTAT(m) \
1032 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1033 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1034
1035static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1036 SSTAT(rx_packets),
1037 SSTAT(tx_packets),
1038 SSTAT(rx_bytes),
1039 SSTAT(tx_bytes),
1040 SSTAT(rx_errors),
1041 SSTAT(tx_errors),
1042 SSTAT(rx_dropped),
1043 SSTAT(tx_dropped),
1044 MIBSTAT(good_octets_received),
1045 MIBSTAT(bad_octets_received),
1046 MIBSTAT(internal_mac_transmit_err),
1047 MIBSTAT(good_frames_received),
1048 MIBSTAT(bad_frames_received),
1049 MIBSTAT(broadcast_frames_received),
1050 MIBSTAT(multicast_frames_received),
1051 MIBSTAT(frames_64_octets),
1052 MIBSTAT(frames_65_to_127_octets),
1053 MIBSTAT(frames_128_to_255_octets),
1054 MIBSTAT(frames_256_to_511_octets),
1055 MIBSTAT(frames_512_to_1023_octets),
1056 MIBSTAT(frames_1024_to_max_octets),
1057 MIBSTAT(good_octets_sent),
1058 MIBSTAT(good_frames_sent),
1059 MIBSTAT(excessive_collision),
1060 MIBSTAT(multicast_frames_sent),
1061 MIBSTAT(broadcast_frames_sent),
1062 MIBSTAT(unrec_mac_control_received),
1063 MIBSTAT(fc_sent),
1064 MIBSTAT(good_fc_received),
1065 MIBSTAT(bad_fc_received),
1066 MIBSTAT(undersize_received),
1067 MIBSTAT(fragments_received),
1068 MIBSTAT(oversize_received),
1069 MIBSTAT(jabber_received),
1070 MIBSTAT(mac_receive_error),
1071 MIBSTAT(bad_crc_event),
1072 MIBSTAT(collision),
1073 MIBSTAT(late_collision),
c9df406f
LB		 1074};
1075
e5371493 1076static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
d0412d96 1077{
e5371493 1078 struct mv643xx_eth_private *mp = netdev_priv(dev);
d0412d96
JC		 1079 int err;
1080
1081 spin_lock_irq(&mp->lock);
1082 err = mii_ethtool_gset(&mp->mii, cmd);
1083 spin_unlock_irq(&mp->lock);
1084
fc32b0e2
LB		 1085 /*
1086 * The MAC does not support 1000baseT_Half.
1087 */
d0412d96
JC		 1088 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1089 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1090
1091 return err;
1092}
1093
e5371493 1094static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1095{
e5371493 1096 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6
DF		 1097 int err;
1098
fc32b0e2
LB		 1099 /*
1100 * The MAC does not support 1000baseT_Half.
1101 */
1102 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1103
c9df406f
LB		 1104 spin_lock_irq(&mp->lock);
1105 err = mii_ethtool_sset(&mp->mii, cmd);
1106 spin_unlock_irq(&mp->lock);
85cf572c 1107
c9df406f
LB		 1108 return err;
1109}
1da177e4 1110
fc32b0e2
LB		 1111static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1112 struct ethtool_drvinfo *drvinfo)
c9df406f 1113{
e5371493
LB		 1114 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1115 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 1116 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 1117 strncpy(drvinfo->bus_info, "platform", 32);
16820054 1118 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1119}
1da177e4 1120
fc32b0e2 1121static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1122{
e5371493 1123 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1124
c9df406f
LB		 1125 return mii_nway_restart(&mp->mii);
1126}
1da177e4 1127
c9df406f
LB		 1128static u32 mv643xx_eth_get_link(struct net_device *dev)
1129{
e5371493 1130 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1131
c9df406f
LB		 1132 return mii_link_ok(&mp->mii);
1133}
1da177e4 1134
fc32b0e2
LB		 1135static void mv643xx_eth_get_strings(struct net_device *dev,
1136 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1137{
1138 int i;
1da177e4 1139
fc32b0e2
LB		 1140 if (stringset == ETH_SS_STATS) {
1141 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1142 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1143 mv643xx_eth_stats[i].stat_string,
e5371493 1144 ETH_GSTRING_LEN);
c9df406f 1145 }
c9df406f
LB		 1146 }
1147}
1da177e4 1148
fc32b0e2
LB		 1149static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1150 struct ethtool_stats *stats,
1151 uint64_t *data)
c9df406f 1152{
fc32b0e2 1153 struct mv643xx_eth_private *mp = dev->priv;
c9df406f 1154 int i;
1da177e4 1155
fc32b0e2 1156 mib_counters_update(mp);
1da177e4 1157
16820054
LB		 1158 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1159 const struct mv643xx_eth_stats *stat;
1160 void *p;
1161
1162 stat = mv643xx_eth_stats + i;
1163
1164 if (stat->netdev_off >= 0)
1165 p = ((void *)mp->dev) + stat->netdev_off;
1166 else
1167 p = ((void *)mp) + stat->mp_off;
1168
1169 data[i] = (stat->sizeof_stat == 8) ?
1170 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1171 }
c9df406f 1172}
1da177e4 1173
fc32b0e2 1174static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1175{
fc32b0e2 1176 if (sset == ETH_SS_STATS)
16820054 1177 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1178
1179 return -EOPNOTSUPP;
c9df406f 1180}
1da177e4 1181
e5371493 1182static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1183 .get_settings = mv643xx_eth_get_settings,
1184 .set_settings = mv643xx_eth_set_settings,
1185 .get_drvinfo = mv643xx_eth_get_drvinfo,
1186 .nway_reset = mv643xx_eth_nway_reset,
1187 .get_link = mv643xx_eth_get_link,
c9df406f 1188 .set_sg = ethtool_op_set_sg,
fc32b0e2
LB		 1189 .get_strings = mv643xx_eth_get_strings,
1190 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
e5371493 1191 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1192};
1da177e4 1193
bea3348e 1194
c9df406f 1195/* address handling *********************************************************/
5daffe94 1196static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1197{
c9df406f
LB		 1198 unsigned int mac_h;
1199 unsigned int mac_l;
1da177e4 1200
fc32b0e2
LB		 1201 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1202 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1da177e4 1203
5daffe94
LB		 1204 addr[0] = (mac_h >> 24) & 0xff;
1205 addr[1] = (mac_h >> 16) & 0xff;
1206 addr[2] = (mac_h >> 8) & 0xff;
1207 addr[3] = mac_h & 0xff;
1208 addr[4] = (mac_l >> 8) & 0xff;
1209 addr[5] = mac_l & 0xff;
c9df406f 1210}
1da177e4 1211
e5371493 1212static void init_mac_tables(struct mv643xx_eth_private *mp)
c9df406f 1213{
fc32b0e2 1214 int i;
1da177e4 1215
fc32b0e2
LB		 1216 for (i = 0; i < 0x100; i += 4) {
1217 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1218 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
c9df406f 1219 }
fc32b0e2
LB		 1220
1221 for (i = 0; i < 0x10; i += 4)
1222 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
c9df406f 1223}
d0412d96 1224
e5371493 1225static void set_filter_table_entry(struct mv643xx_eth_private *mp,
fc32b0e2 1226 int table, unsigned char entry)
c9df406f
LB		 1227{
1228 unsigned int table_reg;
ab4384a6 1229
c9df406f 1230 /* Set "accepts frame bit" at specified table entry */
fc32b0e2
LB		 1231 table_reg = rdl(mp, table + (entry & 0xfc));
1232 table_reg |= 0x01 << (8 * (entry & 3));
1233 wrl(mp, table + (entry & 0xfc), table_reg);
1da177e4
LT		 1234}
1235
5daffe94 1236static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1da177e4 1237{
c9df406f
LB		 1238 unsigned int mac_h;
1239 unsigned int mac_l;
1240 int table;
1da177e4 1241
fc32b0e2
LB		 1242 mac_l = (addr[4] << 8) | addr[5];
1243 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
ff561eef 1244
fc32b0e2
LB		 1245 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1246 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1da177e4 1247
fc32b0e2 1248 table = UNICAST_TABLE(mp->port_num);
5daffe94 1249 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1da177e4
LT		 1250}
1251
fc32b0e2 1252static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1da177e4 1253{
e5371493 1254 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1255
fc32b0e2
LB		 1256 /* +2 is for the offset of the HW addr type */
1257 memcpy(dev->dev_addr, addr + 2, 6);
1258
cc9754b3
LB		 1259 init_mac_tables(mp);
1260 uc_addr_set(mp, dev->dev_addr);
1da177e4
LT		 1261
1262 return 0;
1263}
1264
69876569
LB		 1265static int addr_crc(unsigned char *addr)
1266{
1267 int crc = 0;
1268 int i;
1269
1270 for (i = 0; i < 6; i++) {
1271 int j;
1272
1273 crc = (crc ^ addr[i]) << 8;
1274 for (j = 7; j >= 0; j--) {
1275 if (crc & (0x100 << j))
1276 crc ^= 0x107 << j;
1277 }
1278 }
1279
1280 return crc;
1281}
1282
fc32b0e2 1283static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1da177e4 1284{
fc32b0e2
LB		 1285 struct mv643xx_eth_private *mp = netdev_priv(dev);
1286 u32 port_config;
1287 struct dev_addr_list *addr;
1288 int i;
c8aaea25 1289
fc32b0e2
LB		 1290 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1291 if (dev->flags & IFF_PROMISC)
1292 port_config |= UNICAST_PROMISCUOUS_MODE;
1293 else
1294 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1295 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1da177e4 1296
fc32b0e2
LB		 1297 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1298 int port_num = mp->port_num;
1299 u32 accept = 0x01010101;
c8aaea25 1300
fc32b0e2
LB		 1301 for (i = 0; i < 0x100; i += 4) {
1302 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1303 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1304 }
1305 return;
1306 }
c8aaea25 1307
fc32b0e2
LB		 1308 for (i = 0; i < 0x100; i += 4) {
1309 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1310 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1da177e4
LT		 1311 }
1312
fc32b0e2
LB		 1313 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1314 u8 *a = addr->da_addr;
1315 int table;
324ff2c1 1316
fc32b0e2
LB		 1317 if (addr->da_addrlen != 6)
1318 continue;
1da177e4 1319
fc32b0e2
LB		 1320 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1321 table = SPECIAL_MCAST_TABLE(mp->port_num);
1322 set_filter_table_entry(mp, table, a[5]);
1323 } else {
1324 int crc = addr_crc(a);
1da177e4 1325
fc32b0e2
LB		 1326 table = OTHER_MCAST_TABLE(mp->port_num);
1327 set_filter_table_entry(mp, table, crc);
1328 }
1329 }
c9df406f 1330}
c8aaea25 1331
c8aaea25 1332
c9df406f 1333/* rx/tx queue initialisation ***********************************************/
64da80a2 1334static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1335{
64da80a2 1336 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1337 struct rx_desc *rx_desc;
1338 int size;
c9df406f
LB		 1339 int i;
1340
64da80a2
LB		 1341 rxq->index = index;
1342
8a578111
LB		 1343 rxq->rx_ring_size = mp->default_rx_ring_size;
1344
1345 rxq->rx_desc_count = 0;
1346 rxq->rx_curr_desc = 0;
1347 rxq->rx_used_desc = 0;
1348
1349 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1350
64da80a2 1351 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1352 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1353 mp->rx_desc_sram_size);
1354 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1355 } else {
1356 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1357 &rxq->rx_desc_dma,
1358 GFP_KERNEL);
f7ea3337
PJ		 1359 }
1360
8a578111
LB		 1361 if (rxq->rx_desc_area == NULL) {
1362 dev_printk(KERN_ERR, &mp->dev->dev,
1363 "can't allocate rx ring (%d bytes)\n", size);
1364 goto out;
1365 }
1366 memset(rxq->rx_desc_area, 0, size);
1da177e4 1367
8a578111
LB		 1368 rxq->rx_desc_area_size = size;
1369 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1370 GFP_KERNEL);
1371 if (rxq->rx_skb == NULL) {
1372 dev_printk(KERN_ERR, &mp->dev->dev,
1373 "can't allocate rx skb ring\n");
1374 goto out_free;
1375 }
1376
1377 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1378 for (i = 0; i < rxq->rx_ring_size; i++) {
1379 int nexti = (i + 1) % rxq->rx_ring_size;
1380 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1381 nexti * sizeof(struct rx_desc);
1382 }
1383
1384 init_timer(&rxq->rx_oom);
1385 rxq->rx_oom.data = (unsigned long)rxq;
1386 rxq->rx_oom.function = rxq_refill_timer_wrapper;
1387
1388 return 0;
1389
1390
1391out_free:
64da80a2 1392 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size)
8a578111
LB		 1393 iounmap(rxq->rx_desc_area);
1394 else
1395 dma_free_coherent(NULL, size,
1396 rxq->rx_desc_area,
1397 rxq->rx_desc_dma);
1398
1399out:
1400 return -ENOMEM;
c9df406f 1401}
c8aaea25 1402
8a578111 1403static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1404{
8a578111
LB		 1405 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1406 int i;
1407
1408 rxq_disable(rxq);
c8aaea25 1409
8a578111 1410 del_timer_sync(&rxq->rx_oom);
c9df406f 1411
8a578111
LB		 1412 for (i = 0; i < rxq->rx_ring_size; i++) {
1413 if (rxq->rx_skb[i]) {
1414 dev_kfree_skb(rxq->rx_skb[i]);
1415 rxq->rx_desc_count--;
1da177e4 1416 }
c8aaea25 1417 }
1da177e4 1418
8a578111
LB		 1419 if (rxq->rx_desc_count) {
1420 dev_printk(KERN_ERR, &mp->dev->dev,
1421 "error freeing rx ring -- %d skbs stuck\n",
1422 rxq->rx_desc_count);
1423 }
1424
64da80a2
LB		 1425 if (rxq->index == mp->rxq_primary &&
1426 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1427 iounmap(rxq->rx_desc_area);
c9df406f 1428 else
8a578111
LB		 1429 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1430 rxq->rx_desc_area, rxq->rx_desc_dma);
1431
1432 kfree(rxq->rx_skb);
c9df406f 1433}
1da177e4 1434
3d6b35bc 1435static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1436{
3d6b35bc 1437 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1438 struct tx_desc *tx_desc;
1439 int size;
c9df406f 1440 int i;
1da177e4 1441
3d6b35bc
LB		 1442 txq->index = index;
1443
13d64285
LB		 1444 txq->tx_ring_size = mp->default_tx_ring_size;
1445
1446 txq->tx_desc_count = 0;
1447 txq->tx_curr_desc = 0;
1448 txq->tx_used_desc = 0;
1449
1450 size = txq->tx_ring_size * sizeof(struct tx_desc);
1451
3d6b35bc 1452 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) {
13d64285
LB		 1453 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1454 mp->tx_desc_sram_size);
1455 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1456 } else {
1457 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1458 &txq->tx_desc_dma,
1459 GFP_KERNEL);
1460 }
1461
1462 if (txq->tx_desc_area == NULL) {
1463 dev_printk(KERN_ERR, &mp->dev->dev,
1464 "can't allocate tx ring (%d bytes)\n", size);
1465 goto out;
c9df406f 1466 }
13d64285
LB		 1467 memset(txq->tx_desc_area, 0, size);
1468
1469 txq->tx_desc_area_size = size;
1470 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1471 GFP_KERNEL);
1472 if (txq->tx_skb == NULL) {
1473 dev_printk(KERN_ERR, &mp->dev->dev,
1474 "can't allocate tx skb ring\n");
1475 goto out_free;
1476 }
1477
1478 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1479 for (i = 0; i < txq->tx_ring_size; i++) {
1480 int nexti = (i + 1) % txq->tx_ring_size;
1481 tx_desc[i].next_desc_ptr = txq->tx_desc_dma +
1482 nexti * sizeof(struct tx_desc);
1483 }
1484
1485 return 0;
1486
c9df406f 1487
13d64285 1488out_free:
3d6b35bc 1489 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size)
13d64285
LB		 1490 iounmap(txq->tx_desc_area);
1491 else
1492 dma_free_coherent(NULL, size,
1493 txq->tx_desc_area,
1494 txq->tx_desc_dma);
c9df406f 1495
13d64285
LB		 1496out:
1497 return -ENOMEM;
c8aaea25 1498}
1da177e4 1499
13d64285 1500static void txq_reclaim(struct tx_queue *txq, int force)
c8aaea25 1501{
13d64285 1502 struct mv643xx_eth_private *mp = txq_to_mp(txq);
c8aaea25 1503 unsigned long flags;
1da177e4 1504
13d64285
LB		 1505 spin_lock_irqsave(&mp->lock, flags);
1506 while (txq->tx_desc_count > 0) {
1507 int tx_index;
1508 struct tx_desc *desc;
1509 u32 cmd_sts;
1510 struct sk_buff *skb;
1511 dma_addr_t addr;
1512 int count;
4d64e718 1513
13d64285
LB		 1514 tx_index = txq->tx_used_desc;
1515 desc = &txq->tx_desc_area[tx_index];
c9df406f 1516 cmd_sts = desc->cmd_sts;
4d64e718 1517
13d64285
LB		 1518 if (!force && (cmd_sts & BUFFER_OWNED_BY_DMA))
1519 break;
1da177e4 1520
13d64285
LB		 1521 txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size;
1522 txq->tx_desc_count--;
1da177e4 1523
c9df406f
LB		 1524 addr = desc->buf_ptr;
1525 count = desc->byte_cnt;
13d64285
LB		 1526 skb = txq->tx_skb[tx_index];
1527 txq->tx_skb[tx_index] = NULL;
c8aaea25 1528
cc9754b3 1529 if (cmd_sts & ERROR_SUMMARY) {
13d64285
LB		 1530 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1531 mp->dev->stats.tx_errors++;
c9df406f 1532 }
1da177e4 1533
13d64285
LB		 1534 /*
1535 * Drop mp->lock while we free the skb.
1536 */
c9df406f 1537 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 1538
cc9754b3 1539 if (cmd_sts & TX_FIRST_DESC)
c9df406f
LB		 1540 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1541 else
1542 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
c2e5b352 1543
c9df406f
LB		 1544 if (skb)
1545 dev_kfree_skb_irq(skb);
63c9e549 1546
13d64285 1547 spin_lock_irqsave(&mp->lock, flags);
c9df406f 1548 }
13d64285 1549 spin_unlock_irqrestore(&mp->lock, flags);
c9df406f 1550}
1da177e4 1551
13d64285 1552static void txq_deinit(struct tx_queue *txq)
c9df406f 1553{
13d64285 1554 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 1555
13d64285
LB		 1556 txq_disable(txq);
1557 txq_reclaim(txq, 1);
1da177e4 1558
13d64285 1559 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 1560
3d6b35bc
LB		 1561 if (txq->index == mp->txq_primary &&
1562 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 1563 iounmap(txq->tx_desc_area);
c9df406f 1564 else
13d64285
LB		 1565 dma_free_coherent(NULL, txq->tx_desc_area_size,
1566 txq->tx_desc_area, txq->tx_desc_dma);
1567
1568 kfree(txq->tx_skb);
c9df406f 1569}
1da177e4 1570
1da177e4 1571
c9df406f 1572/* netdev ops and related ***************************************************/
fc32b0e2 1573static void update_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
c9df406f 1574{
13d64285
LB		 1575 u32 pscr_o;
1576 u32 pscr_n;
1da177e4 1577
13d64285 1578 pscr_o = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
63c9e549 1579
c9df406f 1580 /* clear speed, duplex and rx buffer size fields */
13d64285
LB		 1581 pscr_n = pscr_o & ~(SET_MII_SPEED_TO_100 |
1582 SET_GMII_SPEED_TO_1000 |
1583 SET_FULL_DUPLEX_MODE |
1584 MAX_RX_PACKET_MASK);
1da177e4 1585
fc32b0e2 1586 if (speed == SPEED_1000) {
13d64285
LB		 1587 pscr_n |= SET_GMII_SPEED_TO_1000 | MAX_RX_PACKET_9700BYTE;
1588 } else {
fc32b0e2 1589 if (speed == SPEED_100)
13d64285
LB		 1590 pscr_n |= SET_MII_SPEED_TO_100;
1591 pscr_n |= MAX_RX_PACKET_1522BYTE;
c9df406f 1592 }
1da177e4 1593
fc32b0e2 1594 if (duplex == DUPLEX_FULL)
13d64285
LB		 1595 pscr_n |= SET_FULL_DUPLEX_MODE;
1596
1597 if (pscr_n != pscr_o) {
1598 if ((pscr_o & SERIAL_PORT_ENABLE) == 0)
1599 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
c9df406f 1600 else {
3d6b35bc
LB		 1601 int i;
1602
1603 for (i = 0; i < 8; i++)
1604 if (mp->txq_mask & (1 << i))
1605 txq_disable(mp->txq + i);
1606
13d64285
LB		 1607 pscr_o &= ~SERIAL_PORT_ENABLE;
1608 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_o);
1609 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1610 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
3d6b35bc
LB		 1611
1612 for (i = 0; i < 8; i++)
1613 if (mp->txq_mask & (1 << i))
1614 txq_enable(mp->txq + i);
c9df406f
LB		 1615 }
1616 }
1617}
84dd619e 1618
fc32b0e2 1619static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
c9df406f
LB		 1620{
1621 struct net_device *dev = (struct net_device *)dev_id;
e5371493 1622 struct mv643xx_eth_private *mp = netdev_priv(dev);
fc32b0e2
LB		 1623 u32 int_cause;
1624 u32 int_cause_ext;
ce4e2e45 1625
13d64285 1626 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) & (INT_RX | INT_EXT);
fc32b0e2
LB		 1627 if (int_cause == 0)
1628 return IRQ_NONE;
1629
1630 int_cause_ext = 0;
cc9754b3 1631 if (int_cause & INT_EXT) {
13d64285 1632 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
073a345c 1633 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
13d64285 1634 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
c9df406f 1635 }
1da177e4 1636
fc32b0e2 1637 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK)) {
c9df406f 1638 if (mii_link_ok(&mp->mii)) {
13d64285 1639 struct ethtool_cmd cmd;
3d6b35bc 1640 int i;
13d64285 1641
c9df406f 1642 mii_ethtool_gset(&mp->mii, &cmd);
fc32b0e2 1643 update_pscr(mp, cmd.speed, cmd.duplex);
3d6b35bc
LB		 1644 for (i = 0; i < 8; i++)
1645 if (mp->txq_mask & (1 << i))
1646 txq_enable(mp->txq + i);
1647
c9df406f
LB		 1648 if (!netif_carrier_ok(dev)) {
1649 netif_carrier_on(dev);
3d6b35bc 1650 __txq_maybe_wake(mp->txq + mp->txq_primary);
c9df406f
LB		 1651 }
1652 } else if (netif_carrier_ok(dev)) {
1653 netif_stop_queue(dev);
1654 netif_carrier_off(dev);
1655 }
1656 }
1da177e4 1657
64da80a2
LB		 1658 /*
1659 * RxBuffer or RxError set for any of the 8 queues?
1660 */
e5371493 1661#ifdef MV643XX_ETH_NAPI
cc9754b3 1662 if (int_cause & INT_RX) {
13d64285 1663 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
13d64285 1664 rdl(mp, INT_MASK(mp->port_num));
1da177e4 1665
c9df406f 1666 netif_rx_schedule(dev, &mp->napi);
84dd619e 1667 }
c9df406f 1668#else
64da80a2
LB		 1669 if (int_cause & INT_RX) {
1670 int i;
1671
1672 for (i = 7; i >= 0; i--)
1673 if (mp->rxq_mask & (1 << i))
1674 rxq_process(mp->rxq + i, INT_MAX);
1675 }
c9df406f 1676#endif
fc32b0e2 1677
3d6b35bc
LB		 1678 /*
1679 * TxBuffer or TxError set for any of the 8 queues?
1680 */
13d64285 1681 if (int_cause_ext & INT_EXT_TX) {
3d6b35bc
LB		 1682 int i;
1683
1684 for (i = 0; i < 8; i++)
1685 if (mp->txq_mask & (1 << i))
1686 txq_reclaim(mp->txq + i, 0);
1687
1688 __txq_maybe_wake(mp->txq + mp->txq_primary);
13d64285 1689 }
1da177e4 1690
c9df406f 1691 return IRQ_HANDLED;
1da177e4
LT		 1692}
1693
e5371493 1694static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 1695{
fc32b0e2 1696 unsigned int data;
1da177e4 1697
fc32b0e2
LB		 1698 smi_reg_read(mp, mp->phy_addr, 0, &data);
1699 data |= 0x8000;
1700 smi_reg_write(mp, mp->phy_addr, 0, data);
1da177e4 1701
c9df406f
LB		 1702 do {
1703 udelay(1);
fc32b0e2
LB		 1704 smi_reg_read(mp, mp->phy_addr, 0, &data);
1705 } while (data & 0x8000);
1da177e4
LT		 1706}
1707
fc32b0e2 1708static void port_start(struct mv643xx_eth_private *mp)
1da177e4 1709{
d0412d96
JC		 1710 u32 pscr;
1711 struct ethtool_cmd ethtool_cmd;
8a578111 1712 int i;
1da177e4 1713
8a578111
LB		 1714 /*
1715 * Configure basic link parameters.
1716 */
1717 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1718 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
1719 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1720 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1721 DISABLE_AUTO_NEG_SPEED_GMII |
1722 DISABLE_AUTO_NEG_FOR_DUPLEX |
1723 DO_NOT_FORCE_LINK_FAIL |
1724 SERIAL_PORT_CONTROL_RESERVED;
1725 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1726 pscr |= SERIAL_PORT_ENABLE;
1727 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1da177e4 1728
8a578111
LB		 1729 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1730
fc32b0e2 1731 mv643xx_eth_get_settings(mp->dev, &ethtool_cmd);
8a578111 1732 phy_reset(mp);
fc32b0e2 1733 mv643xx_eth_set_settings(mp->dev, &ethtool_cmd);
1da177e4 1734
13d64285
LB		 1735 /*
1736 * Configure TX path and queues.
1737 */
89df5fdc 1738 tx_set_rate(mp, 1000000000, 16777216);
3d6b35bc
LB		 1739 for (i = 0; i < 8; i++) {
1740 struct tx_queue *txq = mp->txq + i;
1741 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, i);
13d64285
LB		 1742 u32 addr;
1743
3d6b35bc
LB		 1744 if ((mp->txq_mask & (1 << i)) == 0)
1745 continue;
1746
13d64285
LB		 1747 addr = (u32)txq->tx_desc_dma;
1748 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
1749 wrl(mp, off, addr);
89df5fdc
LB		 1750
1751 txq_set_rate(txq, 1000000000, 16777216);
1752 txq_set_fixed_prio_mode(txq);
13d64285
LB		 1753 }
1754
fc32b0e2
LB		 1755 /*
1756 * Add configured unicast address to address filter table.
1757 */
1758 uc_addr_set(mp, mp->dev->dev_addr);
1da177e4 1759
d9a073ea
LB		 1760 /*
1761 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1762 * frames to RX queue #0.
1763 */
8a578111 1764 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
01999873 1765
376489a2
LB		 1766 /*
1767 * Treat BPDUs as normal multicasts, and disable partition mode.
1768 */
8a578111 1769 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
01999873 1770
8a578111 1771 /*
64da80a2 1772 * Enable the receive queues.
8a578111 1773 */
64da80a2
LB		 1774 for (i = 0; i < 8; i++) {
1775 struct rx_queue *rxq = mp->rxq + i;
1776 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
8a578111 1777 u32 addr;
1da177e4 1778
64da80a2
LB		 1779 if ((mp->rxq_mask & (1 << i)) == 0)
1780 continue;
1781
8a578111
LB		 1782 addr = (u32)rxq->rx_desc_dma;
1783 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1784 wrl(mp, off, addr);
1da177e4 1785
8a578111
LB		 1786 rxq_enable(rxq);
1787 }
1da177e4
LT		 1788}
1789
ffd86bbe 1790static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 1791{
c9df406f 1792 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 1793
fc32b0e2
LB		 1794 if (coal > 0x3fff)
1795 coal = 0x3fff;
1796
1797 wrl(mp, SDMA_CONFIG(mp->port_num),
c9df406f 1798 ((coal & 0x3fff) << 8) |
fc32b0e2 1799 (rdl(mp, SDMA_CONFIG(mp->port_num))
c9df406f 1800 & 0xffc000ff));
1da177e4
LT		 1801}
1802
ffd86bbe 1803static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 1804{
c9df406f 1805 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 1806
fc32b0e2
LB		 1807 if (coal > 0x3fff)
1808 coal = 0x3fff;
1809 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
16e03018
DF		 1810}
1811
c9df406f 1812static int mv643xx_eth_open(struct net_device *dev)
16e03018 1813{
e5371493 1814 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1815 int err;
64da80a2 1816 int i;
16e03018 1817
fc32b0e2
LB		 1818 wrl(mp, INT_CAUSE(mp->port_num), 0);
1819 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
1820 rdl(mp, INT_CAUSE_EXT(mp->port_num));
c9df406f 1821
fc32b0e2
LB		 1822 err = request_irq(dev->irq, mv643xx_eth_irq,
1823 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
1824 dev->name, dev);
c9df406f 1825 if (err) {
fc32b0e2 1826 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
c9df406f 1827 return -EAGAIN;
16e03018
DF		 1828 }
1829
fc32b0e2 1830 init_mac_tables(mp);
16e03018 1831
64da80a2
LB		 1832 for (i = 0; i < 8; i++) {
1833 if ((mp->rxq_mask & (1 << i)) == 0)
1834 continue;
1835
1836 err = rxq_init(mp, i);
1837 if (err) {
1838 while (--i >= 0)
1839 if (mp->rxq_mask & (1 << i))
1840 rxq_deinit(mp->rxq + i);
1841 goto out;
1842 }
1843
1844 rxq_refill(mp->rxq + i);
1845 }
8a578111 1846
3d6b35bc
LB		 1847 for (i = 0; i < 8; i++) {
1848 if ((mp->txq_mask & (1 << i)) == 0)
1849 continue;
1850
1851 err = txq_init(mp, i);
1852 if (err) {
1853 while (--i >= 0)
1854 if (mp->txq_mask & (1 << i))
1855 txq_deinit(mp->txq + i);
1856 goto out_free;
1857 }
1858 }
16e03018 1859
e5371493 1860#ifdef MV643XX_ETH_NAPI
c9df406f
LB		 1861 napi_enable(&mp->napi);
1862#endif
16e03018 1863
fc32b0e2 1864 port_start(mp);
16e03018 1865
ffd86bbe
LB		 1866 set_rx_coal(mp, 0);
1867 set_tx_coal(mp, 0);
16e03018 1868
fc32b0e2
LB		 1869 wrl(mp, INT_MASK_EXT(mp->port_num),
1870 INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
16e03018 1871
fc32b0e2 1872 wrl(mp, INT_MASK(mp->port_num), INT_RX | INT_EXT);
16e03018 1873
c9df406f
LB		 1874 return 0;
1875
13d64285 1876
fc32b0e2 1877out_free:
64da80a2
LB		 1878 for (i = 0; i < 8; i++)
1879 if (mp->rxq_mask & (1 << i))
1880 rxq_deinit(mp->rxq + i);
fc32b0e2 1881out:
c9df406f
LB		 1882 free_irq(dev->irq, dev);
1883
1884 return err;
16e03018
DF		 1885}
1886
e5371493 1887static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 1888{
fc32b0e2 1889 unsigned int data;
64da80a2 1890 int i;
1da177e4 1891
64da80a2
LB		 1892 for (i = 0; i < 8; i++) {
1893 if (mp->rxq_mask & (1 << i))
1894 rxq_disable(mp->rxq + i);
3d6b35bc
LB		 1895 if (mp->txq_mask & (1 << i))
1896 txq_disable(mp->txq + i);
64da80a2 1897 }
13d64285
LB		 1898 while (!(rdl(mp, PORT_STATUS(mp->port_num)) & TX_FIFO_EMPTY))
1899 udelay(10);
1da177e4 1900
c9df406f 1901 /* Reset the Enable bit in the Configuration Register */
fc32b0e2
LB		 1902 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1903 data &= ~(SERIAL_PORT_ENABLE |
1904 DO_NOT_FORCE_LINK_FAIL |
1905 FORCE_LINK_PASS);
1906 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
1da177e4
LT		 1907}
1908
c9df406f 1909static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 1910{
e5371493 1911 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 1912 int i;
1da177e4 1913
fc32b0e2
LB		 1914 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1915 rdl(mp, INT_MASK(mp->port_num));
1da177e4 1916
e5371493 1917#ifdef MV643XX_ETH_NAPI
c9df406f
LB		 1918 napi_disable(&mp->napi);
1919#endif
1920 netif_carrier_off(dev);
1921 netif_stop_queue(dev);
1da177e4 1922
fc32b0e2
LB		 1923 free_irq(dev->irq, dev);
1924
cc9754b3 1925 port_reset(mp);
fc32b0e2 1926 mib_counters_update(mp);
1da177e4 1927
64da80a2
LB		 1928 for (i = 0; i < 8; i++) {
1929 if (mp->rxq_mask & (1 << i))
1930 rxq_deinit(mp->rxq + i);
3d6b35bc
LB		 1931 if (mp->txq_mask & (1 << i))
1932 txq_deinit(mp->txq + i);
64da80a2 1933 }
1da177e4 1934
c9df406f 1935 return 0;
1da177e4
LT		 1936}
1937
fc32b0e2 1938static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 1939{
e5371493 1940 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1941
c9df406f 1942 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
1da177e4
LT		 1943}
1944
c9df406f 1945static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 1946{
89df5fdc
LB		 1947 struct mv643xx_eth_private *mp = netdev_priv(dev);
1948
fc32b0e2 1949 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 1950 return -EINVAL;
1da177e4 1951
c9df406f 1952 dev->mtu = new_mtu;
89df5fdc
LB		 1953 tx_set_rate(mp, 1000000000, 16777216);
1954
c9df406f
LB		 1955 if (!netif_running(dev))
1956 return 0;
1da177e4 1957
c9df406f
LB		 1958 /*
1959 * Stop and then re-open the interface. This will allocate RX
1960 * skbs of the new MTU.
1961 * There is a possible danger that the open will not succeed,
fc32b0e2 1962 * due to memory being full.
c9df406f
LB		 1963 */
1964 mv643xx_eth_stop(dev);
1965 if (mv643xx_eth_open(dev)) {
fc32b0e2
LB		 1966 dev_printk(KERN_ERR, &dev->dev,
1967 "fatal error on re-opening device after "
1968 "MTU change\n");
c9df406f
LB		 1969 }
1970
1971 return 0;
1da177e4
LT		 1972}
1973
fc32b0e2 1974static void tx_timeout_task(struct work_struct *ugly)
1da177e4 1975{
fc32b0e2 1976 struct mv643xx_eth_private *mp;
1da177e4 1977
fc32b0e2
LB		 1978 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
1979 if (netif_running(mp->dev)) {
1980 netif_stop_queue(mp->dev);
c9df406f 1981
fc32b0e2
LB		 1982 port_reset(mp);
1983 port_start(mp);
c9df406f 1984
3d6b35bc 1985 __txq_maybe_wake(mp->txq + mp->txq_primary);
fc32b0e2 1986 }
c9df406f
LB		 1987}
1988
c9df406f 1989static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 1990{
e5371493 1991 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1992
fc32b0e2 1993 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
d0412d96 1994
c9df406f 1995 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 1996}
1997
c9df406f 1998#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 1999static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2000{
fc32b0e2 2001 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2002
fc32b0e2
LB		 2003 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2004 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2005
fc32b0e2 2006 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2007
fc32b0e2 2008 wrl(mp, INT_MASK(mp->port_num), INT_RX | INT_CAUSE_EXT);
9f8dd319 2009}
c9df406f 2010#endif
9f8dd319 2011
fc32b0e2 2012static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
9f8dd319 2013{
e5371493 2014 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f
LB		 2015 int val;
2016
fc32b0e2
LB		 2017 smi_reg_read(mp, addr, reg, &val);
2018
c9df406f 2019 return val;
9f8dd319
DF		 2020}
2021
fc32b0e2 2022static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
9f8dd319 2023{
e5371493 2024 struct mv643xx_eth_private *mp = netdev_priv(dev);
fc32b0e2 2025 smi_reg_write(mp, addr, reg, val);
c9df406f 2026}
9f8dd319 2027
9f8dd319 2028
c9df406f 2029/* platform glue ************************************************************/
e5371493
LB		 2030static void
2031mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2032 struct mbus_dram_target_info *dram)
c9df406f 2033{
cc9754b3 2034 void __iomem *base = msp->base;
c9df406f
LB		 2035 u32 win_enable;
2036 u32 win_protect;
2037 int i;
9f8dd319 2038
c9df406f
LB		 2039 for (i = 0; i < 6; i++) {
2040 writel(0, base + WINDOW_BASE(i));
2041 writel(0, base + WINDOW_SIZE(i));
2042 if (i < 4)
2043 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2044 }
2045
c9df406f
LB		 2046 win_enable = 0x3f;
2047 win_protect = 0;
2048
2049 for (i = 0; i < dram->num_cs; i++) {
2050 struct mbus_dram_window *cs = dram->cs + i;
2051
2052 writel((cs->base & 0xffff0000) |
2053 (cs->mbus_attr << 8) |
2054 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2055 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2056
2057 win_enable &= ~(1 << i);
2058 win_protect |= 3 << (2 * i);
2059 }
2060
2061 writel(win_enable, base + WINDOW_BAR_ENABLE);
2062 msp->win_protect = win_protect;
9f8dd319
DF		 2063}
2064
c9df406f 2065static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2066{
e5371493 2067 static int mv643xx_eth_version_printed = 0;
c9df406f 2068 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2069 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 2070 struct resource *res;
2071 int ret;
9f8dd319 2072
e5371493 2073 if (!mv643xx_eth_version_printed++)
c9df406f 2074 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
9f8dd319 2075
c9df406f
LB		 2076 ret = -EINVAL;
2077 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2078 if (res == NULL)
2079 goto out;
9f8dd319 2080
c9df406f
LB		 2081 ret = -ENOMEM;
2082 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2083 if (msp == NULL)
2084 goto out;
2085 memset(msp, 0, sizeof(*msp));
2086
cc9754b3
LB		 2087 msp->base = ioremap(res->start, res->end - res->start + 1);
2088 if (msp->base == NULL)
c9df406f
LB		 2089 goto out_free;
2090
2091 spin_lock_init(&msp->phy_lock);
c9df406f
LB		 2092
2093 /*
2094 * (Re-)program MBUS remapping windows if we are asked to.
2095 */
2096 if (pd != NULL && pd->dram != NULL)
2097 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2098
fc32b0e2
LB		 2099 /*
2100 * Detect hardware parameters.
2101 */
2102 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2103
2104 platform_set_drvdata(pdev, msp);
2105
c9df406f
LB		 2106 return 0;
2107
2108out_free:
2109 kfree(msp);
2110out:
2111 return ret;
2112}
2113
2114static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2115{
e5371493 2116 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
c9df406f 2117
cc9754b3 2118 iounmap(msp->base);
c9df406f
LB		 2119 kfree(msp);
2120
2121 return 0;
9f8dd319
DF		 2122}
2123
c9df406f 2124static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2125 .probe = mv643xx_eth_shared_probe,
2126 .remove = mv643xx_eth_shared_remove,
c9df406f 2127 .driver = {
fc32b0e2 2128 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2129 .owner = THIS_MODULE,
2130 },
2131};
2132
e5371493 2133static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2134{
c9df406f 2135 int addr_shift = 5 * mp->port_num;
fc32b0e2 2136 u32 data;
1da177e4 2137
fc32b0e2
LB		 2138 data = rdl(mp, PHY_ADDR);
2139 data &= ~(0x1f << addr_shift);
2140 data |= (phy_addr & 0x1f) << addr_shift;
2141 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2142}
2143
e5371493 2144static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2145{
fc32b0e2
LB		 2146 unsigned int data;
2147
2148 data = rdl(mp, PHY_ADDR);
2149
2150 return (data >> (5 * mp->port_num)) & 0x1f;
2151}
2152
2153static void set_params(struct mv643xx_eth_private *mp,
2154 struct mv643xx_eth_platform_data *pd)
2155{
2156 struct net_device *dev = mp->dev;
2157
2158 if (is_valid_ether_addr(pd->mac_addr))
2159 memcpy(dev->dev_addr, pd->mac_addr, 6);
2160 else
2161 uc_addr_get(mp, dev->dev_addr);
2162
2163 if (pd->phy_addr == -1) {
2164 mp->shared_smi = NULL;
2165 mp->phy_addr = -1;
2166 } else {
2167 mp->shared_smi = mp->shared;
2168 if (pd->shared_smi != NULL)
2169 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2170
2171 if (pd->force_phy_addr || pd->phy_addr) {
2172 mp->phy_addr = pd->phy_addr & 0x3f;
2173 phy_addr_set(mp, mp->phy_addr);
2174 } else {
2175 mp->phy_addr = phy_addr_get(mp);
2176 }
2177 }
1da177e4 2178
fc32b0e2
LB		 2179 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2180 if (pd->rx_queue_size)
2181 mp->default_rx_ring_size = pd->rx_queue_size;
2182 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2183 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2184
64da80a2
LB		 2185 if (pd->rx_queue_mask)
2186 mp->rxq_mask = pd->rx_queue_mask;
2187 else
2188 mp->rxq_mask = 0x01;
2189 mp->rxq_primary = fls(mp->rxq_mask) - 1;
2190
fc32b0e2
LB		 2191 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2192 if (pd->tx_queue_size)
2193 mp->default_tx_ring_size = pd->tx_queue_size;
2194 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2195 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc
LB		 2196
2197 if (pd->tx_queue_mask)
2198 mp->txq_mask = pd->tx_queue_mask;
2199 else
2200 mp->txq_mask = 0x01;
2201 mp->txq_primary = fls(mp->txq_mask) - 1;
1da177e4
LT		 2202}
2203
e5371493 2204static int phy_detect(struct mv643xx_eth_private *mp)
1da177e4 2205{
fc32b0e2
LB		 2206 unsigned int data;
2207 unsigned int data2;
2208
2209 smi_reg_read(mp, mp->phy_addr, 0, &data);
2210 smi_reg_write(mp, mp->phy_addr, 0, data ^ 0x1000);
1da177e4 2211
fc32b0e2
LB		 2212 smi_reg_read(mp, mp->phy_addr, 0, &data2);
2213 if (((data ^ data2) & 0x1000) == 0)
2214 return -ENODEV;
1da177e4 2215
fc32b0e2 2216 smi_reg_write(mp, mp->phy_addr, 0, data);
1da177e4 2217
c9df406f 2218 return 0;
1da177e4
LT		 2219}
2220
fc32b0e2
LB		 2221static int phy_init(struct mv643xx_eth_private *mp,
2222 struct mv643xx_eth_platform_data *pd)
c28a4f89 2223{
fc32b0e2
LB		 2224 struct ethtool_cmd cmd;
2225 int err;
c28a4f89 2226
fc32b0e2
LB		 2227 err = phy_detect(mp);
2228 if (err) {
2229 dev_printk(KERN_INFO, &mp->dev->dev,
2230 "no PHY detected at addr %d\n", mp->phy_addr);
2231 return err;
2232 }
2233 phy_reset(mp);
2234
2235 mp->mii.phy_id = mp->phy_addr;
2236 mp->mii.phy_id_mask = 0x3f;
2237 mp->mii.reg_num_mask = 0x1f;
2238 mp->mii.dev = mp->dev;
2239 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2240 mp->mii.mdio_write = mv643xx_eth_mdio_write;
c28a4f89 2241
fc32b0e2 2242 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
c9df406f 2243
fc32b0e2
LB		 2244 memset(&cmd, 0, sizeof(cmd));
2245
2246 cmd.port = PORT_MII;
2247 cmd.transceiver = XCVR_INTERNAL;
2248 cmd.phy_address = mp->phy_addr;
2249 if (pd->speed == 0) {
2250 cmd.autoneg = AUTONEG_ENABLE;
2251 cmd.speed = SPEED_100;
2252 cmd.advertising = ADVERTISED_10baseT_Half |
2253 ADVERTISED_10baseT_Full |
2254 ADVERTISED_100baseT_Half |
2255 ADVERTISED_100baseT_Full;
c9df406f 2256 if (mp->mii.supports_gmii)
fc32b0e2 2257 cmd.advertising |= ADVERTISED_1000baseT_Full;
c9df406f 2258 } else {
fc32b0e2
LB		 2259 cmd.autoneg = AUTONEG_DISABLE;
2260 cmd.speed = pd->speed;
2261 cmd.duplex = pd->duplex;
c9df406f 2262 }
fc32b0e2
LB		 2263
2264 update_pscr(mp, cmd.speed, cmd.duplex);
2265 mv643xx_eth_set_settings(mp->dev, &cmd);
2266
2267 return 0;
c28a4f89
JC		 2268}
2269
c9df406f 2270static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2271{
c9df406f 2272 struct mv643xx_eth_platform_data *pd;
e5371493 2273 struct mv643xx_eth_private *mp;
c9df406f 2274 struct net_device *dev;
c9df406f 2275 struct resource *res;
c9df406f 2276 DECLARE_MAC_BUF(mac);
fc32b0e2 2277 int err;
1da177e4 2278
c9df406f
LB		 2279 pd = pdev->dev.platform_data;
2280 if (pd == NULL) {
fc32b0e2
LB		 2281 dev_printk(KERN_ERR, &pdev->dev,
2282 "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2283 return -ENODEV;
2284 }
1da177e4 2285
c9df406f 2286 if (pd->shared == NULL) {
fc32b0e2
LB		 2287 dev_printk(KERN_ERR, &pdev->dev,
2288 "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2289 return -ENODEV;
2290 }
8f518703 2291
e5371493 2292 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
c9df406f
LB		 2293 if (!dev)
2294 return -ENOMEM;
1da177e4 2295
c9df406f 2296 mp = netdev_priv(dev);
fc32b0e2
LB		 2297 platform_set_drvdata(pdev, mp);
2298
2299 mp->shared = platform_get_drvdata(pd->shared);
2300 mp->port_num = pd->port_number;
2301
c9df406f 2302 mp->dev = dev;
e5371493
LB		 2303#ifdef MV643XX_ETH_NAPI
2304 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
c9df406f 2305#endif
1da177e4 2306
fc32b0e2
LB		 2307 set_params(mp, pd);
2308
2309 spin_lock_init(&mp->lock);
2310
2311 mib_counters_clear(mp);
2312 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2313
2314 err = phy_init(mp, pd);
2315 if (err)
2316 goto out;
2317 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2318
2319
c9df406f
LB		 2320 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2321 BUG_ON(!res);
2322 dev->irq = res->start;
1da177e4 2323
fc32b0e2 2324 dev->hard_start_xmit = mv643xx_eth_xmit;
c9df406f
LB		 2325 dev->open = mv643xx_eth_open;
2326 dev->stop = mv643xx_eth_stop;
c9df406f 2327 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
fc32b0e2
LB		 2328 dev->set_mac_address = mv643xx_eth_set_mac_address;
2329 dev->do_ioctl = mv643xx_eth_ioctl;
2330 dev->change_mtu = mv643xx_eth_change_mtu;
c9df406f 2331 dev->tx_timeout = mv643xx_eth_tx_timeout;
c9df406f 2332#ifdef CONFIG_NET_POLL_CONTROLLER
e5371493 2333 dev->poll_controller = mv643xx_eth_netpoll;
c9df406f 2334#endif
c9df406f
LB		 2335 dev->watchdog_timeo = 2 * HZ;
2336 dev->base_addr = 0;
1da177e4 2337
e5371493 2338#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
b4de9051 2339 /*
c9df406f
LB		 2340 * Zero copy can only work if we use Discovery II memory. Else, we will
2341 * have to map the buffers to ISA memory which is only 16 MB
b4de9051 2342 */
c9df406f 2343 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
c9df406f 2344#endif
1da177e4 2345
fc32b0e2 2346 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2347
c9df406f 2348 if (mp->shared->win_protect)
fc32b0e2 2349 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2350
c9df406f
LB		 2351 err = register_netdev(dev);
2352 if (err)
2353 goto out;
1da177e4 2354
fc32b0e2
LB		 2355 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2356 mp->port_num, print_mac(mac, dev->dev_addr));
1da177e4 2357
c9df406f 2358 if (dev->features & NETIF_F_SG)
fc32b0e2 2359 dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n");
1da177e4 2360
c9df406f 2361 if (dev->features & NETIF_F_IP_CSUM)
fc32b0e2 2362 dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n");
1da177e4 2363
e5371493 2364#ifdef MV643XX_ETH_NAPI
fc32b0e2 2365 dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n");
c9df406f 2366#endif
1da177e4 2367
13d64285 2368 if (mp->tx_desc_sram_size > 0)
fc32b0e2 2369 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
1da177e4 2370
c9df406f 2371 return 0;
1da177e4 2372
c9df406f
LB		 2373out:
2374 free_netdev(dev);
1da177e4 2375
c9df406f 2376 return err;
1da177e4
LT		 2377}
2378
c9df406f 2379static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2380{
fc32b0e2 2381 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2382
fc32b0e2 2383 unregister_netdev(mp->dev);
c9df406f 2384 flush_scheduled_work();
fc32b0e2 2385 free_netdev(mp->dev);
c9df406f 2386
c9df406f 2387 platform_set_drvdata(pdev, NULL);
fc32b0e2 2388
c9df406f 2389 return 0;
1da177e4
LT		 2390}
2391
c9df406f 2392static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2393{
fc32b0e2 2394 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 2395
c9df406f 2396 /* Mask all interrupts on ethernet port */
fc32b0e2
LB		 2397 wrl(mp, INT_MASK(mp->port_num), 0);
2398 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2399
fc32b0e2
LB		 2400 if (netif_running(mp->dev))
2401 port_reset(mp);
d0412d96
JC		 2402}
2403
c9df406f 2404static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 2405 .probe = mv643xx_eth_probe,
2406 .remove = mv643xx_eth_remove,
2407 .shutdown = mv643xx_eth_shutdown,
c9df406f 2408 .driver = {
fc32b0e2 2409 .name = MV643XX_ETH_NAME,
c9df406f
LB		 2410 .owner = THIS_MODULE,
2411 },
2412};
2413
e5371493 2414static int __init mv643xx_eth_init_module(void)
d0412d96 2415{
c9df406f 2416 int rc;
d0412d96 2417
c9df406f
LB		 2418 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2419 if (!rc) {
2420 rc = platform_driver_register(&mv643xx_eth_driver);
2421 if (rc)
2422 platform_driver_unregister(&mv643xx_eth_shared_driver);
2423 }
fc32b0e2 2424
c9df406f 2425 return rc;
d0412d96 2426}
fc32b0e2 2427module_init(mv643xx_eth_init_module);
d0412d96 2428
e5371493 2429static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 2430{
c9df406f
LB		 2431 platform_driver_unregister(&mv643xx_eth_driver);
2432 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 2433}
e5371493 2434module_exit(mv643xx_eth_cleanup_module);
1da177e4 2435
fc32b0e2
LB		 2436MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani "
2437 "and Dale Farnsworth");
c9df406f 2438MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 2439MODULE_LICENSE("GPL");
c9df406f 2440MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 2441MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux kernel - Deliverables
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