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Merge branch 'oprofile-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
c3efab8e 41#include <linux/ip.h>
1da177e4
LT		 42#include <linux/tcp.h>
43#include <linux/udp.h>
44#include <linux/etherdevice.h>
1da177e4
LT		 45#include <linux/delay.h>
46#include <linux/ethtool.h>
d052d1be 47#include <linux/platform_device.h>
fbd6a754
LB		 48#include <linux/module.h>
49#include <linux/kernel.h>
50#include <linux/spinlock.h>
51#include <linux/workqueue.h>
ed94493f 52#include <linux/phy.h>
fbd6a754 53#include <linux/mv643xx_eth.h>
10a9948d
LB		 54#include <linux/io.h>
55#include <linux/types.h>
eaf5d590 56#include <linux/inet_lro.h>
1da177e4 57#include <asm/system.h>
fbd6a754 58
e5371493 59static char mv643xx_eth_driver_name[] = "mv643xx_eth";
042af53c 60static char mv643xx_eth_driver_version[] = "1.4";
c9df406f 61
fbd6a754 62
fbd6a754
LB		 63/*
64 * Registers shared between all ports.
65 */
3cb4667c
LB		 66#define PHY_ADDR 0x0000
67#define SMI_REG 0x0004
45c5d3bc
LB		 68#define SMI_BUSY 0x10000000
69#define SMI_READ_VALID 0x08000000
70#define SMI_OPCODE_READ 0x04000000
71#define SMI_OPCODE_WRITE 0x00000000
72#define ERR_INT_CAUSE 0x0080
73#define ERR_INT_SMI_DONE 0x00000010
74#define ERR_INT_MASK 0x0084
3cb4667c
LB		 75#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78#define WINDOW_BAR_ENABLE 0x0290
79#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 80
81/*
37a6084f
LB		 82 * Main per-port registers. These live at offset 0x0400 for
83 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
fbd6a754 84 */
37a6084f 85#define PORT_CONFIG 0x0000
d9a073ea 86#define UNICAST_PROMISCUOUS_MODE 0x00000001
37a6084f
LB		 87#define PORT_CONFIG_EXT 0x0004
88#define MAC_ADDR_LOW 0x0014
89#define MAC_ADDR_HIGH 0x0018
90#define SDMA_CONFIG 0x001c
91#define PORT_SERIAL_CONTROL 0x003c
92#define PORT_STATUS 0x0044
a2a41689 93#define TX_FIFO_EMPTY 0x00000400
ae9ae064 94#define TX_IN_PROGRESS 0x00000080
2f7eb47a
LB		 95#define PORT_SPEED_MASK 0x00000030
96#define PORT_SPEED_1000 0x00000010
97#define PORT_SPEED_100 0x00000020
98#define PORT_SPEED_10 0x00000000
99#define FLOW_CONTROL_ENABLED 0x00000008
100#define FULL_DUPLEX 0x00000004
81600eea 101#define LINK_UP 0x00000002
37a6084f
LB		 102#define TXQ_COMMAND 0x0048
103#define TXQ_FIX_PRIO_CONF 0x004c
104#define TX_BW_RATE 0x0050
105#define TX_BW_MTU 0x0058
106#define TX_BW_BURST 0x005c
107#define INT_CAUSE 0x0060
226bb6b7 108#define INT_TX_END 0x07f80000
befefe21 109#define INT_RX 0x000003fc
073a345c 110#define INT_EXT 0x00000002
37a6084f 111#define INT_CAUSE_EXT 0x0064
befefe21
LB		 112#define INT_EXT_LINK_PHY 0x00110000
113#define INT_EXT_TX 0x000000ff
37a6084f
LB		 114#define INT_MASK 0x0068
115#define INT_MASK_EXT 0x006c
116#define TX_FIFO_URGENT_THRESHOLD 0x0074
117#define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
118#define TX_BW_RATE_MOVED 0x00e0
119#define TX_BW_MTU_MOVED 0x00e8
120#define TX_BW_BURST_MOVED 0x00ec
121#define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
122#define RXQ_COMMAND 0x0280
123#define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
124#define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
125#define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
126#define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
127
128/*
129 * Misc per-port registers.
130 */
3cb4667c
LB		 131#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
132#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
133#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
134#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 135
2679a550
LB		 136
137/*
138 * SDMA configuration register.
139 */
e0c6ef93 140#define RX_BURST_SIZE_4_64BIT (2 << 1)
cd4ccf76 141#define RX_BURST_SIZE_16_64BIT (4 << 1)
fbd6a754 142#define BLM_RX_NO_SWAP (1 << 4)
fbd6a754 143#define BLM_TX_NO_SWAP (1 << 5)
e0c6ef93 144#define TX_BURST_SIZE_4_64BIT (2 << 22)
cd4ccf76 145#define TX_BURST_SIZE_16_64BIT (4 << 22)
fbd6a754
LB		 146
147#if defined(__BIG_ENDIAN)
148#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
e0c6ef93
LB		 149 (RX_BURST_SIZE_4_64BIT | \
150 TX_BURST_SIZE_4_64BIT)
fbd6a754
LB		 151#elif defined(__LITTLE_ENDIAN)
152#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
e0c6ef93
LB		 153 (RX_BURST_SIZE_4_64BIT | \
154 BLM_RX_NO_SWAP | \
155 BLM_TX_NO_SWAP | \
156 TX_BURST_SIZE_4_64BIT)
fbd6a754
LB		 157#else
158#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
159#endif
160
2beff77b
LB		 161
162/*
163 * Port serial control register.
164 */
165#define SET_MII_SPEED_TO_100 (1 << 24)
166#define SET_GMII_SPEED_TO_1000 (1 << 23)
167#define SET_FULL_DUPLEX_MODE (1 << 21)
fbd6a754 168#define MAX_RX_PACKET_9700BYTE (5 << 17)
2beff77b
LB		 169#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
170#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
171#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
172#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
173#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
174#define FORCE_LINK_PASS (1 << 1)
175#define SERIAL_PORT_ENABLE (1 << 0)
fbd6a754 176
2b4a624d
LB		 177#define DEFAULT_RX_QUEUE_SIZE 128
178#define DEFAULT_TX_QUEUE_SIZE 256
fbd6a754 179
fbd6a754 180
7ca72a3b
LB		 181/*
182 * RX/TX descriptors.
fbd6a754
LB		 183 */
184#if defined(__BIG_ENDIAN)
cc9754b3 185struct rx_desc {
fbd6a754
LB		 186 u16 byte_cnt; /* Descriptor buffer byte count */
187 u16 buf_size; /* Buffer size */
188 u32 cmd_sts; /* Descriptor command status */
189 u32 next_desc_ptr; /* Next descriptor pointer */
190 u32 buf_ptr; /* Descriptor buffer pointer */
191};
192
cc9754b3 193struct tx_desc {
fbd6a754
LB		 194 u16 byte_cnt; /* buffer byte count */
195 u16 l4i_chk; /* CPU provided TCP checksum */
196 u32 cmd_sts; /* Command/status field */
197 u32 next_desc_ptr; /* Pointer to next descriptor */
198 u32 buf_ptr; /* pointer to buffer for this descriptor*/
199};
200#elif defined(__LITTLE_ENDIAN)
cc9754b3 201struct rx_desc {
fbd6a754
LB		 202 u32 cmd_sts; /* Descriptor command status */
203 u16 buf_size; /* Buffer size */
204 u16 byte_cnt; /* Descriptor buffer byte count */
205 u32 buf_ptr; /* Descriptor buffer pointer */
206 u32 next_desc_ptr; /* Next descriptor pointer */
207};
208
cc9754b3 209struct tx_desc {
fbd6a754
LB		 210 u32 cmd_sts; /* Command/status field */
211 u16 l4i_chk; /* CPU provided TCP checksum */
212 u16 byte_cnt; /* buffer byte count */
213 u32 buf_ptr; /* pointer to buffer for this descriptor*/
214 u32 next_desc_ptr; /* Pointer to next descriptor */
215};
216#else
217#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
218#endif
219
7ca72a3b 220/* RX & TX descriptor command */
cc9754b3 221#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 222
223/* RX & TX descriptor status */
cc9754b3 224#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 225
226/* RX descriptor status */
cc9754b3
LB		 227#define LAYER_4_CHECKSUM_OK 0x40000000
228#define RX_ENABLE_INTERRUPT 0x20000000
229#define RX_FIRST_DESC 0x08000000
230#define RX_LAST_DESC 0x04000000
eaf5d590
LB		 231#define RX_IP_HDR_OK 0x02000000
232#define RX_PKT_IS_IPV4 0x01000000
233#define RX_PKT_IS_ETHERNETV2 0x00800000
234#define RX_PKT_LAYER4_TYPE_MASK 0x00600000
235#define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
236#define RX_PKT_IS_VLAN_TAGGED 0x00080000
7ca72a3b
LB		 237
238/* TX descriptor command */
cc9754b3
LB		 239#define TX_ENABLE_INTERRUPT 0x00800000
240#define GEN_CRC 0x00400000
241#define TX_FIRST_DESC 0x00200000
242#define TX_LAST_DESC 0x00100000
243#define ZERO_PADDING 0x00080000
244#define GEN_IP_V4_CHECKSUM 0x00040000
245#define GEN_TCP_UDP_CHECKSUM 0x00020000
246#define UDP_FRAME 0x00010000
e32b6617
LB		 247#define MAC_HDR_EXTRA_4_BYTES 0x00008000
248#define MAC_HDR_EXTRA_8_BYTES 0x00000200
7ca72a3b 249
cc9754b3 250#define TX_IHL_SHIFT 11
7ca72a3b
LB		 251
252
c9df406f 253/* global *******************************************************************/
e5371493 254struct mv643xx_eth_shared_private {
fc32b0e2
LB		 255 /*
256 * Ethernet controller base address.
257 */
cc9754b3 258 void __iomem *base;
c9df406f 259
fc0eb9f2
LB		 260 /*
261 * Points at the right SMI instance to use.
262 */
263 struct mv643xx_eth_shared_private *smi;
264
fc32b0e2 265 /*
ed94493f 266 * Provides access to local SMI interface.
fc32b0e2 267 */
298cf9be 268 struct mii_bus *smi_bus;
c9df406f 269
45c5d3bc
LB		 270 /*
271 * If we have access to the error interrupt pin (which is
272 * somewhat misnamed as it not only reflects internal errors
273 * but also reflects SMI completion), use that to wait for
274 * SMI access completion instead of polling the SMI busy bit.
275 */
276 int err_interrupt;
277 wait_queue_head_t smi_busy_wait;
278
fc32b0e2
LB		 279 /*
280 * Per-port MBUS window access register value.
281 */
c9df406f
LB		 282 u32 win_protect;
283
fc32b0e2
LB		 284 /*
285 * Hardware-specific parameters.
286 */
c9df406f 287 unsigned int t_clk;
773fc3ee 288 int extended_rx_coal_limit;
457b1d5a 289 int tx_bw_control;
c9df406f
LB		 290};
291
457b1d5a
LB		 292#define TX_BW_CONTROL_ABSENT 0
293#define TX_BW_CONTROL_OLD_LAYOUT 1
294#define TX_BW_CONTROL_NEW_LAYOUT 2
295
e7d2f4db
LB		 296static int mv643xx_eth_open(struct net_device *dev);
297static int mv643xx_eth_stop(struct net_device *dev);
298
c9df406f
LB		 299
300/* per-port *****************************************************************/
e5371493 301struct mib_counters {
fbd6a754
LB		 302 u64 good_octets_received;
303 u32 bad_octets_received;
304 u32 internal_mac_transmit_err;
305 u32 good_frames_received;
306 u32 bad_frames_received;
307 u32 broadcast_frames_received;
308 u32 multicast_frames_received;
309 u32 frames_64_octets;
310 u32 frames_65_to_127_octets;
311 u32 frames_128_to_255_octets;
312 u32 frames_256_to_511_octets;
313 u32 frames_512_to_1023_octets;
314 u32 frames_1024_to_max_octets;
315 u64 good_octets_sent;
316 u32 good_frames_sent;
317 u32 excessive_collision;
318 u32 multicast_frames_sent;
319 u32 broadcast_frames_sent;
320 u32 unrec_mac_control_received;
321 u32 fc_sent;
322 u32 good_fc_received;
323 u32 bad_fc_received;
324 u32 undersize_received;
325 u32 fragments_received;
326 u32 oversize_received;
327 u32 jabber_received;
328 u32 mac_receive_error;
329 u32 bad_crc_event;
330 u32 collision;
331 u32 late_collision;
332};
333
eaf5d590
LB		 334struct lro_counters {
335 u32 lro_aggregated;
336 u32 lro_flushed;
337 u32 lro_no_desc;
338};
339
8a578111 340struct rx_queue {
64da80a2
LB		 341 int index;
342
8a578111
LB		 343 int rx_ring_size;
344
345 int rx_desc_count;
346 int rx_curr_desc;
347 int rx_used_desc;
348
349 struct rx_desc *rx_desc_area;
350 dma_addr_t rx_desc_dma;
351 int rx_desc_area_size;
352 struct sk_buff **rx_skb;
eaf5d590 353
eaf5d590
LB		 354 struct net_lro_mgr lro_mgr;
355 struct net_lro_desc lro_arr[8];
8a578111
LB		 356};
357
13d64285 358struct tx_queue {
3d6b35bc
LB		 359 int index;
360
13d64285 361 int tx_ring_size;
fbd6a754 362
13d64285
LB		 363 int tx_desc_count;
364 int tx_curr_desc;
365 int tx_used_desc;
fbd6a754 366
5daffe94 367 struct tx_desc *tx_desc_area;
fbd6a754
LB		 368 dma_addr_t tx_desc_dma;
369 int tx_desc_area_size;
99ab08e0
LB		 370
371 struct sk_buff_head tx_skb;
8fd89211
LB		 372
373 unsigned long tx_packets;
374 unsigned long tx_bytes;
375 unsigned long tx_dropped;
13d64285
LB		 376};
377
378struct mv643xx_eth_private {
379 struct mv643xx_eth_shared_private *shared;
37a6084f 380 void __iomem *base;
fc32b0e2 381 int port_num;
13d64285 382
fc32b0e2 383 struct net_device *dev;
fbd6a754 384
ed94493f 385 struct phy_device *phy;
fbd6a754 386
4ff3495a
LB		 387 struct timer_list mib_counters_timer;
388 spinlock_t mib_counters_lock;
fc32b0e2 389 struct mib_counters mib_counters;
4ff3495a 390
eaf5d590
LB		 391 struct lro_counters lro_counters;
392
fc32b0e2 393 struct work_struct tx_timeout_task;
8a578111 394
1fa38c58 395 struct napi_struct napi;
1319ebad 396 u8 oom;
1fa38c58
LB		 397 u8 work_link;
398 u8 work_tx;
399 u8 work_tx_end;
400 u8 work_rx;
401 u8 work_rx_refill;
1fa38c58 402
2bcb4b0f
LB		 403 int skb_size;
404 struct sk_buff_head rx_recycle;
405
8a578111
LB		 406 /*
407 * RX state.
408 */
e7d2f4db 409 int rx_ring_size;
8a578111
LB		 410 unsigned long rx_desc_sram_addr;
411 int rx_desc_sram_size;
f7981c1c 412 int rxq_count;
2257e05c 413 struct timer_list rx_oom;
64da80a2 414 struct rx_queue rxq[8];
13d64285
LB		 415
416 /*
417 * TX state.
418 */
e7d2f4db 419 int tx_ring_size;
13d64285
LB		 420 unsigned long tx_desc_sram_addr;
421 int tx_desc_sram_size;
f7981c1c 422 int txq_count;
3d6b35bc 423 struct tx_queue txq[8];
fbd6a754 424};
1da177e4 425
fbd6a754 426
c9df406f 427/* port register accessors **************************************************/
e5371493 428static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 429{
cc9754b3 430 return readl(mp->shared->base + offset);
c9df406f 431}
fbd6a754 432
37a6084f
LB		 433static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
434{
435 return readl(mp->base + offset);
436}
437
e5371493 438static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 439{
cc9754b3 440 writel(data, mp->shared->base + offset);
c9df406f 441}
fbd6a754 442
37a6084f
LB		 443static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
444{
445 writel(data, mp->base + offset);
446}
447
fbd6a754 448
c9df406f 449/* rxq/txq helper functions *************************************************/
8a578111 450static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 451{
64da80a2 452 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 453}
fbd6a754 454
13d64285
LB		 455static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
456{
3d6b35bc 457 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 458}
459
8a578111 460static void rxq_enable(struct rx_queue *rxq)
c9df406f 461{
8a578111 462 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
37a6084f 463 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
8a578111 464}
1da177e4 465
8a578111
LB		 466static void rxq_disable(struct rx_queue *rxq)
467{
468 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 469 u8 mask = 1 << rxq->index;
1da177e4 470
37a6084f
LB		 471 wrlp(mp, RXQ_COMMAND, mask << 8);
472 while (rdlp(mp, RXQ_COMMAND) & mask)
8a578111 473 udelay(10);
c9df406f
LB		 474}
475
6b368f68
LB		 476static void txq_reset_hw_ptr(struct tx_queue *txq)
477{
478 struct mv643xx_eth_private *mp = txq_to_mp(txq);
6b368f68
LB		 479 u32 addr;
480
481 addr = (u32)txq->tx_desc_dma;
482 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
37a6084f 483 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
6b368f68
LB		 484}
485
13d64285 486static void txq_enable(struct tx_queue *txq)
1da177e4 487{
13d64285 488 struct mv643xx_eth_private *mp = txq_to_mp(txq);
37a6084f 489 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
1da177e4
LT		 490}
491
13d64285 492static void txq_disable(struct tx_queue *txq)
1da177e4 493{
13d64285 494 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 495 u8 mask = 1 << txq->index;
c9df406f 496
37a6084f
LB		 497 wrlp(mp, TXQ_COMMAND, mask << 8);
498 while (rdlp(mp, TXQ_COMMAND) & mask)
13d64285
LB		 499 udelay(10);
500}
501
1fa38c58 502static void txq_maybe_wake(struct tx_queue *txq)
13d64285
LB		 503{
504 struct mv643xx_eth_private *mp = txq_to_mp(txq);
e5ef1de1 505 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
3d6b35bc 506
8fd89211
LB		 507 if (netif_tx_queue_stopped(nq)) {
508 __netif_tx_lock(nq, smp_processor_id());
509 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
510 netif_tx_wake_queue(nq);
511 __netif_tx_unlock(nq);
512 }
1da177e4
LT		 513}
514
c9df406f 515
1fa38c58 516/* rx napi ******************************************************************/
eaf5d590
LB		 517static int
518mv643xx_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph,
519 u64 *hdr_flags, void *priv)
520{
521 unsigned long cmd_sts = (unsigned long)priv;
522
523 /*
524 * Make sure that this packet is Ethernet II, is not VLAN
525 * tagged, is IPv4, has a valid IP header, and is TCP.
526 */
527 if ((cmd_sts & (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
528 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_MASK |
529 RX_PKT_IS_VLAN_TAGGED)) !=
530 (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
531 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_TCP_IPV4))
532 return -1;
533
534 skb_reset_network_header(skb);
535 skb_set_transport_header(skb, ip_hdrlen(skb));
536 *iphdr = ip_hdr(skb);
537 *tcph = tcp_hdr(skb);
538 *hdr_flags = LRO_IPV4 | LRO_TCP;
539
540 return 0;
541}
eaf5d590 542
8a578111 543static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 544{
8a578111
LB		 545 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
546 struct net_device_stats *stats = &mp->dev->stats;
eaf5d590 547 int lro_flush_needed;
8a578111 548 int rx;
1da177e4 549
eaf5d590 550 lro_flush_needed = 0;
8a578111 551 rx = 0;
9e1f3772 552 while (rx < budget && rxq->rx_desc_count) {
fc32b0e2 553 struct rx_desc *rx_desc;
96587661 554 unsigned int cmd_sts;
fc32b0e2 555 struct sk_buff *skb;
6b8f90c2 556 u16 byte_cnt;
ff561eef 557
8a578111 558 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 559
96587661 560 cmd_sts = rx_desc->cmd_sts;
2257e05c 561 if (cmd_sts & BUFFER_OWNED_BY_DMA)
96587661 562 break;
96587661 563 rmb();
1da177e4 564
8a578111
LB		 565 skb = rxq->rx_skb[rxq->rx_curr_desc];
566 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 567
9da78745
LB		 568 rxq->rx_curr_desc++;
569 if (rxq->rx_curr_desc == rxq->rx_ring_size)
570 rxq->rx_curr_desc = 0;
ff561eef 571
eb0519b5 572 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
abe78717 573 rx_desc->buf_size, DMA_FROM_DEVICE);
8a578111
LB		 574 rxq->rx_desc_count--;
575 rx++;
b1dd9ca1 576
1fa38c58
LB		 577 mp->work_rx_refill |= 1 << rxq->index;
578
6b8f90c2
LB		 579 byte_cnt = rx_desc->byte_cnt;
580
468d09f8
DF		 581 /*
582 * Update statistics.
fc32b0e2
LB		 583 *
584 * Note that the descriptor byte count includes 2 dummy
585 * bytes automatically inserted by the hardware at the
586 * start of the packet (which we don't count), and a 4
587 * byte CRC at the end of the packet (which we do count).
468d09f8 588 */
1da177e4 589 stats->rx_packets++;
6b8f90c2 590 stats->rx_bytes += byte_cnt - 2;
96587661 591
1da177e4 592 /*
fc32b0e2
LB		 593 * In case we received a packet without first / last bits
594 * on, or the error summary bit is set, the packet needs
595 * to be dropped.
1da177e4 596 */
f61e5547
LB		 597 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
598 != (RX_FIRST_DESC | RX_LAST_DESC))
599 goto err;
600
601 /*
602 * The -4 is for the CRC in the trailer of the
603 * received packet
604 */
605 skb_put(skb, byte_cnt - 2 - 4);
606
607 if (cmd_sts & LAYER_4_CHECKSUM_OK)
608 skb->ip_summed = CHECKSUM_UNNECESSARY;
609 skb->protocol = eth_type_trans(skb, mp->dev);
eaf5d590 610
eaf5d590
LB		 611 if (skb->dev->features & NETIF_F_LRO &&
612 skb->ip_summed == CHECKSUM_UNNECESSARY) {
613 lro_receive_skb(&rxq->lro_mgr, skb, (void *)cmd_sts);
614 lro_flush_needed = 1;
615 } else
eaf5d590 616 netif_receive_skb(skb);
f61e5547
LB		 617
618 continue;
619
620err:
621 stats->rx_dropped++;
622
623 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
624 (RX_FIRST_DESC | RX_LAST_DESC)) {
625 if (net_ratelimit())
626 dev_printk(KERN_ERR, &mp->dev->dev,
627 "received packet spanning "
628 "multiple descriptors\n");
1da177e4 629 }
f61e5547
LB		 630
631 if (cmd_sts & ERROR_SUMMARY)
632 stats->rx_errors++;
633
634 dev_kfree_skb(skb);
1da177e4 635 }
fc32b0e2 636
eaf5d590
LB		 637 if (lro_flush_needed)
638 lro_flush_all(&rxq->lro_mgr);
eaf5d590 639
1fa38c58
LB		 640 if (rx < budget)
641 mp->work_rx &= ~(1 << rxq->index);
642
8a578111 643 return rx;
1da177e4
LT		 644}
645
1fa38c58 646static int rxq_refill(struct rx_queue *rxq, int budget)
d0412d96 647{
1fa38c58 648 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1fa38c58 649 int refilled;
8a578111 650
1fa38c58
LB		 651 refilled = 0;
652 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
653 struct sk_buff *skb;
654 int unaligned;
655 int rx;
53771522 656 struct rx_desc *rx_desc;
d0412d96 657
2bcb4b0f
LB		 658 skb = __skb_dequeue(&mp->rx_recycle);
659 if (skb == NULL)
660 skb = dev_alloc_skb(mp->skb_size +
661 dma_get_cache_alignment() - 1);
662
1fa38c58 663 if (skb == NULL) {
1319ebad 664 mp->oom = 1;
1fa38c58
LB		 665 goto oom;
666 }
d0412d96 667
1fa38c58
LB		 668 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
669 if (unaligned)
670 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
2257e05c 671
1fa38c58
LB		 672 refilled++;
673 rxq->rx_desc_count++;
c9df406f 674
1fa38c58
LB		 675 rx = rxq->rx_used_desc++;
676 if (rxq->rx_used_desc == rxq->rx_ring_size)
677 rxq->rx_used_desc = 0;
2257e05c 678
53771522
LB		 679 rx_desc = rxq->rx_desc_area + rx;
680
eb0519b5
GP		 681 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
682 skb->data, mp->skb_size,
683 DMA_FROM_DEVICE);
53771522 684 rx_desc->buf_size = mp->skb_size;
1fa38c58
LB		 685 rxq->rx_skb[rx] = skb;
686 wmb();
53771522 687 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
1fa38c58 688 wmb();
2257e05c 689
1fa38c58
LB		 690 /*
691 * The hardware automatically prepends 2 bytes of
692 * dummy data to each received packet, so that the
693 * IP header ends up 16-byte aligned.
694 */
695 skb_reserve(skb, 2);
696 }
697
698 if (refilled < budget)
699 mp->work_rx_refill &= ~(1 << rxq->index);
700
701oom:
702 return refilled;
d0412d96
JC		 703}
704
c9df406f
LB		 705
706/* tx ***********************************************************************/
c9df406f 707static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 708{
13d64285 709 int frag;
1da177e4 710
c9df406f 711 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
13d64285
LB		 712 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
713 if (fragp->size <= 8 && fragp->page_offset & 7)
c9df406f 714 return 1;
1da177e4 715 }
13d64285 716
c9df406f
LB		 717 return 0;
718}
7303fde8 719
13d64285 720static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 721{
eb0519b5 722 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 723 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 724 int frag;
1da177e4 725
13d64285
LB		 726 for (frag = 0; frag < nr_frags; frag++) {
727 skb_frag_t *this_frag;
728 int tx_index;
729 struct tx_desc *desc;
730
731 this_frag = &skb_shinfo(skb)->frags[frag];
66823b92
LB		 732 tx_index = txq->tx_curr_desc++;
733 if (txq->tx_curr_desc == txq->tx_ring_size)
734 txq->tx_curr_desc = 0;
13d64285
LB		 735 desc = &txq->tx_desc_area[tx_index];
736
737 /*
738 * The last fragment will generate an interrupt
739 * which will free the skb on TX completion.
740 */
741 if (frag == nr_frags - 1) {
742 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
743 ZERO_PADDING | TX_LAST_DESC |
744 TX_ENABLE_INTERRUPT;
13d64285
LB		 745 } else {
746 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
13d64285
LB		 747 }
748
c9df406f
LB		 749 desc->l4i_chk = 0;
750 desc->byte_cnt = this_frag->size;
eb0519b5
GP		 751 desc->buf_ptr = dma_map_page(mp->dev->dev.parent,
752 this_frag->page,
753 this_frag->page_offset,
754 this_frag->size, DMA_TO_DEVICE);
c9df406f 755 }
1da177e4
LT		 756}
757
c9df406f
LB		 758static inline __be16 sum16_as_be(__sum16 sum)
759{
760 return (__force __be16)sum;
761}
1da177e4 762
4df89bd5 763static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 764{
8fa89bf5 765 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 766 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 767 int tx_index;
cc9754b3 768 struct tx_desc *desc;
c9df406f 769 u32 cmd_sts;
4df89bd5 770 u16 l4i_chk;
c9df406f 771 int length;
1da177e4 772
cc9754b3 773 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
4df89bd5 774 l4i_chk = 0;
c9df406f
LB		 775
776 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4df89bd5 777 int tag_bytes;
e32b6617
LB		 778
779 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
780 skb->protocol != htons(ETH_P_8021Q));
c9df406f 781
4df89bd5
LB		 782 tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN;
783 if (unlikely(tag_bytes & ~12)) {
784 if (skb_checksum_help(skb) == 0)
785 goto no_csum;
786 kfree_skb(skb);
787 return 1;
788 }
c9df406f 789
4df89bd5 790 if (tag_bytes & 4)
e32b6617 791 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
4df89bd5 792 if (tag_bytes & 8)
e32b6617 793 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
4df89bd5
LB		 794
795 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
796 GEN_IP_V4_CHECKSUM |
797 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
e32b6617 798
c9df406f
LB		 799 switch (ip_hdr(skb)->protocol) {
800 case IPPROTO_UDP:
cc9754b3 801 cmd_sts |= UDP_FRAME;
4df89bd5 802 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
c9df406f
LB		 803 break;
804 case IPPROTO_TCP:
4df89bd5 805 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
c9df406f
LB		 806 break;
807 default:
808 BUG();
809 }
810 } else {
4df89bd5 811no_csum:
c9df406f 812 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 813 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 814 }
815
66823b92
LB		 816 tx_index = txq->tx_curr_desc++;
817 if (txq->tx_curr_desc == txq->tx_ring_size)
818 txq->tx_curr_desc = 0;
4df89bd5
LB		 819 desc = &txq->tx_desc_area[tx_index];
820
821 if (nr_frags) {
822 txq_submit_frag_skb(txq, skb);
823 length = skb_headlen(skb);
824 } else {
825 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
826 length = skb->len;
827 }
828
829 desc->l4i_chk = l4i_chk;
830 desc->byte_cnt = length;
eb0519b5
GP		 831 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
832 length, DMA_TO_DEVICE);
4df89bd5 833
99ab08e0
LB		 834 __skb_queue_tail(&txq->tx_skb, skb);
835
c9df406f
LB		 836 /* ensure all other descriptors are written before first cmd_sts */
837 wmb();
838 desc->cmd_sts = cmd_sts;
839
1fa38c58
LB		 840 /* clear TX_END status */
841 mp->work_tx_end &= ~(1 << txq->index);
8fa89bf5 842
c9df406f
LB		 843 /* ensure all descriptors are written before poking hardware */
844 wmb();
13d64285 845 txq_enable(txq);
c9df406f 846
13d64285 847 txq->tx_desc_count += nr_frags + 1;
4df89bd5
LB		 848
849 return 0;
1da177e4 850}
1da177e4 851
fc32b0e2 852static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 853{
e5371493 854 struct mv643xx_eth_private *mp = netdev_priv(dev);
e5ef1de1 855 int queue;
13d64285 856 struct tx_queue *txq;
e5ef1de1 857 struct netdev_queue *nq;
afdb57a2 858
8fd89211
LB		 859 queue = skb_get_queue_mapping(skb);
860 txq = mp->txq + queue;
861 nq = netdev_get_tx_queue(dev, queue);
862
c9df406f 863 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
8fd89211 864 txq->tx_dropped++;
fc32b0e2
LB		 865 dev_printk(KERN_DEBUG, &dev->dev,
866 "failed to linearize skb with tiny "
867 "unaligned fragment\n");
c9df406f
LB		 868 return NETDEV_TX_BUSY;
869 }
870
17cd0a59 871 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
e5ef1de1
LB		 872 if (net_ratelimit())
873 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
3d6b35bc
LB		 874 kfree_skb(skb);
875 return NETDEV_TX_OK;
c9df406f
LB		 876 }
877
4df89bd5
LB		 878 if (!txq_submit_skb(txq, skb)) {
879 int entries_left;
880
881 txq->tx_bytes += skb->len;
882 txq->tx_packets++;
883 dev->trans_start = jiffies;
c9df406f 884
4df89bd5
LB		 885 entries_left = txq->tx_ring_size - txq->tx_desc_count;
886 if (entries_left < MAX_SKB_FRAGS + 1)
887 netif_tx_stop_queue(nq);
888 }
c9df406f 889
c9df406f 890 return NETDEV_TX_OK;
1da177e4
LT		 891}
892
c9df406f 893
1fa38c58
LB		 894/* tx napi ******************************************************************/
895static void txq_kick(struct tx_queue *txq)
896{
897 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 898 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 899 u32 hw_desc_ptr;
900 u32 expected_ptr;
901
8fd89211 902 __netif_tx_lock(nq, smp_processor_id());
1fa38c58 903
37a6084f 904 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
1fa38c58
LB		 905 goto out;
906
37a6084f 907 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
1fa38c58
LB		 908 expected_ptr = (u32)txq->tx_desc_dma +
909 txq->tx_curr_desc * sizeof(struct tx_desc);
910
911 if (hw_desc_ptr != expected_ptr)
912 txq_enable(txq);
913
914out:
8fd89211 915 __netif_tx_unlock(nq);
1fa38c58
LB		 916
917 mp->work_tx_end &= ~(1 << txq->index);
918}
919
920static int txq_reclaim(struct tx_queue *txq, int budget, int force)
921{
922 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 923 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 924 int reclaimed;
925
8fd89211 926 __netif_tx_lock(nq, smp_processor_id());
1fa38c58
LB		 927
928 reclaimed = 0;
929 while (reclaimed < budget && txq->tx_desc_count > 0) {
930 int tx_index;
931 struct tx_desc *desc;
932 u32 cmd_sts;
933 struct sk_buff *skb;
1fa38c58
LB		 934
935 tx_index = txq->tx_used_desc;
936 desc = &txq->tx_desc_area[tx_index];
937 cmd_sts = desc->cmd_sts;
938
939 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
940 if (!force)
941 break;
942 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
943 }
944
945 txq->tx_used_desc = tx_index + 1;
946 if (txq->tx_used_desc == txq->tx_ring_size)
947 txq->tx_used_desc = 0;
948
949 reclaimed++;
950 txq->tx_desc_count--;
951
99ab08e0
LB		 952 skb = NULL;
953 if (cmd_sts & TX_LAST_DESC)
954 skb = __skb_dequeue(&txq->tx_skb);
1fa38c58
LB		 955
956 if (cmd_sts & ERROR_SUMMARY) {
957 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
958 mp->dev->stats.tx_errors++;
959 }
960
a418950c 961 if (cmd_sts & TX_FIRST_DESC) {
eb0519b5 962 dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr,
a418950c
LB		 963 desc->byte_cnt, DMA_TO_DEVICE);
964 } else {
eb0519b5 965 dma_unmap_page(mp->dev->dev.parent, desc->buf_ptr,
a418950c
LB		 966 desc->byte_cnt, DMA_TO_DEVICE);
967 }
1fa38c58 968
2bcb4b0f
LB		 969 if (skb != NULL) {
970 if (skb_queue_len(&mp->rx_recycle) <
e7d2f4db 971 mp->rx_ring_size &&
11b4aa03
LB		 972 skb_recycle_check(skb, mp->skb_size +
973 dma_get_cache_alignment() - 1))
2bcb4b0f
LB		 974 __skb_queue_head(&mp->rx_recycle, skb);
975 else
976 dev_kfree_skb(skb);
977 }
1fa38c58
LB		 978 }
979
8fd89211
LB		 980 __netif_tx_unlock(nq);
981
1fa38c58
LB		 982 if (reclaimed < budget)
983 mp->work_tx &= ~(1 << txq->index);
984
1fa38c58
LB		 985 return reclaimed;
986}
987
988
89df5fdc
LB		 989/* tx rate control **********************************************************/
990/*
991 * Set total maximum TX rate (shared by all TX queues for this port)
992 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
993 */
994static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
995{
996 int token_rate;
997 int mtu;
998 int bucket_size;
999
1000 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
1001 if (token_rate > 1023)
1002 token_rate = 1023;
1003
1004 mtu = (mp->dev->mtu + 255) >> 8;
1005 if (mtu > 63)
1006 mtu = 63;
1007
1008 bucket_size = (burst + 255) >> 8;
1009 if (bucket_size > 65535)
1010 bucket_size = 65535;
1011
457b1d5a
LB		 1012 switch (mp->shared->tx_bw_control) {
1013 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f
LB		 1014 wrlp(mp, TX_BW_RATE, token_rate);
1015 wrlp(mp, TX_BW_MTU, mtu);
1016 wrlp(mp, TX_BW_BURST, bucket_size);
457b1d5a
LB		 1017 break;
1018 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f
LB		 1019 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1020 wrlp(mp, TX_BW_MTU_MOVED, mtu);
1021 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
457b1d5a 1022 break;
1e881592 1023 }
89df5fdc
LB		 1024}
1025
1026static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1027{
1028 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1029 int token_rate;
1030 int bucket_size;
1031
1032 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
1033 if (token_rate > 1023)
1034 token_rate = 1023;
1035
1036 bucket_size = (burst + 255) >> 8;
1037 if (bucket_size > 65535)
1038 bucket_size = 65535;
1039
37a6084f
LB		 1040 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1041 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
89df5fdc
LB		 1042}
1043
1044static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1045{
1046 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1047 int off;
1048 u32 val;
1049
1050 /*
1051 * Turn on fixed priority mode.
1052 */
457b1d5a
LB		 1053 off = 0;
1054 switch (mp->shared->tx_bw_control) {
1055 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f 1056 off = TXQ_FIX_PRIO_CONF;
457b1d5a
LB		 1057 break;
1058 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f 1059 off = TXQ_FIX_PRIO_CONF_MOVED;
457b1d5a
LB		 1060 break;
1061 }
89df5fdc 1062
457b1d5a 1063 if (off) {
37a6084f 1064 val = rdlp(mp, off);
457b1d5a 1065 val |= 1 << txq->index;
37a6084f 1066 wrlp(mp, off, val);
457b1d5a 1067 }
89df5fdc
LB		 1068}
1069
1070static void txq_set_wrr(struct tx_queue *txq, int weight)
1071{
1072 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1073 int off;
1074 u32 val;
1075
1076 /*
1077 * Turn off fixed priority mode.
1078 */
457b1d5a
LB		 1079 off = 0;
1080 switch (mp->shared->tx_bw_control) {
1081 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f 1082 off = TXQ_FIX_PRIO_CONF;
457b1d5a
LB		 1083 break;
1084 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f 1085 off = TXQ_FIX_PRIO_CONF_MOVED;
457b1d5a
LB		 1086 break;
1087 }
89df5fdc 1088
457b1d5a 1089 if (off) {
37a6084f 1090 val = rdlp(mp, off);
457b1d5a 1091 val &= ~(1 << txq->index);
37a6084f 1092 wrlp(mp, off, val);
89df5fdc 1093
457b1d5a
LB		 1094 /*
1095 * Configure WRR weight for this queue.
1096 */
89df5fdc 1097
37a6084f 1098 val = rdlp(mp, off);
457b1d5a 1099 val = (val & ~0xff) | (weight & 0xff);
37a6084f 1100 wrlp(mp, TXQ_BW_WRR_CONF(txq->index), val);
457b1d5a 1101 }
89df5fdc
LB		 1102}
1103
1104
c9df406f 1105/* mii management interface *************************************************/
45c5d3bc
LB		 1106static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1107{
1108 struct mv643xx_eth_shared_private *msp = dev_id;
1109
1110 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1111 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1112 wake_up(&msp->smi_busy_wait);
1113 return IRQ_HANDLED;
1114 }
1115
1116 return IRQ_NONE;
1117}
c9df406f 1118
45c5d3bc 1119static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1da177e4 1120{
45c5d3bc
LB		 1121 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1122}
1da177e4 1123
45c5d3bc
LB		 1124static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1125{
1126 if (msp->err_interrupt == NO_IRQ) {
1127 int i;
c9df406f 1128
45c5d3bc
LB		 1129 for (i = 0; !smi_is_done(msp); i++) {
1130 if (i == 10)
1131 return -ETIMEDOUT;
1132 msleep(10);
c9df406f 1133 }
45c5d3bc
LB		 1134
1135 return 0;
1136 }
1137
ee04448d
LB		 1138 if (!smi_is_done(msp)) {
1139 wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1140 msecs_to_jiffies(100));
1141 if (!smi_is_done(msp))
1142 return -ETIMEDOUT;
1143 }
45c5d3bc
LB		 1144
1145 return 0;
1146}
1147
ed94493f 1148static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
45c5d3bc 1149{
ed94493f 1150 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc
LB		 1151 void __iomem *smi_reg = msp->base + SMI_REG;
1152 int ret;
1153
45c5d3bc 1154 if (smi_wait_ready(msp)) {
10a9948d 1155 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f 1156 return -ETIMEDOUT;
1da177e4
LT		 1157 }
1158
fc32b0e2 1159 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 1160
45c5d3bc 1161 if (smi_wait_ready(msp)) {
10a9948d 1162 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f 1163 return -ETIMEDOUT;
45c5d3bc
LB		 1164 }
1165
1166 ret = readl(smi_reg);
1167 if (!(ret & SMI_READ_VALID)) {
10a9948d 1168 printk(KERN_WARNING "mv643xx_eth: SMI bus read not valid\n");
ed94493f 1169 return -ENODEV;
c9df406f
LB		 1170 }
1171
ed94493f 1172 return ret & 0xffff;
1da177e4
LT		 1173}
1174
ed94493f 1175static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
1da177e4 1176{
ed94493f 1177 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc 1178 void __iomem *smi_reg = msp->base + SMI_REG;
1da177e4 1179
45c5d3bc 1180 if (smi_wait_ready(msp)) {
10a9948d 1181 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
45c5d3bc 1182 return -ETIMEDOUT;
1da177e4
LT		 1183 }
1184
fc32b0e2 1185 writel(SMI_OPCODE_WRITE | (reg << 21) |
ed94493f 1186 (addr << 16) | (val & 0xffff), smi_reg);
45c5d3bc 1187
ed94493f 1188 if (smi_wait_ready(msp)) {
10a9948d 1189 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f
LB		 1190 return -ETIMEDOUT;
1191 }
45c5d3bc
LB		 1192
1193 return 0;
c9df406f 1194}
1da177e4 1195
c9df406f 1196
8fd89211
LB		 1197/* statistics ***************************************************************/
1198static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1199{
1200 struct mv643xx_eth_private *mp = netdev_priv(dev);
1201 struct net_device_stats *stats = &dev->stats;
1202 unsigned long tx_packets = 0;
1203 unsigned long tx_bytes = 0;
1204 unsigned long tx_dropped = 0;
1205 int i;
1206
1207 for (i = 0; i < mp->txq_count; i++) {
1208 struct tx_queue *txq = mp->txq + i;
1209
1210 tx_packets += txq->tx_packets;
1211 tx_bytes += txq->tx_bytes;
1212 tx_dropped += txq->tx_dropped;
1213 }
1214
1215 stats->tx_packets = tx_packets;
1216 stats->tx_bytes = tx_bytes;
1217 stats->tx_dropped = tx_dropped;
1218
1219 return stats;
1220}
1221
eaf5d590
LB		 1222static void mv643xx_eth_grab_lro_stats(struct mv643xx_eth_private *mp)
1223{
1224 u32 lro_aggregated = 0;
1225 u32 lro_flushed = 0;
1226 u32 lro_no_desc = 0;
1227 int i;
1228
eaf5d590
LB		 1229 for (i = 0; i < mp->rxq_count; i++) {
1230 struct rx_queue *rxq = mp->rxq + i;
1231
1232 lro_aggregated += rxq->lro_mgr.stats.aggregated;
1233 lro_flushed += rxq->lro_mgr.stats.flushed;
1234 lro_no_desc += rxq->lro_mgr.stats.no_desc;
1235 }
eaf5d590
LB		 1236
1237 mp->lro_counters.lro_aggregated = lro_aggregated;
1238 mp->lro_counters.lro_flushed = lro_flushed;
1239 mp->lro_counters.lro_no_desc = lro_no_desc;
1240}
1241
fc32b0e2 1242static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 1243{
fc32b0e2 1244 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 1245}
1246
fc32b0e2 1247static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 1248{
fc32b0e2
LB		 1249 int i;
1250
1251 for (i = 0; i < 0x80; i += 4)
1252 mib_read(mp, i);
c9df406f 1253}
d0412d96 1254
fc32b0e2 1255static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 1256{
e5371493 1257 struct mib_counters *p = &mp->mib_counters;
4b8e3655 1258
57e8f26a 1259 spin_lock_bh(&mp->mib_counters_lock);
fc32b0e2 1260 p->good_octets_received += mib_read(mp, 0x00);
fc32b0e2
LB		 1261 p->bad_octets_received += mib_read(mp, 0x08);
1262 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1263 p->good_frames_received += mib_read(mp, 0x10);
1264 p->bad_frames_received += mib_read(mp, 0x14);
1265 p->broadcast_frames_received += mib_read(mp, 0x18);
1266 p->multicast_frames_received += mib_read(mp, 0x1c);
1267 p->frames_64_octets += mib_read(mp, 0x20);
1268 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1269 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1270 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1271 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1272 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1273 p->good_octets_sent += mib_read(mp, 0x38);
fc32b0e2
LB		 1274 p->good_frames_sent += mib_read(mp, 0x40);
1275 p->excessive_collision += mib_read(mp, 0x44);
1276 p->multicast_frames_sent += mib_read(mp, 0x48);
1277 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1278 p->unrec_mac_control_received += mib_read(mp, 0x50);
1279 p->fc_sent += mib_read(mp, 0x54);
1280 p->good_fc_received += mib_read(mp, 0x58);
1281 p->bad_fc_received += mib_read(mp, 0x5c);
1282 p->undersize_received += mib_read(mp, 0x60);
1283 p->fragments_received += mib_read(mp, 0x64);
1284 p->oversize_received += mib_read(mp, 0x68);
1285 p->jabber_received += mib_read(mp, 0x6c);
1286 p->mac_receive_error += mib_read(mp, 0x70);
1287 p->bad_crc_event += mib_read(mp, 0x74);
1288 p->collision += mib_read(mp, 0x78);
1289 p->late_collision += mib_read(mp, 0x7c);
57e8f26a 1290 spin_unlock_bh(&mp->mib_counters_lock);
4ff3495a
LB		 1291
1292 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1293}
1294
1295static void mib_counters_timer_wrapper(unsigned long _mp)
1296{
1297 struct mv643xx_eth_private *mp = (void *)_mp;
1298
1299 mib_counters_update(mp);
d0412d96
JC		 1300}
1301
c9df406f 1302
3e508034
LB		 1303/* interrupt coalescing *****************************************************/
1304/*
1305 * Hardware coalescing parameters are set in units of 64 t_clk
1306 * cycles. I.e.:
1307 *
1308 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1309 *
1310 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1311 *
1312 * In the ->set*() methods, we round the computed register value
1313 * to the nearest integer.
1314 */
1315static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1316{
1317 u32 val = rdlp(mp, SDMA_CONFIG);
1318 u64 temp;
1319
1320 if (mp->shared->extended_rx_coal_limit)
1321 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1322 else
1323 temp = (val & 0x003fff00) >> 8;
1324
1325 temp *= 64000000;
1326 do_div(temp, mp->shared->t_clk);
1327
1328 return (unsigned int)temp;
1329}
1330
1331static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1332{
1333 u64 temp;
1334 u32 val;
1335
1336 temp = (u64)usec * mp->shared->t_clk;
1337 temp += 31999999;
1338 do_div(temp, 64000000);
1339
1340 val = rdlp(mp, SDMA_CONFIG);
1341 if (mp->shared->extended_rx_coal_limit) {
1342 if (temp > 0xffff)
1343 temp = 0xffff;
1344 val &= ~0x023fff80;
1345 val |= (temp & 0x8000) << 10;
1346 val |= (temp & 0x7fff) << 7;
1347 } else {
1348 if (temp > 0x3fff)
1349 temp = 0x3fff;
1350 val &= ~0x003fff00;
1351 val |= (temp & 0x3fff) << 8;
1352 }
1353 wrlp(mp, SDMA_CONFIG, val);
1354}
1355
1356static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1357{
1358 u64 temp;
1359
1360 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1361 temp *= 64000000;
1362 do_div(temp, mp->shared->t_clk);
1363
1364 return (unsigned int)temp;
1365}
1366
1367static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1368{
1369 u64 temp;
1370
1371 temp = (u64)usec * mp->shared->t_clk;
1372 temp += 31999999;
1373 do_div(temp, 64000000);
1374
1375 if (temp > 0x3fff)
1376 temp = 0x3fff;
1377
1378 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1379}
1380
1381
c9df406f 1382/* ethtool ******************************************************************/
e5371493 1383struct mv643xx_eth_stats {
c9df406f
LB		 1384 char stat_string[ETH_GSTRING_LEN];
1385 int sizeof_stat;
16820054
LB		 1386 int netdev_off;
1387 int mp_off;
c9df406f
LB		 1388};
1389
16820054
LB		 1390#define SSTAT(m) \
1391 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1392 offsetof(struct net_device, stats.m), -1 }
1393
1394#define MIBSTAT(m) \
1395 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1396 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1397
eaf5d590
LB		 1398#define LROSTAT(m) \
1399 { #m, FIELD_SIZEOF(struct lro_counters, m), \
1400 -1, offsetof(struct mv643xx_eth_private, lro_counters.m) }
1401
16820054
LB		 1402static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1403 SSTAT(rx_packets),
1404 SSTAT(tx_packets),
1405 SSTAT(rx_bytes),
1406 SSTAT(tx_bytes),
1407 SSTAT(rx_errors),
1408 SSTAT(tx_errors),
1409 SSTAT(rx_dropped),
1410 SSTAT(tx_dropped),
1411 MIBSTAT(good_octets_received),
1412 MIBSTAT(bad_octets_received),
1413 MIBSTAT(internal_mac_transmit_err),
1414 MIBSTAT(good_frames_received),
1415 MIBSTAT(bad_frames_received),
1416 MIBSTAT(broadcast_frames_received),
1417 MIBSTAT(multicast_frames_received),
1418 MIBSTAT(frames_64_octets),
1419 MIBSTAT(frames_65_to_127_octets),
1420 MIBSTAT(frames_128_to_255_octets),
1421 MIBSTAT(frames_256_to_511_octets),
1422 MIBSTAT(frames_512_to_1023_octets),
1423 MIBSTAT(frames_1024_to_max_octets),
1424 MIBSTAT(good_octets_sent),
1425 MIBSTAT(good_frames_sent),
1426 MIBSTAT(excessive_collision),
1427 MIBSTAT(multicast_frames_sent),
1428 MIBSTAT(broadcast_frames_sent),
1429 MIBSTAT(unrec_mac_control_received),
1430 MIBSTAT(fc_sent),
1431 MIBSTAT(good_fc_received),
1432 MIBSTAT(bad_fc_received),
1433 MIBSTAT(undersize_received),
1434 MIBSTAT(fragments_received),
1435 MIBSTAT(oversize_received),
1436 MIBSTAT(jabber_received),
1437 MIBSTAT(mac_receive_error),
1438 MIBSTAT(bad_crc_event),
1439 MIBSTAT(collision),
1440 MIBSTAT(late_collision),
eaf5d590
LB		 1441 LROSTAT(lro_aggregated),
1442 LROSTAT(lro_flushed),
1443 LROSTAT(lro_no_desc),
c9df406f
LB		 1444};
1445
10a9948d 1446static int
6bdf576e
LB		 1447mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1448 struct ethtool_cmd *cmd)
d0412d96 1449{
d0412d96
JC		 1450 int err;
1451
ed94493f
LB		 1452 err = phy_read_status(mp->phy);
1453 if (err == 0)
1454 err = phy_ethtool_gset(mp->phy, cmd);
d0412d96 1455
fc32b0e2
LB		 1456 /*
1457 * The MAC does not support 1000baseT_Half.
1458 */
d0412d96
JC		 1459 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1460 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1461
1462 return err;
1463}
1464
10a9948d 1465static int
6bdf576e 1466mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
10a9948d 1467 struct ethtool_cmd *cmd)
bedfe324 1468{
81600eea
LB		 1469 u32 port_status;
1470
37a6084f 1471 port_status = rdlp(mp, PORT_STATUS);
81600eea 1472
bedfe324
LB		 1473 cmd->supported = SUPPORTED_MII;
1474 cmd->advertising = ADVERTISED_MII;
81600eea
LB		 1475 switch (port_status & PORT_SPEED_MASK) {
1476 case PORT_SPEED_10:
1477 cmd->speed = SPEED_10;
1478 break;
1479 case PORT_SPEED_100:
1480 cmd->speed = SPEED_100;
1481 break;
1482 case PORT_SPEED_1000:
1483 cmd->speed = SPEED_1000;
1484 break;
1485 default:
1486 cmd->speed = -1;
1487 break;
1488 }
1489 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
bedfe324
LB		 1490 cmd->port = PORT_MII;
1491 cmd->phy_address = 0;
1492 cmd->transceiver = XCVR_INTERNAL;
1493 cmd->autoneg = AUTONEG_DISABLE;
1494 cmd->maxtxpkt = 1;
1495 cmd->maxrxpkt = 1;
1496
1497 return 0;
1498}
1499
6bdf576e
LB		 1500static int
1501mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1502{
1503 struct mv643xx_eth_private *mp = netdev_priv(dev);
1504
1505 if (mp->phy != NULL)
1506 return mv643xx_eth_get_settings_phy(mp, cmd);
1507 else
1508 return mv643xx_eth_get_settings_phyless(mp, cmd);
1509}
1510
10a9948d
LB		 1511static int
1512mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1513{
e5371493 1514 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6 1515
6bdf576e
LB		 1516 if (mp->phy == NULL)
1517 return -EINVAL;
1518
fc32b0e2
LB		 1519 /*
1520 * The MAC does not support 1000baseT_Half.
1521 */
1522 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1523
ed94493f 1524 return phy_ethtool_sset(mp->phy, cmd);
c9df406f 1525}
1da177e4 1526
fc32b0e2
LB		 1527static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1528 struct ethtool_drvinfo *drvinfo)
c9df406f 1529{
e5371493
LB		 1530 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1531 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 1532 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 1533 strncpy(drvinfo->bus_info, "platform", 32);
16820054 1534 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1535}
1da177e4 1536
fc32b0e2 1537static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1538{
e5371493 1539 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1540
6bdf576e
LB		 1541 if (mp->phy == NULL)
1542 return -EINVAL;
1da177e4 1543
6bdf576e 1544 return genphy_restart_aneg(mp->phy);
bedfe324
LB		 1545}
1546
c9df406f
LB		 1547static u32 mv643xx_eth_get_link(struct net_device *dev)
1548{
ed94493f 1549 return !!netif_carrier_ok(dev);
bedfe324
LB		 1550}
1551
3e508034
LB		 1552static int
1553mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1554{
1555 struct mv643xx_eth_private *mp = netdev_priv(dev);
1556
1557 ec->rx_coalesce_usecs = get_rx_coal(mp);
1558 ec->tx_coalesce_usecs = get_tx_coal(mp);
1559
1560 return 0;
1561}
1562
1563static int
1564mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1565{
1566 struct mv643xx_eth_private *mp = netdev_priv(dev);
1567
1568 set_rx_coal(mp, ec->rx_coalesce_usecs);
1569 set_tx_coal(mp, ec->tx_coalesce_usecs);
1570
1571 return 0;
1572}
1573
e7d2f4db
LB		 1574static void
1575mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1576{
1577 struct mv643xx_eth_private *mp = netdev_priv(dev);
1578
1579 er->rx_max_pending = 4096;
1580 er->tx_max_pending = 4096;
1581 er->rx_mini_max_pending = 0;
1582 er->rx_jumbo_max_pending = 0;
1583
1584 er->rx_pending = mp->rx_ring_size;
1585 er->tx_pending = mp->tx_ring_size;
1586 er->rx_mini_pending = 0;
1587 er->rx_jumbo_pending = 0;
1588}
1589
1590static int
1591mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1592{
1593 struct mv643xx_eth_private *mp = netdev_priv(dev);
1594
1595 if (er->rx_mini_pending || er->rx_jumbo_pending)
1596 return -EINVAL;
1597
1598 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1599 mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096;
1600
1601 if (netif_running(dev)) {
1602 mv643xx_eth_stop(dev);
1603 if (mv643xx_eth_open(dev)) {
1604 dev_printk(KERN_ERR, &dev->dev,
1605 "fatal error on re-opening device after "
1606 "ring param change\n");
1607 return -ENOMEM;
1608 }
1609 }
1610
1611 return 0;
1612}
1613
d888b373
LB		 1614static u32
1615mv643xx_eth_get_rx_csum(struct net_device *dev)
1616{
1617 struct mv643xx_eth_private *mp = netdev_priv(dev);
1618
1619 return !!(rdlp(mp, PORT_CONFIG) & 0x02000000);
1620}
1621
1622static int
1623mv643xx_eth_set_rx_csum(struct net_device *dev, u32 rx_csum)
1624{
1625 struct mv643xx_eth_private *mp = netdev_priv(dev);
1626
1627 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1628
1629 return 0;
1630}
1631
fc32b0e2
LB		 1632static void mv643xx_eth_get_strings(struct net_device *dev,
1633 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1634{
1635 int i;
1da177e4 1636
fc32b0e2
LB		 1637 if (stringset == ETH_SS_STATS) {
1638 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1639 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1640 mv643xx_eth_stats[i].stat_string,
e5371493 1641 ETH_GSTRING_LEN);
c9df406f 1642 }
c9df406f
LB		 1643 }
1644}
1da177e4 1645
fc32b0e2
LB		 1646static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1647 struct ethtool_stats *stats,
1648 uint64_t *data)
c9df406f 1649{
b9873841 1650 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1651 int i;
1da177e4 1652
8fd89211 1653 mv643xx_eth_get_stats(dev);
fc32b0e2 1654 mib_counters_update(mp);
eaf5d590 1655 mv643xx_eth_grab_lro_stats(mp);
1da177e4 1656
16820054
LB		 1657 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1658 const struct mv643xx_eth_stats *stat;
1659 void *p;
1660
1661 stat = mv643xx_eth_stats + i;
1662
1663 if (stat->netdev_off >= 0)
1664 p = ((void *)mp->dev) + stat->netdev_off;
1665 else
1666 p = ((void *)mp) + stat->mp_off;
1667
1668 data[i] = (stat->sizeof_stat == 8) ?
1669 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1670 }
c9df406f 1671}
1da177e4 1672
fc32b0e2 1673static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1674{
fc32b0e2 1675 if (sset == ETH_SS_STATS)
16820054 1676 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1677
1678 return -EOPNOTSUPP;
c9df406f 1679}
1da177e4 1680
e5371493 1681static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1682 .get_settings = mv643xx_eth_get_settings,
1683 .set_settings = mv643xx_eth_set_settings,
1684 .get_drvinfo = mv643xx_eth_get_drvinfo,
1685 .nway_reset = mv643xx_eth_nway_reset,
1686 .get_link = mv643xx_eth_get_link,
3e508034
LB		 1687 .get_coalesce = mv643xx_eth_get_coalesce,
1688 .set_coalesce = mv643xx_eth_set_coalesce,
e7d2f4db
LB		 1689 .get_ringparam = mv643xx_eth_get_ringparam,
1690 .set_ringparam = mv643xx_eth_set_ringparam,
d888b373
LB		 1691 .get_rx_csum = mv643xx_eth_get_rx_csum,
1692 .set_rx_csum = mv643xx_eth_set_rx_csum,
b8df184f 1693 .set_tx_csum = ethtool_op_set_tx_csum,
c9df406f 1694 .set_sg = ethtool_op_set_sg,
fc32b0e2
LB		 1695 .get_strings = mv643xx_eth_get_strings,
1696 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
eaf5d590
LB		 1697 .get_flags = ethtool_op_get_flags,
1698 .set_flags = ethtool_op_set_flags,
e5371493 1699 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1700};
1da177e4 1701
bea3348e 1702
c9df406f 1703/* address handling *********************************************************/
5daffe94 1704static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1705{
66e63ffb
LB		 1706 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1707 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1da177e4 1708
5daffe94
LB		 1709 addr[0] = (mac_h >> 24) & 0xff;
1710 addr[1] = (mac_h >> 16) & 0xff;
1711 addr[2] = (mac_h >> 8) & 0xff;
1712 addr[3] = mac_h & 0xff;
1713 addr[4] = (mac_l >> 8) & 0xff;
1714 addr[5] = mac_l & 0xff;
c9df406f 1715}
1da177e4 1716
66e63ffb 1717static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1718{
66e63ffb
LB		 1719 wrlp(mp, MAC_ADDR_HIGH,
1720 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1721 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
c9df406f 1722}
d0412d96 1723
66e63ffb 1724static u32 uc_addr_filter_mask(struct net_device *dev)
c9df406f 1725{
66e63ffb
LB		 1726 struct dev_addr_list *uc_ptr;
1727 u32 nibbles;
1da177e4 1728
66e63ffb
LB		 1729 if (dev->flags & IFF_PROMISC)
1730 return 0;
1da177e4 1731
66e63ffb
LB		 1732 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1733 for (uc_ptr = dev->uc_list; uc_ptr != NULL; uc_ptr = uc_ptr->next) {
1734 if (memcmp(dev->dev_addr, uc_ptr->da_addr, 5))
1735 return 0;
1736 if ((dev->dev_addr[5] ^ uc_ptr->da_addr[5]) & 0xf0)
1737 return 0;
ff561eef 1738
66e63ffb
LB		 1739 nibbles |= 1 << (uc_ptr->da_addr[5] & 0x0f);
1740 }
1da177e4 1741
66e63ffb 1742 return nibbles;
1da177e4
LT		 1743}
1744
66e63ffb 1745static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1da177e4 1746{
e5371493 1747 struct mv643xx_eth_private *mp = netdev_priv(dev);
66e63ffb
LB		 1748 u32 port_config;
1749 u32 nibbles;
1750 int i;
1da177e4 1751
cc9754b3 1752 uc_addr_set(mp, dev->dev_addr);
1da177e4 1753
66e63ffb
LB		 1754 port_config = rdlp(mp, PORT_CONFIG);
1755 nibbles = uc_addr_filter_mask(dev);
1756 if (!nibbles) {
1757 port_config |= UNICAST_PROMISCUOUS_MODE;
1758 wrlp(mp, PORT_CONFIG, port_config);
1759 return;
1760 }
1761
1762 for (i = 0; i < 16; i += 4) {
1763 int off = UNICAST_TABLE(mp->port_num) + i;
1764 u32 v;
1765
1766 v = 0;
1767 if (nibbles & 1)
1768 v |= 0x00000001;
1769 if (nibbles & 2)
1770 v |= 0x00000100;
1771 if (nibbles & 4)
1772 v |= 0x00010000;
1773 if (nibbles & 8)
1774 v |= 0x01000000;
1775 nibbles >>= 4;
1776
1777 wrl(mp, off, v);
1778 }
1779
1780 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1781 wrlp(mp, PORT_CONFIG, port_config);
1da177e4
LT		 1782}
1783
69876569
LB		 1784static int addr_crc(unsigned char *addr)
1785{
1786 int crc = 0;
1787 int i;
1788
1789 for (i = 0; i < 6; i++) {
1790 int j;
1791
1792 crc = (crc ^ addr[i]) << 8;
1793 for (j = 7; j >= 0; j--) {
1794 if (crc & (0x100 << j))
1795 crc ^= 0x107 << j;
1796 }
1797 }
1798
1799 return crc;
1800}
1801
66e63ffb 1802static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1da177e4 1803{
fc32b0e2 1804 struct mv643xx_eth_private *mp = netdev_priv(dev);
66e63ffb
LB		 1805 u32 *mc_spec;
1806 u32 *mc_other;
fc32b0e2
LB		 1807 struct dev_addr_list *addr;
1808 int i;
c8aaea25 1809
fc32b0e2 1810 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
66e63ffb
LB		 1811 int port_num;
1812 u32 accept;
1813 int i;
c8aaea25 1814
66e63ffb
LB		 1815oom:
1816 port_num = mp->port_num;
1817 accept = 0x01010101;
fc32b0e2
LB		 1818 for (i = 0; i < 0x100; i += 4) {
1819 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1820 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1821 }
1822 return;
1823 }
c8aaea25 1824
82a5bd6a 1825 mc_spec = kmalloc(0x200, GFP_ATOMIC);
66e63ffb
LB		 1826 if (mc_spec == NULL)
1827 goto oom;
1828 mc_other = mc_spec + (0x100 >> 2);
1829
1830 memset(mc_spec, 0, 0x100);
1831 memset(mc_other, 0, 0x100);
1da177e4 1832
fc32b0e2
LB		 1833 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1834 u8 *a = addr->da_addr;
66e63ffb
LB		 1835 u32 *table;
1836 int entry;
1da177e4 1837
fc32b0e2 1838 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
66e63ffb
LB		 1839 table = mc_spec;
1840 entry = a[5];
fc32b0e2 1841 } else {
66e63ffb
LB		 1842 table = mc_other;
1843 entry = addr_crc(a);
fc32b0e2 1844 }
66e63ffb 1845
2b448334 1846 table[entry >> 2] |= 1 << (8 * (entry & 3));
fc32b0e2 1847 }
66e63ffb
LB		 1848
1849 for (i = 0; i < 0x100; i += 4) {
1850 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1851 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1852 }
1853
1854 kfree(mc_spec);
1855}
1856
1857static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1858{
1859 mv643xx_eth_program_unicast_filter(dev);
1860 mv643xx_eth_program_multicast_filter(dev);
1861}
1862
1863static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1864{
1865 struct sockaddr *sa = addr;
1866
1867 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1868
1869 netif_addr_lock_bh(dev);
1870 mv643xx_eth_program_unicast_filter(dev);
1871 netif_addr_unlock_bh(dev);
1872
1873 return 0;
c9df406f 1874}
c8aaea25 1875
c8aaea25 1876
c9df406f 1877/* rx/tx queue initialisation ***********************************************/
64da80a2 1878static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1879{
64da80a2 1880 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1881 struct rx_desc *rx_desc;
1882 int size;
c9df406f
LB		 1883 int i;
1884
64da80a2
LB		 1885 rxq->index = index;
1886
e7d2f4db 1887 rxq->rx_ring_size = mp->rx_ring_size;
8a578111
LB		 1888
1889 rxq->rx_desc_count = 0;
1890 rxq->rx_curr_desc = 0;
1891 rxq->rx_used_desc = 0;
1892
1893 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1894
f7981c1c 1895 if (index == 0 && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1896 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1897 mp->rx_desc_sram_size);
1898 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1899 } else {
eb0519b5
GP		 1900 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1901 size, &rxq->rx_desc_dma,
1902 GFP_KERNEL);
f7ea3337
PJ		 1903 }
1904
8a578111
LB		 1905 if (rxq->rx_desc_area == NULL) {
1906 dev_printk(KERN_ERR, &mp->dev->dev,
1907 "can't allocate rx ring (%d bytes)\n", size);
1908 goto out;
1909 }
1910 memset(rxq->rx_desc_area, 0, size);
1da177e4 1911
8a578111
LB		 1912 rxq->rx_desc_area_size = size;
1913 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1914 GFP_KERNEL);
1915 if (rxq->rx_skb == NULL) {
1916 dev_printk(KERN_ERR, &mp->dev->dev,
1917 "can't allocate rx skb ring\n");
1918 goto out_free;
1919 }
1920
1921 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1922 for (i = 0; i < rxq->rx_ring_size; i++) {
9da78745
LB		 1923 int nexti;
1924
1925 nexti = i + 1;
1926 if (nexti == rxq->rx_ring_size)
1927 nexti = 0;
1928
8a578111
LB		 1929 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1930 nexti * sizeof(struct rx_desc);
1931 }
1932
eaf5d590
LB		 1933 rxq->lro_mgr.dev = mp->dev;
1934 memset(&rxq->lro_mgr.stats, 0, sizeof(rxq->lro_mgr.stats));
1935 rxq->lro_mgr.features = LRO_F_NAPI;
1936 rxq->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1937 rxq->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1938 rxq->lro_mgr.max_desc = ARRAY_SIZE(rxq->lro_arr);
1939 rxq->lro_mgr.max_aggr = 32;
1940 rxq->lro_mgr.frag_align_pad = 0;
1941 rxq->lro_mgr.lro_arr = rxq->lro_arr;
1942 rxq->lro_mgr.get_skb_header = mv643xx_get_skb_header;
1943
1944 memset(&rxq->lro_arr, 0, sizeof(rxq->lro_arr));
eaf5d590 1945
8a578111
LB		 1946 return 0;
1947
1948
1949out_free:
f7981c1c 1950 if (index == 0 && size <= mp->rx_desc_sram_size)
8a578111
LB		 1951 iounmap(rxq->rx_desc_area);
1952 else
eb0519b5 1953 dma_free_coherent(mp->dev->dev.parent, size,
8a578111
LB		 1954 rxq->rx_desc_area,
1955 rxq->rx_desc_dma);
1956
1957out:
1958 return -ENOMEM;
c9df406f 1959}
c8aaea25 1960
8a578111 1961static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1962{
8a578111
LB		 1963 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1964 int i;
1965
1966 rxq_disable(rxq);
c8aaea25 1967
8a578111
LB		 1968 for (i = 0; i < rxq->rx_ring_size; i++) {
1969 if (rxq->rx_skb[i]) {
1970 dev_kfree_skb(rxq->rx_skb[i]);
1971 rxq->rx_desc_count--;
1da177e4 1972 }
c8aaea25 1973 }
1da177e4 1974
8a578111
LB		 1975 if (rxq->rx_desc_count) {
1976 dev_printk(KERN_ERR, &mp->dev->dev,
1977 "error freeing rx ring -- %d skbs stuck\n",
1978 rxq->rx_desc_count);
1979 }
1980
f7981c1c 1981 if (rxq->index == 0 &&
64da80a2 1982 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1983 iounmap(rxq->rx_desc_area);
c9df406f 1984 else
eb0519b5 1985 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
8a578111
LB		 1986 rxq->rx_desc_area, rxq->rx_desc_dma);
1987
1988 kfree(rxq->rx_skb);
c9df406f 1989}
1da177e4 1990
3d6b35bc 1991static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1992{
3d6b35bc 1993 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1994 struct tx_desc *tx_desc;
1995 int size;
c9df406f 1996 int i;
1da177e4 1997
3d6b35bc
LB		 1998 txq->index = index;
1999
e7d2f4db 2000 txq->tx_ring_size = mp->tx_ring_size;
13d64285
LB		 2001
2002 txq->tx_desc_count = 0;
2003 txq->tx_curr_desc = 0;
2004 txq->tx_used_desc = 0;
2005
2006 size = txq->tx_ring_size * sizeof(struct tx_desc);
2007
f7981c1c 2008 if (index == 0 && size <= mp->tx_desc_sram_size) {
13d64285
LB		 2009 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
2010 mp->tx_desc_sram_size);
2011 txq->tx_desc_dma = mp->tx_desc_sram_addr;
2012 } else {
eb0519b5
GP		 2013 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
2014 size, &txq->tx_desc_dma,
2015 GFP_KERNEL);
13d64285
LB		 2016 }
2017
2018 if (txq->tx_desc_area == NULL) {
2019 dev_printk(KERN_ERR, &mp->dev->dev,
2020 "can't allocate tx ring (%d bytes)\n", size);
99ab08e0 2021 return -ENOMEM;
c9df406f 2022 }
13d64285
LB		 2023 memset(txq->tx_desc_area, 0, size);
2024
2025 txq->tx_desc_area_size = size;
13d64285
LB		 2026
2027 tx_desc = (struct tx_desc *)txq->tx_desc_area;
2028 for (i = 0; i < txq->tx_ring_size; i++) {
6b368f68 2029 struct tx_desc *txd = tx_desc + i;
9da78745
LB		 2030 int nexti;
2031
2032 nexti = i + 1;
2033 if (nexti == txq->tx_ring_size)
2034 nexti = 0;
6b368f68
LB		 2035
2036 txd->cmd_sts = 0;
2037 txd->next_desc_ptr = txq->tx_desc_dma +
13d64285
LB		 2038 nexti * sizeof(struct tx_desc);
2039 }
2040
99ab08e0 2041 skb_queue_head_init(&txq->tx_skb);
c9df406f 2042
99ab08e0 2043 return 0;
c8aaea25 2044}
1da177e4 2045
13d64285 2046static void txq_deinit(struct tx_queue *txq)
c9df406f 2047{
13d64285 2048 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 2049
13d64285 2050 txq_disable(txq);
1fa38c58 2051 txq_reclaim(txq, txq->tx_ring_size, 1);
1da177e4 2052
13d64285 2053 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 2054
f7981c1c 2055 if (txq->index == 0 &&
3d6b35bc 2056 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 2057 iounmap(txq->tx_desc_area);
c9df406f 2058 else
eb0519b5 2059 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
13d64285 2060 txq->tx_desc_area, txq->tx_desc_dma);
c9df406f 2061}
1da177e4 2062
1da177e4 2063
c9df406f 2064/* netdev ops and related ***************************************************/
1fa38c58
LB		 2065static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
2066{
2067 u32 int_cause;
2068 u32 int_cause_ext;
2069
37a6084f 2070 int_cause = rdlp(mp, INT_CAUSE) & (INT_TX_END | INT_RX | INT_EXT);
1fa38c58
LB		 2071 if (int_cause == 0)
2072 return 0;
2073
2074 int_cause_ext = 0;
2075 if (int_cause & INT_EXT)
37a6084f 2076 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
1fa38c58
LB		 2077
2078 int_cause &= INT_TX_END | INT_RX;
2079 if (int_cause) {
37a6084f 2080 wrlp(mp, INT_CAUSE, ~int_cause);
1fa38c58 2081 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
37a6084f 2082 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
1fa38c58
LB		 2083 mp->work_rx |= (int_cause & INT_RX) >> 2;
2084 }
2085
2086 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2087 if (int_cause_ext) {
37a6084f 2088 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
1fa38c58
LB		 2089 if (int_cause_ext & INT_EXT_LINK_PHY)
2090 mp->work_link = 1;
2091 mp->work_tx |= int_cause_ext & INT_EXT_TX;
2092 }
2093
2094 return 1;
2095}
2096
2097static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2098{
2099 struct net_device *dev = (struct net_device *)dev_id;
2100 struct mv643xx_eth_private *mp = netdev_priv(dev);
2101
2102 if (unlikely(!mv643xx_eth_collect_events(mp)))
2103 return IRQ_NONE;
2104
37a6084f 2105 wrlp(mp, INT_MASK, 0);
1fa38c58
LB		 2106 napi_schedule(&mp->napi);
2107
2108 return IRQ_HANDLED;
2109}
2110
2f7eb47a
LB		 2111static void handle_link_event(struct mv643xx_eth_private *mp)
2112{
2113 struct net_device *dev = mp->dev;
2114 u32 port_status;
2115 int speed;
2116 int duplex;
2117 int fc;
2118
37a6084f 2119 port_status = rdlp(mp, PORT_STATUS);
2f7eb47a
LB		 2120 if (!(port_status & LINK_UP)) {
2121 if (netif_carrier_ok(dev)) {
2122 int i;
2123
2124 printk(KERN_INFO "%s: link down\n", dev->name);
2125
2126 netif_carrier_off(dev);
2f7eb47a 2127
f7981c1c 2128 for (i = 0; i < mp->txq_count; i++) {
2f7eb47a
LB		 2129 struct tx_queue *txq = mp->txq + i;
2130
1fa38c58 2131 txq_reclaim(txq, txq->tx_ring_size, 1);
f7981c1c 2132 txq_reset_hw_ptr(txq);
2f7eb47a
LB		 2133 }
2134 }
2135 return;
2136 }
2137
2138 switch (port_status & PORT_SPEED_MASK) {
2139 case PORT_SPEED_10:
2140 speed = 10;
2141 break;
2142 case PORT_SPEED_100:
2143 speed = 100;
2144 break;
2145 case PORT_SPEED_1000:
2146 speed = 1000;
2147 break;
2148 default:
2149 speed = -1;
2150 break;
2151 }
2152 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2153 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2154
2155 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
2156 "flow control %sabled\n", dev->name,
2157 speed, duplex ? "full" : "half",
2158 fc ? "en" : "dis");
2159
4fdeca3f 2160 if (!netif_carrier_ok(dev))
2f7eb47a 2161 netif_carrier_on(dev);
2f7eb47a
LB		 2162}
2163
1fa38c58 2164static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
c9df406f 2165{
1fa38c58
LB		 2166 struct mv643xx_eth_private *mp;
2167 int work_done;
ce4e2e45 2168
1fa38c58 2169 mp = container_of(napi, struct mv643xx_eth_private, napi);
fc32b0e2 2170
1319ebad
LB		 2171 if (unlikely(mp->oom)) {
2172 mp->oom = 0;
2173 del_timer(&mp->rx_oom);
2174 }
1da177e4 2175
1fa38c58
LB		 2176 work_done = 0;
2177 while (work_done < budget) {
2178 u8 queue_mask;
2179 int queue;
2180 int work_tbd;
2181
2182 if (mp->work_link) {
2183 mp->work_link = 0;
2184 handle_link_event(mp);
2185 continue;
2186 }
1da177e4 2187
1319ebad
LB		 2188 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2189 if (likely(!mp->oom))
2190 queue_mask |= mp->work_rx_refill;
2191
1fa38c58
LB		 2192 if (!queue_mask) {
2193 if (mv643xx_eth_collect_events(mp))
2194 continue;
2195 break;
2196 }
1da177e4 2197
1fa38c58
LB		 2198 queue = fls(queue_mask) - 1;
2199 queue_mask = 1 << queue;
2200
2201 work_tbd = budget - work_done;
2202 if (work_tbd > 16)
2203 work_tbd = 16;
2204
2205 if (mp->work_tx_end & queue_mask) {
2206 txq_kick(mp->txq + queue);
2207 } else if (mp->work_tx & queue_mask) {
2208 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2209 txq_maybe_wake(mp->txq + queue);
2210 } else if (mp->work_rx & queue_mask) {
2211 work_done += rxq_process(mp->rxq + queue, work_tbd);
1319ebad 2212 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
1fa38c58
LB		 2213 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2214 } else {
2215 BUG();
2216 }
84dd619e 2217 }
fc32b0e2 2218
1fa38c58 2219 if (work_done < budget) {
1319ebad 2220 if (mp->oom)
1fa38c58
LB		 2221 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2222 napi_complete(napi);
37a6084f 2223 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
226bb6b7 2224 }
3d6b35bc 2225
1fa38c58
LB		 2226 return work_done;
2227}
8fa89bf5 2228
1fa38c58
LB		 2229static inline void oom_timer_wrapper(unsigned long data)
2230{
2231 struct mv643xx_eth_private *mp = (void *)data;
1da177e4 2232
1fa38c58 2233 napi_schedule(&mp->napi);
1da177e4
LT		 2234}
2235
e5371493 2236static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 2237{
45c5d3bc
LB		 2238 int data;
2239
ed94493f 2240 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc
LB		 2241 if (data < 0)
2242 return;
1da177e4 2243
7f106c1d 2244 data |= BMCR_RESET;
ed94493f 2245 if (phy_write(mp->phy, MII_BMCR, data) < 0)
45c5d3bc 2246 return;
1da177e4 2247
c9df406f 2248 do {
ed94493f 2249 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc 2250 } while (data >= 0 && data & BMCR_RESET);
1da177e4
LT		 2251}
2252
fc32b0e2 2253static void port_start(struct mv643xx_eth_private *mp)
1da177e4 2254{
d0412d96 2255 u32 pscr;
8a578111 2256 int i;
1da177e4 2257
bedfe324
LB		 2258 /*
2259 * Perform PHY reset, if there is a PHY.
2260 */
ed94493f 2261 if (mp->phy != NULL) {
bedfe324
LB		 2262 struct ethtool_cmd cmd;
2263
2264 mv643xx_eth_get_settings(mp->dev, &cmd);
2265 phy_reset(mp);
2266 mv643xx_eth_set_settings(mp->dev, &cmd);
2267 }
1da177e4 2268
81600eea
LB		 2269 /*
2270 * Configure basic link parameters.
2271 */
37a6084f 2272 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 2273
2274 pscr |= SERIAL_PORT_ENABLE;
37a6084f 2275 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2276
2277 pscr |= DO_NOT_FORCE_LINK_FAIL;
ed94493f 2278 if (mp->phy == NULL)
81600eea 2279 pscr |= FORCE_LINK_PASS;
37a6084f 2280 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea 2281
13d64285
LB		 2282 /*
2283 * Configure TX path and queues.
2284 */
89df5fdc 2285 tx_set_rate(mp, 1000000000, 16777216);
f7981c1c 2286 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc 2287 struct tx_queue *txq = mp->txq + i;
13d64285 2288
6b368f68 2289 txq_reset_hw_ptr(txq);
89df5fdc
LB		 2290 txq_set_rate(txq, 1000000000, 16777216);
2291 txq_set_fixed_prio_mode(txq);
13d64285
LB		 2292 }
2293
d9a073ea
LB		 2294 /*
2295 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
170e7108
LB		 2296 * frames to RX queue #0, and include the pseudo-header when
2297 * calculating receive checksums.
d9a073ea 2298 */
37a6084f 2299 wrlp(mp, PORT_CONFIG, 0x02000000);
01999873 2300
376489a2
LB		 2301 /*
2302 * Treat BPDUs as normal multicasts, and disable partition mode.
2303 */
37a6084f 2304 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
01999873 2305
5a893922
LB		 2306 /*
2307 * Add configured unicast addresses to address filter table.
2308 */
2309 mv643xx_eth_program_unicast_filter(mp->dev);
2310
8a578111 2311 /*
64da80a2 2312 * Enable the receive queues.
8a578111 2313 */
f7981c1c 2314 for (i = 0; i < mp->rxq_count; i++) {
64da80a2 2315 struct rx_queue *rxq = mp->rxq + i;
8a578111 2316 u32 addr;
1da177e4 2317
8a578111
LB		 2318 addr = (u32)rxq->rx_desc_dma;
2319 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
37a6084f 2320 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
1da177e4 2321
8a578111
LB		 2322 rxq_enable(rxq);
2323 }
1da177e4
LT		 2324}
2325
2bcb4b0f
LB		 2326static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2327{
2328 int skb_size;
2329
2330 /*
2331 * Reserve 2+14 bytes for an ethernet header (the hardware
2332 * automatically prepends 2 bytes of dummy data to each
2333 * received packet), 16 bytes for up to four VLAN tags, and
2334 * 4 bytes for the trailing FCS -- 36 bytes total.
2335 */
2336 skb_size = mp->dev->mtu + 36;
2337
2338 /*
2339 * Make sure that the skb size is a multiple of 8 bytes, as
2340 * the lower three bits of the receive descriptor's buffer
2341 * size field are ignored by the hardware.
2342 */
2343 mp->skb_size = (skb_size + 7) & ~7;
2344}
2345
c9df406f 2346static int mv643xx_eth_open(struct net_device *dev)
16e03018 2347{
e5371493 2348 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2349 int err;
64da80a2 2350 int i;
16e03018 2351
37a6084f
LB		 2352 wrlp(mp, INT_CAUSE, 0);
2353 wrlp(mp, INT_CAUSE_EXT, 0);
2354 rdlp(mp, INT_CAUSE_EXT);
c9df406f 2355
fc32b0e2 2356 err = request_irq(dev->irq, mv643xx_eth_irq,
2a1867a7 2357 IRQF_SHARED, dev->name, dev);
c9df406f 2358 if (err) {
fc32b0e2 2359 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
c9df406f 2360 return -EAGAIN;
16e03018
DF		 2361 }
2362
2bcb4b0f
LB		 2363 mv643xx_eth_recalc_skb_size(mp);
2364
2257e05c
LB		 2365 napi_enable(&mp->napi);
2366
2bcb4b0f
LB		 2367 skb_queue_head_init(&mp->rx_recycle);
2368
f7981c1c 2369 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 2370 err = rxq_init(mp, i);
2371 if (err) {
2372 while (--i >= 0)
f7981c1c 2373 rxq_deinit(mp->rxq + i);
64da80a2
LB		 2374 goto out;
2375 }
2376
1fa38c58 2377 rxq_refill(mp->rxq + i, INT_MAX);
2257e05c
LB		 2378 }
2379
1319ebad 2380 if (mp->oom) {
2257e05c
LB		 2381 mp->rx_oom.expires = jiffies + (HZ / 10);
2382 add_timer(&mp->rx_oom);
64da80a2 2383 }
8a578111 2384
f7981c1c 2385 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc
LB		 2386 err = txq_init(mp, i);
2387 if (err) {
2388 while (--i >= 0)
f7981c1c 2389 txq_deinit(mp->txq + i);
3d6b35bc
LB		 2390 goto out_free;
2391 }
2392 }
16e03018 2393
fc32b0e2 2394 port_start(mp);
16e03018 2395
37a6084f
LB		 2396 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2397 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
16e03018 2398
c9df406f
LB		 2399 return 0;
2400
13d64285 2401
fc32b0e2 2402out_free:
f7981c1c
LB		 2403 for (i = 0; i < mp->rxq_count; i++)
2404 rxq_deinit(mp->rxq + i);
fc32b0e2 2405out:
c9df406f
LB		 2406 free_irq(dev->irq, dev);
2407
2408 return err;
16e03018
DF		 2409}
2410
e5371493 2411static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 2412{
fc32b0e2 2413 unsigned int data;
64da80a2 2414 int i;
1da177e4 2415
f7981c1c
LB		 2416 for (i = 0; i < mp->rxq_count; i++)
2417 rxq_disable(mp->rxq + i);
2418 for (i = 0; i < mp->txq_count; i++)
2419 txq_disable(mp->txq + i);
ae9ae064
LB		 2420
2421 while (1) {
37a6084f 2422 u32 ps = rdlp(mp, PORT_STATUS);
ae9ae064
LB		 2423
2424 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2425 break;
13d64285 2426 udelay(10);
ae9ae064 2427 }
1da177e4 2428
c9df406f 2429 /* Reset the Enable bit in the Configuration Register */
37a6084f 2430 data = rdlp(mp, PORT_SERIAL_CONTROL);
fc32b0e2
LB		 2431 data &= ~(SERIAL_PORT_ENABLE |
2432 DO_NOT_FORCE_LINK_FAIL |
2433 FORCE_LINK_PASS);
37a6084f 2434 wrlp(mp, PORT_SERIAL_CONTROL, data);
1da177e4
LT		 2435}
2436
c9df406f 2437static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 2438{
e5371493 2439 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 2440 int i;
1da177e4 2441
fe65e704 2442 wrlp(mp, INT_MASK_EXT, 0x00000000);
37a6084f
LB		 2443 wrlp(mp, INT_MASK, 0x00000000);
2444 rdlp(mp, INT_MASK);
1da177e4 2445
c9df406f 2446 napi_disable(&mp->napi);
78fff83b 2447
2257e05c
LB		 2448 del_timer_sync(&mp->rx_oom);
2449
c9df406f 2450 netif_carrier_off(dev);
1da177e4 2451
fc32b0e2
LB		 2452 free_irq(dev->irq, dev);
2453
cc9754b3 2454 port_reset(mp);
8fd89211 2455 mv643xx_eth_get_stats(dev);
fc32b0e2 2456 mib_counters_update(mp);
57e8f26a 2457 del_timer_sync(&mp->mib_counters_timer);
1da177e4 2458
2bcb4b0f
LB		 2459 skb_queue_purge(&mp->rx_recycle);
2460
f7981c1c
LB		 2461 for (i = 0; i < mp->rxq_count; i++)
2462 rxq_deinit(mp->rxq + i);
2463 for (i = 0; i < mp->txq_count; i++)
2464 txq_deinit(mp->txq + i);
1da177e4 2465
c9df406f 2466 return 0;
1da177e4
LT		 2467}
2468
fc32b0e2 2469static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 2470{
e5371493 2471 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2472
ed94493f
LB		 2473 if (mp->phy != NULL)
2474 return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd);
bedfe324
LB		 2475
2476 return -EOPNOTSUPP;
1da177e4
LT		 2477}
2478
c9df406f 2479static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 2480{
89df5fdc
LB		 2481 struct mv643xx_eth_private *mp = netdev_priv(dev);
2482
fc32b0e2 2483 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 2484 return -EINVAL;
1da177e4 2485
c9df406f 2486 dev->mtu = new_mtu;
2bcb4b0f 2487 mv643xx_eth_recalc_skb_size(mp);
89df5fdc
LB		 2488 tx_set_rate(mp, 1000000000, 16777216);
2489
c9df406f
LB		 2490 if (!netif_running(dev))
2491 return 0;
1da177e4 2492
c9df406f
LB		 2493 /*
2494 * Stop and then re-open the interface. This will allocate RX
2495 * skbs of the new MTU.
2496 * There is a possible danger that the open will not succeed,
fc32b0e2 2497 * due to memory being full.
c9df406f
LB		 2498 */
2499 mv643xx_eth_stop(dev);
2500 if (mv643xx_eth_open(dev)) {
fc32b0e2
LB		 2501 dev_printk(KERN_ERR, &dev->dev,
2502 "fatal error on re-opening device after "
2503 "MTU change\n");
c9df406f
LB		 2504 }
2505
2506 return 0;
1da177e4
LT		 2507}
2508
fc32b0e2 2509static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2510{
fc32b0e2 2511 struct mv643xx_eth_private *mp;
1da177e4 2512
fc32b0e2
LB		 2513 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2514 if (netif_running(mp->dev)) {
e5ef1de1 2515 netif_tx_stop_all_queues(mp->dev);
fc32b0e2
LB		 2516 port_reset(mp);
2517 port_start(mp);
e5ef1de1 2518 netif_tx_wake_all_queues(mp->dev);
fc32b0e2 2519 }
c9df406f
LB		 2520}
2521
c9df406f 2522static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2523{
e5371493 2524 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2525
fc32b0e2 2526 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
d0412d96 2527
c9df406f 2528 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2529}
2530
c9df406f 2531#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2532static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2533{
fc32b0e2 2534 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2535
37a6084f
LB		 2536 wrlp(mp, INT_MASK, 0x00000000);
2537 rdlp(mp, INT_MASK);
c9df406f 2538
fc32b0e2 2539 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2540
37a6084f 2541 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
9f8dd319 2542}
c9df406f 2543#endif
9f8dd319 2544
9f8dd319 2545
c9df406f 2546/* platform glue ************************************************************/
e5371493
LB		 2547static void
2548mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2549 struct mbus_dram_target_info *dram)
c9df406f 2550{
cc9754b3 2551 void __iomem *base = msp->base;
c9df406f
LB		 2552 u32 win_enable;
2553 u32 win_protect;
2554 int i;
9f8dd319 2555
c9df406f
LB		 2556 for (i = 0; i < 6; i++) {
2557 writel(0, base + WINDOW_BASE(i));
2558 writel(0, base + WINDOW_SIZE(i));
2559 if (i < 4)
2560 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2561 }
2562
c9df406f
LB		 2563 win_enable = 0x3f;
2564 win_protect = 0;
2565
2566 for (i = 0; i < dram->num_cs; i++) {
2567 struct mbus_dram_window *cs = dram->cs + i;
2568
2569 writel((cs->base & 0xffff0000) |
2570 (cs->mbus_attr << 8) |
2571 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2572 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2573
2574 win_enable &= ~(1 << i);
2575 win_protect |= 3 << (2 * i);
2576 }
2577
2578 writel(win_enable, base + WINDOW_BAR_ENABLE);
2579 msp->win_protect = win_protect;
9f8dd319
DF		 2580}
2581
773fc3ee
LB		 2582static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2583{
2584 /*
2585 * Check whether we have a 14-bit coal limit field in bits
2586 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2587 * SDMA config register.
2588 */
37a6084f
LB		 2589 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2590 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
773fc3ee
LB		 2591 msp->extended_rx_coal_limit = 1;
2592 else
2593 msp->extended_rx_coal_limit = 0;
1e881592
LB		 2594
2595 /*
457b1d5a
LB		 2596 * Check whether the MAC supports TX rate control, and if
2597 * yes, whether its associated registers are in the old or
2598 * the new place.
1e881592 2599 */
37a6084f
LB		 2600 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2601 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
457b1d5a
LB		 2602 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2603 } else {
37a6084f
LB		 2604 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2605 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
457b1d5a
LB		 2606 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2607 else
2608 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2609 }
773fc3ee
LB		 2610}
2611
c9df406f 2612static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2613{
10a9948d 2614 static int mv643xx_eth_version_printed;
c9df406f 2615 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2616 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 2617 struct resource *res;
2618 int ret;
9f8dd319 2619
e5371493 2620 if (!mv643xx_eth_version_printed++)
7dde154d
LB		 2621 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2622 "driver version %s\n", mv643xx_eth_driver_version);
9f8dd319 2623
c9df406f
LB		 2624 ret = -EINVAL;
2625 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2626 if (res == NULL)
2627 goto out;
9f8dd319 2628
c9df406f
LB		 2629 ret = -ENOMEM;
2630 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2631 if (msp == NULL)
2632 goto out;
2633 memset(msp, 0, sizeof(*msp));
2634
cc9754b3
LB		 2635 msp->base = ioremap(res->start, res->end - res->start + 1);
2636 if (msp->base == NULL)
c9df406f
LB		 2637 goto out_free;
2638
ed94493f
LB		 2639 /*
2640 * Set up and register SMI bus.
2641 */
2642 if (pd == NULL || pd->shared_smi == NULL) {
298cf9be
LB		 2643 msp->smi_bus = mdiobus_alloc();
2644 if (msp->smi_bus == NULL)
ed94493f 2645 goto out_unmap;
298cf9be
LB		 2646
2647 msp->smi_bus->priv = msp;
2648 msp->smi_bus->name = "mv643xx_eth smi";
2649 msp->smi_bus->read = smi_bus_read;
2650 msp->smi_bus->write = smi_bus_write,
2651 snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
2652 msp->smi_bus->parent = &pdev->dev;
2653 msp->smi_bus->phy_mask = 0xffffffff;
2654 if (mdiobus_register(msp->smi_bus) < 0)
2655 goto out_free_mii_bus;
ed94493f
LB		 2656 msp->smi = msp;
2657 } else {
fc0eb9f2 2658 msp->smi = platform_get_drvdata(pd->shared_smi);
ed94493f 2659 }
c9df406f 2660
45c5d3bc
LB		 2661 msp->err_interrupt = NO_IRQ;
2662 init_waitqueue_head(&msp->smi_busy_wait);
2663
2664 /*
2665 * Check whether the error interrupt is hooked up.
2666 */
2667 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2668 if (res != NULL) {
2669 int err;
2670
2671 err = request_irq(res->start, mv643xx_eth_err_irq,
2672 IRQF_SHARED, "mv643xx_eth", msp);
2673 if (!err) {
2674 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2675 msp->err_interrupt = res->start;
2676 }
2677 }
2678
c9df406f
LB		 2679 /*
2680 * (Re-)program MBUS remapping windows if we are asked to.
2681 */
2682 if (pd != NULL && pd->dram != NULL)
2683 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2684
fc32b0e2
LB		 2685 /*
2686 * Detect hardware parameters.
2687 */
2688 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
773fc3ee 2689 infer_hw_params(msp);
fc32b0e2
LB		 2690
2691 platform_set_drvdata(pdev, msp);
2692
c9df406f
LB		 2693 return 0;
2694
298cf9be
LB		 2695out_free_mii_bus:
2696 mdiobus_free(msp->smi_bus);
ed94493f
LB		 2697out_unmap:
2698 iounmap(msp->base);
c9df406f
LB		 2699out_free:
2700 kfree(msp);
2701out:
2702 return ret;
2703}
2704
2705static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2706{
e5371493 2707 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
ed94493f 2708 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
c9df406f 2709
298cf9be 2710 if (pd == NULL || pd->shared_smi == NULL) {
298cf9be 2711 mdiobus_unregister(msp->smi_bus);
bcb3336c 2712 mdiobus_free(msp->smi_bus);
298cf9be 2713 }
45c5d3bc
LB		 2714 if (msp->err_interrupt != NO_IRQ)
2715 free_irq(msp->err_interrupt, msp);
cc9754b3 2716 iounmap(msp->base);
c9df406f
LB		 2717 kfree(msp);
2718
2719 return 0;
9f8dd319
DF		 2720}
2721
c9df406f 2722static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2723 .probe = mv643xx_eth_shared_probe,
2724 .remove = mv643xx_eth_shared_remove,
c9df406f 2725 .driver = {
fc32b0e2 2726 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2727 .owner = THIS_MODULE,
2728 },
2729};
2730
e5371493 2731static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2732{
c9df406f 2733 int addr_shift = 5 * mp->port_num;
fc32b0e2 2734 u32 data;
1da177e4 2735
fc32b0e2
LB		 2736 data = rdl(mp, PHY_ADDR);
2737 data &= ~(0x1f << addr_shift);
2738 data |= (phy_addr & 0x1f) << addr_shift;
2739 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2740}
2741
e5371493 2742static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2743{
fc32b0e2
LB		 2744 unsigned int data;
2745
2746 data = rdl(mp, PHY_ADDR);
2747
2748 return (data >> (5 * mp->port_num)) & 0x1f;
2749}
2750
2751static void set_params(struct mv643xx_eth_private *mp,
2752 struct mv643xx_eth_platform_data *pd)
2753{
2754 struct net_device *dev = mp->dev;
2755
2756 if (is_valid_ether_addr(pd->mac_addr))
2757 memcpy(dev->dev_addr, pd->mac_addr, 6);
2758 else
2759 uc_addr_get(mp, dev->dev_addr);
2760
e7d2f4db 2761 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
fc32b0e2 2762 if (pd->rx_queue_size)
e7d2f4db 2763 mp->rx_ring_size = pd->rx_queue_size;
fc32b0e2
LB		 2764 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2765 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2766
f7981c1c 2767 mp->rxq_count = pd->rx_queue_count ? : 1;
64da80a2 2768
e7d2f4db 2769 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
fc32b0e2 2770 if (pd->tx_queue_size)
e7d2f4db 2771 mp->tx_ring_size = pd->tx_queue_size;
fc32b0e2
LB		 2772 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2773 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc 2774
f7981c1c 2775 mp->txq_count = pd->tx_queue_count ? : 1;
1da177e4
LT		 2776}
2777
ed94493f
LB		 2778static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2779 int phy_addr)
1da177e4 2780{
298cf9be 2781 struct mii_bus *bus = mp->shared->smi->smi_bus;
ed94493f
LB		 2782 struct phy_device *phydev;
2783 int start;
2784 int num;
2785 int i;
45c5d3bc 2786
ed94493f
LB		 2787 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2788 start = phy_addr_get(mp) & 0x1f;
2789 num = 32;
2790 } else {
2791 start = phy_addr & 0x1f;
2792 num = 1;
2793 }
45c5d3bc 2794
ed94493f
LB		 2795 phydev = NULL;
2796 for (i = 0; i < num; i++) {
2797 int addr = (start + i) & 0x1f;
fc32b0e2 2798
ed94493f
LB		 2799 if (bus->phy_map[addr] == NULL)
2800 mdiobus_scan(bus, addr);
1da177e4 2801
ed94493f
LB		 2802 if (phydev == NULL) {
2803 phydev = bus->phy_map[addr];
2804 if (phydev != NULL)
2805 phy_addr_set(mp, addr);
2806 }
2807 }
1da177e4 2808
ed94493f 2809 return phydev;
1da177e4
LT		 2810}
2811
ed94493f 2812static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
c28a4f89 2813{
ed94493f 2814 struct phy_device *phy = mp->phy;
c28a4f89 2815
fc32b0e2
LB		 2816 phy_reset(mp);
2817
db1d7bf7 2818 phy_attach(mp->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_GMII);
ed94493f
LB		 2819
2820 if (speed == 0) {
2821 phy->autoneg = AUTONEG_ENABLE;
2822 phy->speed = 0;
2823 phy->duplex = 0;
2824 phy->advertising = phy->supported | ADVERTISED_Autoneg;
c9df406f 2825 } else {
ed94493f
LB		 2826 phy->autoneg = AUTONEG_DISABLE;
2827 phy->advertising = 0;
2828 phy->speed = speed;
2829 phy->duplex = duplex;
c9df406f 2830 }
ed94493f 2831 phy_start_aneg(phy);
c28a4f89
JC		 2832}
2833
81600eea
LB		 2834static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2835{
2836 u32 pscr;
2837
37a6084f 2838 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 2839 if (pscr & SERIAL_PORT_ENABLE) {
2840 pscr &= ~SERIAL_PORT_ENABLE;
37a6084f 2841 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2842 }
2843
2844 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
ed94493f 2845 if (mp->phy == NULL) {
81600eea
LB		 2846 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2847 if (speed == SPEED_1000)
2848 pscr |= SET_GMII_SPEED_TO_1000;
2849 else if (speed == SPEED_100)
2850 pscr |= SET_MII_SPEED_TO_100;
2851
2852 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2853
2854 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2855 if (duplex == DUPLEX_FULL)
2856 pscr |= SET_FULL_DUPLEX_MODE;
2857 }
2858
37a6084f 2859 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2860}
2861
ea8a8642
LB		 2862static const struct net_device_ops mv643xx_eth_netdev_ops = {
2863 .ndo_open = mv643xx_eth_open,
2864 .ndo_stop = mv643xx_eth_stop,
2865 .ndo_start_xmit = mv643xx_eth_xmit,
2866 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
2867 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
2868 .ndo_do_ioctl = mv643xx_eth_ioctl,
2869 .ndo_change_mtu = mv643xx_eth_change_mtu,
2870 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
2871 .ndo_get_stats = mv643xx_eth_get_stats,
2872#ifdef CONFIG_NET_POLL_CONTROLLER
2873 .ndo_poll_controller = mv643xx_eth_netpoll,
2874#endif
2875};
2876
c9df406f 2877static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2878{
c9df406f 2879 struct mv643xx_eth_platform_data *pd;
e5371493 2880 struct mv643xx_eth_private *mp;
c9df406f 2881 struct net_device *dev;
c9df406f 2882 struct resource *res;
fc32b0e2 2883 int err;
1da177e4 2884
c9df406f
LB		 2885 pd = pdev->dev.platform_data;
2886 if (pd == NULL) {
fc32b0e2
LB		 2887 dev_printk(KERN_ERR, &pdev->dev,
2888 "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2889 return -ENODEV;
2890 }
1da177e4 2891
c9df406f 2892 if (pd->shared == NULL) {
fc32b0e2
LB		 2893 dev_printk(KERN_ERR, &pdev->dev,
2894 "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2895 return -ENODEV;
2896 }
8f518703 2897
e5ef1de1 2898 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
c9df406f
LB		 2899 if (!dev)
2900 return -ENOMEM;
1da177e4 2901
c9df406f 2902 mp = netdev_priv(dev);
fc32b0e2
LB		 2903 platform_set_drvdata(pdev, mp);
2904
2905 mp->shared = platform_get_drvdata(pd->shared);
37a6084f 2906 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
fc32b0e2
LB		 2907 mp->port_num = pd->port_number;
2908
c9df406f 2909 mp->dev = dev;
78fff83b 2910
fc32b0e2 2911 set_params(mp, pd);
e5ef1de1 2912 dev->real_num_tx_queues = mp->txq_count;
fc32b0e2 2913
ed94493f
LB		 2914 if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2915 mp->phy = phy_scan(mp, pd->phy_addr);
bedfe324 2916
6bdf576e 2917 if (mp->phy != NULL)
ed94493f 2918 phy_init(mp, pd->speed, pd->duplex);
6bdf576e
LB		 2919
2920 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
ed94493f 2921
81600eea 2922 init_pscr(mp, pd->speed, pd->duplex);
fc32b0e2 2923
4ff3495a
LB		 2924
2925 mib_counters_clear(mp);
2926
2927 init_timer(&mp->mib_counters_timer);
2928 mp->mib_counters_timer.data = (unsigned long)mp;
2929 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2930 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2931 add_timer(&mp->mib_counters_timer);
2932
2933 spin_lock_init(&mp->mib_counters_lock);
2934
2935 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2936
2257e05c
LB		 2937 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2938
2939 init_timer(&mp->rx_oom);
2940 mp->rx_oom.data = (unsigned long)mp;
2941 mp->rx_oom.function = oom_timer_wrapper;
2942
fc32b0e2 2943
c9df406f
LB		 2944 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2945 BUG_ON(!res);
2946 dev->irq = res->start;
1da177e4 2947
ea8a8642
LB		 2948 dev->netdev_ops = &mv643xx_eth_netdev_ops;
2949
c9df406f
LB		 2950 dev->watchdog_timeo = 2 * HZ;
2951 dev->base_addr = 0;
1da177e4 2952
c9df406f 2953 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
e32b6617 2954 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4 2955
fc32b0e2 2956 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2957
c9df406f 2958 if (mp->shared->win_protect)
fc32b0e2 2959 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2960
a5fe3616
LB		 2961 netif_carrier_off(dev);
2962
b5e86db4
LB		 2963 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
2964
4fb0a54a 2965 set_rx_coal(mp, 250);
a5fe3616
LB		 2966 set_tx_coal(mp, 0);
2967
c9df406f
LB		 2968 err = register_netdev(dev);
2969 if (err)
2970 goto out;
1da177e4 2971
e174961c
JB		 2972 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %pM\n",
2973 mp->port_num, dev->dev_addr);
1da177e4 2974
13d64285 2975 if (mp->tx_desc_sram_size > 0)
fc32b0e2 2976 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
1da177e4 2977
c9df406f 2978 return 0;
1da177e4 2979
c9df406f
LB		 2980out:
2981 free_netdev(dev);
1da177e4 2982
c9df406f 2983 return err;
1da177e4
LT		 2984}
2985
c9df406f 2986static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2987{
fc32b0e2 2988 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2989
fc32b0e2 2990 unregister_netdev(mp->dev);
ed94493f
LB		 2991 if (mp->phy != NULL)
2992 phy_detach(mp->phy);
c9df406f 2993 flush_scheduled_work();
fc32b0e2 2994 free_netdev(mp->dev);
c9df406f 2995
c9df406f 2996 platform_set_drvdata(pdev, NULL);
fc32b0e2 2997
c9df406f 2998 return 0;
1da177e4
LT		 2999}
3000
c9df406f 3001static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 3002{
fc32b0e2 3003 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 3004
c9df406f 3005 /* Mask all interrupts on ethernet port */
37a6084f
LB		 3006 wrlp(mp, INT_MASK, 0);
3007 rdlp(mp, INT_MASK);
c9df406f 3008
fc32b0e2
LB		 3009 if (netif_running(mp->dev))
3010 port_reset(mp);
d0412d96
JC		 3011}
3012
c9df406f 3013static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 3014 .probe = mv643xx_eth_probe,
3015 .remove = mv643xx_eth_remove,
3016 .shutdown = mv643xx_eth_shutdown,
c9df406f 3017 .driver = {
fc32b0e2 3018 .name = MV643XX_ETH_NAME,
c9df406f
LB		 3019 .owner = THIS_MODULE,
3020 },
3021};
3022
e5371493 3023static int __init mv643xx_eth_init_module(void)
d0412d96 3024{
c9df406f 3025 int rc;
d0412d96 3026
c9df406f
LB		 3027 rc = platform_driver_register(&mv643xx_eth_shared_driver);
3028 if (!rc) {
3029 rc = platform_driver_register(&mv643xx_eth_driver);
3030 if (rc)
3031 platform_driver_unregister(&mv643xx_eth_shared_driver);
3032 }
fc32b0e2 3033
c9df406f 3034 return rc;
d0412d96 3035}
fc32b0e2 3036module_init(mv643xx_eth_init_module);
d0412d96 3037
e5371493 3038static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 3039{
c9df406f
LB		 3040 platform_driver_unregister(&mv643xx_eth_driver);
3041 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 3042}
e5371493 3043module_exit(mv643xx_eth_cleanup_module);
1da177e4 3044
45675bc6
LB		 3045MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3046 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
c9df406f 3047MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 3048MODULE_LICENSE("GPL");
c9df406f 3049MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 3050MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux kernel - Deliverables
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