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mv643xx_eth: allow multiple RX queues
[deliverable/linux.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
1da177e4
LT		 41#include <linux/tcp.h>
42#include <linux/udp.h>
43#include <linux/etherdevice.h>
1da177e4
LT		 44#include <linux/delay.h>
45#include <linux/ethtool.h>
d052d1be 46#include <linux/platform_device.h>
fbd6a754
LB		 47#include <linux/module.h>
48#include <linux/kernel.h>
49#include <linux/spinlock.h>
50#include <linux/workqueue.h>
51#include <linux/mii.h>
fbd6a754 52#include <linux/mv643xx_eth.h>
1da177e4
LT		 53#include <asm/io.h>
54#include <asm/types.h>
1da177e4 55#include <asm/system.h>
fbd6a754 56
e5371493
LB		 57static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58static char mv643xx_eth_driver_version[] = "1.0";
c9df406f 59
e5371493
LB		 60#define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61#define MV643XX_ETH_NAPI
62#define MV643XX_ETH_TX_FAST_REFILL
fbd6a754 63
e5371493 64#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
fbd6a754
LB		 65#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
66#else
67#define MAX_DESCS_PER_SKB 1
68#endif
69
fbd6a754
LB		 70/*
71 * Registers shared between all ports.
72 */
3cb4667c
LB		 73#define PHY_ADDR 0x0000
74#define SMI_REG 0x0004
75#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78#define WINDOW_BAR_ENABLE 0x0290
79#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 80
81/*
82 * Per-port registers.
83 */
3cb4667c 84#define PORT_CONFIG(p) (0x0400 + ((p) << 10))
d9a073ea 85#define UNICAST_PROMISCUOUS_MODE 0x00000001
3cb4667c
LB		 86#define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
87#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
88#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
89#define SDMA_CONFIG(p) (0x041c + ((p) << 10))
90#define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
91#define PORT_STATUS(p) (0x0444 + ((p) << 10))
a2a41689 92#define TX_FIFO_EMPTY 0x00000400
3cb4667c 93#define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
89df5fdc
LB		 94#define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
95#define TX_BW_RATE(p) (0x0450 + ((p) << 10))
3cb4667c 96#define TX_BW_MTU(p) (0x0458 + ((p) << 10))
89df5fdc 97#define TX_BW_BURST(p) (0x045c + ((p) << 10))
3cb4667c 98#define INT_CAUSE(p) (0x0460 + ((p) << 10))
64da80a2 99#define INT_RX 0x0007fbfc
073a345c 100#define INT_EXT 0x00000002
3cb4667c 101#define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
073a345c
LB		 102#define INT_EXT_LINK 0x00100000
103#define INT_EXT_PHY 0x00010000
104#define INT_EXT_TX_ERROR_0 0x00000100
105#define INT_EXT_TX_0 0x00000001
106#define INT_EXT_TX 0x00000101
3cb4667c
LB		 107#define INT_MASK(p) (0x0468 + ((p) << 10))
108#define INT_MASK_EXT(p) (0x046c + ((p) << 10))
109#define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
64da80a2 110#define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
3cb4667c
LB		 111#define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
112#define TXQ_CURRENT_DESC_PTR(p) (0x06c0 + ((p) << 10))
89df5fdc
LB		 113#define TXQ_BW_TOKENS(p) (0x0700 + ((p) << 10))
114#define TXQ_BW_CONF(p) (0x0704 + ((p) << 10))
115#define TXQ_BW_WRR_CONF(p) (0x0708 + ((p) << 10))
3cb4667c
LB		 116#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
117#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
118#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
119#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 120
2679a550
LB		 121
122/*
123 * SDMA configuration register.
124 */
fbd6a754 125#define RX_BURST_SIZE_4_64BIT (2 << 1)
fbd6a754 126#define BLM_RX_NO_SWAP (1 << 4)
fbd6a754 127#define BLM_TX_NO_SWAP (1 << 5)
fbd6a754 128#define TX_BURST_SIZE_4_64BIT (2 << 22)
fbd6a754
LB		 129
130#if defined(__BIG_ENDIAN)
131#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
132 RX_BURST_SIZE_4_64BIT | \
fbd6a754
LB		 133 TX_BURST_SIZE_4_64BIT
134#elif defined(__LITTLE_ENDIAN)
135#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
136 RX_BURST_SIZE_4_64BIT | \
137 BLM_RX_NO_SWAP | \
138 BLM_TX_NO_SWAP | \
fbd6a754
LB		 139 TX_BURST_SIZE_4_64BIT
140#else
141#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
142#endif
143
2beff77b
LB		 144
145/*
146 * Port serial control register.
147 */
148#define SET_MII_SPEED_TO_100 (1 << 24)
149#define SET_GMII_SPEED_TO_1000 (1 << 23)
150#define SET_FULL_DUPLEX_MODE (1 << 21)
fbd6a754 151#define MAX_RX_PACKET_1522BYTE (1 << 17)
fbd6a754
LB		 152#define MAX_RX_PACKET_9700BYTE (5 << 17)
153#define MAX_RX_PACKET_MASK (7 << 17)
2beff77b
LB		 154#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
155#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
156#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
157#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
158#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
159#define FORCE_LINK_PASS (1 << 1)
160#define SERIAL_PORT_ENABLE (1 << 0)
fbd6a754 161
cc9754b3
LB		 162#define DEFAULT_RX_QUEUE_SIZE 400
163#define DEFAULT_TX_QUEUE_SIZE 800
fbd6a754 164
fbd6a754 165
7ca72a3b
LB		 166/*
167 * RX/TX descriptors.
fbd6a754
LB		 168 */
169#if defined(__BIG_ENDIAN)
cc9754b3 170struct rx_desc {
fbd6a754
LB		 171 u16 byte_cnt; /* Descriptor buffer byte count */
172 u16 buf_size; /* Buffer size */
173 u32 cmd_sts; /* Descriptor command status */
174 u32 next_desc_ptr; /* Next descriptor pointer */
175 u32 buf_ptr; /* Descriptor buffer pointer */
176};
177
cc9754b3 178struct tx_desc {
fbd6a754
LB		 179 u16 byte_cnt; /* buffer byte count */
180 u16 l4i_chk; /* CPU provided TCP checksum */
181 u32 cmd_sts; /* Command/status field */
182 u32 next_desc_ptr; /* Pointer to next descriptor */
183 u32 buf_ptr; /* pointer to buffer for this descriptor*/
184};
185#elif defined(__LITTLE_ENDIAN)
cc9754b3 186struct rx_desc {
fbd6a754
LB		 187 u32 cmd_sts; /* Descriptor command status */
188 u16 buf_size; /* Buffer size */
189 u16 byte_cnt; /* Descriptor buffer byte count */
190 u32 buf_ptr; /* Descriptor buffer pointer */
191 u32 next_desc_ptr; /* Next descriptor pointer */
192};
193
cc9754b3 194struct tx_desc {
fbd6a754
LB		 195 u32 cmd_sts; /* Command/status field */
196 u16 l4i_chk; /* CPU provided TCP checksum */
197 u16 byte_cnt; /* buffer byte count */
198 u32 buf_ptr; /* pointer to buffer for this descriptor*/
199 u32 next_desc_ptr; /* Pointer to next descriptor */
200};
201#else
202#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
203#endif
204
7ca72a3b 205/* RX & TX descriptor command */
cc9754b3 206#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 207
208/* RX & TX descriptor status */
cc9754b3 209#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 210
211/* RX descriptor status */
cc9754b3
LB		 212#define LAYER_4_CHECKSUM_OK 0x40000000
213#define RX_ENABLE_INTERRUPT 0x20000000
214#define RX_FIRST_DESC 0x08000000
215#define RX_LAST_DESC 0x04000000
7ca72a3b
LB		 216
217/* TX descriptor command */
cc9754b3
LB		 218#define TX_ENABLE_INTERRUPT 0x00800000
219#define GEN_CRC 0x00400000
220#define TX_FIRST_DESC 0x00200000
221#define TX_LAST_DESC 0x00100000
222#define ZERO_PADDING 0x00080000
223#define GEN_IP_V4_CHECKSUM 0x00040000
224#define GEN_TCP_UDP_CHECKSUM 0x00020000
225#define UDP_FRAME 0x00010000
7ca72a3b 226
cc9754b3 227#define TX_IHL_SHIFT 11
7ca72a3b
LB		 228
229
c9df406f 230/* global *******************************************************************/
e5371493 231struct mv643xx_eth_shared_private {
fc32b0e2
LB		 232 /*
233 * Ethernet controller base address.
234 */
cc9754b3 235 void __iomem *base;
c9df406f 236
fc32b0e2
LB		 237 /*
238 * Protects access to SMI_REG, which is shared between ports.
239 */
c9df406f
LB		 240 spinlock_t phy_lock;
241
fc32b0e2
LB		 242 /*
243 * Per-port MBUS window access register value.
244 */
c9df406f
LB		 245 u32 win_protect;
246
fc32b0e2
LB		 247 /*
248 * Hardware-specific parameters.
249 */
c9df406f
LB		 250 unsigned int t_clk;
251};
252
253
254/* per-port *****************************************************************/
e5371493 255struct mib_counters {
fbd6a754
LB		 256 u64 good_octets_received;
257 u32 bad_octets_received;
258 u32 internal_mac_transmit_err;
259 u32 good_frames_received;
260 u32 bad_frames_received;
261 u32 broadcast_frames_received;
262 u32 multicast_frames_received;
263 u32 frames_64_octets;
264 u32 frames_65_to_127_octets;
265 u32 frames_128_to_255_octets;
266 u32 frames_256_to_511_octets;
267 u32 frames_512_to_1023_octets;
268 u32 frames_1024_to_max_octets;
269 u64 good_octets_sent;
270 u32 good_frames_sent;
271 u32 excessive_collision;
272 u32 multicast_frames_sent;
273 u32 broadcast_frames_sent;
274 u32 unrec_mac_control_received;
275 u32 fc_sent;
276 u32 good_fc_received;
277 u32 bad_fc_received;
278 u32 undersize_received;
279 u32 fragments_received;
280 u32 oversize_received;
281 u32 jabber_received;
282 u32 mac_receive_error;
283 u32 bad_crc_event;
284 u32 collision;
285 u32 late_collision;
286};
287
8a578111 288struct rx_queue {
64da80a2
LB		 289 int index;
290
8a578111
LB		 291 int rx_ring_size;
292
293 int rx_desc_count;
294 int rx_curr_desc;
295 int rx_used_desc;
296
297 struct rx_desc *rx_desc_area;
298 dma_addr_t rx_desc_dma;
299 int rx_desc_area_size;
300 struct sk_buff **rx_skb;
301
302 struct timer_list rx_oom;
303};
304
13d64285
LB		 305struct tx_queue {
306 int tx_ring_size;
fbd6a754 307
13d64285
LB		 308 int tx_desc_count;
309 int tx_curr_desc;
310 int tx_used_desc;
fbd6a754 311
5daffe94 312 struct tx_desc *tx_desc_area;
fbd6a754
LB		 313 dma_addr_t tx_desc_dma;
314 int tx_desc_area_size;
315 struct sk_buff **tx_skb;
13d64285
LB		 316};
317
318struct mv643xx_eth_private {
319 struct mv643xx_eth_shared_private *shared;
fc32b0e2 320 int port_num;
13d64285 321
fc32b0e2 322 struct net_device *dev;
fbd6a754 323
fc32b0e2
LB		 324 struct mv643xx_eth_shared_private *shared_smi;
325 int phy_addr;
fbd6a754 326
fbd6a754 327 spinlock_t lock;
fbd6a754 328
fc32b0e2
LB		 329 struct mib_counters mib_counters;
330 struct work_struct tx_timeout_task;
fbd6a754 331 struct mii_if_info mii;
8a578111
LB		 332
333 /*
334 * RX state.
335 */
336 int default_rx_ring_size;
337 unsigned long rx_desc_sram_addr;
338 int rx_desc_sram_size;
64da80a2
LB		 339 u8 rxq_mask;
340 int rxq_primary;
8a578111 341 struct napi_struct napi;
64da80a2 342 struct rx_queue rxq[8];
13d64285
LB		 343
344 /*
345 * TX state.
346 */
347 int default_tx_ring_size;
348 unsigned long tx_desc_sram_addr;
349 int tx_desc_sram_size;
350 struct tx_queue txq[1];
351#ifdef MV643XX_ETH_TX_FAST_REFILL
352 int tx_clean_threshold;
353#endif
fbd6a754 354};
1da177e4 355
fbd6a754 356
c9df406f 357/* port register accessors **************************************************/
e5371493 358static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 359{
cc9754b3 360 return readl(mp->shared->base + offset);
c9df406f 361}
fbd6a754 362
e5371493 363static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 364{
cc9754b3 365 writel(data, mp->shared->base + offset);
c9df406f 366}
fbd6a754 367
fbd6a754 368
c9df406f 369/* rxq/txq helper functions *************************************************/
8a578111 370static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 371{
64da80a2 372 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 373}
fbd6a754 374
13d64285
LB		 375static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
376{
377 return container_of(txq, struct mv643xx_eth_private, txq[0]);
378}
379
8a578111 380static void rxq_enable(struct rx_queue *rxq)
c9df406f 381{
8a578111 382 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 383 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
8a578111 384}
1da177e4 385
8a578111
LB		 386static void rxq_disable(struct rx_queue *rxq)
387{
388 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 389 u8 mask = 1 << rxq->index;
1da177e4 390
8a578111
LB		 391 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
392 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
393 udelay(10);
c9df406f
LB		 394}
395
13d64285 396static void txq_enable(struct tx_queue *txq)
1da177e4 397{
13d64285
LB		 398 struct mv643xx_eth_private *mp = txq_to_mp(txq);
399 wrl(mp, TXQ_COMMAND(mp->port_num), 1);
1da177e4
LT		 400}
401
13d64285 402static void txq_disable(struct tx_queue *txq)
1da177e4 403{
13d64285
LB		 404 struct mv643xx_eth_private *mp = txq_to_mp(txq);
405 u8 mask = 1;
c9df406f 406
13d64285
LB		 407 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
408 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
409 udelay(10);
410}
411
412static void __txq_maybe_wake(struct tx_queue *txq)
413{
414 struct mv643xx_eth_private *mp = txq_to_mp(txq);
415
416 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB)
417 netif_wake_queue(mp->dev);
1da177e4
LT		 418}
419
c9df406f
LB		 420
421/* rx ***********************************************************************/
13d64285 422static void txq_reclaim(struct tx_queue *txq, int force);
c9df406f 423
8a578111 424static void rxq_refill(struct rx_queue *rxq)
1da177e4 425{
8a578111 426 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
c9df406f 427 unsigned long flags;
1da177e4 428
c9df406f 429 spin_lock_irqsave(&mp->lock, flags);
c0d0f2ca 430
8a578111
LB		 431 while (rxq->rx_desc_count < rxq->rx_ring_size) {
432 int skb_size;
de34f225
LB		 433 struct sk_buff *skb;
434 int unaligned;
435 int rx;
436
8a578111
LB		 437 /*
438 * Reserve 2+14 bytes for an ethernet header (the
439 * hardware automatically prepends 2 bytes of dummy
440 * data to each received packet), 4 bytes for a VLAN
441 * header, and 4 bytes for the trailing FCS -- 24
442 * bytes total.
443 */
444 skb_size = mp->dev->mtu + 24;
445
446 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
de34f225 447 if (skb == NULL)
1da177e4 448 break;
de34f225 449
908b637f 450 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
b44cd572 451 if (unaligned)
908b637f 452 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
de34f225 453
8a578111
LB		 454 rxq->rx_desc_count++;
455 rx = rxq->rx_used_desc;
456 rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size;
de34f225 457
8a578111
LB		 458 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
459 skb_size, DMA_FROM_DEVICE);
460 rxq->rx_desc_area[rx].buf_size = skb_size;
461 rxq->rx_skb[rx] = skb;
de34f225 462 wmb();
8a578111 463 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
de34f225
LB		 464 RX_ENABLE_INTERRUPT;
465 wmb();
466
fc32b0e2
LB		 467 /*
468 * The hardware automatically prepends 2 bytes of
469 * dummy data to each received packet, so that the
470 * IP header ends up 16-byte aligned.
471 */
472 skb_reserve(skb, 2);
1da177e4 473 }
de34f225 474
8a578111
LB		 475 if (rxq->rx_desc_count == 0) {
476 rxq->rx_oom.expires = jiffies + (HZ / 10);
477 add_timer(&rxq->rx_oom);
1da177e4 478 }
de34f225
LB		 479
480 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4
LT		 481}
482
8a578111 483static inline void rxq_refill_timer_wrapper(unsigned long data)
1da177e4 484{
8a578111 485 rxq_refill((struct rx_queue *)data);
1da177e4
LT		 486}
487
8a578111 488static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 489{
8a578111
LB		 490 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
491 struct net_device_stats *stats = &mp->dev->stats;
492 int rx;
1da177e4 493
8a578111
LB		 494 rx = 0;
495 while (rx < budget) {
fc32b0e2 496 struct rx_desc *rx_desc;
96587661 497 unsigned int cmd_sts;
fc32b0e2 498 struct sk_buff *skb;
96587661 499 unsigned long flags;
d344bff9 500
96587661 501 spin_lock_irqsave(&mp->lock, flags);
ff561eef 502
8a578111 503 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 504
96587661
LB		 505 cmd_sts = rx_desc->cmd_sts;
506 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
507 spin_unlock_irqrestore(&mp->lock, flags);
508 break;
509 }
510 rmb();
1da177e4 511
8a578111
LB		 512 skb = rxq->rx_skb[rxq->rx_curr_desc];
513 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 514
8a578111 515 rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size;
ff561eef 516
96587661 517 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 518
fc32b0e2
LB		 519 dma_unmap_single(NULL, rx_desc->buf_ptr + 2,
520 mp->dev->mtu + 24, DMA_FROM_DEVICE);
8a578111
LB		 521 rxq->rx_desc_count--;
522 rx++;
b1dd9ca1 523
468d09f8
DF		 524 /*
525 * Update statistics.
fc32b0e2
LB		 526 *
527 * Note that the descriptor byte count includes 2 dummy
528 * bytes automatically inserted by the hardware at the
529 * start of the packet (which we don't count), and a 4
530 * byte CRC at the end of the packet (which we do count).
468d09f8 531 */
1da177e4 532 stats->rx_packets++;
fc32b0e2 533 stats->rx_bytes += rx_desc->byte_cnt - 2;
96587661 534
1da177e4 535 /*
fc32b0e2
LB		 536 * In case we received a packet without first / last bits
537 * on, or the error summary bit is set, the packet needs
538 * to be dropped.
1da177e4 539 */
96587661 540 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 541 (RX_FIRST_DESC | RX_LAST_DESC))
96587661 542 || (cmd_sts & ERROR_SUMMARY)) {
1da177e4 543 stats->rx_dropped++;
fc32b0e2 544
96587661 545 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 546 (RX_FIRST_DESC | RX_LAST_DESC)) {
1da177e4 547 if (net_ratelimit())
fc32b0e2
LB		 548 dev_printk(KERN_ERR, &mp->dev->dev,
549 "received packet spanning "
550 "multiple descriptors\n");
1da177e4 551 }
fc32b0e2 552
96587661 553 if (cmd_sts & ERROR_SUMMARY)
1da177e4
LT		 554 stats->rx_errors++;
555
556 dev_kfree_skb_irq(skb);
557 } else {
558 /*
559 * The -4 is for the CRC in the trailer of the
560 * received packet
561 */
fc32b0e2 562 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
1da177e4 563
96587661 564 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
1da177e4
LT		 565 skb->ip_summed = CHECKSUM_UNNECESSARY;
566 skb->csum = htons(
96587661 567 (cmd_sts & 0x0007fff8) >> 3);
1da177e4 568 }
8a578111 569 skb->protocol = eth_type_trans(skb, mp->dev);
e5371493 570#ifdef MV643XX_ETH_NAPI
1da177e4
LT		 571 netif_receive_skb(skb);
572#else
573 netif_rx(skb);
574#endif
575 }
fc32b0e2 576
8a578111 577 mp->dev->last_rx = jiffies;
1da177e4 578 }
fc32b0e2 579
8a578111 580 rxq_refill(rxq);
1da177e4 581
8a578111 582 return rx;
1da177e4
LT		 583}
584
e5371493 585#ifdef MV643XX_ETH_NAPI
e5371493 586static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
d0412d96 587{
8a578111
LB		 588 struct mv643xx_eth_private *mp;
589 int rx;
64da80a2 590 int i;
8a578111
LB		 591
592 mp = container_of(napi, struct mv643xx_eth_private, napi);
d0412d96 593
e5371493 594#ifdef MV643XX_ETH_TX_FAST_REFILL
c9df406f 595 if (++mp->tx_clean_threshold > 5) {
13d64285 596 txq_reclaim(mp->txq, 0);
c9df406f 597 mp->tx_clean_threshold = 0;
d0412d96 598 }
c9df406f 599#endif
d0412d96 600
64da80a2
LB		 601 rx = 0;
602 for (i = 7; rx < budget && i >= 0; i--)
603 if (mp->rxq_mask & (1 << i))
604 rx += rxq_process(mp->rxq + i, budget - rx);
d0412d96 605
8a578111
LB		 606 if (rx < budget) {
607 netif_rx_complete(mp->dev, napi);
608 wrl(mp, INT_CAUSE(mp->port_num), 0);
609 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
610 wrl(mp, INT_MASK(mp->port_num), INT_RX | INT_EXT);
d0412d96 611 }
c9df406f 612
8a578111 613 return rx;
d0412d96 614}
c9df406f 615#endif
d0412d96 616
c9df406f
LB		 617
618/* tx ***********************************************************************/
c9df406f 619static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 620{
13d64285 621 int frag;
1da177e4 622
c9df406f 623 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
13d64285
LB		 624 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
625 if (fragp->size <= 8 && fragp->page_offset & 7)
c9df406f 626 return 1;
1da177e4 627 }
13d64285 628
c9df406f
LB		 629 return 0;
630}
7303fde8 631
13d64285 632static int txq_alloc_desc_index(struct tx_queue *txq)
c9df406f
LB		 633{
634 int tx_desc_curr;
d0412d96 635
13d64285 636 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
1da177e4 637
13d64285
LB		 638 tx_desc_curr = txq->tx_curr_desc;
639 txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size;
e4d00fa9 640
13d64285 641 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
468d09f8 642
c9df406f
LB		 643 return tx_desc_curr;
644}
468d09f8 645
13d64285 646static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 647{
13d64285 648 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 649 int frag;
1da177e4 650
13d64285
LB		 651 for (frag = 0; frag < nr_frags; frag++) {
652 skb_frag_t *this_frag;
653 int tx_index;
654 struct tx_desc *desc;
655
656 this_frag = &skb_shinfo(skb)->frags[frag];
657 tx_index = txq_alloc_desc_index(txq);
658 desc = &txq->tx_desc_area[tx_index];
659
660 /*
661 * The last fragment will generate an interrupt
662 * which will free the skb on TX completion.
663 */
664 if (frag == nr_frags - 1) {
665 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
666 ZERO_PADDING | TX_LAST_DESC |
667 TX_ENABLE_INTERRUPT;
668 txq->tx_skb[tx_index] = skb;
669 } else {
670 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
671 txq->tx_skb[tx_index] = NULL;
672 }
673
c9df406f
LB		 674 desc->l4i_chk = 0;
675 desc->byte_cnt = this_frag->size;
676 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
677 this_frag->page_offset,
678 this_frag->size,
679 DMA_TO_DEVICE);
680 }
1da177e4
LT		 681}
682
c9df406f
LB		 683static inline __be16 sum16_as_be(__sum16 sum)
684{
685 return (__force __be16)sum;
686}
1da177e4 687
13d64285 688static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 689{
13d64285 690 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 691 int tx_index;
cc9754b3 692 struct tx_desc *desc;
c9df406f
LB		 693 u32 cmd_sts;
694 int length;
1da177e4 695
cc9754b3 696 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
1da177e4 697
13d64285
LB		 698 tx_index = txq_alloc_desc_index(txq);
699 desc = &txq->tx_desc_area[tx_index];
c9df406f
LB		 700
701 if (nr_frags) {
13d64285 702 txq_submit_frag_skb(txq, skb);
c9df406f
LB		 703
704 length = skb_headlen(skb);
13d64285 705 txq->tx_skb[tx_index] = NULL;
c9df406f 706 } else {
cc9754b3 707 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
c9df406f 708 length = skb->len;
13d64285 709 txq->tx_skb[tx_index] = skb;
c9df406f
LB		 710 }
711
712 desc->byte_cnt = length;
713 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
714
715 if (skb->ip_summed == CHECKSUM_PARTIAL) {
716 BUG_ON(skb->protocol != htons(ETH_P_IP));
717
cc9754b3
LB		 718 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
719 GEN_IP_V4_CHECKSUM |
720 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
c9df406f
LB		 721
722 switch (ip_hdr(skb)->protocol) {
723 case IPPROTO_UDP:
cc9754b3 724 cmd_sts |= UDP_FRAME;
c9df406f
LB		 725 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
726 break;
727 case IPPROTO_TCP:
728 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
729 break;
730 default:
731 BUG();
732 }
733 } else {
734 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 735 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 736 desc->l4i_chk = 0;
737 }
738
739 /* ensure all other descriptors are written before first cmd_sts */
740 wmb();
741 desc->cmd_sts = cmd_sts;
742
743 /* ensure all descriptors are written before poking hardware */
744 wmb();
13d64285 745 txq_enable(txq);
c9df406f 746
13d64285 747 txq->tx_desc_count += nr_frags + 1;
1da177e4 748}
1da177e4 749
fc32b0e2 750static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 751{
e5371493 752 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 753 struct net_device_stats *stats = &dev->stats;
13d64285 754 struct tx_queue *txq;
c9df406f 755 unsigned long flags;
afdb57a2 756
c9df406f 757 BUG_ON(netif_queue_stopped(dev));
afdb57a2 758
c9df406f
LB		 759 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
760 stats->tx_dropped++;
fc32b0e2
LB		 761 dev_printk(KERN_DEBUG, &dev->dev,
762 "failed to linearize skb with tiny "
763 "unaligned fragment\n");
c9df406f
LB		 764 return NETDEV_TX_BUSY;
765 }
766
767 spin_lock_irqsave(&mp->lock, flags);
768
13d64285
LB		 769 txq = mp->txq;
770
771 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) {
c9df406f
LB		 772 printk(KERN_ERR "%s: transmit with queue full\n", dev->name);
773 netif_stop_queue(dev);
774 spin_unlock_irqrestore(&mp->lock, flags);
775 return NETDEV_TX_BUSY;
776 }
777
13d64285 778 txq_submit_skb(txq, skb);
c9df406f
LB		 779 stats->tx_bytes += skb->len;
780 stats->tx_packets++;
781 dev->trans_start = jiffies;
782
13d64285 783 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB)
c9df406f
LB		 784 netif_stop_queue(dev);
785
786 spin_unlock_irqrestore(&mp->lock, flags);
787
788 return NETDEV_TX_OK;
1da177e4
LT		 789}
790
c9df406f 791
89df5fdc
LB		 792/* tx rate control **********************************************************/
793/*
794 * Set total maximum TX rate (shared by all TX queues for this port)
795 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
796 */
797static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
798{
799 int token_rate;
800 int mtu;
801 int bucket_size;
802
803 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
804 if (token_rate > 1023)
805 token_rate = 1023;
806
807 mtu = (mp->dev->mtu + 255) >> 8;
808 if (mtu > 63)
809 mtu = 63;
810
811 bucket_size = (burst + 255) >> 8;
812 if (bucket_size > 65535)
813 bucket_size = 65535;
814
815 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
816 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
817 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
818}
819
820static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
821{
822 struct mv643xx_eth_private *mp = txq_to_mp(txq);
823 int token_rate;
824 int bucket_size;
825
826 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
827 if (token_rate > 1023)
828 token_rate = 1023;
829
830 bucket_size = (burst + 255) >> 8;
831 if (bucket_size > 65535)
832 bucket_size = 65535;
833
834 wrl(mp, TXQ_BW_TOKENS(mp->port_num), token_rate << 14);
835 wrl(mp, TXQ_BW_CONF(mp->port_num),
836 (bucket_size << 10) | token_rate);
837}
838
839static void txq_set_fixed_prio_mode(struct tx_queue *txq)
840{
841 struct mv643xx_eth_private *mp = txq_to_mp(txq);
842 int off;
843 u32 val;
844
845 /*
846 * Turn on fixed priority mode.
847 */
848 off = TXQ_FIX_PRIO_CONF(mp->port_num);
849
850 val = rdl(mp, off);
851 val |= 1;
852 wrl(mp, off, val);
853}
854
855static void txq_set_wrr(struct tx_queue *txq, int weight)
856{
857 struct mv643xx_eth_private *mp = txq_to_mp(txq);
858 int off;
859 u32 val;
860
861 /*
862 * Turn off fixed priority mode.
863 */
864 off = TXQ_FIX_PRIO_CONF(mp->port_num);
865
866 val = rdl(mp, off);
867 val &= ~1;
868 wrl(mp, off, val);
869
870 /*
871 * Configure WRR weight for this queue.
872 */
873 off = TXQ_BW_WRR_CONF(mp->port_num);
874
875 val = rdl(mp, off);
876 val = (val & ~0xff) | (weight & 0xff);
877 wrl(mp, off, val);
878}
879
880
c9df406f 881/* mii management interface *************************************************/
fc32b0e2
LB		 882#define SMI_BUSY 0x10000000
883#define SMI_READ_VALID 0x08000000
884#define SMI_OPCODE_READ 0x04000000
885#define SMI_OPCODE_WRITE 0x00000000
c9df406f 886
fc32b0e2
LB		 887static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr,
888 unsigned int reg, unsigned int *value)
1da177e4 889{
cc9754b3 890 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
c9df406f 891 unsigned long flags;
1da177e4
LT		 892 int i;
893
c9df406f
LB		 894 /* the SMI register is a shared resource */
895 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
896
897 /* wait for the SMI register to become available */
cc9754b3 898 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
e1bea50a 899 if (i == 1000) {
c9df406f
LB		 900 printk("%s: PHY busy timeout\n", mp->dev->name);
901 goto out;
902 }
e1bea50a 903 udelay(10);
1da177e4
LT		 904 }
905
fc32b0e2 906 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 907
c9df406f 908 /* now wait for the data to be valid */
cc9754b3 909 for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
e1bea50a 910 if (i == 1000) {
c9df406f
LB		 911 printk("%s: PHY read timeout\n", mp->dev->name);
912 goto out;
913 }
e1bea50a 914 udelay(10);
c9df406f
LB		 915 }
916
917 *value = readl(smi_reg) & 0xffff;
918out:
919 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1da177e4
LT		 920}
921
fc32b0e2
LB		 922static void smi_reg_write(struct mv643xx_eth_private *mp,
923 unsigned int addr,
924 unsigned int reg, unsigned int value)
1da177e4 925{
cc9754b3 926 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
c9df406f 927 unsigned long flags;
1da177e4
LT		 928 int i;
929
c9df406f
LB		 930 /* the SMI register is a shared resource */
931 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
932
933 /* wait for the SMI register to become available */
cc9754b3 934 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
e1bea50a 935 if (i == 1000) {
c9df406f
LB		 936 printk("%s: PHY busy timeout\n", mp->dev->name);
937 goto out;
938 }
e1bea50a 939 udelay(10);
1da177e4
LT		 940 }
941
fc32b0e2
LB		 942 writel(SMI_OPCODE_WRITE | (reg << 21) |
943 (addr << 16) | (value & 0xffff), smi_reg);
c9df406f
LB		 944out:
945 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
946}
1da177e4 947
c9df406f
LB		 948
949/* mib counters *************************************************************/
fc32b0e2 950static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 951{
fc32b0e2 952 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 953}
954
fc32b0e2 955static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 956{
fc32b0e2
LB		 957 int i;
958
959 for (i = 0; i < 0x80; i += 4)
960 mib_read(mp, i);
c9df406f 961}
d0412d96 962
fc32b0e2 963static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 964{
e5371493 965 struct mib_counters *p = &mp->mib_counters;
4b8e3655 966
fc32b0e2
LB		 967 p->good_octets_received += mib_read(mp, 0x00);
968 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
969 p->bad_octets_received += mib_read(mp, 0x08);
970 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
971 p->good_frames_received += mib_read(mp, 0x10);
972 p->bad_frames_received += mib_read(mp, 0x14);
973 p->broadcast_frames_received += mib_read(mp, 0x18);
974 p->multicast_frames_received += mib_read(mp, 0x1c);
975 p->frames_64_octets += mib_read(mp, 0x20);
976 p->frames_65_to_127_octets += mib_read(mp, 0x24);
977 p->frames_128_to_255_octets += mib_read(mp, 0x28);
978 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
979 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
980 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
981 p->good_octets_sent += mib_read(mp, 0x38);
982 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
983 p->good_frames_sent += mib_read(mp, 0x40);
984 p->excessive_collision += mib_read(mp, 0x44);
985 p->multicast_frames_sent += mib_read(mp, 0x48);
986 p->broadcast_frames_sent += mib_read(mp, 0x4c);
987 p->unrec_mac_control_received += mib_read(mp, 0x50);
988 p->fc_sent += mib_read(mp, 0x54);
989 p->good_fc_received += mib_read(mp, 0x58);
990 p->bad_fc_received += mib_read(mp, 0x5c);
991 p->undersize_received += mib_read(mp, 0x60);
992 p->fragments_received += mib_read(mp, 0x64);
993 p->oversize_received += mib_read(mp, 0x68);
994 p->jabber_received += mib_read(mp, 0x6c);
995 p->mac_receive_error += mib_read(mp, 0x70);
996 p->bad_crc_event += mib_read(mp, 0x74);
997 p->collision += mib_read(mp, 0x78);
998 p->late_collision += mib_read(mp, 0x7c);
d0412d96
JC		 999}
1000
c9df406f
LB		 1001
1002/* ethtool ******************************************************************/
e5371493 1003struct mv643xx_eth_stats {
c9df406f
LB		 1004 char stat_string[ETH_GSTRING_LEN];
1005 int sizeof_stat;
16820054
LB		 1006 int netdev_off;
1007 int mp_off;
c9df406f
LB		 1008};
1009
16820054
LB		 1010#define SSTAT(m) \
1011 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1012 offsetof(struct net_device, stats.m), -1 }
1013
1014#define MIBSTAT(m) \
1015 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1016 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1017
1018static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1019 SSTAT(rx_packets),
1020 SSTAT(tx_packets),
1021 SSTAT(rx_bytes),
1022 SSTAT(tx_bytes),
1023 SSTAT(rx_errors),
1024 SSTAT(tx_errors),
1025 SSTAT(rx_dropped),
1026 SSTAT(tx_dropped),
1027 MIBSTAT(good_octets_received),
1028 MIBSTAT(bad_octets_received),
1029 MIBSTAT(internal_mac_transmit_err),
1030 MIBSTAT(good_frames_received),
1031 MIBSTAT(bad_frames_received),
1032 MIBSTAT(broadcast_frames_received),
1033 MIBSTAT(multicast_frames_received),
1034 MIBSTAT(frames_64_octets),
1035 MIBSTAT(frames_65_to_127_octets),
1036 MIBSTAT(frames_128_to_255_octets),
1037 MIBSTAT(frames_256_to_511_octets),
1038 MIBSTAT(frames_512_to_1023_octets),
1039 MIBSTAT(frames_1024_to_max_octets),
1040 MIBSTAT(good_octets_sent),
1041 MIBSTAT(good_frames_sent),
1042 MIBSTAT(excessive_collision),
1043 MIBSTAT(multicast_frames_sent),
1044 MIBSTAT(broadcast_frames_sent),
1045 MIBSTAT(unrec_mac_control_received),
1046 MIBSTAT(fc_sent),
1047 MIBSTAT(good_fc_received),
1048 MIBSTAT(bad_fc_received),
1049 MIBSTAT(undersize_received),
1050 MIBSTAT(fragments_received),
1051 MIBSTAT(oversize_received),
1052 MIBSTAT(jabber_received),
1053 MIBSTAT(mac_receive_error),
1054 MIBSTAT(bad_crc_event),
1055 MIBSTAT(collision),
1056 MIBSTAT(late_collision),
c9df406f
LB		 1057};
1058
e5371493 1059static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
d0412d96 1060{
e5371493 1061 struct mv643xx_eth_private *mp = netdev_priv(dev);
d0412d96
JC		 1062 int err;
1063
1064 spin_lock_irq(&mp->lock);
1065 err = mii_ethtool_gset(&mp->mii, cmd);
1066 spin_unlock_irq(&mp->lock);
1067
fc32b0e2
LB		 1068 /*
1069 * The MAC does not support 1000baseT_Half.
1070 */
d0412d96
JC		 1071 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1072 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1073
1074 return err;
1075}
1076
e5371493 1077static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1078{
e5371493 1079 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6
DF		 1080 int err;
1081
fc32b0e2
LB		 1082 /*
1083 * The MAC does not support 1000baseT_Half.
1084 */
1085 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1086
c9df406f
LB		 1087 spin_lock_irq(&mp->lock);
1088 err = mii_ethtool_sset(&mp->mii, cmd);
1089 spin_unlock_irq(&mp->lock);
85cf572c 1090
c9df406f
LB		 1091 return err;
1092}
1da177e4 1093
fc32b0e2
LB		 1094static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1095 struct ethtool_drvinfo *drvinfo)
c9df406f 1096{
e5371493
LB		 1097 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1098 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 1099 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 1100 strncpy(drvinfo->bus_info, "platform", 32);
16820054 1101 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1102}
1da177e4 1103
fc32b0e2 1104static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1105{
e5371493 1106 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1107
c9df406f
LB		 1108 return mii_nway_restart(&mp->mii);
1109}
1da177e4 1110
c9df406f
LB		 1111static u32 mv643xx_eth_get_link(struct net_device *dev)
1112{
e5371493 1113 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1114
c9df406f
LB		 1115 return mii_link_ok(&mp->mii);
1116}
1da177e4 1117
fc32b0e2
LB		 1118static void mv643xx_eth_get_strings(struct net_device *dev,
1119 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1120{
1121 int i;
1da177e4 1122
fc32b0e2
LB		 1123 if (stringset == ETH_SS_STATS) {
1124 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1125 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1126 mv643xx_eth_stats[i].stat_string,
e5371493 1127 ETH_GSTRING_LEN);
c9df406f 1128 }
c9df406f
LB		 1129 }
1130}
1da177e4 1131
fc32b0e2
LB		 1132static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1133 struct ethtool_stats *stats,
1134 uint64_t *data)
c9df406f 1135{
fc32b0e2 1136 struct mv643xx_eth_private *mp = dev->priv;
c9df406f 1137 int i;
1da177e4 1138
fc32b0e2 1139 mib_counters_update(mp);
1da177e4 1140
16820054
LB		 1141 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1142 const struct mv643xx_eth_stats *stat;
1143 void *p;
1144
1145 stat = mv643xx_eth_stats + i;
1146
1147 if (stat->netdev_off >= 0)
1148 p = ((void *)mp->dev) + stat->netdev_off;
1149 else
1150 p = ((void *)mp) + stat->mp_off;
1151
1152 data[i] = (stat->sizeof_stat == 8) ?
1153 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1154 }
c9df406f 1155}
1da177e4 1156
fc32b0e2 1157static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1158{
fc32b0e2 1159 if (sset == ETH_SS_STATS)
16820054 1160 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1161
1162 return -EOPNOTSUPP;
c9df406f 1163}
1da177e4 1164
e5371493 1165static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1166 .get_settings = mv643xx_eth_get_settings,
1167 .set_settings = mv643xx_eth_set_settings,
1168 .get_drvinfo = mv643xx_eth_get_drvinfo,
1169 .nway_reset = mv643xx_eth_nway_reset,
1170 .get_link = mv643xx_eth_get_link,
c9df406f 1171 .set_sg = ethtool_op_set_sg,
fc32b0e2
LB		 1172 .get_strings = mv643xx_eth_get_strings,
1173 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
e5371493 1174 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1175};
1da177e4 1176
bea3348e 1177
c9df406f 1178/* address handling *********************************************************/
5daffe94 1179static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1180{
c9df406f
LB		 1181 unsigned int mac_h;
1182 unsigned int mac_l;
1da177e4 1183
fc32b0e2
LB		 1184 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1185 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1da177e4 1186
5daffe94
LB		 1187 addr[0] = (mac_h >> 24) & 0xff;
1188 addr[1] = (mac_h >> 16) & 0xff;
1189 addr[2] = (mac_h >> 8) & 0xff;
1190 addr[3] = mac_h & 0xff;
1191 addr[4] = (mac_l >> 8) & 0xff;
1192 addr[5] = mac_l & 0xff;
c9df406f 1193}
1da177e4 1194
e5371493 1195static void init_mac_tables(struct mv643xx_eth_private *mp)
c9df406f 1196{
fc32b0e2 1197 int i;
1da177e4 1198
fc32b0e2
LB		 1199 for (i = 0; i < 0x100; i += 4) {
1200 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1201 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
c9df406f 1202 }
fc32b0e2
LB		 1203
1204 for (i = 0; i < 0x10; i += 4)
1205 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
c9df406f 1206}
d0412d96 1207
e5371493 1208static void set_filter_table_entry(struct mv643xx_eth_private *mp,
fc32b0e2 1209 int table, unsigned char entry)
c9df406f
LB		 1210{
1211 unsigned int table_reg;
ab4384a6 1212
c9df406f 1213 /* Set "accepts frame bit" at specified table entry */
fc32b0e2
LB		 1214 table_reg = rdl(mp, table + (entry & 0xfc));
1215 table_reg |= 0x01 << (8 * (entry & 3));
1216 wrl(mp, table + (entry & 0xfc), table_reg);
1da177e4
LT		 1217}
1218
5daffe94 1219static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1da177e4 1220{
c9df406f
LB		 1221 unsigned int mac_h;
1222 unsigned int mac_l;
1223 int table;
1da177e4 1224
fc32b0e2
LB		 1225 mac_l = (addr[4] << 8) | addr[5];
1226 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
ff561eef 1227
fc32b0e2
LB		 1228 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1229 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1da177e4 1230
fc32b0e2 1231 table = UNICAST_TABLE(mp->port_num);
5daffe94 1232 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1da177e4
LT		 1233}
1234
fc32b0e2 1235static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1da177e4 1236{
e5371493 1237 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1238
fc32b0e2
LB		 1239 /* +2 is for the offset of the HW addr type */
1240 memcpy(dev->dev_addr, addr + 2, 6);
1241
cc9754b3
LB		 1242 init_mac_tables(mp);
1243 uc_addr_set(mp, dev->dev_addr);
1da177e4
LT		 1244
1245 return 0;
1246}
1247
69876569
LB		 1248static int addr_crc(unsigned char *addr)
1249{
1250 int crc = 0;
1251 int i;
1252
1253 for (i = 0; i < 6; i++) {
1254 int j;
1255
1256 crc = (crc ^ addr[i]) << 8;
1257 for (j = 7; j >= 0; j--) {
1258 if (crc & (0x100 << j))
1259 crc ^= 0x107 << j;
1260 }
1261 }
1262
1263 return crc;
1264}
1265
fc32b0e2 1266static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1da177e4 1267{
fc32b0e2
LB		 1268 struct mv643xx_eth_private *mp = netdev_priv(dev);
1269 u32 port_config;
1270 struct dev_addr_list *addr;
1271 int i;
c8aaea25 1272
fc32b0e2
LB		 1273 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1274 if (dev->flags & IFF_PROMISC)
1275 port_config |= UNICAST_PROMISCUOUS_MODE;
1276 else
1277 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1278 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1da177e4 1279
fc32b0e2
LB		 1280 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1281 int port_num = mp->port_num;
1282 u32 accept = 0x01010101;
c8aaea25 1283
fc32b0e2
LB		 1284 for (i = 0; i < 0x100; i += 4) {
1285 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1286 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1287 }
1288 return;
1289 }
c8aaea25 1290
fc32b0e2
LB		 1291 for (i = 0; i < 0x100; i += 4) {
1292 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1293 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1da177e4
LT		 1294 }
1295
fc32b0e2
LB		 1296 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1297 u8 *a = addr->da_addr;
1298 int table;
324ff2c1 1299
fc32b0e2
LB		 1300 if (addr->da_addrlen != 6)
1301 continue;
1da177e4 1302
fc32b0e2
LB		 1303 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1304 table = SPECIAL_MCAST_TABLE(mp->port_num);
1305 set_filter_table_entry(mp, table, a[5]);
1306 } else {
1307 int crc = addr_crc(a);
1da177e4 1308
fc32b0e2
LB		 1309 table = OTHER_MCAST_TABLE(mp->port_num);
1310 set_filter_table_entry(mp, table, crc);
1311 }
1312 }
c9df406f 1313}
c8aaea25 1314
c8aaea25 1315
c9df406f 1316/* rx/tx queue initialisation ***********************************************/
64da80a2 1317static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1318{
64da80a2 1319 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1320 struct rx_desc *rx_desc;
1321 int size;
c9df406f
LB		 1322 int i;
1323
64da80a2
LB		 1324 rxq->index = index;
1325
8a578111
LB		 1326 rxq->rx_ring_size = mp->default_rx_ring_size;
1327
1328 rxq->rx_desc_count = 0;
1329 rxq->rx_curr_desc = 0;
1330 rxq->rx_used_desc = 0;
1331
1332 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1333
64da80a2 1334 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1335 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1336 mp->rx_desc_sram_size);
1337 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1338 } else {
1339 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1340 &rxq->rx_desc_dma,
1341 GFP_KERNEL);
f7ea3337
PJ		 1342 }
1343
8a578111
LB		 1344 if (rxq->rx_desc_area == NULL) {
1345 dev_printk(KERN_ERR, &mp->dev->dev,
1346 "can't allocate rx ring (%d bytes)\n", size);
1347 goto out;
1348 }
1349 memset(rxq->rx_desc_area, 0, size);
1da177e4 1350
8a578111
LB		 1351 rxq->rx_desc_area_size = size;
1352 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1353 GFP_KERNEL);
1354 if (rxq->rx_skb == NULL) {
1355 dev_printk(KERN_ERR, &mp->dev->dev,
1356 "can't allocate rx skb ring\n");
1357 goto out_free;
1358 }
1359
1360 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1361 for (i = 0; i < rxq->rx_ring_size; i++) {
1362 int nexti = (i + 1) % rxq->rx_ring_size;
1363 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1364 nexti * sizeof(struct rx_desc);
1365 }
1366
1367 init_timer(&rxq->rx_oom);
1368 rxq->rx_oom.data = (unsigned long)rxq;
1369 rxq->rx_oom.function = rxq_refill_timer_wrapper;
1370
1371 return 0;
1372
1373
1374out_free:
64da80a2 1375 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size)
8a578111
LB		 1376 iounmap(rxq->rx_desc_area);
1377 else
1378 dma_free_coherent(NULL, size,
1379 rxq->rx_desc_area,
1380 rxq->rx_desc_dma);
1381
1382out:
1383 return -ENOMEM;
c9df406f 1384}
c8aaea25 1385
8a578111 1386static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1387{
8a578111
LB		 1388 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1389 int i;
1390
1391 rxq_disable(rxq);
c8aaea25 1392
8a578111 1393 del_timer_sync(&rxq->rx_oom);
c9df406f 1394
8a578111
LB		 1395 for (i = 0; i < rxq->rx_ring_size; i++) {
1396 if (rxq->rx_skb[i]) {
1397 dev_kfree_skb(rxq->rx_skb[i]);
1398 rxq->rx_desc_count--;
1da177e4 1399 }
c8aaea25 1400 }
1da177e4 1401
8a578111
LB		 1402 if (rxq->rx_desc_count) {
1403 dev_printk(KERN_ERR, &mp->dev->dev,
1404 "error freeing rx ring -- %d skbs stuck\n",
1405 rxq->rx_desc_count);
1406 }
1407
64da80a2
LB		 1408 if (rxq->index == mp->rxq_primary &&
1409 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1410 iounmap(rxq->rx_desc_area);
c9df406f 1411 else
8a578111
LB		 1412 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1413 rxq->rx_desc_area, rxq->rx_desc_dma);
1414
1415 kfree(rxq->rx_skb);
c9df406f 1416}
1da177e4 1417
13d64285 1418static int txq_init(struct mv643xx_eth_private *mp)
c9df406f 1419{
13d64285
LB		 1420 struct tx_queue *txq = mp->txq;
1421 struct tx_desc *tx_desc;
1422 int size;
c9df406f 1423 int i;
1da177e4 1424
13d64285
LB		 1425 txq->tx_ring_size = mp->default_tx_ring_size;
1426
1427 txq->tx_desc_count = 0;
1428 txq->tx_curr_desc = 0;
1429 txq->tx_used_desc = 0;
1430
1431 size = txq->tx_ring_size * sizeof(struct tx_desc);
1432
1433 if (size <= mp->tx_desc_sram_size) {
1434 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1435 mp->tx_desc_sram_size);
1436 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1437 } else {
1438 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1439 &txq->tx_desc_dma,
1440 GFP_KERNEL);
1441 }
1442
1443 if (txq->tx_desc_area == NULL) {
1444 dev_printk(KERN_ERR, &mp->dev->dev,
1445 "can't allocate tx ring (%d bytes)\n", size);
1446 goto out;
c9df406f 1447 }
13d64285
LB		 1448 memset(txq->tx_desc_area, 0, size);
1449
1450 txq->tx_desc_area_size = size;
1451 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1452 GFP_KERNEL);
1453 if (txq->tx_skb == NULL) {
1454 dev_printk(KERN_ERR, &mp->dev->dev,
1455 "can't allocate tx skb ring\n");
1456 goto out_free;
1457 }
1458
1459 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1460 for (i = 0; i < txq->tx_ring_size; i++) {
1461 int nexti = (i + 1) % txq->tx_ring_size;
1462 tx_desc[i].next_desc_ptr = txq->tx_desc_dma +
1463 nexti * sizeof(struct tx_desc);
1464 }
1465
1466 return 0;
1467
c9df406f 1468
13d64285
LB		 1469out_free:
1470 if (size <= mp->tx_desc_sram_size)
1471 iounmap(txq->tx_desc_area);
1472 else
1473 dma_free_coherent(NULL, size,
1474 txq->tx_desc_area,
1475 txq->tx_desc_dma);
c9df406f 1476
13d64285
LB		 1477out:
1478 return -ENOMEM;
c8aaea25 1479}
1da177e4 1480
13d64285 1481static void txq_reclaim(struct tx_queue *txq, int force)
c8aaea25 1482{
13d64285 1483 struct mv643xx_eth_private *mp = txq_to_mp(txq);
c8aaea25 1484 unsigned long flags;
1da177e4 1485
13d64285
LB		 1486 spin_lock_irqsave(&mp->lock, flags);
1487 while (txq->tx_desc_count > 0) {
1488 int tx_index;
1489 struct tx_desc *desc;
1490 u32 cmd_sts;
1491 struct sk_buff *skb;
1492 dma_addr_t addr;
1493 int count;
4d64e718 1494
13d64285
LB		 1495 tx_index = txq->tx_used_desc;
1496 desc = &txq->tx_desc_area[tx_index];
c9df406f 1497 cmd_sts = desc->cmd_sts;
4d64e718 1498
13d64285
LB		 1499 if (!force && (cmd_sts & BUFFER_OWNED_BY_DMA))
1500 break;
1da177e4 1501
13d64285
LB		 1502 txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size;
1503 txq->tx_desc_count--;
1da177e4 1504
c9df406f
LB		 1505 addr = desc->buf_ptr;
1506 count = desc->byte_cnt;
13d64285
LB		 1507 skb = txq->tx_skb[tx_index];
1508 txq->tx_skb[tx_index] = NULL;
c8aaea25 1509
cc9754b3 1510 if (cmd_sts & ERROR_SUMMARY) {
13d64285
LB		 1511 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1512 mp->dev->stats.tx_errors++;
c9df406f 1513 }
1da177e4 1514
13d64285
LB		 1515 /*
1516 * Drop mp->lock while we free the skb.
1517 */
c9df406f 1518 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 1519
cc9754b3 1520 if (cmd_sts & TX_FIRST_DESC)
c9df406f
LB		 1521 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1522 else
1523 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
c2e5b352 1524
c9df406f
LB		 1525 if (skb)
1526 dev_kfree_skb_irq(skb);
63c9e549 1527
13d64285 1528 spin_lock_irqsave(&mp->lock, flags);
c9df406f 1529 }
13d64285 1530 spin_unlock_irqrestore(&mp->lock, flags);
c9df406f 1531}
1da177e4 1532
13d64285 1533static void txq_deinit(struct tx_queue *txq)
c9df406f 1534{
13d64285 1535 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 1536
13d64285
LB		 1537 txq_disable(txq);
1538 txq_reclaim(txq, 1);
1da177e4 1539
13d64285 1540 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 1541
13d64285
LB		 1542 if (txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1543 iounmap(txq->tx_desc_area);
c9df406f 1544 else
13d64285
LB		 1545 dma_free_coherent(NULL, txq->tx_desc_area_size,
1546 txq->tx_desc_area, txq->tx_desc_dma);
1547
1548 kfree(txq->tx_skb);
c9df406f 1549}
1da177e4 1550
1da177e4 1551
c9df406f 1552/* netdev ops and related ***************************************************/
fc32b0e2 1553static void update_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
c9df406f 1554{
13d64285
LB		 1555 u32 pscr_o;
1556 u32 pscr_n;
1da177e4 1557
13d64285 1558 pscr_o = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
63c9e549 1559
c9df406f 1560 /* clear speed, duplex and rx buffer size fields */
13d64285
LB		 1561 pscr_n = pscr_o & ~(SET_MII_SPEED_TO_100 |
1562 SET_GMII_SPEED_TO_1000 |
1563 SET_FULL_DUPLEX_MODE |
1564 MAX_RX_PACKET_MASK);
1da177e4 1565
fc32b0e2 1566 if (speed == SPEED_1000) {
13d64285
LB		 1567 pscr_n |= SET_GMII_SPEED_TO_1000 | MAX_RX_PACKET_9700BYTE;
1568 } else {
fc32b0e2 1569 if (speed == SPEED_100)
13d64285
LB		 1570 pscr_n |= SET_MII_SPEED_TO_100;
1571 pscr_n |= MAX_RX_PACKET_1522BYTE;
c9df406f 1572 }
1da177e4 1573
fc32b0e2 1574 if (duplex == DUPLEX_FULL)
13d64285
LB		 1575 pscr_n |= SET_FULL_DUPLEX_MODE;
1576
1577 if (pscr_n != pscr_o) {
1578 if ((pscr_o & SERIAL_PORT_ENABLE) == 0)
1579 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
c9df406f 1580 else {
13d64285
LB		 1581 txq_disable(mp->txq);
1582 pscr_o &= ~SERIAL_PORT_ENABLE;
1583 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_o);
1584 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1585 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1586 txq_enable(mp->txq);
c9df406f
LB		 1587 }
1588 }
1589}
84dd619e 1590
fc32b0e2 1591static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
c9df406f
LB		 1592{
1593 struct net_device *dev = (struct net_device *)dev_id;
e5371493 1594 struct mv643xx_eth_private *mp = netdev_priv(dev);
fc32b0e2
LB		 1595 u32 int_cause;
1596 u32 int_cause_ext;
ce4e2e45 1597
13d64285 1598 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) & (INT_RX | INT_EXT);
fc32b0e2
LB		 1599 if (int_cause == 0)
1600 return IRQ_NONE;
1601
1602 int_cause_ext = 0;
cc9754b3 1603 if (int_cause & INT_EXT) {
13d64285 1604 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
073a345c 1605 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
13d64285 1606 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
c9df406f 1607 }
1da177e4 1608
fc32b0e2 1609 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK)) {
c9df406f 1610 if (mii_link_ok(&mp->mii)) {
13d64285
LB		 1611 struct ethtool_cmd cmd;
1612
c9df406f 1613 mii_ethtool_gset(&mp->mii, &cmd);
fc32b0e2 1614 update_pscr(mp, cmd.speed, cmd.duplex);
13d64285 1615 txq_enable(mp->txq);
c9df406f
LB		 1616 if (!netif_carrier_ok(dev)) {
1617 netif_carrier_on(dev);
13d64285 1618 __txq_maybe_wake(mp->txq);
c9df406f
LB		 1619 }
1620 } else if (netif_carrier_ok(dev)) {
1621 netif_stop_queue(dev);
1622 netif_carrier_off(dev);
1623 }
1624 }
1da177e4 1625
64da80a2
LB		 1626 /*
1627 * RxBuffer or RxError set for any of the 8 queues?
1628 */
e5371493 1629#ifdef MV643XX_ETH_NAPI
cc9754b3 1630 if (int_cause & INT_RX) {
13d64285 1631 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
13d64285 1632 rdl(mp, INT_MASK(mp->port_num));
1da177e4 1633
c9df406f 1634 netif_rx_schedule(dev, &mp->napi);
84dd619e 1635 }
c9df406f 1636#else
64da80a2
LB		 1637 if (int_cause & INT_RX) {
1638 int i;
1639
1640 for (i = 7; i >= 0; i--)
1641 if (mp->rxq_mask & (1 << i))
1642 rxq_process(mp->rxq + i, INT_MAX);
1643 }
c9df406f 1644#endif
fc32b0e2 1645
13d64285
LB		 1646 if (int_cause_ext & INT_EXT_TX) {
1647 txq_reclaim(mp->txq, 0);
1648 __txq_maybe_wake(mp->txq);
1649 }
1da177e4 1650
c9df406f 1651 return IRQ_HANDLED;
1da177e4
LT		 1652}
1653
e5371493 1654static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 1655{
fc32b0e2 1656 unsigned int data;
1da177e4 1657
fc32b0e2
LB		 1658 smi_reg_read(mp, mp->phy_addr, 0, &data);
1659 data |= 0x8000;
1660 smi_reg_write(mp, mp->phy_addr, 0, data);
1da177e4 1661
c9df406f
LB		 1662 do {
1663 udelay(1);
fc32b0e2
LB		 1664 smi_reg_read(mp, mp->phy_addr, 0, &data);
1665 } while (data & 0x8000);
1da177e4
LT		 1666}
1667
fc32b0e2 1668static void port_start(struct mv643xx_eth_private *mp)
1da177e4 1669{
d0412d96
JC		 1670 u32 pscr;
1671 struct ethtool_cmd ethtool_cmd;
8a578111 1672 int i;
1da177e4 1673
8a578111
LB		 1674 /*
1675 * Configure basic link parameters.
1676 */
1677 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1678 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
1679 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1680 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1681 DISABLE_AUTO_NEG_SPEED_GMII |
1682 DISABLE_AUTO_NEG_FOR_DUPLEX |
1683 DO_NOT_FORCE_LINK_FAIL |
1684 SERIAL_PORT_CONTROL_RESERVED;
1685 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1686 pscr |= SERIAL_PORT_ENABLE;
1687 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1da177e4 1688
8a578111
LB		 1689 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1690
fc32b0e2 1691 mv643xx_eth_get_settings(mp->dev, &ethtool_cmd);
8a578111 1692 phy_reset(mp);
fc32b0e2 1693 mv643xx_eth_set_settings(mp->dev, &ethtool_cmd);
1da177e4 1694
13d64285
LB		 1695 /*
1696 * Configure TX path and queues.
1697 */
89df5fdc 1698 tx_set_rate(mp, 1000000000, 16777216);
13d64285
LB		 1699 for (i = 0; i < 1; i++) {
1700 struct tx_queue *txq = mp->txq;
1701 int off = TXQ_CURRENT_DESC_PTR(mp->port_num);
1702 u32 addr;
1703
1704 addr = (u32)txq->tx_desc_dma;
1705 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
1706 wrl(mp, off, addr);
89df5fdc
LB		 1707
1708 txq_set_rate(txq, 1000000000, 16777216);
1709 txq_set_fixed_prio_mode(txq);
13d64285
LB		 1710 }
1711
fc32b0e2
LB		 1712 /*
1713 * Add configured unicast address to address filter table.
1714 */
1715 uc_addr_set(mp, mp->dev->dev_addr);
1da177e4 1716
d9a073ea
LB		 1717 /*
1718 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1719 * frames to RX queue #0.
1720 */
8a578111 1721 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
01999873 1722
376489a2
LB		 1723 /*
1724 * Treat BPDUs as normal multicasts, and disable partition mode.
1725 */
8a578111 1726 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
01999873 1727
8a578111 1728 /*
64da80a2 1729 * Enable the receive queues.
8a578111 1730 */
64da80a2
LB		 1731 for (i = 0; i < 8; i++) {
1732 struct rx_queue *rxq = mp->rxq + i;
1733 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
8a578111 1734 u32 addr;
1da177e4 1735
64da80a2
LB		 1736 if ((mp->rxq_mask & (1 << i)) == 0)
1737 continue;
1738
8a578111
LB		 1739 addr = (u32)rxq->rx_desc_dma;
1740 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1741 wrl(mp, off, addr);
1da177e4 1742
8a578111
LB		 1743 rxq_enable(rxq);
1744 }
1da177e4
LT		 1745}
1746
ffd86bbe 1747static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 1748{
c9df406f 1749 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 1750
fc32b0e2
LB		 1751 if (coal > 0x3fff)
1752 coal = 0x3fff;
1753
1754 wrl(mp, SDMA_CONFIG(mp->port_num),
c9df406f 1755 ((coal & 0x3fff) << 8) |
fc32b0e2 1756 (rdl(mp, SDMA_CONFIG(mp->port_num))
c9df406f 1757 & 0xffc000ff));
1da177e4
LT		 1758}
1759
ffd86bbe 1760static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 1761{
c9df406f 1762 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 1763
fc32b0e2
LB		 1764 if (coal > 0x3fff)
1765 coal = 0x3fff;
1766 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
16e03018
DF		 1767}
1768
c9df406f 1769static int mv643xx_eth_open(struct net_device *dev)
16e03018 1770{
e5371493 1771 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1772 int err;
64da80a2 1773 int i;
16e03018 1774
fc32b0e2
LB		 1775 wrl(mp, INT_CAUSE(mp->port_num), 0);
1776 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
1777 rdl(mp, INT_CAUSE_EXT(mp->port_num));
c9df406f 1778
fc32b0e2
LB		 1779 err = request_irq(dev->irq, mv643xx_eth_irq,
1780 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
1781 dev->name, dev);
c9df406f 1782 if (err) {
fc32b0e2 1783 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
c9df406f 1784 return -EAGAIN;
16e03018
DF		 1785 }
1786
fc32b0e2 1787 init_mac_tables(mp);
16e03018 1788
64da80a2
LB		 1789 for (i = 0; i < 8; i++) {
1790 if ((mp->rxq_mask & (1 << i)) == 0)
1791 continue;
1792
1793 err = rxq_init(mp, i);
1794 if (err) {
1795 while (--i >= 0)
1796 if (mp->rxq_mask & (1 << i))
1797 rxq_deinit(mp->rxq + i);
1798 goto out;
1799 }
1800
1801 rxq_refill(mp->rxq + i);
1802 }
8a578111 1803
13d64285
LB		 1804 err = txq_init(mp);
1805 if (err)
fc32b0e2 1806 goto out_free;
16e03018 1807
e5371493 1808#ifdef MV643XX_ETH_NAPI
c9df406f
LB		 1809 napi_enable(&mp->napi);
1810#endif
16e03018 1811
fc32b0e2 1812 port_start(mp);
16e03018 1813
ffd86bbe
LB		 1814 set_rx_coal(mp, 0);
1815 set_tx_coal(mp, 0);
16e03018 1816
fc32b0e2
LB		 1817 wrl(mp, INT_MASK_EXT(mp->port_num),
1818 INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
16e03018 1819
fc32b0e2 1820 wrl(mp, INT_MASK(mp->port_num), INT_RX | INT_EXT);
16e03018 1821
c9df406f
LB		 1822 return 0;
1823
13d64285 1824
fc32b0e2 1825out_free:
64da80a2
LB		 1826 for (i = 0; i < 8; i++)
1827 if (mp->rxq_mask & (1 << i))
1828 rxq_deinit(mp->rxq + i);
fc32b0e2 1829out:
c9df406f
LB		 1830 free_irq(dev->irq, dev);
1831
1832 return err;
16e03018
DF		 1833}
1834
e5371493 1835static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 1836{
fc32b0e2 1837 unsigned int data;
64da80a2 1838 int i;
1da177e4 1839
64da80a2
LB		 1840 for (i = 0; i < 8; i++) {
1841 if (mp->rxq_mask & (1 << i))
1842 rxq_disable(mp->rxq + i);
1843 }
13d64285 1844 txq_disable(mp->txq);
13d64285
LB		 1845 while (!(rdl(mp, PORT_STATUS(mp->port_num)) & TX_FIFO_EMPTY))
1846 udelay(10);
1da177e4 1847
c9df406f 1848 /* Reset the Enable bit in the Configuration Register */
fc32b0e2
LB		 1849 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1850 data &= ~(SERIAL_PORT_ENABLE |
1851 DO_NOT_FORCE_LINK_FAIL |
1852 FORCE_LINK_PASS);
1853 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
1da177e4
LT		 1854}
1855
c9df406f 1856static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 1857{
e5371493 1858 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 1859 int i;
1da177e4 1860
fc32b0e2
LB		 1861 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1862 rdl(mp, INT_MASK(mp->port_num));
1da177e4 1863
e5371493 1864#ifdef MV643XX_ETH_NAPI
c9df406f
LB		 1865 napi_disable(&mp->napi);
1866#endif
1867 netif_carrier_off(dev);
1868 netif_stop_queue(dev);
1da177e4 1869
fc32b0e2
LB		 1870 free_irq(dev->irq, dev);
1871
cc9754b3 1872 port_reset(mp);
fc32b0e2 1873 mib_counters_update(mp);
1da177e4 1874
64da80a2
LB		 1875 for (i = 0; i < 8; i++) {
1876 if (mp->rxq_mask & (1 << i))
1877 rxq_deinit(mp->rxq + i);
1878 }
13d64285 1879 txq_deinit(mp->txq);
1da177e4 1880
c9df406f 1881 return 0;
1da177e4
LT		 1882}
1883
fc32b0e2 1884static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 1885{
e5371493 1886 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1887
c9df406f 1888 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
1da177e4
LT		 1889}
1890
c9df406f 1891static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 1892{
89df5fdc
LB		 1893 struct mv643xx_eth_private *mp = netdev_priv(dev);
1894
fc32b0e2 1895 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 1896 return -EINVAL;
1da177e4 1897
c9df406f 1898 dev->mtu = new_mtu;
89df5fdc
LB		 1899 tx_set_rate(mp, 1000000000, 16777216);
1900
c9df406f
LB		 1901 if (!netif_running(dev))
1902 return 0;
1da177e4 1903
c9df406f
LB		 1904 /*
1905 * Stop and then re-open the interface. This will allocate RX
1906 * skbs of the new MTU.
1907 * There is a possible danger that the open will not succeed,
fc32b0e2 1908 * due to memory being full.
c9df406f
LB		 1909 */
1910 mv643xx_eth_stop(dev);
1911 if (mv643xx_eth_open(dev)) {
fc32b0e2
LB		 1912 dev_printk(KERN_ERR, &dev->dev,
1913 "fatal error on re-opening device after "
1914 "MTU change\n");
c9df406f
LB		 1915 }
1916
1917 return 0;
1da177e4
LT		 1918}
1919
fc32b0e2 1920static void tx_timeout_task(struct work_struct *ugly)
1da177e4 1921{
fc32b0e2 1922 struct mv643xx_eth_private *mp;
1da177e4 1923
fc32b0e2
LB		 1924 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
1925 if (netif_running(mp->dev)) {
1926 netif_stop_queue(mp->dev);
c9df406f 1927
fc32b0e2
LB		 1928 port_reset(mp);
1929 port_start(mp);
c9df406f 1930
fc32b0e2
LB		 1931 __txq_maybe_wake(mp->txq);
1932 }
c9df406f
LB		 1933}
1934
c9df406f 1935static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 1936{
e5371493 1937 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1938
fc32b0e2 1939 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
d0412d96 1940
c9df406f 1941 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 1942}
1943
c9df406f 1944#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 1945static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 1946{
fc32b0e2 1947 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1948
fc32b0e2
LB		 1949 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1950 rdl(mp, INT_MASK(mp->port_num));
c9df406f 1951
fc32b0e2 1952 mv643xx_eth_irq(dev->irq, dev);
c9df406f 1953
fc32b0e2 1954 wrl(mp, INT_MASK(mp->port_num), INT_RX | INT_CAUSE_EXT);
9f8dd319 1955}
c9df406f 1956#endif
9f8dd319 1957
fc32b0e2 1958static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
9f8dd319 1959{
e5371493 1960 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f
LB		 1961 int val;
1962
fc32b0e2
LB		 1963 smi_reg_read(mp, addr, reg, &val);
1964
c9df406f 1965 return val;
9f8dd319
DF		 1966}
1967
fc32b0e2 1968static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
9f8dd319 1969{
e5371493 1970 struct mv643xx_eth_private *mp = netdev_priv(dev);
fc32b0e2 1971 smi_reg_write(mp, addr, reg, val);
c9df406f 1972}
9f8dd319 1973
9f8dd319 1974
c9df406f 1975/* platform glue ************************************************************/
e5371493
LB		 1976static void
1977mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
1978 struct mbus_dram_target_info *dram)
c9df406f 1979{
cc9754b3 1980 void __iomem *base = msp->base;
c9df406f
LB		 1981 u32 win_enable;
1982 u32 win_protect;
1983 int i;
9f8dd319 1984
c9df406f
LB		 1985 for (i = 0; i < 6; i++) {
1986 writel(0, base + WINDOW_BASE(i));
1987 writel(0, base + WINDOW_SIZE(i));
1988 if (i < 4)
1989 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 1990 }
1991
c9df406f
LB		 1992 win_enable = 0x3f;
1993 win_protect = 0;
1994
1995 for (i = 0; i < dram->num_cs; i++) {
1996 struct mbus_dram_window *cs = dram->cs + i;
1997
1998 writel((cs->base & 0xffff0000) |
1999 (cs->mbus_attr << 8) |
2000 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2001 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2002
2003 win_enable &= ~(1 << i);
2004 win_protect |= 3 << (2 * i);
2005 }
2006
2007 writel(win_enable, base + WINDOW_BAR_ENABLE);
2008 msp->win_protect = win_protect;
9f8dd319
DF		 2009}
2010
c9df406f 2011static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2012{
e5371493 2013 static int mv643xx_eth_version_printed = 0;
c9df406f 2014 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2015 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 2016 struct resource *res;
2017 int ret;
9f8dd319 2018
e5371493 2019 if (!mv643xx_eth_version_printed++)
c9df406f 2020 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
9f8dd319 2021
c9df406f
LB		 2022 ret = -EINVAL;
2023 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2024 if (res == NULL)
2025 goto out;
9f8dd319 2026
c9df406f
LB		 2027 ret = -ENOMEM;
2028 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2029 if (msp == NULL)
2030 goto out;
2031 memset(msp, 0, sizeof(*msp));
2032
cc9754b3
LB		 2033 msp->base = ioremap(res->start, res->end - res->start + 1);
2034 if (msp->base == NULL)
c9df406f
LB		 2035 goto out_free;
2036
2037 spin_lock_init(&msp->phy_lock);
c9df406f
LB		 2038
2039 /*
2040 * (Re-)program MBUS remapping windows if we are asked to.
2041 */
2042 if (pd != NULL && pd->dram != NULL)
2043 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2044
fc32b0e2
LB		 2045 /*
2046 * Detect hardware parameters.
2047 */
2048 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2049
2050 platform_set_drvdata(pdev, msp);
2051
c9df406f
LB		 2052 return 0;
2053
2054out_free:
2055 kfree(msp);
2056out:
2057 return ret;
2058}
2059
2060static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2061{
e5371493 2062 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
c9df406f 2063
cc9754b3 2064 iounmap(msp->base);
c9df406f
LB		 2065 kfree(msp);
2066
2067 return 0;
9f8dd319
DF		 2068}
2069
c9df406f 2070static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2071 .probe = mv643xx_eth_shared_probe,
2072 .remove = mv643xx_eth_shared_remove,
c9df406f 2073 .driver = {
fc32b0e2 2074 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2075 .owner = THIS_MODULE,
2076 },
2077};
2078
e5371493 2079static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2080{
c9df406f 2081 int addr_shift = 5 * mp->port_num;
fc32b0e2 2082 u32 data;
1da177e4 2083
fc32b0e2
LB		 2084 data = rdl(mp, PHY_ADDR);
2085 data &= ~(0x1f << addr_shift);
2086 data |= (phy_addr & 0x1f) << addr_shift;
2087 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2088}
2089
e5371493 2090static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2091{
fc32b0e2
LB		 2092 unsigned int data;
2093
2094 data = rdl(mp, PHY_ADDR);
2095
2096 return (data >> (5 * mp->port_num)) & 0x1f;
2097}
2098
2099static void set_params(struct mv643xx_eth_private *mp,
2100 struct mv643xx_eth_platform_data *pd)
2101{
2102 struct net_device *dev = mp->dev;
2103
2104 if (is_valid_ether_addr(pd->mac_addr))
2105 memcpy(dev->dev_addr, pd->mac_addr, 6);
2106 else
2107 uc_addr_get(mp, dev->dev_addr);
2108
2109 if (pd->phy_addr == -1) {
2110 mp->shared_smi = NULL;
2111 mp->phy_addr = -1;
2112 } else {
2113 mp->shared_smi = mp->shared;
2114 if (pd->shared_smi != NULL)
2115 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2116
2117 if (pd->force_phy_addr || pd->phy_addr) {
2118 mp->phy_addr = pd->phy_addr & 0x3f;
2119 phy_addr_set(mp, mp->phy_addr);
2120 } else {
2121 mp->phy_addr = phy_addr_get(mp);
2122 }
2123 }
1da177e4 2124
fc32b0e2
LB		 2125 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2126 if (pd->rx_queue_size)
2127 mp->default_rx_ring_size = pd->rx_queue_size;
2128 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2129 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2130
64da80a2
LB		 2131 if (pd->rx_queue_mask)
2132 mp->rxq_mask = pd->rx_queue_mask;
2133 else
2134 mp->rxq_mask = 0x01;
2135 mp->rxq_primary = fls(mp->rxq_mask) - 1;
2136
fc32b0e2
LB		 2137 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2138 if (pd->tx_queue_size)
2139 mp->default_tx_ring_size = pd->tx_queue_size;
2140 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2141 mp->tx_desc_sram_size = pd->tx_sram_size;
1da177e4
LT		 2142}
2143
e5371493 2144static int phy_detect(struct mv643xx_eth_private *mp)
1da177e4 2145{
fc32b0e2
LB		 2146 unsigned int data;
2147 unsigned int data2;
2148
2149 smi_reg_read(mp, mp->phy_addr, 0, &data);
2150 smi_reg_write(mp, mp->phy_addr, 0, data ^ 0x1000);
1da177e4 2151
fc32b0e2
LB		 2152 smi_reg_read(mp, mp->phy_addr, 0, &data2);
2153 if (((data ^ data2) & 0x1000) == 0)
2154 return -ENODEV;
1da177e4 2155
fc32b0e2 2156 smi_reg_write(mp, mp->phy_addr, 0, data);
1da177e4 2157
c9df406f 2158 return 0;
1da177e4
LT		 2159}
2160
fc32b0e2
LB		 2161static int phy_init(struct mv643xx_eth_private *mp,
2162 struct mv643xx_eth_platform_data *pd)
c28a4f89 2163{
fc32b0e2
LB		 2164 struct ethtool_cmd cmd;
2165 int err;
c28a4f89 2166
fc32b0e2
LB		 2167 err = phy_detect(mp);
2168 if (err) {
2169 dev_printk(KERN_INFO, &mp->dev->dev,
2170 "no PHY detected at addr %d\n", mp->phy_addr);
2171 return err;
2172 }
2173 phy_reset(mp);
2174
2175 mp->mii.phy_id = mp->phy_addr;
2176 mp->mii.phy_id_mask = 0x3f;
2177 mp->mii.reg_num_mask = 0x1f;
2178 mp->mii.dev = mp->dev;
2179 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2180 mp->mii.mdio_write = mv643xx_eth_mdio_write;
c28a4f89 2181
fc32b0e2 2182 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
c9df406f 2183
fc32b0e2
LB		 2184 memset(&cmd, 0, sizeof(cmd));
2185
2186 cmd.port = PORT_MII;
2187 cmd.transceiver = XCVR_INTERNAL;
2188 cmd.phy_address = mp->phy_addr;
2189 if (pd->speed == 0) {
2190 cmd.autoneg = AUTONEG_ENABLE;
2191 cmd.speed = SPEED_100;
2192 cmd.advertising = ADVERTISED_10baseT_Half |
2193 ADVERTISED_10baseT_Full |
2194 ADVERTISED_100baseT_Half |
2195 ADVERTISED_100baseT_Full;
c9df406f 2196 if (mp->mii.supports_gmii)
fc32b0e2 2197 cmd.advertising |= ADVERTISED_1000baseT_Full;
c9df406f 2198 } else {
fc32b0e2
LB		 2199 cmd.autoneg = AUTONEG_DISABLE;
2200 cmd.speed = pd->speed;
2201 cmd.duplex = pd->duplex;
c9df406f 2202 }
fc32b0e2
LB		 2203
2204 update_pscr(mp, cmd.speed, cmd.duplex);
2205 mv643xx_eth_set_settings(mp->dev, &cmd);
2206
2207 return 0;
c28a4f89
JC		 2208}
2209
c9df406f 2210static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2211{
c9df406f 2212 struct mv643xx_eth_platform_data *pd;
e5371493 2213 struct mv643xx_eth_private *mp;
c9df406f 2214 struct net_device *dev;
c9df406f 2215 struct resource *res;
c9df406f 2216 DECLARE_MAC_BUF(mac);
fc32b0e2 2217 int err;
1da177e4 2218
c9df406f
LB		 2219 pd = pdev->dev.platform_data;
2220 if (pd == NULL) {
fc32b0e2
LB		 2221 dev_printk(KERN_ERR, &pdev->dev,
2222 "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2223 return -ENODEV;
2224 }
1da177e4 2225
c9df406f 2226 if (pd->shared == NULL) {
fc32b0e2
LB		 2227 dev_printk(KERN_ERR, &pdev->dev,
2228 "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2229 return -ENODEV;
2230 }
8f518703 2231
e5371493 2232 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
c9df406f
LB		 2233 if (!dev)
2234 return -ENOMEM;
1da177e4 2235
c9df406f 2236 mp = netdev_priv(dev);
fc32b0e2
LB		 2237 platform_set_drvdata(pdev, mp);
2238
2239 mp->shared = platform_get_drvdata(pd->shared);
2240 mp->port_num = pd->port_number;
2241
c9df406f 2242 mp->dev = dev;
e5371493
LB		 2243#ifdef MV643XX_ETH_NAPI
2244 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
c9df406f 2245#endif
1da177e4 2246
fc32b0e2
LB		 2247 set_params(mp, pd);
2248
2249 spin_lock_init(&mp->lock);
2250
2251 mib_counters_clear(mp);
2252 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2253
2254 err = phy_init(mp, pd);
2255 if (err)
2256 goto out;
2257 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2258
2259
c9df406f
LB		 2260 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2261 BUG_ON(!res);
2262 dev->irq = res->start;
1da177e4 2263
fc32b0e2 2264 dev->hard_start_xmit = mv643xx_eth_xmit;
c9df406f
LB		 2265 dev->open = mv643xx_eth_open;
2266 dev->stop = mv643xx_eth_stop;
c9df406f 2267 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
fc32b0e2
LB		 2268 dev->set_mac_address = mv643xx_eth_set_mac_address;
2269 dev->do_ioctl = mv643xx_eth_ioctl;
2270 dev->change_mtu = mv643xx_eth_change_mtu;
c9df406f 2271 dev->tx_timeout = mv643xx_eth_tx_timeout;
c9df406f 2272#ifdef CONFIG_NET_POLL_CONTROLLER
e5371493 2273 dev->poll_controller = mv643xx_eth_netpoll;
c9df406f 2274#endif
c9df406f
LB		 2275 dev->watchdog_timeo = 2 * HZ;
2276 dev->base_addr = 0;
1da177e4 2277
e5371493 2278#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
b4de9051 2279 /*
c9df406f
LB		 2280 * Zero copy can only work if we use Discovery II memory. Else, we will
2281 * have to map the buffers to ISA memory which is only 16 MB
b4de9051 2282 */
c9df406f 2283 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
c9df406f 2284#endif
1da177e4 2285
fc32b0e2 2286 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2287
c9df406f 2288 if (mp->shared->win_protect)
fc32b0e2 2289 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2290
c9df406f
LB		 2291 err = register_netdev(dev);
2292 if (err)
2293 goto out;
1da177e4 2294
fc32b0e2
LB		 2295 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2296 mp->port_num, print_mac(mac, dev->dev_addr));
1da177e4 2297
c9df406f 2298 if (dev->features & NETIF_F_SG)
fc32b0e2 2299 dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n");
1da177e4 2300
c9df406f 2301 if (dev->features & NETIF_F_IP_CSUM)
fc32b0e2 2302 dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n");
1da177e4 2303
e5371493 2304#ifdef MV643XX_ETH_NAPI
fc32b0e2 2305 dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n");
c9df406f 2306#endif
1da177e4 2307
13d64285 2308 if (mp->tx_desc_sram_size > 0)
fc32b0e2 2309 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
1da177e4 2310
c9df406f 2311 return 0;
1da177e4 2312
c9df406f
LB		 2313out:
2314 free_netdev(dev);
1da177e4 2315
c9df406f 2316 return err;
1da177e4
LT		 2317}
2318
c9df406f 2319static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2320{
fc32b0e2 2321 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2322
fc32b0e2 2323 unregister_netdev(mp->dev);
c9df406f 2324 flush_scheduled_work();
fc32b0e2 2325 free_netdev(mp->dev);
c9df406f 2326
c9df406f 2327 platform_set_drvdata(pdev, NULL);
fc32b0e2 2328
c9df406f 2329 return 0;
1da177e4
LT		 2330}
2331
c9df406f 2332static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2333{
fc32b0e2 2334 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 2335
c9df406f 2336 /* Mask all interrupts on ethernet port */
fc32b0e2
LB		 2337 wrl(mp, INT_MASK(mp->port_num), 0);
2338 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2339
fc32b0e2
LB		 2340 if (netif_running(mp->dev))
2341 port_reset(mp);
d0412d96
JC		 2342}
2343
c9df406f 2344static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 2345 .probe = mv643xx_eth_probe,
2346 .remove = mv643xx_eth_remove,
2347 .shutdown = mv643xx_eth_shutdown,
c9df406f 2348 .driver = {
fc32b0e2 2349 .name = MV643XX_ETH_NAME,
c9df406f
LB		 2350 .owner = THIS_MODULE,
2351 },
2352};
2353
e5371493 2354static int __init mv643xx_eth_init_module(void)
d0412d96 2355{
c9df406f 2356 int rc;
d0412d96 2357
c9df406f
LB		 2358 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2359 if (!rc) {
2360 rc = platform_driver_register(&mv643xx_eth_driver);
2361 if (rc)
2362 platform_driver_unregister(&mv643xx_eth_shared_driver);
2363 }
fc32b0e2 2364
c9df406f 2365 return rc;
d0412d96 2366}
fc32b0e2 2367module_init(mv643xx_eth_init_module);
d0412d96 2368
e5371493 2369static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 2370{
c9df406f
LB		 2371 platform_driver_unregister(&mv643xx_eth_driver);
2372 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 2373}
e5371493 2374module_exit(mv643xx_eth_cleanup_module);
1da177e4 2375
fc32b0e2
LB		 2376MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani "
2377 "and Dale Farnsworth");
c9df406f 2378MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 2379MODULE_LICENSE("GPL");
c9df406f 2380MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 2381MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux kernel - Deliverables
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