Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
9c1bbdfe | 2 | * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports |
1da177e4 LT |
3 | * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com> |
4 | * | |
5 | * Based on the 64360 driver from: | |
4547fa61 LB |
6 | * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il> |
7 | * Rabeeh Khoury <rabeeh@marvell.com> | |
1da177e4 LT |
8 | * |
9 | * Copyright (C) 2003 PMC-Sierra, Inc., | |
3bb8a18a | 10 | * written by Manish Lachwani |
1da177e4 LT |
11 | * |
12 | * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> | |
13 | * | |
c8aaea25 | 14 | * Copyright (C) 2004-2006 MontaVista Software, Inc. |
1da177e4 LT |
15 | * Dale Farnsworth <dale@farnsworth.org> |
16 | * | |
17 | * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com> | |
18 | * <sjhill@realitydiluted.com> | |
19 | * | |
4547fa61 LB |
20 | * Copyright (C) 2007-2008 Marvell Semiconductor |
21 | * Lennert Buytenhek <buytenh@marvell.com> | |
22 | * | |
1da177e4 LT |
23 | * This program is free software; you can redistribute it and/or |
24 | * modify it under the terms of the GNU General Public License | |
25 | * as published by the Free Software Foundation; either version 2 | |
26 | * of the License, or (at your option) any later version. | |
27 | * | |
28 | * This program is distributed in the hope that it will be useful, | |
29 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
30 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
31 | * GNU General Public License for more details. | |
32 | * | |
33 | * You should have received a copy of the GNU General Public License | |
34 | * along with this program; if not, write to the Free Software | |
35 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
36 | */ | |
a779d38c | 37 | |
1da177e4 LT |
38 | #include <linux/init.h> |
39 | #include <linux/dma-mapping.h> | |
b6298c22 | 40 | #include <linux/in.h> |
1da177e4 LT |
41 | #include <linux/tcp.h> |
42 | #include <linux/udp.h> | |
43 | #include <linux/etherdevice.h> | |
1da177e4 LT |
44 | #include <linux/delay.h> |
45 | #include <linux/ethtool.h> | |
d052d1be | 46 | #include <linux/platform_device.h> |
fbd6a754 LB |
47 | #include <linux/module.h> |
48 | #include <linux/kernel.h> | |
49 | #include <linux/spinlock.h> | |
50 | #include <linux/workqueue.h> | |
51 | #include <linux/mii.h> | |
fbd6a754 | 52 | #include <linux/mv643xx_eth.h> |
1da177e4 LT |
53 | #include <asm/io.h> |
54 | #include <asm/types.h> | |
1da177e4 | 55 | #include <asm/system.h> |
fbd6a754 | 56 | |
e5371493 | 57 | static char mv643xx_eth_driver_name[] = "mv643xx_eth"; |
45675bc6 | 58 | static char mv643xx_eth_driver_version[] = "1.1"; |
c9df406f | 59 | |
e5371493 LB |
60 | #define MV643XX_ETH_CHECKSUM_OFFLOAD_TX |
61 | #define MV643XX_ETH_NAPI | |
62 | #define MV643XX_ETH_TX_FAST_REFILL | |
fbd6a754 | 63 | |
e5371493 | 64 | #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX |
fbd6a754 LB |
65 | #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1) |
66 | #else | |
67 | #define MAX_DESCS_PER_SKB 1 | |
68 | #endif | |
69 | ||
fbd6a754 LB |
70 | /* |
71 | * Registers shared between all ports. | |
72 | */ | |
3cb4667c LB |
73 | #define PHY_ADDR 0x0000 |
74 | #define SMI_REG 0x0004 | |
75 | #define WINDOW_BASE(w) (0x0200 + ((w) << 3)) | |
76 | #define WINDOW_SIZE(w) (0x0204 + ((w) << 3)) | |
77 | #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2)) | |
78 | #define WINDOW_BAR_ENABLE 0x0290 | |
79 | #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4)) | |
fbd6a754 LB |
80 | |
81 | /* | |
82 | * Per-port registers. | |
83 | */ | |
3cb4667c | 84 | #define PORT_CONFIG(p) (0x0400 + ((p) << 10)) |
d9a073ea | 85 | #define UNICAST_PROMISCUOUS_MODE 0x00000001 |
3cb4667c LB |
86 | #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10)) |
87 | #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10)) | |
88 | #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10)) | |
89 | #define SDMA_CONFIG(p) (0x041c + ((p) << 10)) | |
90 | #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10)) | |
91 | #define PORT_STATUS(p) (0x0444 + ((p) << 10)) | |
a2a41689 | 92 | #define TX_FIFO_EMPTY 0x00000400 |
3cb4667c | 93 | #define TXQ_COMMAND(p) (0x0448 + ((p) << 10)) |
89df5fdc LB |
94 | #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10)) |
95 | #define TX_BW_RATE(p) (0x0450 + ((p) << 10)) | |
3cb4667c | 96 | #define TX_BW_MTU(p) (0x0458 + ((p) << 10)) |
89df5fdc | 97 | #define TX_BW_BURST(p) (0x045c + ((p) << 10)) |
3cb4667c | 98 | #define INT_CAUSE(p) (0x0460 + ((p) << 10)) |
8fa89bf5 | 99 | #define INT_TX_END_0 0x00080000 |
226bb6b7 | 100 | #define INT_TX_END 0x07f80000 |
64da80a2 | 101 | #define INT_RX 0x0007fbfc |
073a345c | 102 | #define INT_EXT 0x00000002 |
3cb4667c | 103 | #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10)) |
073a345c LB |
104 | #define INT_EXT_LINK 0x00100000 |
105 | #define INT_EXT_PHY 0x00010000 | |
106 | #define INT_EXT_TX_ERROR_0 0x00000100 | |
107 | #define INT_EXT_TX_0 0x00000001 | |
3d6b35bc | 108 | #define INT_EXT_TX 0x0000ffff |
3cb4667c LB |
109 | #define INT_MASK(p) (0x0468 + ((p) << 10)) |
110 | #define INT_MASK_EXT(p) (0x046c + ((p) << 10)) | |
111 | #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10)) | |
1e881592 LB |
112 | #define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10)) |
113 | #define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10)) | |
114 | #define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10)) | |
115 | #define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10)) | |
64da80a2 | 116 | #define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4)) |
3cb4667c | 117 | #define RXQ_COMMAND(p) (0x0680 + ((p) << 10)) |
3d6b35bc LB |
118 | #define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2)) |
119 | #define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4)) | |
120 | #define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4)) | |
121 | #define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4)) | |
3cb4667c LB |
122 | #define MIB_COUNTERS(p) (0x1000 + ((p) << 7)) |
123 | #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10)) | |
124 | #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10)) | |
125 | #define UNICAST_TABLE(p) (0x1600 + ((p) << 10)) | |
fbd6a754 | 126 | |
2679a550 LB |
127 | |
128 | /* | |
129 | * SDMA configuration register. | |
130 | */ | |
fbd6a754 | 131 | #define RX_BURST_SIZE_4_64BIT (2 << 1) |
fbd6a754 | 132 | #define BLM_RX_NO_SWAP (1 << 4) |
fbd6a754 | 133 | #define BLM_TX_NO_SWAP (1 << 5) |
fbd6a754 | 134 | #define TX_BURST_SIZE_4_64BIT (2 << 22) |
fbd6a754 LB |
135 | |
136 | #if defined(__BIG_ENDIAN) | |
137 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | |
138 | RX_BURST_SIZE_4_64BIT | \ | |
fbd6a754 LB |
139 | TX_BURST_SIZE_4_64BIT |
140 | #elif defined(__LITTLE_ENDIAN) | |
141 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | |
142 | RX_BURST_SIZE_4_64BIT | \ | |
143 | BLM_RX_NO_SWAP | \ | |
144 | BLM_TX_NO_SWAP | \ | |
fbd6a754 LB |
145 | TX_BURST_SIZE_4_64BIT |
146 | #else | |
147 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | |
148 | #endif | |
149 | ||
2beff77b LB |
150 | |
151 | /* | |
152 | * Port serial control register. | |
153 | */ | |
154 | #define SET_MII_SPEED_TO_100 (1 << 24) | |
155 | #define SET_GMII_SPEED_TO_1000 (1 << 23) | |
156 | #define SET_FULL_DUPLEX_MODE (1 << 21) | |
fbd6a754 LB |
157 | #define MAX_RX_PACKET_9700BYTE (5 << 17) |
158 | #define MAX_RX_PACKET_MASK (7 << 17) | |
2beff77b LB |
159 | #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13) |
160 | #define DO_NOT_FORCE_LINK_FAIL (1 << 10) | |
161 | #define SERIAL_PORT_CONTROL_RESERVED (1 << 9) | |
162 | #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3) | |
163 | #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2) | |
164 | #define FORCE_LINK_PASS (1 << 1) | |
165 | #define SERIAL_PORT_ENABLE (1 << 0) | |
fbd6a754 | 166 | |
cc9754b3 LB |
167 | #define DEFAULT_RX_QUEUE_SIZE 400 |
168 | #define DEFAULT_TX_QUEUE_SIZE 800 | |
fbd6a754 | 169 | |
fbd6a754 | 170 | |
7ca72a3b LB |
171 | /* |
172 | * RX/TX descriptors. | |
fbd6a754 LB |
173 | */ |
174 | #if defined(__BIG_ENDIAN) | |
cc9754b3 | 175 | struct rx_desc { |
fbd6a754 LB |
176 | u16 byte_cnt; /* Descriptor buffer byte count */ |
177 | u16 buf_size; /* Buffer size */ | |
178 | u32 cmd_sts; /* Descriptor command status */ | |
179 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
180 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
181 | }; | |
182 | ||
cc9754b3 | 183 | struct tx_desc { |
fbd6a754 LB |
184 | u16 byte_cnt; /* buffer byte count */ |
185 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
186 | u32 cmd_sts; /* Command/status field */ | |
187 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
188 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
189 | }; | |
190 | #elif defined(__LITTLE_ENDIAN) | |
cc9754b3 | 191 | struct rx_desc { |
fbd6a754 LB |
192 | u32 cmd_sts; /* Descriptor command status */ |
193 | u16 buf_size; /* Buffer size */ | |
194 | u16 byte_cnt; /* Descriptor buffer byte count */ | |
195 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
196 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
197 | }; | |
198 | ||
cc9754b3 | 199 | struct tx_desc { |
fbd6a754 LB |
200 | u32 cmd_sts; /* Command/status field */ |
201 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
202 | u16 byte_cnt; /* buffer byte count */ | |
203 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
204 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
205 | }; | |
206 | #else | |
207 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | |
208 | #endif | |
209 | ||
7ca72a3b | 210 | /* RX & TX descriptor command */ |
cc9754b3 | 211 | #define BUFFER_OWNED_BY_DMA 0x80000000 |
7ca72a3b LB |
212 | |
213 | /* RX & TX descriptor status */ | |
cc9754b3 | 214 | #define ERROR_SUMMARY 0x00000001 |
7ca72a3b LB |
215 | |
216 | /* RX descriptor status */ | |
cc9754b3 LB |
217 | #define LAYER_4_CHECKSUM_OK 0x40000000 |
218 | #define RX_ENABLE_INTERRUPT 0x20000000 | |
219 | #define RX_FIRST_DESC 0x08000000 | |
220 | #define RX_LAST_DESC 0x04000000 | |
7ca72a3b LB |
221 | |
222 | /* TX descriptor command */ | |
cc9754b3 LB |
223 | #define TX_ENABLE_INTERRUPT 0x00800000 |
224 | #define GEN_CRC 0x00400000 | |
225 | #define TX_FIRST_DESC 0x00200000 | |
226 | #define TX_LAST_DESC 0x00100000 | |
227 | #define ZERO_PADDING 0x00080000 | |
228 | #define GEN_IP_V4_CHECKSUM 0x00040000 | |
229 | #define GEN_TCP_UDP_CHECKSUM 0x00020000 | |
230 | #define UDP_FRAME 0x00010000 | |
7ca72a3b | 231 | |
cc9754b3 | 232 | #define TX_IHL_SHIFT 11 |
7ca72a3b LB |
233 | |
234 | ||
c9df406f | 235 | /* global *******************************************************************/ |
e5371493 | 236 | struct mv643xx_eth_shared_private { |
fc32b0e2 LB |
237 | /* |
238 | * Ethernet controller base address. | |
239 | */ | |
cc9754b3 | 240 | void __iomem *base; |
c9df406f | 241 | |
fc32b0e2 LB |
242 | /* |
243 | * Protects access to SMI_REG, which is shared between ports. | |
244 | */ | |
c9df406f LB |
245 | spinlock_t phy_lock; |
246 | ||
fc32b0e2 LB |
247 | /* |
248 | * Per-port MBUS window access register value. | |
249 | */ | |
c9df406f LB |
250 | u32 win_protect; |
251 | ||
fc32b0e2 LB |
252 | /* |
253 | * Hardware-specific parameters. | |
254 | */ | |
c9df406f | 255 | unsigned int t_clk; |
773fc3ee | 256 | int extended_rx_coal_limit; |
1e881592 | 257 | int tx_bw_control_moved; |
c9df406f LB |
258 | }; |
259 | ||
260 | ||
261 | /* per-port *****************************************************************/ | |
e5371493 | 262 | struct mib_counters { |
fbd6a754 LB |
263 | u64 good_octets_received; |
264 | u32 bad_octets_received; | |
265 | u32 internal_mac_transmit_err; | |
266 | u32 good_frames_received; | |
267 | u32 bad_frames_received; | |
268 | u32 broadcast_frames_received; | |
269 | u32 multicast_frames_received; | |
270 | u32 frames_64_octets; | |
271 | u32 frames_65_to_127_octets; | |
272 | u32 frames_128_to_255_octets; | |
273 | u32 frames_256_to_511_octets; | |
274 | u32 frames_512_to_1023_octets; | |
275 | u32 frames_1024_to_max_octets; | |
276 | u64 good_octets_sent; | |
277 | u32 good_frames_sent; | |
278 | u32 excessive_collision; | |
279 | u32 multicast_frames_sent; | |
280 | u32 broadcast_frames_sent; | |
281 | u32 unrec_mac_control_received; | |
282 | u32 fc_sent; | |
283 | u32 good_fc_received; | |
284 | u32 bad_fc_received; | |
285 | u32 undersize_received; | |
286 | u32 fragments_received; | |
287 | u32 oversize_received; | |
288 | u32 jabber_received; | |
289 | u32 mac_receive_error; | |
290 | u32 bad_crc_event; | |
291 | u32 collision; | |
292 | u32 late_collision; | |
293 | }; | |
294 | ||
8a578111 | 295 | struct rx_queue { |
64da80a2 LB |
296 | int index; |
297 | ||
8a578111 LB |
298 | int rx_ring_size; |
299 | ||
300 | int rx_desc_count; | |
301 | int rx_curr_desc; | |
302 | int rx_used_desc; | |
303 | ||
304 | struct rx_desc *rx_desc_area; | |
305 | dma_addr_t rx_desc_dma; | |
306 | int rx_desc_area_size; | |
307 | struct sk_buff **rx_skb; | |
308 | ||
309 | struct timer_list rx_oom; | |
310 | }; | |
311 | ||
13d64285 | 312 | struct tx_queue { |
3d6b35bc LB |
313 | int index; |
314 | ||
13d64285 | 315 | int tx_ring_size; |
fbd6a754 | 316 | |
13d64285 LB |
317 | int tx_desc_count; |
318 | int tx_curr_desc; | |
319 | int tx_used_desc; | |
fbd6a754 | 320 | |
5daffe94 | 321 | struct tx_desc *tx_desc_area; |
fbd6a754 LB |
322 | dma_addr_t tx_desc_dma; |
323 | int tx_desc_area_size; | |
324 | struct sk_buff **tx_skb; | |
13d64285 LB |
325 | }; |
326 | ||
327 | struct mv643xx_eth_private { | |
328 | struct mv643xx_eth_shared_private *shared; | |
fc32b0e2 | 329 | int port_num; |
13d64285 | 330 | |
fc32b0e2 | 331 | struct net_device *dev; |
fbd6a754 | 332 | |
fc32b0e2 LB |
333 | struct mv643xx_eth_shared_private *shared_smi; |
334 | int phy_addr; | |
fbd6a754 | 335 | |
fbd6a754 | 336 | spinlock_t lock; |
fbd6a754 | 337 | |
fc32b0e2 LB |
338 | struct mib_counters mib_counters; |
339 | struct work_struct tx_timeout_task; | |
fbd6a754 | 340 | struct mii_if_info mii; |
8a578111 LB |
341 | |
342 | /* | |
343 | * RX state. | |
344 | */ | |
345 | int default_rx_ring_size; | |
346 | unsigned long rx_desc_sram_addr; | |
347 | int rx_desc_sram_size; | |
64da80a2 LB |
348 | u8 rxq_mask; |
349 | int rxq_primary; | |
8a578111 | 350 | struct napi_struct napi; |
64da80a2 | 351 | struct rx_queue rxq[8]; |
13d64285 LB |
352 | |
353 | /* | |
354 | * TX state. | |
355 | */ | |
356 | int default_tx_ring_size; | |
357 | unsigned long tx_desc_sram_addr; | |
358 | int tx_desc_sram_size; | |
3d6b35bc LB |
359 | u8 txq_mask; |
360 | int txq_primary; | |
361 | struct tx_queue txq[8]; | |
13d64285 LB |
362 | #ifdef MV643XX_ETH_TX_FAST_REFILL |
363 | int tx_clean_threshold; | |
364 | #endif | |
fbd6a754 | 365 | }; |
1da177e4 | 366 | |
fbd6a754 | 367 | |
c9df406f | 368 | /* port register accessors **************************************************/ |
e5371493 | 369 | static inline u32 rdl(struct mv643xx_eth_private *mp, int offset) |
c9df406f | 370 | { |
cc9754b3 | 371 | return readl(mp->shared->base + offset); |
c9df406f | 372 | } |
fbd6a754 | 373 | |
e5371493 | 374 | static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data) |
c9df406f | 375 | { |
cc9754b3 | 376 | writel(data, mp->shared->base + offset); |
c9df406f | 377 | } |
fbd6a754 | 378 | |
fbd6a754 | 379 | |
c9df406f | 380 | /* rxq/txq helper functions *************************************************/ |
8a578111 | 381 | static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq) |
c9df406f | 382 | { |
64da80a2 | 383 | return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]); |
c9df406f | 384 | } |
fbd6a754 | 385 | |
13d64285 LB |
386 | static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq) |
387 | { | |
3d6b35bc | 388 | return container_of(txq, struct mv643xx_eth_private, txq[txq->index]); |
13d64285 LB |
389 | } |
390 | ||
8a578111 | 391 | static void rxq_enable(struct rx_queue *rxq) |
c9df406f | 392 | { |
8a578111 | 393 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
64da80a2 | 394 | wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index); |
8a578111 | 395 | } |
1da177e4 | 396 | |
8a578111 LB |
397 | static void rxq_disable(struct rx_queue *rxq) |
398 | { | |
399 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); | |
64da80a2 | 400 | u8 mask = 1 << rxq->index; |
1da177e4 | 401 | |
8a578111 LB |
402 | wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8); |
403 | while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask) | |
404 | udelay(10); | |
c9df406f LB |
405 | } |
406 | ||
6b368f68 LB |
407 | static void txq_reset_hw_ptr(struct tx_queue *txq) |
408 | { | |
409 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
410 | int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index); | |
411 | u32 addr; | |
412 | ||
413 | addr = (u32)txq->tx_desc_dma; | |
414 | addr += txq->tx_curr_desc * sizeof(struct tx_desc); | |
415 | wrl(mp, off, addr); | |
416 | } | |
417 | ||
13d64285 | 418 | static void txq_enable(struct tx_queue *txq) |
1da177e4 | 419 | { |
13d64285 | 420 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
3d6b35bc | 421 | wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index); |
1da177e4 LT |
422 | } |
423 | ||
13d64285 | 424 | static void txq_disable(struct tx_queue *txq) |
1da177e4 | 425 | { |
13d64285 | 426 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
3d6b35bc | 427 | u8 mask = 1 << txq->index; |
c9df406f | 428 | |
13d64285 LB |
429 | wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8); |
430 | while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask) | |
431 | udelay(10); | |
432 | } | |
433 | ||
434 | static void __txq_maybe_wake(struct tx_queue *txq) | |
435 | { | |
436 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
437 | ||
3d6b35bc LB |
438 | /* |
439 | * netif_{stop,wake}_queue() flow control only applies to | |
440 | * the primary queue. | |
441 | */ | |
442 | BUG_ON(txq->index != mp->txq_primary); | |
443 | ||
13d64285 LB |
444 | if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB) |
445 | netif_wake_queue(mp->dev); | |
1da177e4 LT |
446 | } |
447 | ||
c9df406f LB |
448 | |
449 | /* rx ***********************************************************************/ | |
13d64285 | 450 | static void txq_reclaim(struct tx_queue *txq, int force); |
c9df406f | 451 | |
8a578111 | 452 | static void rxq_refill(struct rx_queue *rxq) |
1da177e4 | 453 | { |
8a578111 | 454 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
c9df406f | 455 | unsigned long flags; |
1da177e4 | 456 | |
c9df406f | 457 | spin_lock_irqsave(&mp->lock, flags); |
c0d0f2ca | 458 | |
8a578111 LB |
459 | while (rxq->rx_desc_count < rxq->rx_ring_size) { |
460 | int skb_size; | |
de34f225 LB |
461 | struct sk_buff *skb; |
462 | int unaligned; | |
463 | int rx; | |
464 | ||
8a578111 LB |
465 | /* |
466 | * Reserve 2+14 bytes for an ethernet header (the | |
467 | * hardware automatically prepends 2 bytes of dummy | |
468 | * data to each received packet), 4 bytes for a VLAN | |
469 | * header, and 4 bytes for the trailing FCS -- 24 | |
470 | * bytes total. | |
471 | */ | |
472 | skb_size = mp->dev->mtu + 24; | |
473 | ||
474 | skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1); | |
de34f225 | 475 | if (skb == NULL) |
1da177e4 | 476 | break; |
de34f225 | 477 | |
908b637f | 478 | unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1); |
b44cd572 | 479 | if (unaligned) |
908b637f | 480 | skb_reserve(skb, dma_get_cache_alignment() - unaligned); |
de34f225 | 481 | |
8a578111 LB |
482 | rxq->rx_desc_count++; |
483 | rx = rxq->rx_used_desc; | |
484 | rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size; | |
de34f225 | 485 | |
8a578111 LB |
486 | rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data, |
487 | skb_size, DMA_FROM_DEVICE); | |
488 | rxq->rx_desc_area[rx].buf_size = skb_size; | |
489 | rxq->rx_skb[rx] = skb; | |
de34f225 | 490 | wmb(); |
8a578111 | 491 | rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA | |
de34f225 LB |
492 | RX_ENABLE_INTERRUPT; |
493 | wmb(); | |
494 | ||
fc32b0e2 LB |
495 | /* |
496 | * The hardware automatically prepends 2 bytes of | |
497 | * dummy data to each received packet, so that the | |
498 | * IP header ends up 16-byte aligned. | |
499 | */ | |
500 | skb_reserve(skb, 2); | |
1da177e4 | 501 | } |
de34f225 | 502 | |
12e4ab79 | 503 | if (rxq->rx_desc_count != rxq->rx_ring_size) { |
8a578111 LB |
504 | rxq->rx_oom.expires = jiffies + (HZ / 10); |
505 | add_timer(&rxq->rx_oom); | |
1da177e4 | 506 | } |
de34f225 LB |
507 | |
508 | spin_unlock_irqrestore(&mp->lock, flags); | |
1da177e4 LT |
509 | } |
510 | ||
8a578111 | 511 | static inline void rxq_refill_timer_wrapper(unsigned long data) |
1da177e4 | 512 | { |
8a578111 | 513 | rxq_refill((struct rx_queue *)data); |
1da177e4 LT |
514 | } |
515 | ||
8a578111 | 516 | static int rxq_process(struct rx_queue *rxq, int budget) |
1da177e4 | 517 | { |
8a578111 LB |
518 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
519 | struct net_device_stats *stats = &mp->dev->stats; | |
520 | int rx; | |
1da177e4 | 521 | |
8a578111 LB |
522 | rx = 0; |
523 | while (rx < budget) { | |
fc32b0e2 | 524 | struct rx_desc *rx_desc; |
96587661 | 525 | unsigned int cmd_sts; |
fc32b0e2 | 526 | struct sk_buff *skb; |
96587661 | 527 | unsigned long flags; |
d344bff9 | 528 | |
96587661 | 529 | spin_lock_irqsave(&mp->lock, flags); |
ff561eef | 530 | |
8a578111 | 531 | rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc]; |
1da177e4 | 532 | |
96587661 LB |
533 | cmd_sts = rx_desc->cmd_sts; |
534 | if (cmd_sts & BUFFER_OWNED_BY_DMA) { | |
535 | spin_unlock_irqrestore(&mp->lock, flags); | |
536 | break; | |
537 | } | |
538 | rmb(); | |
1da177e4 | 539 | |
8a578111 LB |
540 | skb = rxq->rx_skb[rxq->rx_curr_desc]; |
541 | rxq->rx_skb[rxq->rx_curr_desc] = NULL; | |
ff561eef | 542 | |
8a578111 | 543 | rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size; |
ff561eef | 544 | |
96587661 | 545 | spin_unlock_irqrestore(&mp->lock, flags); |
1da177e4 | 546 | |
fc32b0e2 LB |
547 | dma_unmap_single(NULL, rx_desc->buf_ptr + 2, |
548 | mp->dev->mtu + 24, DMA_FROM_DEVICE); | |
8a578111 LB |
549 | rxq->rx_desc_count--; |
550 | rx++; | |
b1dd9ca1 | 551 | |
468d09f8 DF |
552 | /* |
553 | * Update statistics. | |
fc32b0e2 LB |
554 | * |
555 | * Note that the descriptor byte count includes 2 dummy | |
556 | * bytes automatically inserted by the hardware at the | |
557 | * start of the packet (which we don't count), and a 4 | |
558 | * byte CRC at the end of the packet (which we do count). | |
468d09f8 | 559 | */ |
1da177e4 | 560 | stats->rx_packets++; |
fc32b0e2 | 561 | stats->rx_bytes += rx_desc->byte_cnt - 2; |
96587661 | 562 | |
1da177e4 | 563 | /* |
fc32b0e2 LB |
564 | * In case we received a packet without first / last bits |
565 | * on, or the error summary bit is set, the packet needs | |
566 | * to be dropped. | |
1da177e4 | 567 | */ |
96587661 | 568 | if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != |
cc9754b3 | 569 | (RX_FIRST_DESC | RX_LAST_DESC)) |
96587661 | 570 | || (cmd_sts & ERROR_SUMMARY)) { |
1da177e4 | 571 | stats->rx_dropped++; |
fc32b0e2 | 572 | |
96587661 | 573 | if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != |
cc9754b3 | 574 | (RX_FIRST_DESC | RX_LAST_DESC)) { |
1da177e4 | 575 | if (net_ratelimit()) |
fc32b0e2 LB |
576 | dev_printk(KERN_ERR, &mp->dev->dev, |
577 | "received packet spanning " | |
578 | "multiple descriptors\n"); | |
1da177e4 | 579 | } |
fc32b0e2 | 580 | |
96587661 | 581 | if (cmd_sts & ERROR_SUMMARY) |
1da177e4 LT |
582 | stats->rx_errors++; |
583 | ||
584 | dev_kfree_skb_irq(skb); | |
585 | } else { | |
586 | /* | |
587 | * The -4 is for the CRC in the trailer of the | |
588 | * received packet | |
589 | */ | |
fc32b0e2 | 590 | skb_put(skb, rx_desc->byte_cnt - 2 - 4); |
1da177e4 | 591 | |
96587661 | 592 | if (cmd_sts & LAYER_4_CHECKSUM_OK) { |
1da177e4 LT |
593 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
594 | skb->csum = htons( | |
96587661 | 595 | (cmd_sts & 0x0007fff8) >> 3); |
1da177e4 | 596 | } |
8a578111 | 597 | skb->protocol = eth_type_trans(skb, mp->dev); |
e5371493 | 598 | #ifdef MV643XX_ETH_NAPI |
1da177e4 LT |
599 | netif_receive_skb(skb); |
600 | #else | |
601 | netif_rx(skb); | |
602 | #endif | |
603 | } | |
fc32b0e2 | 604 | |
8a578111 | 605 | mp->dev->last_rx = jiffies; |
1da177e4 | 606 | } |
fc32b0e2 | 607 | |
8a578111 | 608 | rxq_refill(rxq); |
1da177e4 | 609 | |
8a578111 | 610 | return rx; |
1da177e4 LT |
611 | } |
612 | ||
e5371493 | 613 | #ifdef MV643XX_ETH_NAPI |
e5371493 | 614 | static int mv643xx_eth_poll(struct napi_struct *napi, int budget) |
d0412d96 | 615 | { |
8a578111 LB |
616 | struct mv643xx_eth_private *mp; |
617 | int rx; | |
64da80a2 | 618 | int i; |
8a578111 LB |
619 | |
620 | mp = container_of(napi, struct mv643xx_eth_private, napi); | |
d0412d96 | 621 | |
e5371493 | 622 | #ifdef MV643XX_ETH_TX_FAST_REFILL |
c9df406f | 623 | if (++mp->tx_clean_threshold > 5) { |
c9df406f | 624 | mp->tx_clean_threshold = 0; |
3d6b35bc LB |
625 | for (i = 0; i < 8; i++) |
626 | if (mp->txq_mask & (1 << i)) | |
627 | txq_reclaim(mp->txq + i, 0); | |
4dfc1c87 LB |
628 | |
629 | if (netif_carrier_ok(mp->dev)) { | |
630 | spin_lock(&mp->lock); | |
631 | __txq_maybe_wake(mp->txq + mp->txq_primary); | |
632 | spin_unlock(&mp->lock); | |
633 | } | |
d0412d96 | 634 | } |
c9df406f | 635 | #endif |
d0412d96 | 636 | |
64da80a2 LB |
637 | rx = 0; |
638 | for (i = 7; rx < budget && i >= 0; i--) | |
639 | if (mp->rxq_mask & (1 << i)) | |
640 | rx += rxq_process(mp->rxq + i, budget - rx); | |
d0412d96 | 641 | |
8a578111 LB |
642 | if (rx < budget) { |
643 | netif_rx_complete(mp->dev, napi); | |
644 | wrl(mp, INT_CAUSE(mp->port_num), 0); | |
645 | wrl(mp, INT_CAUSE_EXT(mp->port_num), 0); | |
226bb6b7 | 646 | wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT); |
d0412d96 | 647 | } |
c9df406f | 648 | |
8a578111 | 649 | return rx; |
d0412d96 | 650 | } |
c9df406f | 651 | #endif |
d0412d96 | 652 | |
c9df406f LB |
653 | |
654 | /* tx ***********************************************************************/ | |
c9df406f | 655 | static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) |
1da177e4 | 656 | { |
13d64285 | 657 | int frag; |
1da177e4 | 658 | |
c9df406f | 659 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { |
13d64285 LB |
660 | skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag]; |
661 | if (fragp->size <= 8 && fragp->page_offset & 7) | |
c9df406f | 662 | return 1; |
1da177e4 | 663 | } |
13d64285 | 664 | |
c9df406f LB |
665 | return 0; |
666 | } | |
7303fde8 | 667 | |
13d64285 | 668 | static int txq_alloc_desc_index(struct tx_queue *txq) |
c9df406f LB |
669 | { |
670 | int tx_desc_curr; | |
d0412d96 | 671 | |
13d64285 | 672 | BUG_ON(txq->tx_desc_count >= txq->tx_ring_size); |
1da177e4 | 673 | |
13d64285 LB |
674 | tx_desc_curr = txq->tx_curr_desc; |
675 | txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size; | |
e4d00fa9 | 676 | |
13d64285 | 677 | BUG_ON(txq->tx_curr_desc == txq->tx_used_desc); |
468d09f8 | 678 | |
c9df406f LB |
679 | return tx_desc_curr; |
680 | } | |
468d09f8 | 681 | |
13d64285 | 682 | static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb) |
c9df406f | 683 | { |
13d64285 | 684 | int nr_frags = skb_shinfo(skb)->nr_frags; |
c9df406f | 685 | int frag; |
1da177e4 | 686 | |
13d64285 LB |
687 | for (frag = 0; frag < nr_frags; frag++) { |
688 | skb_frag_t *this_frag; | |
689 | int tx_index; | |
690 | struct tx_desc *desc; | |
691 | ||
692 | this_frag = &skb_shinfo(skb)->frags[frag]; | |
693 | tx_index = txq_alloc_desc_index(txq); | |
694 | desc = &txq->tx_desc_area[tx_index]; | |
695 | ||
696 | /* | |
697 | * The last fragment will generate an interrupt | |
698 | * which will free the skb on TX completion. | |
699 | */ | |
700 | if (frag == nr_frags - 1) { | |
701 | desc->cmd_sts = BUFFER_OWNED_BY_DMA | | |
702 | ZERO_PADDING | TX_LAST_DESC | | |
703 | TX_ENABLE_INTERRUPT; | |
704 | txq->tx_skb[tx_index] = skb; | |
705 | } else { | |
706 | desc->cmd_sts = BUFFER_OWNED_BY_DMA; | |
707 | txq->tx_skb[tx_index] = NULL; | |
708 | } | |
709 | ||
c9df406f LB |
710 | desc->l4i_chk = 0; |
711 | desc->byte_cnt = this_frag->size; | |
712 | desc->buf_ptr = dma_map_page(NULL, this_frag->page, | |
713 | this_frag->page_offset, | |
714 | this_frag->size, | |
715 | DMA_TO_DEVICE); | |
716 | } | |
1da177e4 LT |
717 | } |
718 | ||
c9df406f LB |
719 | static inline __be16 sum16_as_be(__sum16 sum) |
720 | { | |
721 | return (__force __be16)sum; | |
722 | } | |
1da177e4 | 723 | |
13d64285 | 724 | static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb) |
1da177e4 | 725 | { |
8fa89bf5 | 726 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
13d64285 | 727 | int nr_frags = skb_shinfo(skb)->nr_frags; |
c9df406f | 728 | int tx_index; |
cc9754b3 | 729 | struct tx_desc *desc; |
c9df406f LB |
730 | u32 cmd_sts; |
731 | int length; | |
1da177e4 | 732 | |
cc9754b3 | 733 | cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA; |
1da177e4 | 734 | |
13d64285 LB |
735 | tx_index = txq_alloc_desc_index(txq); |
736 | desc = &txq->tx_desc_area[tx_index]; | |
c9df406f LB |
737 | |
738 | if (nr_frags) { | |
13d64285 | 739 | txq_submit_frag_skb(txq, skb); |
c9df406f LB |
740 | |
741 | length = skb_headlen(skb); | |
13d64285 | 742 | txq->tx_skb[tx_index] = NULL; |
c9df406f | 743 | } else { |
cc9754b3 | 744 | cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT; |
c9df406f | 745 | length = skb->len; |
13d64285 | 746 | txq->tx_skb[tx_index] = skb; |
c9df406f LB |
747 | } |
748 | ||
749 | desc->byte_cnt = length; | |
750 | desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE); | |
751 | ||
752 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
753 | BUG_ON(skb->protocol != htons(ETH_P_IP)); | |
754 | ||
cc9754b3 LB |
755 | cmd_sts |= GEN_TCP_UDP_CHECKSUM | |
756 | GEN_IP_V4_CHECKSUM | | |
757 | ip_hdr(skb)->ihl << TX_IHL_SHIFT; | |
c9df406f LB |
758 | |
759 | switch (ip_hdr(skb)->protocol) { | |
760 | case IPPROTO_UDP: | |
cc9754b3 | 761 | cmd_sts |= UDP_FRAME; |
c9df406f LB |
762 | desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check)); |
763 | break; | |
764 | case IPPROTO_TCP: | |
765 | desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check)); | |
766 | break; | |
767 | default: | |
768 | BUG(); | |
769 | } | |
770 | } else { | |
771 | /* Errata BTS #50, IHL must be 5 if no HW checksum */ | |
cc9754b3 | 772 | cmd_sts |= 5 << TX_IHL_SHIFT; |
c9df406f LB |
773 | desc->l4i_chk = 0; |
774 | } | |
775 | ||
776 | /* ensure all other descriptors are written before first cmd_sts */ | |
777 | wmb(); | |
778 | desc->cmd_sts = cmd_sts; | |
779 | ||
8fa89bf5 LB |
780 | /* clear TX_END interrupt status */ |
781 | wrl(mp, INT_CAUSE(mp->port_num), ~(INT_TX_END_0 << txq->index)); | |
782 | rdl(mp, INT_CAUSE(mp->port_num)); | |
783 | ||
c9df406f LB |
784 | /* ensure all descriptors are written before poking hardware */ |
785 | wmb(); | |
13d64285 | 786 | txq_enable(txq); |
c9df406f | 787 | |
13d64285 | 788 | txq->tx_desc_count += nr_frags + 1; |
1da177e4 | 789 | } |
1da177e4 | 790 | |
fc32b0e2 | 791 | static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 792 | { |
e5371493 | 793 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f | 794 | struct net_device_stats *stats = &dev->stats; |
13d64285 | 795 | struct tx_queue *txq; |
c9df406f | 796 | unsigned long flags; |
afdb57a2 | 797 | |
c9df406f LB |
798 | if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) { |
799 | stats->tx_dropped++; | |
fc32b0e2 LB |
800 | dev_printk(KERN_DEBUG, &dev->dev, |
801 | "failed to linearize skb with tiny " | |
802 | "unaligned fragment\n"); | |
c9df406f LB |
803 | return NETDEV_TX_BUSY; |
804 | } | |
805 | ||
806 | spin_lock_irqsave(&mp->lock, flags); | |
807 | ||
3d6b35bc | 808 | txq = mp->txq + mp->txq_primary; |
13d64285 LB |
809 | |
810 | if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) { | |
c9df406f | 811 | spin_unlock_irqrestore(&mp->lock, flags); |
3d6b35bc LB |
812 | if (txq->index == mp->txq_primary && net_ratelimit()) |
813 | dev_printk(KERN_ERR, &dev->dev, | |
814 | "primary tx queue full?!\n"); | |
815 | kfree_skb(skb); | |
816 | return NETDEV_TX_OK; | |
c9df406f LB |
817 | } |
818 | ||
13d64285 | 819 | txq_submit_skb(txq, skb); |
c9df406f LB |
820 | stats->tx_bytes += skb->len; |
821 | stats->tx_packets++; | |
822 | dev->trans_start = jiffies; | |
823 | ||
3d6b35bc LB |
824 | if (txq->index == mp->txq_primary) { |
825 | int entries_left; | |
826 | ||
827 | entries_left = txq->tx_ring_size - txq->tx_desc_count; | |
828 | if (entries_left < MAX_DESCS_PER_SKB) | |
829 | netif_stop_queue(dev); | |
830 | } | |
c9df406f LB |
831 | |
832 | spin_unlock_irqrestore(&mp->lock, flags); | |
833 | ||
834 | return NETDEV_TX_OK; | |
1da177e4 LT |
835 | } |
836 | ||
c9df406f | 837 | |
89df5fdc LB |
838 | /* tx rate control **********************************************************/ |
839 | /* | |
840 | * Set total maximum TX rate (shared by all TX queues for this port) | |
841 | * to 'rate' bits per second, with a maximum burst of 'burst' bytes. | |
842 | */ | |
843 | static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst) | |
844 | { | |
845 | int token_rate; | |
846 | int mtu; | |
847 | int bucket_size; | |
848 | ||
849 | token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000); | |
850 | if (token_rate > 1023) | |
851 | token_rate = 1023; | |
852 | ||
853 | mtu = (mp->dev->mtu + 255) >> 8; | |
854 | if (mtu > 63) | |
855 | mtu = 63; | |
856 | ||
857 | bucket_size = (burst + 255) >> 8; | |
858 | if (bucket_size > 65535) | |
859 | bucket_size = 65535; | |
860 | ||
1e881592 LB |
861 | if (mp->shared->tx_bw_control_moved) { |
862 | wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate); | |
863 | wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu); | |
864 | wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size); | |
865 | } else { | |
866 | wrl(mp, TX_BW_RATE(mp->port_num), token_rate); | |
867 | wrl(mp, TX_BW_MTU(mp->port_num), mtu); | |
868 | wrl(mp, TX_BW_BURST(mp->port_num), bucket_size); | |
869 | } | |
89df5fdc LB |
870 | } |
871 | ||
872 | static void txq_set_rate(struct tx_queue *txq, int rate, int burst) | |
873 | { | |
874 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
875 | int token_rate; | |
876 | int bucket_size; | |
877 | ||
878 | token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000); | |
879 | if (token_rate > 1023) | |
880 | token_rate = 1023; | |
881 | ||
882 | bucket_size = (burst + 255) >> 8; | |
883 | if (bucket_size > 65535) | |
884 | bucket_size = 65535; | |
885 | ||
3d6b35bc LB |
886 | wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14); |
887 | wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index), | |
89df5fdc LB |
888 | (bucket_size << 10) | token_rate); |
889 | } | |
890 | ||
891 | static void txq_set_fixed_prio_mode(struct tx_queue *txq) | |
892 | { | |
893 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
894 | int off; | |
895 | u32 val; | |
896 | ||
897 | /* | |
898 | * Turn on fixed priority mode. | |
899 | */ | |
1e881592 LB |
900 | if (mp->shared->tx_bw_control_moved) |
901 | off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num); | |
902 | else | |
903 | off = TXQ_FIX_PRIO_CONF(mp->port_num); | |
89df5fdc LB |
904 | |
905 | val = rdl(mp, off); | |
3d6b35bc | 906 | val |= 1 << txq->index; |
89df5fdc LB |
907 | wrl(mp, off, val); |
908 | } | |
909 | ||
910 | static void txq_set_wrr(struct tx_queue *txq, int weight) | |
911 | { | |
912 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
913 | int off; | |
914 | u32 val; | |
915 | ||
916 | /* | |
917 | * Turn off fixed priority mode. | |
918 | */ | |
1e881592 LB |
919 | if (mp->shared->tx_bw_control_moved) |
920 | off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num); | |
921 | else | |
922 | off = TXQ_FIX_PRIO_CONF(mp->port_num); | |
89df5fdc LB |
923 | |
924 | val = rdl(mp, off); | |
3d6b35bc | 925 | val &= ~(1 << txq->index); |
89df5fdc LB |
926 | wrl(mp, off, val); |
927 | ||
928 | /* | |
929 | * Configure WRR weight for this queue. | |
930 | */ | |
3d6b35bc | 931 | off = TXQ_BW_WRR_CONF(mp->port_num, txq->index); |
89df5fdc LB |
932 | |
933 | val = rdl(mp, off); | |
934 | val = (val & ~0xff) | (weight & 0xff); | |
935 | wrl(mp, off, val); | |
936 | } | |
937 | ||
938 | ||
c9df406f | 939 | /* mii management interface *************************************************/ |
fc32b0e2 LB |
940 | #define SMI_BUSY 0x10000000 |
941 | #define SMI_READ_VALID 0x08000000 | |
942 | #define SMI_OPCODE_READ 0x04000000 | |
943 | #define SMI_OPCODE_WRITE 0x00000000 | |
c9df406f | 944 | |
fc32b0e2 LB |
945 | static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr, |
946 | unsigned int reg, unsigned int *value) | |
1da177e4 | 947 | { |
cc9754b3 | 948 | void __iomem *smi_reg = mp->shared_smi->base + SMI_REG; |
c9df406f | 949 | unsigned long flags; |
1da177e4 LT |
950 | int i; |
951 | ||
c9df406f LB |
952 | /* the SMI register is a shared resource */ |
953 | spin_lock_irqsave(&mp->shared_smi->phy_lock, flags); | |
954 | ||
955 | /* wait for the SMI register to become available */ | |
cc9754b3 | 956 | for (i = 0; readl(smi_reg) & SMI_BUSY; i++) { |
e1bea50a | 957 | if (i == 1000) { |
c9df406f LB |
958 | printk("%s: PHY busy timeout\n", mp->dev->name); |
959 | goto out; | |
960 | } | |
e1bea50a | 961 | udelay(10); |
1da177e4 LT |
962 | } |
963 | ||
fc32b0e2 | 964 | writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg); |
1da177e4 | 965 | |
c9df406f | 966 | /* now wait for the data to be valid */ |
cc9754b3 | 967 | for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) { |
e1bea50a | 968 | if (i == 1000) { |
c9df406f LB |
969 | printk("%s: PHY read timeout\n", mp->dev->name); |
970 | goto out; | |
971 | } | |
e1bea50a | 972 | udelay(10); |
c9df406f LB |
973 | } |
974 | ||
975 | *value = readl(smi_reg) & 0xffff; | |
976 | out: | |
977 | spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags); | |
1da177e4 LT |
978 | } |
979 | ||
fc32b0e2 LB |
980 | static void smi_reg_write(struct mv643xx_eth_private *mp, |
981 | unsigned int addr, | |
982 | unsigned int reg, unsigned int value) | |
1da177e4 | 983 | { |
cc9754b3 | 984 | void __iomem *smi_reg = mp->shared_smi->base + SMI_REG; |
c9df406f | 985 | unsigned long flags; |
1da177e4 LT |
986 | int i; |
987 | ||
c9df406f LB |
988 | /* the SMI register is a shared resource */ |
989 | spin_lock_irqsave(&mp->shared_smi->phy_lock, flags); | |
990 | ||
991 | /* wait for the SMI register to become available */ | |
cc9754b3 | 992 | for (i = 0; readl(smi_reg) & SMI_BUSY; i++) { |
e1bea50a | 993 | if (i == 1000) { |
c9df406f LB |
994 | printk("%s: PHY busy timeout\n", mp->dev->name); |
995 | goto out; | |
996 | } | |
e1bea50a | 997 | udelay(10); |
1da177e4 LT |
998 | } |
999 | ||
fc32b0e2 LB |
1000 | writel(SMI_OPCODE_WRITE | (reg << 21) | |
1001 | (addr << 16) | (value & 0xffff), smi_reg); | |
c9df406f LB |
1002 | out: |
1003 | spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags); | |
1004 | } | |
1da177e4 | 1005 | |
c9df406f LB |
1006 | |
1007 | /* mib counters *************************************************************/ | |
fc32b0e2 | 1008 | static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset) |
c9df406f | 1009 | { |
fc32b0e2 | 1010 | return rdl(mp, MIB_COUNTERS(mp->port_num) + offset); |
1da177e4 LT |
1011 | } |
1012 | ||
fc32b0e2 | 1013 | static void mib_counters_clear(struct mv643xx_eth_private *mp) |
d0412d96 | 1014 | { |
fc32b0e2 LB |
1015 | int i; |
1016 | ||
1017 | for (i = 0; i < 0x80; i += 4) | |
1018 | mib_read(mp, i); | |
c9df406f | 1019 | } |
d0412d96 | 1020 | |
fc32b0e2 | 1021 | static void mib_counters_update(struct mv643xx_eth_private *mp) |
c9df406f | 1022 | { |
e5371493 | 1023 | struct mib_counters *p = &mp->mib_counters; |
4b8e3655 | 1024 | |
fc32b0e2 LB |
1025 | p->good_octets_received += mib_read(mp, 0x00); |
1026 | p->good_octets_received += (u64)mib_read(mp, 0x04) << 32; | |
1027 | p->bad_octets_received += mib_read(mp, 0x08); | |
1028 | p->internal_mac_transmit_err += mib_read(mp, 0x0c); | |
1029 | p->good_frames_received += mib_read(mp, 0x10); | |
1030 | p->bad_frames_received += mib_read(mp, 0x14); | |
1031 | p->broadcast_frames_received += mib_read(mp, 0x18); | |
1032 | p->multicast_frames_received += mib_read(mp, 0x1c); | |
1033 | p->frames_64_octets += mib_read(mp, 0x20); | |
1034 | p->frames_65_to_127_octets += mib_read(mp, 0x24); | |
1035 | p->frames_128_to_255_octets += mib_read(mp, 0x28); | |
1036 | p->frames_256_to_511_octets += mib_read(mp, 0x2c); | |
1037 | p->frames_512_to_1023_octets += mib_read(mp, 0x30); | |
1038 | p->frames_1024_to_max_octets += mib_read(mp, 0x34); | |
1039 | p->good_octets_sent += mib_read(mp, 0x38); | |
1040 | p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32; | |
1041 | p->good_frames_sent += mib_read(mp, 0x40); | |
1042 | p->excessive_collision += mib_read(mp, 0x44); | |
1043 | p->multicast_frames_sent += mib_read(mp, 0x48); | |
1044 | p->broadcast_frames_sent += mib_read(mp, 0x4c); | |
1045 | p->unrec_mac_control_received += mib_read(mp, 0x50); | |
1046 | p->fc_sent += mib_read(mp, 0x54); | |
1047 | p->good_fc_received += mib_read(mp, 0x58); | |
1048 | p->bad_fc_received += mib_read(mp, 0x5c); | |
1049 | p->undersize_received += mib_read(mp, 0x60); | |
1050 | p->fragments_received += mib_read(mp, 0x64); | |
1051 | p->oversize_received += mib_read(mp, 0x68); | |
1052 | p->jabber_received += mib_read(mp, 0x6c); | |
1053 | p->mac_receive_error += mib_read(mp, 0x70); | |
1054 | p->bad_crc_event += mib_read(mp, 0x74); | |
1055 | p->collision += mib_read(mp, 0x78); | |
1056 | p->late_collision += mib_read(mp, 0x7c); | |
d0412d96 JC |
1057 | } |
1058 | ||
c9df406f LB |
1059 | |
1060 | /* ethtool ******************************************************************/ | |
e5371493 | 1061 | struct mv643xx_eth_stats { |
c9df406f LB |
1062 | char stat_string[ETH_GSTRING_LEN]; |
1063 | int sizeof_stat; | |
16820054 LB |
1064 | int netdev_off; |
1065 | int mp_off; | |
c9df406f LB |
1066 | }; |
1067 | ||
16820054 LB |
1068 | #define SSTAT(m) \ |
1069 | { #m, FIELD_SIZEOF(struct net_device_stats, m), \ | |
1070 | offsetof(struct net_device, stats.m), -1 } | |
1071 | ||
1072 | #define MIBSTAT(m) \ | |
1073 | { #m, FIELD_SIZEOF(struct mib_counters, m), \ | |
1074 | -1, offsetof(struct mv643xx_eth_private, mib_counters.m) } | |
1075 | ||
1076 | static const struct mv643xx_eth_stats mv643xx_eth_stats[] = { | |
1077 | SSTAT(rx_packets), | |
1078 | SSTAT(tx_packets), | |
1079 | SSTAT(rx_bytes), | |
1080 | SSTAT(tx_bytes), | |
1081 | SSTAT(rx_errors), | |
1082 | SSTAT(tx_errors), | |
1083 | SSTAT(rx_dropped), | |
1084 | SSTAT(tx_dropped), | |
1085 | MIBSTAT(good_octets_received), | |
1086 | MIBSTAT(bad_octets_received), | |
1087 | MIBSTAT(internal_mac_transmit_err), | |
1088 | MIBSTAT(good_frames_received), | |
1089 | MIBSTAT(bad_frames_received), | |
1090 | MIBSTAT(broadcast_frames_received), | |
1091 | MIBSTAT(multicast_frames_received), | |
1092 | MIBSTAT(frames_64_octets), | |
1093 | MIBSTAT(frames_65_to_127_octets), | |
1094 | MIBSTAT(frames_128_to_255_octets), | |
1095 | MIBSTAT(frames_256_to_511_octets), | |
1096 | MIBSTAT(frames_512_to_1023_octets), | |
1097 | MIBSTAT(frames_1024_to_max_octets), | |
1098 | MIBSTAT(good_octets_sent), | |
1099 | MIBSTAT(good_frames_sent), | |
1100 | MIBSTAT(excessive_collision), | |
1101 | MIBSTAT(multicast_frames_sent), | |
1102 | MIBSTAT(broadcast_frames_sent), | |
1103 | MIBSTAT(unrec_mac_control_received), | |
1104 | MIBSTAT(fc_sent), | |
1105 | MIBSTAT(good_fc_received), | |
1106 | MIBSTAT(bad_fc_received), | |
1107 | MIBSTAT(undersize_received), | |
1108 | MIBSTAT(fragments_received), | |
1109 | MIBSTAT(oversize_received), | |
1110 | MIBSTAT(jabber_received), | |
1111 | MIBSTAT(mac_receive_error), | |
1112 | MIBSTAT(bad_crc_event), | |
1113 | MIBSTAT(collision), | |
1114 | MIBSTAT(late_collision), | |
c9df406f LB |
1115 | }; |
1116 | ||
e5371493 | 1117 | static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
d0412d96 | 1118 | { |
e5371493 | 1119 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
d0412d96 JC |
1120 | int err; |
1121 | ||
1122 | spin_lock_irq(&mp->lock); | |
1123 | err = mii_ethtool_gset(&mp->mii, cmd); | |
1124 | spin_unlock_irq(&mp->lock); | |
1125 | ||
fc32b0e2 LB |
1126 | /* |
1127 | * The MAC does not support 1000baseT_Half. | |
1128 | */ | |
d0412d96 JC |
1129 | cmd->supported &= ~SUPPORTED_1000baseT_Half; |
1130 | cmd->advertising &= ~ADVERTISED_1000baseT_Half; | |
1131 | ||
1132 | return err; | |
1133 | } | |
1134 | ||
bedfe324 LB |
1135 | static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd) |
1136 | { | |
1137 | cmd->supported = SUPPORTED_MII; | |
1138 | cmd->advertising = ADVERTISED_MII; | |
1139 | cmd->speed = SPEED_1000; | |
1140 | cmd->duplex = DUPLEX_FULL; | |
1141 | cmd->port = PORT_MII; | |
1142 | cmd->phy_address = 0; | |
1143 | cmd->transceiver = XCVR_INTERNAL; | |
1144 | cmd->autoneg = AUTONEG_DISABLE; | |
1145 | cmd->maxtxpkt = 1; | |
1146 | cmd->maxrxpkt = 1; | |
1147 | ||
1148 | return 0; | |
1149 | } | |
1150 | ||
e5371493 | 1151 | static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 | 1152 | { |
e5371493 | 1153 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
ab4384a6 DF |
1154 | int err; |
1155 | ||
fc32b0e2 LB |
1156 | /* |
1157 | * The MAC does not support 1000baseT_Half. | |
1158 | */ | |
1159 | cmd->advertising &= ~ADVERTISED_1000baseT_Half; | |
1160 | ||
c9df406f LB |
1161 | spin_lock_irq(&mp->lock); |
1162 | err = mii_ethtool_sset(&mp->mii, cmd); | |
1163 | spin_unlock_irq(&mp->lock); | |
85cf572c | 1164 | |
c9df406f LB |
1165 | return err; |
1166 | } | |
1da177e4 | 1167 | |
bedfe324 LB |
1168 | static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd) |
1169 | { | |
1170 | return -EINVAL; | |
1171 | } | |
1172 | ||
fc32b0e2 LB |
1173 | static void mv643xx_eth_get_drvinfo(struct net_device *dev, |
1174 | struct ethtool_drvinfo *drvinfo) | |
c9df406f | 1175 | { |
e5371493 LB |
1176 | strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32); |
1177 | strncpy(drvinfo->version, mv643xx_eth_driver_version, 32); | |
c9df406f | 1178 | strncpy(drvinfo->fw_version, "N/A", 32); |
fc32b0e2 | 1179 | strncpy(drvinfo->bus_info, "platform", 32); |
16820054 | 1180 | drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats); |
c9df406f | 1181 | } |
1da177e4 | 1182 | |
fc32b0e2 | 1183 | static int mv643xx_eth_nway_reset(struct net_device *dev) |
c9df406f | 1184 | { |
e5371493 | 1185 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 1186 | |
c9df406f LB |
1187 | return mii_nway_restart(&mp->mii); |
1188 | } | |
1da177e4 | 1189 | |
bedfe324 LB |
1190 | static int mv643xx_eth_nway_reset_phyless(struct net_device *dev) |
1191 | { | |
1192 | return -EINVAL; | |
1193 | } | |
1194 | ||
c9df406f LB |
1195 | static u32 mv643xx_eth_get_link(struct net_device *dev) |
1196 | { | |
e5371493 | 1197 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 1198 | |
c9df406f LB |
1199 | return mii_link_ok(&mp->mii); |
1200 | } | |
1da177e4 | 1201 | |
bedfe324 LB |
1202 | static u32 mv643xx_eth_get_link_phyless(struct net_device *dev) |
1203 | { | |
1204 | return 1; | |
1205 | } | |
1206 | ||
fc32b0e2 LB |
1207 | static void mv643xx_eth_get_strings(struct net_device *dev, |
1208 | uint32_t stringset, uint8_t *data) | |
c9df406f LB |
1209 | { |
1210 | int i; | |
1da177e4 | 1211 | |
fc32b0e2 LB |
1212 | if (stringset == ETH_SS_STATS) { |
1213 | for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { | |
c9df406f | 1214 | memcpy(data + i * ETH_GSTRING_LEN, |
16820054 | 1215 | mv643xx_eth_stats[i].stat_string, |
e5371493 | 1216 | ETH_GSTRING_LEN); |
c9df406f | 1217 | } |
c9df406f LB |
1218 | } |
1219 | } | |
1da177e4 | 1220 | |
fc32b0e2 LB |
1221 | static void mv643xx_eth_get_ethtool_stats(struct net_device *dev, |
1222 | struct ethtool_stats *stats, | |
1223 | uint64_t *data) | |
c9df406f | 1224 | { |
fc32b0e2 | 1225 | struct mv643xx_eth_private *mp = dev->priv; |
c9df406f | 1226 | int i; |
1da177e4 | 1227 | |
fc32b0e2 | 1228 | mib_counters_update(mp); |
1da177e4 | 1229 | |
16820054 LB |
1230 | for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { |
1231 | const struct mv643xx_eth_stats *stat; | |
1232 | void *p; | |
1233 | ||
1234 | stat = mv643xx_eth_stats + i; | |
1235 | ||
1236 | if (stat->netdev_off >= 0) | |
1237 | p = ((void *)mp->dev) + stat->netdev_off; | |
1238 | else | |
1239 | p = ((void *)mp) + stat->mp_off; | |
1240 | ||
1241 | data[i] = (stat->sizeof_stat == 8) ? | |
1242 | *(uint64_t *)p : *(uint32_t *)p; | |
1da177e4 | 1243 | } |
c9df406f | 1244 | } |
1da177e4 | 1245 | |
fc32b0e2 | 1246 | static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset) |
c9df406f | 1247 | { |
fc32b0e2 | 1248 | if (sset == ETH_SS_STATS) |
16820054 | 1249 | return ARRAY_SIZE(mv643xx_eth_stats); |
fc32b0e2 LB |
1250 | |
1251 | return -EOPNOTSUPP; | |
c9df406f | 1252 | } |
1da177e4 | 1253 | |
e5371493 | 1254 | static const struct ethtool_ops mv643xx_eth_ethtool_ops = { |
fc32b0e2 LB |
1255 | .get_settings = mv643xx_eth_get_settings, |
1256 | .set_settings = mv643xx_eth_set_settings, | |
1257 | .get_drvinfo = mv643xx_eth_get_drvinfo, | |
1258 | .nway_reset = mv643xx_eth_nway_reset, | |
1259 | .get_link = mv643xx_eth_get_link, | |
c9df406f | 1260 | .set_sg = ethtool_op_set_sg, |
fc32b0e2 LB |
1261 | .get_strings = mv643xx_eth_get_strings, |
1262 | .get_ethtool_stats = mv643xx_eth_get_ethtool_stats, | |
e5371493 | 1263 | .get_sset_count = mv643xx_eth_get_sset_count, |
c9df406f | 1264 | }; |
1da177e4 | 1265 | |
bedfe324 LB |
1266 | static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = { |
1267 | .get_settings = mv643xx_eth_get_settings_phyless, | |
1268 | .set_settings = mv643xx_eth_set_settings_phyless, | |
1269 | .get_drvinfo = mv643xx_eth_get_drvinfo, | |
1270 | .nway_reset = mv643xx_eth_nway_reset_phyless, | |
1271 | .get_link = mv643xx_eth_get_link_phyless, | |
1272 | .set_sg = ethtool_op_set_sg, | |
1273 | .get_strings = mv643xx_eth_get_strings, | |
1274 | .get_ethtool_stats = mv643xx_eth_get_ethtool_stats, | |
1275 | .get_sset_count = mv643xx_eth_get_sset_count, | |
1276 | }; | |
1277 | ||
bea3348e | 1278 | |
c9df406f | 1279 | /* address handling *********************************************************/ |
5daffe94 | 1280 | static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr) |
c9df406f | 1281 | { |
c9df406f LB |
1282 | unsigned int mac_h; |
1283 | unsigned int mac_l; | |
1da177e4 | 1284 | |
fc32b0e2 LB |
1285 | mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num)); |
1286 | mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num)); | |
1da177e4 | 1287 | |
5daffe94 LB |
1288 | addr[0] = (mac_h >> 24) & 0xff; |
1289 | addr[1] = (mac_h >> 16) & 0xff; | |
1290 | addr[2] = (mac_h >> 8) & 0xff; | |
1291 | addr[3] = mac_h & 0xff; | |
1292 | addr[4] = (mac_l >> 8) & 0xff; | |
1293 | addr[5] = mac_l & 0xff; | |
c9df406f | 1294 | } |
1da177e4 | 1295 | |
e5371493 | 1296 | static void init_mac_tables(struct mv643xx_eth_private *mp) |
c9df406f | 1297 | { |
fc32b0e2 | 1298 | int i; |
1da177e4 | 1299 | |
fc32b0e2 LB |
1300 | for (i = 0; i < 0x100; i += 4) { |
1301 | wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0); | |
1302 | wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0); | |
c9df406f | 1303 | } |
fc32b0e2 LB |
1304 | |
1305 | for (i = 0; i < 0x10; i += 4) | |
1306 | wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0); | |
c9df406f | 1307 | } |
d0412d96 | 1308 | |
e5371493 | 1309 | static void set_filter_table_entry(struct mv643xx_eth_private *mp, |
fc32b0e2 | 1310 | int table, unsigned char entry) |
c9df406f LB |
1311 | { |
1312 | unsigned int table_reg; | |
ab4384a6 | 1313 | |
c9df406f | 1314 | /* Set "accepts frame bit" at specified table entry */ |
fc32b0e2 LB |
1315 | table_reg = rdl(mp, table + (entry & 0xfc)); |
1316 | table_reg |= 0x01 << (8 * (entry & 3)); | |
1317 | wrl(mp, table + (entry & 0xfc), table_reg); | |
1da177e4 LT |
1318 | } |
1319 | ||
5daffe94 | 1320 | static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr) |
1da177e4 | 1321 | { |
c9df406f LB |
1322 | unsigned int mac_h; |
1323 | unsigned int mac_l; | |
1324 | int table; | |
1da177e4 | 1325 | |
fc32b0e2 LB |
1326 | mac_l = (addr[4] << 8) | addr[5]; |
1327 | mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; | |
ff561eef | 1328 | |
fc32b0e2 LB |
1329 | wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l); |
1330 | wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h); | |
1da177e4 | 1331 | |
fc32b0e2 | 1332 | table = UNICAST_TABLE(mp->port_num); |
5daffe94 | 1333 | set_filter_table_entry(mp, table, addr[5] & 0x0f); |
1da177e4 LT |
1334 | } |
1335 | ||
fc32b0e2 | 1336 | static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr) |
1da177e4 | 1337 | { |
e5371493 | 1338 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 1339 | |
fc32b0e2 LB |
1340 | /* +2 is for the offset of the HW addr type */ |
1341 | memcpy(dev->dev_addr, addr + 2, 6); | |
1342 | ||
cc9754b3 LB |
1343 | init_mac_tables(mp); |
1344 | uc_addr_set(mp, dev->dev_addr); | |
1da177e4 LT |
1345 | |
1346 | return 0; | |
1347 | } | |
1348 | ||
69876569 LB |
1349 | static int addr_crc(unsigned char *addr) |
1350 | { | |
1351 | int crc = 0; | |
1352 | int i; | |
1353 | ||
1354 | for (i = 0; i < 6; i++) { | |
1355 | int j; | |
1356 | ||
1357 | crc = (crc ^ addr[i]) << 8; | |
1358 | for (j = 7; j >= 0; j--) { | |
1359 | if (crc & (0x100 << j)) | |
1360 | crc ^= 0x107 << j; | |
1361 | } | |
1362 | } | |
1363 | ||
1364 | return crc; | |
1365 | } | |
1366 | ||
fc32b0e2 | 1367 | static void mv643xx_eth_set_rx_mode(struct net_device *dev) |
1da177e4 | 1368 | { |
fc32b0e2 LB |
1369 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1370 | u32 port_config; | |
1371 | struct dev_addr_list *addr; | |
1372 | int i; | |
c8aaea25 | 1373 | |
fc32b0e2 LB |
1374 | port_config = rdl(mp, PORT_CONFIG(mp->port_num)); |
1375 | if (dev->flags & IFF_PROMISC) | |
1376 | port_config |= UNICAST_PROMISCUOUS_MODE; | |
1377 | else | |
1378 | port_config &= ~UNICAST_PROMISCUOUS_MODE; | |
1379 | wrl(mp, PORT_CONFIG(mp->port_num), port_config); | |
1da177e4 | 1380 | |
fc32b0e2 LB |
1381 | if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) { |
1382 | int port_num = mp->port_num; | |
1383 | u32 accept = 0x01010101; | |
c8aaea25 | 1384 | |
fc32b0e2 LB |
1385 | for (i = 0; i < 0x100; i += 4) { |
1386 | wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept); | |
1387 | wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept); | |
c9df406f LB |
1388 | } |
1389 | return; | |
1390 | } | |
c8aaea25 | 1391 | |
fc32b0e2 LB |
1392 | for (i = 0; i < 0x100; i += 4) { |
1393 | wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0); | |
1394 | wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0); | |
1da177e4 LT |
1395 | } |
1396 | ||
fc32b0e2 LB |
1397 | for (addr = dev->mc_list; addr != NULL; addr = addr->next) { |
1398 | u8 *a = addr->da_addr; | |
1399 | int table; | |
324ff2c1 | 1400 | |
fc32b0e2 LB |
1401 | if (addr->da_addrlen != 6) |
1402 | continue; | |
1da177e4 | 1403 | |
fc32b0e2 LB |
1404 | if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) { |
1405 | table = SPECIAL_MCAST_TABLE(mp->port_num); | |
1406 | set_filter_table_entry(mp, table, a[5]); | |
1407 | } else { | |
1408 | int crc = addr_crc(a); | |
1da177e4 | 1409 | |
fc32b0e2 LB |
1410 | table = OTHER_MCAST_TABLE(mp->port_num); |
1411 | set_filter_table_entry(mp, table, crc); | |
1412 | } | |
1413 | } | |
c9df406f | 1414 | } |
c8aaea25 | 1415 | |
c8aaea25 | 1416 | |
c9df406f | 1417 | /* rx/tx queue initialisation ***********************************************/ |
64da80a2 | 1418 | static int rxq_init(struct mv643xx_eth_private *mp, int index) |
c9df406f | 1419 | { |
64da80a2 | 1420 | struct rx_queue *rxq = mp->rxq + index; |
8a578111 LB |
1421 | struct rx_desc *rx_desc; |
1422 | int size; | |
c9df406f LB |
1423 | int i; |
1424 | ||
64da80a2 LB |
1425 | rxq->index = index; |
1426 | ||
8a578111 LB |
1427 | rxq->rx_ring_size = mp->default_rx_ring_size; |
1428 | ||
1429 | rxq->rx_desc_count = 0; | |
1430 | rxq->rx_curr_desc = 0; | |
1431 | rxq->rx_used_desc = 0; | |
1432 | ||
1433 | size = rxq->rx_ring_size * sizeof(struct rx_desc); | |
1434 | ||
64da80a2 | 1435 | if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) { |
8a578111 LB |
1436 | rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr, |
1437 | mp->rx_desc_sram_size); | |
1438 | rxq->rx_desc_dma = mp->rx_desc_sram_addr; | |
1439 | } else { | |
1440 | rxq->rx_desc_area = dma_alloc_coherent(NULL, size, | |
1441 | &rxq->rx_desc_dma, | |
1442 | GFP_KERNEL); | |
f7ea3337 PJ |
1443 | } |
1444 | ||
8a578111 LB |
1445 | if (rxq->rx_desc_area == NULL) { |
1446 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1447 | "can't allocate rx ring (%d bytes)\n", size); | |
1448 | goto out; | |
1449 | } | |
1450 | memset(rxq->rx_desc_area, 0, size); | |
1da177e4 | 1451 | |
8a578111 LB |
1452 | rxq->rx_desc_area_size = size; |
1453 | rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb), | |
1454 | GFP_KERNEL); | |
1455 | if (rxq->rx_skb == NULL) { | |
1456 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1457 | "can't allocate rx skb ring\n"); | |
1458 | goto out_free; | |
1459 | } | |
1460 | ||
1461 | rx_desc = (struct rx_desc *)rxq->rx_desc_area; | |
1462 | for (i = 0; i < rxq->rx_ring_size; i++) { | |
1463 | int nexti = (i + 1) % rxq->rx_ring_size; | |
1464 | rx_desc[i].next_desc_ptr = rxq->rx_desc_dma + | |
1465 | nexti * sizeof(struct rx_desc); | |
1466 | } | |
1467 | ||
1468 | init_timer(&rxq->rx_oom); | |
1469 | rxq->rx_oom.data = (unsigned long)rxq; | |
1470 | rxq->rx_oom.function = rxq_refill_timer_wrapper; | |
1471 | ||
1472 | return 0; | |
1473 | ||
1474 | ||
1475 | out_free: | |
64da80a2 | 1476 | if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) |
8a578111 LB |
1477 | iounmap(rxq->rx_desc_area); |
1478 | else | |
1479 | dma_free_coherent(NULL, size, | |
1480 | rxq->rx_desc_area, | |
1481 | rxq->rx_desc_dma); | |
1482 | ||
1483 | out: | |
1484 | return -ENOMEM; | |
c9df406f | 1485 | } |
c8aaea25 | 1486 | |
8a578111 | 1487 | static void rxq_deinit(struct rx_queue *rxq) |
c9df406f | 1488 | { |
8a578111 LB |
1489 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
1490 | int i; | |
1491 | ||
1492 | rxq_disable(rxq); | |
c8aaea25 | 1493 | |
8a578111 | 1494 | del_timer_sync(&rxq->rx_oom); |
c9df406f | 1495 | |
8a578111 LB |
1496 | for (i = 0; i < rxq->rx_ring_size; i++) { |
1497 | if (rxq->rx_skb[i]) { | |
1498 | dev_kfree_skb(rxq->rx_skb[i]); | |
1499 | rxq->rx_desc_count--; | |
1da177e4 | 1500 | } |
c8aaea25 | 1501 | } |
1da177e4 | 1502 | |
8a578111 LB |
1503 | if (rxq->rx_desc_count) { |
1504 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1505 | "error freeing rx ring -- %d skbs stuck\n", | |
1506 | rxq->rx_desc_count); | |
1507 | } | |
1508 | ||
64da80a2 LB |
1509 | if (rxq->index == mp->rxq_primary && |
1510 | rxq->rx_desc_area_size <= mp->rx_desc_sram_size) | |
8a578111 | 1511 | iounmap(rxq->rx_desc_area); |
c9df406f | 1512 | else |
8a578111 LB |
1513 | dma_free_coherent(NULL, rxq->rx_desc_area_size, |
1514 | rxq->rx_desc_area, rxq->rx_desc_dma); | |
1515 | ||
1516 | kfree(rxq->rx_skb); | |
c9df406f | 1517 | } |
1da177e4 | 1518 | |
3d6b35bc | 1519 | static int txq_init(struct mv643xx_eth_private *mp, int index) |
c9df406f | 1520 | { |
3d6b35bc | 1521 | struct tx_queue *txq = mp->txq + index; |
13d64285 LB |
1522 | struct tx_desc *tx_desc; |
1523 | int size; | |
c9df406f | 1524 | int i; |
1da177e4 | 1525 | |
3d6b35bc LB |
1526 | txq->index = index; |
1527 | ||
13d64285 LB |
1528 | txq->tx_ring_size = mp->default_tx_ring_size; |
1529 | ||
1530 | txq->tx_desc_count = 0; | |
1531 | txq->tx_curr_desc = 0; | |
1532 | txq->tx_used_desc = 0; | |
1533 | ||
1534 | size = txq->tx_ring_size * sizeof(struct tx_desc); | |
1535 | ||
3d6b35bc | 1536 | if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) { |
13d64285 LB |
1537 | txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr, |
1538 | mp->tx_desc_sram_size); | |
1539 | txq->tx_desc_dma = mp->tx_desc_sram_addr; | |
1540 | } else { | |
1541 | txq->tx_desc_area = dma_alloc_coherent(NULL, size, | |
1542 | &txq->tx_desc_dma, | |
1543 | GFP_KERNEL); | |
1544 | } | |
1545 | ||
1546 | if (txq->tx_desc_area == NULL) { | |
1547 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1548 | "can't allocate tx ring (%d bytes)\n", size); | |
1549 | goto out; | |
c9df406f | 1550 | } |
13d64285 LB |
1551 | memset(txq->tx_desc_area, 0, size); |
1552 | ||
1553 | txq->tx_desc_area_size = size; | |
1554 | txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb), | |
1555 | GFP_KERNEL); | |
1556 | if (txq->tx_skb == NULL) { | |
1557 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1558 | "can't allocate tx skb ring\n"); | |
1559 | goto out_free; | |
1560 | } | |
1561 | ||
1562 | tx_desc = (struct tx_desc *)txq->tx_desc_area; | |
1563 | for (i = 0; i < txq->tx_ring_size; i++) { | |
6b368f68 | 1564 | struct tx_desc *txd = tx_desc + i; |
13d64285 | 1565 | int nexti = (i + 1) % txq->tx_ring_size; |
6b368f68 LB |
1566 | |
1567 | txd->cmd_sts = 0; | |
1568 | txd->next_desc_ptr = txq->tx_desc_dma + | |
13d64285 LB |
1569 | nexti * sizeof(struct tx_desc); |
1570 | } | |
1571 | ||
1572 | return 0; | |
1573 | ||
c9df406f | 1574 | |
13d64285 | 1575 | out_free: |
3d6b35bc | 1576 | if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) |
13d64285 LB |
1577 | iounmap(txq->tx_desc_area); |
1578 | else | |
1579 | dma_free_coherent(NULL, size, | |
1580 | txq->tx_desc_area, | |
1581 | txq->tx_desc_dma); | |
c9df406f | 1582 | |
13d64285 LB |
1583 | out: |
1584 | return -ENOMEM; | |
c8aaea25 | 1585 | } |
1da177e4 | 1586 | |
13d64285 | 1587 | static void txq_reclaim(struct tx_queue *txq, int force) |
c8aaea25 | 1588 | { |
13d64285 | 1589 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
c8aaea25 | 1590 | unsigned long flags; |
1da177e4 | 1591 | |
13d64285 LB |
1592 | spin_lock_irqsave(&mp->lock, flags); |
1593 | while (txq->tx_desc_count > 0) { | |
1594 | int tx_index; | |
1595 | struct tx_desc *desc; | |
1596 | u32 cmd_sts; | |
1597 | struct sk_buff *skb; | |
1598 | dma_addr_t addr; | |
1599 | int count; | |
4d64e718 | 1600 | |
13d64285 LB |
1601 | tx_index = txq->tx_used_desc; |
1602 | desc = &txq->tx_desc_area[tx_index]; | |
c9df406f | 1603 | cmd_sts = desc->cmd_sts; |
4d64e718 | 1604 | |
6b368f68 LB |
1605 | if (cmd_sts & BUFFER_OWNED_BY_DMA) { |
1606 | if (!force) | |
1607 | break; | |
1608 | desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA; | |
1609 | } | |
1da177e4 | 1610 | |
13d64285 LB |
1611 | txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size; |
1612 | txq->tx_desc_count--; | |
1da177e4 | 1613 | |
c9df406f LB |
1614 | addr = desc->buf_ptr; |
1615 | count = desc->byte_cnt; | |
13d64285 LB |
1616 | skb = txq->tx_skb[tx_index]; |
1617 | txq->tx_skb[tx_index] = NULL; | |
c8aaea25 | 1618 | |
cc9754b3 | 1619 | if (cmd_sts & ERROR_SUMMARY) { |
13d64285 LB |
1620 | dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n"); |
1621 | mp->dev->stats.tx_errors++; | |
c9df406f | 1622 | } |
1da177e4 | 1623 | |
13d64285 LB |
1624 | /* |
1625 | * Drop mp->lock while we free the skb. | |
1626 | */ | |
c9df406f | 1627 | spin_unlock_irqrestore(&mp->lock, flags); |
1da177e4 | 1628 | |
cc9754b3 | 1629 | if (cmd_sts & TX_FIRST_DESC) |
c9df406f LB |
1630 | dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE); |
1631 | else | |
1632 | dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE); | |
c2e5b352 | 1633 | |
c9df406f LB |
1634 | if (skb) |
1635 | dev_kfree_skb_irq(skb); | |
63c9e549 | 1636 | |
13d64285 | 1637 | spin_lock_irqsave(&mp->lock, flags); |
c9df406f | 1638 | } |
13d64285 | 1639 | spin_unlock_irqrestore(&mp->lock, flags); |
c9df406f | 1640 | } |
1da177e4 | 1641 | |
13d64285 | 1642 | static void txq_deinit(struct tx_queue *txq) |
c9df406f | 1643 | { |
13d64285 | 1644 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
fa3959f4 | 1645 | |
13d64285 LB |
1646 | txq_disable(txq); |
1647 | txq_reclaim(txq, 1); | |
1da177e4 | 1648 | |
13d64285 | 1649 | BUG_ON(txq->tx_used_desc != txq->tx_curr_desc); |
1da177e4 | 1650 | |
3d6b35bc LB |
1651 | if (txq->index == mp->txq_primary && |
1652 | txq->tx_desc_area_size <= mp->tx_desc_sram_size) | |
13d64285 | 1653 | iounmap(txq->tx_desc_area); |
c9df406f | 1654 | else |
13d64285 LB |
1655 | dma_free_coherent(NULL, txq->tx_desc_area_size, |
1656 | txq->tx_desc_area, txq->tx_desc_dma); | |
1657 | ||
1658 | kfree(txq->tx_skb); | |
c9df406f | 1659 | } |
1da177e4 | 1660 | |
1da177e4 | 1661 | |
c9df406f | 1662 | /* netdev ops and related ***************************************************/ |
fc32b0e2 | 1663 | static void update_pscr(struct mv643xx_eth_private *mp, int speed, int duplex) |
c9df406f | 1664 | { |
13d64285 LB |
1665 | u32 pscr_o; |
1666 | u32 pscr_n; | |
1da177e4 | 1667 | |
13d64285 | 1668 | pscr_o = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num)); |
63c9e549 | 1669 | |
c9df406f | 1670 | /* clear speed, duplex and rx buffer size fields */ |
13d64285 LB |
1671 | pscr_n = pscr_o & ~(SET_MII_SPEED_TO_100 | |
1672 | SET_GMII_SPEED_TO_1000 | | |
1673 | SET_FULL_DUPLEX_MODE | | |
1674 | MAX_RX_PACKET_MASK); | |
1da177e4 | 1675 | |
65193a91 LB |
1676 | pscr_n |= MAX_RX_PACKET_9700BYTE; |
1677 | ||
1678 | if (speed == SPEED_1000) | |
1679 | pscr_n |= SET_GMII_SPEED_TO_1000; | |
1680 | else if (speed == SPEED_100) | |
1681 | pscr_n |= SET_MII_SPEED_TO_100; | |
1da177e4 | 1682 | |
fc32b0e2 | 1683 | if (duplex == DUPLEX_FULL) |
13d64285 LB |
1684 | pscr_n |= SET_FULL_DUPLEX_MODE; |
1685 | ||
1686 | if (pscr_n != pscr_o) { | |
1687 | if ((pscr_o & SERIAL_PORT_ENABLE) == 0) | |
1688 | wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n); | |
c9df406f | 1689 | else { |
3d6b35bc LB |
1690 | int i; |
1691 | ||
1692 | for (i = 0; i < 8; i++) | |
1693 | if (mp->txq_mask & (1 << i)) | |
1694 | txq_disable(mp->txq + i); | |
1695 | ||
13d64285 LB |
1696 | pscr_o &= ~SERIAL_PORT_ENABLE; |
1697 | wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_o); | |
1698 | wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n); | |
1699 | wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n); | |
3d6b35bc LB |
1700 | |
1701 | for (i = 0; i < 8; i++) | |
1702 | if (mp->txq_mask & (1 << i)) | |
1703 | txq_enable(mp->txq + i); | |
c9df406f LB |
1704 | } |
1705 | } | |
1706 | } | |
84dd619e | 1707 | |
fc32b0e2 | 1708 | static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id) |
c9df406f LB |
1709 | { |
1710 | struct net_device *dev = (struct net_device *)dev_id; | |
e5371493 | 1711 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
fc32b0e2 LB |
1712 | u32 int_cause; |
1713 | u32 int_cause_ext; | |
ce4e2e45 | 1714 | |
226bb6b7 LB |
1715 | int_cause = rdl(mp, INT_CAUSE(mp->port_num)) & |
1716 | (INT_TX_END | INT_RX | INT_EXT); | |
fc32b0e2 LB |
1717 | if (int_cause == 0) |
1718 | return IRQ_NONE; | |
1719 | ||
1720 | int_cause_ext = 0; | |
cc9754b3 | 1721 | if (int_cause & INT_EXT) { |
13d64285 | 1722 | int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num)) |
073a345c | 1723 | & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX); |
13d64285 | 1724 | wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext); |
c9df406f | 1725 | } |
1da177e4 | 1726 | |
fc32b0e2 | 1727 | if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK)) { |
bedfe324 | 1728 | if (mp->phy_addr == -1 || mii_link_ok(&mp->mii)) { |
bedfe324 LB |
1729 | if (mp->phy_addr != -1) { |
1730 | struct ethtool_cmd cmd; | |
1731 | ||
1732 | mii_ethtool_gset(&mp->mii, &cmd); | |
1733 | update_pscr(mp, cmd.speed, cmd.duplex); | |
1734 | } | |
1735 | ||
c9df406f LB |
1736 | if (!netif_carrier_ok(dev)) { |
1737 | netif_carrier_on(dev); | |
6b368f68 | 1738 | netif_wake_queue(dev); |
c9df406f LB |
1739 | } |
1740 | } else if (netif_carrier_ok(dev)) { | |
6b368f68 LB |
1741 | int i; |
1742 | ||
c9df406f LB |
1743 | netif_stop_queue(dev); |
1744 | netif_carrier_off(dev); | |
6b368f68 LB |
1745 | |
1746 | for (i = 0; i < 8; i++) { | |
1747 | struct tx_queue *txq = mp->txq + i; | |
1748 | ||
1749 | if (mp->txq_mask & (1 << i)) { | |
1750 | txq_reclaim(txq, 1); | |
1751 | txq_reset_hw_ptr(txq); | |
1752 | } | |
1753 | } | |
c9df406f LB |
1754 | } |
1755 | } | |
1da177e4 | 1756 | |
64da80a2 LB |
1757 | /* |
1758 | * RxBuffer or RxError set for any of the 8 queues? | |
1759 | */ | |
e5371493 | 1760 | #ifdef MV643XX_ETH_NAPI |
cc9754b3 | 1761 | if (int_cause & INT_RX) { |
13d64285 | 1762 | wrl(mp, INT_MASK(mp->port_num), 0x00000000); |
13d64285 | 1763 | rdl(mp, INT_MASK(mp->port_num)); |
1da177e4 | 1764 | |
c9df406f | 1765 | netif_rx_schedule(dev, &mp->napi); |
84dd619e | 1766 | } |
c9df406f | 1767 | #else |
64da80a2 LB |
1768 | if (int_cause & INT_RX) { |
1769 | int i; | |
1770 | ||
1771 | for (i = 7; i >= 0; i--) | |
1772 | if (mp->rxq_mask & (1 << i)) | |
1773 | rxq_process(mp->rxq + i, INT_MAX); | |
1774 | } | |
c9df406f | 1775 | #endif |
fc32b0e2 | 1776 | |
3d6b35bc LB |
1777 | /* |
1778 | * TxBuffer or TxError set for any of the 8 queues? | |
1779 | */ | |
13d64285 | 1780 | if (int_cause_ext & INT_EXT_TX) { |
3d6b35bc LB |
1781 | int i; |
1782 | ||
1783 | for (i = 0; i < 8; i++) | |
1784 | if (mp->txq_mask & (1 << i)) | |
1785 | txq_reclaim(mp->txq + i, 0); | |
8fa89bf5 LB |
1786 | |
1787 | /* | |
1788 | * Enough space again in the primary TX queue for a | |
1789 | * full packet? | |
1790 | */ | |
6b368f68 LB |
1791 | if (netif_carrier_ok(dev)) { |
1792 | spin_lock(&mp->lock); | |
1793 | __txq_maybe_wake(mp->txq + mp->txq_primary); | |
1794 | spin_unlock(&mp->lock); | |
1795 | } | |
226bb6b7 | 1796 | } |
3d6b35bc | 1797 | |
226bb6b7 LB |
1798 | /* |
1799 | * Any TxEnd interrupts? | |
1800 | */ | |
1801 | if (int_cause & INT_TX_END) { | |
1802 | int i; | |
1803 | ||
1804 | wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END)); | |
8fa89bf5 LB |
1805 | |
1806 | spin_lock(&mp->lock); | |
226bb6b7 LB |
1807 | for (i = 0; i < 8; i++) { |
1808 | struct tx_queue *txq = mp->txq + i; | |
8fa89bf5 LB |
1809 | u32 hw_desc_ptr; |
1810 | u32 expected_ptr; | |
1811 | ||
1812 | if ((int_cause & (INT_TX_END_0 << i)) == 0) | |
1813 | continue; | |
1814 | ||
1815 | hw_desc_ptr = | |
1816 | rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, i)); | |
1817 | expected_ptr = (u32)txq->tx_desc_dma + | |
1818 | txq->tx_curr_desc * sizeof(struct tx_desc); | |
1819 | ||
1820 | if (hw_desc_ptr != expected_ptr) | |
226bb6b7 LB |
1821 | txq_enable(txq); |
1822 | } | |
8fa89bf5 | 1823 | spin_unlock(&mp->lock); |
13d64285 | 1824 | } |
1da177e4 | 1825 | |
c9df406f | 1826 | return IRQ_HANDLED; |
1da177e4 LT |
1827 | } |
1828 | ||
e5371493 | 1829 | static void phy_reset(struct mv643xx_eth_private *mp) |
1da177e4 | 1830 | { |
fc32b0e2 | 1831 | unsigned int data; |
1da177e4 | 1832 | |
fc32b0e2 LB |
1833 | smi_reg_read(mp, mp->phy_addr, 0, &data); |
1834 | data |= 0x8000; | |
1835 | smi_reg_write(mp, mp->phy_addr, 0, data); | |
1da177e4 | 1836 | |
c9df406f LB |
1837 | do { |
1838 | udelay(1); | |
fc32b0e2 LB |
1839 | smi_reg_read(mp, mp->phy_addr, 0, &data); |
1840 | } while (data & 0x8000); | |
1da177e4 LT |
1841 | } |
1842 | ||
fc32b0e2 | 1843 | static void port_start(struct mv643xx_eth_private *mp) |
1da177e4 | 1844 | { |
d0412d96 | 1845 | u32 pscr; |
8a578111 | 1846 | int i; |
1da177e4 | 1847 | |
8a578111 LB |
1848 | /* |
1849 | * Configure basic link parameters. | |
1850 | */ | |
1851 | pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num)); | |
1852 | pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS); | |
1853 | wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr); | |
1854 | pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL | | |
1855 | DISABLE_AUTO_NEG_SPEED_GMII | | |
1856 | DISABLE_AUTO_NEG_FOR_DUPLEX | | |
1857 | DO_NOT_FORCE_LINK_FAIL | | |
1858 | SERIAL_PORT_CONTROL_RESERVED; | |
1859 | wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr); | |
1860 | pscr |= SERIAL_PORT_ENABLE; | |
1861 | wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr); | |
1da177e4 | 1862 | |
8a578111 LB |
1863 | wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE); |
1864 | ||
bedfe324 LB |
1865 | /* |
1866 | * Perform PHY reset, if there is a PHY. | |
1867 | */ | |
1868 | if (mp->phy_addr != -1) { | |
1869 | struct ethtool_cmd cmd; | |
1870 | ||
1871 | mv643xx_eth_get_settings(mp->dev, &cmd); | |
1872 | phy_reset(mp); | |
1873 | mv643xx_eth_set_settings(mp->dev, &cmd); | |
1874 | } | |
1da177e4 | 1875 | |
13d64285 LB |
1876 | /* |
1877 | * Configure TX path and queues. | |
1878 | */ | |
89df5fdc | 1879 | tx_set_rate(mp, 1000000000, 16777216); |
3d6b35bc LB |
1880 | for (i = 0; i < 8; i++) { |
1881 | struct tx_queue *txq = mp->txq + i; | |
13d64285 | 1882 | |
3d6b35bc LB |
1883 | if ((mp->txq_mask & (1 << i)) == 0) |
1884 | continue; | |
1885 | ||
6b368f68 | 1886 | txq_reset_hw_ptr(txq); |
89df5fdc LB |
1887 | txq_set_rate(txq, 1000000000, 16777216); |
1888 | txq_set_fixed_prio_mode(txq); | |
13d64285 LB |
1889 | } |
1890 | ||
fc32b0e2 LB |
1891 | /* |
1892 | * Add configured unicast address to address filter table. | |
1893 | */ | |
1894 | uc_addr_set(mp, mp->dev->dev_addr); | |
1da177e4 | 1895 | |
d9a073ea LB |
1896 | /* |
1897 | * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast | |
1898 | * frames to RX queue #0. | |
1899 | */ | |
8a578111 | 1900 | wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000); |
01999873 | 1901 | |
376489a2 LB |
1902 | /* |
1903 | * Treat BPDUs as normal multicasts, and disable partition mode. | |
1904 | */ | |
8a578111 | 1905 | wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000); |
01999873 | 1906 | |
8a578111 | 1907 | /* |
64da80a2 | 1908 | * Enable the receive queues. |
8a578111 | 1909 | */ |
64da80a2 LB |
1910 | for (i = 0; i < 8; i++) { |
1911 | struct rx_queue *rxq = mp->rxq + i; | |
1912 | int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i); | |
8a578111 | 1913 | u32 addr; |
1da177e4 | 1914 | |
64da80a2 LB |
1915 | if ((mp->rxq_mask & (1 << i)) == 0) |
1916 | continue; | |
1917 | ||
8a578111 LB |
1918 | addr = (u32)rxq->rx_desc_dma; |
1919 | addr += rxq->rx_curr_desc * sizeof(struct rx_desc); | |
1920 | wrl(mp, off, addr); | |
1da177e4 | 1921 | |
8a578111 LB |
1922 | rxq_enable(rxq); |
1923 | } | |
1da177e4 LT |
1924 | } |
1925 | ||
ffd86bbe | 1926 | static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay) |
1da177e4 | 1927 | { |
c9df406f | 1928 | unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64; |
773fc3ee | 1929 | u32 val; |
1da177e4 | 1930 | |
773fc3ee LB |
1931 | val = rdl(mp, SDMA_CONFIG(mp->port_num)); |
1932 | if (mp->shared->extended_rx_coal_limit) { | |
1933 | if (coal > 0xffff) | |
1934 | coal = 0xffff; | |
1935 | val &= ~0x023fff80; | |
1936 | val |= (coal & 0x8000) << 10; | |
1937 | val |= (coal & 0x7fff) << 7; | |
1938 | } else { | |
1939 | if (coal > 0x3fff) | |
1940 | coal = 0x3fff; | |
1941 | val &= ~0x003fff00; | |
1942 | val |= (coal & 0x3fff) << 8; | |
1943 | } | |
1944 | wrl(mp, SDMA_CONFIG(mp->port_num), val); | |
1da177e4 LT |
1945 | } |
1946 | ||
ffd86bbe | 1947 | static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay) |
1da177e4 | 1948 | { |
c9df406f | 1949 | unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64; |
1da177e4 | 1950 | |
fc32b0e2 LB |
1951 | if (coal > 0x3fff) |
1952 | coal = 0x3fff; | |
1953 | wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4); | |
16e03018 DF |
1954 | } |
1955 | ||
c9df406f | 1956 | static int mv643xx_eth_open(struct net_device *dev) |
16e03018 | 1957 | { |
e5371493 | 1958 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f | 1959 | int err; |
64da80a2 | 1960 | int i; |
16e03018 | 1961 | |
fc32b0e2 LB |
1962 | wrl(mp, INT_CAUSE(mp->port_num), 0); |
1963 | wrl(mp, INT_CAUSE_EXT(mp->port_num), 0); | |
1964 | rdl(mp, INT_CAUSE_EXT(mp->port_num)); | |
c9df406f | 1965 | |
fc32b0e2 LB |
1966 | err = request_irq(dev->irq, mv643xx_eth_irq, |
1967 | IRQF_SHARED | IRQF_SAMPLE_RANDOM, | |
1968 | dev->name, dev); | |
c9df406f | 1969 | if (err) { |
fc32b0e2 | 1970 | dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n"); |
c9df406f | 1971 | return -EAGAIN; |
16e03018 DF |
1972 | } |
1973 | ||
fc32b0e2 | 1974 | init_mac_tables(mp); |
16e03018 | 1975 | |
64da80a2 LB |
1976 | for (i = 0; i < 8; i++) { |
1977 | if ((mp->rxq_mask & (1 << i)) == 0) | |
1978 | continue; | |
1979 | ||
1980 | err = rxq_init(mp, i); | |
1981 | if (err) { | |
1982 | while (--i >= 0) | |
1983 | if (mp->rxq_mask & (1 << i)) | |
1984 | rxq_deinit(mp->rxq + i); | |
1985 | goto out; | |
1986 | } | |
1987 | ||
1988 | rxq_refill(mp->rxq + i); | |
1989 | } | |
8a578111 | 1990 | |
3d6b35bc LB |
1991 | for (i = 0; i < 8; i++) { |
1992 | if ((mp->txq_mask & (1 << i)) == 0) | |
1993 | continue; | |
1994 | ||
1995 | err = txq_init(mp, i); | |
1996 | if (err) { | |
1997 | while (--i >= 0) | |
1998 | if (mp->txq_mask & (1 << i)) | |
1999 | txq_deinit(mp->txq + i); | |
2000 | goto out_free; | |
2001 | } | |
2002 | } | |
16e03018 | 2003 | |
e5371493 | 2004 | #ifdef MV643XX_ETH_NAPI |
c9df406f LB |
2005 | napi_enable(&mp->napi); |
2006 | #endif | |
16e03018 | 2007 | |
fc32b0e2 | 2008 | port_start(mp); |
16e03018 | 2009 | |
ffd86bbe LB |
2010 | set_rx_coal(mp, 0); |
2011 | set_tx_coal(mp, 0); | |
16e03018 | 2012 | |
fc32b0e2 LB |
2013 | wrl(mp, INT_MASK_EXT(mp->port_num), |
2014 | INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX); | |
16e03018 | 2015 | |
226bb6b7 | 2016 | wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT); |
16e03018 | 2017 | |
c9df406f LB |
2018 | return 0; |
2019 | ||
13d64285 | 2020 | |
fc32b0e2 | 2021 | out_free: |
64da80a2 LB |
2022 | for (i = 0; i < 8; i++) |
2023 | if (mp->rxq_mask & (1 << i)) | |
2024 | rxq_deinit(mp->rxq + i); | |
fc32b0e2 | 2025 | out: |
c9df406f LB |
2026 | free_irq(dev->irq, dev); |
2027 | ||
2028 | return err; | |
16e03018 DF |
2029 | } |
2030 | ||
e5371493 | 2031 | static void port_reset(struct mv643xx_eth_private *mp) |
1da177e4 | 2032 | { |
fc32b0e2 | 2033 | unsigned int data; |
64da80a2 | 2034 | int i; |
1da177e4 | 2035 | |
64da80a2 LB |
2036 | for (i = 0; i < 8; i++) { |
2037 | if (mp->rxq_mask & (1 << i)) | |
2038 | rxq_disable(mp->rxq + i); | |
3d6b35bc LB |
2039 | if (mp->txq_mask & (1 << i)) |
2040 | txq_disable(mp->txq + i); | |
64da80a2 | 2041 | } |
13d64285 LB |
2042 | while (!(rdl(mp, PORT_STATUS(mp->port_num)) & TX_FIFO_EMPTY)) |
2043 | udelay(10); | |
1da177e4 | 2044 | |
c9df406f | 2045 | /* Reset the Enable bit in the Configuration Register */ |
fc32b0e2 LB |
2046 | data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num)); |
2047 | data &= ~(SERIAL_PORT_ENABLE | | |
2048 | DO_NOT_FORCE_LINK_FAIL | | |
2049 | FORCE_LINK_PASS); | |
2050 | wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data); | |
1da177e4 LT |
2051 | } |
2052 | ||
c9df406f | 2053 | static int mv643xx_eth_stop(struct net_device *dev) |
1da177e4 | 2054 | { |
e5371493 | 2055 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
64da80a2 | 2056 | int i; |
1da177e4 | 2057 | |
fc32b0e2 LB |
2058 | wrl(mp, INT_MASK(mp->port_num), 0x00000000); |
2059 | rdl(mp, INT_MASK(mp->port_num)); | |
1da177e4 | 2060 | |
e5371493 | 2061 | #ifdef MV643XX_ETH_NAPI |
c9df406f LB |
2062 | napi_disable(&mp->napi); |
2063 | #endif | |
2064 | netif_carrier_off(dev); | |
2065 | netif_stop_queue(dev); | |
1da177e4 | 2066 | |
fc32b0e2 LB |
2067 | free_irq(dev->irq, dev); |
2068 | ||
cc9754b3 | 2069 | port_reset(mp); |
fc32b0e2 | 2070 | mib_counters_update(mp); |
1da177e4 | 2071 | |
64da80a2 LB |
2072 | for (i = 0; i < 8; i++) { |
2073 | if (mp->rxq_mask & (1 << i)) | |
2074 | rxq_deinit(mp->rxq + i); | |
3d6b35bc LB |
2075 | if (mp->txq_mask & (1 << i)) |
2076 | txq_deinit(mp->txq + i); | |
64da80a2 | 2077 | } |
1da177e4 | 2078 | |
c9df406f | 2079 | return 0; |
1da177e4 LT |
2080 | } |
2081 | ||
fc32b0e2 | 2082 | static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
1da177e4 | 2083 | { |
e5371493 | 2084 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 2085 | |
bedfe324 LB |
2086 | if (mp->phy_addr != -1) |
2087 | return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL); | |
2088 | ||
2089 | return -EOPNOTSUPP; | |
1da177e4 LT |
2090 | } |
2091 | ||
c9df406f | 2092 | static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu) |
1da177e4 | 2093 | { |
89df5fdc LB |
2094 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
2095 | ||
fc32b0e2 | 2096 | if (new_mtu < 64 || new_mtu > 9500) |
c9df406f | 2097 | return -EINVAL; |
1da177e4 | 2098 | |
c9df406f | 2099 | dev->mtu = new_mtu; |
89df5fdc LB |
2100 | tx_set_rate(mp, 1000000000, 16777216); |
2101 | ||
c9df406f LB |
2102 | if (!netif_running(dev)) |
2103 | return 0; | |
1da177e4 | 2104 | |
c9df406f LB |
2105 | /* |
2106 | * Stop and then re-open the interface. This will allocate RX | |
2107 | * skbs of the new MTU. | |
2108 | * There is a possible danger that the open will not succeed, | |
fc32b0e2 | 2109 | * due to memory being full. |
c9df406f LB |
2110 | */ |
2111 | mv643xx_eth_stop(dev); | |
2112 | if (mv643xx_eth_open(dev)) { | |
fc32b0e2 LB |
2113 | dev_printk(KERN_ERR, &dev->dev, |
2114 | "fatal error on re-opening device after " | |
2115 | "MTU change\n"); | |
c9df406f LB |
2116 | } |
2117 | ||
2118 | return 0; | |
1da177e4 LT |
2119 | } |
2120 | ||
fc32b0e2 | 2121 | static void tx_timeout_task(struct work_struct *ugly) |
1da177e4 | 2122 | { |
fc32b0e2 | 2123 | struct mv643xx_eth_private *mp; |
1da177e4 | 2124 | |
fc32b0e2 LB |
2125 | mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task); |
2126 | if (netif_running(mp->dev)) { | |
2127 | netif_stop_queue(mp->dev); | |
c9df406f | 2128 | |
fc32b0e2 LB |
2129 | port_reset(mp); |
2130 | port_start(mp); | |
c9df406f | 2131 | |
3d6b35bc | 2132 | __txq_maybe_wake(mp->txq + mp->txq_primary); |
fc32b0e2 | 2133 | } |
c9df406f LB |
2134 | } |
2135 | ||
c9df406f | 2136 | static void mv643xx_eth_tx_timeout(struct net_device *dev) |
1da177e4 | 2137 | { |
e5371493 | 2138 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 2139 | |
fc32b0e2 | 2140 | dev_printk(KERN_INFO, &dev->dev, "tx timeout\n"); |
d0412d96 | 2141 | |
c9df406f | 2142 | schedule_work(&mp->tx_timeout_task); |
1da177e4 LT |
2143 | } |
2144 | ||
c9df406f | 2145 | #ifdef CONFIG_NET_POLL_CONTROLLER |
fc32b0e2 | 2146 | static void mv643xx_eth_netpoll(struct net_device *dev) |
9f8dd319 | 2147 | { |
fc32b0e2 | 2148 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f | 2149 | |
fc32b0e2 LB |
2150 | wrl(mp, INT_MASK(mp->port_num), 0x00000000); |
2151 | rdl(mp, INT_MASK(mp->port_num)); | |
c9df406f | 2152 | |
fc32b0e2 | 2153 | mv643xx_eth_irq(dev->irq, dev); |
c9df406f | 2154 | |
f2ca60f2 | 2155 | wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT); |
9f8dd319 | 2156 | } |
c9df406f | 2157 | #endif |
9f8dd319 | 2158 | |
fc32b0e2 | 2159 | static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg) |
9f8dd319 | 2160 | { |
e5371493 | 2161 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f LB |
2162 | int val; |
2163 | ||
fc32b0e2 LB |
2164 | smi_reg_read(mp, addr, reg, &val); |
2165 | ||
c9df406f | 2166 | return val; |
9f8dd319 DF |
2167 | } |
2168 | ||
fc32b0e2 | 2169 | static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val) |
9f8dd319 | 2170 | { |
e5371493 | 2171 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
fc32b0e2 | 2172 | smi_reg_write(mp, addr, reg, val); |
c9df406f | 2173 | } |
9f8dd319 | 2174 | |
9f8dd319 | 2175 | |
c9df406f | 2176 | /* platform glue ************************************************************/ |
e5371493 LB |
2177 | static void |
2178 | mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp, | |
2179 | struct mbus_dram_target_info *dram) | |
c9df406f | 2180 | { |
cc9754b3 | 2181 | void __iomem *base = msp->base; |
c9df406f LB |
2182 | u32 win_enable; |
2183 | u32 win_protect; | |
2184 | int i; | |
9f8dd319 | 2185 | |
c9df406f LB |
2186 | for (i = 0; i < 6; i++) { |
2187 | writel(0, base + WINDOW_BASE(i)); | |
2188 | writel(0, base + WINDOW_SIZE(i)); | |
2189 | if (i < 4) | |
2190 | writel(0, base + WINDOW_REMAP_HIGH(i)); | |
9f8dd319 DF |
2191 | } |
2192 | ||
c9df406f LB |
2193 | win_enable = 0x3f; |
2194 | win_protect = 0; | |
2195 | ||
2196 | for (i = 0; i < dram->num_cs; i++) { | |
2197 | struct mbus_dram_window *cs = dram->cs + i; | |
2198 | ||
2199 | writel((cs->base & 0xffff0000) | | |
2200 | (cs->mbus_attr << 8) | | |
2201 | dram->mbus_dram_target_id, base + WINDOW_BASE(i)); | |
2202 | writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); | |
2203 | ||
2204 | win_enable &= ~(1 << i); | |
2205 | win_protect |= 3 << (2 * i); | |
2206 | } | |
2207 | ||
2208 | writel(win_enable, base + WINDOW_BAR_ENABLE); | |
2209 | msp->win_protect = win_protect; | |
9f8dd319 DF |
2210 | } |
2211 | ||
773fc3ee LB |
2212 | static void infer_hw_params(struct mv643xx_eth_shared_private *msp) |
2213 | { | |
2214 | /* | |
2215 | * Check whether we have a 14-bit coal limit field in bits | |
2216 | * [21:8], or a 16-bit coal limit in bits [25,21:7] of the | |
2217 | * SDMA config register. | |
2218 | */ | |
2219 | writel(0x02000000, msp->base + SDMA_CONFIG(0)); | |
2220 | if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000) | |
2221 | msp->extended_rx_coal_limit = 1; | |
2222 | else | |
2223 | msp->extended_rx_coal_limit = 0; | |
1e881592 LB |
2224 | |
2225 | /* | |
2226 | * Check whether the TX rate control registers are in the | |
2227 | * old or the new place. | |
2228 | */ | |
2229 | writel(1, msp->base + TX_BW_MTU_MOVED(0)); | |
2230 | if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1) | |
2231 | msp->tx_bw_control_moved = 1; | |
2232 | else | |
2233 | msp->tx_bw_control_moved = 0; | |
773fc3ee LB |
2234 | } |
2235 | ||
c9df406f | 2236 | static int mv643xx_eth_shared_probe(struct platform_device *pdev) |
9f8dd319 | 2237 | { |
e5371493 | 2238 | static int mv643xx_eth_version_printed = 0; |
c9df406f | 2239 | struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data; |
e5371493 | 2240 | struct mv643xx_eth_shared_private *msp; |
c9df406f LB |
2241 | struct resource *res; |
2242 | int ret; | |
9f8dd319 | 2243 | |
e5371493 | 2244 | if (!mv643xx_eth_version_printed++) |
c9df406f | 2245 | printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n"); |
9f8dd319 | 2246 | |
c9df406f LB |
2247 | ret = -EINVAL; |
2248 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2249 | if (res == NULL) | |
2250 | goto out; | |
9f8dd319 | 2251 | |
c9df406f LB |
2252 | ret = -ENOMEM; |
2253 | msp = kmalloc(sizeof(*msp), GFP_KERNEL); | |
2254 | if (msp == NULL) | |
2255 | goto out; | |
2256 | memset(msp, 0, sizeof(*msp)); | |
2257 | ||
cc9754b3 LB |
2258 | msp->base = ioremap(res->start, res->end - res->start + 1); |
2259 | if (msp->base == NULL) | |
c9df406f LB |
2260 | goto out_free; |
2261 | ||
2262 | spin_lock_init(&msp->phy_lock); | |
c9df406f LB |
2263 | |
2264 | /* | |
2265 | * (Re-)program MBUS remapping windows if we are asked to. | |
2266 | */ | |
2267 | if (pd != NULL && pd->dram != NULL) | |
2268 | mv643xx_eth_conf_mbus_windows(msp, pd->dram); | |
2269 | ||
fc32b0e2 LB |
2270 | /* |
2271 | * Detect hardware parameters. | |
2272 | */ | |
2273 | msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000; | |
773fc3ee | 2274 | infer_hw_params(msp); |
fc32b0e2 LB |
2275 | |
2276 | platform_set_drvdata(pdev, msp); | |
2277 | ||
c9df406f LB |
2278 | return 0; |
2279 | ||
2280 | out_free: | |
2281 | kfree(msp); | |
2282 | out: | |
2283 | return ret; | |
2284 | } | |
2285 | ||
2286 | static int mv643xx_eth_shared_remove(struct platform_device *pdev) | |
2287 | { | |
e5371493 | 2288 | struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev); |
c9df406f | 2289 | |
cc9754b3 | 2290 | iounmap(msp->base); |
c9df406f LB |
2291 | kfree(msp); |
2292 | ||
2293 | return 0; | |
9f8dd319 DF |
2294 | } |
2295 | ||
c9df406f | 2296 | static struct platform_driver mv643xx_eth_shared_driver = { |
fc32b0e2 LB |
2297 | .probe = mv643xx_eth_shared_probe, |
2298 | .remove = mv643xx_eth_shared_remove, | |
c9df406f | 2299 | .driver = { |
fc32b0e2 | 2300 | .name = MV643XX_ETH_SHARED_NAME, |
c9df406f LB |
2301 | .owner = THIS_MODULE, |
2302 | }, | |
2303 | }; | |
2304 | ||
e5371493 | 2305 | static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr) |
1da177e4 | 2306 | { |
c9df406f | 2307 | int addr_shift = 5 * mp->port_num; |
fc32b0e2 | 2308 | u32 data; |
1da177e4 | 2309 | |
fc32b0e2 LB |
2310 | data = rdl(mp, PHY_ADDR); |
2311 | data &= ~(0x1f << addr_shift); | |
2312 | data |= (phy_addr & 0x1f) << addr_shift; | |
2313 | wrl(mp, PHY_ADDR, data); | |
1da177e4 LT |
2314 | } |
2315 | ||
e5371493 | 2316 | static int phy_addr_get(struct mv643xx_eth_private *mp) |
1da177e4 | 2317 | { |
fc32b0e2 LB |
2318 | unsigned int data; |
2319 | ||
2320 | data = rdl(mp, PHY_ADDR); | |
2321 | ||
2322 | return (data >> (5 * mp->port_num)) & 0x1f; | |
2323 | } | |
2324 | ||
2325 | static void set_params(struct mv643xx_eth_private *mp, | |
2326 | struct mv643xx_eth_platform_data *pd) | |
2327 | { | |
2328 | struct net_device *dev = mp->dev; | |
2329 | ||
2330 | if (is_valid_ether_addr(pd->mac_addr)) | |
2331 | memcpy(dev->dev_addr, pd->mac_addr, 6); | |
2332 | else | |
2333 | uc_addr_get(mp, dev->dev_addr); | |
2334 | ||
2335 | if (pd->phy_addr == -1) { | |
2336 | mp->shared_smi = NULL; | |
2337 | mp->phy_addr = -1; | |
2338 | } else { | |
2339 | mp->shared_smi = mp->shared; | |
2340 | if (pd->shared_smi != NULL) | |
2341 | mp->shared_smi = platform_get_drvdata(pd->shared_smi); | |
2342 | ||
2343 | if (pd->force_phy_addr || pd->phy_addr) { | |
2344 | mp->phy_addr = pd->phy_addr & 0x3f; | |
2345 | phy_addr_set(mp, mp->phy_addr); | |
2346 | } else { | |
2347 | mp->phy_addr = phy_addr_get(mp); | |
2348 | } | |
2349 | } | |
1da177e4 | 2350 | |
fc32b0e2 LB |
2351 | mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE; |
2352 | if (pd->rx_queue_size) | |
2353 | mp->default_rx_ring_size = pd->rx_queue_size; | |
2354 | mp->rx_desc_sram_addr = pd->rx_sram_addr; | |
2355 | mp->rx_desc_sram_size = pd->rx_sram_size; | |
1da177e4 | 2356 | |
64da80a2 LB |
2357 | if (pd->rx_queue_mask) |
2358 | mp->rxq_mask = pd->rx_queue_mask; | |
2359 | else | |
2360 | mp->rxq_mask = 0x01; | |
2361 | mp->rxq_primary = fls(mp->rxq_mask) - 1; | |
2362 | ||
fc32b0e2 LB |
2363 | mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE; |
2364 | if (pd->tx_queue_size) | |
2365 | mp->default_tx_ring_size = pd->tx_queue_size; | |
2366 | mp->tx_desc_sram_addr = pd->tx_sram_addr; | |
2367 | mp->tx_desc_sram_size = pd->tx_sram_size; | |
3d6b35bc LB |
2368 | |
2369 | if (pd->tx_queue_mask) | |
2370 | mp->txq_mask = pd->tx_queue_mask; | |
2371 | else | |
2372 | mp->txq_mask = 0x01; | |
2373 | mp->txq_primary = fls(mp->txq_mask) - 1; | |
1da177e4 LT |
2374 | } |
2375 | ||
e5371493 | 2376 | static int phy_detect(struct mv643xx_eth_private *mp) |
1da177e4 | 2377 | { |
fc32b0e2 LB |
2378 | unsigned int data; |
2379 | unsigned int data2; | |
2380 | ||
2381 | smi_reg_read(mp, mp->phy_addr, 0, &data); | |
2382 | smi_reg_write(mp, mp->phy_addr, 0, data ^ 0x1000); | |
1da177e4 | 2383 | |
fc32b0e2 LB |
2384 | smi_reg_read(mp, mp->phy_addr, 0, &data2); |
2385 | if (((data ^ data2) & 0x1000) == 0) | |
2386 | return -ENODEV; | |
1da177e4 | 2387 | |
fc32b0e2 | 2388 | smi_reg_write(mp, mp->phy_addr, 0, data); |
1da177e4 | 2389 | |
c9df406f | 2390 | return 0; |
1da177e4 LT |
2391 | } |
2392 | ||
fc32b0e2 LB |
2393 | static int phy_init(struct mv643xx_eth_private *mp, |
2394 | struct mv643xx_eth_platform_data *pd) | |
c28a4f89 | 2395 | { |
fc32b0e2 LB |
2396 | struct ethtool_cmd cmd; |
2397 | int err; | |
c28a4f89 | 2398 | |
fc32b0e2 LB |
2399 | err = phy_detect(mp); |
2400 | if (err) { | |
2401 | dev_printk(KERN_INFO, &mp->dev->dev, | |
2402 | "no PHY detected at addr %d\n", mp->phy_addr); | |
2403 | return err; | |
2404 | } | |
2405 | phy_reset(mp); | |
2406 | ||
2407 | mp->mii.phy_id = mp->phy_addr; | |
2408 | mp->mii.phy_id_mask = 0x3f; | |
2409 | mp->mii.reg_num_mask = 0x1f; | |
2410 | mp->mii.dev = mp->dev; | |
2411 | mp->mii.mdio_read = mv643xx_eth_mdio_read; | |
2412 | mp->mii.mdio_write = mv643xx_eth_mdio_write; | |
c28a4f89 | 2413 | |
fc32b0e2 | 2414 | mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii); |
c9df406f | 2415 | |
fc32b0e2 LB |
2416 | memset(&cmd, 0, sizeof(cmd)); |
2417 | ||
2418 | cmd.port = PORT_MII; | |
2419 | cmd.transceiver = XCVR_INTERNAL; | |
2420 | cmd.phy_address = mp->phy_addr; | |
2421 | if (pd->speed == 0) { | |
2422 | cmd.autoneg = AUTONEG_ENABLE; | |
2423 | cmd.speed = SPEED_100; | |
2424 | cmd.advertising = ADVERTISED_10baseT_Half | | |
2425 | ADVERTISED_10baseT_Full | | |
2426 | ADVERTISED_100baseT_Half | | |
2427 | ADVERTISED_100baseT_Full; | |
c9df406f | 2428 | if (mp->mii.supports_gmii) |
fc32b0e2 | 2429 | cmd.advertising |= ADVERTISED_1000baseT_Full; |
c9df406f | 2430 | } else { |
fc32b0e2 LB |
2431 | cmd.autoneg = AUTONEG_DISABLE; |
2432 | cmd.speed = pd->speed; | |
2433 | cmd.duplex = pd->duplex; | |
c9df406f | 2434 | } |
fc32b0e2 LB |
2435 | |
2436 | update_pscr(mp, cmd.speed, cmd.duplex); | |
2437 | mv643xx_eth_set_settings(mp->dev, &cmd); | |
2438 | ||
2439 | return 0; | |
c28a4f89 JC |
2440 | } |
2441 | ||
c9df406f | 2442 | static int mv643xx_eth_probe(struct platform_device *pdev) |
1da177e4 | 2443 | { |
c9df406f | 2444 | struct mv643xx_eth_platform_data *pd; |
e5371493 | 2445 | struct mv643xx_eth_private *mp; |
c9df406f | 2446 | struct net_device *dev; |
c9df406f | 2447 | struct resource *res; |
c9df406f | 2448 | DECLARE_MAC_BUF(mac); |
fc32b0e2 | 2449 | int err; |
1da177e4 | 2450 | |
c9df406f LB |
2451 | pd = pdev->dev.platform_data; |
2452 | if (pd == NULL) { | |
fc32b0e2 LB |
2453 | dev_printk(KERN_ERR, &pdev->dev, |
2454 | "no mv643xx_eth_platform_data\n"); | |
c9df406f LB |
2455 | return -ENODEV; |
2456 | } | |
1da177e4 | 2457 | |
c9df406f | 2458 | if (pd->shared == NULL) { |
fc32b0e2 LB |
2459 | dev_printk(KERN_ERR, &pdev->dev, |
2460 | "no mv643xx_eth_platform_data->shared\n"); | |
c9df406f LB |
2461 | return -ENODEV; |
2462 | } | |
8f518703 | 2463 | |
e5371493 | 2464 | dev = alloc_etherdev(sizeof(struct mv643xx_eth_private)); |
c9df406f LB |
2465 | if (!dev) |
2466 | return -ENOMEM; | |
1da177e4 | 2467 | |
c9df406f | 2468 | mp = netdev_priv(dev); |
fc32b0e2 LB |
2469 | platform_set_drvdata(pdev, mp); |
2470 | ||
2471 | mp->shared = platform_get_drvdata(pd->shared); | |
2472 | mp->port_num = pd->port_number; | |
2473 | ||
c9df406f | 2474 | mp->dev = dev; |
e5371493 LB |
2475 | #ifdef MV643XX_ETH_NAPI |
2476 | netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64); | |
c9df406f | 2477 | #endif |
1da177e4 | 2478 | |
fc32b0e2 LB |
2479 | set_params(mp, pd); |
2480 | ||
2481 | spin_lock_init(&mp->lock); | |
2482 | ||
2483 | mib_counters_clear(mp); | |
2484 | INIT_WORK(&mp->tx_timeout_task, tx_timeout_task); | |
2485 | ||
bedfe324 LB |
2486 | if (mp->phy_addr != -1) { |
2487 | err = phy_init(mp, pd); | |
2488 | if (err) | |
2489 | goto out; | |
2490 | ||
2491 | SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops); | |
2492 | } else { | |
2493 | SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless); | |
2494 | } | |
fc32b0e2 LB |
2495 | |
2496 | ||
c9df406f LB |
2497 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
2498 | BUG_ON(!res); | |
2499 | dev->irq = res->start; | |
1da177e4 | 2500 | |
fc32b0e2 | 2501 | dev->hard_start_xmit = mv643xx_eth_xmit; |
c9df406f LB |
2502 | dev->open = mv643xx_eth_open; |
2503 | dev->stop = mv643xx_eth_stop; | |
c9df406f | 2504 | dev->set_multicast_list = mv643xx_eth_set_rx_mode; |
fc32b0e2 LB |
2505 | dev->set_mac_address = mv643xx_eth_set_mac_address; |
2506 | dev->do_ioctl = mv643xx_eth_ioctl; | |
2507 | dev->change_mtu = mv643xx_eth_change_mtu; | |
c9df406f | 2508 | dev->tx_timeout = mv643xx_eth_tx_timeout; |
c9df406f | 2509 | #ifdef CONFIG_NET_POLL_CONTROLLER |
e5371493 | 2510 | dev->poll_controller = mv643xx_eth_netpoll; |
c9df406f | 2511 | #endif |
c9df406f LB |
2512 | dev->watchdog_timeo = 2 * HZ; |
2513 | dev->base_addr = 0; | |
1da177e4 | 2514 | |
e5371493 | 2515 | #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX |
b4de9051 | 2516 | /* |
c9df406f LB |
2517 | * Zero copy can only work if we use Discovery II memory. Else, we will |
2518 | * have to map the buffers to ISA memory which is only 16 MB | |
b4de9051 | 2519 | */ |
c9df406f | 2520 | dev->features = NETIF_F_SG | NETIF_F_IP_CSUM; |
c9df406f | 2521 | #endif |
1da177e4 | 2522 | |
fc32b0e2 | 2523 | SET_NETDEV_DEV(dev, &pdev->dev); |
8f518703 | 2524 | |
c9df406f | 2525 | if (mp->shared->win_protect) |
fc32b0e2 | 2526 | wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect); |
1da177e4 | 2527 | |
c9df406f LB |
2528 | err = register_netdev(dev); |
2529 | if (err) | |
2530 | goto out; | |
1da177e4 | 2531 | |
fc32b0e2 LB |
2532 | dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n", |
2533 | mp->port_num, print_mac(mac, dev->dev_addr)); | |
1da177e4 | 2534 | |
c9df406f | 2535 | if (dev->features & NETIF_F_SG) |
fc32b0e2 | 2536 | dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n"); |
1da177e4 | 2537 | |
c9df406f | 2538 | if (dev->features & NETIF_F_IP_CSUM) |
fc32b0e2 | 2539 | dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n"); |
1da177e4 | 2540 | |
e5371493 | 2541 | #ifdef MV643XX_ETH_NAPI |
fc32b0e2 | 2542 | dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n"); |
c9df406f | 2543 | #endif |
1da177e4 | 2544 | |
13d64285 | 2545 | if (mp->tx_desc_sram_size > 0) |
fc32b0e2 | 2546 | dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n"); |
1da177e4 | 2547 | |
c9df406f | 2548 | return 0; |
1da177e4 | 2549 | |
c9df406f LB |
2550 | out: |
2551 | free_netdev(dev); | |
1da177e4 | 2552 | |
c9df406f | 2553 | return err; |
1da177e4 LT |
2554 | } |
2555 | ||
c9df406f | 2556 | static int mv643xx_eth_remove(struct platform_device *pdev) |
1da177e4 | 2557 | { |
fc32b0e2 | 2558 | struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); |
1da177e4 | 2559 | |
fc32b0e2 | 2560 | unregister_netdev(mp->dev); |
c9df406f | 2561 | flush_scheduled_work(); |
fc32b0e2 | 2562 | free_netdev(mp->dev); |
c9df406f | 2563 | |
c9df406f | 2564 | platform_set_drvdata(pdev, NULL); |
fc32b0e2 | 2565 | |
c9df406f | 2566 | return 0; |
1da177e4 LT |
2567 | } |
2568 | ||
c9df406f | 2569 | static void mv643xx_eth_shutdown(struct platform_device *pdev) |
d0412d96 | 2570 | { |
fc32b0e2 | 2571 | struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); |
d0412d96 | 2572 | |
c9df406f | 2573 | /* Mask all interrupts on ethernet port */ |
fc32b0e2 LB |
2574 | wrl(mp, INT_MASK(mp->port_num), 0); |
2575 | rdl(mp, INT_MASK(mp->port_num)); | |
c9df406f | 2576 | |
fc32b0e2 LB |
2577 | if (netif_running(mp->dev)) |
2578 | port_reset(mp); | |
d0412d96 JC |
2579 | } |
2580 | ||
c9df406f | 2581 | static struct platform_driver mv643xx_eth_driver = { |
fc32b0e2 LB |
2582 | .probe = mv643xx_eth_probe, |
2583 | .remove = mv643xx_eth_remove, | |
2584 | .shutdown = mv643xx_eth_shutdown, | |
c9df406f | 2585 | .driver = { |
fc32b0e2 | 2586 | .name = MV643XX_ETH_NAME, |
c9df406f LB |
2587 | .owner = THIS_MODULE, |
2588 | }, | |
2589 | }; | |
2590 | ||
e5371493 | 2591 | static int __init mv643xx_eth_init_module(void) |
d0412d96 | 2592 | { |
c9df406f | 2593 | int rc; |
d0412d96 | 2594 | |
c9df406f LB |
2595 | rc = platform_driver_register(&mv643xx_eth_shared_driver); |
2596 | if (!rc) { | |
2597 | rc = platform_driver_register(&mv643xx_eth_driver); | |
2598 | if (rc) | |
2599 | platform_driver_unregister(&mv643xx_eth_shared_driver); | |
2600 | } | |
fc32b0e2 | 2601 | |
c9df406f | 2602 | return rc; |
d0412d96 | 2603 | } |
fc32b0e2 | 2604 | module_init(mv643xx_eth_init_module); |
d0412d96 | 2605 | |
e5371493 | 2606 | static void __exit mv643xx_eth_cleanup_module(void) |
d0412d96 | 2607 | { |
c9df406f LB |
2608 | platform_driver_unregister(&mv643xx_eth_driver); |
2609 | platform_driver_unregister(&mv643xx_eth_shared_driver); | |
d0412d96 | 2610 | } |
e5371493 | 2611 | module_exit(mv643xx_eth_cleanup_module); |
1da177e4 | 2612 | |
45675bc6 LB |
2613 | MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, " |
2614 | "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek"); | |
c9df406f | 2615 | MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); |
fc32b0e2 | 2616 | MODULE_LICENSE("GPL"); |
c9df406f | 2617 | MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME); |
fc32b0e2 | 2618 | MODULE_ALIAS("platform:" MV643XX_ETH_NAME); |