projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mv643xx_eth: unify ethtool ops for phy'd and phy-less interfaces
[deliverable/linux.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
c3efab8e 41#include <linux/ip.h>
1da177e4
LT		 42#include <linux/tcp.h>
43#include <linux/udp.h>
44#include <linux/etherdevice.h>
1da177e4
LT		 45#include <linux/delay.h>
46#include <linux/ethtool.h>
d052d1be 47#include <linux/platform_device.h>
fbd6a754
LB		 48#include <linux/module.h>
49#include <linux/kernel.h>
50#include <linux/spinlock.h>
51#include <linux/workqueue.h>
ed94493f 52#include <linux/phy.h>
fbd6a754 53#include <linux/mv643xx_eth.h>
10a9948d
LB		 54#include <linux/io.h>
55#include <linux/types.h>
1da177e4 56#include <asm/system.h>
fbd6a754 57
e5371493 58static char mv643xx_eth_driver_name[] = "mv643xx_eth";
042af53c 59static char mv643xx_eth_driver_version[] = "1.4";
c9df406f 60
fbd6a754 61
fbd6a754
LB		 62/*
63 * Registers shared between all ports.
64 */
3cb4667c
LB		 65#define PHY_ADDR 0x0000
66#define SMI_REG 0x0004
45c5d3bc
LB		 67#define SMI_BUSY 0x10000000
68#define SMI_READ_VALID 0x08000000
69#define SMI_OPCODE_READ 0x04000000
70#define SMI_OPCODE_WRITE 0x00000000
71#define ERR_INT_CAUSE 0x0080
72#define ERR_INT_SMI_DONE 0x00000010
73#define ERR_INT_MASK 0x0084
3cb4667c
LB		 74#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
75#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
76#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
77#define WINDOW_BAR_ENABLE 0x0290
78#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 79
80/*
37a6084f
LB		 81 * Main per-port registers. These live at offset 0x0400 for
82 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
fbd6a754 83 */
37a6084f 84#define PORT_CONFIG 0x0000
d9a073ea 85#define UNICAST_PROMISCUOUS_MODE 0x00000001
37a6084f
LB		 86#define PORT_CONFIG_EXT 0x0004
87#define MAC_ADDR_LOW 0x0014
88#define MAC_ADDR_HIGH 0x0018
89#define SDMA_CONFIG 0x001c
90#define PORT_SERIAL_CONTROL 0x003c
91#define PORT_STATUS 0x0044
a2a41689 92#define TX_FIFO_EMPTY 0x00000400
ae9ae064 93#define TX_IN_PROGRESS 0x00000080
2f7eb47a
LB		 94#define PORT_SPEED_MASK 0x00000030
95#define PORT_SPEED_1000 0x00000010
96#define PORT_SPEED_100 0x00000020
97#define PORT_SPEED_10 0x00000000
98#define FLOW_CONTROL_ENABLED 0x00000008
99#define FULL_DUPLEX 0x00000004
81600eea 100#define LINK_UP 0x00000002
37a6084f
LB		 101#define TXQ_COMMAND 0x0048
102#define TXQ_FIX_PRIO_CONF 0x004c
103#define TX_BW_RATE 0x0050
104#define TX_BW_MTU 0x0058
105#define TX_BW_BURST 0x005c
106#define INT_CAUSE 0x0060
226bb6b7 107#define INT_TX_END 0x07f80000
befefe21 108#define INT_RX 0x000003fc
073a345c 109#define INT_EXT 0x00000002
37a6084f 110#define INT_CAUSE_EXT 0x0064
befefe21
LB		 111#define INT_EXT_LINK_PHY 0x00110000
112#define INT_EXT_TX 0x000000ff
37a6084f
LB		 113#define INT_MASK 0x0068
114#define INT_MASK_EXT 0x006c
115#define TX_FIFO_URGENT_THRESHOLD 0x0074
116#define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
117#define TX_BW_RATE_MOVED 0x00e0
118#define TX_BW_MTU_MOVED 0x00e8
119#define TX_BW_BURST_MOVED 0x00ec
120#define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
121#define RXQ_COMMAND 0x0280
122#define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
123#define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
124#define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
125#define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
126
127/*
128 * Misc per-port registers.
129 */
3cb4667c
LB		 130#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
131#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
132#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
133#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 134
2679a550
LB		 135
136/*
137 * SDMA configuration register.
138 */
e0c6ef93 139#define RX_BURST_SIZE_4_64BIT (2 << 1)
cd4ccf76 140#define RX_BURST_SIZE_16_64BIT (4 << 1)
fbd6a754 141#define BLM_RX_NO_SWAP (1 << 4)
fbd6a754 142#define BLM_TX_NO_SWAP (1 << 5)
e0c6ef93 143#define TX_BURST_SIZE_4_64BIT (2 << 22)
cd4ccf76 144#define TX_BURST_SIZE_16_64BIT (4 << 22)
fbd6a754
LB		 145
146#if defined(__BIG_ENDIAN)
147#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
e0c6ef93
LB		 148 (RX_BURST_SIZE_4_64BIT | \
149 TX_BURST_SIZE_4_64BIT)
fbd6a754
LB		 150#elif defined(__LITTLE_ENDIAN)
151#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
e0c6ef93
LB		 152 (RX_BURST_SIZE_4_64BIT | \
153 BLM_RX_NO_SWAP | \
154 BLM_TX_NO_SWAP | \
155 TX_BURST_SIZE_4_64BIT)
fbd6a754
LB		 156#else
157#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
158#endif
159
2beff77b
LB		 160
161/*
162 * Port serial control register.
163 */
164#define SET_MII_SPEED_TO_100 (1 << 24)
165#define SET_GMII_SPEED_TO_1000 (1 << 23)
166#define SET_FULL_DUPLEX_MODE (1 << 21)
fbd6a754 167#define MAX_RX_PACKET_9700BYTE (5 << 17)
2beff77b
LB		 168#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
169#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
170#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
171#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
172#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
173#define FORCE_LINK_PASS (1 << 1)
174#define SERIAL_PORT_ENABLE (1 << 0)
fbd6a754 175
2b4a624d
LB		 176#define DEFAULT_RX_QUEUE_SIZE 128
177#define DEFAULT_TX_QUEUE_SIZE 256
fbd6a754 178
fbd6a754 179
7ca72a3b
LB		 180/*
181 * RX/TX descriptors.
fbd6a754
LB		 182 */
183#if defined(__BIG_ENDIAN)
cc9754b3 184struct rx_desc {
fbd6a754
LB		 185 u16 byte_cnt; /* Descriptor buffer byte count */
186 u16 buf_size; /* Buffer size */
187 u32 cmd_sts; /* Descriptor command status */
188 u32 next_desc_ptr; /* Next descriptor pointer */
189 u32 buf_ptr; /* Descriptor buffer pointer */
190};
191
cc9754b3 192struct tx_desc {
fbd6a754
LB		 193 u16 byte_cnt; /* buffer byte count */
194 u16 l4i_chk; /* CPU provided TCP checksum */
195 u32 cmd_sts; /* Command/status field */
196 u32 next_desc_ptr; /* Pointer to next descriptor */
197 u32 buf_ptr; /* pointer to buffer for this descriptor*/
198};
199#elif defined(__LITTLE_ENDIAN)
cc9754b3 200struct rx_desc {
fbd6a754
LB		 201 u32 cmd_sts; /* Descriptor command status */
202 u16 buf_size; /* Buffer size */
203 u16 byte_cnt; /* Descriptor buffer byte count */
204 u32 buf_ptr; /* Descriptor buffer pointer */
205 u32 next_desc_ptr; /* Next descriptor pointer */
206};
207
cc9754b3 208struct tx_desc {
fbd6a754
LB		 209 u32 cmd_sts; /* Command/status field */
210 u16 l4i_chk; /* CPU provided TCP checksum */
211 u16 byte_cnt; /* buffer byte count */
212 u32 buf_ptr; /* pointer to buffer for this descriptor*/
213 u32 next_desc_ptr; /* Pointer to next descriptor */
214};
215#else
216#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
217#endif
218
7ca72a3b 219/* RX & TX descriptor command */
cc9754b3 220#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 221
222/* RX & TX descriptor status */
cc9754b3 223#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 224
225/* RX descriptor status */
cc9754b3
LB		 226#define LAYER_4_CHECKSUM_OK 0x40000000
227#define RX_ENABLE_INTERRUPT 0x20000000
228#define RX_FIRST_DESC 0x08000000
229#define RX_LAST_DESC 0x04000000
7ca72a3b
LB		 230
231/* TX descriptor command */
cc9754b3
LB		 232#define TX_ENABLE_INTERRUPT 0x00800000
233#define GEN_CRC 0x00400000
234#define TX_FIRST_DESC 0x00200000
235#define TX_LAST_DESC 0x00100000
236#define ZERO_PADDING 0x00080000
237#define GEN_IP_V4_CHECKSUM 0x00040000
238#define GEN_TCP_UDP_CHECKSUM 0x00020000
239#define UDP_FRAME 0x00010000
e32b6617
LB		 240#define MAC_HDR_EXTRA_4_BYTES 0x00008000
241#define MAC_HDR_EXTRA_8_BYTES 0x00000200
7ca72a3b 242
cc9754b3 243#define TX_IHL_SHIFT 11
7ca72a3b
LB		 244
245
c9df406f 246/* global *******************************************************************/
e5371493 247struct mv643xx_eth_shared_private {
fc32b0e2
LB		 248 /*
249 * Ethernet controller base address.
250 */
cc9754b3 251 void __iomem *base;
c9df406f 252
fc0eb9f2
LB		 253 /*
254 * Points at the right SMI instance to use.
255 */
256 struct mv643xx_eth_shared_private *smi;
257
fc32b0e2 258 /*
ed94493f 259 * Provides access to local SMI interface.
fc32b0e2 260 */
298cf9be 261 struct mii_bus *smi_bus;
c9df406f 262
45c5d3bc
LB		 263 /*
264 * If we have access to the error interrupt pin (which is
265 * somewhat misnamed as it not only reflects internal errors
266 * but also reflects SMI completion), use that to wait for
267 * SMI access completion instead of polling the SMI busy bit.
268 */
269 int err_interrupt;
270 wait_queue_head_t smi_busy_wait;
271
fc32b0e2
LB		 272 /*
273 * Per-port MBUS window access register value.
274 */
c9df406f
LB		 275 u32 win_protect;
276
fc32b0e2
LB		 277 /*
278 * Hardware-specific parameters.
279 */
c9df406f 280 unsigned int t_clk;
773fc3ee 281 int extended_rx_coal_limit;
457b1d5a 282 int tx_bw_control;
c9df406f
LB		 283};
284
457b1d5a
LB		 285#define TX_BW_CONTROL_ABSENT 0
286#define TX_BW_CONTROL_OLD_LAYOUT 1
287#define TX_BW_CONTROL_NEW_LAYOUT 2
288
c9df406f
LB		 289
290/* per-port *****************************************************************/
e5371493 291struct mib_counters {
fbd6a754
LB		 292 u64 good_octets_received;
293 u32 bad_octets_received;
294 u32 internal_mac_transmit_err;
295 u32 good_frames_received;
296 u32 bad_frames_received;
297 u32 broadcast_frames_received;
298 u32 multicast_frames_received;
299 u32 frames_64_octets;
300 u32 frames_65_to_127_octets;
301 u32 frames_128_to_255_octets;
302 u32 frames_256_to_511_octets;
303 u32 frames_512_to_1023_octets;
304 u32 frames_1024_to_max_octets;
305 u64 good_octets_sent;
306 u32 good_frames_sent;
307 u32 excessive_collision;
308 u32 multicast_frames_sent;
309 u32 broadcast_frames_sent;
310 u32 unrec_mac_control_received;
311 u32 fc_sent;
312 u32 good_fc_received;
313 u32 bad_fc_received;
314 u32 undersize_received;
315 u32 fragments_received;
316 u32 oversize_received;
317 u32 jabber_received;
318 u32 mac_receive_error;
319 u32 bad_crc_event;
320 u32 collision;
321 u32 late_collision;
322};
323
8a578111 324struct rx_queue {
64da80a2
LB		 325 int index;
326
8a578111
LB		 327 int rx_ring_size;
328
329 int rx_desc_count;
330 int rx_curr_desc;
331 int rx_used_desc;
332
333 struct rx_desc *rx_desc_area;
334 dma_addr_t rx_desc_dma;
335 int rx_desc_area_size;
336 struct sk_buff **rx_skb;
8a578111
LB		 337};
338
13d64285 339struct tx_queue {
3d6b35bc
LB		 340 int index;
341
13d64285 342 int tx_ring_size;
fbd6a754 343
13d64285
LB		 344 int tx_desc_count;
345 int tx_curr_desc;
346 int tx_used_desc;
fbd6a754 347
5daffe94 348 struct tx_desc *tx_desc_area;
fbd6a754
LB		 349 dma_addr_t tx_desc_dma;
350 int tx_desc_area_size;
99ab08e0
LB		 351
352 struct sk_buff_head tx_skb;
8fd89211
LB		 353
354 unsigned long tx_packets;
355 unsigned long tx_bytes;
356 unsigned long tx_dropped;
13d64285
LB		 357};
358
359struct mv643xx_eth_private {
360 struct mv643xx_eth_shared_private *shared;
37a6084f 361 void __iomem *base;
fc32b0e2 362 int port_num;
13d64285 363
fc32b0e2 364 struct net_device *dev;
fbd6a754 365
ed94493f 366 struct phy_device *phy;
fbd6a754 367
4ff3495a
LB		 368 struct timer_list mib_counters_timer;
369 spinlock_t mib_counters_lock;
fc32b0e2 370 struct mib_counters mib_counters;
4ff3495a 371
fc32b0e2 372 struct work_struct tx_timeout_task;
8a578111 373
1fa38c58
LB		 374 struct napi_struct napi;
375 u8 work_link;
376 u8 work_tx;
377 u8 work_tx_end;
378 u8 work_rx;
379 u8 work_rx_refill;
380 u8 work_rx_oom;
381
2bcb4b0f
LB		 382 int skb_size;
383 struct sk_buff_head rx_recycle;
384
8a578111
LB		 385 /*
386 * RX state.
387 */
388 int default_rx_ring_size;
389 unsigned long rx_desc_sram_addr;
390 int rx_desc_sram_size;
f7981c1c 391 int rxq_count;
2257e05c 392 struct timer_list rx_oom;
64da80a2 393 struct rx_queue rxq[8];
13d64285
LB		 394
395 /*
396 * TX state.
397 */
398 int default_tx_ring_size;
399 unsigned long tx_desc_sram_addr;
400 int tx_desc_sram_size;
f7981c1c 401 int txq_count;
3d6b35bc 402 struct tx_queue txq[8];
fbd6a754 403};
1da177e4 404
fbd6a754 405
c9df406f 406/* port register accessors **************************************************/
e5371493 407static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 408{
cc9754b3 409 return readl(mp->shared->base + offset);
c9df406f 410}
fbd6a754 411
37a6084f
LB		 412static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
413{
414 return readl(mp->base + offset);
415}
416
e5371493 417static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 418{
cc9754b3 419 writel(data, mp->shared->base + offset);
c9df406f 420}
fbd6a754 421
37a6084f
LB		 422static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
423{
424 writel(data, mp->base + offset);
425}
426
fbd6a754 427
c9df406f 428/* rxq/txq helper functions *************************************************/
8a578111 429static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 430{
64da80a2 431 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 432}
fbd6a754 433
13d64285
LB		 434static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
435{
3d6b35bc 436 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 437}
438
8a578111 439static void rxq_enable(struct rx_queue *rxq)
c9df406f 440{
8a578111 441 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
37a6084f 442 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
8a578111 443}
1da177e4 444
8a578111
LB		 445static void rxq_disable(struct rx_queue *rxq)
446{
447 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 448 u8 mask = 1 << rxq->index;
1da177e4 449
37a6084f
LB		 450 wrlp(mp, RXQ_COMMAND, mask << 8);
451 while (rdlp(mp, RXQ_COMMAND) & mask)
8a578111 452 udelay(10);
c9df406f
LB		 453}
454
6b368f68
LB		 455static void txq_reset_hw_ptr(struct tx_queue *txq)
456{
457 struct mv643xx_eth_private *mp = txq_to_mp(txq);
6b368f68
LB		 458 u32 addr;
459
460 addr = (u32)txq->tx_desc_dma;
461 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
37a6084f 462 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
6b368f68
LB		 463}
464
13d64285 465static void txq_enable(struct tx_queue *txq)
1da177e4 466{
13d64285 467 struct mv643xx_eth_private *mp = txq_to_mp(txq);
37a6084f 468 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
1da177e4
LT		 469}
470
13d64285 471static void txq_disable(struct tx_queue *txq)
1da177e4 472{
13d64285 473 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 474 u8 mask = 1 << txq->index;
c9df406f 475
37a6084f
LB		 476 wrlp(mp, TXQ_COMMAND, mask << 8);
477 while (rdlp(mp, TXQ_COMMAND) & mask)
13d64285
LB		 478 udelay(10);
479}
480
1fa38c58 481static void txq_maybe_wake(struct tx_queue *txq)
13d64285
LB		 482{
483 struct mv643xx_eth_private *mp = txq_to_mp(txq);
e5ef1de1 484 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
3d6b35bc 485
8fd89211
LB		 486 if (netif_tx_queue_stopped(nq)) {
487 __netif_tx_lock(nq, smp_processor_id());
488 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
489 netif_tx_wake_queue(nq);
490 __netif_tx_unlock(nq);
491 }
1da177e4
LT		 492}
493
c9df406f 494
1fa38c58 495/* rx napi ******************************************************************/
8a578111 496static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 497{
8a578111
LB		 498 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
499 struct net_device_stats *stats = &mp->dev->stats;
500 int rx;
1da177e4 501
8a578111 502 rx = 0;
9e1f3772 503 while (rx < budget && rxq->rx_desc_count) {
fc32b0e2 504 struct rx_desc *rx_desc;
96587661 505 unsigned int cmd_sts;
fc32b0e2 506 struct sk_buff *skb;
6b8f90c2 507 u16 byte_cnt;
ff561eef 508
8a578111 509 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 510
96587661 511 cmd_sts = rx_desc->cmd_sts;
2257e05c 512 if (cmd_sts & BUFFER_OWNED_BY_DMA)
96587661 513 break;
96587661 514 rmb();
1da177e4 515
8a578111
LB		 516 skb = rxq->rx_skb[rxq->rx_curr_desc];
517 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 518
9da78745
LB		 519 rxq->rx_curr_desc++;
520 if (rxq->rx_curr_desc == rxq->rx_ring_size)
521 rxq->rx_curr_desc = 0;
ff561eef 522
3a499481 523 dma_unmap_single(NULL, rx_desc->buf_ptr,
abe78717 524 rx_desc->buf_size, DMA_FROM_DEVICE);
8a578111
LB		 525 rxq->rx_desc_count--;
526 rx++;
b1dd9ca1 527
1fa38c58
LB		 528 mp->work_rx_refill |= 1 << rxq->index;
529
6b8f90c2
LB		 530 byte_cnt = rx_desc->byte_cnt;
531
468d09f8
DF		 532 /*
533 * Update statistics.
fc32b0e2
LB		 534 *
535 * Note that the descriptor byte count includes 2 dummy
536 * bytes automatically inserted by the hardware at the
537 * start of the packet (which we don't count), and a 4
538 * byte CRC at the end of the packet (which we do count).
468d09f8 539 */
1da177e4 540 stats->rx_packets++;
6b8f90c2 541 stats->rx_bytes += byte_cnt - 2;
96587661 542
1da177e4 543 /*
fc32b0e2
LB		 544 * In case we received a packet without first / last bits
545 * on, or the error summary bit is set, the packet needs
546 * to be dropped.
1da177e4 547 */
f61e5547
LB		 548 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
549 != (RX_FIRST_DESC | RX_LAST_DESC))
550 goto err;
551
552 /*
553 * The -4 is for the CRC in the trailer of the
554 * received packet
555 */
556 skb_put(skb, byte_cnt - 2 - 4);
557
558 if (cmd_sts & LAYER_4_CHECKSUM_OK)
559 skb->ip_summed = CHECKSUM_UNNECESSARY;
560 skb->protocol = eth_type_trans(skb, mp->dev);
561 netif_receive_skb(skb);
562
563 continue;
564
565err:
566 stats->rx_dropped++;
567
568 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
569 (RX_FIRST_DESC | RX_LAST_DESC)) {
570 if (net_ratelimit())
571 dev_printk(KERN_ERR, &mp->dev->dev,
572 "received packet spanning "
573 "multiple descriptors\n");
1da177e4 574 }
f61e5547
LB		 575
576 if (cmd_sts & ERROR_SUMMARY)
577 stats->rx_errors++;
578
579 dev_kfree_skb(skb);
1da177e4 580 }
fc32b0e2 581
1fa38c58
LB		 582 if (rx < budget)
583 mp->work_rx &= ~(1 << rxq->index);
584
8a578111 585 return rx;
1da177e4
LT		 586}
587
1fa38c58 588static int rxq_refill(struct rx_queue *rxq, int budget)
d0412d96 589{
1fa38c58 590 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1fa38c58 591 int refilled;
8a578111 592
1fa38c58
LB		 593 refilled = 0;
594 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
595 struct sk_buff *skb;
596 int unaligned;
597 int rx;
53771522 598 struct rx_desc *rx_desc;
d0412d96 599
2bcb4b0f
LB		 600 skb = __skb_dequeue(&mp->rx_recycle);
601 if (skb == NULL)
602 skb = dev_alloc_skb(mp->skb_size +
603 dma_get_cache_alignment() - 1);
604
1fa38c58
LB		 605 if (skb == NULL) {
606 mp->work_rx_oom |= 1 << rxq->index;
607 goto oom;
608 }
d0412d96 609
1fa38c58
LB		 610 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
611 if (unaligned)
612 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
2257e05c 613
1fa38c58
LB		 614 refilled++;
615 rxq->rx_desc_count++;
c9df406f 616
1fa38c58
LB		 617 rx = rxq->rx_used_desc++;
618 if (rxq->rx_used_desc == rxq->rx_ring_size)
619 rxq->rx_used_desc = 0;
2257e05c 620
53771522
LB		 621 rx_desc = rxq->rx_desc_area + rx;
622
623 rx_desc->buf_ptr = dma_map_single(NULL, skb->data,
624 mp->skb_size, DMA_FROM_DEVICE);
625 rx_desc->buf_size = mp->skb_size;
1fa38c58
LB		 626 rxq->rx_skb[rx] = skb;
627 wmb();
53771522 628 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
1fa38c58 629 wmb();
2257e05c 630
1fa38c58
LB		 631 /*
632 * The hardware automatically prepends 2 bytes of
633 * dummy data to each received packet, so that the
634 * IP header ends up 16-byte aligned.
635 */
636 skb_reserve(skb, 2);
637 }
638
639 if (refilled < budget)
640 mp->work_rx_refill &= ~(1 << rxq->index);
641
642oom:
643 return refilled;
d0412d96
JC		 644}
645
c9df406f
LB		 646
647/* tx ***********************************************************************/
c9df406f 648static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 649{
13d64285 650 int frag;
1da177e4 651
c9df406f 652 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
13d64285
LB		 653 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
654 if (fragp->size <= 8 && fragp->page_offset & 7)
c9df406f 655 return 1;
1da177e4 656 }
13d64285 657
c9df406f
LB		 658 return 0;
659}
7303fde8 660
13d64285 661static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 662{
13d64285 663 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 664 int frag;
1da177e4 665
13d64285
LB		 666 for (frag = 0; frag < nr_frags; frag++) {
667 skb_frag_t *this_frag;
668 int tx_index;
669 struct tx_desc *desc;
670
671 this_frag = &skb_shinfo(skb)->frags[frag];
66823b92
LB		 672 tx_index = txq->tx_curr_desc++;
673 if (txq->tx_curr_desc == txq->tx_ring_size)
674 txq->tx_curr_desc = 0;
13d64285
LB		 675 desc = &txq->tx_desc_area[tx_index];
676
677 /*
678 * The last fragment will generate an interrupt
679 * which will free the skb on TX completion.
680 */
681 if (frag == nr_frags - 1) {
682 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
683 ZERO_PADDING | TX_LAST_DESC |
684 TX_ENABLE_INTERRUPT;
13d64285
LB		 685 } else {
686 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
13d64285
LB		 687 }
688
c9df406f
LB		 689 desc->l4i_chk = 0;
690 desc->byte_cnt = this_frag->size;
691 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
692 this_frag->page_offset,
693 this_frag->size,
694 DMA_TO_DEVICE);
695 }
1da177e4
LT		 696}
697
c9df406f
LB		 698static inline __be16 sum16_as_be(__sum16 sum)
699{
700 return (__force __be16)sum;
701}
1da177e4 702
4df89bd5 703static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 704{
8fa89bf5 705 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 706 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 707 int tx_index;
cc9754b3 708 struct tx_desc *desc;
c9df406f 709 u32 cmd_sts;
4df89bd5 710 u16 l4i_chk;
c9df406f 711 int length;
1da177e4 712
cc9754b3 713 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
4df89bd5 714 l4i_chk = 0;
c9df406f
LB		 715
716 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4df89bd5 717 int tag_bytes;
e32b6617
LB		 718
719 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
720 skb->protocol != htons(ETH_P_8021Q));
c9df406f 721
4df89bd5
LB		 722 tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN;
723 if (unlikely(tag_bytes & ~12)) {
724 if (skb_checksum_help(skb) == 0)
725 goto no_csum;
726 kfree_skb(skb);
727 return 1;
728 }
c9df406f 729
4df89bd5 730 if (tag_bytes & 4)
e32b6617 731 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
4df89bd5 732 if (tag_bytes & 8)
e32b6617 733 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
4df89bd5
LB		 734
735 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
736 GEN_IP_V4_CHECKSUM |
737 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
e32b6617 738
c9df406f
LB		 739 switch (ip_hdr(skb)->protocol) {
740 case IPPROTO_UDP:
cc9754b3 741 cmd_sts |= UDP_FRAME;
4df89bd5 742 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
c9df406f
LB		 743 break;
744 case IPPROTO_TCP:
4df89bd5 745 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
c9df406f
LB		 746 break;
747 default:
748 BUG();
749 }
750 } else {
4df89bd5 751no_csum:
c9df406f 752 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 753 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 754 }
755
66823b92
LB		 756 tx_index = txq->tx_curr_desc++;
757 if (txq->tx_curr_desc == txq->tx_ring_size)
758 txq->tx_curr_desc = 0;
4df89bd5
LB		 759 desc = &txq->tx_desc_area[tx_index];
760
761 if (nr_frags) {
762 txq_submit_frag_skb(txq, skb);
763 length = skb_headlen(skb);
764 } else {
765 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
766 length = skb->len;
767 }
768
769 desc->l4i_chk = l4i_chk;
770 desc->byte_cnt = length;
771 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
772
99ab08e0
LB		 773 __skb_queue_tail(&txq->tx_skb, skb);
774
c9df406f
LB		 775 /* ensure all other descriptors are written before first cmd_sts */
776 wmb();
777 desc->cmd_sts = cmd_sts;
778
1fa38c58
LB		 779 /* clear TX_END status */
780 mp->work_tx_end &= ~(1 << txq->index);
8fa89bf5 781
c9df406f
LB		 782 /* ensure all descriptors are written before poking hardware */
783 wmb();
13d64285 784 txq_enable(txq);
c9df406f 785
13d64285 786 txq->tx_desc_count += nr_frags + 1;
4df89bd5
LB		 787
788 return 0;
1da177e4 789}
1da177e4 790
fc32b0e2 791static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 792{
e5371493 793 struct mv643xx_eth_private *mp = netdev_priv(dev);
e5ef1de1 794 int queue;
13d64285 795 struct tx_queue *txq;
e5ef1de1 796 struct netdev_queue *nq;
afdb57a2 797
8fd89211
LB		 798 queue = skb_get_queue_mapping(skb);
799 txq = mp->txq + queue;
800 nq = netdev_get_tx_queue(dev, queue);
801
c9df406f 802 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
8fd89211 803 txq->tx_dropped++;
fc32b0e2
LB		 804 dev_printk(KERN_DEBUG, &dev->dev,
805 "failed to linearize skb with tiny "
806 "unaligned fragment\n");
c9df406f
LB		 807 return NETDEV_TX_BUSY;
808 }
809
17cd0a59 810 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
e5ef1de1
LB		 811 if (net_ratelimit())
812 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
3d6b35bc
LB		 813 kfree_skb(skb);
814 return NETDEV_TX_OK;
c9df406f
LB		 815 }
816
4df89bd5
LB		 817 if (!txq_submit_skb(txq, skb)) {
818 int entries_left;
819
820 txq->tx_bytes += skb->len;
821 txq->tx_packets++;
822 dev->trans_start = jiffies;
c9df406f 823
4df89bd5
LB		 824 entries_left = txq->tx_ring_size - txq->tx_desc_count;
825 if (entries_left < MAX_SKB_FRAGS + 1)
826 netif_tx_stop_queue(nq);
827 }
c9df406f 828
c9df406f 829 return NETDEV_TX_OK;
1da177e4
LT		 830}
831
c9df406f 832
1fa38c58
LB		 833/* tx napi ******************************************************************/
834static void txq_kick(struct tx_queue *txq)
835{
836 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 837 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 838 u32 hw_desc_ptr;
839 u32 expected_ptr;
840
8fd89211 841 __netif_tx_lock(nq, smp_processor_id());
1fa38c58 842
37a6084f 843 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
1fa38c58
LB		 844 goto out;
845
37a6084f 846 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
1fa38c58
LB		 847 expected_ptr = (u32)txq->tx_desc_dma +
848 txq->tx_curr_desc * sizeof(struct tx_desc);
849
850 if (hw_desc_ptr != expected_ptr)
851 txq_enable(txq);
852
853out:
8fd89211 854 __netif_tx_unlock(nq);
1fa38c58
LB		 855
856 mp->work_tx_end &= ~(1 << txq->index);
857}
858
859static int txq_reclaim(struct tx_queue *txq, int budget, int force)
860{
861 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 862 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 863 int reclaimed;
864
8fd89211 865 __netif_tx_lock(nq, smp_processor_id());
1fa38c58
LB		 866
867 reclaimed = 0;
868 while (reclaimed < budget && txq->tx_desc_count > 0) {
869 int tx_index;
870 struct tx_desc *desc;
871 u32 cmd_sts;
872 struct sk_buff *skb;
1fa38c58
LB		 873
874 tx_index = txq->tx_used_desc;
875 desc = &txq->tx_desc_area[tx_index];
876 cmd_sts = desc->cmd_sts;
877
878 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
879 if (!force)
880 break;
881 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
882 }
883
884 txq->tx_used_desc = tx_index + 1;
885 if (txq->tx_used_desc == txq->tx_ring_size)
886 txq->tx_used_desc = 0;
887
888 reclaimed++;
889 txq->tx_desc_count--;
890
99ab08e0
LB		 891 skb = NULL;
892 if (cmd_sts & TX_LAST_DESC)
893 skb = __skb_dequeue(&txq->tx_skb);
1fa38c58
LB		 894
895 if (cmd_sts & ERROR_SUMMARY) {
896 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
897 mp->dev->stats.tx_errors++;
898 }
899
a418950c
LB		 900 if (cmd_sts & TX_FIRST_DESC) {
901 dma_unmap_single(NULL, desc->buf_ptr,
902 desc->byte_cnt, DMA_TO_DEVICE);
903 } else {
904 dma_unmap_page(NULL, desc->buf_ptr,
905 desc->byte_cnt, DMA_TO_DEVICE);
906 }
1fa38c58 907
2bcb4b0f
LB		 908 if (skb != NULL) {
909 if (skb_queue_len(&mp->rx_recycle) <
910 mp->default_rx_ring_size &&
11b4aa03
LB		 911 skb_recycle_check(skb, mp->skb_size +
912 dma_get_cache_alignment() - 1))
2bcb4b0f
LB		 913 __skb_queue_head(&mp->rx_recycle, skb);
914 else
915 dev_kfree_skb(skb);
916 }
1fa38c58
LB		 917 }
918
8fd89211
LB		 919 __netif_tx_unlock(nq);
920
1fa38c58
LB		 921 if (reclaimed < budget)
922 mp->work_tx &= ~(1 << txq->index);
923
1fa38c58
LB		 924 return reclaimed;
925}
926
927
89df5fdc
LB		 928/* tx rate control **********************************************************/
929/*
930 * Set total maximum TX rate (shared by all TX queues for this port)
931 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
932 */
933static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
934{
935 int token_rate;
936 int mtu;
937 int bucket_size;
938
939 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
940 if (token_rate > 1023)
941 token_rate = 1023;
942
943 mtu = (mp->dev->mtu + 255) >> 8;
944 if (mtu > 63)
945 mtu = 63;
946
947 bucket_size = (burst + 255) >> 8;
948 if (bucket_size > 65535)
949 bucket_size = 65535;
950
457b1d5a
LB		 951 switch (mp->shared->tx_bw_control) {
952 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f
LB		 953 wrlp(mp, TX_BW_RATE, token_rate);
954 wrlp(mp, TX_BW_MTU, mtu);
955 wrlp(mp, TX_BW_BURST, bucket_size);
457b1d5a
LB		 956 break;
957 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f
LB		 958 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
959 wrlp(mp, TX_BW_MTU_MOVED, mtu);
960 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
457b1d5a 961 break;
1e881592 962 }
89df5fdc
LB		 963}
964
965static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
966{
967 struct mv643xx_eth_private *mp = txq_to_mp(txq);
968 int token_rate;
969 int bucket_size;
970
971 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
972 if (token_rate > 1023)
973 token_rate = 1023;
974
975 bucket_size = (burst + 255) >> 8;
976 if (bucket_size > 65535)
977 bucket_size = 65535;
978
37a6084f
LB		 979 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
980 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
89df5fdc
LB		 981}
982
983static void txq_set_fixed_prio_mode(struct tx_queue *txq)
984{
985 struct mv643xx_eth_private *mp = txq_to_mp(txq);
986 int off;
987 u32 val;
988
989 /*
990 * Turn on fixed priority mode.
991 */
457b1d5a
LB		 992 off = 0;
993 switch (mp->shared->tx_bw_control) {
994 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f 995 off = TXQ_FIX_PRIO_CONF;
457b1d5a
LB		 996 break;
997 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f 998 off = TXQ_FIX_PRIO_CONF_MOVED;
457b1d5a
LB		 999 break;
1000 }
89df5fdc 1001
457b1d5a 1002 if (off) {
37a6084f 1003 val = rdlp(mp, off);
457b1d5a 1004 val |= 1 << txq->index;
37a6084f 1005 wrlp(mp, off, val);
457b1d5a 1006 }
89df5fdc
LB		 1007}
1008
1009static void txq_set_wrr(struct tx_queue *txq, int weight)
1010{
1011 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1012 int off;
1013 u32 val;
1014
1015 /*
1016 * Turn off fixed priority mode.
1017 */
457b1d5a
LB		 1018 off = 0;
1019 switch (mp->shared->tx_bw_control) {
1020 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f 1021 off = TXQ_FIX_PRIO_CONF;
457b1d5a
LB		 1022 break;
1023 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f 1024 off = TXQ_FIX_PRIO_CONF_MOVED;
457b1d5a
LB		 1025 break;
1026 }
89df5fdc 1027
457b1d5a 1028 if (off) {
37a6084f 1029 val = rdlp(mp, off);
457b1d5a 1030 val &= ~(1 << txq->index);
37a6084f 1031 wrlp(mp, off, val);
89df5fdc 1032
457b1d5a
LB		 1033 /*
1034 * Configure WRR weight for this queue.
1035 */
89df5fdc 1036
37a6084f 1037 val = rdlp(mp, off);
457b1d5a 1038 val = (val & ~0xff) | (weight & 0xff);
37a6084f 1039 wrlp(mp, TXQ_BW_WRR_CONF(txq->index), val);
457b1d5a 1040 }
89df5fdc
LB		 1041}
1042
1043
c9df406f 1044/* mii management interface *************************************************/
45c5d3bc
LB		 1045static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1046{
1047 struct mv643xx_eth_shared_private *msp = dev_id;
1048
1049 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1050 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1051 wake_up(&msp->smi_busy_wait);
1052 return IRQ_HANDLED;
1053 }
1054
1055 return IRQ_NONE;
1056}
c9df406f 1057
45c5d3bc 1058static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1da177e4 1059{
45c5d3bc
LB		 1060 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1061}
1da177e4 1062
45c5d3bc
LB		 1063static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1064{
1065 if (msp->err_interrupt == NO_IRQ) {
1066 int i;
c9df406f 1067
45c5d3bc
LB		 1068 for (i = 0; !smi_is_done(msp); i++) {
1069 if (i == 10)
1070 return -ETIMEDOUT;
1071 msleep(10);
c9df406f 1072 }
45c5d3bc
LB		 1073
1074 return 0;
1075 }
1076
ee04448d
LB		 1077 if (!smi_is_done(msp)) {
1078 wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1079 msecs_to_jiffies(100));
1080 if (!smi_is_done(msp))
1081 return -ETIMEDOUT;
1082 }
45c5d3bc
LB		 1083
1084 return 0;
1085}
1086
ed94493f 1087static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
45c5d3bc 1088{
ed94493f 1089 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc
LB		 1090 void __iomem *smi_reg = msp->base + SMI_REG;
1091 int ret;
1092
45c5d3bc 1093 if (smi_wait_ready(msp)) {
10a9948d 1094 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f 1095 return -ETIMEDOUT;
1da177e4
LT		 1096 }
1097
fc32b0e2 1098 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 1099
45c5d3bc 1100 if (smi_wait_ready(msp)) {
10a9948d 1101 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f 1102 return -ETIMEDOUT;
45c5d3bc
LB		 1103 }
1104
1105 ret = readl(smi_reg);
1106 if (!(ret & SMI_READ_VALID)) {
10a9948d 1107 printk(KERN_WARNING "mv643xx_eth: SMI bus read not valid\n");
ed94493f 1108 return -ENODEV;
c9df406f
LB		 1109 }
1110
ed94493f 1111 return ret & 0xffff;
1da177e4
LT		 1112}
1113
ed94493f 1114static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
1da177e4 1115{
ed94493f 1116 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc 1117 void __iomem *smi_reg = msp->base + SMI_REG;
1da177e4 1118
45c5d3bc 1119 if (smi_wait_ready(msp)) {
10a9948d 1120 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
45c5d3bc 1121 return -ETIMEDOUT;
1da177e4
LT		 1122 }
1123
fc32b0e2 1124 writel(SMI_OPCODE_WRITE | (reg << 21) |
ed94493f 1125 (addr << 16) | (val & 0xffff), smi_reg);
45c5d3bc 1126
ed94493f 1127 if (smi_wait_ready(msp)) {
10a9948d 1128 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f
LB		 1129 return -ETIMEDOUT;
1130 }
45c5d3bc
LB		 1131
1132 return 0;
c9df406f 1133}
1da177e4 1134
c9df406f 1135
8fd89211
LB		 1136/* statistics ***************************************************************/
1137static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1138{
1139 struct mv643xx_eth_private *mp = netdev_priv(dev);
1140 struct net_device_stats *stats = &dev->stats;
1141 unsigned long tx_packets = 0;
1142 unsigned long tx_bytes = 0;
1143 unsigned long tx_dropped = 0;
1144 int i;
1145
1146 for (i = 0; i < mp->txq_count; i++) {
1147 struct tx_queue *txq = mp->txq + i;
1148
1149 tx_packets += txq->tx_packets;
1150 tx_bytes += txq->tx_bytes;
1151 tx_dropped += txq->tx_dropped;
1152 }
1153
1154 stats->tx_packets = tx_packets;
1155 stats->tx_bytes = tx_bytes;
1156 stats->tx_dropped = tx_dropped;
1157
1158 return stats;
1159}
1160
fc32b0e2 1161static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 1162{
fc32b0e2 1163 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 1164}
1165
fc32b0e2 1166static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 1167{
fc32b0e2
LB		 1168 int i;
1169
1170 for (i = 0; i < 0x80; i += 4)
1171 mib_read(mp, i);
c9df406f 1172}
d0412d96 1173
fc32b0e2 1174static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 1175{
e5371493 1176 struct mib_counters *p = &mp->mib_counters;
4b8e3655 1177
4ff3495a 1178 spin_lock(&mp->mib_counters_lock);
fc32b0e2
LB		 1179 p->good_octets_received += mib_read(mp, 0x00);
1180 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1181 p->bad_octets_received += mib_read(mp, 0x08);
1182 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1183 p->good_frames_received += mib_read(mp, 0x10);
1184 p->bad_frames_received += mib_read(mp, 0x14);
1185 p->broadcast_frames_received += mib_read(mp, 0x18);
1186 p->multicast_frames_received += mib_read(mp, 0x1c);
1187 p->frames_64_octets += mib_read(mp, 0x20);
1188 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1189 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1190 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1191 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1192 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1193 p->good_octets_sent += mib_read(mp, 0x38);
1194 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1195 p->good_frames_sent += mib_read(mp, 0x40);
1196 p->excessive_collision += mib_read(mp, 0x44);
1197 p->multicast_frames_sent += mib_read(mp, 0x48);
1198 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1199 p->unrec_mac_control_received += mib_read(mp, 0x50);
1200 p->fc_sent += mib_read(mp, 0x54);
1201 p->good_fc_received += mib_read(mp, 0x58);
1202 p->bad_fc_received += mib_read(mp, 0x5c);
1203 p->undersize_received += mib_read(mp, 0x60);
1204 p->fragments_received += mib_read(mp, 0x64);
1205 p->oversize_received += mib_read(mp, 0x68);
1206 p->jabber_received += mib_read(mp, 0x6c);
1207 p->mac_receive_error += mib_read(mp, 0x70);
1208 p->bad_crc_event += mib_read(mp, 0x74);
1209 p->collision += mib_read(mp, 0x78);
1210 p->late_collision += mib_read(mp, 0x7c);
4ff3495a
LB		 1211 spin_unlock(&mp->mib_counters_lock);
1212
1213 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1214}
1215
1216static void mib_counters_timer_wrapper(unsigned long _mp)
1217{
1218 struct mv643xx_eth_private *mp = (void *)_mp;
1219
1220 mib_counters_update(mp);
d0412d96
JC		 1221}
1222
c9df406f
LB		 1223
1224/* ethtool ******************************************************************/
e5371493 1225struct mv643xx_eth_stats {
c9df406f
LB		 1226 char stat_string[ETH_GSTRING_LEN];
1227 int sizeof_stat;
16820054
LB		 1228 int netdev_off;
1229 int mp_off;
c9df406f
LB		 1230};
1231
16820054
LB		 1232#define SSTAT(m) \
1233 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1234 offsetof(struct net_device, stats.m), -1 }
1235
1236#define MIBSTAT(m) \
1237 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1238 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1239
1240static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1241 SSTAT(rx_packets),
1242 SSTAT(tx_packets),
1243 SSTAT(rx_bytes),
1244 SSTAT(tx_bytes),
1245 SSTAT(rx_errors),
1246 SSTAT(tx_errors),
1247 SSTAT(rx_dropped),
1248 SSTAT(tx_dropped),
1249 MIBSTAT(good_octets_received),
1250 MIBSTAT(bad_octets_received),
1251 MIBSTAT(internal_mac_transmit_err),
1252 MIBSTAT(good_frames_received),
1253 MIBSTAT(bad_frames_received),
1254 MIBSTAT(broadcast_frames_received),
1255 MIBSTAT(multicast_frames_received),
1256 MIBSTAT(frames_64_octets),
1257 MIBSTAT(frames_65_to_127_octets),
1258 MIBSTAT(frames_128_to_255_octets),
1259 MIBSTAT(frames_256_to_511_octets),
1260 MIBSTAT(frames_512_to_1023_octets),
1261 MIBSTAT(frames_1024_to_max_octets),
1262 MIBSTAT(good_octets_sent),
1263 MIBSTAT(good_frames_sent),
1264 MIBSTAT(excessive_collision),
1265 MIBSTAT(multicast_frames_sent),
1266 MIBSTAT(broadcast_frames_sent),
1267 MIBSTAT(unrec_mac_control_received),
1268 MIBSTAT(fc_sent),
1269 MIBSTAT(good_fc_received),
1270 MIBSTAT(bad_fc_received),
1271 MIBSTAT(undersize_received),
1272 MIBSTAT(fragments_received),
1273 MIBSTAT(oversize_received),
1274 MIBSTAT(jabber_received),
1275 MIBSTAT(mac_receive_error),
1276 MIBSTAT(bad_crc_event),
1277 MIBSTAT(collision),
1278 MIBSTAT(late_collision),
c9df406f
LB		 1279};
1280
10a9948d 1281static int
6bdf576e
LB		 1282mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1283 struct ethtool_cmd *cmd)
d0412d96 1284{
d0412d96
JC		 1285 int err;
1286
ed94493f
LB		 1287 err = phy_read_status(mp->phy);
1288 if (err == 0)
1289 err = phy_ethtool_gset(mp->phy, cmd);
d0412d96 1290
fc32b0e2
LB		 1291 /*
1292 * The MAC does not support 1000baseT_Half.
1293 */
d0412d96
JC		 1294 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1295 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1296
1297 return err;
1298}
1299
10a9948d 1300static int
6bdf576e 1301mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
10a9948d 1302 struct ethtool_cmd *cmd)
bedfe324 1303{
81600eea
LB		 1304 u32 port_status;
1305
37a6084f 1306 port_status = rdlp(mp, PORT_STATUS);
81600eea 1307
bedfe324
LB		 1308 cmd->supported = SUPPORTED_MII;
1309 cmd->advertising = ADVERTISED_MII;
81600eea
LB		 1310 switch (port_status & PORT_SPEED_MASK) {
1311 case PORT_SPEED_10:
1312 cmd->speed = SPEED_10;
1313 break;
1314 case PORT_SPEED_100:
1315 cmd->speed = SPEED_100;
1316 break;
1317 case PORT_SPEED_1000:
1318 cmd->speed = SPEED_1000;
1319 break;
1320 default:
1321 cmd->speed = -1;
1322 break;
1323 }
1324 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
bedfe324
LB		 1325 cmd->port = PORT_MII;
1326 cmd->phy_address = 0;
1327 cmd->transceiver = XCVR_INTERNAL;
1328 cmd->autoneg = AUTONEG_DISABLE;
1329 cmd->maxtxpkt = 1;
1330 cmd->maxrxpkt = 1;
1331
1332 return 0;
1333}
1334
6bdf576e
LB		 1335static int
1336mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1337{
1338 struct mv643xx_eth_private *mp = netdev_priv(dev);
1339
1340 if (mp->phy != NULL)
1341 return mv643xx_eth_get_settings_phy(mp, cmd);
1342 else
1343 return mv643xx_eth_get_settings_phyless(mp, cmd);
1344}
1345
10a9948d
LB		 1346static int
1347mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1348{
e5371493 1349 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6 1350
6bdf576e
LB		 1351 if (mp->phy == NULL)
1352 return -EINVAL;
1353
fc32b0e2
LB		 1354 /*
1355 * The MAC does not support 1000baseT_Half.
1356 */
1357 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1358
ed94493f 1359 return phy_ethtool_sset(mp->phy, cmd);
c9df406f 1360}
1da177e4 1361
fc32b0e2
LB		 1362static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1363 struct ethtool_drvinfo *drvinfo)
c9df406f 1364{
e5371493
LB		 1365 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1366 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 1367 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 1368 strncpy(drvinfo->bus_info, "platform", 32);
16820054 1369 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1370}
1da177e4 1371
fc32b0e2 1372static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1373{
e5371493 1374 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1375
6bdf576e
LB		 1376 if (mp->phy == NULL)
1377 return -EINVAL;
1da177e4 1378
6bdf576e 1379 return genphy_restart_aneg(mp->phy);
bedfe324
LB		 1380}
1381
c9df406f
LB		 1382static u32 mv643xx_eth_get_link(struct net_device *dev)
1383{
ed94493f 1384 return !!netif_carrier_ok(dev);
bedfe324
LB		 1385}
1386
fc32b0e2
LB		 1387static void mv643xx_eth_get_strings(struct net_device *dev,
1388 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1389{
1390 int i;
1da177e4 1391
fc32b0e2
LB		 1392 if (stringset == ETH_SS_STATS) {
1393 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1394 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1395 mv643xx_eth_stats[i].stat_string,
e5371493 1396 ETH_GSTRING_LEN);
c9df406f 1397 }
c9df406f
LB		 1398 }
1399}
1da177e4 1400
fc32b0e2
LB		 1401static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1402 struct ethtool_stats *stats,
1403 uint64_t *data)
c9df406f 1404{
b9873841 1405 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1406 int i;
1da177e4 1407
8fd89211 1408 mv643xx_eth_get_stats(dev);
fc32b0e2 1409 mib_counters_update(mp);
1da177e4 1410
16820054
LB		 1411 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1412 const struct mv643xx_eth_stats *stat;
1413 void *p;
1414
1415 stat = mv643xx_eth_stats + i;
1416
1417 if (stat->netdev_off >= 0)
1418 p = ((void *)mp->dev) + stat->netdev_off;
1419 else
1420 p = ((void *)mp) + stat->mp_off;
1421
1422 data[i] = (stat->sizeof_stat == 8) ?
1423 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1424 }
c9df406f 1425}
1da177e4 1426
fc32b0e2 1427static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1428{
fc32b0e2 1429 if (sset == ETH_SS_STATS)
16820054 1430 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1431
1432 return -EOPNOTSUPP;
c9df406f 1433}
1da177e4 1434
e5371493 1435static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1436 .get_settings = mv643xx_eth_get_settings,
1437 .set_settings = mv643xx_eth_set_settings,
1438 .get_drvinfo = mv643xx_eth_get_drvinfo,
1439 .nway_reset = mv643xx_eth_nway_reset,
1440 .get_link = mv643xx_eth_get_link,
c9df406f 1441 .set_sg = ethtool_op_set_sg,
fc32b0e2
LB		 1442 .get_strings = mv643xx_eth_get_strings,
1443 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
e5371493 1444 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1445};
1da177e4 1446
bea3348e 1447
c9df406f 1448/* address handling *********************************************************/
5daffe94 1449static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1450{
66e63ffb
LB		 1451 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1452 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1da177e4 1453
5daffe94
LB		 1454 addr[0] = (mac_h >> 24) & 0xff;
1455 addr[1] = (mac_h >> 16) & 0xff;
1456 addr[2] = (mac_h >> 8) & 0xff;
1457 addr[3] = mac_h & 0xff;
1458 addr[4] = (mac_l >> 8) & 0xff;
1459 addr[5] = mac_l & 0xff;
c9df406f 1460}
1da177e4 1461
66e63ffb 1462static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1463{
66e63ffb
LB		 1464 wrlp(mp, MAC_ADDR_HIGH,
1465 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1466 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
c9df406f 1467}
d0412d96 1468
66e63ffb 1469static u32 uc_addr_filter_mask(struct net_device *dev)
c9df406f 1470{
66e63ffb
LB		 1471 struct dev_addr_list *uc_ptr;
1472 u32 nibbles;
1da177e4 1473
66e63ffb
LB		 1474 if (dev->flags & IFF_PROMISC)
1475 return 0;
1da177e4 1476
66e63ffb
LB		 1477 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1478 for (uc_ptr = dev->uc_list; uc_ptr != NULL; uc_ptr = uc_ptr->next) {
1479 if (memcmp(dev->dev_addr, uc_ptr->da_addr, 5))
1480 return 0;
1481 if ((dev->dev_addr[5] ^ uc_ptr->da_addr[5]) & 0xf0)
1482 return 0;
ff561eef 1483
66e63ffb
LB		 1484 nibbles |= 1 << (uc_ptr->da_addr[5] & 0x0f);
1485 }
1da177e4 1486
66e63ffb 1487 return nibbles;
1da177e4
LT		 1488}
1489
66e63ffb 1490static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1da177e4 1491{
e5371493 1492 struct mv643xx_eth_private *mp = netdev_priv(dev);
66e63ffb
LB		 1493 u32 port_config;
1494 u32 nibbles;
1495 int i;
1da177e4 1496
cc9754b3 1497 uc_addr_set(mp, dev->dev_addr);
1da177e4 1498
66e63ffb
LB		 1499 port_config = rdlp(mp, PORT_CONFIG);
1500 nibbles = uc_addr_filter_mask(dev);
1501 if (!nibbles) {
1502 port_config |= UNICAST_PROMISCUOUS_MODE;
1503 wrlp(mp, PORT_CONFIG, port_config);
1504 return;
1505 }
1506
1507 for (i = 0; i < 16; i += 4) {
1508 int off = UNICAST_TABLE(mp->port_num) + i;
1509 u32 v;
1510
1511 v = 0;
1512 if (nibbles & 1)
1513 v |= 0x00000001;
1514 if (nibbles & 2)
1515 v |= 0x00000100;
1516 if (nibbles & 4)
1517 v |= 0x00010000;
1518 if (nibbles & 8)
1519 v |= 0x01000000;
1520 nibbles >>= 4;
1521
1522 wrl(mp, off, v);
1523 }
1524
1525 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1526 wrlp(mp, PORT_CONFIG, port_config);
1da177e4
LT		 1527}
1528
69876569
LB		 1529static int addr_crc(unsigned char *addr)
1530{
1531 int crc = 0;
1532 int i;
1533
1534 for (i = 0; i < 6; i++) {
1535 int j;
1536
1537 crc = (crc ^ addr[i]) << 8;
1538 for (j = 7; j >= 0; j--) {
1539 if (crc & (0x100 << j))
1540 crc ^= 0x107 << j;
1541 }
1542 }
1543
1544 return crc;
1545}
1546
66e63ffb 1547static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1da177e4 1548{
fc32b0e2 1549 struct mv643xx_eth_private *mp = netdev_priv(dev);
66e63ffb
LB		 1550 u32 *mc_spec;
1551 u32 *mc_other;
fc32b0e2
LB		 1552 struct dev_addr_list *addr;
1553 int i;
c8aaea25 1554
fc32b0e2 1555 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
66e63ffb
LB		 1556 int port_num;
1557 u32 accept;
1558 int i;
c8aaea25 1559
66e63ffb
LB		 1560oom:
1561 port_num = mp->port_num;
1562 accept = 0x01010101;
fc32b0e2
LB		 1563 for (i = 0; i < 0x100; i += 4) {
1564 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1565 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1566 }
1567 return;
1568 }
c8aaea25 1569
66e63ffb
LB		 1570 mc_spec = kmalloc(0x200, GFP_KERNEL);
1571 if (mc_spec == NULL)
1572 goto oom;
1573 mc_other = mc_spec + (0x100 >> 2);
1574
1575 memset(mc_spec, 0, 0x100);
1576 memset(mc_other, 0, 0x100);
1da177e4 1577
fc32b0e2
LB		 1578 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1579 u8 *a = addr->da_addr;
66e63ffb
LB		 1580 u32 *table;
1581 int entry;
1da177e4 1582
fc32b0e2 1583 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
66e63ffb
LB		 1584 table = mc_spec;
1585 entry = a[5];
fc32b0e2 1586 } else {
66e63ffb
LB		 1587 table = mc_other;
1588 entry = addr_crc(a);
fc32b0e2 1589 }
66e63ffb 1590
2b448334 1591 table[entry >> 2] |= 1 << (8 * (entry & 3));
fc32b0e2 1592 }
66e63ffb
LB		 1593
1594 for (i = 0; i < 0x100; i += 4) {
1595 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1596 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1597 }
1598
1599 kfree(mc_spec);
1600}
1601
1602static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1603{
1604 mv643xx_eth_program_unicast_filter(dev);
1605 mv643xx_eth_program_multicast_filter(dev);
1606}
1607
1608static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1609{
1610 struct sockaddr *sa = addr;
1611
1612 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1613
1614 netif_addr_lock_bh(dev);
1615 mv643xx_eth_program_unicast_filter(dev);
1616 netif_addr_unlock_bh(dev);
1617
1618 return 0;
c9df406f 1619}
c8aaea25 1620
c8aaea25 1621
c9df406f 1622/* rx/tx queue initialisation ***********************************************/
64da80a2 1623static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1624{
64da80a2 1625 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1626 struct rx_desc *rx_desc;
1627 int size;
c9df406f
LB		 1628 int i;
1629
64da80a2
LB		 1630 rxq->index = index;
1631
8a578111
LB		 1632 rxq->rx_ring_size = mp->default_rx_ring_size;
1633
1634 rxq->rx_desc_count = 0;
1635 rxq->rx_curr_desc = 0;
1636 rxq->rx_used_desc = 0;
1637
1638 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1639
f7981c1c 1640 if (index == 0 && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1641 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1642 mp->rx_desc_sram_size);
1643 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1644 } else {
1645 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1646 &rxq->rx_desc_dma,
1647 GFP_KERNEL);
f7ea3337
PJ		 1648 }
1649
8a578111
LB		 1650 if (rxq->rx_desc_area == NULL) {
1651 dev_printk(KERN_ERR, &mp->dev->dev,
1652 "can't allocate rx ring (%d bytes)\n", size);
1653 goto out;
1654 }
1655 memset(rxq->rx_desc_area, 0, size);
1da177e4 1656
8a578111
LB		 1657 rxq->rx_desc_area_size = size;
1658 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1659 GFP_KERNEL);
1660 if (rxq->rx_skb == NULL) {
1661 dev_printk(KERN_ERR, &mp->dev->dev,
1662 "can't allocate rx skb ring\n");
1663 goto out_free;
1664 }
1665
1666 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1667 for (i = 0; i < rxq->rx_ring_size; i++) {
9da78745
LB		 1668 int nexti;
1669
1670 nexti = i + 1;
1671 if (nexti == rxq->rx_ring_size)
1672 nexti = 0;
1673
8a578111
LB		 1674 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1675 nexti * sizeof(struct rx_desc);
1676 }
1677
8a578111
LB		 1678 return 0;
1679
1680
1681out_free:
f7981c1c 1682 if (index == 0 && size <= mp->rx_desc_sram_size)
8a578111
LB		 1683 iounmap(rxq->rx_desc_area);
1684 else
1685 dma_free_coherent(NULL, size,
1686 rxq->rx_desc_area,
1687 rxq->rx_desc_dma);
1688
1689out:
1690 return -ENOMEM;
c9df406f 1691}
c8aaea25 1692
8a578111 1693static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1694{
8a578111
LB		 1695 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1696 int i;
1697
1698 rxq_disable(rxq);
c8aaea25 1699
8a578111
LB		 1700 for (i = 0; i < rxq->rx_ring_size; i++) {
1701 if (rxq->rx_skb[i]) {
1702 dev_kfree_skb(rxq->rx_skb[i]);
1703 rxq->rx_desc_count--;
1da177e4 1704 }
c8aaea25 1705 }
1da177e4 1706
8a578111
LB		 1707 if (rxq->rx_desc_count) {
1708 dev_printk(KERN_ERR, &mp->dev->dev,
1709 "error freeing rx ring -- %d skbs stuck\n",
1710 rxq->rx_desc_count);
1711 }
1712
f7981c1c 1713 if (rxq->index == 0 &&
64da80a2 1714 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1715 iounmap(rxq->rx_desc_area);
c9df406f 1716 else
8a578111
LB		 1717 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1718 rxq->rx_desc_area, rxq->rx_desc_dma);
1719
1720 kfree(rxq->rx_skb);
c9df406f 1721}
1da177e4 1722
3d6b35bc 1723static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1724{
3d6b35bc 1725 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1726 struct tx_desc *tx_desc;
1727 int size;
c9df406f 1728 int i;
1da177e4 1729
3d6b35bc
LB		 1730 txq->index = index;
1731
13d64285
LB		 1732 txq->tx_ring_size = mp->default_tx_ring_size;
1733
1734 txq->tx_desc_count = 0;
1735 txq->tx_curr_desc = 0;
1736 txq->tx_used_desc = 0;
1737
1738 size = txq->tx_ring_size * sizeof(struct tx_desc);
1739
f7981c1c 1740 if (index == 0 && size <= mp->tx_desc_sram_size) {
13d64285
LB		 1741 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1742 mp->tx_desc_sram_size);
1743 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1744 } else {
1745 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1746 &txq->tx_desc_dma,
1747 GFP_KERNEL);
1748 }
1749
1750 if (txq->tx_desc_area == NULL) {
1751 dev_printk(KERN_ERR, &mp->dev->dev,
1752 "can't allocate tx ring (%d bytes)\n", size);
99ab08e0 1753 return -ENOMEM;
c9df406f 1754 }
13d64285
LB		 1755 memset(txq->tx_desc_area, 0, size);
1756
1757 txq->tx_desc_area_size = size;
13d64285
LB		 1758
1759 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1760 for (i = 0; i < txq->tx_ring_size; i++) {
6b368f68 1761 struct tx_desc *txd = tx_desc + i;
9da78745
LB		 1762 int nexti;
1763
1764 nexti = i + 1;
1765 if (nexti == txq->tx_ring_size)
1766 nexti = 0;
6b368f68
LB		 1767
1768 txd->cmd_sts = 0;
1769 txd->next_desc_ptr = txq->tx_desc_dma +
13d64285
LB		 1770 nexti * sizeof(struct tx_desc);
1771 }
1772
99ab08e0 1773 skb_queue_head_init(&txq->tx_skb);
c9df406f 1774
99ab08e0 1775 return 0;
c8aaea25 1776}
1da177e4 1777
13d64285 1778static void txq_deinit(struct tx_queue *txq)
c9df406f 1779{
13d64285 1780 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 1781
13d64285 1782 txq_disable(txq);
1fa38c58 1783 txq_reclaim(txq, txq->tx_ring_size, 1);
1da177e4 1784
13d64285 1785 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 1786
f7981c1c 1787 if (txq->index == 0 &&
3d6b35bc 1788 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 1789 iounmap(txq->tx_desc_area);
c9df406f 1790 else
13d64285
LB		 1791 dma_free_coherent(NULL, txq->tx_desc_area_size,
1792 txq->tx_desc_area, txq->tx_desc_dma);
c9df406f 1793}
1da177e4 1794
1da177e4 1795
c9df406f 1796/* netdev ops and related ***************************************************/
1fa38c58
LB		 1797static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1798{
1799 u32 int_cause;
1800 u32 int_cause_ext;
1801
37a6084f 1802 int_cause = rdlp(mp, INT_CAUSE) & (INT_TX_END | INT_RX | INT_EXT);
1fa38c58
LB		 1803 if (int_cause == 0)
1804 return 0;
1805
1806 int_cause_ext = 0;
1807 if (int_cause & INT_EXT)
37a6084f 1808 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
1fa38c58
LB		 1809
1810 int_cause &= INT_TX_END | INT_RX;
1811 if (int_cause) {
37a6084f 1812 wrlp(mp, INT_CAUSE, ~int_cause);
1fa38c58 1813 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
37a6084f 1814 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
1fa38c58
LB		 1815 mp->work_rx |= (int_cause & INT_RX) >> 2;
1816 }
1817
1818 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
1819 if (int_cause_ext) {
37a6084f 1820 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
1fa38c58
LB		 1821 if (int_cause_ext & INT_EXT_LINK_PHY)
1822 mp->work_link = 1;
1823 mp->work_tx |= int_cause_ext & INT_EXT_TX;
1824 }
1825
1826 return 1;
1827}
1828
1829static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1830{
1831 struct net_device *dev = (struct net_device *)dev_id;
1832 struct mv643xx_eth_private *mp = netdev_priv(dev);
1833
1834 if (unlikely(!mv643xx_eth_collect_events(mp)))
1835 return IRQ_NONE;
1836
37a6084f 1837 wrlp(mp, INT_MASK, 0);
1fa38c58
LB		 1838 napi_schedule(&mp->napi);
1839
1840 return IRQ_HANDLED;
1841}
1842
2f7eb47a
LB		 1843static void handle_link_event(struct mv643xx_eth_private *mp)
1844{
1845 struct net_device *dev = mp->dev;
1846 u32 port_status;
1847 int speed;
1848 int duplex;
1849 int fc;
1850
37a6084f 1851 port_status = rdlp(mp, PORT_STATUS);
2f7eb47a
LB		 1852 if (!(port_status & LINK_UP)) {
1853 if (netif_carrier_ok(dev)) {
1854 int i;
1855
1856 printk(KERN_INFO "%s: link down\n", dev->name);
1857
1858 netif_carrier_off(dev);
2f7eb47a 1859
f7981c1c 1860 for (i = 0; i < mp->txq_count; i++) {
2f7eb47a
LB		 1861 struct tx_queue *txq = mp->txq + i;
1862
1fa38c58 1863 txq_reclaim(txq, txq->tx_ring_size, 1);
f7981c1c 1864 txq_reset_hw_ptr(txq);
2f7eb47a
LB		 1865 }
1866 }
1867 return;
1868 }
1869
1870 switch (port_status & PORT_SPEED_MASK) {
1871 case PORT_SPEED_10:
1872 speed = 10;
1873 break;
1874 case PORT_SPEED_100:
1875 speed = 100;
1876 break;
1877 case PORT_SPEED_1000:
1878 speed = 1000;
1879 break;
1880 default:
1881 speed = -1;
1882 break;
1883 }
1884 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1885 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1886
1887 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1888 "flow control %sabled\n", dev->name,
1889 speed, duplex ? "full" : "half",
1890 fc ? "en" : "dis");
1891
4fdeca3f 1892 if (!netif_carrier_ok(dev))
2f7eb47a 1893 netif_carrier_on(dev);
2f7eb47a
LB		 1894}
1895
1fa38c58 1896static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
c9df406f 1897{
1fa38c58
LB		 1898 struct mv643xx_eth_private *mp;
1899 int work_done;
ce4e2e45 1900
1fa38c58 1901 mp = container_of(napi, struct mv643xx_eth_private, napi);
fc32b0e2 1902
1fa38c58
LB		 1903 mp->work_rx_refill |= mp->work_rx_oom;
1904 mp->work_rx_oom = 0;
1da177e4 1905
1fa38c58
LB		 1906 work_done = 0;
1907 while (work_done < budget) {
1908 u8 queue_mask;
1909 int queue;
1910 int work_tbd;
1911
1912 if (mp->work_link) {
1913 mp->work_link = 0;
1914 handle_link_event(mp);
1915 continue;
1916 }
1da177e4 1917
1fa38c58
LB		 1918 queue_mask = mp->work_tx | mp->work_tx_end |
1919 mp->work_rx | mp->work_rx_refill;
1920 if (!queue_mask) {
1921 if (mv643xx_eth_collect_events(mp))
1922 continue;
1923 break;
1924 }
1da177e4 1925
1fa38c58
LB		 1926 queue = fls(queue_mask) - 1;
1927 queue_mask = 1 << queue;
1928
1929 work_tbd = budget - work_done;
1930 if (work_tbd > 16)
1931 work_tbd = 16;
1932
1933 if (mp->work_tx_end & queue_mask) {
1934 txq_kick(mp->txq + queue);
1935 } else if (mp->work_tx & queue_mask) {
1936 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
1937 txq_maybe_wake(mp->txq + queue);
1938 } else if (mp->work_rx & queue_mask) {
1939 work_done += rxq_process(mp->rxq + queue, work_tbd);
1940 } else if (mp->work_rx_refill & queue_mask) {
1941 work_done += rxq_refill(mp->rxq + queue, work_tbd);
1942 } else {
1943 BUG();
1944 }
84dd619e 1945 }
fc32b0e2 1946
1fa38c58
LB		 1947 if (work_done < budget) {
1948 if (mp->work_rx_oom)
1949 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
1950 napi_complete(napi);
37a6084f 1951 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
226bb6b7 1952 }
3d6b35bc 1953
1fa38c58
LB		 1954 return work_done;
1955}
8fa89bf5 1956
1fa38c58
LB		 1957static inline void oom_timer_wrapper(unsigned long data)
1958{
1959 struct mv643xx_eth_private *mp = (void *)data;
1da177e4 1960
1fa38c58 1961 napi_schedule(&mp->napi);
1da177e4
LT		 1962}
1963
e5371493 1964static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 1965{
45c5d3bc
LB		 1966 int data;
1967
ed94493f 1968 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc
LB		 1969 if (data < 0)
1970 return;
1da177e4 1971
7f106c1d 1972 data |= BMCR_RESET;
ed94493f 1973 if (phy_write(mp->phy, MII_BMCR, data) < 0)
45c5d3bc 1974 return;
1da177e4 1975
c9df406f 1976 do {
ed94493f 1977 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc 1978 } while (data >= 0 && data & BMCR_RESET);
1da177e4
LT		 1979}
1980
fc32b0e2 1981static void port_start(struct mv643xx_eth_private *mp)
1da177e4 1982{
d0412d96 1983 u32 pscr;
8a578111 1984 int i;
1da177e4 1985
bedfe324
LB		 1986 /*
1987 * Perform PHY reset, if there is a PHY.
1988 */
ed94493f 1989 if (mp->phy != NULL) {
bedfe324
LB		 1990 struct ethtool_cmd cmd;
1991
1992 mv643xx_eth_get_settings(mp->dev, &cmd);
1993 phy_reset(mp);
1994 mv643xx_eth_set_settings(mp->dev, &cmd);
1995 }
1da177e4 1996
81600eea
LB		 1997 /*
1998 * Configure basic link parameters.
1999 */
37a6084f 2000 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 2001
2002 pscr |= SERIAL_PORT_ENABLE;
37a6084f 2003 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2004
2005 pscr |= DO_NOT_FORCE_LINK_FAIL;
ed94493f 2006 if (mp->phy == NULL)
81600eea 2007 pscr |= FORCE_LINK_PASS;
37a6084f 2008 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea 2009
37a6084f 2010 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
81600eea 2011
13d64285
LB		 2012 /*
2013 * Configure TX path and queues.
2014 */
89df5fdc 2015 tx_set_rate(mp, 1000000000, 16777216);
f7981c1c 2016 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc 2017 struct tx_queue *txq = mp->txq + i;
13d64285 2018
6b368f68 2019 txq_reset_hw_ptr(txq);
89df5fdc
LB		 2020 txq_set_rate(txq, 1000000000, 16777216);
2021 txq_set_fixed_prio_mode(txq);
13d64285
LB		 2022 }
2023
fc32b0e2
LB		 2024 /*
2025 * Add configured unicast address to address filter table.
2026 */
66e63ffb 2027 mv643xx_eth_program_unicast_filter(mp->dev);
1da177e4 2028
d9a073ea
LB		 2029 /*
2030 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
170e7108
LB		 2031 * frames to RX queue #0, and include the pseudo-header when
2032 * calculating receive checksums.
d9a073ea 2033 */
37a6084f 2034 wrlp(mp, PORT_CONFIG, 0x02000000);
01999873 2035
376489a2
LB		 2036 /*
2037 * Treat BPDUs as normal multicasts, and disable partition mode.
2038 */
37a6084f 2039 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
01999873 2040
8a578111 2041 /*
64da80a2 2042 * Enable the receive queues.
8a578111 2043 */
f7981c1c 2044 for (i = 0; i < mp->rxq_count; i++) {
64da80a2 2045 struct rx_queue *rxq = mp->rxq + i;
8a578111 2046 u32 addr;
1da177e4 2047
8a578111
LB		 2048 addr = (u32)rxq->rx_desc_dma;
2049 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
37a6084f 2050 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
1da177e4 2051
8a578111
LB		 2052 rxq_enable(rxq);
2053 }
1da177e4
LT		 2054}
2055
ffd86bbe 2056static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 2057{
c9df406f 2058 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
773fc3ee 2059 u32 val;
1da177e4 2060
37a6084f 2061 val = rdlp(mp, SDMA_CONFIG);
773fc3ee
LB		 2062 if (mp->shared->extended_rx_coal_limit) {
2063 if (coal > 0xffff)
2064 coal = 0xffff;
2065 val &= ~0x023fff80;
2066 val |= (coal & 0x8000) << 10;
2067 val |= (coal & 0x7fff) << 7;
2068 } else {
2069 if (coal > 0x3fff)
2070 coal = 0x3fff;
2071 val &= ~0x003fff00;
2072 val |= (coal & 0x3fff) << 8;
2073 }
37a6084f 2074 wrlp(mp, SDMA_CONFIG, val);
1da177e4
LT		 2075}
2076
ffd86bbe 2077static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 2078{
c9df406f 2079 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 2080
fc32b0e2
LB		 2081 if (coal > 0x3fff)
2082 coal = 0x3fff;
37a6084f 2083 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, (coal & 0x3fff) << 4);
16e03018
DF		 2084}
2085
2bcb4b0f
LB		 2086static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2087{
2088 int skb_size;
2089
2090 /*
2091 * Reserve 2+14 bytes for an ethernet header (the hardware
2092 * automatically prepends 2 bytes of dummy data to each
2093 * received packet), 16 bytes for up to four VLAN tags, and
2094 * 4 bytes for the trailing FCS -- 36 bytes total.
2095 */
2096 skb_size = mp->dev->mtu + 36;
2097
2098 /*
2099 * Make sure that the skb size is a multiple of 8 bytes, as
2100 * the lower three bits of the receive descriptor's buffer
2101 * size field are ignored by the hardware.
2102 */
2103 mp->skb_size = (skb_size + 7) & ~7;
2104}
2105
c9df406f 2106static int mv643xx_eth_open(struct net_device *dev)
16e03018 2107{
e5371493 2108 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2109 int err;
64da80a2 2110 int i;
16e03018 2111
37a6084f
LB		 2112 wrlp(mp, INT_CAUSE, 0);
2113 wrlp(mp, INT_CAUSE_EXT, 0);
2114 rdlp(mp, INT_CAUSE_EXT);
c9df406f 2115
fc32b0e2 2116 err = request_irq(dev->irq, mv643xx_eth_irq,
2a1867a7 2117 IRQF_SHARED, dev->name, dev);
c9df406f 2118 if (err) {
fc32b0e2 2119 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
c9df406f 2120 return -EAGAIN;
16e03018
DF		 2121 }
2122
2bcb4b0f
LB		 2123 mv643xx_eth_recalc_skb_size(mp);
2124
2257e05c
LB		 2125 napi_enable(&mp->napi);
2126
2bcb4b0f
LB		 2127 skb_queue_head_init(&mp->rx_recycle);
2128
f7981c1c 2129 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 2130 err = rxq_init(mp, i);
2131 if (err) {
2132 while (--i >= 0)
f7981c1c 2133 rxq_deinit(mp->rxq + i);
64da80a2
LB		 2134 goto out;
2135 }
2136
1fa38c58 2137 rxq_refill(mp->rxq + i, INT_MAX);
2257e05c
LB		 2138 }
2139
1fa38c58 2140 if (mp->work_rx_oom) {
2257e05c
LB		 2141 mp->rx_oom.expires = jiffies + (HZ / 10);
2142 add_timer(&mp->rx_oom);
64da80a2 2143 }
8a578111 2144
f7981c1c 2145 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc
LB		 2146 err = txq_init(mp, i);
2147 if (err) {
2148 while (--i >= 0)
f7981c1c 2149 txq_deinit(mp->txq + i);
3d6b35bc
LB		 2150 goto out_free;
2151 }
2152 }
16e03018 2153
2f7eb47a 2154 netif_carrier_off(dev);
2f7eb47a 2155
fc32b0e2 2156 port_start(mp);
16e03018 2157
ffd86bbe
LB		 2158 set_rx_coal(mp, 0);
2159 set_tx_coal(mp, 0);
16e03018 2160
37a6084f
LB		 2161 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2162 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
16e03018 2163
c9df406f
LB		 2164 return 0;
2165
13d64285 2166
fc32b0e2 2167out_free:
f7981c1c
LB		 2168 for (i = 0; i < mp->rxq_count; i++)
2169 rxq_deinit(mp->rxq + i);
fc32b0e2 2170out:
c9df406f
LB		 2171 free_irq(dev->irq, dev);
2172
2173 return err;
16e03018
DF		 2174}
2175
e5371493 2176static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 2177{
fc32b0e2 2178 unsigned int data;
64da80a2 2179 int i;
1da177e4 2180
f7981c1c
LB		 2181 for (i = 0; i < mp->rxq_count; i++)
2182 rxq_disable(mp->rxq + i);
2183 for (i = 0; i < mp->txq_count; i++)
2184 txq_disable(mp->txq + i);
ae9ae064
LB		 2185
2186 while (1) {
37a6084f 2187 u32 ps = rdlp(mp, PORT_STATUS);
ae9ae064
LB		 2188
2189 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2190 break;
13d64285 2191 udelay(10);
ae9ae064 2192 }
1da177e4 2193
c9df406f 2194 /* Reset the Enable bit in the Configuration Register */
37a6084f 2195 data = rdlp(mp, PORT_SERIAL_CONTROL);
fc32b0e2
LB		 2196 data &= ~(SERIAL_PORT_ENABLE |
2197 DO_NOT_FORCE_LINK_FAIL |
2198 FORCE_LINK_PASS);
37a6084f 2199 wrlp(mp, PORT_SERIAL_CONTROL, data);
1da177e4
LT		 2200}
2201
c9df406f 2202static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 2203{
e5371493 2204 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 2205 int i;
1da177e4 2206
fe65e704 2207 wrlp(mp, INT_MASK_EXT, 0x00000000);
37a6084f
LB		 2208 wrlp(mp, INT_MASK, 0x00000000);
2209 rdlp(mp, INT_MASK);
1da177e4 2210
4ff3495a
LB		 2211 del_timer_sync(&mp->mib_counters_timer);
2212
c9df406f 2213 napi_disable(&mp->napi);
78fff83b 2214
2257e05c
LB		 2215 del_timer_sync(&mp->rx_oom);
2216
c9df406f 2217 netif_carrier_off(dev);
1da177e4 2218
fc32b0e2
LB		 2219 free_irq(dev->irq, dev);
2220
cc9754b3 2221 port_reset(mp);
8fd89211 2222 mv643xx_eth_get_stats(dev);
fc32b0e2 2223 mib_counters_update(mp);
1da177e4 2224
2bcb4b0f
LB		 2225 skb_queue_purge(&mp->rx_recycle);
2226
f7981c1c
LB		 2227 for (i = 0; i < mp->rxq_count; i++)
2228 rxq_deinit(mp->rxq + i);
2229 for (i = 0; i < mp->txq_count; i++)
2230 txq_deinit(mp->txq + i);
1da177e4 2231
c9df406f 2232 return 0;
1da177e4
LT		 2233}
2234
fc32b0e2 2235static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 2236{
e5371493 2237 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2238
ed94493f
LB		 2239 if (mp->phy != NULL)
2240 return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd);
bedfe324
LB		 2241
2242 return -EOPNOTSUPP;
1da177e4
LT		 2243}
2244
c9df406f 2245static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 2246{
89df5fdc
LB		 2247 struct mv643xx_eth_private *mp = netdev_priv(dev);
2248
fc32b0e2 2249 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 2250 return -EINVAL;
1da177e4 2251
c9df406f 2252 dev->mtu = new_mtu;
2bcb4b0f 2253 mv643xx_eth_recalc_skb_size(mp);
89df5fdc
LB		 2254 tx_set_rate(mp, 1000000000, 16777216);
2255
c9df406f
LB		 2256 if (!netif_running(dev))
2257 return 0;
1da177e4 2258
c9df406f
LB		 2259 /*
2260 * Stop and then re-open the interface. This will allocate RX
2261 * skbs of the new MTU.
2262 * There is a possible danger that the open will not succeed,
fc32b0e2 2263 * due to memory being full.
c9df406f
LB		 2264 */
2265 mv643xx_eth_stop(dev);
2266 if (mv643xx_eth_open(dev)) {
fc32b0e2
LB		 2267 dev_printk(KERN_ERR, &dev->dev,
2268 "fatal error on re-opening device after "
2269 "MTU change\n");
c9df406f
LB		 2270 }
2271
2272 return 0;
1da177e4
LT		 2273}
2274
fc32b0e2 2275static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2276{
fc32b0e2 2277 struct mv643xx_eth_private *mp;
1da177e4 2278
fc32b0e2
LB		 2279 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2280 if (netif_running(mp->dev)) {
e5ef1de1 2281 netif_tx_stop_all_queues(mp->dev);
fc32b0e2
LB		 2282 port_reset(mp);
2283 port_start(mp);
e5ef1de1 2284 netif_tx_wake_all_queues(mp->dev);
fc32b0e2 2285 }
c9df406f
LB		 2286}
2287
c9df406f 2288static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2289{
e5371493 2290 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2291
fc32b0e2 2292 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
d0412d96 2293
c9df406f 2294 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2295}
2296
c9df406f 2297#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2298static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2299{
fc32b0e2 2300 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2301
37a6084f
LB		 2302 wrlp(mp, INT_MASK, 0x00000000);
2303 rdlp(mp, INT_MASK);
c9df406f 2304
fc32b0e2 2305 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2306
37a6084f 2307 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
9f8dd319 2308}
c9df406f 2309#endif
9f8dd319 2310
9f8dd319 2311
c9df406f 2312/* platform glue ************************************************************/
e5371493
LB		 2313static void
2314mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2315 struct mbus_dram_target_info *dram)
c9df406f 2316{
cc9754b3 2317 void __iomem *base = msp->base;
c9df406f
LB		 2318 u32 win_enable;
2319 u32 win_protect;
2320 int i;
9f8dd319 2321
c9df406f
LB		 2322 for (i = 0; i < 6; i++) {
2323 writel(0, base + WINDOW_BASE(i));
2324 writel(0, base + WINDOW_SIZE(i));
2325 if (i < 4)
2326 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2327 }
2328
c9df406f
LB		 2329 win_enable = 0x3f;
2330 win_protect = 0;
2331
2332 for (i = 0; i < dram->num_cs; i++) {
2333 struct mbus_dram_window *cs = dram->cs + i;
2334
2335 writel((cs->base & 0xffff0000) |
2336 (cs->mbus_attr << 8) |
2337 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2338 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2339
2340 win_enable &= ~(1 << i);
2341 win_protect |= 3 << (2 * i);
2342 }
2343
2344 writel(win_enable, base + WINDOW_BAR_ENABLE);
2345 msp->win_protect = win_protect;
9f8dd319
DF		 2346}
2347
773fc3ee
LB		 2348static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2349{
2350 /*
2351 * Check whether we have a 14-bit coal limit field in bits
2352 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2353 * SDMA config register.
2354 */
37a6084f
LB		 2355 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2356 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
773fc3ee
LB		 2357 msp->extended_rx_coal_limit = 1;
2358 else
2359 msp->extended_rx_coal_limit = 0;
1e881592
LB		 2360
2361 /*
457b1d5a
LB		 2362 * Check whether the MAC supports TX rate control, and if
2363 * yes, whether its associated registers are in the old or
2364 * the new place.
1e881592 2365 */
37a6084f
LB		 2366 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2367 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
457b1d5a
LB		 2368 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2369 } else {
37a6084f
LB		 2370 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2371 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
457b1d5a
LB		 2372 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2373 else
2374 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2375 }
773fc3ee
LB		 2376}
2377
c9df406f 2378static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2379{
10a9948d 2380 static int mv643xx_eth_version_printed;
c9df406f 2381 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2382 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 2383 struct resource *res;
2384 int ret;
9f8dd319 2385
e5371493 2386 if (!mv643xx_eth_version_printed++)
7dde154d
LB		 2387 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2388 "driver version %s\n", mv643xx_eth_driver_version);
9f8dd319 2389
c9df406f
LB		 2390 ret = -EINVAL;
2391 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2392 if (res == NULL)
2393 goto out;
9f8dd319 2394
c9df406f
LB		 2395 ret = -ENOMEM;
2396 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2397 if (msp == NULL)
2398 goto out;
2399 memset(msp, 0, sizeof(*msp));
2400
cc9754b3
LB		 2401 msp->base = ioremap(res->start, res->end - res->start + 1);
2402 if (msp->base == NULL)
c9df406f
LB		 2403 goto out_free;
2404
ed94493f
LB		 2405 /*
2406 * Set up and register SMI bus.
2407 */
2408 if (pd == NULL || pd->shared_smi == NULL) {
298cf9be
LB		 2409 msp->smi_bus = mdiobus_alloc();
2410 if (msp->smi_bus == NULL)
ed94493f 2411 goto out_unmap;
298cf9be
LB		 2412
2413 msp->smi_bus->priv = msp;
2414 msp->smi_bus->name = "mv643xx_eth smi";
2415 msp->smi_bus->read = smi_bus_read;
2416 msp->smi_bus->write = smi_bus_write,
2417 snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
2418 msp->smi_bus->parent = &pdev->dev;
2419 msp->smi_bus->phy_mask = 0xffffffff;
2420 if (mdiobus_register(msp->smi_bus) < 0)
2421 goto out_free_mii_bus;
ed94493f
LB		 2422 msp->smi = msp;
2423 } else {
fc0eb9f2 2424 msp->smi = platform_get_drvdata(pd->shared_smi);
ed94493f 2425 }
c9df406f 2426
45c5d3bc
LB		 2427 msp->err_interrupt = NO_IRQ;
2428 init_waitqueue_head(&msp->smi_busy_wait);
2429
2430 /*
2431 * Check whether the error interrupt is hooked up.
2432 */
2433 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2434 if (res != NULL) {
2435 int err;
2436
2437 err = request_irq(res->start, mv643xx_eth_err_irq,
2438 IRQF_SHARED, "mv643xx_eth", msp);
2439 if (!err) {
2440 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2441 msp->err_interrupt = res->start;
2442 }
2443 }
2444
c9df406f
LB		 2445 /*
2446 * (Re-)program MBUS remapping windows if we are asked to.
2447 */
2448 if (pd != NULL && pd->dram != NULL)
2449 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2450
fc32b0e2
LB		 2451 /*
2452 * Detect hardware parameters.
2453 */
2454 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
773fc3ee 2455 infer_hw_params(msp);
fc32b0e2
LB		 2456
2457 platform_set_drvdata(pdev, msp);
2458
c9df406f
LB		 2459 return 0;
2460
298cf9be
LB		 2461out_free_mii_bus:
2462 mdiobus_free(msp->smi_bus);
ed94493f
LB		 2463out_unmap:
2464 iounmap(msp->base);
c9df406f
LB		 2465out_free:
2466 kfree(msp);
2467out:
2468 return ret;
2469}
2470
2471static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2472{
e5371493 2473 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
ed94493f 2474 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
c9df406f 2475
298cf9be 2476 if (pd == NULL || pd->shared_smi == NULL) {
298cf9be 2477 mdiobus_unregister(msp->smi_bus);
bcb3336c 2478 mdiobus_free(msp->smi_bus);
298cf9be 2479 }
45c5d3bc
LB		 2480 if (msp->err_interrupt != NO_IRQ)
2481 free_irq(msp->err_interrupt, msp);
cc9754b3 2482 iounmap(msp->base);
c9df406f
LB		 2483 kfree(msp);
2484
2485 return 0;
9f8dd319
DF		 2486}
2487
c9df406f 2488static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2489 .probe = mv643xx_eth_shared_probe,
2490 .remove = mv643xx_eth_shared_remove,
c9df406f 2491 .driver = {
fc32b0e2 2492 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2493 .owner = THIS_MODULE,
2494 },
2495};
2496
e5371493 2497static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2498{
c9df406f 2499 int addr_shift = 5 * mp->port_num;
fc32b0e2 2500 u32 data;
1da177e4 2501
fc32b0e2
LB		 2502 data = rdl(mp, PHY_ADDR);
2503 data &= ~(0x1f << addr_shift);
2504 data |= (phy_addr & 0x1f) << addr_shift;
2505 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2506}
2507
e5371493 2508static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2509{
fc32b0e2
LB		 2510 unsigned int data;
2511
2512 data = rdl(mp, PHY_ADDR);
2513
2514 return (data >> (5 * mp->port_num)) & 0x1f;
2515}
2516
2517static void set_params(struct mv643xx_eth_private *mp,
2518 struct mv643xx_eth_platform_data *pd)
2519{
2520 struct net_device *dev = mp->dev;
2521
2522 if (is_valid_ether_addr(pd->mac_addr))
2523 memcpy(dev->dev_addr, pd->mac_addr, 6);
2524 else
2525 uc_addr_get(mp, dev->dev_addr);
2526
fc32b0e2
LB		 2527 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2528 if (pd->rx_queue_size)
2529 mp->default_rx_ring_size = pd->rx_queue_size;
2530 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2531 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2532
f7981c1c 2533 mp->rxq_count = pd->rx_queue_count ? : 1;
64da80a2 2534
fc32b0e2
LB		 2535 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2536 if (pd->tx_queue_size)
2537 mp->default_tx_ring_size = pd->tx_queue_size;
2538 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2539 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc 2540
f7981c1c 2541 mp->txq_count = pd->tx_queue_count ? : 1;
1da177e4
LT		 2542}
2543
ed94493f
LB		 2544static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2545 int phy_addr)
1da177e4 2546{
298cf9be 2547 struct mii_bus *bus = mp->shared->smi->smi_bus;
ed94493f
LB		 2548 struct phy_device *phydev;
2549 int start;
2550 int num;
2551 int i;
45c5d3bc 2552
ed94493f
LB		 2553 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2554 start = phy_addr_get(mp) & 0x1f;
2555 num = 32;
2556 } else {
2557 start = phy_addr & 0x1f;
2558 num = 1;
2559 }
45c5d3bc 2560
ed94493f
LB		 2561 phydev = NULL;
2562 for (i = 0; i < num; i++) {
2563 int addr = (start + i) & 0x1f;
fc32b0e2 2564
ed94493f
LB		 2565 if (bus->phy_map[addr] == NULL)
2566 mdiobus_scan(bus, addr);
1da177e4 2567
ed94493f
LB		 2568 if (phydev == NULL) {
2569 phydev = bus->phy_map[addr];
2570 if (phydev != NULL)
2571 phy_addr_set(mp, addr);
2572 }
2573 }
1da177e4 2574
ed94493f 2575 return phydev;
1da177e4
LT		 2576}
2577
ed94493f 2578static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
c28a4f89 2579{
ed94493f 2580 struct phy_device *phy = mp->phy;
c28a4f89 2581
fc32b0e2
LB		 2582 phy_reset(mp);
2583
db1d7bf7 2584 phy_attach(mp->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_GMII);
ed94493f
LB		 2585
2586 if (speed == 0) {
2587 phy->autoneg = AUTONEG_ENABLE;
2588 phy->speed = 0;
2589 phy->duplex = 0;
2590 phy->advertising = phy->supported | ADVERTISED_Autoneg;
c9df406f 2591 } else {
ed94493f
LB		 2592 phy->autoneg = AUTONEG_DISABLE;
2593 phy->advertising = 0;
2594 phy->speed = speed;
2595 phy->duplex = duplex;
c9df406f 2596 }
ed94493f 2597 phy_start_aneg(phy);
c28a4f89
JC		 2598}
2599
81600eea
LB		 2600static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2601{
2602 u32 pscr;
2603
37a6084f 2604 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 2605 if (pscr & SERIAL_PORT_ENABLE) {
2606 pscr &= ~SERIAL_PORT_ENABLE;
37a6084f 2607 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2608 }
2609
2610 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
ed94493f 2611 if (mp->phy == NULL) {
81600eea
LB		 2612 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2613 if (speed == SPEED_1000)
2614 pscr |= SET_GMII_SPEED_TO_1000;
2615 else if (speed == SPEED_100)
2616 pscr |= SET_MII_SPEED_TO_100;
2617
2618 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2619
2620 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2621 if (duplex == DUPLEX_FULL)
2622 pscr |= SET_FULL_DUPLEX_MODE;
2623 }
2624
37a6084f 2625 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2626}
2627
c9df406f 2628static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2629{
c9df406f 2630 struct mv643xx_eth_platform_data *pd;
e5371493 2631 struct mv643xx_eth_private *mp;
c9df406f 2632 struct net_device *dev;
c9df406f 2633 struct resource *res;
fc32b0e2 2634 int err;
1da177e4 2635
c9df406f
LB		 2636 pd = pdev->dev.platform_data;
2637 if (pd == NULL) {
fc32b0e2
LB		 2638 dev_printk(KERN_ERR, &pdev->dev,
2639 "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2640 return -ENODEV;
2641 }
1da177e4 2642
c9df406f 2643 if (pd->shared == NULL) {
fc32b0e2
LB		 2644 dev_printk(KERN_ERR, &pdev->dev,
2645 "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2646 return -ENODEV;
2647 }
8f518703 2648
e5ef1de1 2649 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
c9df406f
LB		 2650 if (!dev)
2651 return -ENOMEM;
1da177e4 2652
c9df406f 2653 mp = netdev_priv(dev);
fc32b0e2
LB		 2654 platform_set_drvdata(pdev, mp);
2655
2656 mp->shared = platform_get_drvdata(pd->shared);
37a6084f 2657 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
fc32b0e2
LB		 2658 mp->port_num = pd->port_number;
2659
c9df406f 2660 mp->dev = dev;
78fff83b 2661
fc32b0e2 2662 set_params(mp, pd);
e5ef1de1 2663 dev->real_num_tx_queues = mp->txq_count;
fc32b0e2 2664
ed94493f
LB		 2665 if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2666 mp->phy = phy_scan(mp, pd->phy_addr);
bedfe324 2667
6bdf576e 2668 if (mp->phy != NULL)
ed94493f 2669 phy_init(mp, pd->speed, pd->duplex);
6bdf576e
LB		 2670
2671 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
ed94493f 2672
81600eea 2673 init_pscr(mp, pd->speed, pd->duplex);
fc32b0e2 2674
4ff3495a
LB		 2675
2676 mib_counters_clear(mp);
2677
2678 init_timer(&mp->mib_counters_timer);
2679 mp->mib_counters_timer.data = (unsigned long)mp;
2680 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2681 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2682 add_timer(&mp->mib_counters_timer);
2683
2684 spin_lock_init(&mp->mib_counters_lock);
2685
2686 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2687
2257e05c
LB		 2688 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2689
2690 init_timer(&mp->rx_oom);
2691 mp->rx_oom.data = (unsigned long)mp;
2692 mp->rx_oom.function = oom_timer_wrapper;
2693
fc32b0e2 2694
c9df406f
LB		 2695 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2696 BUG_ON(!res);
2697 dev->irq = res->start;
1da177e4 2698
8fd89211 2699 dev->get_stats = mv643xx_eth_get_stats;
fc32b0e2 2700 dev->hard_start_xmit = mv643xx_eth_xmit;
c9df406f
LB		 2701 dev->open = mv643xx_eth_open;
2702 dev->stop = mv643xx_eth_stop;
66e63ffb 2703 dev->set_rx_mode = mv643xx_eth_set_rx_mode;
fc32b0e2
LB		 2704 dev->set_mac_address = mv643xx_eth_set_mac_address;
2705 dev->do_ioctl = mv643xx_eth_ioctl;
2706 dev->change_mtu = mv643xx_eth_change_mtu;
c9df406f 2707 dev->tx_timeout = mv643xx_eth_tx_timeout;
c9df406f 2708#ifdef CONFIG_NET_POLL_CONTROLLER
e5371493 2709 dev->poll_controller = mv643xx_eth_netpoll;
c9df406f 2710#endif
c9df406f
LB		 2711 dev->watchdog_timeo = 2 * HZ;
2712 dev->base_addr = 0;
1da177e4 2713
c9df406f 2714 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
e32b6617 2715 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4 2716
fc32b0e2 2717 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2718
c9df406f 2719 if (mp->shared->win_protect)
fc32b0e2 2720 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2721
c9df406f
LB		 2722 err = register_netdev(dev);
2723 if (err)
2724 goto out;
1da177e4 2725
e174961c
JB		 2726 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %pM\n",
2727 mp->port_num, dev->dev_addr);
1da177e4 2728
13d64285 2729 if (mp->tx_desc_sram_size > 0)
fc32b0e2 2730 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
1da177e4 2731
c9df406f 2732 return 0;
1da177e4 2733
c9df406f
LB		 2734out:
2735 free_netdev(dev);
1da177e4 2736
c9df406f 2737 return err;
1da177e4
LT		 2738}
2739
c9df406f 2740static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2741{
fc32b0e2 2742 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2743
fc32b0e2 2744 unregister_netdev(mp->dev);
ed94493f
LB		 2745 if (mp->phy != NULL)
2746 phy_detach(mp->phy);
c9df406f 2747 flush_scheduled_work();
fc32b0e2 2748 free_netdev(mp->dev);
c9df406f 2749
c9df406f 2750 platform_set_drvdata(pdev, NULL);
fc32b0e2 2751
c9df406f 2752 return 0;
1da177e4
LT		 2753}
2754
c9df406f 2755static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2756{
fc32b0e2 2757 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 2758
c9df406f 2759 /* Mask all interrupts on ethernet port */
37a6084f
LB		 2760 wrlp(mp, INT_MASK, 0);
2761 rdlp(mp, INT_MASK);
c9df406f 2762
fc32b0e2
LB		 2763 if (netif_running(mp->dev))
2764 port_reset(mp);
d0412d96
JC		 2765}
2766
c9df406f 2767static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 2768 .probe = mv643xx_eth_probe,
2769 .remove = mv643xx_eth_remove,
2770 .shutdown = mv643xx_eth_shutdown,
c9df406f 2771 .driver = {
fc32b0e2 2772 .name = MV643XX_ETH_NAME,
c9df406f
LB		 2773 .owner = THIS_MODULE,
2774 },
2775};
2776
e5371493 2777static int __init mv643xx_eth_init_module(void)
d0412d96 2778{
c9df406f 2779 int rc;
d0412d96 2780
c9df406f
LB		 2781 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2782 if (!rc) {
2783 rc = platform_driver_register(&mv643xx_eth_driver);
2784 if (rc)
2785 platform_driver_unregister(&mv643xx_eth_shared_driver);
2786 }
fc32b0e2 2787
c9df406f 2788 return rc;
d0412d96 2789}
fc32b0e2 2790module_init(mv643xx_eth_init_module);
d0412d96 2791
e5371493 2792static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 2793{
c9df406f
LB		 2794 platform_driver_unregister(&mv643xx_eth_driver);
2795 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 2796}
e5371493 2797module_exit(mv643xx_eth_cleanup_module);
1da177e4 2798
45675bc6
LB		 2799MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2800 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
c9df406f 2801MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 2802MODULE_LICENSE("GPL");
c9df406f 2803MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 2804MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux kernel - Deliverables
This page took 0.703745 seconds and 5 git commands to generate.