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mv643xx_eth: detect extended rx coal register field
[deliverable/linux.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
1da177e4
LT		 41#include <linux/tcp.h>
42#include <linux/udp.h>
43#include <linux/etherdevice.h>
1da177e4
LT		 44#include <linux/delay.h>
45#include <linux/ethtool.h>
d052d1be 46#include <linux/platform_device.h>
fbd6a754
LB		 47#include <linux/module.h>
48#include <linux/kernel.h>
49#include <linux/spinlock.h>
50#include <linux/workqueue.h>
51#include <linux/mii.h>
fbd6a754 52#include <linux/mv643xx_eth.h>
1da177e4
LT		 53#include <asm/io.h>
54#include <asm/types.h>
1da177e4 55#include <asm/system.h>
fbd6a754 56
e5371493
LB		 57static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58static char mv643xx_eth_driver_version[] = "1.0";
c9df406f 59
e5371493
LB		 60#define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61#define MV643XX_ETH_NAPI
62#define MV643XX_ETH_TX_FAST_REFILL
fbd6a754 63
e5371493 64#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
fbd6a754
LB		 65#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
66#else
67#define MAX_DESCS_PER_SKB 1
68#endif
69
fbd6a754
LB		 70/*
71 * Registers shared between all ports.
72 */
3cb4667c
LB		 73#define PHY_ADDR 0x0000
74#define SMI_REG 0x0004
75#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78#define WINDOW_BAR_ENABLE 0x0290
79#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 80
81/*
82 * Per-port registers.
83 */
3cb4667c 84#define PORT_CONFIG(p) (0x0400 + ((p) << 10))
d9a073ea 85#define UNICAST_PROMISCUOUS_MODE 0x00000001
3cb4667c
LB		 86#define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
87#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
88#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
89#define SDMA_CONFIG(p) (0x041c + ((p) << 10))
90#define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
91#define PORT_STATUS(p) (0x0444 + ((p) << 10))
a2a41689 92#define TX_FIFO_EMPTY 0x00000400
3cb4667c 93#define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
89df5fdc
LB		 94#define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
95#define TX_BW_RATE(p) (0x0450 + ((p) << 10))
3cb4667c 96#define TX_BW_MTU(p) (0x0458 + ((p) << 10))
89df5fdc 97#define TX_BW_BURST(p) (0x045c + ((p) << 10))
3cb4667c 98#define INT_CAUSE(p) (0x0460 + ((p) << 10))
226bb6b7 99#define INT_TX_END 0x07f80000
64da80a2 100#define INT_RX 0x0007fbfc
073a345c 101#define INT_EXT 0x00000002
3cb4667c 102#define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
073a345c
LB		 103#define INT_EXT_LINK 0x00100000
104#define INT_EXT_PHY 0x00010000
105#define INT_EXT_TX_ERROR_0 0x00000100
106#define INT_EXT_TX_0 0x00000001
3d6b35bc 107#define INT_EXT_TX 0x0000ffff
3cb4667c
LB		 108#define INT_MASK(p) (0x0468 + ((p) << 10))
109#define INT_MASK_EXT(p) (0x046c + ((p) << 10))
110#define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
64da80a2 111#define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
3cb4667c 112#define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
3d6b35bc
LB		 113#define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
114#define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
115#define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
116#define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
3cb4667c
LB		 117#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
118#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
119#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
120#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 121
2679a550
LB		 122
123/*
124 * SDMA configuration register.
125 */
fbd6a754 126#define RX_BURST_SIZE_4_64BIT (2 << 1)
fbd6a754 127#define BLM_RX_NO_SWAP (1 << 4)
fbd6a754 128#define BLM_TX_NO_SWAP (1 << 5)
fbd6a754 129#define TX_BURST_SIZE_4_64BIT (2 << 22)
fbd6a754
LB		 130
131#if defined(__BIG_ENDIAN)
132#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
133 RX_BURST_SIZE_4_64BIT | \
fbd6a754
LB		 134 TX_BURST_SIZE_4_64BIT
135#elif defined(__LITTLE_ENDIAN)
136#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
137 RX_BURST_SIZE_4_64BIT | \
138 BLM_RX_NO_SWAP | \
139 BLM_TX_NO_SWAP | \
fbd6a754
LB		 140 TX_BURST_SIZE_4_64BIT
141#else
142#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
143#endif
144
2beff77b
LB		 145
146/*
147 * Port serial control register.
148 */
149#define SET_MII_SPEED_TO_100 (1 << 24)
150#define SET_GMII_SPEED_TO_1000 (1 << 23)
151#define SET_FULL_DUPLEX_MODE (1 << 21)
fbd6a754 152#define MAX_RX_PACKET_1522BYTE (1 << 17)
fbd6a754
LB		 153#define MAX_RX_PACKET_9700BYTE (5 << 17)
154#define MAX_RX_PACKET_MASK (7 << 17)
2beff77b
LB		 155#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
156#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
157#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
158#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
159#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
160#define FORCE_LINK_PASS (1 << 1)
161#define SERIAL_PORT_ENABLE (1 << 0)
fbd6a754 162
cc9754b3
LB		 163#define DEFAULT_RX_QUEUE_SIZE 400
164#define DEFAULT_TX_QUEUE_SIZE 800
fbd6a754 165
fbd6a754 166
7ca72a3b
LB		 167/*
168 * RX/TX descriptors.
fbd6a754
LB		 169 */
170#if defined(__BIG_ENDIAN)
cc9754b3 171struct rx_desc {
fbd6a754
LB		 172 u16 byte_cnt; /* Descriptor buffer byte count */
173 u16 buf_size; /* Buffer size */
174 u32 cmd_sts; /* Descriptor command status */
175 u32 next_desc_ptr; /* Next descriptor pointer */
176 u32 buf_ptr; /* Descriptor buffer pointer */
177};
178
cc9754b3 179struct tx_desc {
fbd6a754
LB		 180 u16 byte_cnt; /* buffer byte count */
181 u16 l4i_chk; /* CPU provided TCP checksum */
182 u32 cmd_sts; /* Command/status field */
183 u32 next_desc_ptr; /* Pointer to next descriptor */
184 u32 buf_ptr; /* pointer to buffer for this descriptor*/
185};
186#elif defined(__LITTLE_ENDIAN)
cc9754b3 187struct rx_desc {
fbd6a754
LB		 188 u32 cmd_sts; /* Descriptor command status */
189 u16 buf_size; /* Buffer size */
190 u16 byte_cnt; /* Descriptor buffer byte count */
191 u32 buf_ptr; /* Descriptor buffer pointer */
192 u32 next_desc_ptr; /* Next descriptor pointer */
193};
194
cc9754b3 195struct tx_desc {
fbd6a754
LB		 196 u32 cmd_sts; /* Command/status field */
197 u16 l4i_chk; /* CPU provided TCP checksum */
198 u16 byte_cnt; /* buffer byte count */
199 u32 buf_ptr; /* pointer to buffer for this descriptor*/
200 u32 next_desc_ptr; /* Pointer to next descriptor */
201};
202#else
203#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
204#endif
205
7ca72a3b 206/* RX & TX descriptor command */
cc9754b3 207#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 208
209/* RX & TX descriptor status */
cc9754b3 210#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 211
212/* RX descriptor status */
cc9754b3
LB		 213#define LAYER_4_CHECKSUM_OK 0x40000000
214#define RX_ENABLE_INTERRUPT 0x20000000
215#define RX_FIRST_DESC 0x08000000
216#define RX_LAST_DESC 0x04000000
7ca72a3b
LB		 217
218/* TX descriptor command */
cc9754b3
LB		 219#define TX_ENABLE_INTERRUPT 0x00800000
220#define GEN_CRC 0x00400000
221#define TX_FIRST_DESC 0x00200000
222#define TX_LAST_DESC 0x00100000
223#define ZERO_PADDING 0x00080000
224#define GEN_IP_V4_CHECKSUM 0x00040000
225#define GEN_TCP_UDP_CHECKSUM 0x00020000
226#define UDP_FRAME 0x00010000
7ca72a3b 227
cc9754b3 228#define TX_IHL_SHIFT 11
7ca72a3b
LB		 229
230
c9df406f 231/* global *******************************************************************/
e5371493 232struct mv643xx_eth_shared_private {
fc32b0e2
LB		 233 /*
234 * Ethernet controller base address.
235 */
cc9754b3 236 void __iomem *base;
c9df406f 237
fc32b0e2
LB		 238 /*
239 * Protects access to SMI_REG, which is shared between ports.
240 */
c9df406f
LB		 241 spinlock_t phy_lock;
242
fc32b0e2
LB		 243 /*
244 * Per-port MBUS window access register value.
245 */
c9df406f
LB		 246 u32 win_protect;
247
fc32b0e2
LB		 248 /*
249 * Hardware-specific parameters.
250 */
c9df406f 251 unsigned int t_clk;
773fc3ee 252 int extended_rx_coal_limit;
c9df406f
LB		 253};
254
255
256/* per-port *****************************************************************/
e5371493 257struct mib_counters {
fbd6a754
LB		 258 u64 good_octets_received;
259 u32 bad_octets_received;
260 u32 internal_mac_transmit_err;
261 u32 good_frames_received;
262 u32 bad_frames_received;
263 u32 broadcast_frames_received;
264 u32 multicast_frames_received;
265 u32 frames_64_octets;
266 u32 frames_65_to_127_octets;
267 u32 frames_128_to_255_octets;
268 u32 frames_256_to_511_octets;
269 u32 frames_512_to_1023_octets;
270 u32 frames_1024_to_max_octets;
271 u64 good_octets_sent;
272 u32 good_frames_sent;
273 u32 excessive_collision;
274 u32 multicast_frames_sent;
275 u32 broadcast_frames_sent;
276 u32 unrec_mac_control_received;
277 u32 fc_sent;
278 u32 good_fc_received;
279 u32 bad_fc_received;
280 u32 undersize_received;
281 u32 fragments_received;
282 u32 oversize_received;
283 u32 jabber_received;
284 u32 mac_receive_error;
285 u32 bad_crc_event;
286 u32 collision;
287 u32 late_collision;
288};
289
8a578111 290struct rx_queue {
64da80a2
LB		 291 int index;
292
8a578111
LB		 293 int rx_ring_size;
294
295 int rx_desc_count;
296 int rx_curr_desc;
297 int rx_used_desc;
298
299 struct rx_desc *rx_desc_area;
300 dma_addr_t rx_desc_dma;
301 int rx_desc_area_size;
302 struct sk_buff **rx_skb;
303
304 struct timer_list rx_oom;
305};
306
13d64285 307struct tx_queue {
3d6b35bc
LB		 308 int index;
309
13d64285 310 int tx_ring_size;
fbd6a754 311
13d64285
LB		 312 int tx_desc_count;
313 int tx_curr_desc;
314 int tx_used_desc;
fbd6a754 315
5daffe94 316 struct tx_desc *tx_desc_area;
fbd6a754
LB		 317 dma_addr_t tx_desc_dma;
318 int tx_desc_area_size;
319 struct sk_buff **tx_skb;
13d64285
LB		 320};
321
322struct mv643xx_eth_private {
323 struct mv643xx_eth_shared_private *shared;
fc32b0e2 324 int port_num;
13d64285 325
fc32b0e2 326 struct net_device *dev;
fbd6a754 327
fc32b0e2
LB		 328 struct mv643xx_eth_shared_private *shared_smi;
329 int phy_addr;
fbd6a754 330
fbd6a754 331 spinlock_t lock;
fbd6a754 332
fc32b0e2
LB		 333 struct mib_counters mib_counters;
334 struct work_struct tx_timeout_task;
fbd6a754 335 struct mii_if_info mii;
8a578111
LB		 336
337 /*
338 * RX state.
339 */
340 int default_rx_ring_size;
341 unsigned long rx_desc_sram_addr;
342 int rx_desc_sram_size;
64da80a2
LB		 343 u8 rxq_mask;
344 int rxq_primary;
8a578111 345 struct napi_struct napi;
64da80a2 346 struct rx_queue rxq[8];
13d64285
LB		 347
348 /*
349 * TX state.
350 */
351 int default_tx_ring_size;
352 unsigned long tx_desc_sram_addr;
353 int tx_desc_sram_size;
3d6b35bc
LB		 354 u8 txq_mask;
355 int txq_primary;
356 struct tx_queue txq[8];
13d64285
LB		 357#ifdef MV643XX_ETH_TX_FAST_REFILL
358 int tx_clean_threshold;
359#endif
fbd6a754 360};
1da177e4 361
fbd6a754 362
c9df406f 363/* port register accessors **************************************************/
e5371493 364static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 365{
cc9754b3 366 return readl(mp->shared->base + offset);
c9df406f 367}
fbd6a754 368
e5371493 369static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 370{
cc9754b3 371 writel(data, mp->shared->base + offset);
c9df406f 372}
fbd6a754 373
fbd6a754 374
c9df406f 375/* rxq/txq helper functions *************************************************/
8a578111 376static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 377{
64da80a2 378 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 379}
fbd6a754 380
13d64285
LB		 381static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
382{
3d6b35bc 383 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 384}
385
8a578111 386static void rxq_enable(struct rx_queue *rxq)
c9df406f 387{
8a578111 388 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 389 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
8a578111 390}
1da177e4 391
8a578111
LB		 392static void rxq_disable(struct rx_queue *rxq)
393{
394 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 395 u8 mask = 1 << rxq->index;
1da177e4 396
8a578111
LB		 397 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
398 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
399 udelay(10);
c9df406f
LB		 400}
401
13d64285 402static void txq_enable(struct tx_queue *txq)
1da177e4 403{
13d64285 404 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 405 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
1da177e4
LT		 406}
407
13d64285 408static void txq_disable(struct tx_queue *txq)
1da177e4 409{
13d64285 410 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 411 u8 mask = 1 << txq->index;
c9df406f 412
13d64285
LB		 413 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
414 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
415 udelay(10);
416}
417
418static void __txq_maybe_wake(struct tx_queue *txq)
419{
420 struct mv643xx_eth_private *mp = txq_to_mp(txq);
421
3d6b35bc
LB		 422 /*
423 * netif_{stop,wake}_queue() flow control only applies to
424 * the primary queue.
425 */
426 BUG_ON(txq->index != mp->txq_primary);
427
13d64285
LB		 428 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB)
429 netif_wake_queue(mp->dev);
1da177e4
LT		 430}
431
c9df406f
LB		 432
433/* rx ***********************************************************************/
13d64285 434static void txq_reclaim(struct tx_queue *txq, int force);
c9df406f 435
8a578111 436static void rxq_refill(struct rx_queue *rxq)
1da177e4 437{
8a578111 438 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
c9df406f 439 unsigned long flags;
1da177e4 440
c9df406f 441 spin_lock_irqsave(&mp->lock, flags);
c0d0f2ca 442
8a578111
LB		 443 while (rxq->rx_desc_count < rxq->rx_ring_size) {
444 int skb_size;
de34f225
LB		 445 struct sk_buff *skb;
446 int unaligned;
447 int rx;
448
8a578111
LB		 449 /*
450 * Reserve 2+14 bytes for an ethernet header (the
451 * hardware automatically prepends 2 bytes of dummy
452 * data to each received packet), 4 bytes for a VLAN
453 * header, and 4 bytes for the trailing FCS -- 24
454 * bytes total.
455 */
456 skb_size = mp->dev->mtu + 24;
457
458 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
de34f225 459 if (skb == NULL)
1da177e4 460 break;
de34f225 461
908b637f 462 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
b44cd572 463 if (unaligned)
908b637f 464 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
de34f225 465
8a578111
LB		 466 rxq->rx_desc_count++;
467 rx = rxq->rx_used_desc;
468 rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size;
de34f225 469
8a578111
LB		 470 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
471 skb_size, DMA_FROM_DEVICE);
472 rxq->rx_desc_area[rx].buf_size = skb_size;
473 rxq->rx_skb[rx] = skb;
de34f225 474 wmb();
8a578111 475 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
de34f225
LB		 476 RX_ENABLE_INTERRUPT;
477 wmb();
478
fc32b0e2
LB		 479 /*
480 * The hardware automatically prepends 2 bytes of
481 * dummy data to each received packet, so that the
482 * IP header ends up 16-byte aligned.
483 */
484 skb_reserve(skb, 2);
1da177e4 485 }
de34f225 486
8a578111
LB		 487 if (rxq->rx_desc_count == 0) {
488 rxq->rx_oom.expires = jiffies + (HZ / 10);
489 add_timer(&rxq->rx_oom);
1da177e4 490 }
de34f225
LB		 491
492 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4
LT		 493}
494
8a578111 495static inline void rxq_refill_timer_wrapper(unsigned long data)
1da177e4 496{
8a578111 497 rxq_refill((struct rx_queue *)data);
1da177e4
LT		 498}
499
8a578111 500static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 501{
8a578111
LB		 502 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
503 struct net_device_stats *stats = &mp->dev->stats;
504 int rx;
1da177e4 505
8a578111
LB		 506 rx = 0;
507 while (rx < budget) {
fc32b0e2 508 struct rx_desc *rx_desc;
96587661 509 unsigned int cmd_sts;
fc32b0e2 510 struct sk_buff *skb;
96587661 511 unsigned long flags;
d344bff9 512
96587661 513 spin_lock_irqsave(&mp->lock, flags);
ff561eef 514
8a578111 515 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 516
96587661
LB		 517 cmd_sts = rx_desc->cmd_sts;
518 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
519 spin_unlock_irqrestore(&mp->lock, flags);
520 break;
521 }
522 rmb();
1da177e4 523
8a578111
LB		 524 skb = rxq->rx_skb[rxq->rx_curr_desc];
525 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 526
8a578111 527 rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size;
ff561eef 528
96587661 529 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 530
fc32b0e2
LB		 531 dma_unmap_single(NULL, rx_desc->buf_ptr + 2,
532 mp->dev->mtu + 24, DMA_FROM_DEVICE);
8a578111
LB		 533 rxq->rx_desc_count--;
534 rx++;
b1dd9ca1 535
468d09f8
DF		 536 /*
537 * Update statistics.
fc32b0e2
LB		 538 *
539 * Note that the descriptor byte count includes 2 dummy
540 * bytes automatically inserted by the hardware at the
541 * start of the packet (which we don't count), and a 4
542 * byte CRC at the end of the packet (which we do count).
468d09f8 543 */
1da177e4 544 stats->rx_packets++;
fc32b0e2 545 stats->rx_bytes += rx_desc->byte_cnt - 2;
96587661 546
1da177e4 547 /*
fc32b0e2
LB		 548 * In case we received a packet without first / last bits
549 * on, or the error summary bit is set, the packet needs
550 * to be dropped.
1da177e4 551 */
96587661 552 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 553 (RX_FIRST_DESC | RX_LAST_DESC))
96587661 554 || (cmd_sts & ERROR_SUMMARY)) {
1da177e4 555 stats->rx_dropped++;
fc32b0e2 556
96587661 557 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 558 (RX_FIRST_DESC | RX_LAST_DESC)) {
1da177e4 559 if (net_ratelimit())
fc32b0e2
LB		 560 dev_printk(KERN_ERR, &mp->dev->dev,
561 "received packet spanning "
562 "multiple descriptors\n");
1da177e4 563 }
fc32b0e2 564
96587661 565 if (cmd_sts & ERROR_SUMMARY)
1da177e4
LT		 566 stats->rx_errors++;
567
568 dev_kfree_skb_irq(skb);
569 } else {
570 /*
571 * The -4 is for the CRC in the trailer of the
572 * received packet
573 */
fc32b0e2 574 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
1da177e4 575
96587661 576 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
1da177e4
LT		 577 skb->ip_summed = CHECKSUM_UNNECESSARY;
578 skb->csum = htons(
96587661 579 (cmd_sts & 0x0007fff8) >> 3);
1da177e4 580 }
8a578111 581 skb->protocol = eth_type_trans(skb, mp->dev);
e5371493 582#ifdef MV643XX_ETH_NAPI
1da177e4
LT		 583 netif_receive_skb(skb);
584#else
585 netif_rx(skb);
586#endif
587 }
fc32b0e2 588
8a578111 589 mp->dev->last_rx = jiffies;
1da177e4 590 }
fc32b0e2 591
8a578111 592 rxq_refill(rxq);
1da177e4 593
8a578111 594 return rx;
1da177e4
LT		 595}
596
e5371493 597#ifdef MV643XX_ETH_NAPI
e5371493 598static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
d0412d96 599{
8a578111
LB		 600 struct mv643xx_eth_private *mp;
601 int rx;
64da80a2 602 int i;
8a578111
LB		 603
604 mp = container_of(napi, struct mv643xx_eth_private, napi);
d0412d96 605
e5371493 606#ifdef MV643XX_ETH_TX_FAST_REFILL
c9df406f 607 if (++mp->tx_clean_threshold > 5) {
c9df406f 608 mp->tx_clean_threshold = 0;
3d6b35bc
LB		 609 for (i = 0; i < 8; i++)
610 if (mp->txq_mask & (1 << i))
611 txq_reclaim(mp->txq + i, 0);
d0412d96 612 }
c9df406f 613#endif
d0412d96 614
64da80a2
LB		 615 rx = 0;
616 for (i = 7; rx < budget && i >= 0; i--)
617 if (mp->rxq_mask & (1 << i))
618 rx += rxq_process(mp->rxq + i, budget - rx);
d0412d96 619
8a578111
LB		 620 if (rx < budget) {
621 netif_rx_complete(mp->dev, napi);
622 wrl(mp, INT_CAUSE(mp->port_num), 0);
623 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
226bb6b7 624 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
d0412d96 625 }
c9df406f 626
8a578111 627 return rx;
d0412d96 628}
c9df406f 629#endif
d0412d96 630
c9df406f
LB		 631
632/* tx ***********************************************************************/
c9df406f 633static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 634{
13d64285 635 int frag;
1da177e4 636
c9df406f 637 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
13d64285
LB		 638 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
639 if (fragp->size <= 8 && fragp->page_offset & 7)
c9df406f 640 return 1;
1da177e4 641 }
13d64285 642
c9df406f
LB		 643 return 0;
644}
7303fde8 645
13d64285 646static int txq_alloc_desc_index(struct tx_queue *txq)
c9df406f
LB		 647{
648 int tx_desc_curr;
d0412d96 649
13d64285 650 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
1da177e4 651
13d64285
LB		 652 tx_desc_curr = txq->tx_curr_desc;
653 txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size;
e4d00fa9 654
13d64285 655 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
468d09f8 656
c9df406f
LB		 657 return tx_desc_curr;
658}
468d09f8 659
13d64285 660static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 661{
13d64285 662 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 663 int frag;
1da177e4 664
13d64285
LB		 665 for (frag = 0; frag < nr_frags; frag++) {
666 skb_frag_t *this_frag;
667 int tx_index;
668 struct tx_desc *desc;
669
670 this_frag = &skb_shinfo(skb)->frags[frag];
671 tx_index = txq_alloc_desc_index(txq);
672 desc = &txq->tx_desc_area[tx_index];
673
674 /*
675 * The last fragment will generate an interrupt
676 * which will free the skb on TX completion.
677 */
678 if (frag == nr_frags - 1) {
679 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
680 ZERO_PADDING | TX_LAST_DESC |
681 TX_ENABLE_INTERRUPT;
682 txq->tx_skb[tx_index] = skb;
683 } else {
684 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
685 txq->tx_skb[tx_index] = NULL;
686 }
687
c9df406f
LB		 688 desc->l4i_chk = 0;
689 desc->byte_cnt = this_frag->size;
690 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
691 this_frag->page_offset,
692 this_frag->size,
693 DMA_TO_DEVICE);
694 }
1da177e4
LT		 695}
696
c9df406f
LB		 697static inline __be16 sum16_as_be(__sum16 sum)
698{
699 return (__force __be16)sum;
700}
1da177e4 701
13d64285 702static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 703{
13d64285 704 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 705 int tx_index;
cc9754b3 706 struct tx_desc *desc;
c9df406f
LB		 707 u32 cmd_sts;
708 int length;
1da177e4 709
cc9754b3 710 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
1da177e4 711
13d64285
LB		 712 tx_index = txq_alloc_desc_index(txq);
713 desc = &txq->tx_desc_area[tx_index];
c9df406f
LB		 714
715 if (nr_frags) {
13d64285 716 txq_submit_frag_skb(txq, skb);
c9df406f
LB		 717
718 length = skb_headlen(skb);
13d64285 719 txq->tx_skb[tx_index] = NULL;
c9df406f 720 } else {
cc9754b3 721 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
c9df406f 722 length = skb->len;
13d64285 723 txq->tx_skb[tx_index] = skb;
c9df406f
LB		 724 }
725
726 desc->byte_cnt = length;
727 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
728
729 if (skb->ip_summed == CHECKSUM_PARTIAL) {
730 BUG_ON(skb->protocol != htons(ETH_P_IP));
731
cc9754b3
LB		 732 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
733 GEN_IP_V4_CHECKSUM |
734 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
c9df406f
LB		 735
736 switch (ip_hdr(skb)->protocol) {
737 case IPPROTO_UDP:
cc9754b3 738 cmd_sts |= UDP_FRAME;
c9df406f
LB		 739 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
740 break;
741 case IPPROTO_TCP:
742 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
743 break;
744 default:
745 BUG();
746 }
747 } else {
748 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 749 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 750 desc->l4i_chk = 0;
751 }
752
753 /* ensure all other descriptors are written before first cmd_sts */
754 wmb();
755 desc->cmd_sts = cmd_sts;
756
757 /* ensure all descriptors are written before poking hardware */
758 wmb();
13d64285 759 txq_enable(txq);
c9df406f 760
13d64285 761 txq->tx_desc_count += nr_frags + 1;
1da177e4 762}
1da177e4 763
fc32b0e2 764static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 765{
e5371493 766 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 767 struct net_device_stats *stats = &dev->stats;
13d64285 768 struct tx_queue *txq;
c9df406f 769 unsigned long flags;
afdb57a2 770
c9df406f
LB		 771 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
772 stats->tx_dropped++;
fc32b0e2
LB		 773 dev_printk(KERN_DEBUG, &dev->dev,
774 "failed to linearize skb with tiny "
775 "unaligned fragment\n");
c9df406f
LB		 776 return NETDEV_TX_BUSY;
777 }
778
779 spin_lock_irqsave(&mp->lock, flags);
780
3d6b35bc 781 txq = mp->txq + mp->txq_primary;
13d64285
LB		 782
783 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) {
c9df406f 784 spin_unlock_irqrestore(&mp->lock, flags);
3d6b35bc
LB		 785 if (txq->index == mp->txq_primary && net_ratelimit())
786 dev_printk(KERN_ERR, &dev->dev,
787 "primary tx queue full?!\n");
788 kfree_skb(skb);
789 return NETDEV_TX_OK;
c9df406f
LB		 790 }
791
13d64285 792 txq_submit_skb(txq, skb);
c9df406f
LB		 793 stats->tx_bytes += skb->len;
794 stats->tx_packets++;
795 dev->trans_start = jiffies;
796
3d6b35bc
LB		 797 if (txq->index == mp->txq_primary) {
798 int entries_left;
799
800 entries_left = txq->tx_ring_size - txq->tx_desc_count;
801 if (entries_left < MAX_DESCS_PER_SKB)
802 netif_stop_queue(dev);
803 }
c9df406f
LB		 804
805 spin_unlock_irqrestore(&mp->lock, flags);
806
807 return NETDEV_TX_OK;
1da177e4
LT		 808}
809
c9df406f 810
89df5fdc
LB		 811/* tx rate control **********************************************************/
812/*
813 * Set total maximum TX rate (shared by all TX queues for this port)
814 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
815 */
816static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
817{
818 int token_rate;
819 int mtu;
820 int bucket_size;
821
822 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
823 if (token_rate > 1023)
824 token_rate = 1023;
825
826 mtu = (mp->dev->mtu + 255) >> 8;
827 if (mtu > 63)
828 mtu = 63;
829
830 bucket_size = (burst + 255) >> 8;
831 if (bucket_size > 65535)
832 bucket_size = 65535;
833
834 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
835 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
836 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
837}
838
839static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
840{
841 struct mv643xx_eth_private *mp = txq_to_mp(txq);
842 int token_rate;
843 int bucket_size;
844
845 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
846 if (token_rate > 1023)
847 token_rate = 1023;
848
849 bucket_size = (burst + 255) >> 8;
850 if (bucket_size > 65535)
851 bucket_size = 65535;
852
3d6b35bc
LB		 853 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
854 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
89df5fdc
LB		 855 (bucket_size << 10) | token_rate);
856}
857
858static void txq_set_fixed_prio_mode(struct tx_queue *txq)
859{
860 struct mv643xx_eth_private *mp = txq_to_mp(txq);
861 int off;
862 u32 val;
863
864 /*
865 * Turn on fixed priority mode.
866 */
867 off = TXQ_FIX_PRIO_CONF(mp->port_num);
868
869 val = rdl(mp, off);
3d6b35bc 870 val |= 1 << txq->index;
89df5fdc
LB		 871 wrl(mp, off, val);
872}
873
874static void txq_set_wrr(struct tx_queue *txq, int weight)
875{
876 struct mv643xx_eth_private *mp = txq_to_mp(txq);
877 int off;
878 u32 val;
879
880 /*
881 * Turn off fixed priority mode.
882 */
883 off = TXQ_FIX_PRIO_CONF(mp->port_num);
884
885 val = rdl(mp, off);
3d6b35bc 886 val &= ~(1 << txq->index);
89df5fdc
LB		 887 wrl(mp, off, val);
888
889 /*
890 * Configure WRR weight for this queue.
891 */
3d6b35bc 892 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
89df5fdc
LB		 893
894 val = rdl(mp, off);
895 val = (val & ~0xff) | (weight & 0xff);
896 wrl(mp, off, val);
897}
898
899
c9df406f 900/* mii management interface *************************************************/
fc32b0e2
LB		 901#define SMI_BUSY 0x10000000
902#define SMI_READ_VALID 0x08000000
903#define SMI_OPCODE_READ 0x04000000
904#define SMI_OPCODE_WRITE 0x00000000
c9df406f 905
fc32b0e2
LB		 906static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr,
907 unsigned int reg, unsigned int *value)
1da177e4 908{
cc9754b3 909 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
c9df406f 910 unsigned long flags;
1da177e4
LT		 911 int i;
912
c9df406f
LB		 913 /* the SMI register is a shared resource */
914 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
915
916 /* wait for the SMI register to become available */
cc9754b3 917 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
e1bea50a 918 if (i == 1000) {
c9df406f
LB		 919 printk("%s: PHY busy timeout\n", mp->dev->name);
920 goto out;
921 }
e1bea50a 922 udelay(10);
1da177e4
LT		 923 }
924
fc32b0e2 925 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 926
c9df406f 927 /* now wait for the data to be valid */
cc9754b3 928 for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
e1bea50a 929 if (i == 1000) {
c9df406f
LB		 930 printk("%s: PHY read timeout\n", mp->dev->name);
931 goto out;
932 }
e1bea50a 933 udelay(10);
c9df406f
LB		 934 }
935
936 *value = readl(smi_reg) & 0xffff;
937out:
938 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1da177e4
LT		 939}
940
fc32b0e2
LB		 941static void smi_reg_write(struct mv643xx_eth_private *mp,
942 unsigned int addr,
943 unsigned int reg, unsigned int value)
1da177e4 944{
cc9754b3 945 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
c9df406f 946 unsigned long flags;
1da177e4
LT		 947 int i;
948
c9df406f
LB		 949 /* the SMI register is a shared resource */
950 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
951
952 /* wait for the SMI register to become available */
cc9754b3 953 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
e1bea50a 954 if (i == 1000) {
c9df406f
LB		 955 printk("%s: PHY busy timeout\n", mp->dev->name);
956 goto out;
957 }
e1bea50a 958 udelay(10);
1da177e4
LT		 959 }
960
fc32b0e2
LB		 961 writel(SMI_OPCODE_WRITE | (reg << 21) |
962 (addr << 16) | (value & 0xffff), smi_reg);
c9df406f
LB		 963out:
964 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
965}
1da177e4 966
c9df406f
LB		 967
968/* mib counters *************************************************************/
fc32b0e2 969static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 970{
fc32b0e2 971 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 972}
973
fc32b0e2 974static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 975{
fc32b0e2
LB		 976 int i;
977
978 for (i = 0; i < 0x80; i += 4)
979 mib_read(mp, i);
c9df406f 980}
d0412d96 981
fc32b0e2 982static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 983{
e5371493 984 struct mib_counters *p = &mp->mib_counters;
4b8e3655 985
fc32b0e2
LB		 986 p->good_octets_received += mib_read(mp, 0x00);
987 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
988 p->bad_octets_received += mib_read(mp, 0x08);
989 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
990 p->good_frames_received += mib_read(mp, 0x10);
991 p->bad_frames_received += mib_read(mp, 0x14);
992 p->broadcast_frames_received += mib_read(mp, 0x18);
993 p->multicast_frames_received += mib_read(mp, 0x1c);
994 p->frames_64_octets += mib_read(mp, 0x20);
995 p->frames_65_to_127_octets += mib_read(mp, 0x24);
996 p->frames_128_to_255_octets += mib_read(mp, 0x28);
997 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
998 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
999 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1000 p->good_octets_sent += mib_read(mp, 0x38);
1001 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1002 p->good_frames_sent += mib_read(mp, 0x40);
1003 p->excessive_collision += mib_read(mp, 0x44);
1004 p->multicast_frames_sent += mib_read(mp, 0x48);
1005 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1006 p->unrec_mac_control_received += mib_read(mp, 0x50);
1007 p->fc_sent += mib_read(mp, 0x54);
1008 p->good_fc_received += mib_read(mp, 0x58);
1009 p->bad_fc_received += mib_read(mp, 0x5c);
1010 p->undersize_received += mib_read(mp, 0x60);
1011 p->fragments_received += mib_read(mp, 0x64);
1012 p->oversize_received += mib_read(mp, 0x68);
1013 p->jabber_received += mib_read(mp, 0x6c);
1014 p->mac_receive_error += mib_read(mp, 0x70);
1015 p->bad_crc_event += mib_read(mp, 0x74);
1016 p->collision += mib_read(mp, 0x78);
1017 p->late_collision += mib_read(mp, 0x7c);
d0412d96
JC		 1018}
1019
c9df406f
LB		 1020
1021/* ethtool ******************************************************************/
e5371493 1022struct mv643xx_eth_stats {
c9df406f
LB		 1023 char stat_string[ETH_GSTRING_LEN];
1024 int sizeof_stat;
16820054
LB		 1025 int netdev_off;
1026 int mp_off;
c9df406f
LB		 1027};
1028
16820054
LB		 1029#define SSTAT(m) \
1030 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1031 offsetof(struct net_device, stats.m), -1 }
1032
1033#define MIBSTAT(m) \
1034 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1035 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1036
1037static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1038 SSTAT(rx_packets),
1039 SSTAT(tx_packets),
1040 SSTAT(rx_bytes),
1041 SSTAT(tx_bytes),
1042 SSTAT(rx_errors),
1043 SSTAT(tx_errors),
1044 SSTAT(rx_dropped),
1045 SSTAT(tx_dropped),
1046 MIBSTAT(good_octets_received),
1047 MIBSTAT(bad_octets_received),
1048 MIBSTAT(internal_mac_transmit_err),
1049 MIBSTAT(good_frames_received),
1050 MIBSTAT(bad_frames_received),
1051 MIBSTAT(broadcast_frames_received),
1052 MIBSTAT(multicast_frames_received),
1053 MIBSTAT(frames_64_octets),
1054 MIBSTAT(frames_65_to_127_octets),
1055 MIBSTAT(frames_128_to_255_octets),
1056 MIBSTAT(frames_256_to_511_octets),
1057 MIBSTAT(frames_512_to_1023_octets),
1058 MIBSTAT(frames_1024_to_max_octets),
1059 MIBSTAT(good_octets_sent),
1060 MIBSTAT(good_frames_sent),
1061 MIBSTAT(excessive_collision),
1062 MIBSTAT(multicast_frames_sent),
1063 MIBSTAT(broadcast_frames_sent),
1064 MIBSTAT(unrec_mac_control_received),
1065 MIBSTAT(fc_sent),
1066 MIBSTAT(good_fc_received),
1067 MIBSTAT(bad_fc_received),
1068 MIBSTAT(undersize_received),
1069 MIBSTAT(fragments_received),
1070 MIBSTAT(oversize_received),
1071 MIBSTAT(jabber_received),
1072 MIBSTAT(mac_receive_error),
1073 MIBSTAT(bad_crc_event),
1074 MIBSTAT(collision),
1075 MIBSTAT(late_collision),
c9df406f
LB		 1076};
1077
e5371493 1078static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
d0412d96 1079{
e5371493 1080 struct mv643xx_eth_private *mp = netdev_priv(dev);
d0412d96
JC		 1081 int err;
1082
1083 spin_lock_irq(&mp->lock);
1084 err = mii_ethtool_gset(&mp->mii, cmd);
1085 spin_unlock_irq(&mp->lock);
1086
fc32b0e2
LB		 1087 /*
1088 * The MAC does not support 1000baseT_Half.
1089 */
d0412d96
JC		 1090 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1091 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1092
1093 return err;
1094}
1095
e5371493 1096static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1097{
e5371493 1098 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6
DF		 1099 int err;
1100
fc32b0e2
LB		 1101 /*
1102 * The MAC does not support 1000baseT_Half.
1103 */
1104 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1105
c9df406f
LB		 1106 spin_lock_irq(&mp->lock);
1107 err = mii_ethtool_sset(&mp->mii, cmd);
1108 spin_unlock_irq(&mp->lock);
85cf572c 1109
c9df406f
LB		 1110 return err;
1111}
1da177e4 1112
fc32b0e2
LB		 1113static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1114 struct ethtool_drvinfo *drvinfo)
c9df406f 1115{
e5371493
LB		 1116 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1117 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 1118 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 1119 strncpy(drvinfo->bus_info, "platform", 32);
16820054 1120 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1121}
1da177e4 1122
fc32b0e2 1123static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1124{
e5371493 1125 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1126
c9df406f
LB		 1127 return mii_nway_restart(&mp->mii);
1128}
1da177e4 1129
c9df406f
LB		 1130static u32 mv643xx_eth_get_link(struct net_device *dev)
1131{
e5371493 1132 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1133
c9df406f
LB		 1134 return mii_link_ok(&mp->mii);
1135}
1da177e4 1136
fc32b0e2
LB		 1137static void mv643xx_eth_get_strings(struct net_device *dev,
1138 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1139{
1140 int i;
1da177e4 1141
fc32b0e2
LB		 1142 if (stringset == ETH_SS_STATS) {
1143 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1144 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1145 mv643xx_eth_stats[i].stat_string,
e5371493 1146 ETH_GSTRING_LEN);
c9df406f 1147 }
c9df406f
LB		 1148 }
1149}
1da177e4 1150
fc32b0e2
LB		 1151static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1152 struct ethtool_stats *stats,
1153 uint64_t *data)
c9df406f 1154{
fc32b0e2 1155 struct mv643xx_eth_private *mp = dev->priv;
c9df406f 1156 int i;
1da177e4 1157
fc32b0e2 1158 mib_counters_update(mp);
1da177e4 1159
16820054
LB		 1160 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1161 const struct mv643xx_eth_stats *stat;
1162 void *p;
1163
1164 stat = mv643xx_eth_stats + i;
1165
1166 if (stat->netdev_off >= 0)
1167 p = ((void *)mp->dev) + stat->netdev_off;
1168 else
1169 p = ((void *)mp) + stat->mp_off;
1170
1171 data[i] = (stat->sizeof_stat == 8) ?
1172 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1173 }
c9df406f 1174}
1da177e4 1175
fc32b0e2 1176static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1177{
fc32b0e2 1178 if (sset == ETH_SS_STATS)
16820054 1179 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1180
1181 return -EOPNOTSUPP;
c9df406f 1182}
1da177e4 1183
e5371493 1184static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1185 .get_settings = mv643xx_eth_get_settings,
1186 .set_settings = mv643xx_eth_set_settings,
1187 .get_drvinfo = mv643xx_eth_get_drvinfo,
1188 .nway_reset = mv643xx_eth_nway_reset,
1189 .get_link = mv643xx_eth_get_link,
c9df406f 1190 .set_sg = ethtool_op_set_sg,
fc32b0e2
LB		 1191 .get_strings = mv643xx_eth_get_strings,
1192 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
e5371493 1193 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1194};
1da177e4 1195
bea3348e 1196
c9df406f 1197/* address handling *********************************************************/
5daffe94 1198static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1199{
c9df406f
LB		 1200 unsigned int mac_h;
1201 unsigned int mac_l;
1da177e4 1202
fc32b0e2
LB		 1203 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1204 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1da177e4 1205
5daffe94
LB		 1206 addr[0] = (mac_h >> 24) & 0xff;
1207 addr[1] = (mac_h >> 16) & 0xff;
1208 addr[2] = (mac_h >> 8) & 0xff;
1209 addr[3] = mac_h & 0xff;
1210 addr[4] = (mac_l >> 8) & 0xff;
1211 addr[5] = mac_l & 0xff;
c9df406f 1212}
1da177e4 1213
e5371493 1214static void init_mac_tables(struct mv643xx_eth_private *mp)
c9df406f 1215{
fc32b0e2 1216 int i;
1da177e4 1217
fc32b0e2
LB		 1218 for (i = 0; i < 0x100; i += 4) {
1219 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1220 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
c9df406f 1221 }
fc32b0e2
LB		 1222
1223 for (i = 0; i < 0x10; i += 4)
1224 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
c9df406f 1225}
d0412d96 1226
e5371493 1227static void set_filter_table_entry(struct mv643xx_eth_private *mp,
fc32b0e2 1228 int table, unsigned char entry)
c9df406f
LB		 1229{
1230 unsigned int table_reg;
ab4384a6 1231
c9df406f 1232 /* Set "accepts frame bit" at specified table entry */
fc32b0e2
LB		 1233 table_reg = rdl(mp, table + (entry & 0xfc));
1234 table_reg |= 0x01 << (8 * (entry & 3));
1235 wrl(mp, table + (entry & 0xfc), table_reg);
1da177e4
LT		 1236}
1237
5daffe94 1238static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1da177e4 1239{
c9df406f
LB		 1240 unsigned int mac_h;
1241 unsigned int mac_l;
1242 int table;
1da177e4 1243
fc32b0e2
LB		 1244 mac_l = (addr[4] << 8) | addr[5];
1245 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
ff561eef 1246
fc32b0e2
LB		 1247 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1248 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1da177e4 1249
fc32b0e2 1250 table = UNICAST_TABLE(mp->port_num);
5daffe94 1251 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1da177e4
LT		 1252}
1253
fc32b0e2 1254static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1da177e4 1255{
e5371493 1256 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1257
fc32b0e2
LB		 1258 /* +2 is for the offset of the HW addr type */
1259 memcpy(dev->dev_addr, addr + 2, 6);
1260
cc9754b3
LB		 1261 init_mac_tables(mp);
1262 uc_addr_set(mp, dev->dev_addr);
1da177e4
LT		 1263
1264 return 0;
1265}
1266
69876569
LB		 1267static int addr_crc(unsigned char *addr)
1268{
1269 int crc = 0;
1270 int i;
1271
1272 for (i = 0; i < 6; i++) {
1273 int j;
1274
1275 crc = (crc ^ addr[i]) << 8;
1276 for (j = 7; j >= 0; j--) {
1277 if (crc & (0x100 << j))
1278 crc ^= 0x107 << j;
1279 }
1280 }
1281
1282 return crc;
1283}
1284
fc32b0e2 1285static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1da177e4 1286{
fc32b0e2
LB		 1287 struct mv643xx_eth_private *mp = netdev_priv(dev);
1288 u32 port_config;
1289 struct dev_addr_list *addr;
1290 int i;
c8aaea25 1291
fc32b0e2
LB		 1292 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1293 if (dev->flags & IFF_PROMISC)
1294 port_config |= UNICAST_PROMISCUOUS_MODE;
1295 else
1296 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1297 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1da177e4 1298
fc32b0e2
LB		 1299 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1300 int port_num = mp->port_num;
1301 u32 accept = 0x01010101;
c8aaea25 1302
fc32b0e2
LB		 1303 for (i = 0; i < 0x100; i += 4) {
1304 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1305 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1306 }
1307 return;
1308 }
c8aaea25 1309
fc32b0e2
LB		 1310 for (i = 0; i < 0x100; i += 4) {
1311 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1312 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1da177e4
LT		 1313 }
1314
fc32b0e2
LB		 1315 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1316 u8 *a = addr->da_addr;
1317 int table;
324ff2c1 1318
fc32b0e2
LB		 1319 if (addr->da_addrlen != 6)
1320 continue;
1da177e4 1321
fc32b0e2
LB		 1322 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1323 table = SPECIAL_MCAST_TABLE(mp->port_num);
1324 set_filter_table_entry(mp, table, a[5]);
1325 } else {
1326 int crc = addr_crc(a);
1da177e4 1327
fc32b0e2
LB		 1328 table = OTHER_MCAST_TABLE(mp->port_num);
1329 set_filter_table_entry(mp, table, crc);
1330 }
1331 }
c9df406f 1332}
c8aaea25 1333
c8aaea25 1334
c9df406f 1335/* rx/tx queue initialisation ***********************************************/
64da80a2 1336static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1337{
64da80a2 1338 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1339 struct rx_desc *rx_desc;
1340 int size;
c9df406f
LB		 1341 int i;
1342
64da80a2
LB		 1343 rxq->index = index;
1344
8a578111
LB		 1345 rxq->rx_ring_size = mp->default_rx_ring_size;
1346
1347 rxq->rx_desc_count = 0;
1348 rxq->rx_curr_desc = 0;
1349 rxq->rx_used_desc = 0;
1350
1351 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1352
64da80a2 1353 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1354 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1355 mp->rx_desc_sram_size);
1356 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1357 } else {
1358 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1359 &rxq->rx_desc_dma,
1360 GFP_KERNEL);
f7ea3337
PJ		 1361 }
1362
8a578111
LB		 1363 if (rxq->rx_desc_area == NULL) {
1364 dev_printk(KERN_ERR, &mp->dev->dev,
1365 "can't allocate rx ring (%d bytes)\n", size);
1366 goto out;
1367 }
1368 memset(rxq->rx_desc_area, 0, size);
1da177e4 1369
8a578111
LB		 1370 rxq->rx_desc_area_size = size;
1371 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1372 GFP_KERNEL);
1373 if (rxq->rx_skb == NULL) {
1374 dev_printk(KERN_ERR, &mp->dev->dev,
1375 "can't allocate rx skb ring\n");
1376 goto out_free;
1377 }
1378
1379 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1380 for (i = 0; i < rxq->rx_ring_size; i++) {
1381 int nexti = (i + 1) % rxq->rx_ring_size;
1382 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1383 nexti * sizeof(struct rx_desc);
1384 }
1385
1386 init_timer(&rxq->rx_oom);
1387 rxq->rx_oom.data = (unsigned long)rxq;
1388 rxq->rx_oom.function = rxq_refill_timer_wrapper;
1389
1390 return 0;
1391
1392
1393out_free:
64da80a2 1394 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size)
8a578111
LB		 1395 iounmap(rxq->rx_desc_area);
1396 else
1397 dma_free_coherent(NULL, size,
1398 rxq->rx_desc_area,
1399 rxq->rx_desc_dma);
1400
1401out:
1402 return -ENOMEM;
c9df406f 1403}
c8aaea25 1404
8a578111 1405static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1406{
8a578111
LB		 1407 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1408 int i;
1409
1410 rxq_disable(rxq);
c8aaea25 1411
8a578111 1412 del_timer_sync(&rxq->rx_oom);
c9df406f 1413
8a578111
LB		 1414 for (i = 0; i < rxq->rx_ring_size; i++) {
1415 if (rxq->rx_skb[i]) {
1416 dev_kfree_skb(rxq->rx_skb[i]);
1417 rxq->rx_desc_count--;
1da177e4 1418 }
c8aaea25 1419 }
1da177e4 1420
8a578111
LB		 1421 if (rxq->rx_desc_count) {
1422 dev_printk(KERN_ERR, &mp->dev->dev,
1423 "error freeing rx ring -- %d skbs stuck\n",
1424 rxq->rx_desc_count);
1425 }
1426
64da80a2
LB		 1427 if (rxq->index == mp->rxq_primary &&
1428 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1429 iounmap(rxq->rx_desc_area);
c9df406f 1430 else
8a578111
LB		 1431 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1432 rxq->rx_desc_area, rxq->rx_desc_dma);
1433
1434 kfree(rxq->rx_skb);
c9df406f 1435}
1da177e4 1436
3d6b35bc 1437static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1438{
3d6b35bc 1439 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1440 struct tx_desc *tx_desc;
1441 int size;
c9df406f 1442 int i;
1da177e4 1443
3d6b35bc
LB		 1444 txq->index = index;
1445
13d64285
LB		 1446 txq->tx_ring_size = mp->default_tx_ring_size;
1447
1448 txq->tx_desc_count = 0;
1449 txq->tx_curr_desc = 0;
1450 txq->tx_used_desc = 0;
1451
1452 size = txq->tx_ring_size * sizeof(struct tx_desc);
1453
3d6b35bc 1454 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) {
13d64285
LB		 1455 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1456 mp->tx_desc_sram_size);
1457 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1458 } else {
1459 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1460 &txq->tx_desc_dma,
1461 GFP_KERNEL);
1462 }
1463
1464 if (txq->tx_desc_area == NULL) {
1465 dev_printk(KERN_ERR, &mp->dev->dev,
1466 "can't allocate tx ring (%d bytes)\n", size);
1467 goto out;
c9df406f 1468 }
13d64285
LB		 1469 memset(txq->tx_desc_area, 0, size);
1470
1471 txq->tx_desc_area_size = size;
1472 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1473 GFP_KERNEL);
1474 if (txq->tx_skb == NULL) {
1475 dev_printk(KERN_ERR, &mp->dev->dev,
1476 "can't allocate tx skb ring\n");
1477 goto out_free;
1478 }
1479
1480 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1481 for (i = 0; i < txq->tx_ring_size; i++) {
1482 int nexti = (i + 1) % txq->tx_ring_size;
1483 tx_desc[i].next_desc_ptr = txq->tx_desc_dma +
1484 nexti * sizeof(struct tx_desc);
1485 }
1486
1487 return 0;
1488
c9df406f 1489
13d64285 1490out_free:
3d6b35bc 1491 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size)
13d64285
LB		 1492 iounmap(txq->tx_desc_area);
1493 else
1494 dma_free_coherent(NULL, size,
1495 txq->tx_desc_area,
1496 txq->tx_desc_dma);
c9df406f 1497
13d64285
LB		 1498out:
1499 return -ENOMEM;
c8aaea25 1500}
1da177e4 1501
13d64285 1502static void txq_reclaim(struct tx_queue *txq, int force)
c8aaea25 1503{
13d64285 1504 struct mv643xx_eth_private *mp = txq_to_mp(txq);
c8aaea25 1505 unsigned long flags;
1da177e4 1506
13d64285
LB		 1507 spin_lock_irqsave(&mp->lock, flags);
1508 while (txq->tx_desc_count > 0) {
1509 int tx_index;
1510 struct tx_desc *desc;
1511 u32 cmd_sts;
1512 struct sk_buff *skb;
1513 dma_addr_t addr;
1514 int count;
4d64e718 1515
13d64285
LB		 1516 tx_index = txq->tx_used_desc;
1517 desc = &txq->tx_desc_area[tx_index];
c9df406f 1518 cmd_sts = desc->cmd_sts;
4d64e718 1519
13d64285
LB		 1520 if (!force && (cmd_sts & BUFFER_OWNED_BY_DMA))
1521 break;
1da177e4 1522
13d64285
LB		 1523 txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size;
1524 txq->tx_desc_count--;
1da177e4 1525
c9df406f
LB		 1526 addr = desc->buf_ptr;
1527 count = desc->byte_cnt;
13d64285
LB		 1528 skb = txq->tx_skb[tx_index];
1529 txq->tx_skb[tx_index] = NULL;
c8aaea25 1530
cc9754b3 1531 if (cmd_sts & ERROR_SUMMARY) {
13d64285
LB		 1532 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1533 mp->dev->stats.tx_errors++;
c9df406f 1534 }
1da177e4 1535
13d64285
LB		 1536 /*
1537 * Drop mp->lock while we free the skb.
1538 */
c9df406f 1539 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 1540
cc9754b3 1541 if (cmd_sts & TX_FIRST_DESC)
c9df406f
LB		 1542 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1543 else
1544 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
c2e5b352 1545
c9df406f
LB		 1546 if (skb)
1547 dev_kfree_skb_irq(skb);
63c9e549 1548
13d64285 1549 spin_lock_irqsave(&mp->lock, flags);
c9df406f 1550 }
13d64285 1551 spin_unlock_irqrestore(&mp->lock, flags);
c9df406f 1552}
1da177e4 1553
13d64285 1554static void txq_deinit(struct tx_queue *txq)
c9df406f 1555{
13d64285 1556 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 1557
13d64285
LB		 1558 txq_disable(txq);
1559 txq_reclaim(txq, 1);
1da177e4 1560
13d64285 1561 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 1562
3d6b35bc
LB		 1563 if (txq->index == mp->txq_primary &&
1564 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 1565 iounmap(txq->tx_desc_area);
c9df406f 1566 else
13d64285
LB		 1567 dma_free_coherent(NULL, txq->tx_desc_area_size,
1568 txq->tx_desc_area, txq->tx_desc_dma);
1569
1570 kfree(txq->tx_skb);
c9df406f 1571}
1da177e4 1572
1da177e4 1573
c9df406f 1574/* netdev ops and related ***************************************************/
fc32b0e2 1575static void update_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
c9df406f 1576{
13d64285
LB		 1577 u32 pscr_o;
1578 u32 pscr_n;
1da177e4 1579
13d64285 1580 pscr_o = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
63c9e549 1581
c9df406f 1582 /* clear speed, duplex and rx buffer size fields */
13d64285
LB		 1583 pscr_n = pscr_o & ~(SET_MII_SPEED_TO_100 |
1584 SET_GMII_SPEED_TO_1000 |
1585 SET_FULL_DUPLEX_MODE |
1586 MAX_RX_PACKET_MASK);
1da177e4 1587
fc32b0e2 1588 if (speed == SPEED_1000) {
13d64285
LB		 1589 pscr_n |= SET_GMII_SPEED_TO_1000 | MAX_RX_PACKET_9700BYTE;
1590 } else {
fc32b0e2 1591 if (speed == SPEED_100)
13d64285
LB		 1592 pscr_n |= SET_MII_SPEED_TO_100;
1593 pscr_n |= MAX_RX_PACKET_1522BYTE;
c9df406f 1594 }
1da177e4 1595
fc32b0e2 1596 if (duplex == DUPLEX_FULL)
13d64285
LB		 1597 pscr_n |= SET_FULL_DUPLEX_MODE;
1598
1599 if (pscr_n != pscr_o) {
1600 if ((pscr_o & SERIAL_PORT_ENABLE) == 0)
1601 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
c9df406f 1602 else {
3d6b35bc
LB		 1603 int i;
1604
1605 for (i = 0; i < 8; i++)
1606 if (mp->txq_mask & (1 << i))
1607 txq_disable(mp->txq + i);
1608
13d64285
LB		 1609 pscr_o &= ~SERIAL_PORT_ENABLE;
1610 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_o);
1611 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1612 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
3d6b35bc
LB		 1613
1614 for (i = 0; i < 8; i++)
1615 if (mp->txq_mask & (1 << i))
1616 txq_enable(mp->txq + i);
c9df406f
LB		 1617 }
1618 }
1619}
84dd619e 1620
fc32b0e2 1621static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
c9df406f
LB		 1622{
1623 struct net_device *dev = (struct net_device *)dev_id;
e5371493 1624 struct mv643xx_eth_private *mp = netdev_priv(dev);
fc32b0e2
LB		 1625 u32 int_cause;
1626 u32 int_cause_ext;
226bb6b7 1627 u32 txq_active;
ce4e2e45 1628
226bb6b7
LB		 1629 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1630 (INT_TX_END | INT_RX | INT_EXT);
fc32b0e2
LB		 1631 if (int_cause == 0)
1632 return IRQ_NONE;
1633
1634 int_cause_ext = 0;
cc9754b3 1635 if (int_cause & INT_EXT) {
13d64285 1636 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
073a345c 1637 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
13d64285 1638 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
c9df406f 1639 }
1da177e4 1640
fc32b0e2 1641 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK)) {
c9df406f 1642 if (mii_link_ok(&mp->mii)) {
13d64285 1643 struct ethtool_cmd cmd;
3d6b35bc 1644 int i;
13d64285 1645
c9df406f 1646 mii_ethtool_gset(&mp->mii, &cmd);
fc32b0e2 1647 update_pscr(mp, cmd.speed, cmd.duplex);
3d6b35bc
LB		 1648 for (i = 0; i < 8; i++)
1649 if (mp->txq_mask & (1 << i))
1650 txq_enable(mp->txq + i);
1651
c9df406f
LB		 1652 if (!netif_carrier_ok(dev)) {
1653 netif_carrier_on(dev);
3d6b35bc 1654 __txq_maybe_wake(mp->txq + mp->txq_primary);
c9df406f
LB		 1655 }
1656 } else if (netif_carrier_ok(dev)) {
1657 netif_stop_queue(dev);
1658 netif_carrier_off(dev);
1659 }
1660 }
1da177e4 1661
64da80a2
LB		 1662 /*
1663 * RxBuffer or RxError set for any of the 8 queues?
1664 */
e5371493 1665#ifdef MV643XX_ETH_NAPI
cc9754b3 1666 if (int_cause & INT_RX) {
13d64285 1667 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
13d64285 1668 rdl(mp, INT_MASK(mp->port_num));
1da177e4 1669
c9df406f 1670 netif_rx_schedule(dev, &mp->napi);
84dd619e 1671 }
c9df406f 1672#else
64da80a2
LB		 1673 if (int_cause & INT_RX) {
1674 int i;
1675
1676 for (i = 7; i >= 0; i--)
1677 if (mp->rxq_mask & (1 << i))
1678 rxq_process(mp->rxq + i, INT_MAX);
1679 }
c9df406f 1680#endif
fc32b0e2 1681
226bb6b7
LB		 1682 txq_active = rdl(mp, TXQ_COMMAND(mp->port_num));
1683
3d6b35bc
LB		 1684 /*
1685 * TxBuffer or TxError set for any of the 8 queues?
1686 */
13d64285 1687 if (int_cause_ext & INT_EXT_TX) {
3d6b35bc
LB		 1688 int i;
1689
1690 for (i = 0; i < 8; i++)
1691 if (mp->txq_mask & (1 << i))
1692 txq_reclaim(mp->txq + i, 0);
226bb6b7 1693 }
3d6b35bc 1694
226bb6b7
LB		 1695 /*
1696 * Any TxEnd interrupts?
1697 */
1698 if (int_cause & INT_TX_END) {
1699 int i;
1700
1701 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
1702 for (i = 0; i < 8; i++) {
1703 struct tx_queue *txq = mp->txq + i;
1704 if (txq->tx_desc_count && !((txq_active >> i) & 1))
1705 txq_enable(txq);
1706 }
1707 }
1708
1709 /*
1710 * Enough space again in the primary TX queue for a full packet?
1711 */
1712 if (int_cause_ext & INT_EXT_TX) {
1713 struct tx_queue *txq = mp->txq + mp->txq_primary;
1714 __txq_maybe_wake(txq);
13d64285 1715 }
1da177e4 1716
c9df406f 1717 return IRQ_HANDLED;
1da177e4
LT		 1718}
1719
e5371493 1720static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 1721{
fc32b0e2 1722 unsigned int data;
1da177e4 1723
fc32b0e2
LB		 1724 smi_reg_read(mp, mp->phy_addr, 0, &data);
1725 data |= 0x8000;
1726 smi_reg_write(mp, mp->phy_addr, 0, data);
1da177e4 1727
c9df406f
LB		 1728 do {
1729 udelay(1);
fc32b0e2
LB		 1730 smi_reg_read(mp, mp->phy_addr, 0, &data);
1731 } while (data & 0x8000);
1da177e4
LT		 1732}
1733
fc32b0e2 1734static void port_start(struct mv643xx_eth_private *mp)
1da177e4 1735{
d0412d96
JC		 1736 u32 pscr;
1737 struct ethtool_cmd ethtool_cmd;
8a578111 1738 int i;
1da177e4 1739
8a578111
LB		 1740 /*
1741 * Configure basic link parameters.
1742 */
1743 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1744 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
1745 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1746 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1747 DISABLE_AUTO_NEG_SPEED_GMII |
1748 DISABLE_AUTO_NEG_FOR_DUPLEX |
1749 DO_NOT_FORCE_LINK_FAIL |
1750 SERIAL_PORT_CONTROL_RESERVED;
1751 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1752 pscr |= SERIAL_PORT_ENABLE;
1753 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1da177e4 1754
8a578111
LB		 1755 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1756
fc32b0e2 1757 mv643xx_eth_get_settings(mp->dev, &ethtool_cmd);
8a578111 1758 phy_reset(mp);
fc32b0e2 1759 mv643xx_eth_set_settings(mp->dev, &ethtool_cmd);
1da177e4 1760
13d64285
LB		 1761 /*
1762 * Configure TX path and queues.
1763 */
89df5fdc 1764 tx_set_rate(mp, 1000000000, 16777216);
3d6b35bc
LB		 1765 for (i = 0; i < 8; i++) {
1766 struct tx_queue *txq = mp->txq + i;
1767 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, i);
13d64285
LB		 1768 u32 addr;
1769
3d6b35bc
LB		 1770 if ((mp->txq_mask & (1 << i)) == 0)
1771 continue;
1772
13d64285
LB		 1773 addr = (u32)txq->tx_desc_dma;
1774 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
1775 wrl(mp, off, addr);
89df5fdc
LB		 1776
1777 txq_set_rate(txq, 1000000000, 16777216);
1778 txq_set_fixed_prio_mode(txq);
13d64285
LB		 1779 }
1780
fc32b0e2
LB		 1781 /*
1782 * Add configured unicast address to address filter table.
1783 */
1784 uc_addr_set(mp, mp->dev->dev_addr);
1da177e4 1785
d9a073ea
LB		 1786 /*
1787 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1788 * frames to RX queue #0.
1789 */
8a578111 1790 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
01999873 1791
376489a2
LB		 1792 /*
1793 * Treat BPDUs as normal multicasts, and disable partition mode.
1794 */
8a578111 1795 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
01999873 1796
8a578111 1797 /*
64da80a2 1798 * Enable the receive queues.
8a578111 1799 */
64da80a2
LB		 1800 for (i = 0; i < 8; i++) {
1801 struct rx_queue *rxq = mp->rxq + i;
1802 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
8a578111 1803 u32 addr;
1da177e4 1804
64da80a2
LB		 1805 if ((mp->rxq_mask & (1 << i)) == 0)
1806 continue;
1807
8a578111
LB		 1808 addr = (u32)rxq->rx_desc_dma;
1809 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1810 wrl(mp, off, addr);
1da177e4 1811
8a578111
LB		 1812 rxq_enable(rxq);
1813 }
1da177e4
LT		 1814}
1815
ffd86bbe 1816static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 1817{
c9df406f 1818 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
773fc3ee 1819 u32 val;
1da177e4 1820
773fc3ee
LB		 1821 val = rdl(mp, SDMA_CONFIG(mp->port_num));
1822 if (mp->shared->extended_rx_coal_limit) {
1823 if (coal > 0xffff)
1824 coal = 0xffff;
1825 val &= ~0x023fff80;
1826 val |= (coal & 0x8000) << 10;
1827 val |= (coal & 0x7fff) << 7;
1828 } else {
1829 if (coal > 0x3fff)
1830 coal = 0x3fff;
1831 val &= ~0x003fff00;
1832 val |= (coal & 0x3fff) << 8;
1833 }
1834 wrl(mp, SDMA_CONFIG(mp->port_num), val);
1da177e4
LT		 1835}
1836
ffd86bbe 1837static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 1838{
c9df406f 1839 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 1840
fc32b0e2
LB		 1841 if (coal > 0x3fff)
1842 coal = 0x3fff;
1843 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
16e03018
DF		 1844}
1845
c9df406f 1846static int mv643xx_eth_open(struct net_device *dev)
16e03018 1847{
e5371493 1848 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1849 int err;
64da80a2 1850 int i;
16e03018 1851
fc32b0e2
LB		 1852 wrl(mp, INT_CAUSE(mp->port_num), 0);
1853 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
1854 rdl(mp, INT_CAUSE_EXT(mp->port_num));
c9df406f 1855
fc32b0e2
LB		 1856 err = request_irq(dev->irq, mv643xx_eth_irq,
1857 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
1858 dev->name, dev);
c9df406f 1859 if (err) {
fc32b0e2 1860 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
c9df406f 1861 return -EAGAIN;
16e03018
DF		 1862 }
1863
fc32b0e2 1864 init_mac_tables(mp);
16e03018 1865
64da80a2
LB		 1866 for (i = 0; i < 8; i++) {
1867 if ((mp->rxq_mask & (1 << i)) == 0)
1868 continue;
1869
1870 err = rxq_init(mp, i);
1871 if (err) {
1872 while (--i >= 0)
1873 if (mp->rxq_mask & (1 << i))
1874 rxq_deinit(mp->rxq + i);
1875 goto out;
1876 }
1877
1878 rxq_refill(mp->rxq + i);
1879 }
8a578111 1880
3d6b35bc
LB		 1881 for (i = 0; i < 8; i++) {
1882 if ((mp->txq_mask & (1 << i)) == 0)
1883 continue;
1884
1885 err = txq_init(mp, i);
1886 if (err) {
1887 while (--i >= 0)
1888 if (mp->txq_mask & (1 << i))
1889 txq_deinit(mp->txq + i);
1890 goto out_free;
1891 }
1892 }
16e03018 1893
e5371493 1894#ifdef MV643XX_ETH_NAPI
c9df406f
LB		 1895 napi_enable(&mp->napi);
1896#endif
16e03018 1897
fc32b0e2 1898 port_start(mp);
16e03018 1899
ffd86bbe
LB		 1900 set_rx_coal(mp, 0);
1901 set_tx_coal(mp, 0);
16e03018 1902
fc32b0e2
LB		 1903 wrl(mp, INT_MASK_EXT(mp->port_num),
1904 INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
16e03018 1905
226bb6b7 1906 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
16e03018 1907
c9df406f
LB		 1908 return 0;
1909
13d64285 1910
fc32b0e2 1911out_free:
64da80a2
LB		 1912 for (i = 0; i < 8; i++)
1913 if (mp->rxq_mask & (1 << i))
1914 rxq_deinit(mp->rxq + i);
fc32b0e2 1915out:
c9df406f
LB		 1916 free_irq(dev->irq, dev);
1917
1918 return err;
16e03018
DF		 1919}
1920
e5371493 1921static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 1922{
fc32b0e2 1923 unsigned int data;
64da80a2 1924 int i;
1da177e4 1925
64da80a2
LB		 1926 for (i = 0; i < 8; i++) {
1927 if (mp->rxq_mask & (1 << i))
1928 rxq_disable(mp->rxq + i);
3d6b35bc
LB		 1929 if (mp->txq_mask & (1 << i))
1930 txq_disable(mp->txq + i);
64da80a2 1931 }
13d64285
LB		 1932 while (!(rdl(mp, PORT_STATUS(mp->port_num)) & TX_FIFO_EMPTY))
1933 udelay(10);
1da177e4 1934
c9df406f 1935 /* Reset the Enable bit in the Configuration Register */
fc32b0e2
LB		 1936 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1937 data &= ~(SERIAL_PORT_ENABLE |
1938 DO_NOT_FORCE_LINK_FAIL |
1939 FORCE_LINK_PASS);
1940 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
1da177e4
LT		 1941}
1942
c9df406f 1943static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 1944{
e5371493 1945 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 1946 int i;
1da177e4 1947
fc32b0e2
LB		 1948 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1949 rdl(mp, INT_MASK(mp->port_num));
1da177e4 1950
e5371493 1951#ifdef MV643XX_ETH_NAPI
c9df406f
LB		 1952 napi_disable(&mp->napi);
1953#endif
1954 netif_carrier_off(dev);
1955 netif_stop_queue(dev);
1da177e4 1956
fc32b0e2
LB		 1957 free_irq(dev->irq, dev);
1958
cc9754b3 1959 port_reset(mp);
fc32b0e2 1960 mib_counters_update(mp);
1da177e4 1961
64da80a2
LB		 1962 for (i = 0; i < 8; i++) {
1963 if (mp->rxq_mask & (1 << i))
1964 rxq_deinit(mp->rxq + i);
3d6b35bc
LB		 1965 if (mp->txq_mask & (1 << i))
1966 txq_deinit(mp->txq + i);
64da80a2 1967 }
1da177e4 1968
c9df406f 1969 return 0;
1da177e4
LT		 1970}
1971
fc32b0e2 1972static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 1973{
e5371493 1974 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1975
c9df406f 1976 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
1da177e4
LT		 1977}
1978
c9df406f 1979static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 1980{
89df5fdc
LB		 1981 struct mv643xx_eth_private *mp = netdev_priv(dev);
1982
fc32b0e2 1983 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 1984 return -EINVAL;
1da177e4 1985
c9df406f 1986 dev->mtu = new_mtu;
89df5fdc
LB		 1987 tx_set_rate(mp, 1000000000, 16777216);
1988
c9df406f
LB		 1989 if (!netif_running(dev))
1990 return 0;
1da177e4 1991
c9df406f
LB		 1992 /*
1993 * Stop and then re-open the interface. This will allocate RX
1994 * skbs of the new MTU.
1995 * There is a possible danger that the open will not succeed,
fc32b0e2 1996 * due to memory being full.
c9df406f
LB		 1997 */
1998 mv643xx_eth_stop(dev);
1999 if (mv643xx_eth_open(dev)) {
fc32b0e2
LB		 2000 dev_printk(KERN_ERR, &dev->dev,
2001 "fatal error on re-opening device after "
2002 "MTU change\n");
c9df406f
LB		 2003 }
2004
2005 return 0;
1da177e4
LT		 2006}
2007
fc32b0e2 2008static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2009{
fc32b0e2 2010 struct mv643xx_eth_private *mp;
1da177e4 2011
fc32b0e2
LB		 2012 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2013 if (netif_running(mp->dev)) {
2014 netif_stop_queue(mp->dev);
c9df406f 2015
fc32b0e2
LB		 2016 port_reset(mp);
2017 port_start(mp);
c9df406f 2018
3d6b35bc 2019 __txq_maybe_wake(mp->txq + mp->txq_primary);
fc32b0e2 2020 }
c9df406f
LB		 2021}
2022
c9df406f 2023static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2024{
e5371493 2025 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2026
fc32b0e2 2027 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
d0412d96 2028
c9df406f 2029 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2030}
2031
c9df406f 2032#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2033static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2034{
fc32b0e2 2035 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2036
fc32b0e2
LB		 2037 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2038 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2039
fc32b0e2 2040 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2041
226bb6b7 2042 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_CAUSE_EXT);
9f8dd319 2043}
c9df406f 2044#endif
9f8dd319 2045
fc32b0e2 2046static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
9f8dd319 2047{
e5371493 2048 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f
LB		 2049 int val;
2050
fc32b0e2
LB		 2051 smi_reg_read(mp, addr, reg, &val);
2052
c9df406f 2053 return val;
9f8dd319
DF		 2054}
2055
fc32b0e2 2056static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
9f8dd319 2057{
e5371493 2058 struct mv643xx_eth_private *mp = netdev_priv(dev);
fc32b0e2 2059 smi_reg_write(mp, addr, reg, val);
c9df406f 2060}
9f8dd319 2061
9f8dd319 2062
c9df406f 2063/* platform glue ************************************************************/
e5371493
LB		 2064static void
2065mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2066 struct mbus_dram_target_info *dram)
c9df406f 2067{
cc9754b3 2068 void __iomem *base = msp->base;
c9df406f
LB		 2069 u32 win_enable;
2070 u32 win_protect;
2071 int i;
9f8dd319 2072
c9df406f
LB		 2073 for (i = 0; i < 6; i++) {
2074 writel(0, base + WINDOW_BASE(i));
2075 writel(0, base + WINDOW_SIZE(i));
2076 if (i < 4)
2077 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2078 }
2079
c9df406f
LB		 2080 win_enable = 0x3f;
2081 win_protect = 0;
2082
2083 for (i = 0; i < dram->num_cs; i++) {
2084 struct mbus_dram_window *cs = dram->cs + i;
2085
2086 writel((cs->base & 0xffff0000) |
2087 (cs->mbus_attr << 8) |
2088 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2089 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2090
2091 win_enable &= ~(1 << i);
2092 win_protect |= 3 << (2 * i);
2093 }
2094
2095 writel(win_enable, base + WINDOW_BAR_ENABLE);
2096 msp->win_protect = win_protect;
9f8dd319
DF		 2097}
2098
773fc3ee
LB		 2099static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2100{
2101 /*
2102 * Check whether we have a 14-bit coal limit field in bits
2103 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2104 * SDMA config register.
2105 */
2106 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2107 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2108 msp->extended_rx_coal_limit = 1;
2109 else
2110 msp->extended_rx_coal_limit = 0;
2111}
2112
c9df406f 2113static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2114{
e5371493 2115 static int mv643xx_eth_version_printed = 0;
c9df406f 2116 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2117 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 2118 struct resource *res;
2119 int ret;
9f8dd319 2120
e5371493 2121 if (!mv643xx_eth_version_printed++)
c9df406f 2122 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
9f8dd319 2123
c9df406f
LB		 2124 ret = -EINVAL;
2125 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2126 if (res == NULL)
2127 goto out;
9f8dd319 2128
c9df406f
LB		 2129 ret = -ENOMEM;
2130 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2131 if (msp == NULL)
2132 goto out;
2133 memset(msp, 0, sizeof(*msp));
2134
cc9754b3
LB		 2135 msp->base = ioremap(res->start, res->end - res->start + 1);
2136 if (msp->base == NULL)
c9df406f
LB		 2137 goto out_free;
2138
2139 spin_lock_init(&msp->phy_lock);
c9df406f
LB		 2140
2141 /*
2142 * (Re-)program MBUS remapping windows if we are asked to.
2143 */
2144 if (pd != NULL && pd->dram != NULL)
2145 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2146
fc32b0e2
LB		 2147 /*
2148 * Detect hardware parameters.
2149 */
2150 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
773fc3ee 2151 infer_hw_params(msp);
fc32b0e2
LB		 2152
2153 platform_set_drvdata(pdev, msp);
2154
c9df406f
LB		 2155 return 0;
2156
2157out_free:
2158 kfree(msp);
2159out:
2160 return ret;
2161}
2162
2163static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2164{
e5371493 2165 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
c9df406f 2166
cc9754b3 2167 iounmap(msp->base);
c9df406f
LB		 2168 kfree(msp);
2169
2170 return 0;
9f8dd319
DF		 2171}
2172
c9df406f 2173static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2174 .probe = mv643xx_eth_shared_probe,
2175 .remove = mv643xx_eth_shared_remove,
c9df406f 2176 .driver = {
fc32b0e2 2177 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2178 .owner = THIS_MODULE,
2179 },
2180};
2181
e5371493 2182static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2183{
c9df406f 2184 int addr_shift = 5 * mp->port_num;
fc32b0e2 2185 u32 data;
1da177e4 2186
fc32b0e2
LB		 2187 data = rdl(mp, PHY_ADDR);
2188 data &= ~(0x1f << addr_shift);
2189 data |= (phy_addr & 0x1f) << addr_shift;
2190 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2191}
2192
e5371493 2193static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2194{
fc32b0e2
LB		 2195 unsigned int data;
2196
2197 data = rdl(mp, PHY_ADDR);
2198
2199 return (data >> (5 * mp->port_num)) & 0x1f;
2200}
2201
2202static void set_params(struct mv643xx_eth_private *mp,
2203 struct mv643xx_eth_platform_data *pd)
2204{
2205 struct net_device *dev = mp->dev;
2206
2207 if (is_valid_ether_addr(pd->mac_addr))
2208 memcpy(dev->dev_addr, pd->mac_addr, 6);
2209 else
2210 uc_addr_get(mp, dev->dev_addr);
2211
2212 if (pd->phy_addr == -1) {
2213 mp->shared_smi = NULL;
2214 mp->phy_addr = -1;
2215 } else {
2216 mp->shared_smi = mp->shared;
2217 if (pd->shared_smi != NULL)
2218 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2219
2220 if (pd->force_phy_addr || pd->phy_addr) {
2221 mp->phy_addr = pd->phy_addr & 0x3f;
2222 phy_addr_set(mp, mp->phy_addr);
2223 } else {
2224 mp->phy_addr = phy_addr_get(mp);
2225 }
2226 }
1da177e4 2227
fc32b0e2
LB		 2228 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2229 if (pd->rx_queue_size)
2230 mp->default_rx_ring_size = pd->rx_queue_size;
2231 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2232 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2233
64da80a2
LB		 2234 if (pd->rx_queue_mask)
2235 mp->rxq_mask = pd->rx_queue_mask;
2236 else
2237 mp->rxq_mask = 0x01;
2238 mp->rxq_primary = fls(mp->rxq_mask) - 1;
2239
fc32b0e2
LB		 2240 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2241 if (pd->tx_queue_size)
2242 mp->default_tx_ring_size = pd->tx_queue_size;
2243 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2244 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc
LB		 2245
2246 if (pd->tx_queue_mask)
2247 mp->txq_mask = pd->tx_queue_mask;
2248 else
2249 mp->txq_mask = 0x01;
2250 mp->txq_primary = fls(mp->txq_mask) - 1;
1da177e4
LT		 2251}
2252
e5371493 2253static int phy_detect(struct mv643xx_eth_private *mp)
1da177e4 2254{
fc32b0e2
LB		 2255 unsigned int data;
2256 unsigned int data2;
2257
2258 smi_reg_read(mp, mp->phy_addr, 0, &data);
2259 smi_reg_write(mp, mp->phy_addr, 0, data ^ 0x1000);
1da177e4 2260
fc32b0e2
LB		 2261 smi_reg_read(mp, mp->phy_addr, 0, &data2);
2262 if (((data ^ data2) & 0x1000) == 0)
2263 return -ENODEV;
1da177e4 2264
fc32b0e2 2265 smi_reg_write(mp, mp->phy_addr, 0, data);
1da177e4 2266
c9df406f 2267 return 0;
1da177e4
LT		 2268}
2269
fc32b0e2
LB		 2270static int phy_init(struct mv643xx_eth_private *mp,
2271 struct mv643xx_eth_platform_data *pd)
c28a4f89 2272{
fc32b0e2
LB		 2273 struct ethtool_cmd cmd;
2274 int err;
c28a4f89 2275
fc32b0e2
LB		 2276 err = phy_detect(mp);
2277 if (err) {
2278 dev_printk(KERN_INFO, &mp->dev->dev,
2279 "no PHY detected at addr %d\n", mp->phy_addr);
2280 return err;
2281 }
2282 phy_reset(mp);
2283
2284 mp->mii.phy_id = mp->phy_addr;
2285 mp->mii.phy_id_mask = 0x3f;
2286 mp->mii.reg_num_mask = 0x1f;
2287 mp->mii.dev = mp->dev;
2288 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2289 mp->mii.mdio_write = mv643xx_eth_mdio_write;
c28a4f89 2290
fc32b0e2 2291 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
c9df406f 2292
fc32b0e2
LB		 2293 memset(&cmd, 0, sizeof(cmd));
2294
2295 cmd.port = PORT_MII;
2296 cmd.transceiver = XCVR_INTERNAL;
2297 cmd.phy_address = mp->phy_addr;
2298 if (pd->speed == 0) {
2299 cmd.autoneg = AUTONEG_ENABLE;
2300 cmd.speed = SPEED_100;
2301 cmd.advertising = ADVERTISED_10baseT_Half |
2302 ADVERTISED_10baseT_Full |
2303 ADVERTISED_100baseT_Half |
2304 ADVERTISED_100baseT_Full;
c9df406f 2305 if (mp->mii.supports_gmii)
fc32b0e2 2306 cmd.advertising |= ADVERTISED_1000baseT_Full;
c9df406f 2307 } else {
fc32b0e2
LB		 2308 cmd.autoneg = AUTONEG_DISABLE;
2309 cmd.speed = pd->speed;
2310 cmd.duplex = pd->duplex;
c9df406f 2311 }
fc32b0e2
LB		 2312
2313 update_pscr(mp, cmd.speed, cmd.duplex);
2314 mv643xx_eth_set_settings(mp->dev, &cmd);
2315
2316 return 0;
c28a4f89
JC		 2317}
2318
c9df406f 2319static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2320{
c9df406f 2321 struct mv643xx_eth_platform_data *pd;
e5371493 2322 struct mv643xx_eth_private *mp;
c9df406f 2323 struct net_device *dev;
c9df406f 2324 struct resource *res;
c9df406f 2325 DECLARE_MAC_BUF(mac);
fc32b0e2 2326 int err;
1da177e4 2327
c9df406f
LB		 2328 pd = pdev->dev.platform_data;
2329 if (pd == NULL) {
fc32b0e2
LB		 2330 dev_printk(KERN_ERR, &pdev->dev,
2331 "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2332 return -ENODEV;
2333 }
1da177e4 2334
c9df406f 2335 if (pd->shared == NULL) {
fc32b0e2
LB		 2336 dev_printk(KERN_ERR, &pdev->dev,
2337 "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2338 return -ENODEV;
2339 }
8f518703 2340
e5371493 2341 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
c9df406f
LB		 2342 if (!dev)
2343 return -ENOMEM;
1da177e4 2344
c9df406f 2345 mp = netdev_priv(dev);
fc32b0e2
LB		 2346 platform_set_drvdata(pdev, mp);
2347
2348 mp->shared = platform_get_drvdata(pd->shared);
2349 mp->port_num = pd->port_number;
2350
c9df406f 2351 mp->dev = dev;
e5371493
LB		 2352#ifdef MV643XX_ETH_NAPI
2353 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
c9df406f 2354#endif
1da177e4 2355
fc32b0e2
LB		 2356 set_params(mp, pd);
2357
2358 spin_lock_init(&mp->lock);
2359
2360 mib_counters_clear(mp);
2361 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2362
2363 err = phy_init(mp, pd);
2364 if (err)
2365 goto out;
2366 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2367
2368
c9df406f
LB		 2369 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2370 BUG_ON(!res);
2371 dev->irq = res->start;
1da177e4 2372
fc32b0e2 2373 dev->hard_start_xmit = mv643xx_eth_xmit;
c9df406f
LB		 2374 dev->open = mv643xx_eth_open;
2375 dev->stop = mv643xx_eth_stop;
c9df406f 2376 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
fc32b0e2
LB		 2377 dev->set_mac_address = mv643xx_eth_set_mac_address;
2378 dev->do_ioctl = mv643xx_eth_ioctl;
2379 dev->change_mtu = mv643xx_eth_change_mtu;
c9df406f 2380 dev->tx_timeout = mv643xx_eth_tx_timeout;
c9df406f 2381#ifdef CONFIG_NET_POLL_CONTROLLER
e5371493 2382 dev->poll_controller = mv643xx_eth_netpoll;
c9df406f 2383#endif
c9df406f
LB		 2384 dev->watchdog_timeo = 2 * HZ;
2385 dev->base_addr = 0;
1da177e4 2386
e5371493 2387#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
b4de9051 2388 /*
c9df406f
LB		 2389 * Zero copy can only work if we use Discovery II memory. Else, we will
2390 * have to map the buffers to ISA memory which is only 16 MB
b4de9051 2391 */
c9df406f 2392 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
c9df406f 2393#endif
1da177e4 2394
fc32b0e2 2395 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2396
c9df406f 2397 if (mp->shared->win_protect)
fc32b0e2 2398 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2399
c9df406f
LB		 2400 err = register_netdev(dev);
2401 if (err)
2402 goto out;
1da177e4 2403
fc32b0e2
LB		 2404 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2405 mp->port_num, print_mac(mac, dev->dev_addr));
1da177e4 2406
c9df406f 2407 if (dev->features & NETIF_F_SG)
fc32b0e2 2408 dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n");
1da177e4 2409
c9df406f 2410 if (dev->features & NETIF_F_IP_CSUM)
fc32b0e2 2411 dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n");
1da177e4 2412
e5371493 2413#ifdef MV643XX_ETH_NAPI
fc32b0e2 2414 dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n");
c9df406f 2415#endif
1da177e4 2416
13d64285 2417 if (mp->tx_desc_sram_size > 0)
fc32b0e2 2418 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
1da177e4 2419
c9df406f 2420 return 0;
1da177e4 2421
c9df406f
LB		 2422out:
2423 free_netdev(dev);
1da177e4 2424
c9df406f 2425 return err;
1da177e4
LT		 2426}
2427
c9df406f 2428static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2429{
fc32b0e2 2430 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2431
fc32b0e2 2432 unregister_netdev(mp->dev);
c9df406f 2433 flush_scheduled_work();
fc32b0e2 2434 free_netdev(mp->dev);
c9df406f 2435
c9df406f 2436 platform_set_drvdata(pdev, NULL);
fc32b0e2 2437
c9df406f 2438 return 0;
1da177e4
LT		 2439}
2440
c9df406f 2441static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2442{
fc32b0e2 2443 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 2444
c9df406f 2445 /* Mask all interrupts on ethernet port */
fc32b0e2
LB		 2446 wrl(mp, INT_MASK(mp->port_num), 0);
2447 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2448
fc32b0e2
LB		 2449 if (netif_running(mp->dev))
2450 port_reset(mp);
d0412d96
JC		 2451}
2452
c9df406f 2453static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 2454 .probe = mv643xx_eth_probe,
2455 .remove = mv643xx_eth_remove,
2456 .shutdown = mv643xx_eth_shutdown,
c9df406f 2457 .driver = {
fc32b0e2 2458 .name = MV643XX_ETH_NAME,
c9df406f
LB		 2459 .owner = THIS_MODULE,
2460 },
2461};
2462
e5371493 2463static int __init mv643xx_eth_init_module(void)
d0412d96 2464{
c9df406f 2465 int rc;
d0412d96 2466
c9df406f
LB		 2467 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2468 if (!rc) {
2469 rc = platform_driver_register(&mv643xx_eth_driver);
2470 if (rc)
2471 platform_driver_unregister(&mv643xx_eth_shared_driver);
2472 }
fc32b0e2 2473
c9df406f 2474 return rc;
d0412d96 2475}
fc32b0e2 2476module_init(mv643xx_eth_init_module);
d0412d96 2477
e5371493 2478static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 2479{
c9df406f
LB		 2480 platform_driver_unregister(&mv643xx_eth_driver);
2481 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 2482}
e5371493 2483module_exit(mv643xx_eth_cleanup_module);
1da177e4 2484
fc32b0e2
LB		 2485MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani "
2486 "and Dale Farnsworth");
c9df406f 2487MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 2488MODULE_LICENSE("GPL");
c9df406f 2489MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 2490MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux kernel - Deliverables
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