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mv643xx_eth: add tx rate control
[deliverable/linux.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
1da177e4
LT		 41#include <linux/tcp.h>
42#include <linux/udp.h>
43#include <linux/etherdevice.h>
1da177e4
LT		 44#include <linux/delay.h>
45#include <linux/ethtool.h>
d052d1be 46#include <linux/platform_device.h>
fbd6a754
LB		 47#include <linux/module.h>
48#include <linux/kernel.h>
49#include <linux/spinlock.h>
50#include <linux/workqueue.h>
51#include <linux/mii.h>
fbd6a754 52#include <linux/mv643xx_eth.h>
1da177e4
LT		 53#include <asm/io.h>
54#include <asm/types.h>
1da177e4 55#include <asm/system.h>
fbd6a754 56
e5371493
LB		 57static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58static char mv643xx_eth_driver_version[] = "1.0";
c9df406f 59
e5371493
LB		 60#define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61#define MV643XX_ETH_NAPI
62#define MV643XX_ETH_TX_FAST_REFILL
fbd6a754 63
e5371493 64#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
fbd6a754
LB		 65#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
66#else
67#define MAX_DESCS_PER_SKB 1
68#endif
69
fbd6a754
LB		 70/*
71 * Registers shared between all ports.
72 */
3cb4667c
LB		 73#define PHY_ADDR 0x0000
74#define SMI_REG 0x0004
75#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78#define WINDOW_BAR_ENABLE 0x0290
79#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 80
81/*
82 * Per-port registers.
83 */
3cb4667c 84#define PORT_CONFIG(p) (0x0400 + ((p) << 10))
d9a073ea 85#define UNICAST_PROMISCUOUS_MODE 0x00000001
3cb4667c
LB		 86#define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
87#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
88#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
89#define SDMA_CONFIG(p) (0x041c + ((p) << 10))
90#define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
91#define PORT_STATUS(p) (0x0444 + ((p) << 10))
a2a41689 92#define TX_FIFO_EMPTY 0x00000400
3cb4667c 93#define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
89df5fdc
LB		 94#define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
95#define TX_BW_RATE(p) (0x0450 + ((p) << 10))
3cb4667c 96#define TX_BW_MTU(p) (0x0458 + ((p) << 10))
89df5fdc 97#define TX_BW_BURST(p) (0x045c + ((p) << 10))
3cb4667c 98#define INT_CAUSE(p) (0x0460 + ((p) << 10))
073a345c
LB		 99#define INT_RX 0x00000804
100#define INT_EXT 0x00000002
3cb4667c 101#define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
073a345c
LB		 102#define INT_EXT_LINK 0x00100000
103#define INT_EXT_PHY 0x00010000
104#define INT_EXT_TX_ERROR_0 0x00000100
105#define INT_EXT_TX_0 0x00000001
106#define INT_EXT_TX 0x00000101
3cb4667c
LB		 107#define INT_MASK(p) (0x0468 + ((p) << 10))
108#define INT_MASK_EXT(p) (0x046c + ((p) << 10))
109#define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
110#define RXQ_CURRENT_DESC_PTR(p) (0x060c + ((p) << 10))
111#define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
112#define TXQ_CURRENT_DESC_PTR(p) (0x06c0 + ((p) << 10))
89df5fdc
LB		 113#define TXQ_BW_TOKENS(p) (0x0700 + ((p) << 10))
114#define TXQ_BW_CONF(p) (0x0704 + ((p) << 10))
115#define TXQ_BW_WRR_CONF(p) (0x0708 + ((p) << 10))
3cb4667c
LB		 116#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
117#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
118#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
119#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 120
2679a550
LB		 121
122/*
123 * SDMA configuration register.
124 */
fbd6a754 125#define RX_BURST_SIZE_4_64BIT (2 << 1)
fbd6a754 126#define BLM_RX_NO_SWAP (1 << 4)
fbd6a754 127#define BLM_TX_NO_SWAP (1 << 5)
fbd6a754 128#define TX_BURST_SIZE_4_64BIT (2 << 22)
fbd6a754
LB		 129
130#if defined(__BIG_ENDIAN)
131#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
132 RX_BURST_SIZE_4_64BIT | \
fbd6a754
LB		 133 TX_BURST_SIZE_4_64BIT
134#elif defined(__LITTLE_ENDIAN)
135#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
136 RX_BURST_SIZE_4_64BIT | \
137 BLM_RX_NO_SWAP | \
138 BLM_TX_NO_SWAP | \
fbd6a754
LB		 139 TX_BURST_SIZE_4_64BIT
140#else
141#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
142#endif
143
2beff77b
LB		 144
145/*
146 * Port serial control register.
147 */
148#define SET_MII_SPEED_TO_100 (1 << 24)
149#define SET_GMII_SPEED_TO_1000 (1 << 23)
150#define SET_FULL_DUPLEX_MODE (1 << 21)
fbd6a754 151#define MAX_RX_PACKET_1522BYTE (1 << 17)
fbd6a754
LB		 152#define MAX_RX_PACKET_9700BYTE (5 << 17)
153#define MAX_RX_PACKET_MASK (7 << 17)
2beff77b
LB		 154#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
155#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
156#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
157#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
158#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
159#define FORCE_LINK_PASS (1 << 1)
160#define SERIAL_PORT_ENABLE (1 << 0)
fbd6a754 161
cc9754b3
LB		 162#define DEFAULT_RX_QUEUE_SIZE 400
163#define DEFAULT_TX_QUEUE_SIZE 800
fbd6a754 164
fbd6a754 165
7ca72a3b
LB		 166/*
167 * RX/TX descriptors.
fbd6a754
LB		 168 */
169#if defined(__BIG_ENDIAN)
cc9754b3 170struct rx_desc {
fbd6a754
LB		 171 u16 byte_cnt; /* Descriptor buffer byte count */
172 u16 buf_size; /* Buffer size */
173 u32 cmd_sts; /* Descriptor command status */
174 u32 next_desc_ptr; /* Next descriptor pointer */
175 u32 buf_ptr; /* Descriptor buffer pointer */
176};
177
cc9754b3 178struct tx_desc {
fbd6a754
LB		 179 u16 byte_cnt; /* buffer byte count */
180 u16 l4i_chk; /* CPU provided TCP checksum */
181 u32 cmd_sts; /* Command/status field */
182 u32 next_desc_ptr; /* Pointer to next descriptor */
183 u32 buf_ptr; /* pointer to buffer for this descriptor*/
184};
185#elif defined(__LITTLE_ENDIAN)
cc9754b3 186struct rx_desc {
fbd6a754
LB		 187 u32 cmd_sts; /* Descriptor command status */
188 u16 buf_size; /* Buffer size */
189 u16 byte_cnt; /* Descriptor buffer byte count */
190 u32 buf_ptr; /* Descriptor buffer pointer */
191 u32 next_desc_ptr; /* Next descriptor pointer */
192};
193
cc9754b3 194struct tx_desc {
fbd6a754
LB		 195 u32 cmd_sts; /* Command/status field */
196 u16 l4i_chk; /* CPU provided TCP checksum */
197 u16 byte_cnt; /* buffer byte count */
198 u32 buf_ptr; /* pointer to buffer for this descriptor*/
199 u32 next_desc_ptr; /* Pointer to next descriptor */
200};
201#else
202#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
203#endif
204
7ca72a3b 205/* RX & TX descriptor command */
cc9754b3 206#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 207
208/* RX & TX descriptor status */
cc9754b3 209#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 210
211/* RX descriptor status */
cc9754b3
LB		 212#define LAYER_4_CHECKSUM_OK 0x40000000
213#define RX_ENABLE_INTERRUPT 0x20000000
214#define RX_FIRST_DESC 0x08000000
215#define RX_LAST_DESC 0x04000000
7ca72a3b
LB		 216
217/* TX descriptor command */
cc9754b3
LB		 218#define TX_ENABLE_INTERRUPT 0x00800000
219#define GEN_CRC 0x00400000
220#define TX_FIRST_DESC 0x00200000
221#define TX_LAST_DESC 0x00100000
222#define ZERO_PADDING 0x00080000
223#define GEN_IP_V4_CHECKSUM 0x00040000
224#define GEN_TCP_UDP_CHECKSUM 0x00020000
225#define UDP_FRAME 0x00010000
7ca72a3b 226
cc9754b3 227#define TX_IHL_SHIFT 11
7ca72a3b
LB		 228
229
c9df406f 230/* global *******************************************************************/
e5371493 231struct mv643xx_eth_shared_private {
fc32b0e2
LB		 232 /*
233 * Ethernet controller base address.
234 */
cc9754b3 235 void __iomem *base;
c9df406f 236
fc32b0e2
LB		 237 /*
238 * Protects access to SMI_REG, which is shared between ports.
239 */
c9df406f
LB		 240 spinlock_t phy_lock;
241
fc32b0e2
LB		 242 /*
243 * Per-port MBUS window access register value.
244 */
c9df406f
LB		 245 u32 win_protect;
246
fc32b0e2
LB		 247 /*
248 * Hardware-specific parameters.
249 */
c9df406f
LB		 250 unsigned int t_clk;
251};
252
253
254/* per-port *****************************************************************/
e5371493 255struct mib_counters {
fbd6a754
LB		 256 u64 good_octets_received;
257 u32 bad_octets_received;
258 u32 internal_mac_transmit_err;
259 u32 good_frames_received;
260 u32 bad_frames_received;
261 u32 broadcast_frames_received;
262 u32 multicast_frames_received;
263 u32 frames_64_octets;
264 u32 frames_65_to_127_octets;
265 u32 frames_128_to_255_octets;
266 u32 frames_256_to_511_octets;
267 u32 frames_512_to_1023_octets;
268 u32 frames_1024_to_max_octets;
269 u64 good_octets_sent;
270 u32 good_frames_sent;
271 u32 excessive_collision;
272 u32 multicast_frames_sent;
273 u32 broadcast_frames_sent;
274 u32 unrec_mac_control_received;
275 u32 fc_sent;
276 u32 good_fc_received;
277 u32 bad_fc_received;
278 u32 undersize_received;
279 u32 fragments_received;
280 u32 oversize_received;
281 u32 jabber_received;
282 u32 mac_receive_error;
283 u32 bad_crc_event;
284 u32 collision;
285 u32 late_collision;
286};
287
8a578111
LB		 288struct rx_queue {
289 int rx_ring_size;
290
291 int rx_desc_count;
292 int rx_curr_desc;
293 int rx_used_desc;
294
295 struct rx_desc *rx_desc_area;
296 dma_addr_t rx_desc_dma;
297 int rx_desc_area_size;
298 struct sk_buff **rx_skb;
299
300 struct timer_list rx_oom;
301};
302
13d64285
LB		 303struct tx_queue {
304 int tx_ring_size;
fbd6a754 305
13d64285
LB		 306 int tx_desc_count;
307 int tx_curr_desc;
308 int tx_used_desc;
fbd6a754 309
5daffe94 310 struct tx_desc *tx_desc_area;
fbd6a754
LB		 311 dma_addr_t tx_desc_dma;
312 int tx_desc_area_size;
313 struct sk_buff **tx_skb;
13d64285
LB		 314};
315
316struct mv643xx_eth_private {
317 struct mv643xx_eth_shared_private *shared;
fc32b0e2 318 int port_num;
13d64285 319
fc32b0e2 320 struct net_device *dev;
fbd6a754 321
fc32b0e2
LB		 322 struct mv643xx_eth_shared_private *shared_smi;
323 int phy_addr;
fbd6a754 324
fbd6a754 325 spinlock_t lock;
fbd6a754 326
fc32b0e2
LB		 327 struct mib_counters mib_counters;
328 struct work_struct tx_timeout_task;
fbd6a754 329 struct mii_if_info mii;
8a578111
LB		 330
331 /*
332 * RX state.
333 */
334 int default_rx_ring_size;
335 unsigned long rx_desc_sram_addr;
336 int rx_desc_sram_size;
337 struct napi_struct napi;
338 struct rx_queue rxq[1];
13d64285
LB		 339
340 /*
341 * TX state.
342 */
343 int default_tx_ring_size;
344 unsigned long tx_desc_sram_addr;
345 int tx_desc_sram_size;
346 struct tx_queue txq[1];
347#ifdef MV643XX_ETH_TX_FAST_REFILL
348 int tx_clean_threshold;
349#endif
fbd6a754 350};
1da177e4 351
fbd6a754 352
c9df406f 353/* port register accessors **************************************************/
e5371493 354static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 355{
cc9754b3 356 return readl(mp->shared->base + offset);
c9df406f 357}
fbd6a754 358
e5371493 359static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 360{
cc9754b3 361 writel(data, mp->shared->base + offset);
c9df406f 362}
fbd6a754 363
fbd6a754 364
c9df406f 365/* rxq/txq helper functions *************************************************/
8a578111 366static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 367{
8a578111 368 return container_of(rxq, struct mv643xx_eth_private, rxq[0]);
c9df406f 369}
fbd6a754 370
13d64285
LB		 371static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
372{
373 return container_of(txq, struct mv643xx_eth_private, txq[0]);
374}
375
8a578111 376static void rxq_enable(struct rx_queue *rxq)
c9df406f 377{
8a578111
LB		 378 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
379 wrl(mp, RXQ_COMMAND(mp->port_num), 1);
380}
1da177e4 381
8a578111
LB		 382static void rxq_disable(struct rx_queue *rxq)
383{
384 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
385 u8 mask = 1;
1da177e4 386
8a578111
LB		 387 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
388 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
389 udelay(10);
c9df406f
LB		 390}
391
13d64285 392static void txq_enable(struct tx_queue *txq)
1da177e4 393{
13d64285
LB		 394 struct mv643xx_eth_private *mp = txq_to_mp(txq);
395 wrl(mp, TXQ_COMMAND(mp->port_num), 1);
1da177e4
LT		 396}
397
13d64285 398static void txq_disable(struct tx_queue *txq)
1da177e4 399{
13d64285
LB		 400 struct mv643xx_eth_private *mp = txq_to_mp(txq);
401 u8 mask = 1;
c9df406f 402
13d64285
LB		 403 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
404 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
405 udelay(10);
406}
407
408static void __txq_maybe_wake(struct tx_queue *txq)
409{
410 struct mv643xx_eth_private *mp = txq_to_mp(txq);
411
412 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB)
413 netif_wake_queue(mp->dev);
1da177e4
LT		 414}
415
c9df406f
LB		 416
417/* rx ***********************************************************************/
13d64285 418static void txq_reclaim(struct tx_queue *txq, int force);
c9df406f 419
8a578111 420static void rxq_refill(struct rx_queue *rxq)
1da177e4 421{
8a578111 422 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
c9df406f 423 unsigned long flags;
1da177e4 424
c9df406f 425 spin_lock_irqsave(&mp->lock, flags);
c0d0f2ca 426
8a578111
LB		 427 while (rxq->rx_desc_count < rxq->rx_ring_size) {
428 int skb_size;
de34f225
LB		 429 struct sk_buff *skb;
430 int unaligned;
431 int rx;
432
8a578111
LB		 433 /*
434 * Reserve 2+14 bytes for an ethernet header (the
435 * hardware automatically prepends 2 bytes of dummy
436 * data to each received packet), 4 bytes for a VLAN
437 * header, and 4 bytes for the trailing FCS -- 24
438 * bytes total.
439 */
440 skb_size = mp->dev->mtu + 24;
441
442 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
de34f225 443 if (skb == NULL)
1da177e4 444 break;
de34f225 445
908b637f 446 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
b44cd572 447 if (unaligned)
908b637f 448 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
de34f225 449
8a578111
LB		 450 rxq->rx_desc_count++;
451 rx = rxq->rx_used_desc;
452 rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size;
de34f225 453
8a578111
LB		 454 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
455 skb_size, DMA_FROM_DEVICE);
456 rxq->rx_desc_area[rx].buf_size = skb_size;
457 rxq->rx_skb[rx] = skb;
de34f225 458 wmb();
8a578111 459 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
de34f225
LB		 460 RX_ENABLE_INTERRUPT;
461 wmb();
462
fc32b0e2
LB		 463 /*
464 * The hardware automatically prepends 2 bytes of
465 * dummy data to each received packet, so that the
466 * IP header ends up 16-byte aligned.
467 */
468 skb_reserve(skb, 2);
1da177e4 469 }
de34f225 470
8a578111
LB		 471 if (rxq->rx_desc_count == 0) {
472 rxq->rx_oom.expires = jiffies + (HZ / 10);
473 add_timer(&rxq->rx_oom);
1da177e4 474 }
de34f225
LB		 475
476 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4
LT		 477}
478
8a578111 479static inline void rxq_refill_timer_wrapper(unsigned long data)
1da177e4 480{
8a578111 481 rxq_refill((struct rx_queue *)data);
1da177e4
LT		 482}
483
8a578111 484static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 485{
8a578111
LB		 486 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
487 struct net_device_stats *stats = &mp->dev->stats;
488 int rx;
1da177e4 489
8a578111
LB		 490 rx = 0;
491 while (rx < budget) {
fc32b0e2 492 struct rx_desc *rx_desc;
96587661 493 unsigned int cmd_sts;
fc32b0e2 494 struct sk_buff *skb;
96587661 495 unsigned long flags;
d344bff9 496
96587661 497 spin_lock_irqsave(&mp->lock, flags);
ff561eef 498
8a578111 499 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 500
96587661
LB		 501 cmd_sts = rx_desc->cmd_sts;
502 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
503 spin_unlock_irqrestore(&mp->lock, flags);
504 break;
505 }
506 rmb();
1da177e4 507
8a578111
LB		 508 skb = rxq->rx_skb[rxq->rx_curr_desc];
509 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 510
8a578111 511 rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size;
ff561eef 512
96587661 513 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 514
fc32b0e2
LB		 515 dma_unmap_single(NULL, rx_desc->buf_ptr + 2,
516 mp->dev->mtu + 24, DMA_FROM_DEVICE);
8a578111
LB		 517 rxq->rx_desc_count--;
518 rx++;
b1dd9ca1 519
468d09f8
DF		 520 /*
521 * Update statistics.
fc32b0e2
LB		 522 *
523 * Note that the descriptor byte count includes 2 dummy
524 * bytes automatically inserted by the hardware at the
525 * start of the packet (which we don't count), and a 4
526 * byte CRC at the end of the packet (which we do count).
468d09f8 527 */
1da177e4 528 stats->rx_packets++;
fc32b0e2 529 stats->rx_bytes += rx_desc->byte_cnt - 2;
96587661 530
1da177e4 531 /*
fc32b0e2
LB		 532 * In case we received a packet without first / last bits
533 * on, or the error summary bit is set, the packet needs
534 * to be dropped.
1da177e4 535 */
96587661 536 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 537 (RX_FIRST_DESC | RX_LAST_DESC))
96587661 538 || (cmd_sts & ERROR_SUMMARY)) {
1da177e4 539 stats->rx_dropped++;
fc32b0e2 540
96587661 541 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 542 (RX_FIRST_DESC | RX_LAST_DESC)) {
1da177e4 543 if (net_ratelimit())
fc32b0e2
LB		 544 dev_printk(KERN_ERR, &mp->dev->dev,
545 "received packet spanning "
546 "multiple descriptors\n");
1da177e4 547 }
fc32b0e2 548
96587661 549 if (cmd_sts & ERROR_SUMMARY)
1da177e4
LT		 550 stats->rx_errors++;
551
552 dev_kfree_skb_irq(skb);
553 } else {
554 /*
555 * The -4 is for the CRC in the trailer of the
556 * received packet
557 */
fc32b0e2 558 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
1da177e4 559
96587661 560 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
1da177e4
LT		 561 skb->ip_summed = CHECKSUM_UNNECESSARY;
562 skb->csum = htons(
96587661 563 (cmd_sts & 0x0007fff8) >> 3);
1da177e4 564 }
8a578111 565 skb->protocol = eth_type_trans(skb, mp->dev);
e5371493 566#ifdef MV643XX_ETH_NAPI
1da177e4
LT		 567 netif_receive_skb(skb);
568#else
569 netif_rx(skb);
570#endif
571 }
fc32b0e2 572
8a578111 573 mp->dev->last_rx = jiffies;
1da177e4 574 }
fc32b0e2 575
8a578111 576 rxq_refill(rxq);
1da177e4 577
8a578111 578 return rx;
1da177e4
LT		 579}
580
e5371493 581#ifdef MV643XX_ETH_NAPI
e5371493 582static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
d0412d96 583{
8a578111
LB		 584 struct mv643xx_eth_private *mp;
585 int rx;
586
587 mp = container_of(napi, struct mv643xx_eth_private, napi);
d0412d96 588
e5371493 589#ifdef MV643XX_ETH_TX_FAST_REFILL
c9df406f 590 if (++mp->tx_clean_threshold > 5) {
13d64285 591 txq_reclaim(mp->txq, 0);
c9df406f 592 mp->tx_clean_threshold = 0;
d0412d96 593 }
c9df406f 594#endif
d0412d96 595
8a578111 596 rx = rxq_process(mp->rxq, budget);
d0412d96 597
8a578111
LB		 598 if (rx < budget) {
599 netif_rx_complete(mp->dev, napi);
600 wrl(mp, INT_CAUSE(mp->port_num), 0);
601 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
602 wrl(mp, INT_MASK(mp->port_num), INT_RX | INT_EXT);
d0412d96 603 }
c9df406f 604
8a578111 605 return rx;
d0412d96 606}
c9df406f 607#endif
d0412d96 608
c9df406f
LB		 609
610/* tx ***********************************************************************/
c9df406f 611static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 612{
13d64285 613 int frag;
1da177e4 614
c9df406f 615 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
13d64285
LB		 616 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
617 if (fragp->size <= 8 && fragp->page_offset & 7)
c9df406f 618 return 1;
1da177e4 619 }
13d64285 620
c9df406f
LB		 621 return 0;
622}
7303fde8 623
13d64285 624static int txq_alloc_desc_index(struct tx_queue *txq)
c9df406f
LB		 625{
626 int tx_desc_curr;
d0412d96 627
13d64285 628 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
1da177e4 629
13d64285
LB		 630 tx_desc_curr = txq->tx_curr_desc;
631 txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size;
e4d00fa9 632
13d64285 633 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
468d09f8 634
c9df406f
LB		 635 return tx_desc_curr;
636}
468d09f8 637
13d64285 638static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 639{
13d64285 640 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 641 int frag;
1da177e4 642
13d64285
LB		 643 for (frag = 0; frag < nr_frags; frag++) {
644 skb_frag_t *this_frag;
645 int tx_index;
646 struct tx_desc *desc;
647
648 this_frag = &skb_shinfo(skb)->frags[frag];
649 tx_index = txq_alloc_desc_index(txq);
650 desc = &txq->tx_desc_area[tx_index];
651
652 /*
653 * The last fragment will generate an interrupt
654 * which will free the skb on TX completion.
655 */
656 if (frag == nr_frags - 1) {
657 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
658 ZERO_PADDING | TX_LAST_DESC |
659 TX_ENABLE_INTERRUPT;
660 txq->tx_skb[tx_index] = skb;
661 } else {
662 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
663 txq->tx_skb[tx_index] = NULL;
664 }
665
c9df406f
LB		 666 desc->l4i_chk = 0;
667 desc->byte_cnt = this_frag->size;
668 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
669 this_frag->page_offset,
670 this_frag->size,
671 DMA_TO_DEVICE);
672 }
1da177e4
LT		 673}
674
c9df406f
LB		 675static inline __be16 sum16_as_be(__sum16 sum)
676{
677 return (__force __be16)sum;
678}
1da177e4 679
13d64285 680static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 681{
13d64285 682 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 683 int tx_index;
cc9754b3 684 struct tx_desc *desc;
c9df406f
LB		 685 u32 cmd_sts;
686 int length;
1da177e4 687
cc9754b3 688 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
1da177e4 689
13d64285
LB		 690 tx_index = txq_alloc_desc_index(txq);
691 desc = &txq->tx_desc_area[tx_index];
c9df406f
LB		 692
693 if (nr_frags) {
13d64285 694 txq_submit_frag_skb(txq, skb);
c9df406f
LB		 695
696 length = skb_headlen(skb);
13d64285 697 txq->tx_skb[tx_index] = NULL;
c9df406f 698 } else {
cc9754b3 699 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
c9df406f 700 length = skb->len;
13d64285 701 txq->tx_skb[tx_index] = skb;
c9df406f
LB		 702 }
703
704 desc->byte_cnt = length;
705 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
706
707 if (skb->ip_summed == CHECKSUM_PARTIAL) {
708 BUG_ON(skb->protocol != htons(ETH_P_IP));
709
cc9754b3
LB		 710 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
711 GEN_IP_V4_CHECKSUM |
712 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
c9df406f
LB		 713
714 switch (ip_hdr(skb)->protocol) {
715 case IPPROTO_UDP:
cc9754b3 716 cmd_sts |= UDP_FRAME;
c9df406f
LB		 717 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
718 break;
719 case IPPROTO_TCP:
720 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
721 break;
722 default:
723 BUG();
724 }
725 } else {
726 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 727 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 728 desc->l4i_chk = 0;
729 }
730
731 /* ensure all other descriptors are written before first cmd_sts */
732 wmb();
733 desc->cmd_sts = cmd_sts;
734
735 /* ensure all descriptors are written before poking hardware */
736 wmb();
13d64285 737 txq_enable(txq);
c9df406f 738
13d64285 739 txq->tx_desc_count += nr_frags + 1;
1da177e4 740}
1da177e4 741
fc32b0e2 742static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 743{
e5371493 744 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 745 struct net_device_stats *stats = &dev->stats;
13d64285 746 struct tx_queue *txq;
c9df406f 747 unsigned long flags;
afdb57a2 748
c9df406f 749 BUG_ON(netif_queue_stopped(dev));
afdb57a2 750
c9df406f
LB		 751 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
752 stats->tx_dropped++;
fc32b0e2
LB		 753 dev_printk(KERN_DEBUG, &dev->dev,
754 "failed to linearize skb with tiny "
755 "unaligned fragment\n");
c9df406f
LB		 756 return NETDEV_TX_BUSY;
757 }
758
759 spin_lock_irqsave(&mp->lock, flags);
760
13d64285
LB		 761 txq = mp->txq;
762
763 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) {
c9df406f
LB		 764 printk(KERN_ERR "%s: transmit with queue full\n", dev->name);
765 netif_stop_queue(dev);
766 spin_unlock_irqrestore(&mp->lock, flags);
767 return NETDEV_TX_BUSY;
768 }
769
13d64285 770 txq_submit_skb(txq, skb);
c9df406f
LB		 771 stats->tx_bytes += skb->len;
772 stats->tx_packets++;
773 dev->trans_start = jiffies;
774
13d64285 775 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB)
c9df406f
LB		 776 netif_stop_queue(dev);
777
778 spin_unlock_irqrestore(&mp->lock, flags);
779
780 return NETDEV_TX_OK;
1da177e4
LT		 781}
782
c9df406f 783
89df5fdc
LB		 784/* tx rate control **********************************************************/
785/*
786 * Set total maximum TX rate (shared by all TX queues for this port)
787 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
788 */
789static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
790{
791 int token_rate;
792 int mtu;
793 int bucket_size;
794
795 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
796 if (token_rate > 1023)
797 token_rate = 1023;
798
799 mtu = (mp->dev->mtu + 255) >> 8;
800 if (mtu > 63)
801 mtu = 63;
802
803 bucket_size = (burst + 255) >> 8;
804 if (bucket_size > 65535)
805 bucket_size = 65535;
806
807 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
808 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
809 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
810}
811
812static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
813{
814 struct mv643xx_eth_private *mp = txq_to_mp(txq);
815 int token_rate;
816 int bucket_size;
817
818 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
819 if (token_rate > 1023)
820 token_rate = 1023;
821
822 bucket_size = (burst + 255) >> 8;
823 if (bucket_size > 65535)
824 bucket_size = 65535;
825
826 wrl(mp, TXQ_BW_TOKENS(mp->port_num), token_rate << 14);
827 wrl(mp, TXQ_BW_CONF(mp->port_num),
828 (bucket_size << 10) | token_rate);
829}
830
831static void txq_set_fixed_prio_mode(struct tx_queue *txq)
832{
833 struct mv643xx_eth_private *mp = txq_to_mp(txq);
834 int off;
835 u32 val;
836
837 /*
838 * Turn on fixed priority mode.
839 */
840 off = TXQ_FIX_PRIO_CONF(mp->port_num);
841
842 val = rdl(mp, off);
843 val |= 1;
844 wrl(mp, off, val);
845}
846
847static void txq_set_wrr(struct tx_queue *txq, int weight)
848{
849 struct mv643xx_eth_private *mp = txq_to_mp(txq);
850 int off;
851 u32 val;
852
853 /*
854 * Turn off fixed priority mode.
855 */
856 off = TXQ_FIX_PRIO_CONF(mp->port_num);
857
858 val = rdl(mp, off);
859 val &= ~1;
860 wrl(mp, off, val);
861
862 /*
863 * Configure WRR weight for this queue.
864 */
865 off = TXQ_BW_WRR_CONF(mp->port_num);
866
867 val = rdl(mp, off);
868 val = (val & ~0xff) | (weight & 0xff);
869 wrl(mp, off, val);
870}
871
872
c9df406f 873/* mii management interface *************************************************/
fc32b0e2
LB		 874#define SMI_BUSY 0x10000000
875#define SMI_READ_VALID 0x08000000
876#define SMI_OPCODE_READ 0x04000000
877#define SMI_OPCODE_WRITE 0x00000000
c9df406f 878
fc32b0e2
LB		 879static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr,
880 unsigned int reg, unsigned int *value)
1da177e4 881{
cc9754b3 882 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
c9df406f 883 unsigned long flags;
1da177e4
LT		 884 int i;
885
c9df406f
LB		 886 /* the SMI register is a shared resource */
887 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
888
889 /* wait for the SMI register to become available */
cc9754b3 890 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
e1bea50a 891 if (i == 1000) {
c9df406f
LB		 892 printk("%s: PHY busy timeout\n", mp->dev->name);
893 goto out;
894 }
e1bea50a 895 udelay(10);
1da177e4
LT		 896 }
897
fc32b0e2 898 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 899
c9df406f 900 /* now wait for the data to be valid */
cc9754b3 901 for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
e1bea50a 902 if (i == 1000) {
c9df406f
LB		 903 printk("%s: PHY read timeout\n", mp->dev->name);
904 goto out;
905 }
e1bea50a 906 udelay(10);
c9df406f
LB		 907 }
908
909 *value = readl(smi_reg) & 0xffff;
910out:
911 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1da177e4
LT		 912}
913
fc32b0e2
LB		 914static void smi_reg_write(struct mv643xx_eth_private *mp,
915 unsigned int addr,
916 unsigned int reg, unsigned int value)
1da177e4 917{
cc9754b3 918 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
c9df406f 919 unsigned long flags;
1da177e4
LT		 920 int i;
921
c9df406f
LB		 922 /* the SMI register is a shared resource */
923 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
924
925 /* wait for the SMI register to become available */
cc9754b3 926 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
e1bea50a 927 if (i == 1000) {
c9df406f
LB		 928 printk("%s: PHY busy timeout\n", mp->dev->name);
929 goto out;
930 }
e1bea50a 931 udelay(10);
1da177e4
LT		 932 }
933
fc32b0e2
LB		 934 writel(SMI_OPCODE_WRITE | (reg << 21) |
935 (addr << 16) | (value & 0xffff), smi_reg);
c9df406f
LB		 936out:
937 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
938}
1da177e4 939
c9df406f
LB		 940
941/* mib counters *************************************************************/
fc32b0e2 942static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 943{
fc32b0e2 944 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 945}
946
fc32b0e2 947static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 948{
fc32b0e2
LB		 949 int i;
950
951 for (i = 0; i < 0x80; i += 4)
952 mib_read(mp, i);
c9df406f 953}
d0412d96 954
fc32b0e2 955static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 956{
e5371493 957 struct mib_counters *p = &mp->mib_counters;
4b8e3655 958
fc32b0e2
LB		 959 p->good_octets_received += mib_read(mp, 0x00);
960 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
961 p->bad_octets_received += mib_read(mp, 0x08);
962 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
963 p->good_frames_received += mib_read(mp, 0x10);
964 p->bad_frames_received += mib_read(mp, 0x14);
965 p->broadcast_frames_received += mib_read(mp, 0x18);
966 p->multicast_frames_received += mib_read(mp, 0x1c);
967 p->frames_64_octets += mib_read(mp, 0x20);
968 p->frames_65_to_127_octets += mib_read(mp, 0x24);
969 p->frames_128_to_255_octets += mib_read(mp, 0x28);
970 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
971 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
972 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
973 p->good_octets_sent += mib_read(mp, 0x38);
974 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
975 p->good_frames_sent += mib_read(mp, 0x40);
976 p->excessive_collision += mib_read(mp, 0x44);
977 p->multicast_frames_sent += mib_read(mp, 0x48);
978 p->broadcast_frames_sent += mib_read(mp, 0x4c);
979 p->unrec_mac_control_received += mib_read(mp, 0x50);
980 p->fc_sent += mib_read(mp, 0x54);
981 p->good_fc_received += mib_read(mp, 0x58);
982 p->bad_fc_received += mib_read(mp, 0x5c);
983 p->undersize_received += mib_read(mp, 0x60);
984 p->fragments_received += mib_read(mp, 0x64);
985 p->oversize_received += mib_read(mp, 0x68);
986 p->jabber_received += mib_read(mp, 0x6c);
987 p->mac_receive_error += mib_read(mp, 0x70);
988 p->bad_crc_event += mib_read(mp, 0x74);
989 p->collision += mib_read(mp, 0x78);
990 p->late_collision += mib_read(mp, 0x7c);
d0412d96
JC		 991}
992
c9df406f
LB		 993
994/* ethtool ******************************************************************/
e5371493 995struct mv643xx_eth_stats {
c9df406f
LB		 996 char stat_string[ETH_GSTRING_LEN];
997 int sizeof_stat;
16820054
LB		 998 int netdev_off;
999 int mp_off;
c9df406f
LB		 1000};
1001
16820054
LB		 1002#define SSTAT(m) \
1003 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1004 offsetof(struct net_device, stats.m), -1 }
1005
1006#define MIBSTAT(m) \
1007 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1008 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1009
1010static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1011 SSTAT(rx_packets),
1012 SSTAT(tx_packets),
1013 SSTAT(rx_bytes),
1014 SSTAT(tx_bytes),
1015 SSTAT(rx_errors),
1016 SSTAT(tx_errors),
1017 SSTAT(rx_dropped),
1018 SSTAT(tx_dropped),
1019 MIBSTAT(good_octets_received),
1020 MIBSTAT(bad_octets_received),
1021 MIBSTAT(internal_mac_transmit_err),
1022 MIBSTAT(good_frames_received),
1023 MIBSTAT(bad_frames_received),
1024 MIBSTAT(broadcast_frames_received),
1025 MIBSTAT(multicast_frames_received),
1026 MIBSTAT(frames_64_octets),
1027 MIBSTAT(frames_65_to_127_octets),
1028 MIBSTAT(frames_128_to_255_octets),
1029 MIBSTAT(frames_256_to_511_octets),
1030 MIBSTAT(frames_512_to_1023_octets),
1031 MIBSTAT(frames_1024_to_max_octets),
1032 MIBSTAT(good_octets_sent),
1033 MIBSTAT(good_frames_sent),
1034 MIBSTAT(excessive_collision),
1035 MIBSTAT(multicast_frames_sent),
1036 MIBSTAT(broadcast_frames_sent),
1037 MIBSTAT(unrec_mac_control_received),
1038 MIBSTAT(fc_sent),
1039 MIBSTAT(good_fc_received),
1040 MIBSTAT(bad_fc_received),
1041 MIBSTAT(undersize_received),
1042 MIBSTAT(fragments_received),
1043 MIBSTAT(oversize_received),
1044 MIBSTAT(jabber_received),
1045 MIBSTAT(mac_receive_error),
1046 MIBSTAT(bad_crc_event),
1047 MIBSTAT(collision),
1048 MIBSTAT(late_collision),
c9df406f
LB		 1049};
1050
e5371493 1051static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
d0412d96 1052{
e5371493 1053 struct mv643xx_eth_private *mp = netdev_priv(dev);
d0412d96
JC		 1054 int err;
1055
1056 spin_lock_irq(&mp->lock);
1057 err = mii_ethtool_gset(&mp->mii, cmd);
1058 spin_unlock_irq(&mp->lock);
1059
fc32b0e2
LB		 1060 /*
1061 * The MAC does not support 1000baseT_Half.
1062 */
d0412d96
JC		 1063 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1064 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1065
1066 return err;
1067}
1068
e5371493 1069static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1070{
e5371493 1071 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6
DF		 1072 int err;
1073
fc32b0e2
LB		 1074 /*
1075 * The MAC does not support 1000baseT_Half.
1076 */
1077 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1078
c9df406f
LB		 1079 spin_lock_irq(&mp->lock);
1080 err = mii_ethtool_sset(&mp->mii, cmd);
1081 spin_unlock_irq(&mp->lock);
85cf572c 1082
c9df406f
LB		 1083 return err;
1084}
1da177e4 1085
fc32b0e2
LB		 1086static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1087 struct ethtool_drvinfo *drvinfo)
c9df406f 1088{
e5371493
LB		 1089 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1090 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 1091 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 1092 strncpy(drvinfo->bus_info, "platform", 32);
16820054 1093 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1094}
1da177e4 1095
fc32b0e2 1096static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1097{
e5371493 1098 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1099
c9df406f
LB		 1100 return mii_nway_restart(&mp->mii);
1101}
1da177e4 1102
c9df406f
LB		 1103static u32 mv643xx_eth_get_link(struct net_device *dev)
1104{
e5371493 1105 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1106
c9df406f
LB		 1107 return mii_link_ok(&mp->mii);
1108}
1da177e4 1109
fc32b0e2
LB		 1110static void mv643xx_eth_get_strings(struct net_device *dev,
1111 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1112{
1113 int i;
1da177e4 1114
fc32b0e2
LB		 1115 if (stringset == ETH_SS_STATS) {
1116 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1117 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1118 mv643xx_eth_stats[i].stat_string,
e5371493 1119 ETH_GSTRING_LEN);
c9df406f 1120 }
c9df406f
LB		 1121 }
1122}
1da177e4 1123
fc32b0e2
LB		 1124static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1125 struct ethtool_stats *stats,
1126 uint64_t *data)
c9df406f 1127{
fc32b0e2 1128 struct mv643xx_eth_private *mp = dev->priv;
c9df406f 1129 int i;
1da177e4 1130
fc32b0e2 1131 mib_counters_update(mp);
1da177e4 1132
16820054
LB		 1133 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1134 const struct mv643xx_eth_stats *stat;
1135 void *p;
1136
1137 stat = mv643xx_eth_stats + i;
1138
1139 if (stat->netdev_off >= 0)
1140 p = ((void *)mp->dev) + stat->netdev_off;
1141 else
1142 p = ((void *)mp) + stat->mp_off;
1143
1144 data[i] = (stat->sizeof_stat == 8) ?
1145 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1146 }
c9df406f 1147}
1da177e4 1148
fc32b0e2 1149static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1150{
fc32b0e2 1151 if (sset == ETH_SS_STATS)
16820054 1152 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1153
1154 return -EOPNOTSUPP;
c9df406f 1155}
1da177e4 1156
e5371493 1157static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1158 .get_settings = mv643xx_eth_get_settings,
1159 .set_settings = mv643xx_eth_set_settings,
1160 .get_drvinfo = mv643xx_eth_get_drvinfo,
1161 .nway_reset = mv643xx_eth_nway_reset,
1162 .get_link = mv643xx_eth_get_link,
c9df406f 1163 .set_sg = ethtool_op_set_sg,
fc32b0e2
LB		 1164 .get_strings = mv643xx_eth_get_strings,
1165 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
e5371493 1166 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1167};
1da177e4 1168
bea3348e 1169
c9df406f 1170/* address handling *********************************************************/
5daffe94 1171static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1172{
c9df406f
LB		 1173 unsigned int mac_h;
1174 unsigned int mac_l;
1da177e4 1175
fc32b0e2
LB		 1176 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1177 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1da177e4 1178
5daffe94
LB		 1179 addr[0] = (mac_h >> 24) & 0xff;
1180 addr[1] = (mac_h >> 16) & 0xff;
1181 addr[2] = (mac_h >> 8) & 0xff;
1182 addr[3] = mac_h & 0xff;
1183 addr[4] = (mac_l >> 8) & 0xff;
1184 addr[5] = mac_l & 0xff;
c9df406f 1185}
1da177e4 1186
e5371493 1187static void init_mac_tables(struct mv643xx_eth_private *mp)
c9df406f 1188{
fc32b0e2 1189 int i;
1da177e4 1190
fc32b0e2
LB		 1191 for (i = 0; i < 0x100; i += 4) {
1192 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1193 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
c9df406f 1194 }
fc32b0e2
LB		 1195
1196 for (i = 0; i < 0x10; i += 4)
1197 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
c9df406f 1198}
d0412d96 1199
e5371493 1200static void set_filter_table_entry(struct mv643xx_eth_private *mp,
fc32b0e2 1201 int table, unsigned char entry)
c9df406f
LB		 1202{
1203 unsigned int table_reg;
ab4384a6 1204
c9df406f 1205 /* Set "accepts frame bit" at specified table entry */
fc32b0e2
LB		 1206 table_reg = rdl(mp, table + (entry & 0xfc));
1207 table_reg |= 0x01 << (8 * (entry & 3));
1208 wrl(mp, table + (entry & 0xfc), table_reg);
1da177e4
LT		 1209}
1210
5daffe94 1211static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1da177e4 1212{
c9df406f
LB		 1213 unsigned int mac_h;
1214 unsigned int mac_l;
1215 int table;
1da177e4 1216
fc32b0e2
LB		 1217 mac_l = (addr[4] << 8) | addr[5];
1218 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
ff561eef 1219
fc32b0e2
LB		 1220 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1221 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1da177e4 1222
fc32b0e2 1223 table = UNICAST_TABLE(mp->port_num);
5daffe94 1224 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1da177e4
LT		 1225}
1226
fc32b0e2 1227static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1da177e4 1228{
e5371493 1229 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1230
fc32b0e2
LB		 1231 /* +2 is for the offset of the HW addr type */
1232 memcpy(dev->dev_addr, addr + 2, 6);
1233
cc9754b3
LB		 1234 init_mac_tables(mp);
1235 uc_addr_set(mp, dev->dev_addr);
1da177e4
LT		 1236
1237 return 0;
1238}
1239
69876569
LB		 1240static int addr_crc(unsigned char *addr)
1241{
1242 int crc = 0;
1243 int i;
1244
1245 for (i = 0; i < 6; i++) {
1246 int j;
1247
1248 crc = (crc ^ addr[i]) << 8;
1249 for (j = 7; j >= 0; j--) {
1250 if (crc & (0x100 << j))
1251 crc ^= 0x107 << j;
1252 }
1253 }
1254
1255 return crc;
1256}
1257
fc32b0e2 1258static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1da177e4 1259{
fc32b0e2
LB		 1260 struct mv643xx_eth_private *mp = netdev_priv(dev);
1261 u32 port_config;
1262 struct dev_addr_list *addr;
1263 int i;
c8aaea25 1264
fc32b0e2
LB		 1265 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1266 if (dev->flags & IFF_PROMISC)
1267 port_config |= UNICAST_PROMISCUOUS_MODE;
1268 else
1269 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1270 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1da177e4 1271
fc32b0e2
LB		 1272 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1273 int port_num = mp->port_num;
1274 u32 accept = 0x01010101;
c8aaea25 1275
fc32b0e2
LB		 1276 for (i = 0; i < 0x100; i += 4) {
1277 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1278 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1279 }
1280 return;
1281 }
c8aaea25 1282
fc32b0e2
LB		 1283 for (i = 0; i < 0x100; i += 4) {
1284 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1285 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1da177e4
LT		 1286 }
1287
fc32b0e2
LB		 1288 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1289 u8 *a = addr->da_addr;
1290 int table;
324ff2c1 1291
fc32b0e2
LB		 1292 if (addr->da_addrlen != 6)
1293 continue;
1da177e4 1294
fc32b0e2
LB		 1295 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1296 table = SPECIAL_MCAST_TABLE(mp->port_num);
1297 set_filter_table_entry(mp, table, a[5]);
1298 } else {
1299 int crc = addr_crc(a);
1da177e4 1300
fc32b0e2
LB		 1301 table = OTHER_MCAST_TABLE(mp->port_num);
1302 set_filter_table_entry(mp, table, crc);
1303 }
1304 }
c9df406f 1305}
c8aaea25 1306
c8aaea25 1307
c9df406f 1308/* rx/tx queue initialisation ***********************************************/
8a578111 1309static int rxq_init(struct mv643xx_eth_private *mp)
c9df406f 1310{
8a578111
LB		 1311 struct rx_queue *rxq = mp->rxq;
1312 struct rx_desc *rx_desc;
1313 int size;
c9df406f
LB		 1314 int i;
1315
8a578111
LB		 1316 rxq->rx_ring_size = mp->default_rx_ring_size;
1317
1318 rxq->rx_desc_count = 0;
1319 rxq->rx_curr_desc = 0;
1320 rxq->rx_used_desc = 0;
1321
1322 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1323
1324 if (size <= mp->rx_desc_sram_size) {
1325 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1326 mp->rx_desc_sram_size);
1327 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1328 } else {
1329 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1330 &rxq->rx_desc_dma,
1331 GFP_KERNEL);
f7ea3337
PJ		 1332 }
1333
8a578111
LB		 1334 if (rxq->rx_desc_area == NULL) {
1335 dev_printk(KERN_ERR, &mp->dev->dev,
1336 "can't allocate rx ring (%d bytes)\n", size);
1337 goto out;
1338 }
1339 memset(rxq->rx_desc_area, 0, size);
1da177e4 1340
8a578111
LB		 1341 rxq->rx_desc_area_size = size;
1342 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1343 GFP_KERNEL);
1344 if (rxq->rx_skb == NULL) {
1345 dev_printk(KERN_ERR, &mp->dev->dev,
1346 "can't allocate rx skb ring\n");
1347 goto out_free;
1348 }
1349
1350 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1351 for (i = 0; i < rxq->rx_ring_size; i++) {
1352 int nexti = (i + 1) % rxq->rx_ring_size;
1353 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1354 nexti * sizeof(struct rx_desc);
1355 }
1356
1357 init_timer(&rxq->rx_oom);
1358 rxq->rx_oom.data = (unsigned long)rxq;
1359 rxq->rx_oom.function = rxq_refill_timer_wrapper;
1360
1361 return 0;
1362
1363
1364out_free:
1365 if (size <= mp->rx_desc_sram_size)
1366 iounmap(rxq->rx_desc_area);
1367 else
1368 dma_free_coherent(NULL, size,
1369 rxq->rx_desc_area,
1370 rxq->rx_desc_dma);
1371
1372out:
1373 return -ENOMEM;
c9df406f 1374}
c8aaea25 1375
8a578111 1376static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1377{
8a578111
LB		 1378 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1379 int i;
1380
1381 rxq_disable(rxq);
c8aaea25 1382
8a578111 1383 del_timer_sync(&rxq->rx_oom);
c9df406f 1384
8a578111
LB		 1385 for (i = 0; i < rxq->rx_ring_size; i++) {
1386 if (rxq->rx_skb[i]) {
1387 dev_kfree_skb(rxq->rx_skb[i]);
1388 rxq->rx_desc_count--;
1da177e4 1389 }
c8aaea25 1390 }
1da177e4 1391
8a578111
LB		 1392 if (rxq->rx_desc_count) {
1393 dev_printk(KERN_ERR, &mp->dev->dev,
1394 "error freeing rx ring -- %d skbs stuck\n",
1395 rxq->rx_desc_count);
1396 }
1397
1398 if (rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1399 iounmap(rxq->rx_desc_area);
c9df406f 1400 else
8a578111
LB		 1401 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1402 rxq->rx_desc_area, rxq->rx_desc_dma);
1403
1404 kfree(rxq->rx_skb);
c9df406f 1405}
1da177e4 1406
13d64285 1407static int txq_init(struct mv643xx_eth_private *mp)
c9df406f 1408{
13d64285
LB		 1409 struct tx_queue *txq = mp->txq;
1410 struct tx_desc *tx_desc;
1411 int size;
c9df406f 1412 int i;
1da177e4 1413
13d64285
LB		 1414 txq->tx_ring_size = mp->default_tx_ring_size;
1415
1416 txq->tx_desc_count = 0;
1417 txq->tx_curr_desc = 0;
1418 txq->tx_used_desc = 0;
1419
1420 size = txq->tx_ring_size * sizeof(struct tx_desc);
1421
1422 if (size <= mp->tx_desc_sram_size) {
1423 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1424 mp->tx_desc_sram_size);
1425 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1426 } else {
1427 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1428 &txq->tx_desc_dma,
1429 GFP_KERNEL);
1430 }
1431
1432 if (txq->tx_desc_area == NULL) {
1433 dev_printk(KERN_ERR, &mp->dev->dev,
1434 "can't allocate tx ring (%d bytes)\n", size);
1435 goto out;
c9df406f 1436 }
13d64285
LB		 1437 memset(txq->tx_desc_area, 0, size);
1438
1439 txq->tx_desc_area_size = size;
1440 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1441 GFP_KERNEL);
1442 if (txq->tx_skb == NULL) {
1443 dev_printk(KERN_ERR, &mp->dev->dev,
1444 "can't allocate tx skb ring\n");
1445 goto out_free;
1446 }
1447
1448 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1449 for (i = 0; i < txq->tx_ring_size; i++) {
1450 int nexti = (i + 1) % txq->tx_ring_size;
1451 tx_desc[i].next_desc_ptr = txq->tx_desc_dma +
1452 nexti * sizeof(struct tx_desc);
1453 }
1454
1455 return 0;
1456
c9df406f 1457
13d64285
LB		 1458out_free:
1459 if (size <= mp->tx_desc_sram_size)
1460 iounmap(txq->tx_desc_area);
1461 else
1462 dma_free_coherent(NULL, size,
1463 txq->tx_desc_area,
1464 txq->tx_desc_dma);
c9df406f 1465
13d64285
LB		 1466out:
1467 return -ENOMEM;
c8aaea25 1468}
1da177e4 1469
13d64285 1470static void txq_reclaim(struct tx_queue *txq, int force)
c8aaea25 1471{
13d64285 1472 struct mv643xx_eth_private *mp = txq_to_mp(txq);
c8aaea25 1473 unsigned long flags;
1da177e4 1474
13d64285
LB		 1475 spin_lock_irqsave(&mp->lock, flags);
1476 while (txq->tx_desc_count > 0) {
1477 int tx_index;
1478 struct tx_desc *desc;
1479 u32 cmd_sts;
1480 struct sk_buff *skb;
1481 dma_addr_t addr;
1482 int count;
4d64e718 1483
13d64285
LB		 1484 tx_index = txq->tx_used_desc;
1485 desc = &txq->tx_desc_area[tx_index];
c9df406f 1486 cmd_sts = desc->cmd_sts;
4d64e718 1487
13d64285
LB		 1488 if (!force && (cmd_sts & BUFFER_OWNED_BY_DMA))
1489 break;
1da177e4 1490
13d64285
LB		 1491 txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size;
1492 txq->tx_desc_count--;
1da177e4 1493
c9df406f
LB		 1494 addr = desc->buf_ptr;
1495 count = desc->byte_cnt;
13d64285
LB		 1496 skb = txq->tx_skb[tx_index];
1497 txq->tx_skb[tx_index] = NULL;
c8aaea25 1498
cc9754b3 1499 if (cmd_sts & ERROR_SUMMARY) {
13d64285
LB		 1500 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1501 mp->dev->stats.tx_errors++;
c9df406f 1502 }
1da177e4 1503
13d64285
LB		 1504 /*
1505 * Drop mp->lock while we free the skb.
1506 */
c9df406f 1507 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 1508
cc9754b3 1509 if (cmd_sts & TX_FIRST_DESC)
c9df406f
LB		 1510 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1511 else
1512 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
c2e5b352 1513
c9df406f
LB		 1514 if (skb)
1515 dev_kfree_skb_irq(skb);
63c9e549 1516
13d64285 1517 spin_lock_irqsave(&mp->lock, flags);
c9df406f 1518 }
13d64285 1519 spin_unlock_irqrestore(&mp->lock, flags);
c9df406f 1520}
1da177e4 1521
13d64285 1522static void txq_deinit(struct tx_queue *txq)
c9df406f 1523{
13d64285 1524 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 1525
13d64285
LB		 1526 txq_disable(txq);
1527 txq_reclaim(txq, 1);
1da177e4 1528
13d64285 1529 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 1530
13d64285
LB		 1531 if (txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1532 iounmap(txq->tx_desc_area);
c9df406f 1533 else
13d64285
LB		 1534 dma_free_coherent(NULL, txq->tx_desc_area_size,
1535 txq->tx_desc_area, txq->tx_desc_dma);
1536
1537 kfree(txq->tx_skb);
c9df406f 1538}
1da177e4 1539
1da177e4 1540
c9df406f 1541/* netdev ops and related ***************************************************/
fc32b0e2 1542static void update_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
c9df406f 1543{
13d64285
LB		 1544 u32 pscr_o;
1545 u32 pscr_n;
1da177e4 1546
13d64285 1547 pscr_o = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
63c9e549 1548
c9df406f 1549 /* clear speed, duplex and rx buffer size fields */
13d64285
LB		 1550 pscr_n = pscr_o & ~(SET_MII_SPEED_TO_100 |
1551 SET_GMII_SPEED_TO_1000 |
1552 SET_FULL_DUPLEX_MODE |
1553 MAX_RX_PACKET_MASK);
1da177e4 1554
fc32b0e2 1555 if (speed == SPEED_1000) {
13d64285
LB		 1556 pscr_n |= SET_GMII_SPEED_TO_1000 | MAX_RX_PACKET_9700BYTE;
1557 } else {
fc32b0e2 1558 if (speed == SPEED_100)
13d64285
LB		 1559 pscr_n |= SET_MII_SPEED_TO_100;
1560 pscr_n |= MAX_RX_PACKET_1522BYTE;
c9df406f 1561 }
1da177e4 1562
fc32b0e2 1563 if (duplex == DUPLEX_FULL)
13d64285
LB		 1564 pscr_n |= SET_FULL_DUPLEX_MODE;
1565
1566 if (pscr_n != pscr_o) {
1567 if ((pscr_o & SERIAL_PORT_ENABLE) == 0)
1568 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
c9df406f 1569 else {
13d64285
LB		 1570 txq_disable(mp->txq);
1571 pscr_o &= ~SERIAL_PORT_ENABLE;
1572 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_o);
1573 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1574 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1575 txq_enable(mp->txq);
c9df406f
LB		 1576 }
1577 }
1578}
84dd619e 1579
fc32b0e2 1580static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
c9df406f
LB		 1581{
1582 struct net_device *dev = (struct net_device *)dev_id;
e5371493 1583 struct mv643xx_eth_private *mp = netdev_priv(dev);
fc32b0e2
LB		 1584 u32 int_cause;
1585 u32 int_cause_ext;
ce4e2e45 1586
13d64285 1587 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) & (INT_RX | INT_EXT);
fc32b0e2
LB		 1588 if (int_cause == 0)
1589 return IRQ_NONE;
1590
1591 int_cause_ext = 0;
cc9754b3 1592 if (int_cause & INT_EXT) {
13d64285 1593 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
073a345c 1594 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
13d64285 1595 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
c9df406f 1596 }
1da177e4 1597
fc32b0e2 1598 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK)) {
c9df406f 1599 if (mii_link_ok(&mp->mii)) {
13d64285
LB		 1600 struct ethtool_cmd cmd;
1601
c9df406f 1602 mii_ethtool_gset(&mp->mii, &cmd);
fc32b0e2 1603 update_pscr(mp, cmd.speed, cmd.duplex);
13d64285 1604 txq_enable(mp->txq);
c9df406f
LB		 1605 if (!netif_carrier_ok(dev)) {
1606 netif_carrier_on(dev);
13d64285 1607 __txq_maybe_wake(mp->txq);
c9df406f
LB		 1608 }
1609 } else if (netif_carrier_ok(dev)) {
1610 netif_stop_queue(dev);
1611 netif_carrier_off(dev);
1612 }
1613 }
1da177e4 1614
e5371493 1615#ifdef MV643XX_ETH_NAPI
cc9754b3 1616 if (int_cause & INT_RX) {
13d64285 1617 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
13d64285 1618 rdl(mp, INT_MASK(mp->port_num));
1da177e4 1619
c9df406f 1620 netif_rx_schedule(dev, &mp->napi);
84dd619e 1621 }
c9df406f 1622#else
cc9754b3 1623 if (int_cause & INT_RX)
8a578111 1624 rxq_process(mp->rxq, INT_MAX);
c9df406f 1625#endif
fc32b0e2 1626
13d64285
LB		 1627 if (int_cause_ext & INT_EXT_TX) {
1628 txq_reclaim(mp->txq, 0);
1629 __txq_maybe_wake(mp->txq);
1630 }
1da177e4 1631
c9df406f 1632 return IRQ_HANDLED;
1da177e4
LT		 1633}
1634
e5371493 1635static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 1636{
fc32b0e2 1637 unsigned int data;
1da177e4 1638
fc32b0e2
LB		 1639 smi_reg_read(mp, mp->phy_addr, 0, &data);
1640 data |= 0x8000;
1641 smi_reg_write(mp, mp->phy_addr, 0, data);
1da177e4 1642
c9df406f
LB		 1643 do {
1644 udelay(1);
fc32b0e2
LB		 1645 smi_reg_read(mp, mp->phy_addr, 0, &data);
1646 } while (data & 0x8000);
1da177e4
LT		 1647}
1648
fc32b0e2 1649static void port_start(struct mv643xx_eth_private *mp)
1da177e4 1650{
d0412d96
JC		 1651 u32 pscr;
1652 struct ethtool_cmd ethtool_cmd;
8a578111 1653 int i;
1da177e4 1654
8a578111
LB		 1655 /*
1656 * Configure basic link parameters.
1657 */
1658 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1659 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
1660 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1661 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1662 DISABLE_AUTO_NEG_SPEED_GMII |
1663 DISABLE_AUTO_NEG_FOR_DUPLEX |
1664 DO_NOT_FORCE_LINK_FAIL |
1665 SERIAL_PORT_CONTROL_RESERVED;
1666 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1667 pscr |= SERIAL_PORT_ENABLE;
1668 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1da177e4 1669
8a578111
LB		 1670 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1671
fc32b0e2 1672 mv643xx_eth_get_settings(mp->dev, &ethtool_cmd);
8a578111 1673 phy_reset(mp);
fc32b0e2 1674 mv643xx_eth_set_settings(mp->dev, &ethtool_cmd);
1da177e4 1675
13d64285
LB		 1676 /*
1677 * Configure TX path and queues.
1678 */
89df5fdc 1679 tx_set_rate(mp, 1000000000, 16777216);
13d64285
LB		 1680 for (i = 0; i < 1; i++) {
1681 struct tx_queue *txq = mp->txq;
1682 int off = TXQ_CURRENT_DESC_PTR(mp->port_num);
1683 u32 addr;
1684
1685 addr = (u32)txq->tx_desc_dma;
1686 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
1687 wrl(mp, off, addr);
89df5fdc
LB		 1688
1689 txq_set_rate(txq, 1000000000, 16777216);
1690 txq_set_fixed_prio_mode(txq);
13d64285
LB		 1691 }
1692
fc32b0e2
LB		 1693 /*
1694 * Add configured unicast address to address filter table.
1695 */
1696 uc_addr_set(mp, mp->dev->dev_addr);
1da177e4 1697
d9a073ea
LB		 1698 /*
1699 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1700 * frames to RX queue #0.
1701 */
8a578111 1702 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
01999873 1703
376489a2
LB		 1704 /*
1705 * Treat BPDUs as normal multicasts, and disable partition mode.
1706 */
8a578111 1707 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
01999873 1708
8a578111
LB		 1709 /*
1710 * Enable the receive queue.
1711 */
1712 for (i = 0; i < 1; i++) {
1713 struct rx_queue *rxq = mp->rxq;
1714 int off = RXQ_CURRENT_DESC_PTR(mp->port_num);
1715 u32 addr;
1da177e4 1716
8a578111
LB		 1717 addr = (u32)rxq->rx_desc_dma;
1718 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1719 wrl(mp, off, addr);
1da177e4 1720
8a578111
LB		 1721 rxq_enable(rxq);
1722 }
1da177e4
LT		 1723}
1724
ffd86bbe 1725static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 1726{
c9df406f 1727 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 1728
fc32b0e2
LB		 1729 if (coal > 0x3fff)
1730 coal = 0x3fff;
1731
1732 wrl(mp, SDMA_CONFIG(mp->port_num),
c9df406f 1733 ((coal & 0x3fff) << 8) |
fc32b0e2 1734 (rdl(mp, SDMA_CONFIG(mp->port_num))
c9df406f 1735 & 0xffc000ff));
1da177e4
LT		 1736}
1737
ffd86bbe 1738static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 1739{
c9df406f 1740 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 1741
fc32b0e2
LB		 1742 if (coal > 0x3fff)
1743 coal = 0x3fff;
1744 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
16e03018
DF		 1745}
1746
c9df406f 1747static int mv643xx_eth_open(struct net_device *dev)
16e03018 1748{
e5371493 1749 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1750 int err;
16e03018 1751
fc32b0e2
LB		 1752 wrl(mp, INT_CAUSE(mp->port_num), 0);
1753 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
1754 rdl(mp, INT_CAUSE_EXT(mp->port_num));
c9df406f 1755
fc32b0e2
LB		 1756 err = request_irq(dev->irq, mv643xx_eth_irq,
1757 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
1758 dev->name, dev);
c9df406f 1759 if (err) {
fc32b0e2 1760 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
c9df406f 1761 return -EAGAIN;
16e03018
DF		 1762 }
1763
fc32b0e2 1764 init_mac_tables(mp);
16e03018 1765
8a578111
LB		 1766 err = rxq_init(mp);
1767 if (err)
fc32b0e2 1768 goto out;
8a578111
LB		 1769 rxq_refill(mp->rxq);
1770
13d64285
LB		 1771 err = txq_init(mp);
1772 if (err)
fc32b0e2 1773 goto out_free;
16e03018 1774
e5371493 1775#ifdef MV643XX_ETH_NAPI
c9df406f
LB		 1776 napi_enable(&mp->napi);
1777#endif
16e03018 1778
fc32b0e2 1779 port_start(mp);
16e03018 1780
ffd86bbe
LB		 1781 set_rx_coal(mp, 0);
1782 set_tx_coal(mp, 0);
16e03018 1783
fc32b0e2
LB		 1784 wrl(mp, INT_MASK_EXT(mp->port_num),
1785 INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
16e03018 1786
fc32b0e2 1787 wrl(mp, INT_MASK(mp->port_num), INT_RX | INT_EXT);
16e03018 1788
c9df406f
LB		 1789 return 0;
1790
13d64285 1791
fc32b0e2 1792out_free:
8a578111 1793 rxq_deinit(mp->rxq);
fc32b0e2 1794out:
c9df406f
LB		 1795 free_irq(dev->irq, dev);
1796
1797 return err;
16e03018
DF		 1798}
1799
e5371493 1800static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 1801{
fc32b0e2 1802 unsigned int data;
1da177e4 1803
13d64285 1804 txq_disable(mp->txq);
8a578111 1805 rxq_disable(mp->rxq);
13d64285
LB		 1806 while (!(rdl(mp, PORT_STATUS(mp->port_num)) & TX_FIFO_EMPTY))
1807 udelay(10);
1da177e4 1808
c9df406f 1809 /* Reset the Enable bit in the Configuration Register */
fc32b0e2
LB		 1810 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1811 data &= ~(SERIAL_PORT_ENABLE |
1812 DO_NOT_FORCE_LINK_FAIL |
1813 FORCE_LINK_PASS);
1814 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
1da177e4
LT		 1815}
1816
c9df406f 1817static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 1818{
e5371493 1819 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1820
fc32b0e2
LB		 1821 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1822 rdl(mp, INT_MASK(mp->port_num));
1da177e4 1823
e5371493 1824#ifdef MV643XX_ETH_NAPI
c9df406f
LB		 1825 napi_disable(&mp->napi);
1826#endif
1827 netif_carrier_off(dev);
1828 netif_stop_queue(dev);
1da177e4 1829
fc32b0e2
LB		 1830 free_irq(dev->irq, dev);
1831
cc9754b3 1832 port_reset(mp);
fc32b0e2 1833 mib_counters_update(mp);
1da177e4 1834
13d64285 1835 txq_deinit(mp->txq);
8a578111 1836 rxq_deinit(mp->rxq);
1da177e4 1837
c9df406f 1838 return 0;
1da177e4
LT		 1839}
1840
fc32b0e2 1841static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 1842{
e5371493 1843 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1844
c9df406f 1845 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
1da177e4
LT		 1846}
1847
c9df406f 1848static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 1849{
89df5fdc
LB		 1850 struct mv643xx_eth_private *mp = netdev_priv(dev);
1851
fc32b0e2 1852 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 1853 return -EINVAL;
1da177e4 1854
c9df406f 1855 dev->mtu = new_mtu;
89df5fdc
LB		 1856 tx_set_rate(mp, 1000000000, 16777216);
1857
c9df406f
LB		 1858 if (!netif_running(dev))
1859 return 0;
1da177e4 1860
c9df406f
LB		 1861 /*
1862 * Stop and then re-open the interface. This will allocate RX
1863 * skbs of the new MTU.
1864 * There is a possible danger that the open will not succeed,
fc32b0e2 1865 * due to memory being full.
c9df406f
LB		 1866 */
1867 mv643xx_eth_stop(dev);
1868 if (mv643xx_eth_open(dev)) {
fc32b0e2
LB		 1869 dev_printk(KERN_ERR, &dev->dev,
1870 "fatal error on re-opening device after "
1871 "MTU change\n");
c9df406f
LB		 1872 }
1873
1874 return 0;
1da177e4
LT		 1875}
1876
fc32b0e2 1877static void tx_timeout_task(struct work_struct *ugly)
1da177e4 1878{
fc32b0e2 1879 struct mv643xx_eth_private *mp;
1da177e4 1880
fc32b0e2
LB		 1881 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
1882 if (netif_running(mp->dev)) {
1883 netif_stop_queue(mp->dev);
c9df406f 1884
fc32b0e2
LB		 1885 port_reset(mp);
1886 port_start(mp);
c9df406f 1887
fc32b0e2
LB		 1888 __txq_maybe_wake(mp->txq);
1889 }
c9df406f
LB		 1890}
1891
c9df406f 1892static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 1893{
e5371493 1894 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1895
fc32b0e2 1896 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
d0412d96 1897
c9df406f 1898 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 1899}
1900
c9df406f 1901#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 1902static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 1903{
fc32b0e2 1904 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1905
fc32b0e2
LB		 1906 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1907 rdl(mp, INT_MASK(mp->port_num));
c9df406f 1908
fc32b0e2 1909 mv643xx_eth_irq(dev->irq, dev);
c9df406f 1910
fc32b0e2 1911 wrl(mp, INT_MASK(mp->port_num), INT_RX | INT_CAUSE_EXT);
9f8dd319 1912}
c9df406f 1913#endif
9f8dd319 1914
fc32b0e2 1915static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
9f8dd319 1916{
e5371493 1917 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f
LB		 1918 int val;
1919
fc32b0e2
LB		 1920 smi_reg_read(mp, addr, reg, &val);
1921
c9df406f 1922 return val;
9f8dd319
DF		 1923}
1924
fc32b0e2 1925static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
9f8dd319 1926{
e5371493 1927 struct mv643xx_eth_private *mp = netdev_priv(dev);
fc32b0e2 1928 smi_reg_write(mp, addr, reg, val);
c9df406f 1929}
9f8dd319 1930
9f8dd319 1931
c9df406f 1932/* platform glue ************************************************************/
e5371493
LB		 1933static void
1934mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
1935 struct mbus_dram_target_info *dram)
c9df406f 1936{
cc9754b3 1937 void __iomem *base = msp->base;
c9df406f
LB		 1938 u32 win_enable;
1939 u32 win_protect;
1940 int i;
9f8dd319 1941
c9df406f
LB		 1942 for (i = 0; i < 6; i++) {
1943 writel(0, base + WINDOW_BASE(i));
1944 writel(0, base + WINDOW_SIZE(i));
1945 if (i < 4)
1946 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 1947 }
1948
c9df406f
LB		 1949 win_enable = 0x3f;
1950 win_protect = 0;
1951
1952 for (i = 0; i < dram->num_cs; i++) {
1953 struct mbus_dram_window *cs = dram->cs + i;
1954
1955 writel((cs->base & 0xffff0000) |
1956 (cs->mbus_attr << 8) |
1957 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
1958 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
1959
1960 win_enable &= ~(1 << i);
1961 win_protect |= 3 << (2 * i);
1962 }
1963
1964 writel(win_enable, base + WINDOW_BAR_ENABLE);
1965 msp->win_protect = win_protect;
9f8dd319
DF		 1966}
1967
c9df406f 1968static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 1969{
e5371493 1970 static int mv643xx_eth_version_printed = 0;
c9df406f 1971 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 1972 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 1973 struct resource *res;
1974 int ret;
9f8dd319 1975
e5371493 1976 if (!mv643xx_eth_version_printed++)
c9df406f 1977 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
9f8dd319 1978
c9df406f
LB		 1979 ret = -EINVAL;
1980 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1981 if (res == NULL)
1982 goto out;
9f8dd319 1983
c9df406f
LB		 1984 ret = -ENOMEM;
1985 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
1986 if (msp == NULL)
1987 goto out;
1988 memset(msp, 0, sizeof(*msp));
1989
cc9754b3
LB		 1990 msp->base = ioremap(res->start, res->end - res->start + 1);
1991 if (msp->base == NULL)
c9df406f
LB		 1992 goto out_free;
1993
1994 spin_lock_init(&msp->phy_lock);
c9df406f
LB		 1995
1996 /*
1997 * (Re-)program MBUS remapping windows if we are asked to.
1998 */
1999 if (pd != NULL && pd->dram != NULL)
2000 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2001
fc32b0e2
LB		 2002 /*
2003 * Detect hardware parameters.
2004 */
2005 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2006
2007 platform_set_drvdata(pdev, msp);
2008
c9df406f
LB		 2009 return 0;
2010
2011out_free:
2012 kfree(msp);
2013out:
2014 return ret;
2015}
2016
2017static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2018{
e5371493 2019 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
c9df406f 2020
cc9754b3 2021 iounmap(msp->base);
c9df406f
LB		 2022 kfree(msp);
2023
2024 return 0;
9f8dd319
DF		 2025}
2026
c9df406f 2027static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2028 .probe = mv643xx_eth_shared_probe,
2029 .remove = mv643xx_eth_shared_remove,
c9df406f 2030 .driver = {
fc32b0e2 2031 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2032 .owner = THIS_MODULE,
2033 },
2034};
2035
e5371493 2036static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2037{
c9df406f 2038 int addr_shift = 5 * mp->port_num;
fc32b0e2 2039 u32 data;
1da177e4 2040
fc32b0e2
LB		 2041 data = rdl(mp, PHY_ADDR);
2042 data &= ~(0x1f << addr_shift);
2043 data |= (phy_addr & 0x1f) << addr_shift;
2044 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2045}
2046
e5371493 2047static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2048{
fc32b0e2
LB		 2049 unsigned int data;
2050
2051 data = rdl(mp, PHY_ADDR);
2052
2053 return (data >> (5 * mp->port_num)) & 0x1f;
2054}
2055
2056static void set_params(struct mv643xx_eth_private *mp,
2057 struct mv643xx_eth_platform_data *pd)
2058{
2059 struct net_device *dev = mp->dev;
2060
2061 if (is_valid_ether_addr(pd->mac_addr))
2062 memcpy(dev->dev_addr, pd->mac_addr, 6);
2063 else
2064 uc_addr_get(mp, dev->dev_addr);
2065
2066 if (pd->phy_addr == -1) {
2067 mp->shared_smi = NULL;
2068 mp->phy_addr = -1;
2069 } else {
2070 mp->shared_smi = mp->shared;
2071 if (pd->shared_smi != NULL)
2072 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2073
2074 if (pd->force_phy_addr || pd->phy_addr) {
2075 mp->phy_addr = pd->phy_addr & 0x3f;
2076 phy_addr_set(mp, mp->phy_addr);
2077 } else {
2078 mp->phy_addr = phy_addr_get(mp);
2079 }
2080 }
1da177e4 2081
fc32b0e2
LB		 2082 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2083 if (pd->rx_queue_size)
2084 mp->default_rx_ring_size = pd->rx_queue_size;
2085 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2086 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2087
fc32b0e2
LB		 2088 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2089 if (pd->tx_queue_size)
2090 mp->default_tx_ring_size = pd->tx_queue_size;
2091 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2092 mp->tx_desc_sram_size = pd->tx_sram_size;
1da177e4
LT		 2093}
2094
e5371493 2095static int phy_detect(struct mv643xx_eth_private *mp)
1da177e4 2096{
fc32b0e2
LB		 2097 unsigned int data;
2098 unsigned int data2;
2099
2100 smi_reg_read(mp, mp->phy_addr, 0, &data);
2101 smi_reg_write(mp, mp->phy_addr, 0, data ^ 0x1000);
1da177e4 2102
fc32b0e2
LB		 2103 smi_reg_read(mp, mp->phy_addr, 0, &data2);
2104 if (((data ^ data2) & 0x1000) == 0)
2105 return -ENODEV;
1da177e4 2106
fc32b0e2 2107 smi_reg_write(mp, mp->phy_addr, 0, data);
1da177e4 2108
c9df406f 2109 return 0;
1da177e4
LT		 2110}
2111
fc32b0e2
LB		 2112static int phy_init(struct mv643xx_eth_private *mp,
2113 struct mv643xx_eth_platform_data *pd)
c28a4f89 2114{
fc32b0e2
LB		 2115 struct ethtool_cmd cmd;
2116 int err;
c28a4f89 2117
fc32b0e2
LB		 2118 err = phy_detect(mp);
2119 if (err) {
2120 dev_printk(KERN_INFO, &mp->dev->dev,
2121 "no PHY detected at addr %d\n", mp->phy_addr);
2122 return err;
2123 }
2124 phy_reset(mp);
2125
2126 mp->mii.phy_id = mp->phy_addr;
2127 mp->mii.phy_id_mask = 0x3f;
2128 mp->mii.reg_num_mask = 0x1f;
2129 mp->mii.dev = mp->dev;
2130 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2131 mp->mii.mdio_write = mv643xx_eth_mdio_write;
c28a4f89 2132
fc32b0e2 2133 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
c9df406f 2134
fc32b0e2
LB		 2135 memset(&cmd, 0, sizeof(cmd));
2136
2137 cmd.port = PORT_MII;
2138 cmd.transceiver = XCVR_INTERNAL;
2139 cmd.phy_address = mp->phy_addr;
2140 if (pd->speed == 0) {
2141 cmd.autoneg = AUTONEG_ENABLE;
2142 cmd.speed = SPEED_100;
2143 cmd.advertising = ADVERTISED_10baseT_Half |
2144 ADVERTISED_10baseT_Full |
2145 ADVERTISED_100baseT_Half |
2146 ADVERTISED_100baseT_Full;
c9df406f 2147 if (mp->mii.supports_gmii)
fc32b0e2 2148 cmd.advertising |= ADVERTISED_1000baseT_Full;
c9df406f 2149 } else {
fc32b0e2
LB		 2150 cmd.autoneg = AUTONEG_DISABLE;
2151 cmd.speed = pd->speed;
2152 cmd.duplex = pd->duplex;
c9df406f 2153 }
fc32b0e2
LB		 2154
2155 update_pscr(mp, cmd.speed, cmd.duplex);
2156 mv643xx_eth_set_settings(mp->dev, &cmd);
2157
2158 return 0;
c28a4f89
JC		 2159}
2160
c9df406f 2161static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2162{
c9df406f 2163 struct mv643xx_eth_platform_data *pd;
e5371493 2164 struct mv643xx_eth_private *mp;
c9df406f 2165 struct net_device *dev;
c9df406f 2166 struct resource *res;
c9df406f 2167 DECLARE_MAC_BUF(mac);
fc32b0e2 2168 int err;
1da177e4 2169
c9df406f
LB		 2170 pd = pdev->dev.platform_data;
2171 if (pd == NULL) {
fc32b0e2
LB		 2172 dev_printk(KERN_ERR, &pdev->dev,
2173 "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2174 return -ENODEV;
2175 }
1da177e4 2176
c9df406f 2177 if (pd->shared == NULL) {
fc32b0e2
LB		 2178 dev_printk(KERN_ERR, &pdev->dev,
2179 "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2180 return -ENODEV;
2181 }
8f518703 2182
e5371493 2183 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
c9df406f
LB		 2184 if (!dev)
2185 return -ENOMEM;
1da177e4 2186
c9df406f 2187 mp = netdev_priv(dev);
fc32b0e2
LB		 2188 platform_set_drvdata(pdev, mp);
2189
2190 mp->shared = platform_get_drvdata(pd->shared);
2191 mp->port_num = pd->port_number;
2192
c9df406f 2193 mp->dev = dev;
e5371493
LB		 2194#ifdef MV643XX_ETH_NAPI
2195 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
c9df406f 2196#endif
1da177e4 2197
fc32b0e2
LB		 2198 set_params(mp, pd);
2199
2200 spin_lock_init(&mp->lock);
2201
2202 mib_counters_clear(mp);
2203 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2204
2205 err = phy_init(mp, pd);
2206 if (err)
2207 goto out;
2208 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2209
2210
c9df406f
LB		 2211 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2212 BUG_ON(!res);
2213 dev->irq = res->start;
1da177e4 2214
fc32b0e2 2215 dev->hard_start_xmit = mv643xx_eth_xmit;
c9df406f
LB		 2216 dev->open = mv643xx_eth_open;
2217 dev->stop = mv643xx_eth_stop;
c9df406f 2218 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
fc32b0e2
LB		 2219 dev->set_mac_address = mv643xx_eth_set_mac_address;
2220 dev->do_ioctl = mv643xx_eth_ioctl;
2221 dev->change_mtu = mv643xx_eth_change_mtu;
c9df406f 2222 dev->tx_timeout = mv643xx_eth_tx_timeout;
c9df406f 2223#ifdef CONFIG_NET_POLL_CONTROLLER
e5371493 2224 dev->poll_controller = mv643xx_eth_netpoll;
c9df406f 2225#endif
c9df406f
LB		 2226 dev->watchdog_timeo = 2 * HZ;
2227 dev->base_addr = 0;
1da177e4 2228
e5371493 2229#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
b4de9051 2230 /*
c9df406f
LB		 2231 * Zero copy can only work if we use Discovery II memory. Else, we will
2232 * have to map the buffers to ISA memory which is only 16 MB
b4de9051 2233 */
c9df406f 2234 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
c9df406f 2235#endif
1da177e4 2236
fc32b0e2 2237 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2238
c9df406f 2239 if (mp->shared->win_protect)
fc32b0e2 2240 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2241
c9df406f
LB		 2242 err = register_netdev(dev);
2243 if (err)
2244 goto out;
1da177e4 2245
fc32b0e2
LB		 2246 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2247 mp->port_num, print_mac(mac, dev->dev_addr));
1da177e4 2248
c9df406f 2249 if (dev->features & NETIF_F_SG)
fc32b0e2 2250 dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n");
1da177e4 2251
c9df406f 2252 if (dev->features & NETIF_F_IP_CSUM)
fc32b0e2 2253 dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n");
1da177e4 2254
e5371493 2255#ifdef MV643XX_ETH_NAPI
fc32b0e2 2256 dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n");
c9df406f 2257#endif
1da177e4 2258
13d64285 2259 if (mp->tx_desc_sram_size > 0)
fc32b0e2 2260 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
1da177e4 2261
c9df406f 2262 return 0;
1da177e4 2263
c9df406f
LB		 2264out:
2265 free_netdev(dev);
1da177e4 2266
c9df406f 2267 return err;
1da177e4
LT		 2268}
2269
c9df406f 2270static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2271{
fc32b0e2 2272 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2273
fc32b0e2 2274 unregister_netdev(mp->dev);
c9df406f 2275 flush_scheduled_work();
fc32b0e2 2276 free_netdev(mp->dev);
c9df406f 2277
c9df406f 2278 platform_set_drvdata(pdev, NULL);
fc32b0e2 2279
c9df406f 2280 return 0;
1da177e4
LT		 2281}
2282
c9df406f 2283static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2284{
fc32b0e2 2285 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 2286
c9df406f 2287 /* Mask all interrupts on ethernet port */
fc32b0e2
LB		 2288 wrl(mp, INT_MASK(mp->port_num), 0);
2289 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2290
fc32b0e2
LB		 2291 if (netif_running(mp->dev))
2292 port_reset(mp);
d0412d96
JC		 2293}
2294
c9df406f 2295static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 2296 .probe = mv643xx_eth_probe,
2297 .remove = mv643xx_eth_remove,
2298 .shutdown = mv643xx_eth_shutdown,
c9df406f 2299 .driver = {
fc32b0e2 2300 .name = MV643XX_ETH_NAME,
c9df406f
LB		 2301 .owner = THIS_MODULE,
2302 },
2303};
2304
e5371493 2305static int __init mv643xx_eth_init_module(void)
d0412d96 2306{
c9df406f 2307 int rc;
d0412d96 2308
c9df406f
LB		 2309 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2310 if (!rc) {
2311 rc = platform_driver_register(&mv643xx_eth_driver);
2312 if (rc)
2313 platform_driver_unregister(&mv643xx_eth_shared_driver);
2314 }
fc32b0e2 2315
c9df406f 2316 return rc;
d0412d96 2317}
fc32b0e2 2318module_init(mv643xx_eth_init_module);
d0412d96 2319
e5371493 2320static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 2321{
c9df406f
LB		 2322 platform_driver_unregister(&mv643xx_eth_driver);
2323 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 2324}
e5371493 2325module_exit(mv643xx_eth_cleanup_module);
1da177e4 2326
fc32b0e2
LB		 2327MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani "
2328 "and Dale Farnsworth");
c9df406f 2329MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 2330MODULE_LICENSE("GPL");
c9df406f 2331MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 2332MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux kernel - Deliverables
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