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mv643xx_eth: switch to netif tx queue lock, get rid of private spinlock
[deliverable/linux.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
1da177e4
LT		 41#include <linux/tcp.h>
42#include <linux/udp.h>
43#include <linux/etherdevice.h>
1da177e4
LT		 44#include <linux/delay.h>
45#include <linux/ethtool.h>
d052d1be 46#include <linux/platform_device.h>
fbd6a754
LB		 47#include <linux/module.h>
48#include <linux/kernel.h>
49#include <linux/spinlock.h>
50#include <linux/workqueue.h>
51#include <linux/mii.h>
fbd6a754 52#include <linux/mv643xx_eth.h>
1da177e4
LT		 53#include <asm/io.h>
54#include <asm/types.h>
1da177e4 55#include <asm/system.h>
fbd6a754 56
e5371493 57static char mv643xx_eth_driver_name[] = "mv643xx_eth";
c4560318 58static char mv643xx_eth_driver_version[] = "1.3";
c9df406f 59
fbd6a754 60
fbd6a754
LB		 61/*
62 * Registers shared between all ports.
63 */
3cb4667c
LB		 64#define PHY_ADDR 0x0000
65#define SMI_REG 0x0004
45c5d3bc
LB		 66#define SMI_BUSY 0x10000000
67#define SMI_READ_VALID 0x08000000
68#define SMI_OPCODE_READ 0x04000000
69#define SMI_OPCODE_WRITE 0x00000000
70#define ERR_INT_CAUSE 0x0080
71#define ERR_INT_SMI_DONE 0x00000010
72#define ERR_INT_MASK 0x0084
3cb4667c
LB		 73#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
74#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
75#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
76#define WINDOW_BAR_ENABLE 0x0290
77#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 78
79/*
80 * Per-port registers.
81 */
3cb4667c 82#define PORT_CONFIG(p) (0x0400 + ((p) << 10))
d9a073ea 83#define UNICAST_PROMISCUOUS_MODE 0x00000001
3cb4667c
LB		 84#define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
85#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
86#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
87#define SDMA_CONFIG(p) (0x041c + ((p) << 10))
88#define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
89#define PORT_STATUS(p) (0x0444 + ((p) << 10))
a2a41689 90#define TX_FIFO_EMPTY 0x00000400
ae9ae064 91#define TX_IN_PROGRESS 0x00000080
2f7eb47a
LB		 92#define PORT_SPEED_MASK 0x00000030
93#define PORT_SPEED_1000 0x00000010
94#define PORT_SPEED_100 0x00000020
95#define PORT_SPEED_10 0x00000000
96#define FLOW_CONTROL_ENABLED 0x00000008
97#define FULL_DUPLEX 0x00000004
81600eea 98#define LINK_UP 0x00000002
3cb4667c 99#define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
89df5fdc
LB		 100#define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
101#define TX_BW_RATE(p) (0x0450 + ((p) << 10))
3cb4667c 102#define TX_BW_MTU(p) (0x0458 + ((p) << 10))
89df5fdc 103#define TX_BW_BURST(p) (0x045c + ((p) << 10))
3cb4667c 104#define INT_CAUSE(p) (0x0460 + ((p) << 10))
226bb6b7 105#define INT_TX_END 0x07f80000
befefe21 106#define INT_RX 0x000003fc
073a345c 107#define INT_EXT 0x00000002
3cb4667c 108#define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
befefe21
LB		 109#define INT_EXT_LINK_PHY 0x00110000
110#define INT_EXT_TX 0x000000ff
3cb4667c
LB		 111#define INT_MASK(p) (0x0468 + ((p) << 10))
112#define INT_MASK_EXT(p) (0x046c + ((p) << 10))
113#define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
1e881592
LB		 114#define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
115#define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
116#define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
117#define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
64da80a2 118#define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
3cb4667c 119#define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
3d6b35bc
LB		 120#define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
121#define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
122#define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
123#define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
3cb4667c
LB		 124#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
125#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
126#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
127#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 128
2679a550
LB		 129
130/*
131 * SDMA configuration register.
132 */
cd4ccf76 133#define RX_BURST_SIZE_16_64BIT (4 << 1)
fbd6a754 134#define BLM_RX_NO_SWAP (1 << 4)
fbd6a754 135#define BLM_TX_NO_SWAP (1 << 5)
cd4ccf76 136#define TX_BURST_SIZE_16_64BIT (4 << 22)
fbd6a754
LB		 137
138#if defined(__BIG_ENDIAN)
139#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
cd4ccf76
LB		 140 RX_BURST_SIZE_16_64BIT | \
141 TX_BURST_SIZE_16_64BIT
fbd6a754
LB		 142#elif defined(__LITTLE_ENDIAN)
143#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
cd4ccf76 144 RX_BURST_SIZE_16_64BIT | \
fbd6a754
LB		 145 BLM_RX_NO_SWAP | \
146 BLM_TX_NO_SWAP | \
cd4ccf76 147 TX_BURST_SIZE_16_64BIT
fbd6a754
LB		 148#else
149#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
150#endif
151
2beff77b
LB		 152
153/*
154 * Port serial control register.
155 */
156#define SET_MII_SPEED_TO_100 (1 << 24)
157#define SET_GMII_SPEED_TO_1000 (1 << 23)
158#define SET_FULL_DUPLEX_MODE (1 << 21)
fbd6a754 159#define MAX_RX_PACKET_9700BYTE (5 << 17)
2beff77b
LB		 160#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
161#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
162#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
163#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
164#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
165#define FORCE_LINK_PASS (1 << 1)
166#define SERIAL_PORT_ENABLE (1 << 0)
fbd6a754 167
cc9754b3
LB		 168#define DEFAULT_RX_QUEUE_SIZE 400
169#define DEFAULT_TX_QUEUE_SIZE 800
fbd6a754 170
fbd6a754 171
7ca72a3b
LB		 172/*
173 * RX/TX descriptors.
fbd6a754
LB		 174 */
175#if defined(__BIG_ENDIAN)
cc9754b3 176struct rx_desc {
fbd6a754
LB		 177 u16 byte_cnt; /* Descriptor buffer byte count */
178 u16 buf_size; /* Buffer size */
179 u32 cmd_sts; /* Descriptor command status */
180 u32 next_desc_ptr; /* Next descriptor pointer */
181 u32 buf_ptr; /* Descriptor buffer pointer */
182};
183
cc9754b3 184struct tx_desc {
fbd6a754
LB		 185 u16 byte_cnt; /* buffer byte count */
186 u16 l4i_chk; /* CPU provided TCP checksum */
187 u32 cmd_sts; /* Command/status field */
188 u32 next_desc_ptr; /* Pointer to next descriptor */
189 u32 buf_ptr; /* pointer to buffer for this descriptor*/
190};
191#elif defined(__LITTLE_ENDIAN)
cc9754b3 192struct rx_desc {
fbd6a754
LB		 193 u32 cmd_sts; /* Descriptor command status */
194 u16 buf_size; /* Buffer size */
195 u16 byte_cnt; /* Descriptor buffer byte count */
196 u32 buf_ptr; /* Descriptor buffer pointer */
197 u32 next_desc_ptr; /* Next descriptor pointer */
198};
199
cc9754b3 200struct tx_desc {
fbd6a754
LB		 201 u32 cmd_sts; /* Command/status field */
202 u16 l4i_chk; /* CPU provided TCP checksum */
203 u16 byte_cnt; /* buffer byte count */
204 u32 buf_ptr; /* pointer to buffer for this descriptor*/
205 u32 next_desc_ptr; /* Pointer to next descriptor */
206};
207#else
208#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
209#endif
210
7ca72a3b 211/* RX & TX descriptor command */
cc9754b3 212#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 213
214/* RX & TX descriptor status */
cc9754b3 215#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 216
217/* RX descriptor status */
cc9754b3
LB		 218#define LAYER_4_CHECKSUM_OK 0x40000000
219#define RX_ENABLE_INTERRUPT 0x20000000
220#define RX_FIRST_DESC 0x08000000
221#define RX_LAST_DESC 0x04000000
7ca72a3b
LB		 222
223/* TX descriptor command */
cc9754b3
LB		 224#define TX_ENABLE_INTERRUPT 0x00800000
225#define GEN_CRC 0x00400000
226#define TX_FIRST_DESC 0x00200000
227#define TX_LAST_DESC 0x00100000
228#define ZERO_PADDING 0x00080000
229#define GEN_IP_V4_CHECKSUM 0x00040000
230#define GEN_TCP_UDP_CHECKSUM 0x00020000
231#define UDP_FRAME 0x00010000
e32b6617
LB		 232#define MAC_HDR_EXTRA_4_BYTES 0x00008000
233#define MAC_HDR_EXTRA_8_BYTES 0x00000200
7ca72a3b 234
cc9754b3 235#define TX_IHL_SHIFT 11
7ca72a3b
LB		 236
237
c9df406f 238/* global *******************************************************************/
e5371493 239struct mv643xx_eth_shared_private {
fc32b0e2
LB		 240 /*
241 * Ethernet controller base address.
242 */
cc9754b3 243 void __iomem *base;
c9df406f 244
fc0eb9f2
LB		 245 /*
246 * Points at the right SMI instance to use.
247 */
248 struct mv643xx_eth_shared_private *smi;
249
fc32b0e2
LB		 250 /*
251 * Protects access to SMI_REG, which is shared between ports.
252 */
2b3ba0e3 253 struct mutex phy_lock;
c9df406f 254
45c5d3bc
LB		 255 /*
256 * If we have access to the error interrupt pin (which is
257 * somewhat misnamed as it not only reflects internal errors
258 * but also reflects SMI completion), use that to wait for
259 * SMI access completion instead of polling the SMI busy bit.
260 */
261 int err_interrupt;
262 wait_queue_head_t smi_busy_wait;
263
fc32b0e2
LB		 264 /*
265 * Per-port MBUS window access register value.
266 */
c9df406f
LB		 267 u32 win_protect;
268
fc32b0e2
LB		 269 /*
270 * Hardware-specific parameters.
271 */
c9df406f 272 unsigned int t_clk;
773fc3ee 273 int extended_rx_coal_limit;
1e881592 274 int tx_bw_control_moved;
c9df406f
LB		 275};
276
277
278/* per-port *****************************************************************/
e5371493 279struct mib_counters {
fbd6a754
LB		 280 u64 good_octets_received;
281 u32 bad_octets_received;
282 u32 internal_mac_transmit_err;
283 u32 good_frames_received;
284 u32 bad_frames_received;
285 u32 broadcast_frames_received;
286 u32 multicast_frames_received;
287 u32 frames_64_octets;
288 u32 frames_65_to_127_octets;
289 u32 frames_128_to_255_octets;
290 u32 frames_256_to_511_octets;
291 u32 frames_512_to_1023_octets;
292 u32 frames_1024_to_max_octets;
293 u64 good_octets_sent;
294 u32 good_frames_sent;
295 u32 excessive_collision;
296 u32 multicast_frames_sent;
297 u32 broadcast_frames_sent;
298 u32 unrec_mac_control_received;
299 u32 fc_sent;
300 u32 good_fc_received;
301 u32 bad_fc_received;
302 u32 undersize_received;
303 u32 fragments_received;
304 u32 oversize_received;
305 u32 jabber_received;
306 u32 mac_receive_error;
307 u32 bad_crc_event;
308 u32 collision;
309 u32 late_collision;
310};
311
8a578111 312struct rx_queue {
64da80a2
LB		 313 int index;
314
8a578111
LB		 315 int rx_ring_size;
316
317 int rx_desc_count;
318 int rx_curr_desc;
319 int rx_used_desc;
320
321 struct rx_desc *rx_desc_area;
322 dma_addr_t rx_desc_dma;
323 int rx_desc_area_size;
324 struct sk_buff **rx_skb;
8a578111
LB		 325};
326
13d64285 327struct tx_queue {
3d6b35bc
LB		 328 int index;
329
13d64285 330 int tx_ring_size;
fbd6a754 331
13d64285
LB		 332 int tx_desc_count;
333 int tx_curr_desc;
334 int tx_used_desc;
fbd6a754 335
5daffe94 336 struct tx_desc *tx_desc_area;
fbd6a754
LB		 337 dma_addr_t tx_desc_dma;
338 int tx_desc_area_size;
339 struct sk_buff **tx_skb;
8fd89211
LB		 340
341 unsigned long tx_packets;
342 unsigned long tx_bytes;
343 unsigned long tx_dropped;
13d64285
LB		 344};
345
346struct mv643xx_eth_private {
347 struct mv643xx_eth_shared_private *shared;
fc32b0e2 348 int port_num;
13d64285 349
fc32b0e2 350 struct net_device *dev;
fbd6a754 351
fc32b0e2 352 int phy_addr;
fbd6a754 353
fc32b0e2
LB		 354 struct mib_counters mib_counters;
355 struct work_struct tx_timeout_task;
fbd6a754 356 struct mii_if_info mii;
8a578111 357
1fa38c58
LB		 358 struct napi_struct napi;
359 u8 work_link;
360 u8 work_tx;
361 u8 work_tx_end;
362 u8 work_rx;
363 u8 work_rx_refill;
364 u8 work_rx_oom;
365
8a578111
LB		 366 /*
367 * RX state.
368 */
369 int default_rx_ring_size;
370 unsigned long rx_desc_sram_addr;
371 int rx_desc_sram_size;
f7981c1c 372 int rxq_count;
2257e05c 373 struct timer_list rx_oom;
64da80a2 374 struct rx_queue rxq[8];
13d64285
LB		 375
376 /*
377 * TX state.
378 */
379 int default_tx_ring_size;
380 unsigned long tx_desc_sram_addr;
381 int tx_desc_sram_size;
f7981c1c 382 int txq_count;
3d6b35bc 383 struct tx_queue txq[8];
fbd6a754 384};
1da177e4 385
fbd6a754 386
c9df406f 387/* port register accessors **************************************************/
e5371493 388static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 389{
cc9754b3 390 return readl(mp->shared->base + offset);
c9df406f 391}
fbd6a754 392
e5371493 393static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 394{
cc9754b3 395 writel(data, mp->shared->base + offset);
c9df406f 396}
fbd6a754 397
fbd6a754 398
c9df406f 399/* rxq/txq helper functions *************************************************/
8a578111 400static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 401{
64da80a2 402 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 403}
fbd6a754 404
13d64285
LB		 405static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
406{
3d6b35bc 407 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 408}
409
8a578111 410static void rxq_enable(struct rx_queue *rxq)
c9df406f 411{
8a578111 412 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 413 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
8a578111 414}
1da177e4 415
8a578111
LB		 416static void rxq_disable(struct rx_queue *rxq)
417{
418 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 419 u8 mask = 1 << rxq->index;
1da177e4 420
8a578111
LB		 421 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
422 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
423 udelay(10);
c9df406f
LB		 424}
425
6b368f68
LB		 426static void txq_reset_hw_ptr(struct tx_queue *txq)
427{
428 struct mv643xx_eth_private *mp = txq_to_mp(txq);
429 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
430 u32 addr;
431
432 addr = (u32)txq->tx_desc_dma;
433 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
434 wrl(mp, off, addr);
435}
436
13d64285 437static void txq_enable(struct tx_queue *txq)
1da177e4 438{
13d64285 439 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 440 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
1da177e4
LT		 441}
442
13d64285 443static void txq_disable(struct tx_queue *txq)
1da177e4 444{
13d64285 445 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 446 u8 mask = 1 << txq->index;
c9df406f 447
13d64285
LB		 448 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
449 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
450 udelay(10);
451}
452
1fa38c58 453static void txq_maybe_wake(struct tx_queue *txq)
13d64285
LB		 454{
455 struct mv643xx_eth_private *mp = txq_to_mp(txq);
e5ef1de1 456 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
3d6b35bc 457
8fd89211
LB		 458 if (netif_tx_queue_stopped(nq)) {
459 __netif_tx_lock(nq, smp_processor_id());
460 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
461 netif_tx_wake_queue(nq);
462 __netif_tx_unlock(nq);
463 }
1da177e4
LT		 464}
465
c9df406f 466
1fa38c58 467/* rx napi ******************************************************************/
8a578111 468static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 469{
8a578111
LB		 470 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
471 struct net_device_stats *stats = &mp->dev->stats;
472 int rx;
1da177e4 473
8a578111 474 rx = 0;
9e1f3772 475 while (rx < budget && rxq->rx_desc_count) {
fc32b0e2 476 struct rx_desc *rx_desc;
96587661 477 unsigned int cmd_sts;
fc32b0e2 478 struct sk_buff *skb;
ff561eef 479
8a578111 480 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 481
96587661 482 cmd_sts = rx_desc->cmd_sts;
2257e05c 483 if (cmd_sts & BUFFER_OWNED_BY_DMA)
96587661 484 break;
96587661 485 rmb();
1da177e4 486
8a578111
LB		 487 skb = rxq->rx_skb[rxq->rx_curr_desc];
488 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 489
9da78745
LB		 490 rxq->rx_curr_desc++;
491 if (rxq->rx_curr_desc == rxq->rx_ring_size)
492 rxq->rx_curr_desc = 0;
ff561eef 493
3a499481 494 dma_unmap_single(NULL, rx_desc->buf_ptr,
abe78717 495 rx_desc->buf_size, DMA_FROM_DEVICE);
8a578111
LB		 496 rxq->rx_desc_count--;
497 rx++;
b1dd9ca1 498
1fa38c58
LB		 499 mp->work_rx_refill |= 1 << rxq->index;
500
468d09f8
DF		 501 /*
502 * Update statistics.
fc32b0e2
LB		 503 *
504 * Note that the descriptor byte count includes 2 dummy
505 * bytes automatically inserted by the hardware at the
506 * start of the packet (which we don't count), and a 4
507 * byte CRC at the end of the packet (which we do count).
468d09f8 508 */
1da177e4 509 stats->rx_packets++;
fc32b0e2 510 stats->rx_bytes += rx_desc->byte_cnt - 2;
96587661 511
1da177e4 512 /*
fc32b0e2
LB		 513 * In case we received a packet without first / last bits
514 * on, or the error summary bit is set, the packet needs
515 * to be dropped.
1da177e4 516 */
96587661 517 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 518 (RX_FIRST_DESC | RX_LAST_DESC))
96587661 519 || (cmd_sts & ERROR_SUMMARY)) {
1da177e4 520 stats->rx_dropped++;
fc32b0e2 521
96587661 522 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 523 (RX_FIRST_DESC | RX_LAST_DESC)) {
1da177e4 524 if (net_ratelimit())
fc32b0e2
LB		 525 dev_printk(KERN_ERR, &mp->dev->dev,
526 "received packet spanning "
527 "multiple descriptors\n");
1da177e4 528 }
fc32b0e2 529
96587661 530 if (cmd_sts & ERROR_SUMMARY)
1da177e4
LT		 531 stats->rx_errors++;
532
78fff83b 533 dev_kfree_skb(skb);
1da177e4
LT		 534 } else {
535 /*
536 * The -4 is for the CRC in the trailer of the
537 * received packet
538 */
fc32b0e2 539 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
1da177e4 540
96587661 541 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
1da177e4
LT		 542 skb->ip_summed = CHECKSUM_UNNECESSARY;
543 skb->csum = htons(
96587661 544 (cmd_sts & 0x0007fff8) >> 3);
1da177e4 545 }
8a578111 546 skb->protocol = eth_type_trans(skb, mp->dev);
1da177e4 547 netif_receive_skb(skb);
1da177e4 548 }
fc32b0e2 549
8a578111 550 mp->dev->last_rx = jiffies;
1da177e4 551 }
fc32b0e2 552
1fa38c58
LB		 553 if (rx < budget)
554 mp->work_rx &= ~(1 << rxq->index);
555
8a578111 556 return rx;
1da177e4
LT		 557}
558
1fa38c58 559static int rxq_refill(struct rx_queue *rxq, int budget)
d0412d96 560{
1fa38c58
LB		 561 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
562 int skb_size;
563 int refilled;
8a578111 564
1fa38c58
LB		 565 /*
566 * Reserve 2+14 bytes for an ethernet header (the hardware
567 * automatically prepends 2 bytes of dummy data to each
568 * received packet), 16 bytes for up to four VLAN tags, and
569 * 4 bytes for the trailing FCS -- 36 bytes total.
570 */
571 skb_size = rxq_to_mp(rxq)->dev->mtu + 36;
d0412d96 572
1fa38c58
LB		 573 /*
574 * Make sure that the skb size is a multiple of 8 bytes, as
575 * the lower three bits of the receive descriptor's buffer
576 * size field are ignored by the hardware.
577 */
578 skb_size = (skb_size + 7) & ~7;
4dfc1c87 579
1fa38c58
LB		 580 refilled = 0;
581 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
582 struct sk_buff *skb;
583 int unaligned;
584 int rx;
d0412d96 585
1fa38c58
LB		 586 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
587 if (skb == NULL) {
588 mp->work_rx_oom |= 1 << rxq->index;
589 goto oom;
590 }
d0412d96 591
1fa38c58
LB		 592 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
593 if (unaligned)
594 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
2257e05c 595
1fa38c58
LB		 596 refilled++;
597 rxq->rx_desc_count++;
c9df406f 598
1fa38c58
LB		 599 rx = rxq->rx_used_desc++;
600 if (rxq->rx_used_desc == rxq->rx_ring_size)
601 rxq->rx_used_desc = 0;
2257e05c 602
1fa38c58
LB		 603 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
604 skb_size, DMA_FROM_DEVICE);
605 rxq->rx_desc_area[rx].buf_size = skb_size;
606 rxq->rx_skb[rx] = skb;
607 wmb();
608 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
609 RX_ENABLE_INTERRUPT;
610 wmb();
2257e05c 611
1fa38c58
LB		 612 /*
613 * The hardware automatically prepends 2 bytes of
614 * dummy data to each received packet, so that the
615 * IP header ends up 16-byte aligned.
616 */
617 skb_reserve(skb, 2);
618 }
619
620 if (refilled < budget)
621 mp->work_rx_refill &= ~(1 << rxq->index);
622
623oom:
624 return refilled;
d0412d96
JC		 625}
626
c9df406f
LB		 627
628/* tx ***********************************************************************/
c9df406f 629static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 630{
13d64285 631 int frag;
1da177e4 632
c9df406f 633 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
13d64285
LB		 634 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
635 if (fragp->size <= 8 && fragp->page_offset & 7)
c9df406f 636 return 1;
1da177e4 637 }
13d64285 638
c9df406f
LB		 639 return 0;
640}
7303fde8 641
13d64285 642static int txq_alloc_desc_index(struct tx_queue *txq)
c9df406f
LB		 643{
644 int tx_desc_curr;
d0412d96 645
13d64285 646 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
1da177e4 647
9da78745
LB		 648 tx_desc_curr = txq->tx_curr_desc++;
649 if (txq->tx_curr_desc == txq->tx_ring_size)
650 txq->tx_curr_desc = 0;
e4d00fa9 651
13d64285 652 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
468d09f8 653
c9df406f
LB		 654 return tx_desc_curr;
655}
468d09f8 656
13d64285 657static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 658{
13d64285 659 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 660 int frag;
1da177e4 661
13d64285
LB		 662 for (frag = 0; frag < nr_frags; frag++) {
663 skb_frag_t *this_frag;
664 int tx_index;
665 struct tx_desc *desc;
666
667 this_frag = &skb_shinfo(skb)->frags[frag];
668 tx_index = txq_alloc_desc_index(txq);
669 desc = &txq->tx_desc_area[tx_index];
670
671 /*
672 * The last fragment will generate an interrupt
673 * which will free the skb on TX completion.
674 */
675 if (frag == nr_frags - 1) {
676 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
677 ZERO_PADDING | TX_LAST_DESC |
678 TX_ENABLE_INTERRUPT;
679 txq->tx_skb[tx_index] = skb;
680 } else {
681 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
682 txq->tx_skb[tx_index] = NULL;
683 }
684
c9df406f
LB		 685 desc->l4i_chk = 0;
686 desc->byte_cnt = this_frag->size;
687 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
688 this_frag->page_offset,
689 this_frag->size,
690 DMA_TO_DEVICE);
691 }
1da177e4
LT		 692}
693
c9df406f
LB		 694static inline __be16 sum16_as_be(__sum16 sum)
695{
696 return (__force __be16)sum;
697}
1da177e4 698
13d64285 699static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 700{
8fa89bf5 701 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 702 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 703 int tx_index;
cc9754b3 704 struct tx_desc *desc;
c9df406f
LB		 705 u32 cmd_sts;
706 int length;
1da177e4 707
cc9754b3 708 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
1da177e4 709
13d64285
LB		 710 tx_index = txq_alloc_desc_index(txq);
711 desc = &txq->tx_desc_area[tx_index];
c9df406f
LB		 712
713 if (nr_frags) {
13d64285 714 txq_submit_frag_skb(txq, skb);
c9df406f
LB		 715
716 length = skb_headlen(skb);
13d64285 717 txq->tx_skb[tx_index] = NULL;
c9df406f 718 } else {
cc9754b3 719 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
c9df406f 720 length = skb->len;
13d64285 721 txq->tx_skb[tx_index] = skb;
c9df406f
LB		 722 }
723
724 desc->byte_cnt = length;
725 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
726
727 if (skb->ip_summed == CHECKSUM_PARTIAL) {
e32b6617
LB		 728 int mac_hdr_len;
729
730 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
731 skb->protocol != htons(ETH_P_8021Q));
c9df406f 732
cc9754b3
LB		 733 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
734 GEN_IP_V4_CHECKSUM |
735 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
c9df406f 736
e32b6617
LB		 737 mac_hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
738 switch (mac_hdr_len - ETH_HLEN) {
739 case 0:
740 break;
741 case 4:
742 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
743 break;
744 case 8:
745 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
746 break;
747 case 12:
748 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
749 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
750 break;
751 default:
752 if (net_ratelimit())
753 dev_printk(KERN_ERR, &txq_to_mp(txq)->dev->dev,
754 "mac header length is %d?!\n", mac_hdr_len);
755 break;
756 }
757
c9df406f
LB		 758 switch (ip_hdr(skb)->protocol) {
759 case IPPROTO_UDP:
cc9754b3 760 cmd_sts |= UDP_FRAME;
c9df406f
LB		 761 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
762 break;
763 case IPPROTO_TCP:
764 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
765 break;
766 default:
767 BUG();
768 }
769 } else {
770 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 771 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 772 desc->l4i_chk = 0;
773 }
774
775 /* ensure all other descriptors are written before first cmd_sts */
776 wmb();
777 desc->cmd_sts = cmd_sts;
778
1fa38c58
LB		 779 /* clear TX_END status */
780 mp->work_tx_end &= ~(1 << txq->index);
8fa89bf5 781
c9df406f
LB		 782 /* ensure all descriptors are written before poking hardware */
783 wmb();
13d64285 784 txq_enable(txq);
c9df406f 785
13d64285 786 txq->tx_desc_count += nr_frags + 1;
1da177e4 787}
1da177e4 788
fc32b0e2 789static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 790{
e5371493 791 struct mv643xx_eth_private *mp = netdev_priv(dev);
e5ef1de1 792 int queue;
13d64285 793 struct tx_queue *txq;
e5ef1de1 794 struct netdev_queue *nq;
e5ef1de1 795 int entries_left;
afdb57a2 796
8fd89211
LB		 797 queue = skb_get_queue_mapping(skb);
798 txq = mp->txq + queue;
799 nq = netdev_get_tx_queue(dev, queue);
800
c9df406f 801 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
8fd89211 802 txq->tx_dropped++;
fc32b0e2
LB		 803 dev_printk(KERN_DEBUG, &dev->dev,
804 "failed to linearize skb with tiny "
805 "unaligned fragment\n");
c9df406f
LB		 806 return NETDEV_TX_BUSY;
807 }
808
17cd0a59 809 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
e5ef1de1
LB		 810 if (net_ratelimit())
811 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
3d6b35bc
LB		 812 kfree_skb(skb);
813 return NETDEV_TX_OK;
c9df406f
LB		 814 }
815
13d64285 816 txq_submit_skb(txq, skb);
8fd89211
LB		 817 txq->tx_bytes += skb->len;
818 txq->tx_packets++;
c9df406f
LB		 819 dev->trans_start = jiffies;
820
e5ef1de1
LB		 821 entries_left = txq->tx_ring_size - txq->tx_desc_count;
822 if (entries_left < MAX_SKB_FRAGS + 1)
823 netif_tx_stop_queue(nq);
c9df406f 824
c9df406f 825 return NETDEV_TX_OK;
1da177e4
LT		 826}
827
c9df406f 828
1fa38c58
LB		 829/* tx napi ******************************************************************/
830static void txq_kick(struct tx_queue *txq)
831{
832 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 833 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 834 u32 hw_desc_ptr;
835 u32 expected_ptr;
836
8fd89211 837 __netif_tx_lock(nq, smp_processor_id());
1fa38c58
LB		 838
839 if (rdl(mp, TXQ_COMMAND(mp->port_num)) & (1 << txq->index))
840 goto out;
841
842 hw_desc_ptr = rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index));
843 expected_ptr = (u32)txq->tx_desc_dma +
844 txq->tx_curr_desc * sizeof(struct tx_desc);
845
846 if (hw_desc_ptr != expected_ptr)
847 txq_enable(txq);
848
849out:
8fd89211 850 __netif_tx_unlock(nq);
1fa38c58
LB		 851
852 mp->work_tx_end &= ~(1 << txq->index);
853}
854
855static int txq_reclaim(struct tx_queue *txq, int budget, int force)
856{
857 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 858 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 859 int reclaimed;
860
8fd89211 861 __netif_tx_lock(nq, smp_processor_id());
1fa38c58
LB		 862
863 reclaimed = 0;
864 while (reclaimed < budget && txq->tx_desc_count > 0) {
865 int tx_index;
866 struct tx_desc *desc;
867 u32 cmd_sts;
868 struct sk_buff *skb;
869 dma_addr_t addr;
870 int count;
871
872 tx_index = txq->tx_used_desc;
873 desc = &txq->tx_desc_area[tx_index];
874 cmd_sts = desc->cmd_sts;
875
876 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
877 if (!force)
878 break;
879 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
880 }
881
882 txq->tx_used_desc = tx_index + 1;
883 if (txq->tx_used_desc == txq->tx_ring_size)
884 txq->tx_used_desc = 0;
885
886 reclaimed++;
887 txq->tx_desc_count--;
888
889 addr = desc->buf_ptr;
890 count = desc->byte_cnt;
891 skb = txq->tx_skb[tx_index];
892 txq->tx_skb[tx_index] = NULL;
893
894 if (cmd_sts & ERROR_SUMMARY) {
895 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
896 mp->dev->stats.tx_errors++;
897 }
898
899 /*
8fd89211 900 * Drop tx queue lock while we free the skb.
1fa38c58 901 */
8fd89211 902 __netif_tx_unlock(nq);
1fa38c58
LB		 903
904 if (cmd_sts & TX_FIRST_DESC)
905 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
906 else
907 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
908
909 if (skb)
910 dev_kfree_skb(skb);
911
8fd89211 912 __netif_tx_lock(nq, smp_processor_id());
1fa38c58
LB		 913 }
914
8fd89211
LB		 915 __netif_tx_unlock(nq);
916
1fa38c58
LB		 917 if (reclaimed < budget)
918 mp->work_tx &= ~(1 << txq->index);
919
1fa38c58
LB		 920 return reclaimed;
921}
922
923
89df5fdc
LB		 924/* tx rate control **********************************************************/
925/*
926 * Set total maximum TX rate (shared by all TX queues for this port)
927 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
928 */
929static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
930{
931 int token_rate;
932 int mtu;
933 int bucket_size;
934
935 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
936 if (token_rate > 1023)
937 token_rate = 1023;
938
939 mtu = (mp->dev->mtu + 255) >> 8;
940 if (mtu > 63)
941 mtu = 63;
942
943 bucket_size = (burst + 255) >> 8;
944 if (bucket_size > 65535)
945 bucket_size = 65535;
946
1e881592
LB		 947 if (mp->shared->tx_bw_control_moved) {
948 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
949 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
950 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
951 } else {
952 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
953 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
954 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
955 }
89df5fdc
LB		 956}
957
958static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
959{
960 struct mv643xx_eth_private *mp = txq_to_mp(txq);
961 int token_rate;
962 int bucket_size;
963
964 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
965 if (token_rate > 1023)
966 token_rate = 1023;
967
968 bucket_size = (burst + 255) >> 8;
969 if (bucket_size > 65535)
970 bucket_size = 65535;
971
3d6b35bc
LB		 972 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
973 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
89df5fdc
LB		 974 (bucket_size << 10) | token_rate);
975}
976
977static void txq_set_fixed_prio_mode(struct tx_queue *txq)
978{
979 struct mv643xx_eth_private *mp = txq_to_mp(txq);
980 int off;
981 u32 val;
982
983 /*
984 * Turn on fixed priority mode.
985 */
1e881592
LB		 986 if (mp->shared->tx_bw_control_moved)
987 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
988 else
989 off = TXQ_FIX_PRIO_CONF(mp->port_num);
89df5fdc
LB		 990
991 val = rdl(mp, off);
3d6b35bc 992 val |= 1 << txq->index;
89df5fdc
LB		 993 wrl(mp, off, val);
994}
995
996static void txq_set_wrr(struct tx_queue *txq, int weight)
997{
998 struct mv643xx_eth_private *mp = txq_to_mp(txq);
999 int off;
1000 u32 val;
1001
1002 /*
1003 * Turn off fixed priority mode.
1004 */
1e881592
LB		 1005 if (mp->shared->tx_bw_control_moved)
1006 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
1007 else
1008 off = TXQ_FIX_PRIO_CONF(mp->port_num);
89df5fdc
LB		 1009
1010 val = rdl(mp, off);
3d6b35bc 1011 val &= ~(1 << txq->index);
89df5fdc
LB		 1012 wrl(mp, off, val);
1013
1014 /*
1015 * Configure WRR weight for this queue.
1016 */
3d6b35bc 1017 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
89df5fdc
LB		 1018
1019 val = rdl(mp, off);
1020 val = (val & ~0xff) | (weight & 0xff);
1021 wrl(mp, off, val);
1022}
1023
1024
c9df406f 1025/* mii management interface *************************************************/
45c5d3bc
LB		 1026static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1027{
1028 struct mv643xx_eth_shared_private *msp = dev_id;
1029
1030 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1031 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1032 wake_up(&msp->smi_busy_wait);
1033 return IRQ_HANDLED;
1034 }
1035
1036 return IRQ_NONE;
1037}
c9df406f 1038
45c5d3bc 1039static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1da177e4 1040{
45c5d3bc
LB		 1041 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1042}
1da177e4 1043
45c5d3bc
LB		 1044static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1045{
1046 if (msp->err_interrupt == NO_IRQ) {
1047 int i;
c9df406f 1048
45c5d3bc
LB		 1049 for (i = 0; !smi_is_done(msp); i++) {
1050 if (i == 10)
1051 return -ETIMEDOUT;
1052 msleep(10);
c9df406f 1053 }
45c5d3bc
LB		 1054
1055 return 0;
1056 }
1057
1058 if (!wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1059 msecs_to_jiffies(100)))
1060 return -ETIMEDOUT;
1061
1062 return 0;
1063}
1064
1065static int smi_reg_read(struct mv643xx_eth_private *mp,
1066 unsigned int addr, unsigned int reg)
1067{
fc0eb9f2 1068 struct mv643xx_eth_shared_private *msp = mp->shared->smi;
45c5d3bc
LB		 1069 void __iomem *smi_reg = msp->base + SMI_REG;
1070 int ret;
1071
1072 mutex_lock(&msp->phy_lock);
1073
1074 if (smi_wait_ready(msp)) {
1075 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1076 ret = -ETIMEDOUT;
1077 goto out;
1da177e4
LT		 1078 }
1079
fc32b0e2 1080 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 1081
45c5d3bc
LB		 1082 if (smi_wait_ready(msp)) {
1083 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1084 ret = -ETIMEDOUT;
1085 goto out;
1086 }
1087
1088 ret = readl(smi_reg);
1089 if (!(ret & SMI_READ_VALID)) {
1090 printk("%s: SMI bus read not valid\n", mp->dev->name);
1091 ret = -ENODEV;
1092 goto out;
c9df406f
LB		 1093 }
1094
45c5d3bc
LB		 1095 ret &= 0xffff;
1096
c9df406f 1097out:
45c5d3bc
LB		 1098 mutex_unlock(&msp->phy_lock);
1099
1100 return ret;
1da177e4
LT		 1101}
1102
45c5d3bc
LB		 1103static int smi_reg_write(struct mv643xx_eth_private *mp, unsigned int addr,
1104 unsigned int reg, unsigned int value)
1da177e4 1105{
fc0eb9f2 1106 struct mv643xx_eth_shared_private *msp = mp->shared->smi;
45c5d3bc 1107 void __iomem *smi_reg = msp->base + SMI_REG;
1da177e4 1108
45c5d3bc 1109 mutex_lock(&msp->phy_lock);
c9df406f 1110
45c5d3bc
LB		 1111 if (smi_wait_ready(msp)) {
1112 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1113 mutex_unlock(&msp->phy_lock);
1114 return -ETIMEDOUT;
1da177e4
LT		 1115 }
1116
fc32b0e2
LB		 1117 writel(SMI_OPCODE_WRITE | (reg << 21) |
1118 (addr << 16) | (value & 0xffff), smi_reg);
45c5d3bc
LB		 1119
1120 mutex_unlock(&msp->phy_lock);
1121
1122 return 0;
c9df406f 1123}
1da177e4 1124
c9df406f 1125
8fd89211
LB		 1126/* statistics ***************************************************************/
1127static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1128{
1129 struct mv643xx_eth_private *mp = netdev_priv(dev);
1130 struct net_device_stats *stats = &dev->stats;
1131 unsigned long tx_packets = 0;
1132 unsigned long tx_bytes = 0;
1133 unsigned long tx_dropped = 0;
1134 int i;
1135
1136 for (i = 0; i < mp->txq_count; i++) {
1137 struct tx_queue *txq = mp->txq + i;
1138
1139 tx_packets += txq->tx_packets;
1140 tx_bytes += txq->tx_bytes;
1141 tx_dropped += txq->tx_dropped;
1142 }
1143
1144 stats->tx_packets = tx_packets;
1145 stats->tx_bytes = tx_bytes;
1146 stats->tx_dropped = tx_dropped;
1147
1148 return stats;
1149}
1150
fc32b0e2 1151static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 1152{
fc32b0e2 1153 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 1154}
1155
fc32b0e2 1156static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 1157{
fc32b0e2
LB		 1158 int i;
1159
1160 for (i = 0; i < 0x80; i += 4)
1161 mib_read(mp, i);
c9df406f 1162}
d0412d96 1163
fc32b0e2 1164static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 1165{
e5371493 1166 struct mib_counters *p = &mp->mib_counters;
4b8e3655 1167
fc32b0e2
LB		 1168 p->good_octets_received += mib_read(mp, 0x00);
1169 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1170 p->bad_octets_received += mib_read(mp, 0x08);
1171 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1172 p->good_frames_received += mib_read(mp, 0x10);
1173 p->bad_frames_received += mib_read(mp, 0x14);
1174 p->broadcast_frames_received += mib_read(mp, 0x18);
1175 p->multicast_frames_received += mib_read(mp, 0x1c);
1176 p->frames_64_octets += mib_read(mp, 0x20);
1177 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1178 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1179 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1180 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1181 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1182 p->good_octets_sent += mib_read(mp, 0x38);
1183 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1184 p->good_frames_sent += mib_read(mp, 0x40);
1185 p->excessive_collision += mib_read(mp, 0x44);
1186 p->multicast_frames_sent += mib_read(mp, 0x48);
1187 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1188 p->unrec_mac_control_received += mib_read(mp, 0x50);
1189 p->fc_sent += mib_read(mp, 0x54);
1190 p->good_fc_received += mib_read(mp, 0x58);
1191 p->bad_fc_received += mib_read(mp, 0x5c);
1192 p->undersize_received += mib_read(mp, 0x60);
1193 p->fragments_received += mib_read(mp, 0x64);
1194 p->oversize_received += mib_read(mp, 0x68);
1195 p->jabber_received += mib_read(mp, 0x6c);
1196 p->mac_receive_error += mib_read(mp, 0x70);
1197 p->bad_crc_event += mib_read(mp, 0x74);
1198 p->collision += mib_read(mp, 0x78);
1199 p->late_collision += mib_read(mp, 0x7c);
d0412d96
JC		 1200}
1201
c9df406f
LB		 1202
1203/* ethtool ******************************************************************/
e5371493 1204struct mv643xx_eth_stats {
c9df406f
LB		 1205 char stat_string[ETH_GSTRING_LEN];
1206 int sizeof_stat;
16820054
LB		 1207 int netdev_off;
1208 int mp_off;
c9df406f
LB		 1209};
1210
16820054
LB		 1211#define SSTAT(m) \
1212 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1213 offsetof(struct net_device, stats.m), -1 }
1214
1215#define MIBSTAT(m) \
1216 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1217 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1218
1219static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1220 SSTAT(rx_packets),
1221 SSTAT(tx_packets),
1222 SSTAT(rx_bytes),
1223 SSTAT(tx_bytes),
1224 SSTAT(rx_errors),
1225 SSTAT(tx_errors),
1226 SSTAT(rx_dropped),
1227 SSTAT(tx_dropped),
1228 MIBSTAT(good_octets_received),
1229 MIBSTAT(bad_octets_received),
1230 MIBSTAT(internal_mac_transmit_err),
1231 MIBSTAT(good_frames_received),
1232 MIBSTAT(bad_frames_received),
1233 MIBSTAT(broadcast_frames_received),
1234 MIBSTAT(multicast_frames_received),
1235 MIBSTAT(frames_64_octets),
1236 MIBSTAT(frames_65_to_127_octets),
1237 MIBSTAT(frames_128_to_255_octets),
1238 MIBSTAT(frames_256_to_511_octets),
1239 MIBSTAT(frames_512_to_1023_octets),
1240 MIBSTAT(frames_1024_to_max_octets),
1241 MIBSTAT(good_octets_sent),
1242 MIBSTAT(good_frames_sent),
1243 MIBSTAT(excessive_collision),
1244 MIBSTAT(multicast_frames_sent),
1245 MIBSTAT(broadcast_frames_sent),
1246 MIBSTAT(unrec_mac_control_received),
1247 MIBSTAT(fc_sent),
1248 MIBSTAT(good_fc_received),
1249 MIBSTAT(bad_fc_received),
1250 MIBSTAT(undersize_received),
1251 MIBSTAT(fragments_received),
1252 MIBSTAT(oversize_received),
1253 MIBSTAT(jabber_received),
1254 MIBSTAT(mac_receive_error),
1255 MIBSTAT(bad_crc_event),
1256 MIBSTAT(collision),
1257 MIBSTAT(late_collision),
c9df406f
LB		 1258};
1259
e5371493 1260static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
d0412d96 1261{
e5371493 1262 struct mv643xx_eth_private *mp = netdev_priv(dev);
d0412d96
JC		 1263 int err;
1264
d0412d96 1265 err = mii_ethtool_gset(&mp->mii, cmd);
d0412d96 1266
fc32b0e2
LB		 1267 /*
1268 * The MAC does not support 1000baseT_Half.
1269 */
d0412d96
JC		 1270 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1271 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1272
1273 return err;
1274}
1275
bedfe324
LB		 1276static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1277{
81600eea
LB		 1278 struct mv643xx_eth_private *mp = netdev_priv(dev);
1279 u32 port_status;
1280
1281 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1282
bedfe324
LB		 1283 cmd->supported = SUPPORTED_MII;
1284 cmd->advertising = ADVERTISED_MII;
81600eea
LB		 1285 switch (port_status & PORT_SPEED_MASK) {
1286 case PORT_SPEED_10:
1287 cmd->speed = SPEED_10;
1288 break;
1289 case PORT_SPEED_100:
1290 cmd->speed = SPEED_100;
1291 break;
1292 case PORT_SPEED_1000:
1293 cmd->speed = SPEED_1000;
1294 break;
1295 default:
1296 cmd->speed = -1;
1297 break;
1298 }
1299 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
bedfe324
LB		 1300 cmd->port = PORT_MII;
1301 cmd->phy_address = 0;
1302 cmd->transceiver = XCVR_INTERNAL;
1303 cmd->autoneg = AUTONEG_DISABLE;
1304 cmd->maxtxpkt = 1;
1305 cmd->maxrxpkt = 1;
1306
1307 return 0;
1308}
1309
e5371493 1310static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1311{
e5371493 1312 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6 1313
fc32b0e2
LB		 1314 /*
1315 * The MAC does not support 1000baseT_Half.
1316 */
1317 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1318
2b3ba0e3 1319 return mii_ethtool_sset(&mp->mii, cmd);
c9df406f 1320}
1da177e4 1321
bedfe324
LB		 1322static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1323{
1324 return -EINVAL;
1325}
1326
fc32b0e2
LB		 1327static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1328 struct ethtool_drvinfo *drvinfo)
c9df406f 1329{
e5371493
LB		 1330 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1331 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 1332 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 1333 strncpy(drvinfo->bus_info, "platform", 32);
16820054 1334 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1335}
1da177e4 1336
fc32b0e2 1337static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1338{
e5371493 1339 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1340
c9df406f
LB		 1341 return mii_nway_restart(&mp->mii);
1342}
1da177e4 1343
bedfe324
LB		 1344static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1345{
1346 return -EINVAL;
1347}
1348
c9df406f
LB		 1349static u32 mv643xx_eth_get_link(struct net_device *dev)
1350{
e5371493 1351 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1352
c9df406f
LB		 1353 return mii_link_ok(&mp->mii);
1354}
1da177e4 1355
bedfe324
LB		 1356static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1357{
1358 return 1;
1359}
1360
fc32b0e2
LB		 1361static void mv643xx_eth_get_strings(struct net_device *dev,
1362 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1363{
1364 int i;
1da177e4 1365
fc32b0e2
LB		 1366 if (stringset == ETH_SS_STATS) {
1367 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1368 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1369 mv643xx_eth_stats[i].stat_string,
e5371493 1370 ETH_GSTRING_LEN);
c9df406f 1371 }
c9df406f
LB		 1372 }
1373}
1da177e4 1374
fc32b0e2
LB		 1375static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1376 struct ethtool_stats *stats,
1377 uint64_t *data)
c9df406f 1378{
b9873841 1379 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1380 int i;
1da177e4 1381
8fd89211 1382 mv643xx_eth_get_stats(dev);
fc32b0e2 1383 mib_counters_update(mp);
1da177e4 1384
16820054
LB		 1385 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1386 const struct mv643xx_eth_stats *stat;
1387 void *p;
1388
1389 stat = mv643xx_eth_stats + i;
1390
1391 if (stat->netdev_off >= 0)
1392 p = ((void *)mp->dev) + stat->netdev_off;
1393 else
1394 p = ((void *)mp) + stat->mp_off;
1395
1396 data[i] = (stat->sizeof_stat == 8) ?
1397 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1398 }
c9df406f 1399}
1da177e4 1400
fc32b0e2 1401static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1402{
fc32b0e2 1403 if (sset == ETH_SS_STATS)
16820054 1404 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1405
1406 return -EOPNOTSUPP;
c9df406f 1407}
1da177e4 1408
e5371493 1409static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1410 .get_settings = mv643xx_eth_get_settings,
1411 .set_settings = mv643xx_eth_set_settings,
1412 .get_drvinfo = mv643xx_eth_get_drvinfo,
1413 .nway_reset = mv643xx_eth_nway_reset,
1414 .get_link = mv643xx_eth_get_link,
c9df406f 1415 .set_sg = ethtool_op_set_sg,
fc32b0e2
LB		 1416 .get_strings = mv643xx_eth_get_strings,
1417 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
e5371493 1418 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1419};
1da177e4 1420
bedfe324
LB		 1421static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1422 .get_settings = mv643xx_eth_get_settings_phyless,
1423 .set_settings = mv643xx_eth_set_settings_phyless,
1424 .get_drvinfo = mv643xx_eth_get_drvinfo,
1425 .nway_reset = mv643xx_eth_nway_reset_phyless,
1426 .get_link = mv643xx_eth_get_link_phyless,
1427 .set_sg = ethtool_op_set_sg,
1428 .get_strings = mv643xx_eth_get_strings,
1429 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1430 .get_sset_count = mv643xx_eth_get_sset_count,
1431};
1432
bea3348e 1433
c9df406f 1434/* address handling *********************************************************/
5daffe94 1435static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1436{
c9df406f
LB		 1437 unsigned int mac_h;
1438 unsigned int mac_l;
1da177e4 1439
fc32b0e2
LB		 1440 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1441 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1da177e4 1442
5daffe94
LB		 1443 addr[0] = (mac_h >> 24) & 0xff;
1444 addr[1] = (mac_h >> 16) & 0xff;
1445 addr[2] = (mac_h >> 8) & 0xff;
1446 addr[3] = mac_h & 0xff;
1447 addr[4] = (mac_l >> 8) & 0xff;
1448 addr[5] = mac_l & 0xff;
c9df406f 1449}
1da177e4 1450
e5371493 1451static void init_mac_tables(struct mv643xx_eth_private *mp)
c9df406f 1452{
fc32b0e2 1453 int i;
1da177e4 1454
fc32b0e2
LB		 1455 for (i = 0; i < 0x100; i += 4) {
1456 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1457 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
c9df406f 1458 }
fc32b0e2
LB		 1459
1460 for (i = 0; i < 0x10; i += 4)
1461 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
c9df406f 1462}
d0412d96 1463
e5371493 1464static void set_filter_table_entry(struct mv643xx_eth_private *mp,
fc32b0e2 1465 int table, unsigned char entry)
c9df406f
LB		 1466{
1467 unsigned int table_reg;
ab4384a6 1468
c9df406f 1469 /* Set "accepts frame bit" at specified table entry */
fc32b0e2
LB		 1470 table_reg = rdl(mp, table + (entry & 0xfc));
1471 table_reg |= 0x01 << (8 * (entry & 3));
1472 wrl(mp, table + (entry & 0xfc), table_reg);
1da177e4
LT		 1473}
1474
5daffe94 1475static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1da177e4 1476{
c9df406f
LB		 1477 unsigned int mac_h;
1478 unsigned int mac_l;
1479 int table;
1da177e4 1480
fc32b0e2
LB		 1481 mac_l = (addr[4] << 8) | addr[5];
1482 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
ff561eef 1483
fc32b0e2
LB		 1484 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1485 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1da177e4 1486
fc32b0e2 1487 table = UNICAST_TABLE(mp->port_num);
5daffe94 1488 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1da177e4
LT		 1489}
1490
fc32b0e2 1491static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1da177e4 1492{
e5371493 1493 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1494
fc32b0e2
LB		 1495 /* +2 is for the offset of the HW addr type */
1496 memcpy(dev->dev_addr, addr + 2, 6);
1497
cc9754b3
LB		 1498 init_mac_tables(mp);
1499 uc_addr_set(mp, dev->dev_addr);
1da177e4
LT		 1500
1501 return 0;
1502}
1503
69876569
LB		 1504static int addr_crc(unsigned char *addr)
1505{
1506 int crc = 0;
1507 int i;
1508
1509 for (i = 0; i < 6; i++) {
1510 int j;
1511
1512 crc = (crc ^ addr[i]) << 8;
1513 for (j = 7; j >= 0; j--) {
1514 if (crc & (0x100 << j))
1515 crc ^= 0x107 << j;
1516 }
1517 }
1518
1519 return crc;
1520}
1521
fc32b0e2 1522static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1da177e4 1523{
fc32b0e2
LB		 1524 struct mv643xx_eth_private *mp = netdev_priv(dev);
1525 u32 port_config;
1526 struct dev_addr_list *addr;
1527 int i;
c8aaea25 1528
fc32b0e2
LB		 1529 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1530 if (dev->flags & IFF_PROMISC)
1531 port_config |= UNICAST_PROMISCUOUS_MODE;
1532 else
1533 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1534 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1da177e4 1535
fc32b0e2
LB		 1536 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1537 int port_num = mp->port_num;
1538 u32 accept = 0x01010101;
c8aaea25 1539
fc32b0e2
LB		 1540 for (i = 0; i < 0x100; i += 4) {
1541 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1542 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1543 }
1544 return;
1545 }
c8aaea25 1546
fc32b0e2
LB		 1547 for (i = 0; i < 0x100; i += 4) {
1548 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1549 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1da177e4
LT		 1550 }
1551
fc32b0e2
LB		 1552 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1553 u8 *a = addr->da_addr;
1554 int table;
324ff2c1 1555
fc32b0e2
LB		 1556 if (addr->da_addrlen != 6)
1557 continue;
1da177e4 1558
fc32b0e2
LB		 1559 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1560 table = SPECIAL_MCAST_TABLE(mp->port_num);
1561 set_filter_table_entry(mp, table, a[5]);
1562 } else {
1563 int crc = addr_crc(a);
1da177e4 1564
fc32b0e2
LB		 1565 table = OTHER_MCAST_TABLE(mp->port_num);
1566 set_filter_table_entry(mp, table, crc);
1567 }
1568 }
c9df406f 1569}
c8aaea25 1570
c8aaea25 1571
c9df406f 1572/* rx/tx queue initialisation ***********************************************/
64da80a2 1573static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1574{
64da80a2 1575 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1576 struct rx_desc *rx_desc;
1577 int size;
c9df406f
LB		 1578 int i;
1579
64da80a2
LB		 1580 rxq->index = index;
1581
8a578111
LB		 1582 rxq->rx_ring_size = mp->default_rx_ring_size;
1583
1584 rxq->rx_desc_count = 0;
1585 rxq->rx_curr_desc = 0;
1586 rxq->rx_used_desc = 0;
1587
1588 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1589
f7981c1c 1590 if (index == 0 && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1591 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1592 mp->rx_desc_sram_size);
1593 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1594 } else {
1595 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1596 &rxq->rx_desc_dma,
1597 GFP_KERNEL);
f7ea3337
PJ		 1598 }
1599
8a578111
LB		 1600 if (rxq->rx_desc_area == NULL) {
1601 dev_printk(KERN_ERR, &mp->dev->dev,
1602 "can't allocate rx ring (%d bytes)\n", size);
1603 goto out;
1604 }
1605 memset(rxq->rx_desc_area, 0, size);
1da177e4 1606
8a578111
LB		 1607 rxq->rx_desc_area_size = size;
1608 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1609 GFP_KERNEL);
1610 if (rxq->rx_skb == NULL) {
1611 dev_printk(KERN_ERR, &mp->dev->dev,
1612 "can't allocate rx skb ring\n");
1613 goto out_free;
1614 }
1615
1616 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1617 for (i = 0; i < rxq->rx_ring_size; i++) {
9da78745
LB		 1618 int nexti;
1619
1620 nexti = i + 1;
1621 if (nexti == rxq->rx_ring_size)
1622 nexti = 0;
1623
8a578111
LB		 1624 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1625 nexti * sizeof(struct rx_desc);
1626 }
1627
8a578111
LB		 1628 return 0;
1629
1630
1631out_free:
f7981c1c 1632 if (index == 0 && size <= mp->rx_desc_sram_size)
8a578111
LB		 1633 iounmap(rxq->rx_desc_area);
1634 else
1635 dma_free_coherent(NULL, size,
1636 rxq->rx_desc_area,
1637 rxq->rx_desc_dma);
1638
1639out:
1640 return -ENOMEM;
c9df406f 1641}
c8aaea25 1642
8a578111 1643static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1644{
8a578111
LB		 1645 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1646 int i;
1647
1648 rxq_disable(rxq);
c8aaea25 1649
8a578111
LB		 1650 for (i = 0; i < rxq->rx_ring_size; i++) {
1651 if (rxq->rx_skb[i]) {
1652 dev_kfree_skb(rxq->rx_skb[i]);
1653 rxq->rx_desc_count--;
1da177e4 1654 }
c8aaea25 1655 }
1da177e4 1656
8a578111
LB		 1657 if (rxq->rx_desc_count) {
1658 dev_printk(KERN_ERR, &mp->dev->dev,
1659 "error freeing rx ring -- %d skbs stuck\n",
1660 rxq->rx_desc_count);
1661 }
1662
f7981c1c 1663 if (rxq->index == 0 &&
64da80a2 1664 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1665 iounmap(rxq->rx_desc_area);
c9df406f 1666 else
8a578111
LB		 1667 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1668 rxq->rx_desc_area, rxq->rx_desc_dma);
1669
1670 kfree(rxq->rx_skb);
c9df406f 1671}
1da177e4 1672
3d6b35bc 1673static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1674{
3d6b35bc 1675 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1676 struct tx_desc *tx_desc;
1677 int size;
c9df406f 1678 int i;
1da177e4 1679
3d6b35bc
LB		 1680 txq->index = index;
1681
13d64285
LB		 1682 txq->tx_ring_size = mp->default_tx_ring_size;
1683
1684 txq->tx_desc_count = 0;
1685 txq->tx_curr_desc = 0;
1686 txq->tx_used_desc = 0;
1687
1688 size = txq->tx_ring_size * sizeof(struct tx_desc);
1689
f7981c1c 1690 if (index == 0 && size <= mp->tx_desc_sram_size) {
13d64285
LB		 1691 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1692 mp->tx_desc_sram_size);
1693 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1694 } else {
1695 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1696 &txq->tx_desc_dma,
1697 GFP_KERNEL);
1698 }
1699
1700 if (txq->tx_desc_area == NULL) {
1701 dev_printk(KERN_ERR, &mp->dev->dev,
1702 "can't allocate tx ring (%d bytes)\n", size);
1703 goto out;
c9df406f 1704 }
13d64285
LB		 1705 memset(txq->tx_desc_area, 0, size);
1706
1707 txq->tx_desc_area_size = size;
1708 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1709 GFP_KERNEL);
1710 if (txq->tx_skb == NULL) {
1711 dev_printk(KERN_ERR, &mp->dev->dev,
1712 "can't allocate tx skb ring\n");
1713 goto out_free;
1714 }
1715
1716 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1717 for (i = 0; i < txq->tx_ring_size; i++) {
6b368f68 1718 struct tx_desc *txd = tx_desc + i;
9da78745
LB		 1719 int nexti;
1720
1721 nexti = i + 1;
1722 if (nexti == txq->tx_ring_size)
1723 nexti = 0;
6b368f68
LB		 1724
1725 txd->cmd_sts = 0;
1726 txd->next_desc_ptr = txq->tx_desc_dma +
13d64285
LB		 1727 nexti * sizeof(struct tx_desc);
1728 }
1729
1730 return 0;
1731
13d64285 1732out_free:
f7981c1c 1733 if (index == 0 && size <= mp->tx_desc_sram_size)
13d64285
LB		 1734 iounmap(txq->tx_desc_area);
1735 else
1736 dma_free_coherent(NULL, size,
1737 txq->tx_desc_area,
1738 txq->tx_desc_dma);
c9df406f 1739
13d64285
LB		 1740out:
1741 return -ENOMEM;
c8aaea25 1742}
1da177e4 1743
13d64285 1744static void txq_deinit(struct tx_queue *txq)
c9df406f 1745{
13d64285 1746 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 1747
13d64285 1748 txq_disable(txq);
1fa38c58 1749 txq_reclaim(txq, txq->tx_ring_size, 1);
1da177e4 1750
13d64285 1751 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 1752
f7981c1c 1753 if (txq->index == 0 &&
3d6b35bc 1754 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 1755 iounmap(txq->tx_desc_area);
c9df406f 1756 else
13d64285
LB		 1757 dma_free_coherent(NULL, txq->tx_desc_area_size,
1758 txq->tx_desc_area, txq->tx_desc_dma);
1759
1760 kfree(txq->tx_skb);
c9df406f 1761}
1da177e4 1762
1da177e4 1763
c9df406f 1764/* netdev ops and related ***************************************************/
1fa38c58
LB		 1765static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1766{
1767 u32 int_cause;
1768 u32 int_cause_ext;
1769
1770 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1771 (INT_TX_END | INT_RX | INT_EXT);
1772 if (int_cause == 0)
1773 return 0;
1774
1775 int_cause_ext = 0;
1776 if (int_cause & INT_EXT)
1777 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num));
1778
1779 int_cause &= INT_TX_END | INT_RX;
1780 if (int_cause) {
1781 wrl(mp, INT_CAUSE(mp->port_num), ~int_cause);
1782 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
1783 ~(rdl(mp, TXQ_COMMAND(mp->port_num)) & 0xff);
1784 mp->work_rx |= (int_cause & INT_RX) >> 2;
1785 }
1786
1787 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
1788 if (int_cause_ext) {
1789 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1790 if (int_cause_ext & INT_EXT_LINK_PHY)
1791 mp->work_link = 1;
1792 mp->work_tx |= int_cause_ext & INT_EXT_TX;
1793 }
1794
1795 return 1;
1796}
1797
1798static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1799{
1800 struct net_device *dev = (struct net_device *)dev_id;
1801 struct mv643xx_eth_private *mp = netdev_priv(dev);
1802
1803 if (unlikely(!mv643xx_eth_collect_events(mp)))
1804 return IRQ_NONE;
1805
1806 wrl(mp, INT_MASK(mp->port_num), 0);
1807 napi_schedule(&mp->napi);
1808
1809 return IRQ_HANDLED;
1810}
1811
2f7eb47a
LB		 1812static void handle_link_event(struct mv643xx_eth_private *mp)
1813{
1814 struct net_device *dev = mp->dev;
1815 u32 port_status;
1816 int speed;
1817 int duplex;
1818 int fc;
1819
1820 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1821 if (!(port_status & LINK_UP)) {
1822 if (netif_carrier_ok(dev)) {
1823 int i;
1824
1825 printk(KERN_INFO "%s: link down\n", dev->name);
1826
1827 netif_carrier_off(dev);
2f7eb47a 1828
f7981c1c 1829 for (i = 0; i < mp->txq_count; i++) {
2f7eb47a
LB		 1830 struct tx_queue *txq = mp->txq + i;
1831
1fa38c58 1832 txq_reclaim(txq, txq->tx_ring_size, 1);
f7981c1c 1833 txq_reset_hw_ptr(txq);
2f7eb47a
LB		 1834 }
1835 }
1836 return;
1837 }
1838
1839 switch (port_status & PORT_SPEED_MASK) {
1840 case PORT_SPEED_10:
1841 speed = 10;
1842 break;
1843 case PORT_SPEED_100:
1844 speed = 100;
1845 break;
1846 case PORT_SPEED_1000:
1847 speed = 1000;
1848 break;
1849 default:
1850 speed = -1;
1851 break;
1852 }
1853 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1854 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1855
1856 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1857 "flow control %sabled\n", dev->name,
1858 speed, duplex ? "full" : "half",
1859 fc ? "en" : "dis");
1860
4fdeca3f 1861 if (!netif_carrier_ok(dev))
2f7eb47a 1862 netif_carrier_on(dev);
2f7eb47a
LB		 1863}
1864
1fa38c58 1865static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
c9df406f 1866{
1fa38c58
LB		 1867 struct mv643xx_eth_private *mp;
1868 int work_done;
ce4e2e45 1869
1fa38c58 1870 mp = container_of(napi, struct mv643xx_eth_private, napi);
fc32b0e2 1871
1fa38c58
LB		 1872 mp->work_rx_refill |= mp->work_rx_oom;
1873 mp->work_rx_oom = 0;
1da177e4 1874
1fa38c58
LB		 1875 work_done = 0;
1876 while (work_done < budget) {
1877 u8 queue_mask;
1878 int queue;
1879 int work_tbd;
1880
1881 if (mp->work_link) {
1882 mp->work_link = 0;
1883 handle_link_event(mp);
1884 continue;
1885 }
1da177e4 1886
1fa38c58
LB		 1887 queue_mask = mp->work_tx | mp->work_tx_end |
1888 mp->work_rx | mp->work_rx_refill;
1889 if (!queue_mask) {
1890 if (mv643xx_eth_collect_events(mp))
1891 continue;
1892 break;
1893 }
1da177e4 1894
1fa38c58
LB		 1895 queue = fls(queue_mask) - 1;
1896 queue_mask = 1 << queue;
1897
1898 work_tbd = budget - work_done;
1899 if (work_tbd > 16)
1900 work_tbd = 16;
1901
1902 if (mp->work_tx_end & queue_mask) {
1903 txq_kick(mp->txq + queue);
1904 } else if (mp->work_tx & queue_mask) {
1905 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
1906 txq_maybe_wake(mp->txq + queue);
1907 } else if (mp->work_rx & queue_mask) {
1908 work_done += rxq_process(mp->rxq + queue, work_tbd);
1909 } else if (mp->work_rx_refill & queue_mask) {
1910 work_done += rxq_refill(mp->rxq + queue, work_tbd);
1911 } else {
1912 BUG();
1913 }
84dd619e 1914 }
fc32b0e2 1915
1fa38c58
LB		 1916 if (work_done < budget) {
1917 if (mp->work_rx_oom)
1918 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
1919 napi_complete(napi);
1920 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
226bb6b7 1921 }
3d6b35bc 1922
1fa38c58
LB		 1923 return work_done;
1924}
8fa89bf5 1925
1fa38c58
LB		 1926static inline void oom_timer_wrapper(unsigned long data)
1927{
1928 struct mv643xx_eth_private *mp = (void *)data;
1da177e4 1929
1fa38c58 1930 napi_schedule(&mp->napi);
1da177e4
LT		 1931}
1932
e5371493 1933static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 1934{
45c5d3bc
LB		 1935 int data;
1936
1937 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1938 if (data < 0)
1939 return;
1da177e4 1940
7f106c1d 1941 data |= BMCR_RESET;
45c5d3bc
LB		 1942 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data) < 0)
1943 return;
1da177e4 1944
c9df406f 1945 do {
45c5d3bc
LB		 1946 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1947 } while (data >= 0 && data & BMCR_RESET);
1da177e4
LT		 1948}
1949
fc32b0e2 1950static void port_start(struct mv643xx_eth_private *mp)
1da177e4 1951{
d0412d96 1952 u32 pscr;
8a578111 1953 int i;
1da177e4 1954
bedfe324
LB		 1955 /*
1956 * Perform PHY reset, if there is a PHY.
1957 */
1958 if (mp->phy_addr != -1) {
1959 struct ethtool_cmd cmd;
1960
1961 mv643xx_eth_get_settings(mp->dev, &cmd);
1962 phy_reset(mp);
1963 mv643xx_eth_set_settings(mp->dev, &cmd);
1964 }
1da177e4 1965
81600eea
LB		 1966 /*
1967 * Configure basic link parameters.
1968 */
1969 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1970
1971 pscr |= SERIAL_PORT_ENABLE;
1972 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1973
1974 pscr |= DO_NOT_FORCE_LINK_FAIL;
1975 if (mp->phy_addr == -1)
1976 pscr |= FORCE_LINK_PASS;
1977 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1978
1979 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1980
13d64285
LB		 1981 /*
1982 * Configure TX path and queues.
1983 */
89df5fdc 1984 tx_set_rate(mp, 1000000000, 16777216);
f7981c1c 1985 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc 1986 struct tx_queue *txq = mp->txq + i;
13d64285 1987
6b368f68 1988 txq_reset_hw_ptr(txq);
89df5fdc
LB		 1989 txq_set_rate(txq, 1000000000, 16777216);
1990 txq_set_fixed_prio_mode(txq);
13d64285
LB		 1991 }
1992
fc32b0e2
LB		 1993 /*
1994 * Add configured unicast address to address filter table.
1995 */
1996 uc_addr_set(mp, mp->dev->dev_addr);
1da177e4 1997
d9a073ea
LB		 1998 /*
1999 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2000 * frames to RX queue #0.
2001 */
8a578111 2002 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
01999873 2003
376489a2
LB		 2004 /*
2005 * Treat BPDUs as normal multicasts, and disable partition mode.
2006 */
8a578111 2007 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
01999873 2008
8a578111 2009 /*
64da80a2 2010 * Enable the receive queues.
8a578111 2011 */
f7981c1c 2012 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 2013 struct rx_queue *rxq = mp->rxq + i;
2014 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
8a578111 2015 u32 addr;
1da177e4 2016
8a578111
LB		 2017 addr = (u32)rxq->rx_desc_dma;
2018 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2019 wrl(mp, off, addr);
1da177e4 2020
8a578111
LB		 2021 rxq_enable(rxq);
2022 }
1da177e4
LT		 2023}
2024
ffd86bbe 2025static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 2026{
c9df406f 2027 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
773fc3ee 2028 u32 val;
1da177e4 2029
773fc3ee
LB		 2030 val = rdl(mp, SDMA_CONFIG(mp->port_num));
2031 if (mp->shared->extended_rx_coal_limit) {
2032 if (coal > 0xffff)
2033 coal = 0xffff;
2034 val &= ~0x023fff80;
2035 val |= (coal & 0x8000) << 10;
2036 val |= (coal & 0x7fff) << 7;
2037 } else {
2038 if (coal > 0x3fff)
2039 coal = 0x3fff;
2040 val &= ~0x003fff00;
2041 val |= (coal & 0x3fff) << 8;
2042 }
2043 wrl(mp, SDMA_CONFIG(mp->port_num), val);
1da177e4
LT		 2044}
2045
ffd86bbe 2046static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 2047{
c9df406f 2048 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 2049
fc32b0e2
LB		 2050 if (coal > 0x3fff)
2051 coal = 0x3fff;
2052 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
16e03018
DF		 2053}
2054
c9df406f 2055static int mv643xx_eth_open(struct net_device *dev)
16e03018 2056{
e5371493 2057 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2058 int err;
64da80a2 2059 int i;
16e03018 2060
fc32b0e2
LB		 2061 wrl(mp, INT_CAUSE(mp->port_num), 0);
2062 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
2063 rdl(mp, INT_CAUSE_EXT(mp->port_num));
c9df406f 2064
fc32b0e2 2065 err = request_irq(dev->irq, mv643xx_eth_irq,
2a1867a7 2066 IRQF_SHARED, dev->name, dev);
c9df406f 2067 if (err) {
fc32b0e2 2068 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
c9df406f 2069 return -EAGAIN;
16e03018
DF		 2070 }
2071
fc32b0e2 2072 init_mac_tables(mp);
16e03018 2073
2257e05c
LB		 2074 napi_enable(&mp->napi);
2075
f7981c1c 2076 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 2077 err = rxq_init(mp, i);
2078 if (err) {
2079 while (--i >= 0)
f7981c1c 2080 rxq_deinit(mp->rxq + i);
64da80a2
LB		 2081 goto out;
2082 }
2083
1fa38c58 2084 rxq_refill(mp->rxq + i, INT_MAX);
2257e05c
LB		 2085 }
2086
1fa38c58 2087 if (mp->work_rx_oom) {
2257e05c
LB		 2088 mp->rx_oom.expires = jiffies + (HZ / 10);
2089 add_timer(&mp->rx_oom);
64da80a2 2090 }
8a578111 2091
f7981c1c 2092 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc
LB		 2093 err = txq_init(mp, i);
2094 if (err) {
2095 while (--i >= 0)
f7981c1c 2096 txq_deinit(mp->txq + i);
3d6b35bc
LB		 2097 goto out_free;
2098 }
2099 }
16e03018 2100
2f7eb47a 2101 netif_carrier_off(dev);
2f7eb47a 2102
fc32b0e2 2103 port_start(mp);
16e03018 2104
ffd86bbe
LB		 2105 set_rx_coal(mp, 0);
2106 set_tx_coal(mp, 0);
16e03018 2107
befefe21 2108 wrl(mp, INT_MASK_EXT(mp->port_num), INT_EXT_LINK_PHY | INT_EXT_TX);
226bb6b7 2109 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
16e03018 2110
c9df406f
LB		 2111 return 0;
2112
13d64285 2113
fc32b0e2 2114out_free:
f7981c1c
LB		 2115 for (i = 0; i < mp->rxq_count; i++)
2116 rxq_deinit(mp->rxq + i);
fc32b0e2 2117out:
c9df406f
LB		 2118 free_irq(dev->irq, dev);
2119
2120 return err;
16e03018
DF		 2121}
2122
e5371493 2123static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 2124{
fc32b0e2 2125 unsigned int data;
64da80a2 2126 int i;
1da177e4 2127
f7981c1c
LB		 2128 for (i = 0; i < mp->rxq_count; i++)
2129 rxq_disable(mp->rxq + i);
2130 for (i = 0; i < mp->txq_count; i++)
2131 txq_disable(mp->txq + i);
ae9ae064
LB		 2132
2133 while (1) {
2134 u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
2135
2136 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2137 break;
13d64285 2138 udelay(10);
ae9ae064 2139 }
1da177e4 2140
c9df406f 2141 /* Reset the Enable bit in the Configuration Register */
fc32b0e2
LB		 2142 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2143 data &= ~(SERIAL_PORT_ENABLE |
2144 DO_NOT_FORCE_LINK_FAIL |
2145 FORCE_LINK_PASS);
2146 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
1da177e4
LT		 2147}
2148
c9df406f 2149static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 2150{
e5371493 2151 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 2152 int i;
1da177e4 2153
fc32b0e2
LB		 2154 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2155 rdl(mp, INT_MASK(mp->port_num));
1da177e4 2156
c9df406f 2157 napi_disable(&mp->napi);
78fff83b 2158
2257e05c
LB		 2159 del_timer_sync(&mp->rx_oom);
2160
c9df406f 2161 netif_carrier_off(dev);
1da177e4 2162
fc32b0e2
LB		 2163 free_irq(dev->irq, dev);
2164
cc9754b3 2165 port_reset(mp);
8fd89211 2166 mv643xx_eth_get_stats(dev);
fc32b0e2 2167 mib_counters_update(mp);
1da177e4 2168
f7981c1c
LB		 2169 for (i = 0; i < mp->rxq_count; i++)
2170 rxq_deinit(mp->rxq + i);
2171 for (i = 0; i < mp->txq_count; i++)
2172 txq_deinit(mp->txq + i);
1da177e4 2173
c9df406f 2174 return 0;
1da177e4
LT		 2175}
2176
fc32b0e2 2177static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 2178{
e5371493 2179 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2180
bedfe324
LB		 2181 if (mp->phy_addr != -1)
2182 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2183
2184 return -EOPNOTSUPP;
1da177e4
LT		 2185}
2186
c9df406f 2187static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 2188{
89df5fdc
LB		 2189 struct mv643xx_eth_private *mp = netdev_priv(dev);
2190
fc32b0e2 2191 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 2192 return -EINVAL;
1da177e4 2193
c9df406f 2194 dev->mtu = new_mtu;
89df5fdc
LB		 2195 tx_set_rate(mp, 1000000000, 16777216);
2196
c9df406f
LB		 2197 if (!netif_running(dev))
2198 return 0;
1da177e4 2199
c9df406f
LB		 2200 /*
2201 * Stop and then re-open the interface. This will allocate RX
2202 * skbs of the new MTU.
2203 * There is a possible danger that the open will not succeed,
fc32b0e2 2204 * due to memory being full.
c9df406f
LB		 2205 */
2206 mv643xx_eth_stop(dev);
2207 if (mv643xx_eth_open(dev)) {
fc32b0e2
LB		 2208 dev_printk(KERN_ERR, &dev->dev,
2209 "fatal error on re-opening device after "
2210 "MTU change\n");
c9df406f
LB		 2211 }
2212
2213 return 0;
1da177e4
LT		 2214}
2215
fc32b0e2 2216static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2217{
fc32b0e2 2218 struct mv643xx_eth_private *mp;
1da177e4 2219
fc32b0e2
LB		 2220 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2221 if (netif_running(mp->dev)) {
e5ef1de1 2222 netif_tx_stop_all_queues(mp->dev);
fc32b0e2
LB		 2223 port_reset(mp);
2224 port_start(mp);
e5ef1de1 2225 netif_tx_wake_all_queues(mp->dev);
fc32b0e2 2226 }
c9df406f
LB		 2227}
2228
c9df406f 2229static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2230{
e5371493 2231 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2232
fc32b0e2 2233 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
d0412d96 2234
c9df406f 2235 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2236}
2237
c9df406f 2238#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2239static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2240{
fc32b0e2 2241 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2242
fc32b0e2
LB		 2243 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2244 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2245
fc32b0e2 2246 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2247
f2ca60f2 2248 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
9f8dd319 2249}
c9df406f 2250#endif
9f8dd319 2251
fc32b0e2 2252static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
9f8dd319 2253{
e5371493 2254 struct mv643xx_eth_private *mp = netdev_priv(dev);
45c5d3bc 2255 return smi_reg_read(mp, addr, reg);
9f8dd319
DF		 2256}
2257
fc32b0e2 2258static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
9f8dd319 2259{
e5371493 2260 struct mv643xx_eth_private *mp = netdev_priv(dev);
fc32b0e2 2261 smi_reg_write(mp, addr, reg, val);
c9df406f 2262}
9f8dd319 2263
9f8dd319 2264
c9df406f 2265/* platform glue ************************************************************/
e5371493
LB		 2266static void
2267mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2268 struct mbus_dram_target_info *dram)
c9df406f 2269{
cc9754b3 2270 void __iomem *base = msp->base;
c9df406f
LB		 2271 u32 win_enable;
2272 u32 win_protect;
2273 int i;
9f8dd319 2274
c9df406f
LB		 2275 for (i = 0; i < 6; i++) {
2276 writel(0, base + WINDOW_BASE(i));
2277 writel(0, base + WINDOW_SIZE(i));
2278 if (i < 4)
2279 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2280 }
2281
c9df406f
LB		 2282 win_enable = 0x3f;
2283 win_protect = 0;
2284
2285 for (i = 0; i < dram->num_cs; i++) {
2286 struct mbus_dram_window *cs = dram->cs + i;
2287
2288 writel((cs->base & 0xffff0000) |
2289 (cs->mbus_attr << 8) |
2290 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2291 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2292
2293 win_enable &= ~(1 << i);
2294 win_protect |= 3 << (2 * i);
2295 }
2296
2297 writel(win_enable, base + WINDOW_BAR_ENABLE);
2298 msp->win_protect = win_protect;
9f8dd319
DF		 2299}
2300
773fc3ee
LB		 2301static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2302{
2303 /*
2304 * Check whether we have a 14-bit coal limit field in bits
2305 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2306 * SDMA config register.
2307 */
2308 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2309 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2310 msp->extended_rx_coal_limit = 1;
2311 else
2312 msp->extended_rx_coal_limit = 0;
1e881592
LB		 2313
2314 /*
2315 * Check whether the TX rate control registers are in the
2316 * old or the new place.
2317 */
2318 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2319 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
2320 msp->tx_bw_control_moved = 1;
2321 else
2322 msp->tx_bw_control_moved = 0;
773fc3ee
LB		 2323}
2324
c9df406f 2325static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2326{
e5371493 2327 static int mv643xx_eth_version_printed = 0;
c9df406f 2328 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2329 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 2330 struct resource *res;
2331 int ret;
9f8dd319 2332
e5371493 2333 if (!mv643xx_eth_version_printed++)
7dde154d
LB		 2334 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2335 "driver version %s\n", mv643xx_eth_driver_version);
9f8dd319 2336
c9df406f
LB		 2337 ret = -EINVAL;
2338 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2339 if (res == NULL)
2340 goto out;
9f8dd319 2341
c9df406f
LB		 2342 ret = -ENOMEM;
2343 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2344 if (msp == NULL)
2345 goto out;
2346 memset(msp, 0, sizeof(*msp));
2347
cc9754b3
LB		 2348 msp->base = ioremap(res->start, res->end - res->start + 1);
2349 if (msp->base == NULL)
c9df406f
LB		 2350 goto out_free;
2351
fc0eb9f2
LB		 2352 msp->smi = msp;
2353 if (pd != NULL && pd->shared_smi != NULL)
2354 msp->smi = platform_get_drvdata(pd->shared_smi);
2355
2b3ba0e3 2356 mutex_init(&msp->phy_lock);
c9df406f 2357
45c5d3bc
LB		 2358 msp->err_interrupt = NO_IRQ;
2359 init_waitqueue_head(&msp->smi_busy_wait);
2360
2361 /*
2362 * Check whether the error interrupt is hooked up.
2363 */
2364 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2365 if (res != NULL) {
2366 int err;
2367
2368 err = request_irq(res->start, mv643xx_eth_err_irq,
2369 IRQF_SHARED, "mv643xx_eth", msp);
2370 if (!err) {
2371 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2372 msp->err_interrupt = res->start;
2373 }
2374 }
2375
c9df406f
LB		 2376 /*
2377 * (Re-)program MBUS remapping windows if we are asked to.
2378 */
2379 if (pd != NULL && pd->dram != NULL)
2380 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2381
fc32b0e2
LB		 2382 /*
2383 * Detect hardware parameters.
2384 */
2385 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
773fc3ee 2386 infer_hw_params(msp);
fc32b0e2
LB		 2387
2388 platform_set_drvdata(pdev, msp);
2389
c9df406f
LB		 2390 return 0;
2391
2392out_free:
2393 kfree(msp);
2394out:
2395 return ret;
2396}
2397
2398static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2399{
e5371493 2400 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
c9df406f 2401
45c5d3bc
LB		 2402 if (msp->err_interrupt != NO_IRQ)
2403 free_irq(msp->err_interrupt, msp);
cc9754b3 2404 iounmap(msp->base);
c9df406f
LB		 2405 kfree(msp);
2406
2407 return 0;
9f8dd319
DF		 2408}
2409
c9df406f 2410static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2411 .probe = mv643xx_eth_shared_probe,
2412 .remove = mv643xx_eth_shared_remove,
c9df406f 2413 .driver = {
fc32b0e2 2414 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2415 .owner = THIS_MODULE,
2416 },
2417};
2418
e5371493 2419static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2420{
c9df406f 2421 int addr_shift = 5 * mp->port_num;
fc32b0e2 2422 u32 data;
1da177e4 2423
fc32b0e2
LB		 2424 data = rdl(mp, PHY_ADDR);
2425 data &= ~(0x1f << addr_shift);
2426 data |= (phy_addr & 0x1f) << addr_shift;
2427 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2428}
2429
e5371493 2430static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2431{
fc32b0e2
LB		 2432 unsigned int data;
2433
2434 data = rdl(mp, PHY_ADDR);
2435
2436 return (data >> (5 * mp->port_num)) & 0x1f;
2437}
2438
2439static void set_params(struct mv643xx_eth_private *mp,
2440 struct mv643xx_eth_platform_data *pd)
2441{
2442 struct net_device *dev = mp->dev;
2443
2444 if (is_valid_ether_addr(pd->mac_addr))
2445 memcpy(dev->dev_addr, pd->mac_addr, 6);
2446 else
2447 uc_addr_get(mp, dev->dev_addr);
2448
ac840605 2449 if (pd->phy_addr == MV643XX_ETH_PHY_NONE) {
fc32b0e2
LB		 2450 mp->phy_addr = -1;
2451 } else {
ac840605 2452 if (pd->phy_addr != MV643XX_ETH_PHY_ADDR_DEFAULT) {
fc32b0e2
LB		 2453 mp->phy_addr = pd->phy_addr & 0x3f;
2454 phy_addr_set(mp, mp->phy_addr);
2455 } else {
2456 mp->phy_addr = phy_addr_get(mp);
2457 }
2458 }
1da177e4 2459
fc32b0e2
LB		 2460 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2461 if (pd->rx_queue_size)
2462 mp->default_rx_ring_size = pd->rx_queue_size;
2463 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2464 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2465
f7981c1c 2466 mp->rxq_count = pd->rx_queue_count ? : 1;
64da80a2 2467
fc32b0e2
LB		 2468 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2469 if (pd->tx_queue_size)
2470 mp->default_tx_ring_size = pd->tx_queue_size;
2471 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2472 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc 2473
f7981c1c 2474 mp->txq_count = pd->tx_queue_count ? : 1;
1da177e4
LT		 2475}
2476
e5371493 2477static int phy_detect(struct mv643xx_eth_private *mp)
1da177e4 2478{
45c5d3bc
LB		 2479 int data;
2480 int data2;
2481
2482 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2483 if (data < 0)
2484 return -ENODEV;
2485
2486 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data ^ BMCR_ANENABLE) < 0)
2487 return -ENODEV;
fc32b0e2 2488
45c5d3bc
LB		 2489 data2 = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2490 if (data2 < 0)
2491 return -ENODEV;
1da177e4 2492
7f106c1d 2493 if (((data ^ data2) & BMCR_ANENABLE) == 0)
fc32b0e2 2494 return -ENODEV;
1da177e4 2495
7f106c1d 2496 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
1da177e4 2497
c9df406f 2498 return 0;
1da177e4
LT		 2499}
2500
fc32b0e2
LB		 2501static int phy_init(struct mv643xx_eth_private *mp,
2502 struct mv643xx_eth_platform_data *pd)
c28a4f89 2503{
fc32b0e2
LB		 2504 struct ethtool_cmd cmd;
2505 int err;
c28a4f89 2506
fc32b0e2
LB		 2507 err = phy_detect(mp);
2508 if (err) {
2509 dev_printk(KERN_INFO, &mp->dev->dev,
2510 "no PHY detected at addr %d\n", mp->phy_addr);
2511 return err;
2512 }
2513 phy_reset(mp);
2514
2515 mp->mii.phy_id = mp->phy_addr;
2516 mp->mii.phy_id_mask = 0x3f;
2517 mp->mii.reg_num_mask = 0x1f;
2518 mp->mii.dev = mp->dev;
2519 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2520 mp->mii.mdio_write = mv643xx_eth_mdio_write;
c28a4f89 2521
fc32b0e2 2522 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
c9df406f 2523
fc32b0e2
LB		 2524 memset(&cmd, 0, sizeof(cmd));
2525
2526 cmd.port = PORT_MII;
2527 cmd.transceiver = XCVR_INTERNAL;
2528 cmd.phy_address = mp->phy_addr;
2529 if (pd->speed == 0) {
2530 cmd.autoneg = AUTONEG_ENABLE;
2531 cmd.speed = SPEED_100;
2532 cmd.advertising = ADVERTISED_10baseT_Half |
2533 ADVERTISED_10baseT_Full |
2534 ADVERTISED_100baseT_Half |
2535 ADVERTISED_100baseT_Full;
c9df406f 2536 if (mp->mii.supports_gmii)
fc32b0e2 2537 cmd.advertising |= ADVERTISED_1000baseT_Full;
c9df406f 2538 } else {
fc32b0e2
LB		 2539 cmd.autoneg = AUTONEG_DISABLE;
2540 cmd.speed = pd->speed;
2541 cmd.duplex = pd->duplex;
c9df406f 2542 }
fc32b0e2 2543
fc32b0e2
LB		 2544 mv643xx_eth_set_settings(mp->dev, &cmd);
2545
2546 return 0;
c28a4f89
JC		 2547}
2548
81600eea
LB		 2549static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2550{
2551 u32 pscr;
2552
2553 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2554 if (pscr & SERIAL_PORT_ENABLE) {
2555 pscr &= ~SERIAL_PORT_ENABLE;
2556 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2557 }
2558
2559 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2560 if (mp->phy_addr == -1) {
2561 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2562 if (speed == SPEED_1000)
2563 pscr |= SET_GMII_SPEED_TO_1000;
2564 else if (speed == SPEED_100)
2565 pscr |= SET_MII_SPEED_TO_100;
2566
2567 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2568
2569 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2570 if (duplex == DUPLEX_FULL)
2571 pscr |= SET_FULL_DUPLEX_MODE;
2572 }
2573
2574 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2575}
2576
c9df406f 2577static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2578{
c9df406f 2579 struct mv643xx_eth_platform_data *pd;
e5371493 2580 struct mv643xx_eth_private *mp;
c9df406f 2581 struct net_device *dev;
c9df406f 2582 struct resource *res;
c9df406f 2583 DECLARE_MAC_BUF(mac);
fc32b0e2 2584 int err;
1da177e4 2585
c9df406f
LB		 2586 pd = pdev->dev.platform_data;
2587 if (pd == NULL) {
fc32b0e2
LB		 2588 dev_printk(KERN_ERR, &pdev->dev,
2589 "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2590 return -ENODEV;
2591 }
1da177e4 2592
c9df406f 2593 if (pd->shared == NULL) {
fc32b0e2
LB		 2594 dev_printk(KERN_ERR, &pdev->dev,
2595 "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2596 return -ENODEV;
2597 }
8f518703 2598
e5ef1de1 2599 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
c9df406f
LB		 2600 if (!dev)
2601 return -ENOMEM;
1da177e4 2602
c9df406f 2603 mp = netdev_priv(dev);
fc32b0e2
LB		 2604 platform_set_drvdata(pdev, mp);
2605
2606 mp->shared = platform_get_drvdata(pd->shared);
2607 mp->port_num = pd->port_number;
2608
c9df406f 2609 mp->dev = dev;
78fff83b 2610
fc32b0e2 2611 set_params(mp, pd);
e5ef1de1 2612 dev->real_num_tx_queues = mp->txq_count;
fc32b0e2 2613
fc32b0e2
LB		 2614 mib_counters_clear(mp);
2615 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2616
bedfe324
LB		 2617 if (mp->phy_addr != -1) {
2618 err = phy_init(mp, pd);
2619 if (err)
2620 goto out;
2621
2622 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2623 } else {
2624 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2625 }
81600eea 2626 init_pscr(mp, pd->speed, pd->duplex);
fc32b0e2 2627
2257e05c
LB		 2628 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2629
2630 init_timer(&mp->rx_oom);
2631 mp->rx_oom.data = (unsigned long)mp;
2632 mp->rx_oom.function = oom_timer_wrapper;
2633
fc32b0e2 2634
c9df406f
LB		 2635 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2636 BUG_ON(!res);
2637 dev->irq = res->start;
1da177e4 2638
8fd89211 2639 dev->get_stats = mv643xx_eth_get_stats;
fc32b0e2 2640 dev->hard_start_xmit = mv643xx_eth_xmit;
c9df406f
LB		 2641 dev->open = mv643xx_eth_open;
2642 dev->stop = mv643xx_eth_stop;
c9df406f 2643 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
fc32b0e2
LB		 2644 dev->set_mac_address = mv643xx_eth_set_mac_address;
2645 dev->do_ioctl = mv643xx_eth_ioctl;
2646 dev->change_mtu = mv643xx_eth_change_mtu;
c9df406f 2647 dev->tx_timeout = mv643xx_eth_tx_timeout;
c9df406f 2648#ifdef CONFIG_NET_POLL_CONTROLLER
e5371493 2649 dev->poll_controller = mv643xx_eth_netpoll;
c9df406f 2650#endif
c9df406f
LB		 2651 dev->watchdog_timeo = 2 * HZ;
2652 dev->base_addr = 0;
1da177e4 2653
c9df406f 2654 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
e32b6617 2655 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4 2656
fc32b0e2 2657 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2658
c9df406f 2659 if (mp->shared->win_protect)
fc32b0e2 2660 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2661
c9df406f
LB		 2662 err = register_netdev(dev);
2663 if (err)
2664 goto out;
1da177e4 2665
fc32b0e2
LB		 2666 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2667 mp->port_num, print_mac(mac, dev->dev_addr));
1da177e4 2668
13d64285 2669 if (mp->tx_desc_sram_size > 0)
fc32b0e2 2670 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
1da177e4 2671
c9df406f 2672 return 0;
1da177e4 2673
c9df406f
LB		 2674out:
2675 free_netdev(dev);
1da177e4 2676
c9df406f 2677 return err;
1da177e4
LT		 2678}
2679
c9df406f 2680static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2681{
fc32b0e2 2682 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2683
fc32b0e2 2684 unregister_netdev(mp->dev);
c9df406f 2685 flush_scheduled_work();
fc32b0e2 2686 free_netdev(mp->dev);
c9df406f 2687
c9df406f 2688 platform_set_drvdata(pdev, NULL);
fc32b0e2 2689
c9df406f 2690 return 0;
1da177e4
LT		 2691}
2692
c9df406f 2693static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2694{
fc32b0e2 2695 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 2696
c9df406f 2697 /* Mask all interrupts on ethernet port */
fc32b0e2
LB		 2698 wrl(mp, INT_MASK(mp->port_num), 0);
2699 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2700
fc32b0e2
LB		 2701 if (netif_running(mp->dev))
2702 port_reset(mp);
d0412d96
JC		 2703}
2704
c9df406f 2705static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 2706 .probe = mv643xx_eth_probe,
2707 .remove = mv643xx_eth_remove,
2708 .shutdown = mv643xx_eth_shutdown,
c9df406f 2709 .driver = {
fc32b0e2 2710 .name = MV643XX_ETH_NAME,
c9df406f
LB		 2711 .owner = THIS_MODULE,
2712 },
2713};
2714
e5371493 2715static int __init mv643xx_eth_init_module(void)
d0412d96 2716{
c9df406f 2717 int rc;
d0412d96 2718
c9df406f
LB		 2719 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2720 if (!rc) {
2721 rc = platform_driver_register(&mv643xx_eth_driver);
2722 if (rc)
2723 platform_driver_unregister(&mv643xx_eth_shared_driver);
2724 }
fc32b0e2 2725
c9df406f 2726 return rc;
d0412d96 2727}
fc32b0e2 2728module_init(mv643xx_eth_init_module);
d0412d96 2729
e5371493 2730static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 2731{
c9df406f
LB		 2732 platform_driver_unregister(&mv643xx_eth_driver);
2733 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 2734}
e5371493 2735module_exit(mv643xx_eth_cleanup_module);
1da177e4 2736
45675bc6
LB		 2737MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2738 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
c9df406f 2739MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 2740MODULE_LICENSE("GPL");
c9df406f 2741MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 2742MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux kernel - Deliverables
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