projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'for-linus' of master.kernel.org:/pub/scm/linux/kernel/git/roland/infiniband
[deliverable/linux.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 rabeeh@galileo.co.il
7 *
8 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 9 * written by Manish Lachwani
1da177e4
LT		 10 *
11 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
12 *
c8aaea25 13 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 14 * Dale Farnsworth <dale@farnsworth.org>
15 *
16 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
17 * <sjhill@realitydiluted.com>
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version 2
22 * of the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 */
33#include <linux/init.h>
34#include <linux/dma-mapping.h>
b6298c22
AV		 35#include <linux/in.h>
36#include <linux/ip.h>
1da177e4
LT		 37#include <linux/tcp.h>
38#include <linux/udp.h>
39#include <linux/etherdevice.h>
40
41#include <linux/bitops.h>
42#include <linux/delay.h>
43#include <linux/ethtool.h>
d052d1be
RK		 44#include <linux/platform_device.h>
45
1da177e4
LT		 46#include <asm/io.h>
47#include <asm/types.h>
48#include <asm/pgtable.h>
49#include <asm/system.h>
50#include <asm/delay.h>
51#include "mv643xx_eth.h"
52
1da177e4 53/* Static function declarations */
1da177e4
LT		 54static void eth_port_uc_addr_get(struct net_device *dev,
55 unsigned char *MacAddr);
16e03018 56static void eth_port_set_multicast_list(struct net_device *);
9f8dd319 57static void mv643xx_eth_port_enable_tx(unsigned int port_num,
12a87c64 58 unsigned int queues);
9f8dd319 59static void mv643xx_eth_port_enable_rx(unsigned int port_num,
12a87c64 60 unsigned int queues);
9f8dd319
DF		 61static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num);
62static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num);
ab4384a6
DF		 63static int mv643xx_eth_open(struct net_device *);
64static int mv643xx_eth_stop(struct net_device *);
1da177e4
LT		 65static int mv643xx_eth_change_mtu(struct net_device *, int);
66static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *);
67static void eth_port_init_mac_tables(unsigned int eth_port_num);
68#ifdef MV643XX_NAPI
69static int mv643xx_poll(struct net_device *dev, int *budget);
70#endif
c28a4f89 71static int ethernet_phy_get(unsigned int eth_port_num);
1da177e4
LT		 72static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
73static int ethernet_phy_detect(unsigned int eth_port_num);
c28a4f89
JC		 74static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location);
75static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val);
d0412d96 76static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
7282d491 77static const struct ethtool_ops mv643xx_ethtool_ops;
1da177e4
LT		 78
79static char mv643xx_driver_name[] = "mv643xx_eth";
80static char mv643xx_driver_version[] = "1.0";
81
82static void __iomem *mv643xx_eth_shared_base;
83
84/* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */
a9f6a0dd 85static DEFINE_SPINLOCK(mv643xx_eth_phy_lock);
1da177e4
LT		 86
87static inline u32 mv_read(int offset)
88{
dc074a8a 89 void __iomem *reg_base;
1da177e4
LT		 90
91 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
92
93 return readl(reg_base + offset);
94}
95
96static inline void mv_write(int offset, u32 data)
97{
dc074a8a 98 void __iomem *reg_base;
1da177e4
LT		 99
100 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
101 writel(data, reg_base + offset);
102}
103
104/*
105 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
106 *
107 * Input : pointer to ethernet interface network device structure
108 * new mtu size
109 * Output : 0 upon success, -EINVAL upon failure
110 */
111static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
112{
8f518703 113 if ((new_mtu > 9500) || (new_mtu < 64))
1da177e4 114 return -EINVAL;
1da177e4
LT		 115
116 dev->mtu = new_mtu;
117 /*
118 * Stop then re-open the interface. This will allocate RX skb's with
119 * the new MTU.
120 * There is a possible danger that the open will not successed, due
121 * to memory is full, which might fail the open function.
122 */
123 if (netif_running(dev)) {
ab4384a6
DF		 124 mv643xx_eth_stop(dev);
125 if (mv643xx_eth_open(dev))
1da177e4
LT		 126 printk(KERN_ERR
127 "%s: Fatal error on opening device\n",
128 dev->name);
129 }
130
1da177e4
LT		 131 return 0;
132}
133
134/*
f78fb474 135 * mv643xx_eth_rx_refill_descs
1da177e4
LT		 136 *
137 * Fills / refills RX queue on a certain gigabit ethernet port
138 *
139 * Input : pointer to ethernet interface network device structure
140 * Output : N/A
141 */
f78fb474 142static void mv643xx_eth_rx_refill_descs(struct net_device *dev)
1da177e4 143{
1da177e4
LT		 144 struct mv643xx_private *mp = netdev_priv(dev);
145 struct pkt_info pkt_info;
146 struct sk_buff *skb;
b44cd572 147 int unaligned;
1da177e4 148
f78fb474 149 while (mp->rx_desc_count < mp->rx_ring_size) {
908b637f 150 skb = dev_alloc_skb(ETH_RX_SKB_SIZE + dma_get_cache_alignment());
1da177e4
LT		 151 if (!skb)
152 break;
f98e36f1 153 mp->rx_desc_count++;
908b637f 154 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
b44cd572 155 if (unaligned)
908b637f 156 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
1da177e4 157 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
7303fde8
DF		 158 pkt_info.byte_cnt = ETH_RX_SKB_SIZE;
159 pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
160 ETH_RX_SKB_SIZE, DMA_FROM_DEVICE);
1da177e4
LT		 161 pkt_info.return_info = skb;
162 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
163 printk(KERN_ERR
164 "%s: Error allocating RX Ring\n", dev->name);
165 break;
166 }
7303fde8 167 skb_reserve(skb, ETH_HW_IP_ALIGN);
1da177e4 168 }
1da177e4
LT		 169 /*
170 * If RX ring is empty of SKB, set a timer to try allocating
f78fb474 171 * again at a later time.
1da177e4 172 */
f78fb474 173 if (mp->rx_desc_count == 0) {
1da177e4 174 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
f78fb474 175 mp->timeout.expires = jiffies + (HZ / 10); /* 100 mSec */
1da177e4 176 add_timer(&mp->timeout);
1da177e4 177 }
1da177e4
LT		 178}
179
180/*
f78fb474 181 * mv643xx_eth_rx_refill_descs_timer_wrapper
1da177e4
LT		 182 *
183 * Timer routine to wake up RX queue filling task. This function is
184 * used only in case the RX queue is empty, and all alloc_skb has
185 * failed (due to out of memory event).
186 *
187 * Input : pointer to ethernet interface network device structure
188 * Output : N/A
189 */
f78fb474 190static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data)
1da177e4 191{
f78fb474 192 mv643xx_eth_rx_refill_descs((struct net_device *)data);
1da177e4
LT		 193}
194
195/*
196 * mv643xx_eth_update_mac_address
197 *
198 * Update the MAC address of the port in the address table
199 *
200 * Input : pointer to ethernet interface network device structure
201 * Output : N/A
202 */
203static void mv643xx_eth_update_mac_address(struct net_device *dev)
204{
205 struct mv643xx_private *mp = netdev_priv(dev);
206 unsigned int port_num = mp->port_num;
207
208 eth_port_init_mac_tables(port_num);
ed9b5d45 209 eth_port_uc_addr_set(port_num, dev->dev_addr);
1da177e4
LT		 210}
211
212/*
213 * mv643xx_eth_set_rx_mode
214 *
215 * Change from promiscuos to regular rx mode
216 *
217 * Input : pointer to ethernet interface network device structure
218 * Output : N/A
219 */
220static void mv643xx_eth_set_rx_mode(struct net_device *dev)
221{
222 struct mv643xx_private *mp = netdev_priv(dev);
01999873 223 u32 config_reg;
1da177e4 224
01999873 225 config_reg = mv_read(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num));
1da177e4 226 if (dev->flags & IFF_PROMISC)
01999873 227 config_reg |= (u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
1da177e4 228 else
01999873
DF		 229 config_reg &= ~(u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
230 mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num), config_reg);
16e03018
DF		 231
232 eth_port_set_multicast_list(dev);
1da177e4
LT		 233}
234
235/*
236 * mv643xx_eth_set_mac_address
237 *
238 * Change the interface's mac address.
239 * No special hardware thing should be done because interface is always
240 * put in promiscuous mode.
241 *
242 * Input : pointer to ethernet interface network device structure and
243 * a pointer to the designated entry to be added to the cache.
244 * Output : zero upon success, negative upon failure
245 */
246static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
247{
248 int i;
249
250 for (i = 0; i < 6; i++)
251 /* +2 is for the offset of the HW addr type */
252 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
253 mv643xx_eth_update_mac_address(dev);
254 return 0;
255}
256
257/*
258 * mv643xx_eth_tx_timeout
259 *
260 * Called upon a timeout on transmitting a packet
261 *
262 * Input : pointer to ethernet interface network device structure.
263 * Output : N/A
264 */
265static void mv643xx_eth_tx_timeout(struct net_device *dev)
266{
267 struct mv643xx_private *mp = netdev_priv(dev);
268
269 printk(KERN_INFO "%s: TX timeout ", dev->name);
270
271 /* Do the reset outside of interrupt context */
272 schedule_work(&mp->tx_timeout_task);
273}
274
275/*
276 * mv643xx_eth_tx_timeout_task
277 *
278 * Actual routine to reset the adapter when a timeout on Tx has occurred
279 */
91c7c568 280static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly)
1da177e4 281{
91c7c568
AV		 282 struct mv643xx_private *mp = container_of(ugly, struct mv643xx_private,
283 tx_timeout_task);
284 struct net_device *dev = mp->mii.dev; /* yuck */
1da177e4 285
94843566
DF		 286 if (!netif_running(dev))
287 return;
288
289 netif_stop_queue(dev);
290
1da177e4 291 eth_port_reset(mp->port_num);
ed9b5d45 292 eth_port_start(dev);
94843566
DF		 293
294 if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
295 netif_wake_queue(dev);
1da177e4
LT		 296}
297
ff561eef
DF		 298/**
299 * mv643xx_eth_free_tx_descs - Free the tx desc data for completed descriptors
1da177e4 300 *
ff561eef 301 * If force is non-zero, frees uncompleted descriptors as well
1da177e4 302 */
ff561eef 303int mv643xx_eth_free_tx_descs(struct net_device *dev, int force)
1da177e4
LT		 304{
305 struct mv643xx_private *mp = netdev_priv(dev);
ff561eef
DF		 306 struct eth_tx_desc *desc;
307 u32 cmd_sts;
308 struct sk_buff *skb;
309 unsigned long flags;
310 int tx_index;
311 dma_addr_t addr;
312 int count;
313 int released = 0;
1da177e4 314
ff561eef
DF		 315 while (mp->tx_desc_count > 0) {
316 spin_lock_irqsave(&mp->lock, flags);
d344bff9
DF		 317
318 /* tx_desc_count might have changed before acquiring the lock */
319 if (mp->tx_desc_count <= 0) {
320 spin_unlock_irqrestore(&mp->lock, flags);
321 return released;
322 }
323
ff561eef
DF		 324 tx_index = mp->tx_used_desc_q;
325 desc = &mp->p_tx_desc_area[tx_index];
326 cmd_sts = desc->cmd_sts;
327
328 if (!force && (cmd_sts & ETH_BUFFER_OWNED_BY_DMA)) {
329 spin_unlock_irqrestore(&mp->lock, flags);
330 return released;
331 }
332
333 mp->tx_used_desc_q = (tx_index + 1) % mp->tx_ring_size;
334 mp->tx_desc_count--;
335
336 addr = desc->buf_ptr;
337 count = desc->byte_cnt;
338 skb = mp->tx_skb[tx_index];
339 if (skb)
340 mp->tx_skb[tx_index] = NULL;
341
7303fde8 342 if (cmd_sts & ETH_ERROR_SUMMARY) {
1da177e4 343 printk("%s: Error in TX\n", dev->name);
ff561eef 344 mp->stats.tx_errors++;
1da177e4
LT		 345 }
346
d344bff9
DF		 347 spin_unlock_irqrestore(&mp->lock, flags);
348
ff561eef
DF		 349 if (cmd_sts & ETH_TX_FIRST_DESC)
350 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
cb415d30 351 else
ff561eef 352 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
1da177e4 353
ff561eef
DF		 354 if (skb)
355 dev_kfree_skb_irq(skb);
356
357 released = 1;
1da177e4
LT		 358 }
359
1da177e4
LT		 360 return released;
361}
362
ff561eef
DF		 363static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev)
364{
365 struct mv643xx_private *mp = netdev_priv(dev);
366
367 if (mv643xx_eth_free_tx_descs(dev, 0) &&
368 mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
369 netif_wake_queue(dev);
370}
371
372static void mv643xx_eth_free_all_tx_descs(struct net_device *dev)
373{
374 mv643xx_eth_free_tx_descs(dev, 1);
375}
376
1da177e4
LT		 377/*
378 * mv643xx_eth_receive
379 *
380 * This function is forward packets that are received from the port's
381 * queues toward kernel core or FastRoute them to another interface.
382 *
383 * Input : dev - a pointer to the required interface
384 * max - maximum number to receive (0 means unlimted)
385 *
386 * Output : number of served packets
387 */
1da177e4 388static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
1da177e4
LT		 389{
390 struct mv643xx_private *mp = netdev_priv(dev);
391 struct net_device_stats *stats = &mp->stats;
392 unsigned int received_packets = 0;
393 struct sk_buff *skb;
394 struct pkt_info pkt_info;
395
b1dd9ca1 396 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
54caf44d 397 dma_unmap_single(NULL, pkt_info.buf_ptr, ETH_RX_SKB_SIZE,
71d28725 398 DMA_FROM_DEVICE);
f98e36f1 399 mp->rx_desc_count--;
1da177e4 400 received_packets++;
b1dd9ca1 401
468d09f8
DF		 402 /*
403 * Update statistics.
404 * Note byte count includes 4 byte CRC count
405 */
1da177e4
LT		 406 stats->rx_packets++;
407 stats->rx_bytes += pkt_info.byte_cnt;
408 skb = pkt_info.return_info;
409 /*
410 * In case received a packet without first / last bits on OR
411 * the error summary bit is on, the packets needs to be dropeed.
412 */
413 if (((pkt_info.cmd_sts
414 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
415 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
416 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
417 stats->rx_dropped++;
418 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
419 ETH_RX_LAST_DESC)) !=
420 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
421 if (net_ratelimit())
422 printk(KERN_ERR
423 "%s: Received packet spread "
424 "on multiple descriptors\n",
425 dev->name);
426 }
427 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
428 stats->rx_errors++;
429
430 dev_kfree_skb_irq(skb);
431 } else {
432 /*
433 * The -4 is for the CRC in the trailer of the
434 * received packet
435 */
436 skb_put(skb, pkt_info.byte_cnt - 4);
437 skb->dev = dev;
438
439 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
440 skb->ip_summed = CHECKSUM_UNNECESSARY;
441 skb->csum = htons(
442 (pkt_info.cmd_sts & 0x0007fff8) >> 3);
443 }
444 skb->protocol = eth_type_trans(skb, dev);
445#ifdef MV643XX_NAPI
446 netif_receive_skb(skb);
447#else
448 netif_rx(skb);
449#endif
450 }
12ad74f8 451 dev->last_rx = jiffies;
1da177e4 452 }
f78fb474 453 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
1da177e4
LT		 454
455 return received_packets;
456}
457
d0412d96
JC		 458/* Set the mv643xx port configuration register for the speed/duplex mode. */
459static void mv643xx_eth_update_pscr(struct net_device *dev,
460 struct ethtool_cmd *ecmd)
461{
462 struct mv643xx_private *mp = netdev_priv(dev);
463 int port_num = mp->port_num;
464 u32 o_pscr, n_pscr;
12a87c64 465 unsigned int queues;
d0412d96
JC		 466
467 o_pscr = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
468 n_pscr = o_pscr;
469
470 /* clear speed, duplex and rx buffer size fields */
471 n_pscr &= ~(MV643XX_ETH_SET_MII_SPEED_TO_100 |
472 MV643XX_ETH_SET_GMII_SPEED_TO_1000 |
473 MV643XX_ETH_SET_FULL_DUPLEX_MODE |
474 MV643XX_ETH_MAX_RX_PACKET_MASK);
475
476 if (ecmd->duplex == DUPLEX_FULL)
477 n_pscr |= MV643XX_ETH_SET_FULL_DUPLEX_MODE;
478
479 if (ecmd->speed == SPEED_1000)
480 n_pscr |= MV643XX_ETH_SET_GMII_SPEED_TO_1000 |
481 MV643XX_ETH_MAX_RX_PACKET_9700BYTE;
482 else {
483 if (ecmd->speed == SPEED_100)
484 n_pscr |= MV643XX_ETH_SET_MII_SPEED_TO_100;
485 n_pscr |= MV643XX_ETH_MAX_RX_PACKET_1522BYTE;
486 }
487
488 if (n_pscr != o_pscr) {
489 if ((o_pscr & MV643XX_ETH_SERIAL_PORT_ENABLE) == 0)
490 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
491 n_pscr);
492 else {
12a87c64 493 queues = mv643xx_eth_port_disable_tx(port_num);
d0412d96
JC		 494
495 o_pscr &= ~MV643XX_ETH_SERIAL_PORT_ENABLE;
496 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
497 o_pscr);
498 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
499 n_pscr);
500 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
501 n_pscr);
12a87c64
DF		 502 if (queues)
503 mv643xx_eth_port_enable_tx(port_num, queues);
d0412d96
JC		 504 }
505 }
506}
507
1da177e4
LT		 508/*
509 * mv643xx_eth_int_handler
510 *
511 * Main interrupt handler for the gigbit ethernet ports
512 *
513 * Input : irq - irq number (not used)
514 * dev_id - a pointer to the required interface's data structure
515 * regs - not used
516 * Output : N/A
517 */
518
7d12e780 519static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id)
1da177e4
LT		 520{
521 struct net_device *dev = (struct net_device *)dev_id;
522 struct mv643xx_private *mp = netdev_priv(dev);
523 u32 eth_int_cause, eth_int_cause_ext = 0;
524 unsigned int port_num = mp->port_num;
525
526 /* Read interrupt cause registers */
527 eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) &
7303fde8 528 ETH_INT_UNMASK_ALL;
468d09f8 529 if (eth_int_cause & ETH_INT_CAUSE_EXT) {
1da177e4
LT		 530 eth_int_cause_ext = mv_read(
531 MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
7303fde8 532 ETH_INT_UNMASK_ALL_EXT;
468d09f8
DF		 533 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num),
534 ~eth_int_cause_ext);
1da177e4 535 }
7303fde8 536
1da177e4 537 /* PHY status changed */
468d09f8 538 if (eth_int_cause_ext & ETH_INT_CAUSE_PHY) {
d0412d96
JC		 539 struct ethtool_cmd cmd;
540
c28a4f89 541 if (mii_link_ok(&mp->mii)) {
d0412d96
JC		 542 mii_ethtool_gset(&mp->mii, &cmd);
543 mv643xx_eth_update_pscr(dev, &cmd);
ff561eef
DF		 544 mv643xx_eth_port_enable_tx(port_num,
545 ETH_TX_QUEUES_ENABLED);
c28a4f89
JC		 546 if (!netif_carrier_ok(dev)) {
547 netif_carrier_on(dev);
ff561eef
DF		 548 if (mp->tx_ring_size - mp->tx_desc_count >=
549 MAX_DESCS_PER_SKB)
d0412d96 550 netif_wake_queue(dev);
c28a4f89
JC		 551 }
552 } else if (netif_carrier_ok(dev)) {
1da177e4 553 netif_stop_queue(dev);
c28a4f89 554 netif_carrier_off(dev);
1da177e4
LT		 555 }
556 }
557
468d09f8
DF		 558#ifdef MV643XX_NAPI
559 if (eth_int_cause & ETH_INT_CAUSE_RX) {
560 /* schedule the NAPI poll routine to maintain port */
561 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
562 ETH_INT_MASK_ALL);
563 /* wait for previous write to complete */
564 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
565
566 netif_rx_schedule(dev);
567 }
568#else
569 if (eth_int_cause & ETH_INT_CAUSE_RX)
570 mv643xx_eth_receive_queue(dev, INT_MAX);
5c537408 571#endif
468d09f8
DF		 572 if (eth_int_cause_ext & ETH_INT_CAUSE_TX)
573 mv643xx_eth_free_completed_tx_descs(dev);
468d09f8 574
1da177e4
LT		 575 /*
576 * If no real interrupt occured, exit.
577 * This can happen when using gigE interrupt coalescing mechanism.
578 */
579 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
580 return IRQ_NONE;
581
582 return IRQ_HANDLED;
583}
584
585#ifdef MV643XX_COAL
586
587/*
588 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
589 *
590 * DESCRIPTION:
591 * This routine sets the RX coalescing interrupt mechanism parameter.
592 * This parameter is a timeout counter, that counts in 64 t_clk
593 * chunks ; that when timeout event occurs a maskable interrupt
594 * occurs.
595 * The parameter is calculated using the tClk of the MV-643xx chip
596 * , and the required delay of the interrupt in usec.
597 *
598 * INPUT:
599 * unsigned int eth_port_num Ethernet port number
600 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
601 * unsigned int delay Delay in usec
602 *
603 * OUTPUT:
604 * Interrupt coalescing mechanism value is set in MV-643xx chip.
605 *
606 * RETURN:
607 * The interrupt coalescing value set in the gigE port.
608 *
609 */
610static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
611 unsigned int t_clk, unsigned int delay)
612{
613 unsigned int coal = ((t_clk / 1000000) * delay) / 64;
614
615 /* Set RX Coalescing mechanism */
616 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num),
617 ((coal & 0x3fff) << 8) |
618 (mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num))
619 & 0xffc000ff));
620
621 return coal;
622}
623#endif
624
625/*
626 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
627 *
628 * DESCRIPTION:
629 * This routine sets the TX coalescing interrupt mechanism parameter.
630 * This parameter is a timeout counter, that counts in 64 t_clk
631 * chunks ; that when timeout event occurs a maskable interrupt
632 * occurs.
633 * The parameter is calculated using the t_cLK frequency of the
634 * MV-643xx chip and the required delay in the interrupt in uSec
635 *
636 * INPUT:
637 * unsigned int eth_port_num Ethernet port number
638 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
639 * unsigned int delay Delay in uSeconds
640 *
641 * OUTPUT:
642 * Interrupt coalescing mechanism value is set in MV-643xx chip.
643 *
644 * RETURN:
645 * The interrupt coalescing value set in the gigE port.
646 *
647 */
648static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num,
649 unsigned int t_clk, unsigned int delay)
650{
651 unsigned int coal;
652 coal = ((t_clk / 1000000) * delay) / 64;
653 /* Set TX Coalescing mechanism */
654 mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num),
655 coal << 4);
656 return coal;
657}
658
1da177e4
LT		 659/*
660 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
661 *
662 * DESCRIPTION:
663 * This function prepares a Rx chained list of descriptors and packet
664 * buffers in a form of a ring. The routine must be called after port
665 * initialization routine and before port start routine.
666 * The Ethernet SDMA engine uses CPU bus addresses to access the various
667 * devices in the system (i.e. DRAM). This function uses the ethernet
668 * struct 'virtual to physical' routine (set by the user) to set the ring
669 * with physical addresses.
670 *
671 * INPUT:
672 * struct mv643xx_private *mp Ethernet Port Control srtuct.
673 *
674 * OUTPUT:
675 * The routine updates the Ethernet port control struct with information
676 * regarding the Rx descriptors and buffers.
677 *
678 * RETURN:
679 * None.
680 */
681static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
682{
683 volatile struct eth_rx_desc *p_rx_desc;
684 int rx_desc_num = mp->rx_ring_size;
685 int i;
686
687 /* initialize the next_desc_ptr links in the Rx descriptors ring */
688 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
689 for (i = 0; i < rx_desc_num; i++) {
690 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
691 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
692 }
693
694 /* Save Rx desc pointer to driver struct. */
695 mp->rx_curr_desc_q = 0;
696 mp->rx_used_desc_q = 0;
697
698 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
1da177e4
LT		 699}
700
701/*
702 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
703 *
704 * DESCRIPTION:
705 * This function prepares a Tx chained list of descriptors and packet
706 * buffers in a form of a ring. The routine must be called after port
707 * initialization routine and before port start routine.
708 * The Ethernet SDMA engine uses CPU bus addresses to access the various
709 * devices in the system (i.e. DRAM). This function uses the ethernet
710 * struct 'virtual to physical' routine (set by the user) to set the ring
711 * with physical addresses.
712 *
713 * INPUT:
714 * struct mv643xx_private *mp Ethernet Port Control srtuct.
715 *
716 * OUTPUT:
717 * The routine updates the Ethernet port control struct with information
718 * regarding the Tx descriptors and buffers.
719 *
720 * RETURN:
721 * None.
722 */
723static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
724{
725 int tx_desc_num = mp->tx_ring_size;
726 struct eth_tx_desc *p_tx_desc;
727 int i;
728
729 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
730 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
731 for (i = 0; i < tx_desc_num; i++) {
732 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
733 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
734 }
735
736 mp->tx_curr_desc_q = 0;
737 mp->tx_used_desc_q = 0;
1da177e4
LT		 738
739 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
1da177e4
LT		 740}
741
d0412d96
JC		 742static int mv643xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
743{
744 struct mv643xx_private *mp = netdev_priv(dev);
745 int err;
746
747 spin_lock_irq(&mp->lock);
748 err = mii_ethtool_sset(&mp->mii, cmd);
749 spin_unlock_irq(&mp->lock);
750
751 return err;
752}
753
754static int mv643xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
755{
756 struct mv643xx_private *mp = netdev_priv(dev);
757 int err;
758
759 spin_lock_irq(&mp->lock);
760 err = mii_ethtool_gset(&mp->mii, cmd);
761 spin_unlock_irq(&mp->lock);
762
763 /* The PHY may support 1000baseT_Half, but the mv643xx does not */
764 cmd->supported &= ~SUPPORTED_1000baseT_Half;
765 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
766
767 return err;
768}
769
ab4384a6
DF		 770/*
771 * mv643xx_eth_open
772 *
773 * This function is called when openning the network device. The function
774 * should initialize all the hardware, initialize cyclic Rx/Tx
775 * descriptors chain and buffers and allocate an IRQ to the network
776 * device.
777 *
778 * Input : a pointer to the network device structure
779 *
780 * Output : zero of success , nonzero if fails.
781 */
782
783static int mv643xx_eth_open(struct net_device *dev)
1da177e4
LT		 784{
785 struct mv643xx_private *mp = netdev_priv(dev);
786 unsigned int port_num = mp->port_num;
787 unsigned int size;
ab4384a6
DF		 788 int err;
789
85cf572c
DF		 790 /* Clear any pending ethernet port interrupts */
791 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
792 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
793 /* wait for previous write to complete */
794 mv_read (MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num));
795
ab4384a6 796 err = request_irq(dev->irq, mv643xx_eth_int_handler,
1fb9df5d 797 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
ab4384a6
DF		 798 if (err) {
799 printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n",
800 port_num);
801 return -EAGAIN;
802 }
1da177e4 803
1da177e4
LT		 804 eth_port_init(mp);
805
1da177e4 806 memset(&mp->timeout, 0, sizeof(struct timer_list));
f78fb474 807 mp->timeout.function = mv643xx_eth_rx_refill_descs_timer_wrapper;
1da177e4
LT		 808 mp->timeout.data = (unsigned long)dev;
809
1da177e4
LT		 810 /* Allocate RX and TX skb rings */
811 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
812 GFP_KERNEL);
813 if (!mp->rx_skb) {
814 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
ab4384a6
DF		 815 err = -ENOMEM;
816 goto out_free_irq;
1da177e4
LT		 817 }
818 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
819 GFP_KERNEL);
820 if (!mp->tx_skb) {
821 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
ab4384a6
DF		 822 err = -ENOMEM;
823 goto out_free_rx_skb;
1da177e4
LT		 824 }
825
826 /* Allocate TX ring */
f98e36f1 827 mp->tx_desc_count = 0;
1da177e4
LT		 828 size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
829 mp->tx_desc_area_size = size;
830
831 if (mp->tx_sram_size) {
832 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
833 mp->tx_sram_size);
834 mp->tx_desc_dma = mp->tx_sram_addr;
835 } else
836 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
837 &mp->tx_desc_dma,
838 GFP_KERNEL);
839
840 if (!mp->p_tx_desc_area) {
841 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
842 dev->name, size);
ab4384a6
DF		 843 err = -ENOMEM;
844 goto out_free_tx_skb;
1da177e4
LT		 845 }
846 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
847 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
848
849 ether_init_tx_desc_ring(mp);
850
851 /* Allocate RX ring */
f98e36f1 852 mp->rx_desc_count = 0;
1da177e4
LT		 853 size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
854 mp->rx_desc_area_size = size;
855
856 if (mp->rx_sram_size) {
857 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
858 mp->rx_sram_size);
859 mp->rx_desc_dma = mp->rx_sram_addr;
860 } else
861 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
862 &mp->rx_desc_dma,
863 GFP_KERNEL);
864
865 if (!mp->p_rx_desc_area) {
866 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
867 dev->name, size);
868 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
869 dev->name);
870 if (mp->rx_sram_size)
dd09b1de 871 iounmap(mp->p_tx_desc_area);
1da177e4
LT		 872 else
873 dma_free_coherent(NULL, mp->tx_desc_area_size,
874 mp->p_tx_desc_area, mp->tx_desc_dma);
ab4384a6
DF		 875 err = -ENOMEM;
876 goto out_free_tx_skb;
1da177e4
LT		 877 }
878 memset((void *)mp->p_rx_desc_area, 0, size);
879
880 ether_init_rx_desc_ring(mp);
881
f78fb474 882 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
1da177e4 883
ed9b5d45 884 eth_port_start(dev);
1da177e4
LT		 885
886 /* Interrupt Coalescing */
887
888#ifdef MV643XX_COAL
889 mp->rx_int_coal =
890 eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL);
891#endif
892
893 mp->tx_int_coal =
894 eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL);
895
8f518703
DF		 896 /* Unmask phy and link status changes interrupts */
897 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
7303fde8 898 ETH_INT_UNMASK_ALL_EXT);
1da177e4 899
8f518703 900 /* Unmask RX buffer and TX end interrupt */
7303fde8 901 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
d0412d96 902
1da177e4 903 return 0;
ab4384a6
DF		 904
905out_free_tx_skb:
906 kfree(mp->tx_skb);
907out_free_rx_skb:
908 kfree(mp->rx_skb);
909out_free_irq:
910 free_irq(dev->irq, dev);
911
912 return err;
1da177e4
LT		 913}
914
915static void mv643xx_eth_free_tx_rings(struct net_device *dev)
916{
917 struct mv643xx_private *mp = netdev_priv(dev);
1da177e4
LT		 918
919 /* Stop Tx Queues */
ff561eef 920 mv643xx_eth_port_disable_tx(mp->port_num);
1da177e4 921
ff561eef
DF		 922 /* Free outstanding skb's on TX ring */
923 mv643xx_eth_free_all_tx_descs(dev);
924
925 BUG_ON(mp->tx_used_desc_q != mp->tx_curr_desc_q);
1da177e4
LT		 926
927 /* Free TX ring */
928 if (mp->tx_sram_size)
929 iounmap(mp->p_tx_desc_area);
930 else
931 dma_free_coherent(NULL, mp->tx_desc_area_size,
932 mp->p_tx_desc_area, mp->tx_desc_dma);
933}
934
935static void mv643xx_eth_free_rx_rings(struct net_device *dev)
936{
937 struct mv643xx_private *mp = netdev_priv(dev);
938 unsigned int port_num = mp->port_num;
939 int curr;
940
941 /* Stop RX Queues */
9f8dd319 942 mv643xx_eth_port_disable_rx(port_num);
1da177e4
LT		 943
944 /* Free preallocated skb's on RX rings */
f98e36f1 945 for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) {
1da177e4
LT		 946 if (mp->rx_skb[curr]) {
947 dev_kfree_skb(mp->rx_skb[curr]);
f98e36f1 948 mp->rx_desc_count--;
1da177e4
LT		 949 }
950 }
951
f98e36f1 952 if (mp->rx_desc_count)
1da177e4
LT		 953 printk(KERN_ERR
954 "%s: Error in freeing Rx Ring. %d skb's still"
955 " stuck in RX Ring - ignoring them\n", dev->name,
f98e36f1 956 mp->rx_desc_count);
1da177e4
LT		 957 /* Free RX ring */
958 if (mp->rx_sram_size)
959 iounmap(mp->p_rx_desc_area);
960 else
961 dma_free_coherent(NULL, mp->rx_desc_area_size,
962 mp->p_rx_desc_area, mp->rx_desc_dma);
963}
964
965/*
966 * mv643xx_eth_stop
967 *
968 * This function is used when closing the network device.
969 * It updates the hardware,
970 * release all memory that holds buffers and descriptors and release the IRQ.
971 * Input : a pointer to the device structure
972 * Output : zero if success , nonzero if fails
973 */
974
ab4384a6 975static int mv643xx_eth_stop(struct net_device *dev)
1da177e4
LT		 976{
977 struct mv643xx_private *mp = netdev_priv(dev);
978 unsigned int port_num = mp->port_num;
979
c2e5b352 980 /* Mask all interrupts on ethernet port */
7303fde8 981 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
c2e5b352 982 /* wait for previous write to complete */
8f518703
DF		 983 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
984
985#ifdef MV643XX_NAPI
986 netif_poll_disable(dev);
987#endif
1da177e4
LT		 988 netif_carrier_off(dev);
989 netif_stop_queue(dev);
990
1da177e4
LT		 991 eth_port_reset(mp->port_num);
992
8f518703
DF		 993 mv643xx_eth_free_tx_rings(dev);
994 mv643xx_eth_free_rx_rings(dev);
1da177e4 995
8f518703
DF		 996#ifdef MV643XX_NAPI
997 netif_poll_enable(dev);
998#endif
1da177e4 999
1da177e4 1000 free_irq(dev->irq, dev);
1da177e4
LT		 1001
1002 return 0;
1003}
1004
1005#ifdef MV643XX_NAPI
1da177e4
LT		 1006/*
1007 * mv643xx_poll
1008 *
1009 * This function is used in case of NAPI
1010 */
1011static int mv643xx_poll(struct net_device *dev, int *budget)
1012{
1013 struct mv643xx_private *mp = netdev_priv(dev);
1014 int done = 1, orig_budget, work_done;
1015 unsigned int port_num = mp->port_num;
1da177e4
LT		 1016
1017#ifdef MV643XX_TX_FAST_REFILL
1018 if (++mp->tx_clean_threshold > 5) {
ff561eef 1019 mv643xx_eth_free_completed_tx_descs(dev);
1da177e4 1020 mp->tx_clean_threshold = 0;
1da177e4
LT		 1021 }
1022#endif
1023
1024 if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
1025 != (u32) mp->rx_used_desc_q) {
1026 orig_budget = *budget;
1027 if (orig_budget > dev->quota)
1028 orig_budget = dev->quota;
1029 work_done = mv643xx_eth_receive_queue(dev, orig_budget);
1da177e4
LT		 1030 *budget -= work_done;
1031 dev->quota -= work_done;
1032 if (work_done >= orig_budget)
1033 done = 0;
1034 }
1035
1036 if (done) {
8f518703 1037 netif_rx_complete(dev);
1da177e4
LT		 1038 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
1039 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1040 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
7303fde8 1041 ETH_INT_UNMASK_ALL);
1da177e4
LT		 1042 }
1043
1044 return done ? 0 : 1;
1045}
1046#endif
1047
c8aaea25
DF		 1048/**
1049 * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments
1050 *
1051 * Hardware can't handle unaligned fragments smaller than 9 bytes.
f7ea3337
PJ		 1052 * This helper function detects that case.
1053 */
1054
1055static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1056{
b4de9051
DF		 1057 unsigned int frag;
1058 skb_frag_t *fragp;
f7ea3337 1059
b4de9051
DF		 1060 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1061 fragp = &skb_shinfo(skb)->frags[frag];
1062 if (fragp->size <= 8 && fragp->page_offset & 0x7)
1063 return 1;
1064 }
1065 return 0;
f7ea3337
PJ		 1066}
1067
c8aaea25
DF		 1068/**
1069 * eth_alloc_tx_desc_index - return the index of the next available tx desc
1070 */
1071static int eth_alloc_tx_desc_index(struct mv643xx_private *mp)
1072{
1073 int tx_desc_curr;
1074
c8aaea25 1075 BUG_ON(mp->tx_desc_count >= mp->tx_ring_size);
c8aaea25 1076
ff561eef 1077 tx_desc_curr = mp->tx_curr_desc_q;
c8aaea25
DF		 1078 mp->tx_curr_desc_q = (tx_desc_curr + 1) % mp->tx_ring_size;
1079
1080 BUG_ON(mp->tx_curr_desc_q == mp->tx_used_desc_q);
1081
1082 return tx_desc_curr;
1083}
1084
1085/**
1086 * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments.
1da177e4 1087 *
c8aaea25
DF		 1088 * Ensure the data for each fragment to be transmitted is mapped properly,
1089 * then fill in descriptors in the tx hw queue.
1da177e4 1090 */
c8aaea25
DF		 1091static void eth_tx_fill_frag_descs(struct mv643xx_private *mp,
1092 struct sk_buff *skb)
1da177e4 1093{
c8aaea25
DF		 1094 int frag;
1095 int tx_index;
1096 struct eth_tx_desc *desc;
1da177e4 1097
c8aaea25
DF		 1098 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1099 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1100
1101 tx_index = eth_alloc_tx_desc_index(mp);
1102 desc = &mp->p_tx_desc_area[tx_index];
1103
1104 desc->cmd_sts = ETH_BUFFER_OWNED_BY_DMA;
1105 /* Last Frag enables interrupt and frees the skb */
1106 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
1107 desc->cmd_sts |= ETH_ZERO_PADDING |
1108 ETH_TX_LAST_DESC |
1109 ETH_TX_ENABLE_INTERRUPT;
1110 mp->tx_skb[tx_index] = skb;
1111 } else
05980775 1112 mp->tx_skb[tx_index] = NULL;
c8aaea25
DF		 1113
1114 desc = &mp->p_tx_desc_area[tx_index];
1115 desc->l4i_chk = 0;
1116 desc->byte_cnt = this_frag->size;
1117 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
1118 this_frag->page_offset,
1119 this_frag->size,
1120 DMA_TO_DEVICE);
1da177e4 1121 }
c8aaea25 1122}
1da177e4 1123
c8aaea25
DF		 1124/**
1125 * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw
1126 *
1127 * Ensure the data for an skb to be transmitted is mapped properly,
1128 * then fill in descriptors in the tx hw queue and start the hardware.
1129 */
ff561eef
DF		 1130static void eth_tx_submit_descs_for_skb(struct mv643xx_private *mp,
1131 struct sk_buff *skb)
c8aaea25
DF		 1132{
1133 int tx_index;
1134 struct eth_tx_desc *desc;
1135 u32 cmd_sts;
1136 int length;
ff561eef 1137 int nr_frags = skb_shinfo(skb)->nr_frags;
1da177e4 1138
c8aaea25 1139 cmd_sts = ETH_TX_FIRST_DESC | ETH_GEN_CRC | ETH_BUFFER_OWNED_BY_DMA;
1da177e4 1140
c8aaea25
DF		 1141 tx_index = eth_alloc_tx_desc_index(mp);
1142 desc = &mp->p_tx_desc_area[tx_index];
1143
ff561eef 1144 if (nr_frags) {
c8aaea25
DF		 1145 eth_tx_fill_frag_descs(mp, skb);
1146
1147 length = skb_headlen(skb);
05980775 1148 mp->tx_skb[tx_index] = NULL;
c8aaea25
DF		 1149 } else {
1150 cmd_sts |= ETH_ZERO_PADDING |
1151 ETH_TX_LAST_DESC |
1152 ETH_TX_ENABLE_INTERRUPT;
1153 length = skb->len;
1154 mp->tx_skb[tx_index] = skb;
f7ea3337
PJ		 1155 }
1156
c8aaea25
DF		 1157 desc->byte_cnt = length;
1158 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
1da177e4 1159
84fa7933 1160 if (skb->ip_summed == CHECKSUM_PARTIAL) {
c8aaea25
DF		 1161 BUG_ON(skb->protocol != ETH_P_IP);
1162
1163 cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM |
1164 ETH_GEN_IP_V_4_CHECKSUM |
1165 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
1166
1167 switch (skb->nh.iph->protocol) {
1168 case IPPROTO_UDP:
1169 cmd_sts |= ETH_UDP_FRAME;
1170 desc->l4i_chk = skb->h.uh->check;
1171 break;
1172 case IPPROTO_TCP:
1173 desc->l4i_chk = skb->h.th->check;
1174 break;
1175 default:
1176 BUG();
1da177e4 1177 }
1da177e4 1178 } else {
c8aaea25
DF		 1179 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1180 cmd_sts |= 5 << ETH_TX_IHL_SHIFT;
1181 desc->l4i_chk = 0;
1182 }
1da177e4 1183
c8aaea25
DF		 1184 /* ensure all other descriptors are written before first cmd_sts */
1185 wmb();
1186 desc->cmd_sts = cmd_sts;
1da177e4 1187
c8aaea25
DF		 1188 /* ensure all descriptors are written before poking hardware */
1189 wmb();
ff561eef 1190 mv643xx_eth_port_enable_tx(mp->port_num, ETH_TX_QUEUES_ENABLED);
1da177e4 1191
ff561eef 1192 mp->tx_desc_count += nr_frags + 1;
c8aaea25 1193}
1da177e4 1194
c8aaea25
DF		 1195/**
1196 * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission
1197 *
1198 */
1199static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1200{
1201 struct mv643xx_private *mp = netdev_priv(dev);
1202 struct net_device_stats *stats = &mp->stats;
1203 unsigned long flags;
1da177e4 1204
c8aaea25
DF		 1205 BUG_ON(netif_queue_stopped(dev));
1206 BUG_ON(skb == NULL);
94843566
DF		 1207
1208 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) {
1209 printk(KERN_ERR "%s: transmit with queue full\n", dev->name);
1210 netif_stop_queue(dev);
1211 return 1;
1212 }
1da177e4 1213
c8aaea25 1214 if (has_tiny_unaligned_frags(skb)) {
364c6bad 1215 if (__skb_linearize(skb)) {
c8aaea25
DF		 1216 stats->tx_dropped++;
1217 printk(KERN_DEBUG "%s: failed to linearize tiny "
1218 "unaligned fragment\n", dev->name);
1219 return 1;
1da177e4
LT		 1220 }
1221 }
f7ea3337 1222
c8aaea25 1223 spin_lock_irqsave(&mp->lock, flags);
1da177e4 1224
ff561eef
DF		 1225 eth_tx_submit_descs_for_skb(mp, skb);
1226 stats->tx_bytes = skb->len;
1da177e4
LT		 1227 stats->tx_packets++;
1228 dev->trans_start = jiffies;
1229
c8aaea25
DF		 1230 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB)
1231 netif_stop_queue(dev);
1232
1da177e4
LT		 1233 spin_unlock_irqrestore(&mp->lock, flags);
1234
1235 return 0; /* success */
1236}
1237
1238/*
1239 * mv643xx_eth_get_stats
1240 *
1241 * Returns a pointer to the interface statistics.
1242 *
1243 * Input : dev - a pointer to the required interface
1244 *
1245 * Output : a pointer to the interface's statistics
1246 */
1247
1248static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1249{
1250 struct mv643xx_private *mp = netdev_priv(dev);
1251
1252 return &mp->stats;
1253}
1254
63c9e549 1255#ifdef CONFIG_NET_POLL_CONTROLLER
63c9e549
DF		 1256static void mv643xx_netpoll(struct net_device *netdev)
1257{
1258 struct mv643xx_private *mp = netdev_priv(netdev);
c2e5b352
DF		 1259 int port_num = mp->port_num;
1260
7303fde8 1261 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
c2e5b352
DF		 1262 /* wait for previous write to complete */
1263 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
63c9e549 1264
9da3b1ad 1265 mv643xx_eth_int_handler(netdev->irq, netdev);
c2e5b352 1266
7303fde8 1267 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
63c9e549
DF		 1268}
1269#endif
1270
d0412d96
JC		 1271static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address,
1272 int speed, int duplex,
1273 struct ethtool_cmd *cmd)
1274{
1275 struct mv643xx_private *mp = netdev_priv(dev);
1276
1277 memset(cmd, 0, sizeof(*cmd));
1278
1279 cmd->port = PORT_MII;
1280 cmd->transceiver = XCVR_INTERNAL;
1281 cmd->phy_address = phy_address;
1282
1283 if (speed == 0) {
1284 cmd->autoneg = AUTONEG_ENABLE;
1285 /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */
1286 cmd->speed = SPEED_100;
1287 cmd->advertising = ADVERTISED_10baseT_Half |
1288 ADVERTISED_10baseT_Full |
1289 ADVERTISED_100baseT_Half |
1290 ADVERTISED_100baseT_Full;
1291 if (mp->mii.supports_gmii)
1292 cmd->advertising |= ADVERTISED_1000baseT_Full;
1293 } else {
1294 cmd->autoneg = AUTONEG_DISABLE;
1295 cmd->speed = speed;
1296 cmd->duplex = duplex;
1297 }
1298}
1299
1da177e4
LT		 1300/*/
1301 * mv643xx_eth_probe
1302 *
1303 * First function called after registering the network device.
1304 * It's purpose is to initialize the device as an ethernet device,
1305 * fill the ethernet device structure with pointers * to functions,
1306 * and set the MAC address of the interface
1307 *
1308 * Input : struct device *
1309 * Output : -ENOMEM if failed , 0 if success
1310 */
3ae5eaec 1311static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 1312{
1da177e4 1313 struct mv643xx_eth_platform_data *pd;
84dd619e 1314 int port_num;
1da177e4
LT		 1315 struct mv643xx_private *mp;
1316 struct net_device *dev;
1317 u8 *p;
1318 struct resource *res;
1319 int err;
d0412d96 1320 struct ethtool_cmd cmd;
01999873
DF		 1321 int duplex = DUPLEX_HALF;
1322 int speed = 0; /* default to auto-negotiation */
1da177e4 1323
84dd619e
DF		 1324 pd = pdev->dev.platform_data;
1325 if (pd == NULL) {
1326 printk(KERN_ERR "No mv643xx_eth_platform_data\n");
1327 return -ENODEV;
1328 }
1329
1da177e4
LT		 1330 dev = alloc_etherdev(sizeof(struct mv643xx_private));
1331 if (!dev)
1332 return -ENOMEM;
1333
3ae5eaec 1334 platform_set_drvdata(pdev, dev);
1da177e4
LT		 1335
1336 mp = netdev_priv(dev);
1337
1338 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1339 BUG_ON(!res);
1340 dev->irq = res->start;
1341
1da177e4
LT		 1342 dev->open = mv643xx_eth_open;
1343 dev->stop = mv643xx_eth_stop;
1344 dev->hard_start_xmit = mv643xx_eth_start_xmit;
1345 dev->get_stats = mv643xx_eth_get_stats;
1346 dev->set_mac_address = mv643xx_eth_set_mac_address;
1347 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
1348
1349 /* No need to Tx Timeout */
1350 dev->tx_timeout = mv643xx_eth_tx_timeout;
1351#ifdef MV643XX_NAPI
1352 dev->poll = mv643xx_poll;
1353 dev->weight = 64;
1354#endif
1355
63c9e549
DF		 1356#ifdef CONFIG_NET_POLL_CONTROLLER
1357 dev->poll_controller = mv643xx_netpoll;
1358#endif
1359
1da177e4
LT		 1360 dev->watchdog_timeo = 2 * HZ;
1361 dev->tx_queue_len = mp->tx_ring_size;
1362 dev->base_addr = 0;
1363 dev->change_mtu = mv643xx_eth_change_mtu;
d0412d96 1364 dev->do_ioctl = mv643xx_eth_do_ioctl;
1da177e4
LT		 1365 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
1366
1367#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1368#ifdef MAX_SKB_FRAGS
1369 /*
1370 * Zero copy can only work if we use Discovery II memory. Else, we will
1371 * have to map the buffers to ISA memory which is only 16 MB
1372 */
63890576 1373 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4
LT		 1374#endif
1375#endif
1376
1377 /* Configure the timeout task */
91c7c568 1378 INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task);
1da177e4
LT		 1379
1380 spin_lock_init(&mp->lock);
1381
fadac406 1382 port_num = mp->port_num = pd->port_number;
84dd619e 1383
1da177e4
LT		 1384 /* set default config values */
1385 eth_port_uc_addr_get(dev, dev->dev_addr);
1da177e4
LT		 1386 mp->rx_ring_size = MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
1387 mp->tx_ring_size = MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
1388
84dd619e
DF		 1389 if (is_valid_ether_addr(pd->mac_addr))
1390 memcpy(dev->dev_addr, pd->mac_addr, 6);
1da177e4 1391
84dd619e
DF		 1392 if (pd->phy_addr || pd->force_phy_addr)
1393 ethernet_phy_set(port_num, pd->phy_addr);
1da177e4 1394
84dd619e
DF		 1395 if (pd->rx_queue_size)
1396 mp->rx_ring_size = pd->rx_queue_size;
1da177e4 1397
84dd619e
DF		 1398 if (pd->tx_queue_size)
1399 mp->tx_ring_size = pd->tx_queue_size;
1da177e4 1400
84dd619e
DF		 1401 if (pd->tx_sram_size) {
1402 mp->tx_sram_size = pd->tx_sram_size;
1403 mp->tx_sram_addr = pd->tx_sram_addr;
1404 }
01999873 1405
84dd619e
DF		 1406 if (pd->rx_sram_size) {
1407 mp->rx_sram_size = pd->rx_sram_size;
1408 mp->rx_sram_addr = pd->rx_sram_addr;
1da177e4
LT		 1409 }
1410
84dd619e
DF		 1411 duplex = pd->duplex;
1412 speed = pd->speed;
1413
c28a4f89
JC		 1414 /* Hook up MII support for ethtool */
1415 mp->mii.dev = dev;
1416 mp->mii.mdio_read = mv643xx_mdio_read;
1417 mp->mii.mdio_write = mv643xx_mdio_write;
1418 mp->mii.phy_id = ethernet_phy_get(port_num);
1419 mp->mii.phy_id_mask = 0x3f;
1420 mp->mii.reg_num_mask = 0x1f;
1421
1da177e4
LT		 1422 err = ethernet_phy_detect(port_num);
1423 if (err) {
1424 pr_debug("MV643xx ethernet port %d: "
1425 "No PHY detected at addr %d\n",
1426 port_num, ethernet_phy_get(port_num));
d0412d96 1427 goto out;
1da177e4
LT		 1428 }
1429
01999873 1430 ethernet_phy_reset(port_num);
c28a4f89 1431 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
d0412d96
JC		 1432 mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd);
1433 mv643xx_eth_update_pscr(dev, &cmd);
1434 mv643xx_set_settings(dev, &cmd);
c28a4f89 1435
b0b8dab2
OH		 1436 SET_MODULE_OWNER(dev);
1437 SET_NETDEV_DEV(dev, &pdev->dev);
1da177e4
LT		 1438 err = register_netdev(dev);
1439 if (err)
1440 goto out;
1441
1442 p = dev->dev_addr;
1443 printk(KERN_NOTICE
1444 "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
1445 dev->name, port_num, p[0], p[1], p[2], p[3], p[4], p[5]);
1446
1447 if (dev->features & NETIF_F_SG)
1448 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
1449
1450 if (dev->features & NETIF_F_IP_CSUM)
1451 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
1452 dev->name);
1453
1454#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1455 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
1456#endif
1457
1458#ifdef MV643XX_COAL
1459 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
1460 dev->name);
1461#endif
1462
1463#ifdef MV643XX_NAPI
1464 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
1465#endif
1466
b1529871
ND		 1467 if (mp->tx_sram_size > 0)
1468 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
1469
1da177e4
LT		 1470 return 0;
1471
1472out:
1473 free_netdev(dev);
1474
1475 return err;
1476}
1477
3ae5eaec 1478static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 1479{
3ae5eaec 1480 struct net_device *dev = platform_get_drvdata(pdev);
1da177e4
LT		 1481
1482 unregister_netdev(dev);
1483 flush_scheduled_work();
1484
1485 free_netdev(dev);
3ae5eaec 1486 platform_set_drvdata(pdev, NULL);
1da177e4
LT		 1487 return 0;
1488}
1489
3ae5eaec 1490static int mv643xx_eth_shared_probe(struct platform_device *pdev)
1da177e4 1491{
1da177e4
LT		 1492 struct resource *res;
1493
1494 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
1495
1496 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1497 if (res == NULL)
1498 return -ENODEV;
1499
1500 mv643xx_eth_shared_base = ioremap(res->start,
1501 MV643XX_ETH_SHARED_REGS_SIZE);
1502 if (mv643xx_eth_shared_base == NULL)
1503 return -ENOMEM;
1504
1505 return 0;
1506
1507}
1508
3ae5eaec 1509static int mv643xx_eth_shared_remove(struct platform_device *pdev)
1da177e4
LT		 1510{
1511 iounmap(mv643xx_eth_shared_base);
1512 mv643xx_eth_shared_base = NULL;
1513
1514 return 0;
1515}
1516
d57ab6fd
DF		 1517static void mv643xx_eth_shutdown(struct platform_device *pdev)
1518{
1519 struct net_device *dev = platform_get_drvdata(pdev);
1520 struct mv643xx_private *mp = netdev_priv(dev);
1521 unsigned int port_num = mp->port_num;
1522
1523 /* Mask all interrupts on ethernet port */
1524 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0);
1525 mv_read (MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
1526
1527 eth_port_reset(port_num);
1528}
1529
3ae5eaec 1530static struct platform_driver mv643xx_eth_driver = {
1da177e4
LT		 1531 .probe = mv643xx_eth_probe,
1532 .remove = mv643xx_eth_remove,
d57ab6fd 1533 .shutdown = mv643xx_eth_shutdown,
3ae5eaec
RK		 1534 .driver = {
1535 .name = MV643XX_ETH_NAME,
1536 },
1da177e4
LT		 1537};
1538
3ae5eaec 1539static struct platform_driver mv643xx_eth_shared_driver = {
1da177e4
LT		 1540 .probe = mv643xx_eth_shared_probe,
1541 .remove = mv643xx_eth_shared_remove,
3ae5eaec
RK		 1542 .driver = {
1543 .name = MV643XX_ETH_SHARED_NAME,
1544 },
1da177e4
LT		 1545};
1546
1547/*
1548 * mv643xx_init_module
1549 *
1550 * Registers the network drivers into the Linux kernel
1551 *
1552 * Input : N/A
1553 *
1554 * Output : N/A
1555 */
1556static int __init mv643xx_init_module(void)
1557{
1558 int rc;
1559
3ae5eaec 1560 rc = platform_driver_register(&mv643xx_eth_shared_driver);
1da177e4 1561 if (!rc) {
3ae5eaec 1562 rc = platform_driver_register(&mv643xx_eth_driver);
1da177e4 1563 if (rc)
3ae5eaec 1564 platform_driver_unregister(&mv643xx_eth_shared_driver);
1da177e4
LT		 1565 }
1566 return rc;
1567}
1568
1569/*
1570 * mv643xx_cleanup_module
1571 *
1572 * Registers the network drivers into the Linux kernel
1573 *
1574 * Input : N/A
1575 *
1576 * Output : N/A
1577 */
1578static void __exit mv643xx_cleanup_module(void)
1579{
3ae5eaec
RK		 1580 platform_driver_unregister(&mv643xx_eth_driver);
1581 platform_driver_unregister(&mv643xx_eth_shared_driver);
1da177e4
LT		 1582}
1583
1584module_init(mv643xx_init_module);
1585module_exit(mv643xx_cleanup_module);
1586
1587MODULE_LICENSE("GPL");
1588MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
1589 " and Dale Farnsworth");
1590MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
1591
1592/*
1593 * The second part is the low level driver of the gigE ethernet ports.
1594 */
1595
1596/*
1597 * Marvell's Gigabit Ethernet controller low level driver
1598 *
1599 * DESCRIPTION:
1600 * This file introduce low level API to Marvell's Gigabit Ethernet
1601 * controller. This Gigabit Ethernet Controller driver API controls
1602 * 1) Operations (i.e. port init, start, reset etc').
1603 * 2) Data flow (i.e. port send, receive etc').
1604 * Each Gigabit Ethernet port is controlled via
1605 * struct mv643xx_private.
1606 * This struct includes user configuration information as well as
1607 * driver internal data needed for its operations.
1608 *
1609 * Supported Features:
1610 * - This low level driver is OS independent. Allocating memory for
1611 * the descriptor rings and buffers are not within the scope of
1612 * this driver.
1613 * - The user is free from Rx/Tx queue managing.
1614 * - This low level driver introduce functionality API that enable
1615 * the to operate Marvell's Gigabit Ethernet Controller in a
1616 * convenient way.
1617 * - Simple Gigabit Ethernet port operation API.
1618 * - Simple Gigabit Ethernet port data flow API.
1619 * - Data flow and operation API support per queue functionality.
1620 * - Support cached descriptors for better performance.
1621 * - Enable access to all four DRAM banks and internal SRAM memory
1622 * spaces.
1623 * - PHY access and control API.
1624 * - Port control register configuration API.
1625 * - Full control over Unicast and Multicast MAC configurations.
1626 *
1627 * Operation flow:
1628 *
1629 * Initialization phase
1630 * This phase complete the initialization of the the
1631 * mv643xx_private struct.
1632 * User information regarding port configuration has to be set
1633 * prior to calling the port initialization routine.
1634 *
1635 * In this phase any port Tx/Rx activity is halted, MIB counters
1636 * are cleared, PHY address is set according to user parameter and
1637 * access to DRAM and internal SRAM memory spaces.
1638 *
1639 * Driver ring initialization
1640 * Allocating memory for the descriptor rings and buffers is not
1641 * within the scope of this driver. Thus, the user is required to
1642 * allocate memory for the descriptors ring and buffers. Those
1643 * memory parameters are used by the Rx and Tx ring initialization
1644 * routines in order to curve the descriptor linked list in a form
1645 * of a ring.
1646 * Note: Pay special attention to alignment issues when using
1647 * cached descriptors/buffers. In this phase the driver store
1648 * information in the mv643xx_private struct regarding each queue
1649 * ring.
1650 *
1651 * Driver start
1652 * This phase prepares the Ethernet port for Rx and Tx activity.
1653 * It uses the information stored in the mv643xx_private struct to
1654 * initialize the various port registers.
1655 *
1656 * Data flow:
1657 * All packet references to/from the driver are done using
1658 * struct pkt_info.
1659 * This struct is a unified struct used with Rx and Tx operations.
1660 * This way the user is not required to be familiar with neither
1661 * Tx nor Rx descriptors structures.
1662 * The driver's descriptors rings are management by indexes.
1663 * Those indexes controls the ring resources and used to indicate
1664 * a SW resource error:
1665 * 'current'
1666 * This index points to the current available resource for use. For
1667 * example in Rx process this index will point to the descriptor
1668 * that will be passed to the user upon calling the receive
1669 * routine. In Tx process, this index will point to the descriptor
1670 * that will be assigned with the user packet info and transmitted.
1671 * 'used'
1672 * This index points to the descriptor that need to restore its
1673 * resources. For example in Rx process, using the Rx buffer return
1674 * API will attach the buffer returned in packet info to the
1675 * descriptor pointed by 'used'. In Tx process, using the Tx
1676 * descriptor return will merely return the user packet info with
1677 * the command status of the transmitted buffer pointed by the
1678 * 'used' index. Nevertheless, it is essential to use this routine
1679 * to update the 'used' index.
1680 * 'first'
1681 * This index supports Tx Scatter-Gather. It points to the first
1682 * descriptor of a packet assembled of multiple buffers. For
1683 * example when in middle of Such packet we have a Tx resource
1684 * error the 'curr' index get the value of 'first' to indicate
1685 * that the ring returned to its state before trying to transmit
1686 * this packet.
1687 *
1688 * Receive operation:
1689 * The eth_port_receive API set the packet information struct,
1690 * passed by the caller, with received information from the
1691 * 'current' SDMA descriptor.
1692 * It is the user responsibility to return this resource back
1693 * to the Rx descriptor ring to enable the reuse of this source.
1694 * Return Rx resource is done using the eth_rx_return_buff API.
1695 *
1da177e4
LT		 1696 * Prior to calling the initialization routine eth_port_init() the user
1697 * must set the following fields under mv643xx_private struct:
1698 * port_num User Ethernet port number.
1da177e4
LT		 1699 * port_config User port configuration value.
1700 * port_config_extend User port config extend value.
1701 * port_sdma_config User port SDMA config value.
1702 * port_serial_control User port serial control value.
1703 *
1704 * This driver data flow is done using the struct pkt_info which
1705 * is a unified struct for Rx and Tx operations:
1706 *
1707 * byte_cnt Tx/Rx descriptor buffer byte count.
1708 * l4i_chk CPU provided TCP Checksum. For Tx operation
1709 * only.
1710 * cmd_sts Tx/Rx descriptor command status.
1711 * buf_ptr Tx/Rx descriptor buffer pointer.
1712 * return_info Tx/Rx user resource return information.
1713 */
1714
1da177e4
LT		 1715/* PHY routines */
1716static int ethernet_phy_get(unsigned int eth_port_num);
1717static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
1718
1719/* Ethernet Port routines */
cf4086c7 1720static void eth_port_set_filter_table_entry(int table, unsigned char entry);
1da177e4
LT		 1721
1722/*
1723 * eth_port_init - Initialize the Ethernet port driver
1724 *
1725 * DESCRIPTION:
1726 * This function prepares the ethernet port to start its activity:
1727 * 1) Completes the ethernet port driver struct initialization toward port
1728 * start routine.
1729 * 2) Resets the device to a quiescent state in case of warm reboot.
1730 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1731 * 4) Clean MAC tables. The reset status of those tables is unknown.
1732 * 5) Set PHY address.
1733 * Note: Call this routine prior to eth_port_start routine and after
1734 * setting user values in the user fields of Ethernet port control
1735 * struct.
1736 *
1737 * INPUT:
1738 * struct mv643xx_private *mp Ethernet port control struct
1739 *
1740 * OUTPUT:
1741 * See description.
1742 *
1743 * RETURN:
1744 * None.
1745 */
1746static void eth_port_init(struct mv643xx_private *mp)
1747{
1da177e4 1748 mp->rx_resource_err = 0;
1da177e4
LT		 1749
1750 eth_port_reset(mp->port_num);
1751
1752 eth_port_init_mac_tables(mp->port_num);
1da177e4
LT		 1753}
1754
1755/*
1756 * eth_port_start - Start the Ethernet port activity.
1757 *
1758 * DESCRIPTION:
1759 * This routine prepares the Ethernet port for Rx and Tx activity:
1760 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1761 * has been initialized a descriptor's ring (using
1762 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
1763 * 2. Initialize and enable the Ethernet configuration port by writing to
1764 * the port's configuration and command registers.
1765 * 3. Initialize and enable the SDMA by writing to the SDMA's
1766 * configuration and command registers. After completing these steps,
1767 * the ethernet port SDMA can starts to perform Rx and Tx activities.
1768 *
1769 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1770 * to calling this function (use ether_init_tx_desc_ring for Tx queues
1771 * and ether_init_rx_desc_ring for Rx queues).
1772 *
1773 * INPUT:
ed9b5d45 1774 * dev - a pointer to the required interface
1da177e4
LT		 1775 *
1776 * OUTPUT:
1777 * Ethernet port is ready to receive and transmit.
1778 *
1779 * RETURN:
1780 * None.
1781 */
ed9b5d45 1782static void eth_port_start(struct net_device *dev)
1da177e4 1783{
ed9b5d45 1784 struct mv643xx_private *mp = netdev_priv(dev);
1da177e4
LT		 1785 unsigned int port_num = mp->port_num;
1786 int tx_curr_desc, rx_curr_desc;
d0412d96
JC		 1787 u32 pscr;
1788 struct ethtool_cmd ethtool_cmd;
1da177e4
LT		 1789
1790 /* Assignment of Tx CTRP of given queue */
1791 tx_curr_desc = mp->tx_curr_desc_q;
1792 mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1793 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
1794
1795 /* Assignment of Rx CRDP of given queue */
1796 rx_curr_desc = mp->rx_curr_desc_q;
1797 mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1798 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
1799
1800 /* Add the assigned Ethernet address to the port's address table */
ed9b5d45 1801 eth_port_uc_addr_set(port_num, dev->dev_addr);
1da177e4
LT		 1802
1803 /* Assign port configuration and command. */
01999873
DF		 1804 mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num),
1805 MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE);
1806
1807 mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num),
1808 MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE);
1da177e4 1809
d0412d96 1810 pscr = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
01999873
DF		 1811
1812 pscr &= ~(MV643XX_ETH_SERIAL_PORT_ENABLE | MV643XX_ETH_FORCE_LINK_PASS);
d0412d96 1813 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr);
1da177e4 1814
d0412d96
JC		 1815 pscr |= MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1816 MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII |
1817 MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX |
1818 MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL |
1819 MV643XX_ETH_SERIAL_PORT_CONTROL_RESERVED;
1da177e4 1820
d0412d96 1821 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr);
1da177e4 1822
d0412d96
JC		 1823 pscr |= MV643XX_ETH_SERIAL_PORT_ENABLE;
1824 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr);
1da177e4
LT		 1825
1826 /* Assign port SDMA configuration */
01999873
DF		 1827 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num),
1828 MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE);
1da177e4
LT		 1829
1830 /* Enable port Rx. */
ff561eef 1831 mv643xx_eth_port_enable_rx(port_num, ETH_RX_QUEUES_ENABLED);
8f543718
DF		 1832
1833 /* Disable port bandwidth limits by clearing MTU register */
1834 mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num), 0);
d0412d96
JC		 1835
1836 /* save phy settings across reset */
1837 mv643xx_get_settings(dev, &ethtool_cmd);
1838 ethernet_phy_reset(mp->port_num);
1839 mv643xx_set_settings(dev, &ethtool_cmd);
1da177e4
LT		 1840}
1841
1842/*
1843 * eth_port_uc_addr_set - This function Set the port Unicast address.
1844 *
1845 * DESCRIPTION:
1846 * This function Set the port Ethernet MAC address.
1847 *
1848 * INPUT:
1849 * unsigned int eth_port_num Port number.
1850 * char * p_addr Address to be set
1851 *
1852 * OUTPUT:
cf4086c7
DF		 1853 * Set MAC address low and high registers. also calls
1854 * eth_port_set_filter_table_entry() to set the unicast
1855 * table with the proper information.
1da177e4
LT		 1856 *
1857 * RETURN:
1858 * N/A.
1859 *
1860 */
1861static void eth_port_uc_addr_set(unsigned int eth_port_num,
1862 unsigned char *p_addr)
1863{
1864 unsigned int mac_h;
1865 unsigned int mac_l;
cf4086c7 1866 int table;
1da177e4
LT		 1867
1868 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1869 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
1870 (p_addr[3] << 0);
1871
1872 mv_write(MV643XX_ETH_MAC_ADDR_LOW(eth_port_num), mac_l);
1873 mv_write(MV643XX_ETH_MAC_ADDR_HIGH(eth_port_num), mac_h);
1874
1875 /* Accept frames of this address */
cf4086c7
DF		 1876 table = MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(eth_port_num);
1877 eth_port_set_filter_table_entry(table, p_addr[5] & 0x0f);
1da177e4
LT		 1878}
1879
1880/*
1881 * eth_port_uc_addr_get - This function retrieves the port Unicast address
1882 * (MAC address) from the ethernet hw registers.
1883 *
1884 * DESCRIPTION:
1885 * This function retrieves the port Ethernet MAC address.
1886 *
1887 * INPUT:
1888 * unsigned int eth_port_num Port number.
1889 * char *MacAddr pointer where the MAC address is stored
1890 *
1891 * OUTPUT:
1892 * Copy the MAC address to the location pointed to by MacAddr
1893 *
1894 * RETURN:
1895 * N/A.
1896 *
1897 */
1898static void eth_port_uc_addr_get(struct net_device *dev, unsigned char *p_addr)
1899{
1900 struct mv643xx_private *mp = netdev_priv(dev);
1901 unsigned int mac_h;
1902 unsigned int mac_l;
1903
1904 mac_h = mv_read(MV643XX_ETH_MAC_ADDR_HIGH(mp->port_num));
1905 mac_l = mv_read(MV643XX_ETH_MAC_ADDR_LOW(mp->port_num));
1906
1907 p_addr[0] = (mac_h >> 24) & 0xff;
1908 p_addr[1] = (mac_h >> 16) & 0xff;
1909 p_addr[2] = (mac_h >> 8) & 0xff;
1910 p_addr[3] = mac_h & 0xff;
1911 p_addr[4] = (mac_l >> 8) & 0xff;
1912 p_addr[5] = mac_l & 0xff;
1913}
1914
16e03018
DF		 1915/*
1916 * The entries in each table are indexed by a hash of a packet's MAC
1917 * address. One bit in each entry determines whether the packet is
1918 * accepted. There are 4 entries (each 8 bits wide) in each register
1919 * of the table. The bits in each entry are defined as follows:
1920 * 0 Accept=1, Drop=0
1921 * 3-1 Queue (ETH_Q0=0)
1922 * 7-4 Reserved = 0;
1923 */
1924static void eth_port_set_filter_table_entry(int table, unsigned char entry)
1925{
1926 unsigned int table_reg;
1927 unsigned int tbl_offset;
1928 unsigned int reg_offset;
1929
1930 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
1931 reg_offset = entry % 4; /* Entry offset within the register */
1932
1933 /* Set "accepts frame bit" at specified table entry */
1934 table_reg = mv_read(table + tbl_offset);
1935 table_reg |= 0x01 << (8 * reg_offset);
1936 mv_write(table + tbl_offset, table_reg);
1937}
1938
1939/*
1940 * eth_port_mc_addr - Multicast address settings.
1941 *
1942 * The MV device supports multicast using two tables:
1943 * 1) Special Multicast Table for MAC addresses of the form
1944 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
1945 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1946 * Table entries in the DA-Filter table.
1947 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
1948 * is used as an index to the Other Multicast Table entries in the
1949 * DA-Filter table. This function calculates the CRC-8bit value.
1950 * In either case, eth_port_set_filter_table_entry() is then called
1951 * to set to set the actual table entry.
1952 */
1953static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr)
1954{
1955 unsigned int mac_h;
1956 unsigned int mac_l;
1957 unsigned char crc_result = 0;
1958 int table;
1959 int mac_array[48];
1960 int crc[8];
1961 int i;
1962
1963 if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) &&
1964 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
1965 table = MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
1966 (eth_port_num);
1967 eth_port_set_filter_table_entry(table, p_addr[5]);
1968 return;
1969 }
1970
1971 /* Calculate CRC-8 out of the given address */
1972 mac_h = (p_addr[0] << 8) | (p_addr[1]);
1973 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
1974 (p_addr[4] << 8) | (p_addr[5] << 0);
1975
1976 for (i = 0; i < 32; i++)
1977 mac_array[i] = (mac_l >> i) & 0x1;
1978 for (i = 32; i < 48; i++)
1979 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
1980
1981 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
1982 mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
1983 mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
1984 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
1985 mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0];
1986
1987 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
1988 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
1989 mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
1990 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
1991 mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
1992 mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
1993 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0];
1994
1995 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
1996 mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
1997 mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
1998 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
1999 mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^
2000 mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0];
2001
2002 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2003 mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
2004 mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
2005 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
2006 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^
2007 mac_array[3] ^ mac_array[2] ^ mac_array[1];
2008
2009 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
2010 mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
2011 mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
2012 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
2013 mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^
2014 mac_array[3] ^ mac_array[2];
2015
2016 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
2017 mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
2018 mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
2019 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
2020 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^
2021 mac_array[4] ^ mac_array[3];
2022
2023 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
2024 mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
2025 mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
2026 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
2027 mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^
2028 mac_array[4];
2029
2030 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
2031 mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
2032 mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
2033 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
2034 mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5];
2035
2036 for (i = 0; i < 8; i++)
2037 crc_result = crc_result | (crc[i] << i);
2038
2039 table = MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num);
2040 eth_port_set_filter_table_entry(table, crc_result);
2041}
2042
2043/*
2044 * Set the entire multicast list based on dev->mc_list.
2045 */
2046static void eth_port_set_multicast_list(struct net_device *dev)
2047{
2048
2049 struct dev_mc_list *mc_list;
2050 int i;
2051 int table_index;
2052 struct mv643xx_private *mp = netdev_priv(dev);
2053 unsigned int eth_port_num = mp->port_num;
2054
2055 /* If the device is in promiscuous mode or in all multicast mode,
2056 * we will fully populate both multicast tables with accept.
2057 * This is guaranteed to yield a match on all multicast addresses...
2058 */
2059 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
2060 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
b4de9051
DF		 2061 /* Set all entries in DA filter special multicast
2062 * table (Ex_dFSMT)
2063 * Set for ETH_Q0 for now
2064 * Bits
2065 * 0 Accept=1, Drop=0
2066 * 3-1 Queue ETH_Q0=0
2067 * 7-4 Reserved = 0;
2068 */
2069 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2070
2071 /* Set all entries in DA filter other multicast
2072 * table (Ex_dFOMT)
2073 * Set for ETH_Q0 for now
2074 * Bits
2075 * 0 Accept=1, Drop=0
2076 * 3-1 Queue ETH_Q0=0
2077 * 7-4 Reserved = 0;
2078 */
2079 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2080 }
16e03018
DF		 2081 return;
2082 }
2083
2084 /* We will clear out multicast tables every time we get the list.
2085 * Then add the entire new list...
2086 */
2087 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2088 /* Clear DA filter special multicast table (Ex_dFSMT) */
2089 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2090 (eth_port_num) + table_index, 0);
2091
2092 /* Clear DA filter other multicast table (Ex_dFOMT) */
2093 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2094 (eth_port_num) + table_index, 0);
2095 }
2096
2097 /* Get pointer to net_device multicast list and add each one... */
2098 for (i = 0, mc_list = dev->mc_list;
2099 (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
2100 i++, mc_list = mc_list->next)
2101 if (mc_list->dmi_addrlen == 6)
2102 eth_port_mc_addr(eth_port_num, mc_list->dmi_addr);
2103}
2104
1da177e4
LT		 2105/*
2106 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2107 *
2108 * DESCRIPTION:
2109 * Go through all the DA filter tables (Unicast, Special Multicast &
2110 * Other Multicast) and set each entry to 0.
2111 *
2112 * INPUT:
2113 * unsigned int eth_port_num Ethernet Port number.
2114 *
2115 * OUTPUT:
2116 * Multicast and Unicast packets are rejected.
2117 *
2118 * RETURN:
2119 * None.
2120 */
2121static void eth_port_init_mac_tables(unsigned int eth_port_num)
2122{
2123 int table_index;
2124
2125 /* Clear DA filter unicast table (Ex_dFUT) */
2126 for (table_index = 0; table_index <= 0xC; table_index += 4)
cf4086c7
DF		 2127 mv_write(MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2128 (eth_port_num) + table_index, 0);
1da177e4
LT		 2129
2130 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2131 /* Clear DA filter special multicast table (Ex_dFSMT) */
16e03018
DF		 2132 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2133 (eth_port_num) + table_index, 0);
1da177e4 2134 /* Clear DA filter other multicast table (Ex_dFOMT) */
16e03018
DF		 2135 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2136 (eth_port_num) + table_index, 0);
1da177e4
LT		 2137 }
2138}
2139
2140/*
2141 * eth_clear_mib_counters - Clear all MIB counters
2142 *
2143 * DESCRIPTION:
2144 * This function clears all MIB counters of a specific ethernet port.
2145 * A read from the MIB counter will reset the counter.
2146 *
2147 * INPUT:
2148 * unsigned int eth_port_num Ethernet Port number.
2149 *
2150 * OUTPUT:
2151 * After reading all MIB counters, the counters resets.
2152 *
2153 * RETURN:
2154 * MIB counter value.
2155 *
2156 */
2157static void eth_clear_mib_counters(unsigned int eth_port_num)
2158{
2159 int i;
2160
2161 /* Perform dummy reads from MIB counters */
2162 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2163 i += 4)
2164 mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num) + i);
2165}
2166
2167static inline u32 read_mib(struct mv643xx_private *mp, int offset)
2168{
2169 return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp->port_num) + offset);
2170}
2171
2172static void eth_update_mib_counters(struct mv643xx_private *mp)
2173{
2174 struct mv643xx_mib_counters *p = &mp->mib_counters;
2175 int offset;
2176
2177 p->good_octets_received +=
2178 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
2179 p->good_octets_received +=
2180 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
2181
2182 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
2183 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
2184 offset += 4)
70fbf327 2185 *(u32 *)((char *)p + offset) += read_mib(mp, offset);
1da177e4
LT		 2186
2187 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
2188 p->good_octets_sent +=
2189 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
2190
2191 for (offset = ETH_MIB_GOOD_FRAMES_SENT;
2192 offset <= ETH_MIB_LATE_COLLISION;
2193 offset += 4)
70fbf327 2194 *(u32 *)((char *)p + offset) += read_mib(mp, offset);
1da177e4
LT		 2195}
2196
2197/*
2198 * ethernet_phy_detect - Detect whether a phy is present
2199 *
2200 * DESCRIPTION:
2201 * This function tests whether there is a PHY present on
2202 * the specified port.
2203 *
2204 * INPUT:
2205 * unsigned int eth_port_num Ethernet Port number.
2206 *
2207 * OUTPUT:
2208 * None
2209 *
2210 * RETURN:
2211 * 0 on success
2212 * -ENODEV on failure
2213 *
2214 */
2215static int ethernet_phy_detect(unsigned int port_num)
2216{
2217 unsigned int phy_reg_data0;
2218 int auto_neg;
2219
2220 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2221 auto_neg = phy_reg_data0 & 0x1000;
2222 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2223 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2224
2225 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2226 if ((phy_reg_data0 & 0x1000) == auto_neg)
2227 return -ENODEV; /* change didn't take */
2228
2229 phy_reg_data0 ^= 0x1000;
2230 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2231 return 0;
2232}
2233
2234/*
2235 * ethernet_phy_get - Get the ethernet port PHY address.
2236 *
2237 * DESCRIPTION:
2238 * This routine returns the given ethernet port PHY address.
2239 *
2240 * INPUT:
2241 * unsigned int eth_port_num Ethernet Port number.
2242 *
2243 * OUTPUT:
2244 * None.
2245 *
2246 * RETURN:
2247 * PHY address.
2248 *
2249 */
2250static int ethernet_phy_get(unsigned int eth_port_num)
2251{
2252 unsigned int reg_data;
2253
2254 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2255
2256 return ((reg_data >> (5 * eth_port_num)) & 0x1f);
2257}
2258
2259/*
2260 * ethernet_phy_set - Set the ethernet port PHY address.
2261 *
2262 * DESCRIPTION:
2263 * This routine sets the given ethernet port PHY address.
2264 *
2265 * INPUT:
2266 * unsigned int eth_port_num Ethernet Port number.
2267 * int phy_addr PHY address.
2268 *
2269 * OUTPUT:
2270 * None.
2271 *
2272 * RETURN:
2273 * None.
2274 *
2275 */
2276static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr)
2277{
2278 u32 reg_data;
2279 int addr_shift = 5 * eth_port_num;
2280
2281 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2282 reg_data &= ~(0x1f << addr_shift);
2283 reg_data |= (phy_addr & 0x1f) << addr_shift;
2284 mv_write(MV643XX_ETH_PHY_ADDR_REG, reg_data);
2285}
2286
2287/*
2288 * ethernet_phy_reset - Reset Ethernet port PHY.
2289 *
2290 * DESCRIPTION:
2291 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2292 *
2293 * INPUT:
2294 * unsigned int eth_port_num Ethernet Port number.
2295 *
2296 * OUTPUT:
2297 * The PHY is reset.
2298 *
2299 * RETURN:
2300 * None.
2301 *
2302 */
2303static void ethernet_phy_reset(unsigned int eth_port_num)
2304{
2305 unsigned int phy_reg_data;
2306
2307 /* Reset the PHY */
2308 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
2309 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2310 eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data);
d0412d96
JC		 2311
2312 /* wait for PHY to come out of reset */
2313 do {
2314 udelay(1);
2315 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
2316 } while (phy_reg_data & 0x8000);
1da177e4
LT		 2317}
2318
9f8dd319 2319static void mv643xx_eth_port_enable_tx(unsigned int port_num,
12a87c64 2320 unsigned int queues)
9f8dd319 2321{
12a87c64 2322 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), queues);
9f8dd319
DF		 2323}
2324
2325static void mv643xx_eth_port_enable_rx(unsigned int port_num,
12a87c64 2326 unsigned int queues)
9f8dd319 2327{
12a87c64 2328 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), queues);
9f8dd319
DF		 2329}
2330
2331static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num)
2332{
12a87c64 2333 u32 queues;
9f8dd319
DF		 2334
2335 /* Stop Tx port activity. Check port Tx activity. */
12a87c64 2336 queues = mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
9f8dd319 2337 & 0xFF;
12a87c64
DF		 2338 if (queues) {
2339 /* Issue stop command for active queues only */
9f8dd319 2340 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num),
12a87c64 2341 (queues << 8));
9f8dd319
DF		 2342
2343 /* Wait for all Tx activity to terminate. */
2344 /* Check port cause register that all Tx queues are stopped */
2345 while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
2346 & 0xFF)
2347 udelay(PHY_WAIT_MICRO_SECONDS);
2348
2349 /* Wait for Tx FIFO to empty */
2350 while (mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num)) &
2351 ETH_PORT_TX_FIFO_EMPTY)
2352 udelay(PHY_WAIT_MICRO_SECONDS);
2353 }
2354
12a87c64 2355 return queues;
9f8dd319
DF		 2356}
2357
2358static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num)
2359{
12a87c64 2360 u32 queues;
9f8dd319
DF		 2361
2362 /* Stop Rx port activity. Check port Rx activity. */
12a87c64 2363 queues = mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
e38fd1a0 2364 & 0xFF;
12a87c64
DF		 2365 if (queues) {
2366 /* Issue stop command for active queues only */
9f8dd319 2367 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
12a87c64 2368 (queues << 8));
9f8dd319
DF		 2369
2370 /* Wait for all Rx activity to terminate. */
2371 /* Check port cause register that all Rx queues are stopped */
2372 while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
2373 & 0xFF)
2374 udelay(PHY_WAIT_MICRO_SECONDS);
2375 }
2376
12a87c64 2377 return queues;
9f8dd319
DF		 2378}
2379
1da177e4
LT		 2380/*
2381 * eth_port_reset - Reset Ethernet port
2382 *
2383 * DESCRIPTION:
2384 * This routine resets the chip by aborting any SDMA engine activity and
2385 * clearing the MIB counters. The Receiver and the Transmit unit are in
2386 * idle state after this command is performed and the port is disabled.
2387 *
2388 * INPUT:
2389 * unsigned int eth_port_num Ethernet Port number.
2390 *
2391 * OUTPUT:
2392 * Channel activity is halted.
2393 *
2394 * RETURN:
2395 * None.
2396 *
2397 */
2398static void eth_port_reset(unsigned int port_num)
2399{
2400 unsigned int reg_data;
2401
9f8dd319
DF		 2402 mv643xx_eth_port_disable_tx(port_num);
2403 mv643xx_eth_port_disable_rx(port_num);
1da177e4
LT		 2404
2405 /* Clear all MIB counters */
2406 eth_clear_mib_counters(port_num);
2407
2408 /* Reset the Enable bit in the Configuration Register */
2409 reg_data = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
d0412d96
JC		 2410 reg_data &= ~(MV643XX_ETH_SERIAL_PORT_ENABLE |
2411 MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL |
2412 MV643XX_ETH_FORCE_LINK_PASS);
1da177e4
LT		 2413 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), reg_data);
2414}
2415
1da177e4 2416
1da177e4
LT		 2417/*
2418 * eth_port_read_smi_reg - Read PHY registers
2419 *
2420 * DESCRIPTION:
2421 * This routine utilize the SMI interface to interact with the PHY in
2422 * order to perform PHY register read.
2423 *
2424 * INPUT:
2425 * unsigned int port_num Ethernet Port number.
2426 * unsigned int phy_reg PHY register address offset.
2427 * unsigned int *value Register value buffer.
2428 *
2429 * OUTPUT:
2430 * Write the value of a specified PHY register into given buffer.
2431 *
2432 * RETURN:
2433 * false if the PHY is busy or read data is not in valid state.
2434 * true otherwise.
2435 *
2436 */
2437static void eth_port_read_smi_reg(unsigned int port_num,
2438 unsigned int phy_reg, unsigned int *value)
2439{
2440 int phy_addr = ethernet_phy_get(port_num);
2441 unsigned long flags;
2442 int i;
2443
2444 /* the SMI register is a shared resource */
2445 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2446
2447 /* wait for the SMI register to become available */
2448 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2449 if (i == PHY_WAIT_ITERATIONS) {
2450 printk("mv643xx PHY busy timeout, port %d\n", port_num);
2451 goto out;
2452 }
2453 udelay(PHY_WAIT_MICRO_SECONDS);
2454 }
2455
2456 mv_write(MV643XX_ETH_SMI_REG,
2457 (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);
2458
2459 /* now wait for the data to be valid */
2460 for (i = 0; !(mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_READ_VALID); i++) {
2461 if (i == PHY_WAIT_ITERATIONS) {
2462 printk("mv643xx PHY read timeout, port %d\n", port_num);
2463 goto out;
2464 }
2465 udelay(PHY_WAIT_MICRO_SECONDS);
2466 }
2467
2468 *value = mv_read(MV643XX_ETH_SMI_REG) & 0xffff;
2469out:
2470 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2471}
2472
2473/*
2474 * eth_port_write_smi_reg - Write to PHY registers
2475 *
2476 * DESCRIPTION:
2477 * This routine utilize the SMI interface to interact with the PHY in
2478 * order to perform writes to PHY registers.
2479 *
2480 * INPUT:
2481 * unsigned int eth_port_num Ethernet Port number.
2482 * unsigned int phy_reg PHY register address offset.
2483 * unsigned int value Register value.
2484 *
2485 * OUTPUT:
2486 * Write the given value to the specified PHY register.
2487 *
2488 * RETURN:
2489 * false if the PHY is busy.
2490 * true otherwise.
2491 *
2492 */
2493static void eth_port_write_smi_reg(unsigned int eth_port_num,
2494 unsigned int phy_reg, unsigned int value)
2495{
2496 int phy_addr;
2497 int i;
2498 unsigned long flags;
2499
2500 phy_addr = ethernet_phy_get(eth_port_num);
2501
2502 /* the SMI register is a shared resource */
2503 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2504
2505 /* wait for the SMI register to become available */
2506 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2507 if (i == PHY_WAIT_ITERATIONS) {
2508 printk("mv643xx PHY busy timeout, port %d\n",
2509 eth_port_num);
2510 goto out;
2511 }
2512 udelay(PHY_WAIT_MICRO_SECONDS);
2513 }
2514
2515 mv_write(MV643XX_ETH_SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
2516 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2517out:
2518 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2519}
2520
c28a4f89
JC		 2521/*
2522 * Wrappers for MII support library.
2523 */
2524static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location)
2525{
2526 int val;
2527 struct mv643xx_private *mp = netdev_priv(dev);
2528
2529 eth_port_read_smi_reg(mp->port_num, location, &val);
2530 return val;
2531}
2532
2533static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val)
2534{
2535 struct mv643xx_private *mp = netdev_priv(dev);
2536 eth_port_write_smi_reg(mp->port_num, location, val);
2537}
2538
1da177e4
LT		 2539/*
2540 * eth_port_receive - Get received information from Rx ring.
2541 *
2542 * DESCRIPTION:
2543 * This routine returns the received data to the caller. There is no
2544 * data copying during routine operation. All information is returned
2545 * using pointer to packet information struct passed from the caller.
2546 * If the routine exhausts Rx ring resources then the resource error flag
2547 * is set.
2548 *
2549 * INPUT:
2550 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2551 * struct pkt_info *p_pkt_info User packet buffer.
2552 *
2553 * OUTPUT:
2554 * Rx ring current and used indexes are updated.
2555 *
2556 * RETURN:
2557 * ETH_ERROR in case the routine can not access Rx desc ring.
2558 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
2559 * ETH_END_OF_JOB if there is no received data.
2560 * ETH_OK otherwise.
2561 */
2562static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
2563 struct pkt_info *p_pkt_info)
2564{
2565 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
2566 volatile struct eth_rx_desc *p_rx_desc;
2567 unsigned int command_status;
8f518703 2568 unsigned long flags;
1da177e4
LT		 2569
2570 /* Do not process Rx ring in case of Rx ring resource error */
2571 if (mp->rx_resource_err)
2572 return ETH_QUEUE_FULL;
2573
8f518703
DF		 2574 spin_lock_irqsave(&mp->lock, flags);
2575
1da177e4
LT		 2576 /* Get the Rx Desc ring 'curr and 'used' indexes */
2577 rx_curr_desc = mp->rx_curr_desc_q;
2578 rx_used_desc = mp->rx_used_desc_q;
2579
2580 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];
2581
2582 /* The following parameters are used to save readings from memory */
2583 command_status = p_rx_desc->cmd_sts;
2584 rmb();
2585
2586 /* Nothing to receive... */
8f518703
DF		 2587 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2588 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 2589 return ETH_END_OF_JOB;
8f518703 2590 }
1da177e4
LT		 2591
2592 p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET;
2593 p_pkt_info->cmd_sts = command_status;
2594 p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET;
2595 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
2596 p_pkt_info->l4i_chk = p_rx_desc->buf_size;
2597
b4de9051
DF		 2598 /*
2599 * Clean the return info field to indicate that the
2600 * packet has been moved to the upper layers
2601 */
1da177e4
LT		 2602 mp->rx_skb[rx_curr_desc] = NULL;
2603
2604 /* Update current index in data structure */
2605 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
2606 mp->rx_curr_desc_q = rx_next_curr_desc;
2607
2608 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
2609 if (rx_next_curr_desc == rx_used_desc)
2610 mp->rx_resource_err = 1;
2611
8f518703
DF		 2612 spin_unlock_irqrestore(&mp->lock, flags);
2613
1da177e4
LT		 2614 return ETH_OK;
2615}
2616
2617/*
2618 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
2619 *
2620 * DESCRIPTION:
2621 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
2622 * next 'used' descriptor and attached the returned buffer to it.
2623 * In case the Rx ring was in "resource error" condition, where there are
2624 * no available Rx resources, the function resets the resource error flag.
2625 *
2626 * INPUT:
2627 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2628 * struct pkt_info *p_pkt_info Information on returned buffer.
2629 *
2630 * OUTPUT:
2631 * New available Rx resource in Rx descriptor ring.
2632 *
2633 * RETURN:
2634 * ETH_ERROR in case the routine can not access Rx desc ring.
2635 * ETH_OK otherwise.
2636 */
2637static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
2638 struct pkt_info *p_pkt_info)
2639{
2640 int used_rx_desc; /* Where to return Rx resource */
2641 volatile struct eth_rx_desc *p_used_rx_desc;
8f518703
DF		 2642 unsigned long flags;
2643
2644 spin_lock_irqsave(&mp->lock, flags);
1da177e4
LT		 2645
2646 /* Get 'used' Rx descriptor */
2647 used_rx_desc = mp->rx_used_desc_q;
2648 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];
2649
2650 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
2651 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
2652 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
2653
2654 /* Flush the write pipe */
2655
2656 /* Return the descriptor to DMA ownership */
2657 wmb();
2658 p_used_rx_desc->cmd_sts =
2659 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
2660 wmb();
2661
2662 /* Move the used descriptor pointer to the next descriptor */
2663 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;
2664
2665 /* Any Rx return cancels the Rx resource error status */
2666 mp->rx_resource_err = 0;
2667
8f518703
DF		 2668 spin_unlock_irqrestore(&mp->lock, flags);
2669
1da177e4
LT		 2670 return ETH_OK;
2671}
2672
2673/************* Begin ethtool support *************************/
2674
2675struct mv643xx_stats {
2676 char stat_string[ETH_GSTRING_LEN];
2677 int sizeof_stat;
2678 int stat_offset;
2679};
2680
2681#define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \
b4de9051 2682 offsetof(struct mv643xx_private, m)
1da177e4
LT		 2683
2684static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
2685 { "rx_packets", MV643XX_STAT(stats.rx_packets) },
2686 { "tx_packets", MV643XX_STAT(stats.tx_packets) },
2687 { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
2688 { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
2689 { "rx_errors", MV643XX_STAT(stats.rx_errors) },
2690 { "tx_errors", MV643XX_STAT(stats.tx_errors) },
2691 { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
2692 { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
2693 { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
2694 { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
2695 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
2696 { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
2697 { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
2698 { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
2699 { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
2700 { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
2701 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
2702 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
2703 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
2704 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
2705 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
2706 { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
2707 { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
2708 { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
2709 { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
2710 { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
2711 { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
2712 { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
2713 { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
2714 { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
2715 { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
2716 { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
2717 { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
2718 { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
2719 { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
2720 { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
2721 { "collision", MV643XX_STAT(mib_counters.collision) },
2722 { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
2723};
2724
2725#define MV643XX_STATS_LEN \
2726 sizeof(mv643xx_gstrings_stats) / sizeof(struct mv643xx_stats)
2727
b4de9051
DF		 2728static void mv643xx_get_drvinfo(struct net_device *netdev,
2729 struct ethtool_drvinfo *drvinfo)
1da177e4
LT		 2730{
2731 strncpy(drvinfo->driver, mv643xx_driver_name, 32);
2732 strncpy(drvinfo->version, mv643xx_driver_version, 32);
2733 strncpy(drvinfo->fw_version, "N/A", 32);
2734 strncpy(drvinfo->bus_info, "mv643xx", 32);
2735 drvinfo->n_stats = MV643XX_STATS_LEN;
2736}
2737
b4de9051 2738static int mv643xx_get_stats_count(struct net_device *netdev)
1da177e4
LT		 2739{
2740 return MV643XX_STATS_LEN;
2741}
2742
b4de9051
DF		 2743static void mv643xx_get_ethtool_stats(struct net_device *netdev,
2744 struct ethtool_stats *stats, uint64_t *data)
1da177e4
LT		 2745{
2746 struct mv643xx_private *mp = netdev->priv;
2747 int i;
2748
2749 eth_update_mib_counters(mp);
2750
b4de9051 2751 for (i = 0; i < MV643XX_STATS_LEN; i++) {
6aa20a22 2752 char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset;
b4de9051 2753 data[i] = (mv643xx_gstrings_stats[i].sizeof_stat ==
1da177e4
LT		 2754 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
2755 }
2756}
2757
b4de9051
DF		 2758static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset,
2759 uint8_t *data)
1da177e4
LT		 2760{
2761 int i;
2762
2763 switch(stringset) {
2764 case ETH_SS_STATS:
2765 for (i=0; i < MV643XX_STATS_LEN; i++) {
b4de9051
DF		 2766 memcpy(data + i * ETH_GSTRING_LEN,
2767 mv643xx_gstrings_stats[i].stat_string,
2768 ETH_GSTRING_LEN);
1da177e4
LT		 2769 }
2770 break;
2771 }
2772}
2773
d0412d96
JC		 2774static u32 mv643xx_eth_get_link(struct net_device *dev)
2775{
2776 struct mv643xx_private *mp = netdev_priv(dev);
2777
2778 return mii_link_ok(&mp->mii);
2779}
2780
2781static int mv643xx_eth_nway_restart(struct net_device *dev)
2782{
2783 struct mv643xx_private *mp = netdev_priv(dev);
2784
2785 return mii_nway_restart(&mp->mii);
2786}
2787
2788static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2789{
2790 struct mv643xx_private *mp = netdev_priv(dev);
2791
2792 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2793}
2794
7282d491 2795static const struct ethtool_ops mv643xx_ethtool_ops = {
1da177e4 2796 .get_settings = mv643xx_get_settings,
d0412d96 2797 .set_settings = mv643xx_set_settings,
1da177e4 2798 .get_drvinfo = mv643xx_get_drvinfo,
d0412d96 2799 .get_link = mv643xx_eth_get_link,
1da177e4
LT		 2800 .get_sg = ethtool_op_get_sg,
2801 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 2802 .get_stats_count = mv643xx_get_stats_count,
2803 .get_ethtool_stats = mv643xx_get_ethtool_stats,
d0412d96
JC		 2804 .get_strings = mv643xx_get_strings,
2805 .get_stats_count = mv643xx_get_stats_count,
2806 .get_ethtool_stats = mv643xx_get_ethtool_stats,
2807 .nway_reset = mv643xx_eth_nway_restart,
1da177e4
LT		 2808};
2809
2810/************* End ethtool support *************************/
Linux kernel - Deliverables
This page took 1.029984 seconds and 5 git commands to generate.