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mv643xx_eth: avoid dropping tx lock during transmit reclaim
[deliverable/linux.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
1da177e4
LT		 41#include <linux/tcp.h>
42#include <linux/udp.h>
43#include <linux/etherdevice.h>
1da177e4
LT		 44#include <linux/delay.h>
45#include <linux/ethtool.h>
d052d1be 46#include <linux/platform_device.h>
fbd6a754
LB		 47#include <linux/module.h>
48#include <linux/kernel.h>
49#include <linux/spinlock.h>
50#include <linux/workqueue.h>
51#include <linux/mii.h>
fbd6a754 52#include <linux/mv643xx_eth.h>
1da177e4
LT		 53#include <asm/io.h>
54#include <asm/types.h>
1da177e4 55#include <asm/system.h>
fbd6a754 56
e5371493 57static char mv643xx_eth_driver_name[] = "mv643xx_eth";
c4560318 58static char mv643xx_eth_driver_version[] = "1.3";
c9df406f 59
fbd6a754 60
fbd6a754
LB		 61/*
62 * Registers shared between all ports.
63 */
3cb4667c
LB		 64#define PHY_ADDR 0x0000
65#define SMI_REG 0x0004
45c5d3bc
LB		 66#define SMI_BUSY 0x10000000
67#define SMI_READ_VALID 0x08000000
68#define SMI_OPCODE_READ 0x04000000
69#define SMI_OPCODE_WRITE 0x00000000
70#define ERR_INT_CAUSE 0x0080
71#define ERR_INT_SMI_DONE 0x00000010
72#define ERR_INT_MASK 0x0084
3cb4667c
LB		 73#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
74#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
75#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
76#define WINDOW_BAR_ENABLE 0x0290
77#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 78
79/*
80 * Per-port registers.
81 */
3cb4667c 82#define PORT_CONFIG(p) (0x0400 + ((p) << 10))
d9a073ea 83#define UNICAST_PROMISCUOUS_MODE 0x00000001
3cb4667c
LB		 84#define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
85#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
86#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
87#define SDMA_CONFIG(p) (0x041c + ((p) << 10))
88#define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
89#define PORT_STATUS(p) (0x0444 + ((p) << 10))
a2a41689 90#define TX_FIFO_EMPTY 0x00000400
ae9ae064 91#define TX_IN_PROGRESS 0x00000080
2f7eb47a
LB		 92#define PORT_SPEED_MASK 0x00000030
93#define PORT_SPEED_1000 0x00000010
94#define PORT_SPEED_100 0x00000020
95#define PORT_SPEED_10 0x00000000
96#define FLOW_CONTROL_ENABLED 0x00000008
97#define FULL_DUPLEX 0x00000004
81600eea 98#define LINK_UP 0x00000002
3cb4667c 99#define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
89df5fdc
LB		 100#define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
101#define TX_BW_RATE(p) (0x0450 + ((p) << 10))
3cb4667c 102#define TX_BW_MTU(p) (0x0458 + ((p) << 10))
89df5fdc 103#define TX_BW_BURST(p) (0x045c + ((p) << 10))
3cb4667c 104#define INT_CAUSE(p) (0x0460 + ((p) << 10))
226bb6b7 105#define INT_TX_END 0x07f80000
befefe21 106#define INT_RX 0x000003fc
073a345c 107#define INT_EXT 0x00000002
3cb4667c 108#define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
befefe21
LB		 109#define INT_EXT_LINK_PHY 0x00110000
110#define INT_EXT_TX 0x000000ff
3cb4667c
LB		 111#define INT_MASK(p) (0x0468 + ((p) << 10))
112#define INT_MASK_EXT(p) (0x046c + ((p) << 10))
113#define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
1e881592
LB		 114#define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
115#define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
116#define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
117#define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
64da80a2 118#define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
3cb4667c 119#define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
3d6b35bc
LB		 120#define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
121#define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
122#define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
123#define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
3cb4667c
LB		 124#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
125#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
126#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
127#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 128
2679a550
LB		 129
130/*
131 * SDMA configuration register.
132 */
cd4ccf76 133#define RX_BURST_SIZE_16_64BIT (4 << 1)
fbd6a754 134#define BLM_RX_NO_SWAP (1 << 4)
fbd6a754 135#define BLM_TX_NO_SWAP (1 << 5)
cd4ccf76 136#define TX_BURST_SIZE_16_64BIT (4 << 22)
fbd6a754
LB		 137
138#if defined(__BIG_ENDIAN)
139#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
cd4ccf76
LB		 140 RX_BURST_SIZE_16_64BIT | \
141 TX_BURST_SIZE_16_64BIT
fbd6a754
LB		 142#elif defined(__LITTLE_ENDIAN)
143#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
cd4ccf76 144 RX_BURST_SIZE_16_64BIT | \
fbd6a754
LB		 145 BLM_RX_NO_SWAP | \
146 BLM_TX_NO_SWAP | \
cd4ccf76 147 TX_BURST_SIZE_16_64BIT
fbd6a754
LB		 148#else
149#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
150#endif
151
2beff77b
LB		 152
153/*
154 * Port serial control register.
155 */
156#define SET_MII_SPEED_TO_100 (1 << 24)
157#define SET_GMII_SPEED_TO_1000 (1 << 23)
158#define SET_FULL_DUPLEX_MODE (1 << 21)
fbd6a754 159#define MAX_RX_PACKET_9700BYTE (5 << 17)
2beff77b
LB		 160#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
161#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
162#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
163#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
164#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
165#define FORCE_LINK_PASS (1 << 1)
166#define SERIAL_PORT_ENABLE (1 << 0)
fbd6a754 167
cc9754b3
LB		 168#define DEFAULT_RX_QUEUE_SIZE 400
169#define DEFAULT_TX_QUEUE_SIZE 800
fbd6a754 170
fbd6a754 171
7ca72a3b
LB		 172/*
173 * RX/TX descriptors.
fbd6a754
LB		 174 */
175#if defined(__BIG_ENDIAN)
cc9754b3 176struct rx_desc {
fbd6a754
LB		 177 u16 byte_cnt; /* Descriptor buffer byte count */
178 u16 buf_size; /* Buffer size */
179 u32 cmd_sts; /* Descriptor command status */
180 u32 next_desc_ptr; /* Next descriptor pointer */
181 u32 buf_ptr; /* Descriptor buffer pointer */
182};
183
cc9754b3 184struct tx_desc {
fbd6a754
LB		 185 u16 byte_cnt; /* buffer byte count */
186 u16 l4i_chk; /* CPU provided TCP checksum */
187 u32 cmd_sts; /* Command/status field */
188 u32 next_desc_ptr; /* Pointer to next descriptor */
189 u32 buf_ptr; /* pointer to buffer for this descriptor*/
190};
191#elif defined(__LITTLE_ENDIAN)
cc9754b3 192struct rx_desc {
fbd6a754
LB		 193 u32 cmd_sts; /* Descriptor command status */
194 u16 buf_size; /* Buffer size */
195 u16 byte_cnt; /* Descriptor buffer byte count */
196 u32 buf_ptr; /* Descriptor buffer pointer */
197 u32 next_desc_ptr; /* Next descriptor pointer */
198};
199
cc9754b3 200struct tx_desc {
fbd6a754
LB		 201 u32 cmd_sts; /* Command/status field */
202 u16 l4i_chk; /* CPU provided TCP checksum */
203 u16 byte_cnt; /* buffer byte count */
204 u32 buf_ptr; /* pointer to buffer for this descriptor*/
205 u32 next_desc_ptr; /* Pointer to next descriptor */
206};
207#else
208#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
209#endif
210
7ca72a3b 211/* RX & TX descriptor command */
cc9754b3 212#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 213
214/* RX & TX descriptor status */
cc9754b3 215#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 216
217/* RX descriptor status */
cc9754b3
LB		 218#define LAYER_4_CHECKSUM_OK 0x40000000
219#define RX_ENABLE_INTERRUPT 0x20000000
220#define RX_FIRST_DESC 0x08000000
221#define RX_LAST_DESC 0x04000000
7ca72a3b
LB		 222
223/* TX descriptor command */
cc9754b3
LB		 224#define TX_ENABLE_INTERRUPT 0x00800000
225#define GEN_CRC 0x00400000
226#define TX_FIRST_DESC 0x00200000
227#define TX_LAST_DESC 0x00100000
228#define ZERO_PADDING 0x00080000
229#define GEN_IP_V4_CHECKSUM 0x00040000
230#define GEN_TCP_UDP_CHECKSUM 0x00020000
231#define UDP_FRAME 0x00010000
e32b6617
LB		 232#define MAC_HDR_EXTRA_4_BYTES 0x00008000
233#define MAC_HDR_EXTRA_8_BYTES 0x00000200
7ca72a3b 234
cc9754b3 235#define TX_IHL_SHIFT 11
7ca72a3b
LB		 236
237
c9df406f 238/* global *******************************************************************/
e5371493 239struct mv643xx_eth_shared_private {
fc32b0e2
LB		 240 /*
241 * Ethernet controller base address.
242 */
cc9754b3 243 void __iomem *base;
c9df406f 244
fc0eb9f2
LB		 245 /*
246 * Points at the right SMI instance to use.
247 */
248 struct mv643xx_eth_shared_private *smi;
249
fc32b0e2
LB		 250 /*
251 * Protects access to SMI_REG, which is shared between ports.
252 */
2b3ba0e3 253 struct mutex phy_lock;
c9df406f 254
45c5d3bc
LB		 255 /*
256 * If we have access to the error interrupt pin (which is
257 * somewhat misnamed as it not only reflects internal errors
258 * but also reflects SMI completion), use that to wait for
259 * SMI access completion instead of polling the SMI busy bit.
260 */
261 int err_interrupt;
262 wait_queue_head_t smi_busy_wait;
263
fc32b0e2
LB		 264 /*
265 * Per-port MBUS window access register value.
266 */
c9df406f
LB		 267 u32 win_protect;
268
fc32b0e2
LB		 269 /*
270 * Hardware-specific parameters.
271 */
c9df406f 272 unsigned int t_clk;
773fc3ee 273 int extended_rx_coal_limit;
1e881592 274 int tx_bw_control_moved;
c9df406f
LB		 275};
276
277
278/* per-port *****************************************************************/
e5371493 279struct mib_counters {
fbd6a754
LB		 280 u64 good_octets_received;
281 u32 bad_octets_received;
282 u32 internal_mac_transmit_err;
283 u32 good_frames_received;
284 u32 bad_frames_received;
285 u32 broadcast_frames_received;
286 u32 multicast_frames_received;
287 u32 frames_64_octets;
288 u32 frames_65_to_127_octets;
289 u32 frames_128_to_255_octets;
290 u32 frames_256_to_511_octets;
291 u32 frames_512_to_1023_octets;
292 u32 frames_1024_to_max_octets;
293 u64 good_octets_sent;
294 u32 good_frames_sent;
295 u32 excessive_collision;
296 u32 multicast_frames_sent;
297 u32 broadcast_frames_sent;
298 u32 unrec_mac_control_received;
299 u32 fc_sent;
300 u32 good_fc_received;
301 u32 bad_fc_received;
302 u32 undersize_received;
303 u32 fragments_received;
304 u32 oversize_received;
305 u32 jabber_received;
306 u32 mac_receive_error;
307 u32 bad_crc_event;
308 u32 collision;
309 u32 late_collision;
310};
311
8a578111 312struct rx_queue {
64da80a2
LB		 313 int index;
314
8a578111
LB		 315 int rx_ring_size;
316
317 int rx_desc_count;
318 int rx_curr_desc;
319 int rx_used_desc;
320
321 struct rx_desc *rx_desc_area;
322 dma_addr_t rx_desc_dma;
323 int rx_desc_area_size;
324 struct sk_buff **rx_skb;
8a578111
LB		 325};
326
13d64285 327struct tx_queue {
3d6b35bc
LB		 328 int index;
329
13d64285 330 int tx_ring_size;
fbd6a754 331
13d64285
LB		 332 int tx_desc_count;
333 int tx_curr_desc;
334 int tx_used_desc;
fbd6a754 335
5daffe94 336 struct tx_desc *tx_desc_area;
fbd6a754
LB		 337 dma_addr_t tx_desc_dma;
338 int tx_desc_area_size;
339 struct sk_buff **tx_skb;
8fd89211
LB		 340
341 unsigned long tx_packets;
342 unsigned long tx_bytes;
343 unsigned long tx_dropped;
13d64285
LB		 344};
345
346struct mv643xx_eth_private {
347 struct mv643xx_eth_shared_private *shared;
fc32b0e2 348 int port_num;
13d64285 349
fc32b0e2 350 struct net_device *dev;
fbd6a754 351
fc32b0e2 352 int phy_addr;
fbd6a754 353
fc32b0e2
LB		 354 struct mib_counters mib_counters;
355 struct work_struct tx_timeout_task;
fbd6a754 356 struct mii_if_info mii;
8a578111 357
1fa38c58
LB		 358 struct napi_struct napi;
359 u8 work_link;
360 u8 work_tx;
361 u8 work_tx_end;
362 u8 work_rx;
363 u8 work_rx_refill;
364 u8 work_rx_oom;
365
8a578111
LB		 366 /*
367 * RX state.
368 */
369 int default_rx_ring_size;
370 unsigned long rx_desc_sram_addr;
371 int rx_desc_sram_size;
f7981c1c 372 int rxq_count;
2257e05c 373 struct timer_list rx_oom;
64da80a2 374 struct rx_queue rxq[8];
13d64285
LB		 375
376 /*
377 * TX state.
378 */
379 int default_tx_ring_size;
380 unsigned long tx_desc_sram_addr;
381 int tx_desc_sram_size;
f7981c1c 382 int txq_count;
3d6b35bc 383 struct tx_queue txq[8];
fbd6a754 384};
1da177e4 385
fbd6a754 386
c9df406f 387/* port register accessors **************************************************/
e5371493 388static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 389{
cc9754b3 390 return readl(mp->shared->base + offset);
c9df406f 391}
fbd6a754 392
e5371493 393static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 394{
cc9754b3 395 writel(data, mp->shared->base + offset);
c9df406f 396}
fbd6a754 397
fbd6a754 398
c9df406f 399/* rxq/txq helper functions *************************************************/
8a578111 400static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 401{
64da80a2 402 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 403}
fbd6a754 404
13d64285
LB		 405static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
406{
3d6b35bc 407 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 408}
409
8a578111 410static void rxq_enable(struct rx_queue *rxq)
c9df406f 411{
8a578111 412 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 413 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
8a578111 414}
1da177e4 415
8a578111
LB		 416static void rxq_disable(struct rx_queue *rxq)
417{
418 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 419 u8 mask = 1 << rxq->index;
1da177e4 420
8a578111
LB		 421 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
422 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
423 udelay(10);
c9df406f
LB		 424}
425
6b368f68
LB		 426static void txq_reset_hw_ptr(struct tx_queue *txq)
427{
428 struct mv643xx_eth_private *mp = txq_to_mp(txq);
429 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
430 u32 addr;
431
432 addr = (u32)txq->tx_desc_dma;
433 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
434 wrl(mp, off, addr);
435}
436
13d64285 437static void txq_enable(struct tx_queue *txq)
1da177e4 438{
13d64285 439 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 440 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
1da177e4
LT		 441}
442
13d64285 443static void txq_disable(struct tx_queue *txq)
1da177e4 444{
13d64285 445 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 446 u8 mask = 1 << txq->index;
c9df406f 447
13d64285
LB		 448 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
449 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
450 udelay(10);
451}
452
1fa38c58 453static void txq_maybe_wake(struct tx_queue *txq)
13d64285
LB		 454{
455 struct mv643xx_eth_private *mp = txq_to_mp(txq);
e5ef1de1 456 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
3d6b35bc 457
8fd89211
LB		 458 if (netif_tx_queue_stopped(nq)) {
459 __netif_tx_lock(nq, smp_processor_id());
460 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
461 netif_tx_wake_queue(nq);
462 __netif_tx_unlock(nq);
463 }
1da177e4
LT		 464}
465
c9df406f 466
1fa38c58 467/* rx napi ******************************************************************/
8a578111 468static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 469{
8a578111
LB		 470 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
471 struct net_device_stats *stats = &mp->dev->stats;
472 int rx;
1da177e4 473
8a578111 474 rx = 0;
9e1f3772 475 while (rx < budget && rxq->rx_desc_count) {
fc32b0e2 476 struct rx_desc *rx_desc;
96587661 477 unsigned int cmd_sts;
fc32b0e2 478 struct sk_buff *skb;
ff561eef 479
8a578111 480 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 481
96587661 482 cmd_sts = rx_desc->cmd_sts;
2257e05c 483 if (cmd_sts & BUFFER_OWNED_BY_DMA)
96587661 484 break;
96587661 485 rmb();
1da177e4 486
8a578111
LB		 487 skb = rxq->rx_skb[rxq->rx_curr_desc];
488 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 489
9da78745
LB		 490 rxq->rx_curr_desc++;
491 if (rxq->rx_curr_desc == rxq->rx_ring_size)
492 rxq->rx_curr_desc = 0;
ff561eef 493
3a499481 494 dma_unmap_single(NULL, rx_desc->buf_ptr,
abe78717 495 rx_desc->buf_size, DMA_FROM_DEVICE);
8a578111
LB		 496 rxq->rx_desc_count--;
497 rx++;
b1dd9ca1 498
1fa38c58
LB		 499 mp->work_rx_refill |= 1 << rxq->index;
500
468d09f8
DF		 501 /*
502 * Update statistics.
fc32b0e2
LB		 503 *
504 * Note that the descriptor byte count includes 2 dummy
505 * bytes automatically inserted by the hardware at the
506 * start of the packet (which we don't count), and a 4
507 * byte CRC at the end of the packet (which we do count).
468d09f8 508 */
1da177e4 509 stats->rx_packets++;
fc32b0e2 510 stats->rx_bytes += rx_desc->byte_cnt - 2;
96587661 511
1da177e4 512 /*
fc32b0e2
LB		 513 * In case we received a packet without first / last bits
514 * on, or the error summary bit is set, the packet needs
515 * to be dropped.
1da177e4 516 */
96587661 517 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 518 (RX_FIRST_DESC | RX_LAST_DESC))
96587661 519 || (cmd_sts & ERROR_SUMMARY)) {
1da177e4 520 stats->rx_dropped++;
fc32b0e2 521
96587661 522 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 523 (RX_FIRST_DESC | RX_LAST_DESC)) {
1da177e4 524 if (net_ratelimit())
fc32b0e2
LB		 525 dev_printk(KERN_ERR, &mp->dev->dev,
526 "received packet spanning "
527 "multiple descriptors\n");
1da177e4 528 }
fc32b0e2 529
96587661 530 if (cmd_sts & ERROR_SUMMARY)
1da177e4
LT		 531 stats->rx_errors++;
532
78fff83b 533 dev_kfree_skb(skb);
1da177e4
LT		 534 } else {
535 /*
536 * The -4 is for the CRC in the trailer of the
537 * received packet
538 */
fc32b0e2 539 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
1da177e4 540
96587661 541 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
1da177e4
LT		 542 skb->ip_summed = CHECKSUM_UNNECESSARY;
543 skb->csum = htons(
96587661 544 (cmd_sts & 0x0007fff8) >> 3);
1da177e4 545 }
8a578111 546 skb->protocol = eth_type_trans(skb, mp->dev);
1da177e4 547 netif_receive_skb(skb);
1da177e4 548 }
fc32b0e2 549
8a578111 550 mp->dev->last_rx = jiffies;
1da177e4 551 }
fc32b0e2 552
1fa38c58
LB		 553 if (rx < budget)
554 mp->work_rx &= ~(1 << rxq->index);
555
8a578111 556 return rx;
1da177e4
LT		 557}
558
1fa38c58 559static int rxq_refill(struct rx_queue *rxq, int budget)
d0412d96 560{
1fa38c58
LB		 561 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
562 int skb_size;
563 int refilled;
8a578111 564
1fa38c58
LB		 565 /*
566 * Reserve 2+14 bytes for an ethernet header (the hardware
567 * automatically prepends 2 bytes of dummy data to each
568 * received packet), 16 bytes for up to four VLAN tags, and
569 * 4 bytes for the trailing FCS -- 36 bytes total.
570 */
571 skb_size = rxq_to_mp(rxq)->dev->mtu + 36;
d0412d96 572
1fa38c58
LB		 573 /*
574 * Make sure that the skb size is a multiple of 8 bytes, as
575 * the lower three bits of the receive descriptor's buffer
576 * size field are ignored by the hardware.
577 */
578 skb_size = (skb_size + 7) & ~7;
4dfc1c87 579
1fa38c58
LB		 580 refilled = 0;
581 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
582 struct sk_buff *skb;
583 int unaligned;
584 int rx;
d0412d96 585
1fa38c58
LB		 586 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
587 if (skb == NULL) {
588 mp->work_rx_oom |= 1 << rxq->index;
589 goto oom;
590 }
d0412d96 591
1fa38c58
LB		 592 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
593 if (unaligned)
594 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
2257e05c 595
1fa38c58
LB		 596 refilled++;
597 rxq->rx_desc_count++;
c9df406f 598
1fa38c58
LB		 599 rx = rxq->rx_used_desc++;
600 if (rxq->rx_used_desc == rxq->rx_ring_size)
601 rxq->rx_used_desc = 0;
2257e05c 602
1fa38c58
LB		 603 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
604 skb_size, DMA_FROM_DEVICE);
605 rxq->rx_desc_area[rx].buf_size = skb_size;
606 rxq->rx_skb[rx] = skb;
607 wmb();
608 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
609 RX_ENABLE_INTERRUPT;
610 wmb();
2257e05c 611
1fa38c58
LB		 612 /*
613 * The hardware automatically prepends 2 bytes of
614 * dummy data to each received packet, so that the
615 * IP header ends up 16-byte aligned.
616 */
617 skb_reserve(skb, 2);
618 }
619
620 if (refilled < budget)
621 mp->work_rx_refill &= ~(1 << rxq->index);
622
623oom:
624 return refilled;
d0412d96
JC		 625}
626
c9df406f
LB		 627
628/* tx ***********************************************************************/
c9df406f 629static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 630{
13d64285 631 int frag;
1da177e4 632
c9df406f 633 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
13d64285
LB		 634 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
635 if (fragp->size <= 8 && fragp->page_offset & 7)
c9df406f 636 return 1;
1da177e4 637 }
13d64285 638
c9df406f
LB		 639 return 0;
640}
7303fde8 641
13d64285 642static int txq_alloc_desc_index(struct tx_queue *txq)
c9df406f
LB		 643{
644 int tx_desc_curr;
d0412d96 645
13d64285 646 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
1da177e4 647
9da78745
LB		 648 tx_desc_curr = txq->tx_curr_desc++;
649 if (txq->tx_curr_desc == txq->tx_ring_size)
650 txq->tx_curr_desc = 0;
e4d00fa9 651
13d64285 652 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
468d09f8 653
c9df406f
LB		 654 return tx_desc_curr;
655}
468d09f8 656
13d64285 657static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 658{
13d64285 659 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 660 int frag;
1da177e4 661
13d64285
LB		 662 for (frag = 0; frag < nr_frags; frag++) {
663 skb_frag_t *this_frag;
664 int tx_index;
665 struct tx_desc *desc;
666
667 this_frag = &skb_shinfo(skb)->frags[frag];
668 tx_index = txq_alloc_desc_index(txq);
669 desc = &txq->tx_desc_area[tx_index];
670
671 /*
672 * The last fragment will generate an interrupt
673 * which will free the skb on TX completion.
674 */
675 if (frag == nr_frags - 1) {
676 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
677 ZERO_PADDING | TX_LAST_DESC |
678 TX_ENABLE_INTERRUPT;
679 txq->tx_skb[tx_index] = skb;
680 } else {
681 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
682 txq->tx_skb[tx_index] = NULL;
683 }
684
c9df406f
LB		 685 desc->l4i_chk = 0;
686 desc->byte_cnt = this_frag->size;
687 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
688 this_frag->page_offset,
689 this_frag->size,
690 DMA_TO_DEVICE);
691 }
1da177e4
LT		 692}
693
c9df406f
LB		 694static inline __be16 sum16_as_be(__sum16 sum)
695{
696 return (__force __be16)sum;
697}
1da177e4 698
13d64285 699static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 700{
8fa89bf5 701 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 702 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 703 int tx_index;
cc9754b3 704 struct tx_desc *desc;
c9df406f
LB		 705 u32 cmd_sts;
706 int length;
1da177e4 707
cc9754b3 708 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
1da177e4 709
13d64285
LB		 710 tx_index = txq_alloc_desc_index(txq);
711 desc = &txq->tx_desc_area[tx_index];
c9df406f
LB		 712
713 if (nr_frags) {
13d64285 714 txq_submit_frag_skb(txq, skb);
c9df406f
LB		 715
716 length = skb_headlen(skb);
13d64285 717 txq->tx_skb[tx_index] = NULL;
c9df406f 718 } else {
cc9754b3 719 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
c9df406f 720 length = skb->len;
13d64285 721 txq->tx_skb[tx_index] = skb;
c9df406f
LB		 722 }
723
724 desc->byte_cnt = length;
725 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
726
727 if (skb->ip_summed == CHECKSUM_PARTIAL) {
e32b6617
LB		 728 int mac_hdr_len;
729
730 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
731 skb->protocol != htons(ETH_P_8021Q));
c9df406f 732
cc9754b3
LB		 733 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
734 GEN_IP_V4_CHECKSUM |
735 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
c9df406f 736
e32b6617
LB		 737 mac_hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
738 switch (mac_hdr_len - ETH_HLEN) {
739 case 0:
740 break;
741 case 4:
742 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
743 break;
744 case 8:
745 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
746 break;
747 case 12:
748 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
749 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
750 break;
751 default:
752 if (net_ratelimit())
753 dev_printk(KERN_ERR, &txq_to_mp(txq)->dev->dev,
754 "mac header length is %d?!\n", mac_hdr_len);
755 break;
756 }
757
c9df406f
LB		 758 switch (ip_hdr(skb)->protocol) {
759 case IPPROTO_UDP:
cc9754b3 760 cmd_sts |= UDP_FRAME;
c9df406f
LB		 761 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
762 break;
763 case IPPROTO_TCP:
764 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
765 break;
766 default:
767 BUG();
768 }
769 } else {
770 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 771 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 772 desc->l4i_chk = 0;
773 }
774
775 /* ensure all other descriptors are written before first cmd_sts */
776 wmb();
777 desc->cmd_sts = cmd_sts;
778
1fa38c58
LB		 779 /* clear TX_END status */
780 mp->work_tx_end &= ~(1 << txq->index);
8fa89bf5 781
c9df406f
LB		 782 /* ensure all descriptors are written before poking hardware */
783 wmb();
13d64285 784 txq_enable(txq);
c9df406f 785
13d64285 786 txq->tx_desc_count += nr_frags + 1;
1da177e4 787}
1da177e4 788
fc32b0e2 789static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 790{
e5371493 791 struct mv643xx_eth_private *mp = netdev_priv(dev);
e5ef1de1 792 int queue;
13d64285 793 struct tx_queue *txq;
e5ef1de1 794 struct netdev_queue *nq;
e5ef1de1 795 int entries_left;
afdb57a2 796
8fd89211
LB		 797 queue = skb_get_queue_mapping(skb);
798 txq = mp->txq + queue;
799 nq = netdev_get_tx_queue(dev, queue);
800
c9df406f 801 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
8fd89211 802 txq->tx_dropped++;
fc32b0e2
LB		 803 dev_printk(KERN_DEBUG, &dev->dev,
804 "failed to linearize skb with tiny "
805 "unaligned fragment\n");
c9df406f
LB		 806 return NETDEV_TX_BUSY;
807 }
808
17cd0a59 809 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
e5ef1de1
LB		 810 if (net_ratelimit())
811 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
3d6b35bc
LB		 812 kfree_skb(skb);
813 return NETDEV_TX_OK;
c9df406f
LB		 814 }
815
13d64285 816 txq_submit_skb(txq, skb);
8fd89211
LB		 817 txq->tx_bytes += skb->len;
818 txq->tx_packets++;
c9df406f
LB		 819 dev->trans_start = jiffies;
820
e5ef1de1
LB		 821 entries_left = txq->tx_ring_size - txq->tx_desc_count;
822 if (entries_left < MAX_SKB_FRAGS + 1)
823 netif_tx_stop_queue(nq);
c9df406f 824
c9df406f 825 return NETDEV_TX_OK;
1da177e4
LT		 826}
827
c9df406f 828
1fa38c58
LB		 829/* tx napi ******************************************************************/
830static void txq_kick(struct tx_queue *txq)
831{
832 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 833 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 834 u32 hw_desc_ptr;
835 u32 expected_ptr;
836
8fd89211 837 __netif_tx_lock(nq, smp_processor_id());
1fa38c58
LB		 838
839 if (rdl(mp, TXQ_COMMAND(mp->port_num)) & (1 << txq->index))
840 goto out;
841
842 hw_desc_ptr = rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index));
843 expected_ptr = (u32)txq->tx_desc_dma +
844 txq->tx_curr_desc * sizeof(struct tx_desc);
845
846 if (hw_desc_ptr != expected_ptr)
847 txq_enable(txq);
848
849out:
8fd89211 850 __netif_tx_unlock(nq);
1fa38c58
LB		 851
852 mp->work_tx_end &= ~(1 << txq->index);
853}
854
855static int txq_reclaim(struct tx_queue *txq, int budget, int force)
856{
857 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 858 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 859 int reclaimed;
860
8fd89211 861 __netif_tx_lock(nq, smp_processor_id());
1fa38c58
LB		 862
863 reclaimed = 0;
864 while (reclaimed < budget && txq->tx_desc_count > 0) {
865 int tx_index;
866 struct tx_desc *desc;
867 u32 cmd_sts;
868 struct sk_buff *skb;
1fa38c58
LB		 869
870 tx_index = txq->tx_used_desc;
871 desc = &txq->tx_desc_area[tx_index];
872 cmd_sts = desc->cmd_sts;
873
874 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
875 if (!force)
876 break;
877 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
878 }
879
880 txq->tx_used_desc = tx_index + 1;
881 if (txq->tx_used_desc == txq->tx_ring_size)
882 txq->tx_used_desc = 0;
883
884 reclaimed++;
885 txq->tx_desc_count--;
886
1fa38c58
LB		 887 skb = txq->tx_skb[tx_index];
888 txq->tx_skb[tx_index] = NULL;
889
890 if (cmd_sts & ERROR_SUMMARY) {
891 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
892 mp->dev->stats.tx_errors++;
893 }
894
a418950c
LB		 895 if (cmd_sts & TX_FIRST_DESC) {
896 dma_unmap_single(NULL, desc->buf_ptr,
897 desc->byte_cnt, DMA_TO_DEVICE);
898 } else {
899 dma_unmap_page(NULL, desc->buf_ptr,
900 desc->byte_cnt, DMA_TO_DEVICE);
901 }
1fa38c58
LB		 902
903 if (skb)
904 dev_kfree_skb(skb);
1fa38c58
LB		 905 }
906
8fd89211
LB		 907 __netif_tx_unlock(nq);
908
1fa38c58
LB		 909 if (reclaimed < budget)
910 mp->work_tx &= ~(1 << txq->index);
911
1fa38c58
LB		 912 return reclaimed;
913}
914
915
89df5fdc
LB		 916/* tx rate control **********************************************************/
917/*
918 * Set total maximum TX rate (shared by all TX queues for this port)
919 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
920 */
921static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
922{
923 int token_rate;
924 int mtu;
925 int bucket_size;
926
927 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
928 if (token_rate > 1023)
929 token_rate = 1023;
930
931 mtu = (mp->dev->mtu + 255) >> 8;
932 if (mtu > 63)
933 mtu = 63;
934
935 bucket_size = (burst + 255) >> 8;
936 if (bucket_size > 65535)
937 bucket_size = 65535;
938
1e881592
LB		 939 if (mp->shared->tx_bw_control_moved) {
940 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
941 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
942 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
943 } else {
944 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
945 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
946 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
947 }
89df5fdc
LB		 948}
949
950static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
951{
952 struct mv643xx_eth_private *mp = txq_to_mp(txq);
953 int token_rate;
954 int bucket_size;
955
956 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
957 if (token_rate > 1023)
958 token_rate = 1023;
959
960 bucket_size = (burst + 255) >> 8;
961 if (bucket_size > 65535)
962 bucket_size = 65535;
963
3d6b35bc
LB		 964 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
965 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
89df5fdc
LB		 966 (bucket_size << 10) | token_rate);
967}
968
969static void txq_set_fixed_prio_mode(struct tx_queue *txq)
970{
971 struct mv643xx_eth_private *mp = txq_to_mp(txq);
972 int off;
973 u32 val;
974
975 /*
976 * Turn on fixed priority mode.
977 */
1e881592
LB		 978 if (mp->shared->tx_bw_control_moved)
979 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
980 else
981 off = TXQ_FIX_PRIO_CONF(mp->port_num);
89df5fdc
LB		 982
983 val = rdl(mp, off);
3d6b35bc 984 val |= 1 << txq->index;
89df5fdc
LB		 985 wrl(mp, off, val);
986}
987
988static void txq_set_wrr(struct tx_queue *txq, int weight)
989{
990 struct mv643xx_eth_private *mp = txq_to_mp(txq);
991 int off;
992 u32 val;
993
994 /*
995 * Turn off fixed priority mode.
996 */
1e881592
LB		 997 if (mp->shared->tx_bw_control_moved)
998 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
999 else
1000 off = TXQ_FIX_PRIO_CONF(mp->port_num);
89df5fdc
LB		 1001
1002 val = rdl(mp, off);
3d6b35bc 1003 val &= ~(1 << txq->index);
89df5fdc
LB		 1004 wrl(mp, off, val);
1005
1006 /*
1007 * Configure WRR weight for this queue.
1008 */
3d6b35bc 1009 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
89df5fdc
LB		 1010
1011 val = rdl(mp, off);
1012 val = (val & ~0xff) | (weight & 0xff);
1013 wrl(mp, off, val);
1014}
1015
1016
c9df406f 1017/* mii management interface *************************************************/
45c5d3bc
LB		 1018static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1019{
1020 struct mv643xx_eth_shared_private *msp = dev_id;
1021
1022 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1023 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1024 wake_up(&msp->smi_busy_wait);
1025 return IRQ_HANDLED;
1026 }
1027
1028 return IRQ_NONE;
1029}
c9df406f 1030
45c5d3bc 1031static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1da177e4 1032{
45c5d3bc
LB		 1033 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1034}
1da177e4 1035
45c5d3bc
LB		 1036static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1037{
1038 if (msp->err_interrupt == NO_IRQ) {
1039 int i;
c9df406f 1040
45c5d3bc
LB		 1041 for (i = 0; !smi_is_done(msp); i++) {
1042 if (i == 10)
1043 return -ETIMEDOUT;
1044 msleep(10);
c9df406f 1045 }
45c5d3bc
LB		 1046
1047 return 0;
1048 }
1049
1050 if (!wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1051 msecs_to_jiffies(100)))
1052 return -ETIMEDOUT;
1053
1054 return 0;
1055}
1056
1057static int smi_reg_read(struct mv643xx_eth_private *mp,
1058 unsigned int addr, unsigned int reg)
1059{
fc0eb9f2 1060 struct mv643xx_eth_shared_private *msp = mp->shared->smi;
45c5d3bc
LB		 1061 void __iomem *smi_reg = msp->base + SMI_REG;
1062 int ret;
1063
1064 mutex_lock(&msp->phy_lock);
1065
1066 if (smi_wait_ready(msp)) {
1067 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1068 ret = -ETIMEDOUT;
1069 goto out;
1da177e4
LT		 1070 }
1071
fc32b0e2 1072 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 1073
45c5d3bc
LB		 1074 if (smi_wait_ready(msp)) {
1075 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1076 ret = -ETIMEDOUT;
1077 goto out;
1078 }
1079
1080 ret = readl(smi_reg);
1081 if (!(ret & SMI_READ_VALID)) {
1082 printk("%s: SMI bus read not valid\n", mp->dev->name);
1083 ret = -ENODEV;
1084 goto out;
c9df406f
LB		 1085 }
1086
45c5d3bc
LB		 1087 ret &= 0xffff;
1088
c9df406f 1089out:
45c5d3bc
LB		 1090 mutex_unlock(&msp->phy_lock);
1091
1092 return ret;
1da177e4
LT		 1093}
1094
45c5d3bc
LB		 1095static int smi_reg_write(struct mv643xx_eth_private *mp, unsigned int addr,
1096 unsigned int reg, unsigned int value)
1da177e4 1097{
fc0eb9f2 1098 struct mv643xx_eth_shared_private *msp = mp->shared->smi;
45c5d3bc 1099 void __iomem *smi_reg = msp->base + SMI_REG;
1da177e4 1100
45c5d3bc 1101 mutex_lock(&msp->phy_lock);
c9df406f 1102
45c5d3bc
LB		 1103 if (smi_wait_ready(msp)) {
1104 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1105 mutex_unlock(&msp->phy_lock);
1106 return -ETIMEDOUT;
1da177e4
LT		 1107 }
1108
fc32b0e2
LB		 1109 writel(SMI_OPCODE_WRITE | (reg << 21) |
1110 (addr << 16) | (value & 0xffff), smi_reg);
45c5d3bc
LB		 1111
1112 mutex_unlock(&msp->phy_lock);
1113
1114 return 0;
c9df406f 1115}
1da177e4 1116
c9df406f 1117
8fd89211
LB		 1118/* statistics ***************************************************************/
1119static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1120{
1121 struct mv643xx_eth_private *mp = netdev_priv(dev);
1122 struct net_device_stats *stats = &dev->stats;
1123 unsigned long tx_packets = 0;
1124 unsigned long tx_bytes = 0;
1125 unsigned long tx_dropped = 0;
1126 int i;
1127
1128 for (i = 0; i < mp->txq_count; i++) {
1129 struct tx_queue *txq = mp->txq + i;
1130
1131 tx_packets += txq->tx_packets;
1132 tx_bytes += txq->tx_bytes;
1133 tx_dropped += txq->tx_dropped;
1134 }
1135
1136 stats->tx_packets = tx_packets;
1137 stats->tx_bytes = tx_bytes;
1138 stats->tx_dropped = tx_dropped;
1139
1140 return stats;
1141}
1142
fc32b0e2 1143static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 1144{
fc32b0e2 1145 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 1146}
1147
fc32b0e2 1148static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 1149{
fc32b0e2
LB		 1150 int i;
1151
1152 for (i = 0; i < 0x80; i += 4)
1153 mib_read(mp, i);
c9df406f 1154}
d0412d96 1155
fc32b0e2 1156static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 1157{
e5371493 1158 struct mib_counters *p = &mp->mib_counters;
4b8e3655 1159
fc32b0e2
LB		 1160 p->good_octets_received += mib_read(mp, 0x00);
1161 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1162 p->bad_octets_received += mib_read(mp, 0x08);
1163 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1164 p->good_frames_received += mib_read(mp, 0x10);
1165 p->bad_frames_received += mib_read(mp, 0x14);
1166 p->broadcast_frames_received += mib_read(mp, 0x18);
1167 p->multicast_frames_received += mib_read(mp, 0x1c);
1168 p->frames_64_octets += mib_read(mp, 0x20);
1169 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1170 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1171 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1172 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1173 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1174 p->good_octets_sent += mib_read(mp, 0x38);
1175 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1176 p->good_frames_sent += mib_read(mp, 0x40);
1177 p->excessive_collision += mib_read(mp, 0x44);
1178 p->multicast_frames_sent += mib_read(mp, 0x48);
1179 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1180 p->unrec_mac_control_received += mib_read(mp, 0x50);
1181 p->fc_sent += mib_read(mp, 0x54);
1182 p->good_fc_received += mib_read(mp, 0x58);
1183 p->bad_fc_received += mib_read(mp, 0x5c);
1184 p->undersize_received += mib_read(mp, 0x60);
1185 p->fragments_received += mib_read(mp, 0x64);
1186 p->oversize_received += mib_read(mp, 0x68);
1187 p->jabber_received += mib_read(mp, 0x6c);
1188 p->mac_receive_error += mib_read(mp, 0x70);
1189 p->bad_crc_event += mib_read(mp, 0x74);
1190 p->collision += mib_read(mp, 0x78);
1191 p->late_collision += mib_read(mp, 0x7c);
d0412d96
JC		 1192}
1193
c9df406f
LB		 1194
1195/* ethtool ******************************************************************/
e5371493 1196struct mv643xx_eth_stats {
c9df406f
LB		 1197 char stat_string[ETH_GSTRING_LEN];
1198 int sizeof_stat;
16820054
LB		 1199 int netdev_off;
1200 int mp_off;
c9df406f
LB		 1201};
1202
16820054
LB		 1203#define SSTAT(m) \
1204 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1205 offsetof(struct net_device, stats.m), -1 }
1206
1207#define MIBSTAT(m) \
1208 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1209 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1210
1211static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1212 SSTAT(rx_packets),
1213 SSTAT(tx_packets),
1214 SSTAT(rx_bytes),
1215 SSTAT(tx_bytes),
1216 SSTAT(rx_errors),
1217 SSTAT(tx_errors),
1218 SSTAT(rx_dropped),
1219 SSTAT(tx_dropped),
1220 MIBSTAT(good_octets_received),
1221 MIBSTAT(bad_octets_received),
1222 MIBSTAT(internal_mac_transmit_err),
1223 MIBSTAT(good_frames_received),
1224 MIBSTAT(bad_frames_received),
1225 MIBSTAT(broadcast_frames_received),
1226 MIBSTAT(multicast_frames_received),
1227 MIBSTAT(frames_64_octets),
1228 MIBSTAT(frames_65_to_127_octets),
1229 MIBSTAT(frames_128_to_255_octets),
1230 MIBSTAT(frames_256_to_511_octets),
1231 MIBSTAT(frames_512_to_1023_octets),
1232 MIBSTAT(frames_1024_to_max_octets),
1233 MIBSTAT(good_octets_sent),
1234 MIBSTAT(good_frames_sent),
1235 MIBSTAT(excessive_collision),
1236 MIBSTAT(multicast_frames_sent),
1237 MIBSTAT(broadcast_frames_sent),
1238 MIBSTAT(unrec_mac_control_received),
1239 MIBSTAT(fc_sent),
1240 MIBSTAT(good_fc_received),
1241 MIBSTAT(bad_fc_received),
1242 MIBSTAT(undersize_received),
1243 MIBSTAT(fragments_received),
1244 MIBSTAT(oversize_received),
1245 MIBSTAT(jabber_received),
1246 MIBSTAT(mac_receive_error),
1247 MIBSTAT(bad_crc_event),
1248 MIBSTAT(collision),
1249 MIBSTAT(late_collision),
c9df406f
LB		 1250};
1251
e5371493 1252static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
d0412d96 1253{
e5371493 1254 struct mv643xx_eth_private *mp = netdev_priv(dev);
d0412d96
JC		 1255 int err;
1256
d0412d96 1257 err = mii_ethtool_gset(&mp->mii, cmd);
d0412d96 1258
fc32b0e2
LB		 1259 /*
1260 * The MAC does not support 1000baseT_Half.
1261 */
d0412d96
JC		 1262 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1263 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1264
1265 return err;
1266}
1267
bedfe324
LB		 1268static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1269{
81600eea
LB		 1270 struct mv643xx_eth_private *mp = netdev_priv(dev);
1271 u32 port_status;
1272
1273 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1274
bedfe324
LB		 1275 cmd->supported = SUPPORTED_MII;
1276 cmd->advertising = ADVERTISED_MII;
81600eea
LB		 1277 switch (port_status & PORT_SPEED_MASK) {
1278 case PORT_SPEED_10:
1279 cmd->speed = SPEED_10;
1280 break;
1281 case PORT_SPEED_100:
1282 cmd->speed = SPEED_100;
1283 break;
1284 case PORT_SPEED_1000:
1285 cmd->speed = SPEED_1000;
1286 break;
1287 default:
1288 cmd->speed = -1;
1289 break;
1290 }
1291 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
bedfe324
LB		 1292 cmd->port = PORT_MII;
1293 cmd->phy_address = 0;
1294 cmd->transceiver = XCVR_INTERNAL;
1295 cmd->autoneg = AUTONEG_DISABLE;
1296 cmd->maxtxpkt = 1;
1297 cmd->maxrxpkt = 1;
1298
1299 return 0;
1300}
1301
e5371493 1302static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1303{
e5371493 1304 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6 1305
fc32b0e2
LB		 1306 /*
1307 * The MAC does not support 1000baseT_Half.
1308 */
1309 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1310
2b3ba0e3 1311 return mii_ethtool_sset(&mp->mii, cmd);
c9df406f 1312}
1da177e4 1313
bedfe324
LB		 1314static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1315{
1316 return -EINVAL;
1317}
1318
fc32b0e2
LB		 1319static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1320 struct ethtool_drvinfo *drvinfo)
c9df406f 1321{
e5371493
LB		 1322 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1323 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 1324 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 1325 strncpy(drvinfo->bus_info, "platform", 32);
16820054 1326 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1327}
1da177e4 1328
fc32b0e2 1329static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1330{
e5371493 1331 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1332
c9df406f
LB		 1333 return mii_nway_restart(&mp->mii);
1334}
1da177e4 1335
bedfe324
LB		 1336static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1337{
1338 return -EINVAL;
1339}
1340
c9df406f
LB		 1341static u32 mv643xx_eth_get_link(struct net_device *dev)
1342{
e5371493 1343 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1344
c9df406f
LB		 1345 return mii_link_ok(&mp->mii);
1346}
1da177e4 1347
bedfe324
LB		 1348static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1349{
1350 return 1;
1351}
1352
fc32b0e2
LB		 1353static void mv643xx_eth_get_strings(struct net_device *dev,
1354 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1355{
1356 int i;
1da177e4 1357
fc32b0e2
LB		 1358 if (stringset == ETH_SS_STATS) {
1359 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1360 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1361 mv643xx_eth_stats[i].stat_string,
e5371493 1362 ETH_GSTRING_LEN);
c9df406f 1363 }
c9df406f
LB		 1364 }
1365}
1da177e4 1366
fc32b0e2
LB		 1367static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1368 struct ethtool_stats *stats,
1369 uint64_t *data)
c9df406f 1370{
b9873841 1371 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1372 int i;
1da177e4 1373
8fd89211 1374 mv643xx_eth_get_stats(dev);
fc32b0e2 1375 mib_counters_update(mp);
1da177e4 1376
16820054
LB		 1377 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1378 const struct mv643xx_eth_stats *stat;
1379 void *p;
1380
1381 stat = mv643xx_eth_stats + i;
1382
1383 if (stat->netdev_off >= 0)
1384 p = ((void *)mp->dev) + stat->netdev_off;
1385 else
1386 p = ((void *)mp) + stat->mp_off;
1387
1388 data[i] = (stat->sizeof_stat == 8) ?
1389 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1390 }
c9df406f 1391}
1da177e4 1392
fc32b0e2 1393static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1394{
fc32b0e2 1395 if (sset == ETH_SS_STATS)
16820054 1396 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1397
1398 return -EOPNOTSUPP;
c9df406f 1399}
1da177e4 1400
e5371493 1401static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1402 .get_settings = mv643xx_eth_get_settings,
1403 .set_settings = mv643xx_eth_set_settings,
1404 .get_drvinfo = mv643xx_eth_get_drvinfo,
1405 .nway_reset = mv643xx_eth_nway_reset,
1406 .get_link = mv643xx_eth_get_link,
c9df406f 1407 .set_sg = ethtool_op_set_sg,
fc32b0e2
LB		 1408 .get_strings = mv643xx_eth_get_strings,
1409 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
e5371493 1410 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1411};
1da177e4 1412
bedfe324
LB		 1413static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1414 .get_settings = mv643xx_eth_get_settings_phyless,
1415 .set_settings = mv643xx_eth_set_settings_phyless,
1416 .get_drvinfo = mv643xx_eth_get_drvinfo,
1417 .nway_reset = mv643xx_eth_nway_reset_phyless,
1418 .get_link = mv643xx_eth_get_link_phyless,
1419 .set_sg = ethtool_op_set_sg,
1420 .get_strings = mv643xx_eth_get_strings,
1421 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1422 .get_sset_count = mv643xx_eth_get_sset_count,
1423};
1424
bea3348e 1425
c9df406f 1426/* address handling *********************************************************/
5daffe94 1427static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1428{
c9df406f
LB		 1429 unsigned int mac_h;
1430 unsigned int mac_l;
1da177e4 1431
fc32b0e2
LB		 1432 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1433 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1da177e4 1434
5daffe94
LB		 1435 addr[0] = (mac_h >> 24) & 0xff;
1436 addr[1] = (mac_h >> 16) & 0xff;
1437 addr[2] = (mac_h >> 8) & 0xff;
1438 addr[3] = mac_h & 0xff;
1439 addr[4] = (mac_l >> 8) & 0xff;
1440 addr[5] = mac_l & 0xff;
c9df406f 1441}
1da177e4 1442
e5371493 1443static void init_mac_tables(struct mv643xx_eth_private *mp)
c9df406f 1444{
fc32b0e2 1445 int i;
1da177e4 1446
fc32b0e2
LB		 1447 for (i = 0; i < 0x100; i += 4) {
1448 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1449 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
c9df406f 1450 }
fc32b0e2
LB		 1451
1452 for (i = 0; i < 0x10; i += 4)
1453 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
c9df406f 1454}
d0412d96 1455
e5371493 1456static void set_filter_table_entry(struct mv643xx_eth_private *mp,
fc32b0e2 1457 int table, unsigned char entry)
c9df406f
LB		 1458{
1459 unsigned int table_reg;
ab4384a6 1460
c9df406f 1461 /* Set "accepts frame bit" at specified table entry */
fc32b0e2
LB		 1462 table_reg = rdl(mp, table + (entry & 0xfc));
1463 table_reg |= 0x01 << (8 * (entry & 3));
1464 wrl(mp, table + (entry & 0xfc), table_reg);
1da177e4
LT		 1465}
1466
5daffe94 1467static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1da177e4 1468{
c9df406f
LB		 1469 unsigned int mac_h;
1470 unsigned int mac_l;
1471 int table;
1da177e4 1472
fc32b0e2
LB		 1473 mac_l = (addr[4] << 8) | addr[5];
1474 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
ff561eef 1475
fc32b0e2
LB		 1476 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1477 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1da177e4 1478
fc32b0e2 1479 table = UNICAST_TABLE(mp->port_num);
5daffe94 1480 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1da177e4
LT		 1481}
1482
fc32b0e2 1483static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1da177e4 1484{
e5371493 1485 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1486
fc32b0e2
LB		 1487 /* +2 is for the offset of the HW addr type */
1488 memcpy(dev->dev_addr, addr + 2, 6);
1489
cc9754b3
LB		 1490 init_mac_tables(mp);
1491 uc_addr_set(mp, dev->dev_addr);
1da177e4
LT		 1492
1493 return 0;
1494}
1495
69876569
LB		 1496static int addr_crc(unsigned char *addr)
1497{
1498 int crc = 0;
1499 int i;
1500
1501 for (i = 0; i < 6; i++) {
1502 int j;
1503
1504 crc = (crc ^ addr[i]) << 8;
1505 for (j = 7; j >= 0; j--) {
1506 if (crc & (0x100 << j))
1507 crc ^= 0x107 << j;
1508 }
1509 }
1510
1511 return crc;
1512}
1513
fc32b0e2 1514static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1da177e4 1515{
fc32b0e2
LB		 1516 struct mv643xx_eth_private *mp = netdev_priv(dev);
1517 u32 port_config;
1518 struct dev_addr_list *addr;
1519 int i;
c8aaea25 1520
fc32b0e2
LB		 1521 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1522 if (dev->flags & IFF_PROMISC)
1523 port_config |= UNICAST_PROMISCUOUS_MODE;
1524 else
1525 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1526 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1da177e4 1527
fc32b0e2
LB		 1528 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1529 int port_num = mp->port_num;
1530 u32 accept = 0x01010101;
c8aaea25 1531
fc32b0e2
LB		 1532 for (i = 0; i < 0x100; i += 4) {
1533 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1534 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1535 }
1536 return;
1537 }
c8aaea25 1538
fc32b0e2
LB		 1539 for (i = 0; i < 0x100; i += 4) {
1540 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1541 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1da177e4
LT		 1542 }
1543
fc32b0e2
LB		 1544 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1545 u8 *a = addr->da_addr;
1546 int table;
324ff2c1 1547
fc32b0e2
LB		 1548 if (addr->da_addrlen != 6)
1549 continue;
1da177e4 1550
fc32b0e2
LB		 1551 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1552 table = SPECIAL_MCAST_TABLE(mp->port_num);
1553 set_filter_table_entry(mp, table, a[5]);
1554 } else {
1555 int crc = addr_crc(a);
1da177e4 1556
fc32b0e2
LB		 1557 table = OTHER_MCAST_TABLE(mp->port_num);
1558 set_filter_table_entry(mp, table, crc);
1559 }
1560 }
c9df406f 1561}
c8aaea25 1562
c8aaea25 1563
c9df406f 1564/* rx/tx queue initialisation ***********************************************/
64da80a2 1565static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1566{
64da80a2 1567 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1568 struct rx_desc *rx_desc;
1569 int size;
c9df406f
LB		 1570 int i;
1571
64da80a2
LB		 1572 rxq->index = index;
1573
8a578111
LB		 1574 rxq->rx_ring_size = mp->default_rx_ring_size;
1575
1576 rxq->rx_desc_count = 0;
1577 rxq->rx_curr_desc = 0;
1578 rxq->rx_used_desc = 0;
1579
1580 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1581
f7981c1c 1582 if (index == 0 && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1583 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1584 mp->rx_desc_sram_size);
1585 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1586 } else {
1587 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1588 &rxq->rx_desc_dma,
1589 GFP_KERNEL);
f7ea3337
PJ		 1590 }
1591
8a578111
LB		 1592 if (rxq->rx_desc_area == NULL) {
1593 dev_printk(KERN_ERR, &mp->dev->dev,
1594 "can't allocate rx ring (%d bytes)\n", size);
1595 goto out;
1596 }
1597 memset(rxq->rx_desc_area, 0, size);
1da177e4 1598
8a578111
LB		 1599 rxq->rx_desc_area_size = size;
1600 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1601 GFP_KERNEL);
1602 if (rxq->rx_skb == NULL) {
1603 dev_printk(KERN_ERR, &mp->dev->dev,
1604 "can't allocate rx skb ring\n");
1605 goto out_free;
1606 }
1607
1608 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1609 for (i = 0; i < rxq->rx_ring_size; i++) {
9da78745
LB		 1610 int nexti;
1611
1612 nexti = i + 1;
1613 if (nexti == rxq->rx_ring_size)
1614 nexti = 0;
1615
8a578111
LB		 1616 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1617 nexti * sizeof(struct rx_desc);
1618 }
1619
8a578111
LB		 1620 return 0;
1621
1622
1623out_free:
f7981c1c 1624 if (index == 0 && size <= mp->rx_desc_sram_size)
8a578111
LB		 1625 iounmap(rxq->rx_desc_area);
1626 else
1627 dma_free_coherent(NULL, size,
1628 rxq->rx_desc_area,
1629 rxq->rx_desc_dma);
1630
1631out:
1632 return -ENOMEM;
c9df406f 1633}
c8aaea25 1634
8a578111 1635static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1636{
8a578111
LB		 1637 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1638 int i;
1639
1640 rxq_disable(rxq);
c8aaea25 1641
8a578111
LB		 1642 for (i = 0; i < rxq->rx_ring_size; i++) {
1643 if (rxq->rx_skb[i]) {
1644 dev_kfree_skb(rxq->rx_skb[i]);
1645 rxq->rx_desc_count--;
1da177e4 1646 }
c8aaea25 1647 }
1da177e4 1648
8a578111
LB		 1649 if (rxq->rx_desc_count) {
1650 dev_printk(KERN_ERR, &mp->dev->dev,
1651 "error freeing rx ring -- %d skbs stuck\n",
1652 rxq->rx_desc_count);
1653 }
1654
f7981c1c 1655 if (rxq->index == 0 &&
64da80a2 1656 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1657 iounmap(rxq->rx_desc_area);
c9df406f 1658 else
8a578111
LB		 1659 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1660 rxq->rx_desc_area, rxq->rx_desc_dma);
1661
1662 kfree(rxq->rx_skb);
c9df406f 1663}
1da177e4 1664
3d6b35bc 1665static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1666{
3d6b35bc 1667 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1668 struct tx_desc *tx_desc;
1669 int size;
c9df406f 1670 int i;
1da177e4 1671
3d6b35bc
LB		 1672 txq->index = index;
1673
13d64285
LB		 1674 txq->tx_ring_size = mp->default_tx_ring_size;
1675
1676 txq->tx_desc_count = 0;
1677 txq->tx_curr_desc = 0;
1678 txq->tx_used_desc = 0;
1679
1680 size = txq->tx_ring_size * sizeof(struct tx_desc);
1681
f7981c1c 1682 if (index == 0 && size <= mp->tx_desc_sram_size) {
13d64285
LB		 1683 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1684 mp->tx_desc_sram_size);
1685 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1686 } else {
1687 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1688 &txq->tx_desc_dma,
1689 GFP_KERNEL);
1690 }
1691
1692 if (txq->tx_desc_area == NULL) {
1693 dev_printk(KERN_ERR, &mp->dev->dev,
1694 "can't allocate tx ring (%d bytes)\n", size);
1695 goto out;
c9df406f 1696 }
13d64285
LB		 1697 memset(txq->tx_desc_area, 0, size);
1698
1699 txq->tx_desc_area_size = size;
1700 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1701 GFP_KERNEL);
1702 if (txq->tx_skb == NULL) {
1703 dev_printk(KERN_ERR, &mp->dev->dev,
1704 "can't allocate tx skb ring\n");
1705 goto out_free;
1706 }
1707
1708 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1709 for (i = 0; i < txq->tx_ring_size; i++) {
6b368f68 1710 struct tx_desc *txd = tx_desc + i;
9da78745
LB		 1711 int nexti;
1712
1713 nexti = i + 1;
1714 if (nexti == txq->tx_ring_size)
1715 nexti = 0;
6b368f68
LB		 1716
1717 txd->cmd_sts = 0;
1718 txd->next_desc_ptr = txq->tx_desc_dma +
13d64285
LB		 1719 nexti * sizeof(struct tx_desc);
1720 }
1721
1722 return 0;
1723
13d64285 1724out_free:
f7981c1c 1725 if (index == 0 && size <= mp->tx_desc_sram_size)
13d64285
LB		 1726 iounmap(txq->tx_desc_area);
1727 else
1728 dma_free_coherent(NULL, size,
1729 txq->tx_desc_area,
1730 txq->tx_desc_dma);
c9df406f 1731
13d64285
LB		 1732out:
1733 return -ENOMEM;
c8aaea25 1734}
1da177e4 1735
13d64285 1736static void txq_deinit(struct tx_queue *txq)
c9df406f 1737{
13d64285 1738 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 1739
13d64285 1740 txq_disable(txq);
1fa38c58 1741 txq_reclaim(txq, txq->tx_ring_size, 1);
1da177e4 1742
13d64285 1743 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 1744
f7981c1c 1745 if (txq->index == 0 &&
3d6b35bc 1746 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 1747 iounmap(txq->tx_desc_area);
c9df406f 1748 else
13d64285
LB		 1749 dma_free_coherent(NULL, txq->tx_desc_area_size,
1750 txq->tx_desc_area, txq->tx_desc_dma);
1751
1752 kfree(txq->tx_skb);
c9df406f 1753}
1da177e4 1754
1da177e4 1755
c9df406f 1756/* netdev ops and related ***************************************************/
1fa38c58
LB		 1757static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1758{
1759 u32 int_cause;
1760 u32 int_cause_ext;
1761
1762 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1763 (INT_TX_END | INT_RX | INT_EXT);
1764 if (int_cause == 0)
1765 return 0;
1766
1767 int_cause_ext = 0;
1768 if (int_cause & INT_EXT)
1769 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num));
1770
1771 int_cause &= INT_TX_END | INT_RX;
1772 if (int_cause) {
1773 wrl(mp, INT_CAUSE(mp->port_num), ~int_cause);
1774 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
1775 ~(rdl(mp, TXQ_COMMAND(mp->port_num)) & 0xff);
1776 mp->work_rx |= (int_cause & INT_RX) >> 2;
1777 }
1778
1779 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
1780 if (int_cause_ext) {
1781 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1782 if (int_cause_ext & INT_EXT_LINK_PHY)
1783 mp->work_link = 1;
1784 mp->work_tx |= int_cause_ext & INT_EXT_TX;
1785 }
1786
1787 return 1;
1788}
1789
1790static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1791{
1792 struct net_device *dev = (struct net_device *)dev_id;
1793 struct mv643xx_eth_private *mp = netdev_priv(dev);
1794
1795 if (unlikely(!mv643xx_eth_collect_events(mp)))
1796 return IRQ_NONE;
1797
1798 wrl(mp, INT_MASK(mp->port_num), 0);
1799 napi_schedule(&mp->napi);
1800
1801 return IRQ_HANDLED;
1802}
1803
2f7eb47a
LB		 1804static void handle_link_event(struct mv643xx_eth_private *mp)
1805{
1806 struct net_device *dev = mp->dev;
1807 u32 port_status;
1808 int speed;
1809 int duplex;
1810 int fc;
1811
1812 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1813 if (!(port_status & LINK_UP)) {
1814 if (netif_carrier_ok(dev)) {
1815 int i;
1816
1817 printk(KERN_INFO "%s: link down\n", dev->name);
1818
1819 netif_carrier_off(dev);
2f7eb47a 1820
f7981c1c 1821 for (i = 0; i < mp->txq_count; i++) {
2f7eb47a
LB		 1822 struct tx_queue *txq = mp->txq + i;
1823
1fa38c58 1824 txq_reclaim(txq, txq->tx_ring_size, 1);
f7981c1c 1825 txq_reset_hw_ptr(txq);
2f7eb47a
LB		 1826 }
1827 }
1828 return;
1829 }
1830
1831 switch (port_status & PORT_SPEED_MASK) {
1832 case PORT_SPEED_10:
1833 speed = 10;
1834 break;
1835 case PORT_SPEED_100:
1836 speed = 100;
1837 break;
1838 case PORT_SPEED_1000:
1839 speed = 1000;
1840 break;
1841 default:
1842 speed = -1;
1843 break;
1844 }
1845 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1846 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1847
1848 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1849 "flow control %sabled\n", dev->name,
1850 speed, duplex ? "full" : "half",
1851 fc ? "en" : "dis");
1852
4fdeca3f 1853 if (!netif_carrier_ok(dev))
2f7eb47a 1854 netif_carrier_on(dev);
2f7eb47a
LB		 1855}
1856
1fa38c58 1857static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
c9df406f 1858{
1fa38c58
LB		 1859 struct mv643xx_eth_private *mp;
1860 int work_done;
ce4e2e45 1861
1fa38c58 1862 mp = container_of(napi, struct mv643xx_eth_private, napi);
fc32b0e2 1863
1fa38c58
LB		 1864 mp->work_rx_refill |= mp->work_rx_oom;
1865 mp->work_rx_oom = 0;
1da177e4 1866
1fa38c58
LB		 1867 work_done = 0;
1868 while (work_done < budget) {
1869 u8 queue_mask;
1870 int queue;
1871 int work_tbd;
1872
1873 if (mp->work_link) {
1874 mp->work_link = 0;
1875 handle_link_event(mp);
1876 continue;
1877 }
1da177e4 1878
1fa38c58
LB		 1879 queue_mask = mp->work_tx | mp->work_tx_end |
1880 mp->work_rx | mp->work_rx_refill;
1881 if (!queue_mask) {
1882 if (mv643xx_eth_collect_events(mp))
1883 continue;
1884 break;
1885 }
1da177e4 1886
1fa38c58
LB		 1887 queue = fls(queue_mask) - 1;
1888 queue_mask = 1 << queue;
1889
1890 work_tbd = budget - work_done;
1891 if (work_tbd > 16)
1892 work_tbd = 16;
1893
1894 if (mp->work_tx_end & queue_mask) {
1895 txq_kick(mp->txq + queue);
1896 } else if (mp->work_tx & queue_mask) {
1897 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
1898 txq_maybe_wake(mp->txq + queue);
1899 } else if (mp->work_rx & queue_mask) {
1900 work_done += rxq_process(mp->rxq + queue, work_tbd);
1901 } else if (mp->work_rx_refill & queue_mask) {
1902 work_done += rxq_refill(mp->rxq + queue, work_tbd);
1903 } else {
1904 BUG();
1905 }
84dd619e 1906 }
fc32b0e2 1907
1fa38c58
LB		 1908 if (work_done < budget) {
1909 if (mp->work_rx_oom)
1910 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
1911 napi_complete(napi);
1912 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
226bb6b7 1913 }
3d6b35bc 1914
1fa38c58
LB		 1915 return work_done;
1916}
8fa89bf5 1917
1fa38c58
LB		 1918static inline void oom_timer_wrapper(unsigned long data)
1919{
1920 struct mv643xx_eth_private *mp = (void *)data;
1da177e4 1921
1fa38c58 1922 napi_schedule(&mp->napi);
1da177e4
LT		 1923}
1924
e5371493 1925static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 1926{
45c5d3bc
LB		 1927 int data;
1928
1929 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1930 if (data < 0)
1931 return;
1da177e4 1932
7f106c1d 1933 data |= BMCR_RESET;
45c5d3bc
LB		 1934 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data) < 0)
1935 return;
1da177e4 1936
c9df406f 1937 do {
45c5d3bc
LB		 1938 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1939 } while (data >= 0 && data & BMCR_RESET);
1da177e4
LT		 1940}
1941
fc32b0e2 1942static void port_start(struct mv643xx_eth_private *mp)
1da177e4 1943{
d0412d96 1944 u32 pscr;
8a578111 1945 int i;
1da177e4 1946
bedfe324
LB		 1947 /*
1948 * Perform PHY reset, if there is a PHY.
1949 */
1950 if (mp->phy_addr != -1) {
1951 struct ethtool_cmd cmd;
1952
1953 mv643xx_eth_get_settings(mp->dev, &cmd);
1954 phy_reset(mp);
1955 mv643xx_eth_set_settings(mp->dev, &cmd);
1956 }
1da177e4 1957
81600eea
LB		 1958 /*
1959 * Configure basic link parameters.
1960 */
1961 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1962
1963 pscr |= SERIAL_PORT_ENABLE;
1964 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1965
1966 pscr |= DO_NOT_FORCE_LINK_FAIL;
1967 if (mp->phy_addr == -1)
1968 pscr |= FORCE_LINK_PASS;
1969 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1970
1971 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1972
13d64285
LB		 1973 /*
1974 * Configure TX path and queues.
1975 */
89df5fdc 1976 tx_set_rate(mp, 1000000000, 16777216);
f7981c1c 1977 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc 1978 struct tx_queue *txq = mp->txq + i;
13d64285 1979
6b368f68 1980 txq_reset_hw_ptr(txq);
89df5fdc
LB		 1981 txq_set_rate(txq, 1000000000, 16777216);
1982 txq_set_fixed_prio_mode(txq);
13d64285
LB		 1983 }
1984
fc32b0e2
LB		 1985 /*
1986 * Add configured unicast address to address filter table.
1987 */
1988 uc_addr_set(mp, mp->dev->dev_addr);
1da177e4 1989
d9a073ea
LB		 1990 /*
1991 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1992 * frames to RX queue #0.
1993 */
8a578111 1994 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
01999873 1995
376489a2
LB		 1996 /*
1997 * Treat BPDUs as normal multicasts, and disable partition mode.
1998 */
8a578111 1999 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
01999873 2000
8a578111 2001 /*
64da80a2 2002 * Enable the receive queues.
8a578111 2003 */
f7981c1c 2004 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 2005 struct rx_queue *rxq = mp->rxq + i;
2006 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
8a578111 2007 u32 addr;
1da177e4 2008
8a578111
LB		 2009 addr = (u32)rxq->rx_desc_dma;
2010 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2011 wrl(mp, off, addr);
1da177e4 2012
8a578111
LB		 2013 rxq_enable(rxq);
2014 }
1da177e4
LT		 2015}
2016
ffd86bbe 2017static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 2018{
c9df406f 2019 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
773fc3ee 2020 u32 val;
1da177e4 2021
773fc3ee
LB		 2022 val = rdl(mp, SDMA_CONFIG(mp->port_num));
2023 if (mp->shared->extended_rx_coal_limit) {
2024 if (coal > 0xffff)
2025 coal = 0xffff;
2026 val &= ~0x023fff80;
2027 val |= (coal & 0x8000) << 10;
2028 val |= (coal & 0x7fff) << 7;
2029 } else {
2030 if (coal > 0x3fff)
2031 coal = 0x3fff;
2032 val &= ~0x003fff00;
2033 val |= (coal & 0x3fff) << 8;
2034 }
2035 wrl(mp, SDMA_CONFIG(mp->port_num), val);
1da177e4
LT		 2036}
2037
ffd86bbe 2038static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 2039{
c9df406f 2040 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 2041
fc32b0e2
LB		 2042 if (coal > 0x3fff)
2043 coal = 0x3fff;
2044 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
16e03018
DF		 2045}
2046
c9df406f 2047static int mv643xx_eth_open(struct net_device *dev)
16e03018 2048{
e5371493 2049 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2050 int err;
64da80a2 2051 int i;
16e03018 2052
fc32b0e2
LB		 2053 wrl(mp, INT_CAUSE(mp->port_num), 0);
2054 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
2055 rdl(mp, INT_CAUSE_EXT(mp->port_num));
c9df406f 2056
fc32b0e2 2057 err = request_irq(dev->irq, mv643xx_eth_irq,
2a1867a7 2058 IRQF_SHARED, dev->name, dev);
c9df406f 2059 if (err) {
fc32b0e2 2060 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
c9df406f 2061 return -EAGAIN;
16e03018
DF		 2062 }
2063
fc32b0e2 2064 init_mac_tables(mp);
16e03018 2065
2257e05c
LB		 2066 napi_enable(&mp->napi);
2067
f7981c1c 2068 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 2069 err = rxq_init(mp, i);
2070 if (err) {
2071 while (--i >= 0)
f7981c1c 2072 rxq_deinit(mp->rxq + i);
64da80a2
LB		 2073 goto out;
2074 }
2075
1fa38c58 2076 rxq_refill(mp->rxq + i, INT_MAX);
2257e05c
LB		 2077 }
2078
1fa38c58 2079 if (mp->work_rx_oom) {
2257e05c
LB		 2080 mp->rx_oom.expires = jiffies + (HZ / 10);
2081 add_timer(&mp->rx_oom);
64da80a2 2082 }
8a578111 2083
f7981c1c 2084 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc
LB		 2085 err = txq_init(mp, i);
2086 if (err) {
2087 while (--i >= 0)
f7981c1c 2088 txq_deinit(mp->txq + i);
3d6b35bc
LB		 2089 goto out_free;
2090 }
2091 }
16e03018 2092
2f7eb47a 2093 netif_carrier_off(dev);
2f7eb47a 2094
fc32b0e2 2095 port_start(mp);
16e03018 2096
ffd86bbe
LB		 2097 set_rx_coal(mp, 0);
2098 set_tx_coal(mp, 0);
16e03018 2099
befefe21 2100 wrl(mp, INT_MASK_EXT(mp->port_num), INT_EXT_LINK_PHY | INT_EXT_TX);
226bb6b7 2101 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
16e03018 2102
c9df406f
LB		 2103 return 0;
2104
13d64285 2105
fc32b0e2 2106out_free:
f7981c1c
LB		 2107 for (i = 0; i < mp->rxq_count; i++)
2108 rxq_deinit(mp->rxq + i);
fc32b0e2 2109out:
c9df406f
LB		 2110 free_irq(dev->irq, dev);
2111
2112 return err;
16e03018
DF		 2113}
2114
e5371493 2115static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 2116{
fc32b0e2 2117 unsigned int data;
64da80a2 2118 int i;
1da177e4 2119
f7981c1c
LB		 2120 for (i = 0; i < mp->rxq_count; i++)
2121 rxq_disable(mp->rxq + i);
2122 for (i = 0; i < mp->txq_count; i++)
2123 txq_disable(mp->txq + i);
ae9ae064
LB		 2124
2125 while (1) {
2126 u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
2127
2128 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2129 break;
13d64285 2130 udelay(10);
ae9ae064 2131 }
1da177e4 2132
c9df406f 2133 /* Reset the Enable bit in the Configuration Register */
fc32b0e2
LB		 2134 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2135 data &= ~(SERIAL_PORT_ENABLE |
2136 DO_NOT_FORCE_LINK_FAIL |
2137 FORCE_LINK_PASS);
2138 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
1da177e4
LT		 2139}
2140
c9df406f 2141static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 2142{
e5371493 2143 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 2144 int i;
1da177e4 2145
fc32b0e2
LB		 2146 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2147 rdl(mp, INT_MASK(mp->port_num));
1da177e4 2148
c9df406f 2149 napi_disable(&mp->napi);
78fff83b 2150
2257e05c
LB		 2151 del_timer_sync(&mp->rx_oom);
2152
c9df406f 2153 netif_carrier_off(dev);
1da177e4 2154
fc32b0e2
LB		 2155 free_irq(dev->irq, dev);
2156
cc9754b3 2157 port_reset(mp);
8fd89211 2158 mv643xx_eth_get_stats(dev);
fc32b0e2 2159 mib_counters_update(mp);
1da177e4 2160
f7981c1c
LB		 2161 for (i = 0; i < mp->rxq_count; i++)
2162 rxq_deinit(mp->rxq + i);
2163 for (i = 0; i < mp->txq_count; i++)
2164 txq_deinit(mp->txq + i);
1da177e4 2165
c9df406f 2166 return 0;
1da177e4
LT		 2167}
2168
fc32b0e2 2169static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 2170{
e5371493 2171 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2172
bedfe324
LB		 2173 if (mp->phy_addr != -1)
2174 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2175
2176 return -EOPNOTSUPP;
1da177e4
LT		 2177}
2178
c9df406f 2179static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 2180{
89df5fdc
LB		 2181 struct mv643xx_eth_private *mp = netdev_priv(dev);
2182
fc32b0e2 2183 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 2184 return -EINVAL;
1da177e4 2185
c9df406f 2186 dev->mtu = new_mtu;
89df5fdc
LB		 2187 tx_set_rate(mp, 1000000000, 16777216);
2188
c9df406f
LB		 2189 if (!netif_running(dev))
2190 return 0;
1da177e4 2191
c9df406f
LB		 2192 /*
2193 * Stop and then re-open the interface. This will allocate RX
2194 * skbs of the new MTU.
2195 * There is a possible danger that the open will not succeed,
fc32b0e2 2196 * due to memory being full.
c9df406f
LB		 2197 */
2198 mv643xx_eth_stop(dev);
2199 if (mv643xx_eth_open(dev)) {
fc32b0e2
LB		 2200 dev_printk(KERN_ERR, &dev->dev,
2201 "fatal error on re-opening device after "
2202 "MTU change\n");
c9df406f
LB		 2203 }
2204
2205 return 0;
1da177e4
LT		 2206}
2207
fc32b0e2 2208static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2209{
fc32b0e2 2210 struct mv643xx_eth_private *mp;
1da177e4 2211
fc32b0e2
LB		 2212 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2213 if (netif_running(mp->dev)) {
e5ef1de1 2214 netif_tx_stop_all_queues(mp->dev);
fc32b0e2
LB		 2215 port_reset(mp);
2216 port_start(mp);
e5ef1de1 2217 netif_tx_wake_all_queues(mp->dev);
fc32b0e2 2218 }
c9df406f
LB		 2219}
2220
c9df406f 2221static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2222{
e5371493 2223 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2224
fc32b0e2 2225 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
d0412d96 2226
c9df406f 2227 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2228}
2229
c9df406f 2230#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2231static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2232{
fc32b0e2 2233 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2234
fc32b0e2
LB		 2235 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2236 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2237
fc32b0e2 2238 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2239
f2ca60f2 2240 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
9f8dd319 2241}
c9df406f 2242#endif
9f8dd319 2243
fc32b0e2 2244static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
9f8dd319 2245{
e5371493 2246 struct mv643xx_eth_private *mp = netdev_priv(dev);
45c5d3bc 2247 return smi_reg_read(mp, addr, reg);
9f8dd319
DF		 2248}
2249
fc32b0e2 2250static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
9f8dd319 2251{
e5371493 2252 struct mv643xx_eth_private *mp = netdev_priv(dev);
fc32b0e2 2253 smi_reg_write(mp, addr, reg, val);
c9df406f 2254}
9f8dd319 2255
9f8dd319 2256
c9df406f 2257/* platform glue ************************************************************/
e5371493
LB		 2258static void
2259mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2260 struct mbus_dram_target_info *dram)
c9df406f 2261{
cc9754b3 2262 void __iomem *base = msp->base;
c9df406f
LB		 2263 u32 win_enable;
2264 u32 win_protect;
2265 int i;
9f8dd319 2266
c9df406f
LB		 2267 for (i = 0; i < 6; i++) {
2268 writel(0, base + WINDOW_BASE(i));
2269 writel(0, base + WINDOW_SIZE(i));
2270 if (i < 4)
2271 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2272 }
2273
c9df406f
LB		 2274 win_enable = 0x3f;
2275 win_protect = 0;
2276
2277 for (i = 0; i < dram->num_cs; i++) {
2278 struct mbus_dram_window *cs = dram->cs + i;
2279
2280 writel((cs->base & 0xffff0000) |
2281 (cs->mbus_attr << 8) |
2282 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2283 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2284
2285 win_enable &= ~(1 << i);
2286 win_protect |= 3 << (2 * i);
2287 }
2288
2289 writel(win_enable, base + WINDOW_BAR_ENABLE);
2290 msp->win_protect = win_protect;
9f8dd319
DF		 2291}
2292
773fc3ee
LB		 2293static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2294{
2295 /*
2296 * Check whether we have a 14-bit coal limit field in bits
2297 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2298 * SDMA config register.
2299 */
2300 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2301 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2302 msp->extended_rx_coal_limit = 1;
2303 else
2304 msp->extended_rx_coal_limit = 0;
1e881592
LB		 2305
2306 /*
2307 * Check whether the TX rate control registers are in the
2308 * old or the new place.
2309 */
2310 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2311 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
2312 msp->tx_bw_control_moved = 1;
2313 else
2314 msp->tx_bw_control_moved = 0;
773fc3ee
LB		 2315}
2316
c9df406f 2317static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2318{
e5371493 2319 static int mv643xx_eth_version_printed = 0;
c9df406f 2320 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2321 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 2322 struct resource *res;
2323 int ret;
9f8dd319 2324
e5371493 2325 if (!mv643xx_eth_version_printed++)
7dde154d
LB		 2326 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2327 "driver version %s\n", mv643xx_eth_driver_version);
9f8dd319 2328
c9df406f
LB		 2329 ret = -EINVAL;
2330 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2331 if (res == NULL)
2332 goto out;
9f8dd319 2333
c9df406f
LB		 2334 ret = -ENOMEM;
2335 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2336 if (msp == NULL)
2337 goto out;
2338 memset(msp, 0, sizeof(*msp));
2339
cc9754b3
LB		 2340 msp->base = ioremap(res->start, res->end - res->start + 1);
2341 if (msp->base == NULL)
c9df406f
LB		 2342 goto out_free;
2343
fc0eb9f2
LB		 2344 msp->smi = msp;
2345 if (pd != NULL && pd->shared_smi != NULL)
2346 msp->smi = platform_get_drvdata(pd->shared_smi);
2347
2b3ba0e3 2348 mutex_init(&msp->phy_lock);
c9df406f 2349
45c5d3bc
LB		 2350 msp->err_interrupt = NO_IRQ;
2351 init_waitqueue_head(&msp->smi_busy_wait);
2352
2353 /*
2354 * Check whether the error interrupt is hooked up.
2355 */
2356 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2357 if (res != NULL) {
2358 int err;
2359
2360 err = request_irq(res->start, mv643xx_eth_err_irq,
2361 IRQF_SHARED, "mv643xx_eth", msp);
2362 if (!err) {
2363 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2364 msp->err_interrupt = res->start;
2365 }
2366 }
2367
c9df406f
LB		 2368 /*
2369 * (Re-)program MBUS remapping windows if we are asked to.
2370 */
2371 if (pd != NULL && pd->dram != NULL)
2372 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2373
fc32b0e2
LB		 2374 /*
2375 * Detect hardware parameters.
2376 */
2377 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
773fc3ee 2378 infer_hw_params(msp);
fc32b0e2
LB		 2379
2380 platform_set_drvdata(pdev, msp);
2381
c9df406f
LB		 2382 return 0;
2383
2384out_free:
2385 kfree(msp);
2386out:
2387 return ret;
2388}
2389
2390static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2391{
e5371493 2392 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
c9df406f 2393
45c5d3bc
LB		 2394 if (msp->err_interrupt != NO_IRQ)
2395 free_irq(msp->err_interrupt, msp);
cc9754b3 2396 iounmap(msp->base);
c9df406f
LB		 2397 kfree(msp);
2398
2399 return 0;
9f8dd319
DF		 2400}
2401
c9df406f 2402static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2403 .probe = mv643xx_eth_shared_probe,
2404 .remove = mv643xx_eth_shared_remove,
c9df406f 2405 .driver = {
fc32b0e2 2406 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2407 .owner = THIS_MODULE,
2408 },
2409};
2410
e5371493 2411static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2412{
c9df406f 2413 int addr_shift = 5 * mp->port_num;
fc32b0e2 2414 u32 data;
1da177e4 2415
fc32b0e2
LB		 2416 data = rdl(mp, PHY_ADDR);
2417 data &= ~(0x1f << addr_shift);
2418 data |= (phy_addr & 0x1f) << addr_shift;
2419 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2420}
2421
e5371493 2422static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2423{
fc32b0e2
LB		 2424 unsigned int data;
2425
2426 data = rdl(mp, PHY_ADDR);
2427
2428 return (data >> (5 * mp->port_num)) & 0x1f;
2429}
2430
2431static void set_params(struct mv643xx_eth_private *mp,
2432 struct mv643xx_eth_platform_data *pd)
2433{
2434 struct net_device *dev = mp->dev;
2435
2436 if (is_valid_ether_addr(pd->mac_addr))
2437 memcpy(dev->dev_addr, pd->mac_addr, 6);
2438 else
2439 uc_addr_get(mp, dev->dev_addr);
2440
ac840605 2441 if (pd->phy_addr == MV643XX_ETH_PHY_NONE) {
fc32b0e2
LB		 2442 mp->phy_addr = -1;
2443 } else {
ac840605 2444 if (pd->phy_addr != MV643XX_ETH_PHY_ADDR_DEFAULT) {
fc32b0e2
LB		 2445 mp->phy_addr = pd->phy_addr & 0x3f;
2446 phy_addr_set(mp, mp->phy_addr);
2447 } else {
2448 mp->phy_addr = phy_addr_get(mp);
2449 }
2450 }
1da177e4 2451
fc32b0e2
LB		 2452 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2453 if (pd->rx_queue_size)
2454 mp->default_rx_ring_size = pd->rx_queue_size;
2455 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2456 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2457
f7981c1c 2458 mp->rxq_count = pd->rx_queue_count ? : 1;
64da80a2 2459
fc32b0e2
LB		 2460 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2461 if (pd->tx_queue_size)
2462 mp->default_tx_ring_size = pd->tx_queue_size;
2463 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2464 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc 2465
f7981c1c 2466 mp->txq_count = pd->tx_queue_count ? : 1;
1da177e4
LT		 2467}
2468
e5371493 2469static int phy_detect(struct mv643xx_eth_private *mp)
1da177e4 2470{
45c5d3bc
LB		 2471 int data;
2472 int data2;
2473
2474 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2475 if (data < 0)
2476 return -ENODEV;
2477
2478 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data ^ BMCR_ANENABLE) < 0)
2479 return -ENODEV;
fc32b0e2 2480
45c5d3bc
LB		 2481 data2 = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2482 if (data2 < 0)
2483 return -ENODEV;
1da177e4 2484
7f106c1d 2485 if (((data ^ data2) & BMCR_ANENABLE) == 0)
fc32b0e2 2486 return -ENODEV;
1da177e4 2487
7f106c1d 2488 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
1da177e4 2489
c9df406f 2490 return 0;
1da177e4
LT		 2491}
2492
fc32b0e2
LB		 2493static int phy_init(struct mv643xx_eth_private *mp,
2494 struct mv643xx_eth_platform_data *pd)
c28a4f89 2495{
fc32b0e2
LB		 2496 struct ethtool_cmd cmd;
2497 int err;
c28a4f89 2498
fc32b0e2
LB		 2499 err = phy_detect(mp);
2500 if (err) {
2501 dev_printk(KERN_INFO, &mp->dev->dev,
2502 "no PHY detected at addr %d\n", mp->phy_addr);
2503 return err;
2504 }
2505 phy_reset(mp);
2506
2507 mp->mii.phy_id = mp->phy_addr;
2508 mp->mii.phy_id_mask = 0x3f;
2509 mp->mii.reg_num_mask = 0x1f;
2510 mp->mii.dev = mp->dev;
2511 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2512 mp->mii.mdio_write = mv643xx_eth_mdio_write;
c28a4f89 2513
fc32b0e2 2514 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
c9df406f 2515
fc32b0e2
LB		 2516 memset(&cmd, 0, sizeof(cmd));
2517
2518 cmd.port = PORT_MII;
2519 cmd.transceiver = XCVR_INTERNAL;
2520 cmd.phy_address = mp->phy_addr;
2521 if (pd->speed == 0) {
2522 cmd.autoneg = AUTONEG_ENABLE;
2523 cmd.speed = SPEED_100;
2524 cmd.advertising = ADVERTISED_10baseT_Half |
2525 ADVERTISED_10baseT_Full |
2526 ADVERTISED_100baseT_Half |
2527 ADVERTISED_100baseT_Full;
c9df406f 2528 if (mp->mii.supports_gmii)
fc32b0e2 2529 cmd.advertising |= ADVERTISED_1000baseT_Full;
c9df406f 2530 } else {
fc32b0e2
LB		 2531 cmd.autoneg = AUTONEG_DISABLE;
2532 cmd.speed = pd->speed;
2533 cmd.duplex = pd->duplex;
c9df406f 2534 }
fc32b0e2 2535
fc32b0e2
LB		 2536 mv643xx_eth_set_settings(mp->dev, &cmd);
2537
2538 return 0;
c28a4f89
JC		 2539}
2540
81600eea
LB		 2541static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2542{
2543 u32 pscr;
2544
2545 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2546 if (pscr & SERIAL_PORT_ENABLE) {
2547 pscr &= ~SERIAL_PORT_ENABLE;
2548 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2549 }
2550
2551 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2552 if (mp->phy_addr == -1) {
2553 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2554 if (speed == SPEED_1000)
2555 pscr |= SET_GMII_SPEED_TO_1000;
2556 else if (speed == SPEED_100)
2557 pscr |= SET_MII_SPEED_TO_100;
2558
2559 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2560
2561 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2562 if (duplex == DUPLEX_FULL)
2563 pscr |= SET_FULL_DUPLEX_MODE;
2564 }
2565
2566 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2567}
2568
c9df406f 2569static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2570{
c9df406f 2571 struct mv643xx_eth_platform_data *pd;
e5371493 2572 struct mv643xx_eth_private *mp;
c9df406f 2573 struct net_device *dev;
c9df406f 2574 struct resource *res;
c9df406f 2575 DECLARE_MAC_BUF(mac);
fc32b0e2 2576 int err;
1da177e4 2577
c9df406f
LB		 2578 pd = pdev->dev.platform_data;
2579 if (pd == NULL) {
fc32b0e2
LB		 2580 dev_printk(KERN_ERR, &pdev->dev,
2581 "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2582 return -ENODEV;
2583 }
1da177e4 2584
c9df406f 2585 if (pd->shared == NULL) {
fc32b0e2
LB		 2586 dev_printk(KERN_ERR, &pdev->dev,
2587 "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2588 return -ENODEV;
2589 }
8f518703 2590
e5ef1de1 2591 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
c9df406f
LB		 2592 if (!dev)
2593 return -ENOMEM;
1da177e4 2594
c9df406f 2595 mp = netdev_priv(dev);
fc32b0e2
LB		 2596 platform_set_drvdata(pdev, mp);
2597
2598 mp->shared = platform_get_drvdata(pd->shared);
2599 mp->port_num = pd->port_number;
2600
c9df406f 2601 mp->dev = dev;
78fff83b 2602
fc32b0e2 2603 set_params(mp, pd);
e5ef1de1 2604 dev->real_num_tx_queues = mp->txq_count;
fc32b0e2 2605
fc32b0e2
LB		 2606 mib_counters_clear(mp);
2607 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2608
bedfe324
LB		 2609 if (mp->phy_addr != -1) {
2610 err = phy_init(mp, pd);
2611 if (err)
2612 goto out;
2613
2614 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2615 } else {
2616 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2617 }
81600eea 2618 init_pscr(mp, pd->speed, pd->duplex);
fc32b0e2 2619
2257e05c
LB		 2620 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2621
2622 init_timer(&mp->rx_oom);
2623 mp->rx_oom.data = (unsigned long)mp;
2624 mp->rx_oom.function = oom_timer_wrapper;
2625
fc32b0e2 2626
c9df406f
LB		 2627 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2628 BUG_ON(!res);
2629 dev->irq = res->start;
1da177e4 2630
8fd89211 2631 dev->get_stats = mv643xx_eth_get_stats;
fc32b0e2 2632 dev->hard_start_xmit = mv643xx_eth_xmit;
c9df406f
LB		 2633 dev->open = mv643xx_eth_open;
2634 dev->stop = mv643xx_eth_stop;
c9df406f 2635 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
fc32b0e2
LB		 2636 dev->set_mac_address = mv643xx_eth_set_mac_address;
2637 dev->do_ioctl = mv643xx_eth_ioctl;
2638 dev->change_mtu = mv643xx_eth_change_mtu;
c9df406f 2639 dev->tx_timeout = mv643xx_eth_tx_timeout;
c9df406f 2640#ifdef CONFIG_NET_POLL_CONTROLLER
e5371493 2641 dev->poll_controller = mv643xx_eth_netpoll;
c9df406f 2642#endif
c9df406f
LB		 2643 dev->watchdog_timeo = 2 * HZ;
2644 dev->base_addr = 0;
1da177e4 2645
c9df406f 2646 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
e32b6617 2647 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4 2648
fc32b0e2 2649 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2650
c9df406f 2651 if (mp->shared->win_protect)
fc32b0e2 2652 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2653
c9df406f
LB		 2654 err = register_netdev(dev);
2655 if (err)
2656 goto out;
1da177e4 2657
fc32b0e2
LB		 2658 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2659 mp->port_num, print_mac(mac, dev->dev_addr));
1da177e4 2660
13d64285 2661 if (mp->tx_desc_sram_size > 0)
fc32b0e2 2662 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
1da177e4 2663
c9df406f 2664 return 0;
1da177e4 2665
c9df406f
LB		 2666out:
2667 free_netdev(dev);
1da177e4 2668
c9df406f 2669 return err;
1da177e4
LT		 2670}
2671
c9df406f 2672static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2673{
fc32b0e2 2674 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2675
fc32b0e2 2676 unregister_netdev(mp->dev);
c9df406f 2677 flush_scheduled_work();
fc32b0e2 2678 free_netdev(mp->dev);
c9df406f 2679
c9df406f 2680 platform_set_drvdata(pdev, NULL);
fc32b0e2 2681
c9df406f 2682 return 0;
1da177e4
LT		 2683}
2684
c9df406f 2685static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2686{
fc32b0e2 2687 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 2688
c9df406f 2689 /* Mask all interrupts on ethernet port */
fc32b0e2
LB		 2690 wrl(mp, INT_MASK(mp->port_num), 0);
2691 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2692
fc32b0e2
LB		 2693 if (netif_running(mp->dev))
2694 port_reset(mp);
d0412d96
JC		 2695}
2696
c9df406f 2697static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 2698 .probe = mv643xx_eth_probe,
2699 .remove = mv643xx_eth_remove,
2700 .shutdown = mv643xx_eth_shutdown,
c9df406f 2701 .driver = {
fc32b0e2 2702 .name = MV643XX_ETH_NAME,
c9df406f
LB		 2703 .owner = THIS_MODULE,
2704 },
2705};
2706
e5371493 2707static int __init mv643xx_eth_init_module(void)
d0412d96 2708{
c9df406f 2709 int rc;
d0412d96 2710
c9df406f
LB		 2711 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2712 if (!rc) {
2713 rc = platform_driver_register(&mv643xx_eth_driver);
2714 if (rc)
2715 platform_driver_unregister(&mv643xx_eth_shared_driver);
2716 }
fc32b0e2 2717
c9df406f 2718 return rc;
d0412d96 2719}
fc32b0e2 2720module_init(mv643xx_eth_init_module);
d0412d96 2721
e5371493 2722static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 2723{
c9df406f
LB		 2724 platform_driver_unregister(&mv643xx_eth_driver);
2725 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 2726}
e5371493 2727module_exit(mv643xx_eth_cleanup_module);
1da177e4 2728
45675bc6
LB		 2729MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2730 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
c9df406f 2731MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 2732MODULE_LICENSE("GPL");
c9df406f 2733MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 2734MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux kernel - Deliverables
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