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pcnet32: Fix PCnet32 performance bug on non-coherent architecutres
[deliverable/linux.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 rabeeh@galileo.co.il
7 *
8 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 9 * written by Manish Lachwani
1da177e4
LT		 10 *
11 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
12 *
c8aaea25 13 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 14 * Dale Farnsworth <dale@farnsworth.org>
15 *
16 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
17 * <sjhill@realitydiluted.com>
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version 2
22 * of the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 */
33#include <linux/init.h>
34#include <linux/dma-mapping.h>
b6298c22
AV		 35#include <linux/in.h>
36#include <linux/ip.h>
1da177e4
LT		 37#include <linux/tcp.h>
38#include <linux/udp.h>
39#include <linux/etherdevice.h>
40
41#include <linux/bitops.h>
42#include <linux/delay.h>
43#include <linux/ethtool.h>
d052d1be
RK		 44#include <linux/platform_device.h>
45
1da177e4
LT		 46#include <asm/io.h>
47#include <asm/types.h>
48#include <asm/pgtable.h>
49#include <asm/system.h>
50#include <asm/delay.h>
51#include "mv643xx_eth.h"
52
1da177e4 53/* Static function declarations */
1da177e4
LT		 54static void eth_port_uc_addr_get(struct net_device *dev,
55 unsigned char *MacAddr);
16e03018 56static void eth_port_set_multicast_list(struct net_device *);
9f8dd319 57static void mv643xx_eth_port_enable_tx(unsigned int port_num,
12a87c64 58 unsigned int queues);
9f8dd319 59static void mv643xx_eth_port_enable_rx(unsigned int port_num,
12a87c64 60 unsigned int queues);
9f8dd319
DF		 61static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num);
62static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num);
ab4384a6
DF		 63static int mv643xx_eth_open(struct net_device *);
64static int mv643xx_eth_stop(struct net_device *);
1da177e4
LT		 65static int mv643xx_eth_change_mtu(struct net_device *, int);
66static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *);
67static void eth_port_init_mac_tables(unsigned int eth_port_num);
68#ifdef MV643XX_NAPI
69static int mv643xx_poll(struct net_device *dev, int *budget);
70#endif
c28a4f89 71static int ethernet_phy_get(unsigned int eth_port_num);
1da177e4
LT		 72static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
73static int ethernet_phy_detect(unsigned int eth_port_num);
c28a4f89
JC		 74static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location);
75static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val);
d0412d96 76static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
7282d491 77static const struct ethtool_ops mv643xx_ethtool_ops;
1da177e4
LT		 78
79static char mv643xx_driver_name[] = "mv643xx_eth";
80static char mv643xx_driver_version[] = "1.0";
81
82static void __iomem *mv643xx_eth_shared_base;
83
84/* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */
a9f6a0dd 85static DEFINE_SPINLOCK(mv643xx_eth_phy_lock);
1da177e4
LT		 86
87static inline u32 mv_read(int offset)
88{
dc074a8a 89 void __iomem *reg_base;
1da177e4
LT		 90
91 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
92
93 return readl(reg_base + offset);
94}
95
96static inline void mv_write(int offset, u32 data)
97{
dc074a8a 98 void __iomem *reg_base;
1da177e4
LT		 99
100 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
101 writel(data, reg_base + offset);
102}
103
104/*
105 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
106 *
107 * Input : pointer to ethernet interface network device structure
108 * new mtu size
109 * Output : 0 upon success, -EINVAL upon failure
110 */
111static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
112{
8f518703 113 if ((new_mtu > 9500) || (new_mtu < 64))
1da177e4 114 return -EINVAL;
1da177e4
LT		 115
116 dev->mtu = new_mtu;
117 /*
118 * Stop then re-open the interface. This will allocate RX skb's with
119 * the new MTU.
120 * There is a possible danger that the open will not successed, due
121 * to memory is full, which might fail the open function.
122 */
123 if (netif_running(dev)) {
ab4384a6
DF		 124 mv643xx_eth_stop(dev);
125 if (mv643xx_eth_open(dev))
1da177e4
LT		 126 printk(KERN_ERR
127 "%s: Fatal error on opening device\n",
128 dev->name);
129 }
130
1da177e4
LT		 131 return 0;
132}
133
134/*
f78fb474 135 * mv643xx_eth_rx_refill_descs
1da177e4
LT		 136 *
137 * Fills / refills RX queue on a certain gigabit ethernet port
138 *
139 * Input : pointer to ethernet interface network device structure
140 * Output : N/A
141 */
f78fb474 142static void mv643xx_eth_rx_refill_descs(struct net_device *dev)
1da177e4 143{
1da177e4
LT		 144 struct mv643xx_private *mp = netdev_priv(dev);
145 struct pkt_info pkt_info;
146 struct sk_buff *skb;
b44cd572 147 int unaligned;
1da177e4 148
f78fb474 149 while (mp->rx_desc_count < mp->rx_ring_size) {
908b637f 150 skb = dev_alloc_skb(ETH_RX_SKB_SIZE + dma_get_cache_alignment());
1da177e4
LT		 151 if (!skb)
152 break;
f98e36f1 153 mp->rx_desc_count++;
908b637f 154 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
b44cd572 155 if (unaligned)
908b637f 156 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
1da177e4 157 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
7303fde8
DF		 158 pkt_info.byte_cnt = ETH_RX_SKB_SIZE;
159 pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
160 ETH_RX_SKB_SIZE, DMA_FROM_DEVICE);
1da177e4
LT		 161 pkt_info.return_info = skb;
162 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
163 printk(KERN_ERR
164 "%s: Error allocating RX Ring\n", dev->name);
165 break;
166 }
7303fde8 167 skb_reserve(skb, ETH_HW_IP_ALIGN);
1da177e4 168 }
1da177e4
LT		 169 /*
170 * If RX ring is empty of SKB, set a timer to try allocating
f78fb474 171 * again at a later time.
1da177e4 172 */
f78fb474 173 if (mp->rx_desc_count == 0) {
1da177e4 174 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
f78fb474 175 mp->timeout.expires = jiffies + (HZ / 10); /* 100 mSec */
1da177e4 176 add_timer(&mp->timeout);
1da177e4 177 }
1da177e4
LT		 178}
179
180/*
f78fb474 181 * mv643xx_eth_rx_refill_descs_timer_wrapper
1da177e4
LT		 182 *
183 * Timer routine to wake up RX queue filling task. This function is
184 * used only in case the RX queue is empty, and all alloc_skb has
185 * failed (due to out of memory event).
186 *
187 * Input : pointer to ethernet interface network device structure
188 * Output : N/A
189 */
f78fb474 190static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data)
1da177e4 191{
f78fb474 192 mv643xx_eth_rx_refill_descs((struct net_device *)data);
1da177e4
LT		 193}
194
195/*
196 * mv643xx_eth_update_mac_address
197 *
198 * Update the MAC address of the port in the address table
199 *
200 * Input : pointer to ethernet interface network device structure
201 * Output : N/A
202 */
203static void mv643xx_eth_update_mac_address(struct net_device *dev)
204{
205 struct mv643xx_private *mp = netdev_priv(dev);
206 unsigned int port_num = mp->port_num;
207
208 eth_port_init_mac_tables(port_num);
ed9b5d45 209 eth_port_uc_addr_set(port_num, dev->dev_addr);
1da177e4
LT		 210}
211
212/*
213 * mv643xx_eth_set_rx_mode
214 *
215 * Change from promiscuos to regular rx mode
216 *
217 * Input : pointer to ethernet interface network device structure
218 * Output : N/A
219 */
220static void mv643xx_eth_set_rx_mode(struct net_device *dev)
221{
222 struct mv643xx_private *mp = netdev_priv(dev);
01999873 223 u32 config_reg;
1da177e4 224
01999873 225 config_reg = mv_read(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num));
1da177e4 226 if (dev->flags & IFF_PROMISC)
01999873 227 config_reg |= (u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
1da177e4 228 else
01999873
DF		 229 config_reg &= ~(u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
230 mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num), config_reg);
16e03018
DF		 231
232 eth_port_set_multicast_list(dev);
1da177e4
LT		 233}
234
235/*
236 * mv643xx_eth_set_mac_address
237 *
238 * Change the interface's mac address.
239 * No special hardware thing should be done because interface is always
240 * put in promiscuous mode.
241 *
242 * Input : pointer to ethernet interface network device structure and
243 * a pointer to the designated entry to be added to the cache.
244 * Output : zero upon success, negative upon failure
245 */
246static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
247{
248 int i;
249
250 for (i = 0; i < 6; i++)
251 /* +2 is for the offset of the HW addr type */
252 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
253 mv643xx_eth_update_mac_address(dev);
254 return 0;
255}
256
257/*
258 * mv643xx_eth_tx_timeout
259 *
260 * Called upon a timeout on transmitting a packet
261 *
262 * Input : pointer to ethernet interface network device structure.
263 * Output : N/A
264 */
265static void mv643xx_eth_tx_timeout(struct net_device *dev)
266{
267 struct mv643xx_private *mp = netdev_priv(dev);
268
269 printk(KERN_INFO "%s: TX timeout ", dev->name);
270
271 /* Do the reset outside of interrupt context */
272 schedule_work(&mp->tx_timeout_task);
273}
274
275/*
276 * mv643xx_eth_tx_timeout_task
277 *
278 * Actual routine to reset the adapter when a timeout on Tx has occurred
279 */
91c7c568 280static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly)
1da177e4 281{
91c7c568
AV		 282 struct mv643xx_private *mp = container_of(ugly, struct mv643xx_private,
283 tx_timeout_task);
284 struct net_device *dev = mp->mii.dev; /* yuck */
1da177e4 285
94843566
DF		 286 if (!netif_running(dev))
287 return;
288
289 netif_stop_queue(dev);
290
1da177e4 291 eth_port_reset(mp->port_num);
ed9b5d45 292 eth_port_start(dev);
94843566
DF		 293
294 if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
295 netif_wake_queue(dev);
1da177e4
LT		 296}
297
ff561eef
DF		 298/**
299 * mv643xx_eth_free_tx_descs - Free the tx desc data for completed descriptors
1da177e4 300 *
ff561eef 301 * If force is non-zero, frees uncompleted descriptors as well
1da177e4 302 */
ff561eef 303int mv643xx_eth_free_tx_descs(struct net_device *dev, int force)
1da177e4
LT		 304{
305 struct mv643xx_private *mp = netdev_priv(dev);
ff561eef
DF		 306 struct eth_tx_desc *desc;
307 u32 cmd_sts;
308 struct sk_buff *skb;
309 unsigned long flags;
310 int tx_index;
311 dma_addr_t addr;
312 int count;
313 int released = 0;
1da177e4 314
ff561eef
DF		 315 while (mp->tx_desc_count > 0) {
316 spin_lock_irqsave(&mp->lock, flags);
d344bff9
DF		 317
318 /* tx_desc_count might have changed before acquiring the lock */
319 if (mp->tx_desc_count <= 0) {
320 spin_unlock_irqrestore(&mp->lock, flags);
321 return released;
322 }
323
ff561eef
DF		 324 tx_index = mp->tx_used_desc_q;
325 desc = &mp->p_tx_desc_area[tx_index];
326 cmd_sts = desc->cmd_sts;
327
328 if (!force && (cmd_sts & ETH_BUFFER_OWNED_BY_DMA)) {
329 spin_unlock_irqrestore(&mp->lock, flags);
330 return released;
331 }
332
333 mp->tx_used_desc_q = (tx_index + 1) % mp->tx_ring_size;
334 mp->tx_desc_count--;
335
336 addr = desc->buf_ptr;
337 count = desc->byte_cnt;
338 skb = mp->tx_skb[tx_index];
339 if (skb)
340 mp->tx_skb[tx_index] = NULL;
341
7303fde8 342 if (cmd_sts & ETH_ERROR_SUMMARY) {
1da177e4 343 printk("%s: Error in TX\n", dev->name);
ff561eef 344 mp->stats.tx_errors++;
1da177e4
LT		 345 }
346
d344bff9
DF		 347 spin_unlock_irqrestore(&mp->lock, flags);
348
ff561eef
DF		 349 if (cmd_sts & ETH_TX_FIRST_DESC)
350 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
cb415d30 351 else
ff561eef 352 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
1da177e4 353
ff561eef
DF		 354 if (skb)
355 dev_kfree_skb_irq(skb);
356
357 released = 1;
1da177e4
LT		 358 }
359
1da177e4
LT		 360 return released;
361}
362
ff561eef
DF		 363static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev)
364{
365 struct mv643xx_private *mp = netdev_priv(dev);
366
367 if (mv643xx_eth_free_tx_descs(dev, 0) &&
368 mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
369 netif_wake_queue(dev);
370}
371
372static void mv643xx_eth_free_all_tx_descs(struct net_device *dev)
373{
374 mv643xx_eth_free_tx_descs(dev, 1);
375}
376
1da177e4
LT		 377/*
378 * mv643xx_eth_receive
379 *
380 * This function is forward packets that are received from the port's
381 * queues toward kernel core or FastRoute them to another interface.
382 *
383 * Input : dev - a pointer to the required interface
384 * max - maximum number to receive (0 means unlimted)
385 *
386 * Output : number of served packets
387 */
1da177e4 388static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
1da177e4
LT		 389{
390 struct mv643xx_private *mp = netdev_priv(dev);
391 struct net_device_stats *stats = &mp->stats;
392 unsigned int received_packets = 0;
393 struct sk_buff *skb;
394 struct pkt_info pkt_info;
395
b1dd9ca1 396 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
54caf44d 397 dma_unmap_single(NULL, pkt_info.buf_ptr, ETH_RX_SKB_SIZE,
71d28725 398 DMA_FROM_DEVICE);
f98e36f1 399 mp->rx_desc_count--;
1da177e4 400 received_packets++;
b1dd9ca1 401
468d09f8
DF		 402 /*
403 * Update statistics.
404 * Note byte count includes 4 byte CRC count
405 */
1da177e4
LT		 406 stats->rx_packets++;
407 stats->rx_bytes += pkt_info.byte_cnt;
408 skb = pkt_info.return_info;
409 /*
410 * In case received a packet without first / last bits on OR
411 * the error summary bit is on, the packets needs to be dropeed.
412 */
413 if (((pkt_info.cmd_sts
414 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
415 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
416 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
417 stats->rx_dropped++;
418 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
419 ETH_RX_LAST_DESC)) !=
420 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
421 if (net_ratelimit())
422 printk(KERN_ERR
423 "%s: Received packet spread "
424 "on multiple descriptors\n",
425 dev->name);
426 }
427 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
428 stats->rx_errors++;
429
430 dev_kfree_skb_irq(skb);
431 } else {
432 /*
433 * The -4 is for the CRC in the trailer of the
434 * received packet
435 */
436 skb_put(skb, pkt_info.byte_cnt - 4);
437 skb->dev = dev;
438
439 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
440 skb->ip_summed = CHECKSUM_UNNECESSARY;
441 skb->csum = htons(
442 (pkt_info.cmd_sts & 0x0007fff8) >> 3);
443 }
444 skb->protocol = eth_type_trans(skb, dev);
445#ifdef MV643XX_NAPI
446 netif_receive_skb(skb);
447#else
448 netif_rx(skb);
449#endif
450 }
12ad74f8 451 dev->last_rx = jiffies;
1da177e4 452 }
f78fb474 453 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
1da177e4
LT		 454
455 return received_packets;
456}
457
d0412d96
JC		 458/* Set the mv643xx port configuration register for the speed/duplex mode. */
459static void mv643xx_eth_update_pscr(struct net_device *dev,
460 struct ethtool_cmd *ecmd)
461{
462 struct mv643xx_private *mp = netdev_priv(dev);
463 int port_num = mp->port_num;
464 u32 o_pscr, n_pscr;
12a87c64 465 unsigned int queues;
d0412d96
JC		 466
467 o_pscr = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
468 n_pscr = o_pscr;
469
470 /* clear speed, duplex and rx buffer size fields */
471 n_pscr &= ~(MV643XX_ETH_SET_MII_SPEED_TO_100 |
472 MV643XX_ETH_SET_GMII_SPEED_TO_1000 |
473 MV643XX_ETH_SET_FULL_DUPLEX_MODE |
474 MV643XX_ETH_MAX_RX_PACKET_MASK);
475
476 if (ecmd->duplex == DUPLEX_FULL)
477 n_pscr |= MV643XX_ETH_SET_FULL_DUPLEX_MODE;
478
479 if (ecmd->speed == SPEED_1000)
480 n_pscr |= MV643XX_ETH_SET_GMII_SPEED_TO_1000 |
481 MV643XX_ETH_MAX_RX_PACKET_9700BYTE;
482 else {
483 if (ecmd->speed == SPEED_100)
484 n_pscr |= MV643XX_ETH_SET_MII_SPEED_TO_100;
485 n_pscr |= MV643XX_ETH_MAX_RX_PACKET_1522BYTE;
486 }
487
488 if (n_pscr != o_pscr) {
489 if ((o_pscr & MV643XX_ETH_SERIAL_PORT_ENABLE) == 0)
490 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
491 n_pscr);
492 else {
12a87c64 493 queues = mv643xx_eth_port_disable_tx(port_num);
d0412d96
JC		 494
495 o_pscr &= ~MV643XX_ETH_SERIAL_PORT_ENABLE;
496 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
497 o_pscr);
498 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
499 n_pscr);
500 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
501 n_pscr);
12a87c64
DF		 502 if (queues)
503 mv643xx_eth_port_enable_tx(port_num, queues);
d0412d96
JC		 504 }
505 }
506}
507
1da177e4
LT		 508/*
509 * mv643xx_eth_int_handler
510 *
511 * Main interrupt handler for the gigbit ethernet ports
512 *
513 * Input : irq - irq number (not used)
514 * dev_id - a pointer to the required interface's data structure
515 * regs - not used
516 * Output : N/A
517 */
518
7d12e780 519static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id)
1da177e4
LT		 520{
521 struct net_device *dev = (struct net_device *)dev_id;
522 struct mv643xx_private *mp = netdev_priv(dev);
523 u32 eth_int_cause, eth_int_cause_ext = 0;
524 unsigned int port_num = mp->port_num;
525
526 /* Read interrupt cause registers */
527 eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) &
7303fde8 528 ETH_INT_UNMASK_ALL;
468d09f8 529 if (eth_int_cause & ETH_INT_CAUSE_EXT) {
1da177e4
LT		 530 eth_int_cause_ext = mv_read(
531 MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
7303fde8 532 ETH_INT_UNMASK_ALL_EXT;
468d09f8
DF		 533 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num),
534 ~eth_int_cause_ext);
1da177e4 535 }
7303fde8 536
1da177e4 537 /* PHY status changed */
468d09f8 538 if (eth_int_cause_ext & ETH_INT_CAUSE_PHY) {
d0412d96
JC		 539 struct ethtool_cmd cmd;
540
c28a4f89 541 if (mii_link_ok(&mp->mii)) {
d0412d96
JC		 542 mii_ethtool_gset(&mp->mii, &cmd);
543 mv643xx_eth_update_pscr(dev, &cmd);
ff561eef
DF		 544 mv643xx_eth_port_enable_tx(port_num,
545 ETH_TX_QUEUES_ENABLED);
c28a4f89
JC		 546 if (!netif_carrier_ok(dev)) {
547 netif_carrier_on(dev);
ff561eef
DF		 548 if (mp->tx_ring_size - mp->tx_desc_count >=
549 MAX_DESCS_PER_SKB)
d0412d96 550 netif_wake_queue(dev);
c28a4f89
JC		 551 }
552 } else if (netif_carrier_ok(dev)) {
1da177e4 553 netif_stop_queue(dev);
c28a4f89 554 netif_carrier_off(dev);
1da177e4
LT		 555 }
556 }
557
468d09f8
DF		 558#ifdef MV643XX_NAPI
559 if (eth_int_cause & ETH_INT_CAUSE_RX) {
560 /* schedule the NAPI poll routine to maintain port */
561 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
562 ETH_INT_MASK_ALL);
563 /* wait for previous write to complete */
564 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
565
566 netif_rx_schedule(dev);
567 }
568#else
569 if (eth_int_cause & ETH_INT_CAUSE_RX)
570 mv643xx_eth_receive_queue(dev, INT_MAX);
5c537408 571#endif
468d09f8
DF		 572 if (eth_int_cause_ext & ETH_INT_CAUSE_TX)
573 mv643xx_eth_free_completed_tx_descs(dev);
468d09f8 574
1da177e4
LT		 575 /*
576 * If no real interrupt occured, exit.
577 * This can happen when using gigE interrupt coalescing mechanism.
578 */
579 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
580 return IRQ_NONE;
581
582 return IRQ_HANDLED;
583}
584
585#ifdef MV643XX_COAL
586
587/*
588 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
589 *
590 * DESCRIPTION:
591 * This routine sets the RX coalescing interrupt mechanism parameter.
592 * This parameter is a timeout counter, that counts in 64 t_clk
593 * chunks ; that when timeout event occurs a maskable interrupt
594 * occurs.
595 * The parameter is calculated using the tClk of the MV-643xx chip
596 * , and the required delay of the interrupt in usec.
597 *
598 * INPUT:
599 * unsigned int eth_port_num Ethernet port number
600 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
601 * unsigned int delay Delay in usec
602 *
603 * OUTPUT:
604 * Interrupt coalescing mechanism value is set in MV-643xx chip.
605 *
606 * RETURN:
607 * The interrupt coalescing value set in the gigE port.
608 *
609 */
610static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
611 unsigned int t_clk, unsigned int delay)
612{
613 unsigned int coal = ((t_clk / 1000000) * delay) / 64;
614
615 /* Set RX Coalescing mechanism */
616 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num),
617 ((coal & 0x3fff) << 8) |
618 (mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num))
619 & 0xffc000ff));
620
621 return coal;
622}
623#endif
624
625/*
626 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
627 *
628 * DESCRIPTION:
629 * This routine sets the TX coalescing interrupt mechanism parameter.
630 * This parameter is a timeout counter, that counts in 64 t_clk
631 * chunks ; that when timeout event occurs a maskable interrupt
632 * occurs.
633 * The parameter is calculated using the t_cLK frequency of the
634 * MV-643xx chip and the required delay in the interrupt in uSec
635 *
636 * INPUT:
637 * unsigned int eth_port_num Ethernet port number
638 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
639 * unsigned int delay Delay in uSeconds
640 *
641 * OUTPUT:
642 * Interrupt coalescing mechanism value is set in MV-643xx chip.
643 *
644 * RETURN:
645 * The interrupt coalescing value set in the gigE port.
646 *
647 */
648static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num,
649 unsigned int t_clk, unsigned int delay)
650{
651 unsigned int coal;
652 coal = ((t_clk / 1000000) * delay) / 64;
653 /* Set TX Coalescing mechanism */
654 mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num),
655 coal << 4);
656 return coal;
657}
658
1da177e4
LT		 659/*
660 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
661 *
662 * DESCRIPTION:
663 * This function prepares a Rx chained list of descriptors and packet
664 * buffers in a form of a ring. The routine must be called after port
665 * initialization routine and before port start routine.
666 * The Ethernet SDMA engine uses CPU bus addresses to access the various
667 * devices in the system (i.e. DRAM). This function uses the ethernet
668 * struct 'virtual to physical' routine (set by the user) to set the ring
669 * with physical addresses.
670 *
671 * INPUT:
672 * struct mv643xx_private *mp Ethernet Port Control srtuct.
673 *
674 * OUTPUT:
675 * The routine updates the Ethernet port control struct with information
676 * regarding the Rx descriptors and buffers.
677 *
678 * RETURN:
679 * None.
680 */
681static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
682{
683 volatile struct eth_rx_desc *p_rx_desc;
684 int rx_desc_num = mp->rx_ring_size;
685 int i;
686
687 /* initialize the next_desc_ptr links in the Rx descriptors ring */
688 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
689 for (i = 0; i < rx_desc_num; i++) {
690 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
691 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
692 }
693
694 /* Save Rx desc pointer to driver struct. */
695 mp->rx_curr_desc_q = 0;
696 mp->rx_used_desc_q = 0;
697
698 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
1da177e4
LT		 699}
700
701/*
702 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
703 *
704 * DESCRIPTION:
705 * This function prepares a Tx chained list of descriptors and packet
706 * buffers in a form of a ring. The routine must be called after port
707 * initialization routine and before port start routine.
708 * The Ethernet SDMA engine uses CPU bus addresses to access the various
709 * devices in the system (i.e. DRAM). This function uses the ethernet
710 * struct 'virtual to physical' routine (set by the user) to set the ring
711 * with physical addresses.
712 *
713 * INPUT:
714 * struct mv643xx_private *mp Ethernet Port Control srtuct.
715 *
716 * OUTPUT:
717 * The routine updates the Ethernet port control struct with information
718 * regarding the Tx descriptors and buffers.
719 *
720 * RETURN:
721 * None.
722 */
723static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
724{
725 int tx_desc_num = mp->tx_ring_size;
726 struct eth_tx_desc *p_tx_desc;
727 int i;
728
729 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
730 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
731 for (i = 0; i < tx_desc_num; i++) {
732 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
733 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
734 }
735
736 mp->tx_curr_desc_q = 0;
737 mp->tx_used_desc_q = 0;
1da177e4
LT		 738
739 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
1da177e4
LT		 740}
741
d0412d96
JC		 742static int mv643xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
743{
744 struct mv643xx_private *mp = netdev_priv(dev);
745 int err;
746
747 spin_lock_irq(&mp->lock);
748 err = mii_ethtool_sset(&mp->mii, cmd);
749 spin_unlock_irq(&mp->lock);
750
751 return err;
752}
753
754static int mv643xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
755{
756 struct mv643xx_private *mp = netdev_priv(dev);
757 int err;
758
759 spin_lock_irq(&mp->lock);
760 err = mii_ethtool_gset(&mp->mii, cmd);
761 spin_unlock_irq(&mp->lock);
762
763 /* The PHY may support 1000baseT_Half, but the mv643xx does not */
764 cmd->supported &= ~SUPPORTED_1000baseT_Half;
765 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
766
767 return err;
768}
769
ab4384a6
DF		 770/*
771 * mv643xx_eth_open
772 *
773 * This function is called when openning the network device. The function
774 * should initialize all the hardware, initialize cyclic Rx/Tx
775 * descriptors chain and buffers and allocate an IRQ to the network
776 * device.
777 *
778 * Input : a pointer to the network device structure
779 *
780 * Output : zero of success , nonzero if fails.
781 */
782
783static int mv643xx_eth_open(struct net_device *dev)
1da177e4
LT		 784{
785 struct mv643xx_private *mp = netdev_priv(dev);
786 unsigned int port_num = mp->port_num;
787 unsigned int size;
ab4384a6
DF		 788 int err;
789
790 err = request_irq(dev->irq, mv643xx_eth_int_handler,
1fb9df5d 791 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
ab4384a6
DF		 792 if (err) {
793 printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n",
794 port_num);
795 return -EAGAIN;
796 }
1da177e4 797
1da177e4
LT		 798 eth_port_init(mp);
799
1da177e4 800 memset(&mp->timeout, 0, sizeof(struct timer_list));
f78fb474 801 mp->timeout.function = mv643xx_eth_rx_refill_descs_timer_wrapper;
1da177e4
LT		 802 mp->timeout.data = (unsigned long)dev;
803
1da177e4
LT		 804 /* Allocate RX and TX skb rings */
805 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
806 GFP_KERNEL);
807 if (!mp->rx_skb) {
808 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
ab4384a6
DF		 809 err = -ENOMEM;
810 goto out_free_irq;
1da177e4
LT		 811 }
812 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
813 GFP_KERNEL);
814 if (!mp->tx_skb) {
815 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
ab4384a6
DF		 816 err = -ENOMEM;
817 goto out_free_rx_skb;
1da177e4
LT		 818 }
819
820 /* Allocate TX ring */
f98e36f1 821 mp->tx_desc_count = 0;
1da177e4
LT		 822 size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
823 mp->tx_desc_area_size = size;
824
825 if (mp->tx_sram_size) {
826 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
827 mp->tx_sram_size);
828 mp->tx_desc_dma = mp->tx_sram_addr;
829 } else
830 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
831 &mp->tx_desc_dma,
832 GFP_KERNEL);
833
834 if (!mp->p_tx_desc_area) {
835 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
836 dev->name, size);
ab4384a6
DF		 837 err = -ENOMEM;
838 goto out_free_tx_skb;
1da177e4
LT		 839 }
840 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
841 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
842
843 ether_init_tx_desc_ring(mp);
844
845 /* Allocate RX ring */
f98e36f1 846 mp->rx_desc_count = 0;
1da177e4
LT		 847 size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
848 mp->rx_desc_area_size = size;
849
850 if (mp->rx_sram_size) {
851 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
852 mp->rx_sram_size);
853 mp->rx_desc_dma = mp->rx_sram_addr;
854 } else
855 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
856 &mp->rx_desc_dma,
857 GFP_KERNEL);
858
859 if (!mp->p_rx_desc_area) {
860 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
861 dev->name, size);
862 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
863 dev->name);
864 if (mp->rx_sram_size)
dd09b1de 865 iounmap(mp->p_tx_desc_area);
1da177e4
LT		 866 else
867 dma_free_coherent(NULL, mp->tx_desc_area_size,
868 mp->p_tx_desc_area, mp->tx_desc_dma);
ab4384a6
DF		 869 err = -ENOMEM;
870 goto out_free_tx_skb;
1da177e4
LT		 871 }
872 memset((void *)mp->p_rx_desc_area, 0, size);
873
874 ether_init_rx_desc_ring(mp);
875
f78fb474 876 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
1da177e4 877
d0412d96
JC		 878 /* Clear any pending ethernet port interrupts */
879 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
880 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
881
ed9b5d45 882 eth_port_start(dev);
1da177e4
LT		 883
884 /* Interrupt Coalescing */
885
886#ifdef MV643XX_COAL
887 mp->rx_int_coal =
888 eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL);
889#endif
890
891 mp->tx_int_coal =
892 eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL);
893
8f518703
DF		 894 /* Unmask phy and link status changes interrupts */
895 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
7303fde8 896 ETH_INT_UNMASK_ALL_EXT);
1da177e4 897
8f518703 898 /* Unmask RX buffer and TX end interrupt */
7303fde8 899 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
d0412d96 900
1da177e4 901 return 0;
ab4384a6
DF		 902
903out_free_tx_skb:
904 kfree(mp->tx_skb);
905out_free_rx_skb:
906 kfree(mp->rx_skb);
907out_free_irq:
908 free_irq(dev->irq, dev);
909
910 return err;
1da177e4
LT		 911}
912
913static void mv643xx_eth_free_tx_rings(struct net_device *dev)
914{
915 struct mv643xx_private *mp = netdev_priv(dev);
1da177e4
LT		 916
917 /* Stop Tx Queues */
ff561eef 918 mv643xx_eth_port_disable_tx(mp->port_num);
1da177e4 919
ff561eef
DF		 920 /* Free outstanding skb's on TX ring */
921 mv643xx_eth_free_all_tx_descs(dev);
922
923 BUG_ON(mp->tx_used_desc_q != mp->tx_curr_desc_q);
1da177e4
LT		 924
925 /* Free TX ring */
926 if (mp->tx_sram_size)
927 iounmap(mp->p_tx_desc_area);
928 else
929 dma_free_coherent(NULL, mp->tx_desc_area_size,
930 mp->p_tx_desc_area, mp->tx_desc_dma);
931}
932
933static void mv643xx_eth_free_rx_rings(struct net_device *dev)
934{
935 struct mv643xx_private *mp = netdev_priv(dev);
936 unsigned int port_num = mp->port_num;
937 int curr;
938
939 /* Stop RX Queues */
9f8dd319 940 mv643xx_eth_port_disable_rx(port_num);
1da177e4
LT		 941
942 /* Free preallocated skb's on RX rings */
f98e36f1 943 for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) {
1da177e4
LT		 944 if (mp->rx_skb[curr]) {
945 dev_kfree_skb(mp->rx_skb[curr]);
f98e36f1 946 mp->rx_desc_count--;
1da177e4
LT		 947 }
948 }
949
f98e36f1 950 if (mp->rx_desc_count)
1da177e4
LT		 951 printk(KERN_ERR
952 "%s: Error in freeing Rx Ring. %d skb's still"
953 " stuck in RX Ring - ignoring them\n", dev->name,
f98e36f1 954 mp->rx_desc_count);
1da177e4
LT		 955 /* Free RX ring */
956 if (mp->rx_sram_size)
957 iounmap(mp->p_rx_desc_area);
958 else
959 dma_free_coherent(NULL, mp->rx_desc_area_size,
960 mp->p_rx_desc_area, mp->rx_desc_dma);
961}
962
963/*
964 * mv643xx_eth_stop
965 *
966 * This function is used when closing the network device.
967 * It updates the hardware,
968 * release all memory that holds buffers and descriptors and release the IRQ.
969 * Input : a pointer to the device structure
970 * Output : zero if success , nonzero if fails
971 */
972
ab4384a6 973static int mv643xx_eth_stop(struct net_device *dev)
1da177e4
LT		 974{
975 struct mv643xx_private *mp = netdev_priv(dev);
976 unsigned int port_num = mp->port_num;
977
c2e5b352 978 /* Mask all interrupts on ethernet port */
7303fde8 979 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
c2e5b352 980 /* wait for previous write to complete */
8f518703
DF		 981 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
982
983#ifdef MV643XX_NAPI
984 netif_poll_disable(dev);
985#endif
1da177e4
LT		 986 netif_carrier_off(dev);
987 netif_stop_queue(dev);
988
1da177e4
LT		 989 eth_port_reset(mp->port_num);
990
8f518703
DF		 991 mv643xx_eth_free_tx_rings(dev);
992 mv643xx_eth_free_rx_rings(dev);
1da177e4 993
8f518703
DF		 994#ifdef MV643XX_NAPI
995 netif_poll_enable(dev);
996#endif
1da177e4 997
1da177e4 998 free_irq(dev->irq, dev);
1da177e4
LT		 999
1000 return 0;
1001}
1002
1003#ifdef MV643XX_NAPI
1da177e4
LT		 1004/*
1005 * mv643xx_poll
1006 *
1007 * This function is used in case of NAPI
1008 */
1009static int mv643xx_poll(struct net_device *dev, int *budget)
1010{
1011 struct mv643xx_private *mp = netdev_priv(dev);
1012 int done = 1, orig_budget, work_done;
1013 unsigned int port_num = mp->port_num;
1da177e4
LT		 1014
1015#ifdef MV643XX_TX_FAST_REFILL
1016 if (++mp->tx_clean_threshold > 5) {
ff561eef 1017 mv643xx_eth_free_completed_tx_descs(dev);
1da177e4 1018 mp->tx_clean_threshold = 0;
1da177e4
LT		 1019 }
1020#endif
1021
1022 if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
1023 != (u32) mp->rx_used_desc_q) {
1024 orig_budget = *budget;
1025 if (orig_budget > dev->quota)
1026 orig_budget = dev->quota;
1027 work_done = mv643xx_eth_receive_queue(dev, orig_budget);
1da177e4
LT		 1028 *budget -= work_done;
1029 dev->quota -= work_done;
1030 if (work_done >= orig_budget)
1031 done = 0;
1032 }
1033
1034 if (done) {
8f518703 1035 netif_rx_complete(dev);
1da177e4
LT		 1036 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
1037 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1038 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
7303fde8 1039 ETH_INT_UNMASK_ALL);
1da177e4
LT		 1040 }
1041
1042 return done ? 0 : 1;
1043}
1044#endif
1045
c8aaea25
DF		 1046/**
1047 * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments
1048 *
1049 * Hardware can't handle unaligned fragments smaller than 9 bytes.
f7ea3337
PJ		 1050 * This helper function detects that case.
1051 */
1052
1053static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1054{
b4de9051
DF		 1055 unsigned int frag;
1056 skb_frag_t *fragp;
f7ea3337 1057
b4de9051
DF		 1058 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1059 fragp = &skb_shinfo(skb)->frags[frag];
1060 if (fragp->size <= 8 && fragp->page_offset & 0x7)
1061 return 1;
1062 }
1063 return 0;
f7ea3337
PJ		 1064}
1065
c8aaea25
DF		 1066/**
1067 * eth_alloc_tx_desc_index - return the index of the next available tx desc
1068 */
1069static int eth_alloc_tx_desc_index(struct mv643xx_private *mp)
1070{
1071 int tx_desc_curr;
1072
c8aaea25 1073 BUG_ON(mp->tx_desc_count >= mp->tx_ring_size);
c8aaea25 1074
ff561eef 1075 tx_desc_curr = mp->tx_curr_desc_q;
c8aaea25
DF		 1076 mp->tx_curr_desc_q = (tx_desc_curr + 1) % mp->tx_ring_size;
1077
1078 BUG_ON(mp->tx_curr_desc_q == mp->tx_used_desc_q);
1079
1080 return tx_desc_curr;
1081}
1082
1083/**
1084 * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments.
1da177e4 1085 *
c8aaea25
DF		 1086 * Ensure the data for each fragment to be transmitted is mapped properly,
1087 * then fill in descriptors in the tx hw queue.
1da177e4 1088 */
c8aaea25
DF		 1089static void eth_tx_fill_frag_descs(struct mv643xx_private *mp,
1090 struct sk_buff *skb)
1da177e4 1091{
c8aaea25
DF		 1092 int frag;
1093 int tx_index;
1094 struct eth_tx_desc *desc;
1da177e4 1095
c8aaea25
DF		 1096 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1097 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1098
1099 tx_index = eth_alloc_tx_desc_index(mp);
1100 desc = &mp->p_tx_desc_area[tx_index];
1101
1102 desc->cmd_sts = ETH_BUFFER_OWNED_BY_DMA;
1103 /* Last Frag enables interrupt and frees the skb */
1104 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
1105 desc->cmd_sts |= ETH_ZERO_PADDING |
1106 ETH_TX_LAST_DESC |
1107 ETH_TX_ENABLE_INTERRUPT;
1108 mp->tx_skb[tx_index] = skb;
1109 } else
05980775 1110 mp->tx_skb[tx_index] = NULL;
c8aaea25
DF		 1111
1112 desc = &mp->p_tx_desc_area[tx_index];
1113 desc->l4i_chk = 0;
1114 desc->byte_cnt = this_frag->size;
1115 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
1116 this_frag->page_offset,
1117 this_frag->size,
1118 DMA_TO_DEVICE);
1da177e4 1119 }
c8aaea25 1120}
1da177e4 1121
c8aaea25
DF		 1122/**
1123 * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw
1124 *
1125 * Ensure the data for an skb to be transmitted is mapped properly,
1126 * then fill in descriptors in the tx hw queue and start the hardware.
1127 */
ff561eef
DF		 1128static void eth_tx_submit_descs_for_skb(struct mv643xx_private *mp,
1129 struct sk_buff *skb)
c8aaea25
DF		 1130{
1131 int tx_index;
1132 struct eth_tx_desc *desc;
1133 u32 cmd_sts;
1134 int length;
ff561eef 1135 int nr_frags = skb_shinfo(skb)->nr_frags;
1da177e4 1136
c8aaea25 1137 cmd_sts = ETH_TX_FIRST_DESC | ETH_GEN_CRC | ETH_BUFFER_OWNED_BY_DMA;
1da177e4 1138
c8aaea25
DF		 1139 tx_index = eth_alloc_tx_desc_index(mp);
1140 desc = &mp->p_tx_desc_area[tx_index];
1141
ff561eef 1142 if (nr_frags) {
c8aaea25
DF		 1143 eth_tx_fill_frag_descs(mp, skb);
1144
1145 length = skb_headlen(skb);
05980775 1146 mp->tx_skb[tx_index] = NULL;
c8aaea25
DF		 1147 } else {
1148 cmd_sts |= ETH_ZERO_PADDING |
1149 ETH_TX_LAST_DESC |
1150 ETH_TX_ENABLE_INTERRUPT;
1151 length = skb->len;
1152 mp->tx_skb[tx_index] = skb;
f7ea3337
PJ		 1153 }
1154
c8aaea25
DF		 1155 desc->byte_cnt = length;
1156 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
1da177e4 1157
84fa7933 1158 if (skb->ip_summed == CHECKSUM_PARTIAL) {
c8aaea25
DF		 1159 BUG_ON(skb->protocol != ETH_P_IP);
1160
1161 cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM |
1162 ETH_GEN_IP_V_4_CHECKSUM |
1163 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
1164
1165 switch (skb->nh.iph->protocol) {
1166 case IPPROTO_UDP:
1167 cmd_sts |= ETH_UDP_FRAME;
1168 desc->l4i_chk = skb->h.uh->check;
1169 break;
1170 case IPPROTO_TCP:
1171 desc->l4i_chk = skb->h.th->check;
1172 break;
1173 default:
1174 BUG();
1da177e4 1175 }
1da177e4 1176 } else {
c8aaea25
DF		 1177 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1178 cmd_sts |= 5 << ETH_TX_IHL_SHIFT;
1179 desc->l4i_chk = 0;
1180 }
1da177e4 1181
c8aaea25
DF		 1182 /* ensure all other descriptors are written before first cmd_sts */
1183 wmb();
1184 desc->cmd_sts = cmd_sts;
1da177e4 1185
c8aaea25
DF		 1186 /* ensure all descriptors are written before poking hardware */
1187 wmb();
ff561eef 1188 mv643xx_eth_port_enable_tx(mp->port_num, ETH_TX_QUEUES_ENABLED);
1da177e4 1189
ff561eef 1190 mp->tx_desc_count += nr_frags + 1;
c8aaea25 1191}
1da177e4 1192
c8aaea25
DF		 1193/**
1194 * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission
1195 *
1196 */
1197static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1198{
1199 struct mv643xx_private *mp = netdev_priv(dev);
1200 struct net_device_stats *stats = &mp->stats;
1201 unsigned long flags;
1da177e4 1202
c8aaea25
DF		 1203 BUG_ON(netif_queue_stopped(dev));
1204 BUG_ON(skb == NULL);
94843566
DF		 1205
1206 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) {
1207 printk(KERN_ERR "%s: transmit with queue full\n", dev->name);
1208 netif_stop_queue(dev);
1209 return 1;
1210 }
1da177e4 1211
c8aaea25 1212 if (has_tiny_unaligned_frags(skb)) {
364c6bad 1213 if (__skb_linearize(skb)) {
c8aaea25
DF		 1214 stats->tx_dropped++;
1215 printk(KERN_DEBUG "%s: failed to linearize tiny "
1216 "unaligned fragment\n", dev->name);
1217 return 1;
1da177e4
LT		 1218 }
1219 }
f7ea3337 1220
c8aaea25 1221 spin_lock_irqsave(&mp->lock, flags);
1da177e4 1222
ff561eef
DF		 1223 eth_tx_submit_descs_for_skb(mp, skb);
1224 stats->tx_bytes = skb->len;
1da177e4
LT		 1225 stats->tx_packets++;
1226 dev->trans_start = jiffies;
1227
c8aaea25
DF		 1228 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB)
1229 netif_stop_queue(dev);
1230
1da177e4
LT		 1231 spin_unlock_irqrestore(&mp->lock, flags);
1232
1233 return 0; /* success */
1234}
1235
1236/*
1237 * mv643xx_eth_get_stats
1238 *
1239 * Returns a pointer to the interface statistics.
1240 *
1241 * Input : dev - a pointer to the required interface
1242 *
1243 * Output : a pointer to the interface's statistics
1244 */
1245
1246static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1247{
1248 struct mv643xx_private *mp = netdev_priv(dev);
1249
1250 return &mp->stats;
1251}
1252
63c9e549 1253#ifdef CONFIG_NET_POLL_CONTROLLER
63c9e549
DF		 1254static void mv643xx_netpoll(struct net_device *netdev)
1255{
1256 struct mv643xx_private *mp = netdev_priv(netdev);
c2e5b352
DF		 1257 int port_num = mp->port_num;
1258
7303fde8 1259 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
c2e5b352
DF		 1260 /* wait for previous write to complete */
1261 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
63c9e549 1262
9da3b1ad 1263 mv643xx_eth_int_handler(netdev->irq, netdev);
c2e5b352 1264
7303fde8 1265 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
63c9e549
DF		 1266}
1267#endif
1268
d0412d96
JC		 1269static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address,
1270 int speed, int duplex,
1271 struct ethtool_cmd *cmd)
1272{
1273 struct mv643xx_private *mp = netdev_priv(dev);
1274
1275 memset(cmd, 0, sizeof(*cmd));
1276
1277 cmd->port = PORT_MII;
1278 cmd->transceiver = XCVR_INTERNAL;
1279 cmd->phy_address = phy_address;
1280
1281 if (speed == 0) {
1282 cmd->autoneg = AUTONEG_ENABLE;
1283 /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */
1284 cmd->speed = SPEED_100;
1285 cmd->advertising = ADVERTISED_10baseT_Half |
1286 ADVERTISED_10baseT_Full |
1287 ADVERTISED_100baseT_Half |
1288 ADVERTISED_100baseT_Full;
1289 if (mp->mii.supports_gmii)
1290 cmd->advertising |= ADVERTISED_1000baseT_Full;
1291 } else {
1292 cmd->autoneg = AUTONEG_DISABLE;
1293 cmd->speed = speed;
1294 cmd->duplex = duplex;
1295 }
1296}
1297
1da177e4
LT		 1298/*/
1299 * mv643xx_eth_probe
1300 *
1301 * First function called after registering the network device.
1302 * It's purpose is to initialize the device as an ethernet device,
1303 * fill the ethernet device structure with pointers * to functions,
1304 * and set the MAC address of the interface
1305 *
1306 * Input : struct device *
1307 * Output : -ENOMEM if failed , 0 if success
1308 */
3ae5eaec 1309static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 1310{
1da177e4
LT		 1311 struct mv643xx_eth_platform_data *pd;
1312 int port_num = pdev->id;
1313 struct mv643xx_private *mp;
1314 struct net_device *dev;
1315 u8 *p;
1316 struct resource *res;
1317 int err;
d0412d96 1318 struct ethtool_cmd cmd;
01999873
DF		 1319 int duplex = DUPLEX_HALF;
1320 int speed = 0; /* default to auto-negotiation */
1da177e4
LT		 1321
1322 dev = alloc_etherdev(sizeof(struct mv643xx_private));
1323 if (!dev)
1324 return -ENOMEM;
1325
3ae5eaec 1326 platform_set_drvdata(pdev, dev);
1da177e4
LT		 1327
1328 mp = netdev_priv(dev);
1329
1330 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1331 BUG_ON(!res);
1332 dev->irq = res->start;
1333
1334 mp->port_num = port_num;
1335
1336 dev->open = mv643xx_eth_open;
1337 dev->stop = mv643xx_eth_stop;
1338 dev->hard_start_xmit = mv643xx_eth_start_xmit;
1339 dev->get_stats = mv643xx_eth_get_stats;
1340 dev->set_mac_address = mv643xx_eth_set_mac_address;
1341 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
1342
1343 /* No need to Tx Timeout */
1344 dev->tx_timeout = mv643xx_eth_tx_timeout;
1345#ifdef MV643XX_NAPI
1346 dev->poll = mv643xx_poll;
1347 dev->weight = 64;
1348#endif
1349
63c9e549
DF		 1350#ifdef CONFIG_NET_POLL_CONTROLLER
1351 dev->poll_controller = mv643xx_netpoll;
1352#endif
1353
1da177e4
LT		 1354 dev->watchdog_timeo = 2 * HZ;
1355 dev->tx_queue_len = mp->tx_ring_size;
1356 dev->base_addr = 0;
1357 dev->change_mtu = mv643xx_eth_change_mtu;
d0412d96 1358 dev->do_ioctl = mv643xx_eth_do_ioctl;
1da177e4
LT		 1359 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
1360
1361#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1362#ifdef MAX_SKB_FRAGS
1363 /*
1364 * Zero copy can only work if we use Discovery II memory. Else, we will
1365 * have to map the buffers to ISA memory which is only 16 MB
1366 */
63890576 1367 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4
LT		 1368#endif
1369#endif
1370
1371 /* Configure the timeout task */
91c7c568 1372 INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task);
1da177e4
LT		 1373
1374 spin_lock_init(&mp->lock);
1375
1376 /* set default config values */
1377 eth_port_uc_addr_get(dev, dev->dev_addr);
1da177e4
LT		 1378 mp->rx_ring_size = MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
1379 mp->tx_ring_size = MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
1380
1381 pd = pdev->dev.platform_data;
1382 if (pd) {
5ada386b 1383 if (is_valid_ether_addr(pd->mac_addr))
1da177e4
LT		 1384 memcpy(dev->dev_addr, pd->mac_addr, 6);
1385
1386 if (pd->phy_addr || pd->force_phy_addr)
1387 ethernet_phy_set(port_num, pd->phy_addr);
1388
1da177e4
LT		 1389 if (pd->rx_queue_size)
1390 mp->rx_ring_size = pd->rx_queue_size;
1391
1392 if (pd->tx_queue_size)
1393 mp->tx_ring_size = pd->tx_queue_size;
1394
1395 if (pd->tx_sram_size) {
1396 mp->tx_sram_size = pd->tx_sram_size;
1397 mp->tx_sram_addr = pd->tx_sram_addr;
1398 }
1399
1400 if (pd->rx_sram_size) {
1401 mp->rx_sram_size = pd->rx_sram_size;
1402 mp->rx_sram_addr = pd->rx_sram_addr;
1403 }
01999873
DF		 1404
1405 duplex = pd->duplex;
1406 speed = pd->speed;
1da177e4
LT		 1407 }
1408
c28a4f89
JC		 1409 /* Hook up MII support for ethtool */
1410 mp->mii.dev = dev;
1411 mp->mii.mdio_read = mv643xx_mdio_read;
1412 mp->mii.mdio_write = mv643xx_mdio_write;
1413 mp->mii.phy_id = ethernet_phy_get(port_num);
1414 mp->mii.phy_id_mask = 0x3f;
1415 mp->mii.reg_num_mask = 0x1f;
1416
1da177e4
LT		 1417 err = ethernet_phy_detect(port_num);
1418 if (err) {
1419 pr_debug("MV643xx ethernet port %d: "
1420 "No PHY detected at addr %d\n",
1421 port_num, ethernet_phy_get(port_num));
d0412d96 1422 goto out;
1da177e4
LT		 1423 }
1424
01999873 1425 ethernet_phy_reset(port_num);
c28a4f89 1426 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
d0412d96
JC		 1427 mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd);
1428 mv643xx_eth_update_pscr(dev, &cmd);
1429 mv643xx_set_settings(dev, &cmd);
c28a4f89 1430
b0b8dab2
OH		 1431 SET_MODULE_OWNER(dev);
1432 SET_NETDEV_DEV(dev, &pdev->dev);
1da177e4
LT		 1433 err = register_netdev(dev);
1434 if (err)
1435 goto out;
1436
1437 p = dev->dev_addr;
1438 printk(KERN_NOTICE
1439 "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
1440 dev->name, port_num, p[0], p[1], p[2], p[3], p[4], p[5]);
1441
1442 if (dev->features & NETIF_F_SG)
1443 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
1444
1445 if (dev->features & NETIF_F_IP_CSUM)
1446 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
1447 dev->name);
1448
1449#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1450 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
1451#endif
1452
1453#ifdef MV643XX_COAL
1454 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
1455 dev->name);
1456#endif
1457
1458#ifdef MV643XX_NAPI
1459 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
1460#endif
1461
b1529871
ND		 1462 if (mp->tx_sram_size > 0)
1463 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
1464
1da177e4
LT		 1465 return 0;
1466
1467out:
1468 free_netdev(dev);
1469
1470 return err;
1471}
1472
3ae5eaec 1473static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 1474{
3ae5eaec 1475 struct net_device *dev = platform_get_drvdata(pdev);
1da177e4
LT		 1476
1477 unregister_netdev(dev);
1478 flush_scheduled_work();
1479
1480 free_netdev(dev);
3ae5eaec 1481 platform_set_drvdata(pdev, NULL);
1da177e4
LT		 1482 return 0;
1483}
1484
3ae5eaec 1485static int mv643xx_eth_shared_probe(struct platform_device *pdev)
1da177e4 1486{
1da177e4
LT		 1487 struct resource *res;
1488
1489 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
1490
1491 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1492 if (res == NULL)
1493 return -ENODEV;
1494
1495 mv643xx_eth_shared_base = ioremap(res->start,
1496 MV643XX_ETH_SHARED_REGS_SIZE);
1497 if (mv643xx_eth_shared_base == NULL)
1498 return -ENOMEM;
1499
1500 return 0;
1501
1502}
1503
3ae5eaec 1504static int mv643xx_eth_shared_remove(struct platform_device *pdev)
1da177e4
LT		 1505{
1506 iounmap(mv643xx_eth_shared_base);
1507 mv643xx_eth_shared_base = NULL;
1508
1509 return 0;
1510}
1511
3ae5eaec 1512static struct platform_driver mv643xx_eth_driver = {
1da177e4
LT		 1513 .probe = mv643xx_eth_probe,
1514 .remove = mv643xx_eth_remove,
3ae5eaec
RK		 1515 .driver = {
1516 .name = MV643XX_ETH_NAME,
1517 },
1da177e4
LT		 1518};
1519
3ae5eaec 1520static struct platform_driver mv643xx_eth_shared_driver = {
1da177e4
LT		 1521 .probe = mv643xx_eth_shared_probe,
1522 .remove = mv643xx_eth_shared_remove,
3ae5eaec
RK		 1523 .driver = {
1524 .name = MV643XX_ETH_SHARED_NAME,
1525 },
1da177e4
LT		 1526};
1527
1528/*
1529 * mv643xx_init_module
1530 *
1531 * Registers the network drivers into the Linux kernel
1532 *
1533 * Input : N/A
1534 *
1535 * Output : N/A
1536 */
1537static int __init mv643xx_init_module(void)
1538{
1539 int rc;
1540
3ae5eaec 1541 rc = platform_driver_register(&mv643xx_eth_shared_driver);
1da177e4 1542 if (!rc) {
3ae5eaec 1543 rc = platform_driver_register(&mv643xx_eth_driver);
1da177e4 1544 if (rc)
3ae5eaec 1545 platform_driver_unregister(&mv643xx_eth_shared_driver);
1da177e4
LT		 1546 }
1547 return rc;
1548}
1549
1550/*
1551 * mv643xx_cleanup_module
1552 *
1553 * Registers the network drivers into the Linux kernel
1554 *
1555 * Input : N/A
1556 *
1557 * Output : N/A
1558 */
1559static void __exit mv643xx_cleanup_module(void)
1560{
3ae5eaec
RK		 1561 platform_driver_unregister(&mv643xx_eth_driver);
1562 platform_driver_unregister(&mv643xx_eth_shared_driver);
1da177e4
LT		 1563}
1564
1565module_init(mv643xx_init_module);
1566module_exit(mv643xx_cleanup_module);
1567
1568MODULE_LICENSE("GPL");
1569MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
1570 " and Dale Farnsworth");
1571MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
1572
1573/*
1574 * The second part is the low level driver of the gigE ethernet ports.
1575 */
1576
1577/*
1578 * Marvell's Gigabit Ethernet controller low level driver
1579 *
1580 * DESCRIPTION:
1581 * This file introduce low level API to Marvell's Gigabit Ethernet
1582 * controller. This Gigabit Ethernet Controller driver API controls
1583 * 1) Operations (i.e. port init, start, reset etc').
1584 * 2) Data flow (i.e. port send, receive etc').
1585 * Each Gigabit Ethernet port is controlled via
1586 * struct mv643xx_private.
1587 * This struct includes user configuration information as well as
1588 * driver internal data needed for its operations.
1589 *
1590 * Supported Features:
1591 * - This low level driver is OS independent. Allocating memory for
1592 * the descriptor rings and buffers are not within the scope of
1593 * this driver.
1594 * - The user is free from Rx/Tx queue managing.
1595 * - This low level driver introduce functionality API that enable
1596 * the to operate Marvell's Gigabit Ethernet Controller in a
1597 * convenient way.
1598 * - Simple Gigabit Ethernet port operation API.
1599 * - Simple Gigabit Ethernet port data flow API.
1600 * - Data flow and operation API support per queue functionality.
1601 * - Support cached descriptors for better performance.
1602 * - Enable access to all four DRAM banks and internal SRAM memory
1603 * spaces.
1604 * - PHY access and control API.
1605 * - Port control register configuration API.
1606 * - Full control over Unicast and Multicast MAC configurations.
1607 *
1608 * Operation flow:
1609 *
1610 * Initialization phase
1611 * This phase complete the initialization of the the
1612 * mv643xx_private struct.
1613 * User information regarding port configuration has to be set
1614 * prior to calling the port initialization routine.
1615 *
1616 * In this phase any port Tx/Rx activity is halted, MIB counters
1617 * are cleared, PHY address is set according to user parameter and
1618 * access to DRAM and internal SRAM memory spaces.
1619 *
1620 * Driver ring initialization
1621 * Allocating memory for the descriptor rings and buffers is not
1622 * within the scope of this driver. Thus, the user is required to
1623 * allocate memory for the descriptors ring and buffers. Those
1624 * memory parameters are used by the Rx and Tx ring initialization
1625 * routines in order to curve the descriptor linked list in a form
1626 * of a ring.
1627 * Note: Pay special attention to alignment issues when using
1628 * cached descriptors/buffers. In this phase the driver store
1629 * information in the mv643xx_private struct regarding each queue
1630 * ring.
1631 *
1632 * Driver start
1633 * This phase prepares the Ethernet port for Rx and Tx activity.
1634 * It uses the information stored in the mv643xx_private struct to
1635 * initialize the various port registers.
1636 *
1637 * Data flow:
1638 * All packet references to/from the driver are done using
1639 * struct pkt_info.
1640 * This struct is a unified struct used with Rx and Tx operations.
1641 * This way the user is not required to be familiar with neither
1642 * Tx nor Rx descriptors structures.
1643 * The driver's descriptors rings are management by indexes.
1644 * Those indexes controls the ring resources and used to indicate
1645 * a SW resource error:
1646 * 'current'
1647 * This index points to the current available resource for use. For
1648 * example in Rx process this index will point to the descriptor
1649 * that will be passed to the user upon calling the receive
1650 * routine. In Tx process, this index will point to the descriptor
1651 * that will be assigned with the user packet info and transmitted.
1652 * 'used'
1653 * This index points to the descriptor that need to restore its
1654 * resources. For example in Rx process, using the Rx buffer return
1655 * API will attach the buffer returned in packet info to the
1656 * descriptor pointed by 'used'. In Tx process, using the Tx
1657 * descriptor return will merely return the user packet info with
1658 * the command status of the transmitted buffer pointed by the
1659 * 'used' index. Nevertheless, it is essential to use this routine
1660 * to update the 'used' index.
1661 * 'first'
1662 * This index supports Tx Scatter-Gather. It points to the first
1663 * descriptor of a packet assembled of multiple buffers. For
1664 * example when in middle of Such packet we have a Tx resource
1665 * error the 'curr' index get the value of 'first' to indicate
1666 * that the ring returned to its state before trying to transmit
1667 * this packet.
1668 *
1669 * Receive operation:
1670 * The eth_port_receive API set the packet information struct,
1671 * passed by the caller, with received information from the
1672 * 'current' SDMA descriptor.
1673 * It is the user responsibility to return this resource back
1674 * to the Rx descriptor ring to enable the reuse of this source.
1675 * Return Rx resource is done using the eth_rx_return_buff API.
1676 *
1da177e4
LT		 1677 * Prior to calling the initialization routine eth_port_init() the user
1678 * must set the following fields under mv643xx_private struct:
1679 * port_num User Ethernet port number.
1da177e4
LT		 1680 * port_config User port configuration value.
1681 * port_config_extend User port config extend value.
1682 * port_sdma_config User port SDMA config value.
1683 * port_serial_control User port serial control value.
1684 *
1685 * This driver data flow is done using the struct pkt_info which
1686 * is a unified struct for Rx and Tx operations:
1687 *
1688 * byte_cnt Tx/Rx descriptor buffer byte count.
1689 * l4i_chk CPU provided TCP Checksum. For Tx operation
1690 * only.
1691 * cmd_sts Tx/Rx descriptor command status.
1692 * buf_ptr Tx/Rx descriptor buffer pointer.
1693 * return_info Tx/Rx user resource return information.
1694 */
1695
1da177e4
LT		 1696/* PHY routines */
1697static int ethernet_phy_get(unsigned int eth_port_num);
1698static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
1699
1700/* Ethernet Port routines */
cf4086c7 1701static void eth_port_set_filter_table_entry(int table, unsigned char entry);
1da177e4
LT		 1702
1703/*
1704 * eth_port_init - Initialize the Ethernet port driver
1705 *
1706 * DESCRIPTION:
1707 * This function prepares the ethernet port to start its activity:
1708 * 1) Completes the ethernet port driver struct initialization toward port
1709 * start routine.
1710 * 2) Resets the device to a quiescent state in case of warm reboot.
1711 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1712 * 4) Clean MAC tables. The reset status of those tables is unknown.
1713 * 5) Set PHY address.
1714 * Note: Call this routine prior to eth_port_start routine and after
1715 * setting user values in the user fields of Ethernet port control
1716 * struct.
1717 *
1718 * INPUT:
1719 * struct mv643xx_private *mp Ethernet port control struct
1720 *
1721 * OUTPUT:
1722 * See description.
1723 *
1724 * RETURN:
1725 * None.
1726 */
1727static void eth_port_init(struct mv643xx_private *mp)
1728{
1da177e4 1729 mp->rx_resource_err = 0;
1da177e4
LT		 1730
1731 eth_port_reset(mp->port_num);
1732
1733 eth_port_init_mac_tables(mp->port_num);
1da177e4
LT		 1734}
1735
1736/*
1737 * eth_port_start - Start the Ethernet port activity.
1738 *
1739 * DESCRIPTION:
1740 * This routine prepares the Ethernet port for Rx and Tx activity:
1741 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1742 * has been initialized a descriptor's ring (using
1743 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
1744 * 2. Initialize and enable the Ethernet configuration port by writing to
1745 * the port's configuration and command registers.
1746 * 3. Initialize and enable the SDMA by writing to the SDMA's
1747 * configuration and command registers. After completing these steps,
1748 * the ethernet port SDMA can starts to perform Rx and Tx activities.
1749 *
1750 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1751 * to calling this function (use ether_init_tx_desc_ring for Tx queues
1752 * and ether_init_rx_desc_ring for Rx queues).
1753 *
1754 * INPUT:
ed9b5d45 1755 * dev - a pointer to the required interface
1da177e4
LT		 1756 *
1757 * OUTPUT:
1758 * Ethernet port is ready to receive and transmit.
1759 *
1760 * RETURN:
1761 * None.
1762 */
ed9b5d45 1763static void eth_port_start(struct net_device *dev)
1da177e4 1764{
ed9b5d45 1765 struct mv643xx_private *mp = netdev_priv(dev);
1da177e4
LT		 1766 unsigned int port_num = mp->port_num;
1767 int tx_curr_desc, rx_curr_desc;
d0412d96
JC		 1768 u32 pscr;
1769 struct ethtool_cmd ethtool_cmd;
1da177e4
LT		 1770
1771 /* Assignment of Tx CTRP of given queue */
1772 tx_curr_desc = mp->tx_curr_desc_q;
1773 mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1774 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
1775
1776 /* Assignment of Rx CRDP of given queue */
1777 rx_curr_desc = mp->rx_curr_desc_q;
1778 mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1779 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
1780
1781 /* Add the assigned Ethernet address to the port's address table */
ed9b5d45 1782 eth_port_uc_addr_set(port_num, dev->dev_addr);
1da177e4
LT		 1783
1784 /* Assign port configuration and command. */
01999873
DF		 1785 mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num),
1786 MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE);
1787
1788 mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num),
1789 MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE);
1da177e4 1790
d0412d96 1791 pscr = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
01999873
DF		 1792
1793 pscr &= ~(MV643XX_ETH_SERIAL_PORT_ENABLE | MV643XX_ETH_FORCE_LINK_PASS);
d0412d96 1794 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr);
1da177e4 1795
d0412d96
JC		 1796 pscr |= MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1797 MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII |
1798 MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX |
1799 MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL |
1800 MV643XX_ETH_SERIAL_PORT_CONTROL_RESERVED;
1da177e4 1801
d0412d96 1802 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr);
1da177e4 1803
d0412d96
JC		 1804 pscr |= MV643XX_ETH_SERIAL_PORT_ENABLE;
1805 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr);
1da177e4
LT		 1806
1807 /* Assign port SDMA configuration */
01999873
DF		 1808 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num),
1809 MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE);
1da177e4
LT		 1810
1811 /* Enable port Rx. */
ff561eef 1812 mv643xx_eth_port_enable_rx(port_num, ETH_RX_QUEUES_ENABLED);
8f543718
DF		 1813
1814 /* Disable port bandwidth limits by clearing MTU register */
1815 mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num), 0);
d0412d96
JC		 1816
1817 /* save phy settings across reset */
1818 mv643xx_get_settings(dev, &ethtool_cmd);
1819 ethernet_phy_reset(mp->port_num);
1820 mv643xx_set_settings(dev, &ethtool_cmd);
1da177e4
LT		 1821}
1822
1823/*
1824 * eth_port_uc_addr_set - This function Set the port Unicast address.
1825 *
1826 * DESCRIPTION:
1827 * This function Set the port Ethernet MAC address.
1828 *
1829 * INPUT:
1830 * unsigned int eth_port_num Port number.
1831 * char * p_addr Address to be set
1832 *
1833 * OUTPUT:
cf4086c7
DF		 1834 * Set MAC address low and high registers. also calls
1835 * eth_port_set_filter_table_entry() to set the unicast
1836 * table with the proper information.
1da177e4
LT		 1837 *
1838 * RETURN:
1839 * N/A.
1840 *
1841 */
1842static void eth_port_uc_addr_set(unsigned int eth_port_num,
1843 unsigned char *p_addr)
1844{
1845 unsigned int mac_h;
1846 unsigned int mac_l;
cf4086c7 1847 int table;
1da177e4
LT		 1848
1849 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1850 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
1851 (p_addr[3] << 0);
1852
1853 mv_write(MV643XX_ETH_MAC_ADDR_LOW(eth_port_num), mac_l);
1854 mv_write(MV643XX_ETH_MAC_ADDR_HIGH(eth_port_num), mac_h);
1855
1856 /* Accept frames of this address */
cf4086c7
DF		 1857 table = MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(eth_port_num);
1858 eth_port_set_filter_table_entry(table, p_addr[5] & 0x0f);
1da177e4
LT		 1859}
1860
1861/*
1862 * eth_port_uc_addr_get - This function retrieves the port Unicast address
1863 * (MAC address) from the ethernet hw registers.
1864 *
1865 * DESCRIPTION:
1866 * This function retrieves the port Ethernet MAC address.
1867 *
1868 * INPUT:
1869 * unsigned int eth_port_num Port number.
1870 * char *MacAddr pointer where the MAC address is stored
1871 *
1872 * OUTPUT:
1873 * Copy the MAC address to the location pointed to by MacAddr
1874 *
1875 * RETURN:
1876 * N/A.
1877 *
1878 */
1879static void eth_port_uc_addr_get(struct net_device *dev, unsigned char *p_addr)
1880{
1881 struct mv643xx_private *mp = netdev_priv(dev);
1882 unsigned int mac_h;
1883 unsigned int mac_l;
1884
1885 mac_h = mv_read(MV643XX_ETH_MAC_ADDR_HIGH(mp->port_num));
1886 mac_l = mv_read(MV643XX_ETH_MAC_ADDR_LOW(mp->port_num));
1887
1888 p_addr[0] = (mac_h >> 24) & 0xff;
1889 p_addr[1] = (mac_h >> 16) & 0xff;
1890 p_addr[2] = (mac_h >> 8) & 0xff;
1891 p_addr[3] = mac_h & 0xff;
1892 p_addr[4] = (mac_l >> 8) & 0xff;
1893 p_addr[5] = mac_l & 0xff;
1894}
1895
16e03018
DF		 1896/*
1897 * The entries in each table are indexed by a hash of a packet's MAC
1898 * address. One bit in each entry determines whether the packet is
1899 * accepted. There are 4 entries (each 8 bits wide) in each register
1900 * of the table. The bits in each entry are defined as follows:
1901 * 0 Accept=1, Drop=0
1902 * 3-1 Queue (ETH_Q0=0)
1903 * 7-4 Reserved = 0;
1904 */
1905static void eth_port_set_filter_table_entry(int table, unsigned char entry)
1906{
1907 unsigned int table_reg;
1908 unsigned int tbl_offset;
1909 unsigned int reg_offset;
1910
1911 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
1912 reg_offset = entry % 4; /* Entry offset within the register */
1913
1914 /* Set "accepts frame bit" at specified table entry */
1915 table_reg = mv_read(table + tbl_offset);
1916 table_reg |= 0x01 << (8 * reg_offset);
1917 mv_write(table + tbl_offset, table_reg);
1918}
1919
1920/*
1921 * eth_port_mc_addr - Multicast address settings.
1922 *
1923 * The MV device supports multicast using two tables:
1924 * 1) Special Multicast Table for MAC addresses of the form
1925 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
1926 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1927 * Table entries in the DA-Filter table.
1928 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
1929 * is used as an index to the Other Multicast Table entries in the
1930 * DA-Filter table. This function calculates the CRC-8bit value.
1931 * In either case, eth_port_set_filter_table_entry() is then called
1932 * to set to set the actual table entry.
1933 */
1934static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr)
1935{
1936 unsigned int mac_h;
1937 unsigned int mac_l;
1938 unsigned char crc_result = 0;
1939 int table;
1940 int mac_array[48];
1941 int crc[8];
1942 int i;
1943
1944 if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) &&
1945 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
1946 table = MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
1947 (eth_port_num);
1948 eth_port_set_filter_table_entry(table, p_addr[5]);
1949 return;
1950 }
1951
1952 /* Calculate CRC-8 out of the given address */
1953 mac_h = (p_addr[0] << 8) | (p_addr[1]);
1954 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
1955 (p_addr[4] << 8) | (p_addr[5] << 0);
1956
1957 for (i = 0; i < 32; i++)
1958 mac_array[i] = (mac_l >> i) & 0x1;
1959 for (i = 32; i < 48; i++)
1960 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
1961
1962 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
1963 mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
1964 mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
1965 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
1966 mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0];
1967
1968 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
1969 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
1970 mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
1971 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
1972 mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
1973 mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
1974 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0];
1975
1976 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
1977 mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
1978 mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
1979 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
1980 mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^
1981 mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0];
1982
1983 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
1984 mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
1985 mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
1986 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
1987 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^
1988 mac_array[3] ^ mac_array[2] ^ mac_array[1];
1989
1990 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
1991 mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
1992 mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
1993 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
1994 mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^
1995 mac_array[3] ^ mac_array[2];
1996
1997 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
1998 mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
1999 mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
2000 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
2001 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^
2002 mac_array[4] ^ mac_array[3];
2003
2004 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
2005 mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
2006 mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
2007 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
2008 mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^
2009 mac_array[4];
2010
2011 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
2012 mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
2013 mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
2014 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
2015 mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5];
2016
2017 for (i = 0; i < 8; i++)
2018 crc_result = crc_result | (crc[i] << i);
2019
2020 table = MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num);
2021 eth_port_set_filter_table_entry(table, crc_result);
2022}
2023
2024/*
2025 * Set the entire multicast list based on dev->mc_list.
2026 */
2027static void eth_port_set_multicast_list(struct net_device *dev)
2028{
2029
2030 struct dev_mc_list *mc_list;
2031 int i;
2032 int table_index;
2033 struct mv643xx_private *mp = netdev_priv(dev);
2034 unsigned int eth_port_num = mp->port_num;
2035
2036 /* If the device is in promiscuous mode or in all multicast mode,
2037 * we will fully populate both multicast tables with accept.
2038 * This is guaranteed to yield a match on all multicast addresses...
2039 */
2040 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
2041 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
b4de9051
DF		 2042 /* Set all entries in DA filter special multicast
2043 * table (Ex_dFSMT)
2044 * Set for ETH_Q0 for now
2045 * Bits
2046 * 0 Accept=1, Drop=0
2047 * 3-1 Queue ETH_Q0=0
2048 * 7-4 Reserved = 0;
2049 */
2050 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2051
2052 /* Set all entries in DA filter other multicast
2053 * table (Ex_dFOMT)
2054 * Set for ETH_Q0 for now
2055 * Bits
2056 * 0 Accept=1, Drop=0
2057 * 3-1 Queue ETH_Q0=0
2058 * 7-4 Reserved = 0;
2059 */
2060 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2061 }
16e03018
DF		 2062 return;
2063 }
2064
2065 /* We will clear out multicast tables every time we get the list.
2066 * Then add the entire new list...
2067 */
2068 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2069 /* Clear DA filter special multicast table (Ex_dFSMT) */
2070 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2071 (eth_port_num) + table_index, 0);
2072
2073 /* Clear DA filter other multicast table (Ex_dFOMT) */
2074 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2075 (eth_port_num) + table_index, 0);
2076 }
2077
2078 /* Get pointer to net_device multicast list and add each one... */
2079 for (i = 0, mc_list = dev->mc_list;
2080 (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
2081 i++, mc_list = mc_list->next)
2082 if (mc_list->dmi_addrlen == 6)
2083 eth_port_mc_addr(eth_port_num, mc_list->dmi_addr);
2084}
2085
1da177e4
LT		 2086/*
2087 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2088 *
2089 * DESCRIPTION:
2090 * Go through all the DA filter tables (Unicast, Special Multicast &
2091 * Other Multicast) and set each entry to 0.
2092 *
2093 * INPUT:
2094 * unsigned int eth_port_num Ethernet Port number.
2095 *
2096 * OUTPUT:
2097 * Multicast and Unicast packets are rejected.
2098 *
2099 * RETURN:
2100 * None.
2101 */
2102static void eth_port_init_mac_tables(unsigned int eth_port_num)
2103{
2104 int table_index;
2105
2106 /* Clear DA filter unicast table (Ex_dFUT) */
2107 for (table_index = 0; table_index <= 0xC; table_index += 4)
cf4086c7
DF		 2108 mv_write(MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2109 (eth_port_num) + table_index, 0);
1da177e4
LT		 2110
2111 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2112 /* Clear DA filter special multicast table (Ex_dFSMT) */
16e03018
DF		 2113 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2114 (eth_port_num) + table_index, 0);
1da177e4 2115 /* Clear DA filter other multicast table (Ex_dFOMT) */
16e03018
DF		 2116 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2117 (eth_port_num) + table_index, 0);
1da177e4
LT		 2118 }
2119}
2120
2121/*
2122 * eth_clear_mib_counters - Clear all MIB counters
2123 *
2124 * DESCRIPTION:
2125 * This function clears all MIB counters of a specific ethernet port.
2126 * A read from the MIB counter will reset the counter.
2127 *
2128 * INPUT:
2129 * unsigned int eth_port_num Ethernet Port number.
2130 *
2131 * OUTPUT:
2132 * After reading all MIB counters, the counters resets.
2133 *
2134 * RETURN:
2135 * MIB counter value.
2136 *
2137 */
2138static void eth_clear_mib_counters(unsigned int eth_port_num)
2139{
2140 int i;
2141
2142 /* Perform dummy reads from MIB counters */
2143 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2144 i += 4)
2145 mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num) + i);
2146}
2147
2148static inline u32 read_mib(struct mv643xx_private *mp, int offset)
2149{
2150 return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp->port_num) + offset);
2151}
2152
2153static void eth_update_mib_counters(struct mv643xx_private *mp)
2154{
2155 struct mv643xx_mib_counters *p = &mp->mib_counters;
2156 int offset;
2157
2158 p->good_octets_received +=
2159 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
2160 p->good_octets_received +=
2161 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
2162
2163 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
2164 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
2165 offset += 4)
70fbf327 2166 *(u32 *)((char *)p + offset) += read_mib(mp, offset);
1da177e4
LT		 2167
2168 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
2169 p->good_octets_sent +=
2170 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
2171
2172 for (offset = ETH_MIB_GOOD_FRAMES_SENT;
2173 offset <= ETH_MIB_LATE_COLLISION;
2174 offset += 4)
70fbf327 2175 *(u32 *)((char *)p + offset) += read_mib(mp, offset);
1da177e4
LT		 2176}
2177
2178/*
2179 * ethernet_phy_detect - Detect whether a phy is present
2180 *
2181 * DESCRIPTION:
2182 * This function tests whether there is a PHY present on
2183 * the specified port.
2184 *
2185 * INPUT:
2186 * unsigned int eth_port_num Ethernet Port number.
2187 *
2188 * OUTPUT:
2189 * None
2190 *
2191 * RETURN:
2192 * 0 on success
2193 * -ENODEV on failure
2194 *
2195 */
2196static int ethernet_phy_detect(unsigned int port_num)
2197{
2198 unsigned int phy_reg_data0;
2199 int auto_neg;
2200
2201 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2202 auto_neg = phy_reg_data0 & 0x1000;
2203 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2204 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2205
2206 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2207 if ((phy_reg_data0 & 0x1000) == auto_neg)
2208 return -ENODEV; /* change didn't take */
2209
2210 phy_reg_data0 ^= 0x1000;
2211 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2212 return 0;
2213}
2214
2215/*
2216 * ethernet_phy_get - Get the ethernet port PHY address.
2217 *
2218 * DESCRIPTION:
2219 * This routine returns the given ethernet port PHY address.
2220 *
2221 * INPUT:
2222 * unsigned int eth_port_num Ethernet Port number.
2223 *
2224 * OUTPUT:
2225 * None.
2226 *
2227 * RETURN:
2228 * PHY address.
2229 *
2230 */
2231static int ethernet_phy_get(unsigned int eth_port_num)
2232{
2233 unsigned int reg_data;
2234
2235 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2236
2237 return ((reg_data >> (5 * eth_port_num)) & 0x1f);
2238}
2239
2240/*
2241 * ethernet_phy_set - Set the ethernet port PHY address.
2242 *
2243 * DESCRIPTION:
2244 * This routine sets the given ethernet port PHY address.
2245 *
2246 * INPUT:
2247 * unsigned int eth_port_num Ethernet Port number.
2248 * int phy_addr PHY address.
2249 *
2250 * OUTPUT:
2251 * None.
2252 *
2253 * RETURN:
2254 * None.
2255 *
2256 */
2257static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr)
2258{
2259 u32 reg_data;
2260 int addr_shift = 5 * eth_port_num;
2261
2262 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2263 reg_data &= ~(0x1f << addr_shift);
2264 reg_data |= (phy_addr & 0x1f) << addr_shift;
2265 mv_write(MV643XX_ETH_PHY_ADDR_REG, reg_data);
2266}
2267
2268/*
2269 * ethernet_phy_reset - Reset Ethernet port PHY.
2270 *
2271 * DESCRIPTION:
2272 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2273 *
2274 * INPUT:
2275 * unsigned int eth_port_num Ethernet Port number.
2276 *
2277 * OUTPUT:
2278 * The PHY is reset.
2279 *
2280 * RETURN:
2281 * None.
2282 *
2283 */
2284static void ethernet_phy_reset(unsigned int eth_port_num)
2285{
2286 unsigned int phy_reg_data;
2287
2288 /* Reset the PHY */
2289 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
2290 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2291 eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data);
d0412d96
JC		 2292
2293 /* wait for PHY to come out of reset */
2294 do {
2295 udelay(1);
2296 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
2297 } while (phy_reg_data & 0x8000);
1da177e4
LT		 2298}
2299
9f8dd319 2300static void mv643xx_eth_port_enable_tx(unsigned int port_num,
12a87c64 2301 unsigned int queues)
9f8dd319 2302{
12a87c64 2303 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), queues);
9f8dd319
DF		 2304}
2305
2306static void mv643xx_eth_port_enable_rx(unsigned int port_num,
12a87c64 2307 unsigned int queues)
9f8dd319 2308{
12a87c64 2309 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), queues);
9f8dd319
DF		 2310}
2311
2312static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num)
2313{
12a87c64 2314 u32 queues;
9f8dd319
DF		 2315
2316 /* Stop Tx port activity. Check port Tx activity. */
12a87c64 2317 queues = mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
9f8dd319 2318 & 0xFF;
12a87c64
DF		 2319 if (queues) {
2320 /* Issue stop command for active queues only */
9f8dd319 2321 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num),
12a87c64 2322 (queues << 8));
9f8dd319
DF		 2323
2324 /* Wait for all Tx activity to terminate. */
2325 /* Check port cause register that all Tx queues are stopped */
2326 while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
2327 & 0xFF)
2328 udelay(PHY_WAIT_MICRO_SECONDS);
2329
2330 /* Wait for Tx FIFO to empty */
2331 while (mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num)) &
2332 ETH_PORT_TX_FIFO_EMPTY)
2333 udelay(PHY_WAIT_MICRO_SECONDS);
2334 }
2335
12a87c64 2336 return queues;
9f8dd319
DF		 2337}
2338
2339static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num)
2340{
12a87c64 2341 u32 queues;
9f8dd319
DF		 2342
2343 /* Stop Rx port activity. Check port Rx activity. */
12a87c64 2344 queues = mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
e38fd1a0 2345 & 0xFF;
12a87c64
DF		 2346 if (queues) {
2347 /* Issue stop command for active queues only */
9f8dd319 2348 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
12a87c64 2349 (queues << 8));
9f8dd319
DF		 2350
2351 /* Wait for all Rx activity to terminate. */
2352 /* Check port cause register that all Rx queues are stopped */
2353 while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
2354 & 0xFF)
2355 udelay(PHY_WAIT_MICRO_SECONDS);
2356 }
2357
12a87c64 2358 return queues;
9f8dd319
DF		 2359}
2360
1da177e4
LT		 2361/*
2362 * eth_port_reset - Reset Ethernet port
2363 *
2364 * DESCRIPTION:
2365 * This routine resets the chip by aborting any SDMA engine activity and
2366 * clearing the MIB counters. The Receiver and the Transmit unit are in
2367 * idle state after this command is performed and the port is disabled.
2368 *
2369 * INPUT:
2370 * unsigned int eth_port_num Ethernet Port number.
2371 *
2372 * OUTPUT:
2373 * Channel activity is halted.
2374 *
2375 * RETURN:
2376 * None.
2377 *
2378 */
2379static void eth_port_reset(unsigned int port_num)
2380{
2381 unsigned int reg_data;
2382
9f8dd319
DF		 2383 mv643xx_eth_port_disable_tx(port_num);
2384 mv643xx_eth_port_disable_rx(port_num);
1da177e4
LT		 2385
2386 /* Clear all MIB counters */
2387 eth_clear_mib_counters(port_num);
2388
2389 /* Reset the Enable bit in the Configuration Register */
2390 reg_data = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
d0412d96
JC		 2391 reg_data &= ~(MV643XX_ETH_SERIAL_PORT_ENABLE |
2392 MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL |
2393 MV643XX_ETH_FORCE_LINK_PASS);
1da177e4
LT		 2394 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), reg_data);
2395}
2396
1da177e4 2397
1da177e4
LT		 2398/*
2399 * eth_port_read_smi_reg - Read PHY registers
2400 *
2401 * DESCRIPTION:
2402 * This routine utilize the SMI interface to interact with the PHY in
2403 * order to perform PHY register read.
2404 *
2405 * INPUT:
2406 * unsigned int port_num Ethernet Port number.
2407 * unsigned int phy_reg PHY register address offset.
2408 * unsigned int *value Register value buffer.
2409 *
2410 * OUTPUT:
2411 * Write the value of a specified PHY register into given buffer.
2412 *
2413 * RETURN:
2414 * false if the PHY is busy or read data is not in valid state.
2415 * true otherwise.
2416 *
2417 */
2418static void eth_port_read_smi_reg(unsigned int port_num,
2419 unsigned int phy_reg, unsigned int *value)
2420{
2421 int phy_addr = ethernet_phy_get(port_num);
2422 unsigned long flags;
2423 int i;
2424
2425 /* the SMI register is a shared resource */
2426 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2427
2428 /* wait for the SMI register to become available */
2429 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2430 if (i == PHY_WAIT_ITERATIONS) {
2431 printk("mv643xx PHY busy timeout, port %d\n", port_num);
2432 goto out;
2433 }
2434 udelay(PHY_WAIT_MICRO_SECONDS);
2435 }
2436
2437 mv_write(MV643XX_ETH_SMI_REG,
2438 (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);
2439
2440 /* now wait for the data to be valid */
2441 for (i = 0; !(mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_READ_VALID); i++) {
2442 if (i == PHY_WAIT_ITERATIONS) {
2443 printk("mv643xx PHY read timeout, port %d\n", port_num);
2444 goto out;
2445 }
2446 udelay(PHY_WAIT_MICRO_SECONDS);
2447 }
2448
2449 *value = mv_read(MV643XX_ETH_SMI_REG) & 0xffff;
2450out:
2451 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2452}
2453
2454/*
2455 * eth_port_write_smi_reg - Write to PHY registers
2456 *
2457 * DESCRIPTION:
2458 * This routine utilize the SMI interface to interact with the PHY in
2459 * order to perform writes to PHY registers.
2460 *
2461 * INPUT:
2462 * unsigned int eth_port_num Ethernet Port number.
2463 * unsigned int phy_reg PHY register address offset.
2464 * unsigned int value Register value.
2465 *
2466 * OUTPUT:
2467 * Write the given value to the specified PHY register.
2468 *
2469 * RETURN:
2470 * false if the PHY is busy.
2471 * true otherwise.
2472 *
2473 */
2474static void eth_port_write_smi_reg(unsigned int eth_port_num,
2475 unsigned int phy_reg, unsigned int value)
2476{
2477 int phy_addr;
2478 int i;
2479 unsigned long flags;
2480
2481 phy_addr = ethernet_phy_get(eth_port_num);
2482
2483 /* the SMI register is a shared resource */
2484 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2485
2486 /* wait for the SMI register to become available */
2487 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2488 if (i == PHY_WAIT_ITERATIONS) {
2489 printk("mv643xx PHY busy timeout, port %d\n",
2490 eth_port_num);
2491 goto out;
2492 }
2493 udelay(PHY_WAIT_MICRO_SECONDS);
2494 }
2495
2496 mv_write(MV643XX_ETH_SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
2497 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2498out:
2499 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2500}
2501
c28a4f89
JC		 2502/*
2503 * Wrappers for MII support library.
2504 */
2505static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location)
2506{
2507 int val;
2508 struct mv643xx_private *mp = netdev_priv(dev);
2509
2510 eth_port_read_smi_reg(mp->port_num, location, &val);
2511 return val;
2512}
2513
2514static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val)
2515{
2516 struct mv643xx_private *mp = netdev_priv(dev);
2517 eth_port_write_smi_reg(mp->port_num, location, val);
2518}
2519
1da177e4
LT		 2520/*
2521 * eth_port_receive - Get received information from Rx ring.
2522 *
2523 * DESCRIPTION:
2524 * This routine returns the received data to the caller. There is no
2525 * data copying during routine operation. All information is returned
2526 * using pointer to packet information struct passed from the caller.
2527 * If the routine exhausts Rx ring resources then the resource error flag
2528 * is set.
2529 *
2530 * INPUT:
2531 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2532 * struct pkt_info *p_pkt_info User packet buffer.
2533 *
2534 * OUTPUT:
2535 * Rx ring current and used indexes are updated.
2536 *
2537 * RETURN:
2538 * ETH_ERROR in case the routine can not access Rx desc ring.
2539 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
2540 * ETH_END_OF_JOB if there is no received data.
2541 * ETH_OK otherwise.
2542 */
2543static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
2544 struct pkt_info *p_pkt_info)
2545{
2546 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
2547 volatile struct eth_rx_desc *p_rx_desc;
2548 unsigned int command_status;
8f518703 2549 unsigned long flags;
1da177e4
LT		 2550
2551 /* Do not process Rx ring in case of Rx ring resource error */
2552 if (mp->rx_resource_err)
2553 return ETH_QUEUE_FULL;
2554
8f518703
DF		 2555 spin_lock_irqsave(&mp->lock, flags);
2556
1da177e4
LT		 2557 /* Get the Rx Desc ring 'curr and 'used' indexes */
2558 rx_curr_desc = mp->rx_curr_desc_q;
2559 rx_used_desc = mp->rx_used_desc_q;
2560
2561 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];
2562
2563 /* The following parameters are used to save readings from memory */
2564 command_status = p_rx_desc->cmd_sts;
2565 rmb();
2566
2567 /* Nothing to receive... */
8f518703
DF		 2568 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2569 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 2570 return ETH_END_OF_JOB;
8f518703 2571 }
1da177e4
LT		 2572
2573 p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET;
2574 p_pkt_info->cmd_sts = command_status;
2575 p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET;
2576 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
2577 p_pkt_info->l4i_chk = p_rx_desc->buf_size;
2578
b4de9051
DF		 2579 /*
2580 * Clean the return info field to indicate that the
2581 * packet has been moved to the upper layers
2582 */
1da177e4
LT		 2583 mp->rx_skb[rx_curr_desc] = NULL;
2584
2585 /* Update current index in data structure */
2586 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
2587 mp->rx_curr_desc_q = rx_next_curr_desc;
2588
2589 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
2590 if (rx_next_curr_desc == rx_used_desc)
2591 mp->rx_resource_err = 1;
2592
8f518703
DF		 2593 spin_unlock_irqrestore(&mp->lock, flags);
2594
1da177e4
LT		 2595 return ETH_OK;
2596}
2597
2598/*
2599 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
2600 *
2601 * DESCRIPTION:
2602 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
2603 * next 'used' descriptor and attached the returned buffer to it.
2604 * In case the Rx ring was in "resource error" condition, where there are
2605 * no available Rx resources, the function resets the resource error flag.
2606 *
2607 * INPUT:
2608 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2609 * struct pkt_info *p_pkt_info Information on returned buffer.
2610 *
2611 * OUTPUT:
2612 * New available Rx resource in Rx descriptor ring.
2613 *
2614 * RETURN:
2615 * ETH_ERROR in case the routine can not access Rx desc ring.
2616 * ETH_OK otherwise.
2617 */
2618static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
2619 struct pkt_info *p_pkt_info)
2620{
2621 int used_rx_desc; /* Where to return Rx resource */
2622 volatile struct eth_rx_desc *p_used_rx_desc;
8f518703
DF		 2623 unsigned long flags;
2624
2625 spin_lock_irqsave(&mp->lock, flags);
1da177e4
LT		 2626
2627 /* Get 'used' Rx descriptor */
2628 used_rx_desc = mp->rx_used_desc_q;
2629 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];
2630
2631 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
2632 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
2633 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
2634
2635 /* Flush the write pipe */
2636
2637 /* Return the descriptor to DMA ownership */
2638 wmb();
2639 p_used_rx_desc->cmd_sts =
2640 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
2641 wmb();
2642
2643 /* Move the used descriptor pointer to the next descriptor */
2644 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;
2645
2646 /* Any Rx return cancels the Rx resource error status */
2647 mp->rx_resource_err = 0;
2648
8f518703
DF		 2649 spin_unlock_irqrestore(&mp->lock, flags);
2650
1da177e4
LT		 2651 return ETH_OK;
2652}
2653
2654/************* Begin ethtool support *************************/
2655
2656struct mv643xx_stats {
2657 char stat_string[ETH_GSTRING_LEN];
2658 int sizeof_stat;
2659 int stat_offset;
2660};
2661
2662#define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \
b4de9051 2663 offsetof(struct mv643xx_private, m)
1da177e4
LT		 2664
2665static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
2666 { "rx_packets", MV643XX_STAT(stats.rx_packets) },
2667 { "tx_packets", MV643XX_STAT(stats.tx_packets) },
2668 { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
2669 { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
2670 { "rx_errors", MV643XX_STAT(stats.rx_errors) },
2671 { "tx_errors", MV643XX_STAT(stats.tx_errors) },
2672 { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
2673 { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
2674 { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
2675 { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
2676 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
2677 { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
2678 { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
2679 { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
2680 { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
2681 { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
2682 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
2683 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
2684 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
2685 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
2686 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
2687 { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
2688 { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
2689 { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
2690 { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
2691 { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
2692 { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
2693 { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
2694 { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
2695 { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
2696 { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
2697 { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
2698 { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
2699 { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
2700 { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
2701 { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
2702 { "collision", MV643XX_STAT(mib_counters.collision) },
2703 { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
2704};
2705
2706#define MV643XX_STATS_LEN \
2707 sizeof(mv643xx_gstrings_stats) / sizeof(struct mv643xx_stats)
2708
b4de9051
DF		 2709static void mv643xx_get_drvinfo(struct net_device *netdev,
2710 struct ethtool_drvinfo *drvinfo)
1da177e4
LT		 2711{
2712 strncpy(drvinfo->driver, mv643xx_driver_name, 32);
2713 strncpy(drvinfo->version, mv643xx_driver_version, 32);
2714 strncpy(drvinfo->fw_version, "N/A", 32);
2715 strncpy(drvinfo->bus_info, "mv643xx", 32);
2716 drvinfo->n_stats = MV643XX_STATS_LEN;
2717}
2718
b4de9051 2719static int mv643xx_get_stats_count(struct net_device *netdev)
1da177e4
LT		 2720{
2721 return MV643XX_STATS_LEN;
2722}
2723
b4de9051
DF		 2724static void mv643xx_get_ethtool_stats(struct net_device *netdev,
2725 struct ethtool_stats *stats, uint64_t *data)
1da177e4
LT		 2726{
2727 struct mv643xx_private *mp = netdev->priv;
2728 int i;
2729
2730 eth_update_mib_counters(mp);
2731
b4de9051 2732 for (i = 0; i < MV643XX_STATS_LEN; i++) {
6aa20a22 2733 char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset;
b4de9051 2734 data[i] = (mv643xx_gstrings_stats[i].sizeof_stat ==
1da177e4
LT		 2735 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
2736 }
2737}
2738
b4de9051
DF		 2739static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset,
2740 uint8_t *data)
1da177e4
LT		 2741{
2742 int i;
2743
2744 switch(stringset) {
2745 case ETH_SS_STATS:
2746 for (i=0; i < MV643XX_STATS_LEN; i++) {
b4de9051
DF		 2747 memcpy(data + i * ETH_GSTRING_LEN,
2748 mv643xx_gstrings_stats[i].stat_string,
2749 ETH_GSTRING_LEN);
1da177e4
LT		 2750 }
2751 break;
2752 }
2753}
2754
d0412d96
JC		 2755static u32 mv643xx_eth_get_link(struct net_device *dev)
2756{
2757 struct mv643xx_private *mp = netdev_priv(dev);
2758
2759 return mii_link_ok(&mp->mii);
2760}
2761
2762static int mv643xx_eth_nway_restart(struct net_device *dev)
2763{
2764 struct mv643xx_private *mp = netdev_priv(dev);
2765
2766 return mii_nway_restart(&mp->mii);
2767}
2768
2769static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2770{
2771 struct mv643xx_private *mp = netdev_priv(dev);
2772
2773 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2774}
2775
7282d491 2776static const struct ethtool_ops mv643xx_ethtool_ops = {
1da177e4 2777 .get_settings = mv643xx_get_settings,
d0412d96 2778 .set_settings = mv643xx_set_settings,
1da177e4 2779 .get_drvinfo = mv643xx_get_drvinfo,
d0412d96 2780 .get_link = mv643xx_eth_get_link,
1da177e4
LT		 2781 .get_sg = ethtool_op_get_sg,
2782 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 2783 .get_stats_count = mv643xx_get_stats_count,
2784 .get_ethtool_stats = mv643xx_get_ethtool_stats,
d0412d96
JC		 2785 .get_strings = mv643xx_get_strings,
2786 .get_stats_count = mv643xx_get_stats_count,
2787 .get_ethtool_stats = mv643xx_get_ethtool_stats,
2788 .nway_reset = mv643xx_eth_nway_restart,
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LT		 2789};
2790
2791/************* End ethtool support *************************/
Linux kernel - Deliverables
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