Commit | Line | Data |
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1da177e4 | 1 | /* |
9c1bbdfe | 2 | * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports |
1da177e4 LT |
3 | * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com> |
4 | * | |
5 | * Based on the 64360 driver from: | |
4547fa61 LB |
6 | * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il> |
7 | * Rabeeh Khoury <rabeeh@marvell.com> | |
1da177e4 LT |
8 | * |
9 | * Copyright (C) 2003 PMC-Sierra, Inc., | |
3bb8a18a | 10 | * written by Manish Lachwani |
1da177e4 LT |
11 | * |
12 | * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> | |
13 | * | |
c8aaea25 | 14 | * Copyright (C) 2004-2006 MontaVista Software, Inc. |
1da177e4 LT |
15 | * Dale Farnsworth <dale@farnsworth.org> |
16 | * | |
17 | * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com> | |
18 | * <sjhill@realitydiluted.com> | |
19 | * | |
4547fa61 LB |
20 | * Copyright (C) 2007-2008 Marvell Semiconductor |
21 | * Lennert Buytenhek <buytenh@marvell.com> | |
22 | * | |
1da177e4 LT |
23 | * This program is free software; you can redistribute it and/or |
24 | * modify it under the terms of the GNU General Public License | |
25 | * as published by the Free Software Foundation; either version 2 | |
26 | * of the License, or (at your option) any later version. | |
27 | * | |
28 | * This program is distributed in the hope that it will be useful, | |
29 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
30 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
31 | * GNU General Public License for more details. | |
32 | * | |
33 | * You should have received a copy of the GNU General Public License | |
34 | * along with this program; if not, write to the Free Software | |
35 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
36 | */ | |
37 | #include <linux/init.h> | |
38 | #include <linux/dma-mapping.h> | |
b6298c22 AV |
39 | #include <linux/in.h> |
40 | #include <linux/ip.h> | |
1da177e4 LT |
41 | #include <linux/tcp.h> |
42 | #include <linux/udp.h> | |
43 | #include <linux/etherdevice.h> | |
44 | ||
45 | #include <linux/bitops.h> | |
46 | #include <linux/delay.h> | |
47 | #include <linux/ethtool.h> | |
d052d1be RK |
48 | #include <linux/platform_device.h> |
49 | ||
fbd6a754 LB |
50 | #include <linux/module.h> |
51 | #include <linux/kernel.h> | |
52 | #include <linux/spinlock.h> | |
53 | #include <linux/workqueue.h> | |
54 | #include <linux/mii.h> | |
55 | ||
56 | #include <linux/mv643xx_eth.h> | |
57 | ||
1da177e4 LT |
58 | #include <asm/io.h> |
59 | #include <asm/types.h> | |
60 | #include <asm/pgtable.h> | |
61 | #include <asm/system.h> | |
62 | #include <asm/delay.h> | |
fbd6a754 LB |
63 | #include <asm/dma-mapping.h> |
64 | ||
fbd6a754 LB |
65 | #define MV643XX_CHECKSUM_OFFLOAD_TX |
66 | #define MV643XX_NAPI | |
67 | #define MV643XX_TX_FAST_REFILL | |
68 | #undef MV643XX_COAL | |
69 | ||
fbd6a754 LB |
70 | #define MV643XX_TX_COAL 100 |
71 | #ifdef MV643XX_COAL | |
72 | #define MV643XX_RX_COAL 100 | |
73 | #endif | |
74 | ||
75 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX | |
76 | #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1) | |
77 | #else | |
78 | #define MAX_DESCS_PER_SKB 1 | |
79 | #endif | |
80 | ||
81 | #define ETH_VLAN_HLEN 4 | |
82 | #define ETH_FCS_LEN 4 | |
83 | #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */ | |
84 | #define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \ | |
85 | ETH_VLAN_HLEN + ETH_FCS_LEN) | |
86 | #define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + \ | |
87 | dma_get_cache_alignment()) | |
88 | ||
89 | /* | |
90 | * Registers shared between all ports. | |
91 | */ | |
92 | #define PHY_ADDR_REG 0x0000 | |
93 | #define SMI_REG 0x0004 | |
f2ce825d LB |
94 | #define WINDOW_BASE(i) (0x0200 + ((i) << 3)) |
95 | #define WINDOW_SIZE(i) (0x0204 + ((i) << 3)) | |
96 | #define WINDOW_REMAP_HIGH(i) (0x0280 + ((i) << 2)) | |
97 | #define WINDOW_BAR_ENABLE 0x0290 | |
98 | #define WINDOW_PROTECT(i) (0x0294 + ((i) << 4)) | |
fbd6a754 LB |
99 | |
100 | /* | |
101 | * Per-port registers. | |
102 | */ | |
103 | #define PORT_CONFIG_REG(p) (0x0400 + ((p) << 10)) | |
104 | #define PORT_CONFIG_EXTEND_REG(p) (0x0404 + ((p) << 10)) | |
105 | #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10)) | |
106 | #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10)) | |
107 | #define SDMA_CONFIG_REG(p) (0x041c + ((p) << 10)) | |
108 | #define PORT_SERIAL_CONTROL_REG(p) (0x043c + ((p) << 10)) | |
109 | #define PORT_STATUS_REG(p) (0x0444 + ((p) << 10)) | |
110 | #define TRANSMIT_QUEUE_COMMAND_REG(p) (0x0448 + ((p) << 10)) | |
111 | #define MAXIMUM_TRANSMIT_UNIT(p) (0x0458 + ((p) << 10)) | |
112 | #define INTERRUPT_CAUSE_REG(p) (0x0460 + ((p) << 10)) | |
113 | #define INTERRUPT_CAUSE_EXTEND_REG(p) (0x0464 + ((p) << 10)) | |
114 | #define INTERRUPT_MASK_REG(p) (0x0468 + ((p) << 10)) | |
115 | #define INTERRUPT_EXTEND_MASK_REG(p) (0x046c + ((p) << 10)) | |
116 | #define TX_FIFO_URGENT_THRESHOLD_REG(p) (0x0474 + ((p) << 10)) | |
117 | #define RX_CURRENT_QUEUE_DESC_PTR_0(p) (0x060c + ((p) << 10)) | |
118 | #define RECEIVE_QUEUE_COMMAND_REG(p) (0x0680 + ((p) << 10)) | |
119 | #define TX_CURRENT_QUEUE_DESC_PTR_0(p) (0x06c0 + ((p) << 10)) | |
120 | #define MIB_COUNTERS_BASE(p) (0x1000 + ((p) << 7)) | |
121 | #define DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(p) (0x1400 + ((p) << 10)) | |
122 | #define DA_FILTER_OTHER_MULTICAST_TABLE_BASE(p) (0x1500 + ((p) << 10)) | |
123 | #define DA_FILTER_UNICAST_TABLE_BASE(p) (0x1600 + ((p) << 10)) | |
124 | ||
125 | /* These macros describe Ethernet Port configuration reg (Px_cR) bits */ | |
126 | #define UNICAST_NORMAL_MODE (0 << 0) | |
127 | #define UNICAST_PROMISCUOUS_MODE (1 << 0) | |
128 | #define DEFAULT_RX_QUEUE(queue) ((queue) << 1) | |
129 | #define DEFAULT_RX_ARP_QUEUE(queue) ((queue) << 4) | |
130 | #define RECEIVE_BC_IF_NOT_IP_OR_ARP (0 << 7) | |
131 | #define REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7) | |
132 | #define RECEIVE_BC_IF_IP (0 << 8) | |
133 | #define REJECT_BC_IF_IP (1 << 8) | |
134 | #define RECEIVE_BC_IF_ARP (0 << 9) | |
135 | #define REJECT_BC_IF_ARP (1 << 9) | |
136 | #define TX_AM_NO_UPDATE_ERROR_SUMMARY (1 << 12) | |
137 | #define CAPTURE_TCP_FRAMES_DIS (0 << 14) | |
138 | #define CAPTURE_TCP_FRAMES_EN (1 << 14) | |
139 | #define CAPTURE_UDP_FRAMES_DIS (0 << 15) | |
140 | #define CAPTURE_UDP_FRAMES_EN (1 << 15) | |
141 | #define DEFAULT_RX_TCP_QUEUE(queue) ((queue) << 16) | |
142 | #define DEFAULT_RX_UDP_QUEUE(queue) ((queue) << 19) | |
143 | #define DEFAULT_RX_BPDU_QUEUE(queue) ((queue) << 22) | |
144 | ||
145 | #define PORT_CONFIG_DEFAULT_VALUE \ | |
146 | UNICAST_NORMAL_MODE | \ | |
147 | DEFAULT_RX_QUEUE(0) | \ | |
148 | DEFAULT_RX_ARP_QUEUE(0) | \ | |
149 | RECEIVE_BC_IF_NOT_IP_OR_ARP | \ | |
150 | RECEIVE_BC_IF_IP | \ | |
151 | RECEIVE_BC_IF_ARP | \ | |
152 | CAPTURE_TCP_FRAMES_DIS | \ | |
153 | CAPTURE_UDP_FRAMES_DIS | \ | |
154 | DEFAULT_RX_TCP_QUEUE(0) | \ | |
155 | DEFAULT_RX_UDP_QUEUE(0) | \ | |
156 | DEFAULT_RX_BPDU_QUEUE(0) | |
157 | ||
158 | /* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/ | |
159 | #define CLASSIFY_EN (1 << 0) | |
160 | #define SPAN_BPDU_PACKETS_AS_NORMAL (0 << 1) | |
161 | #define SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1 << 1) | |
162 | #define PARTITION_DISABLE (0 << 2) | |
163 | #define PARTITION_ENABLE (1 << 2) | |
164 | ||
165 | #define PORT_CONFIG_EXTEND_DEFAULT_VALUE \ | |
166 | SPAN_BPDU_PACKETS_AS_NORMAL | \ | |
167 | PARTITION_DISABLE | |
168 | ||
169 | /* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */ | |
170 | #define RIFB (1 << 0) | |
171 | #define RX_BURST_SIZE_1_64BIT (0 << 1) | |
172 | #define RX_BURST_SIZE_2_64BIT (1 << 1) | |
173 | #define RX_BURST_SIZE_4_64BIT (2 << 1) | |
174 | #define RX_BURST_SIZE_8_64BIT (3 << 1) | |
175 | #define RX_BURST_SIZE_16_64BIT (4 << 1) | |
176 | #define BLM_RX_NO_SWAP (1 << 4) | |
177 | #define BLM_RX_BYTE_SWAP (0 << 4) | |
178 | #define BLM_TX_NO_SWAP (1 << 5) | |
179 | #define BLM_TX_BYTE_SWAP (0 << 5) | |
180 | #define DESCRIPTORS_BYTE_SWAP (1 << 6) | |
181 | #define DESCRIPTORS_NO_SWAP (0 << 6) | |
182 | #define IPG_INT_RX(value) (((value) & 0x3fff) << 8) | |
183 | #define TX_BURST_SIZE_1_64BIT (0 << 22) | |
184 | #define TX_BURST_SIZE_2_64BIT (1 << 22) | |
185 | #define TX_BURST_SIZE_4_64BIT (2 << 22) | |
186 | #define TX_BURST_SIZE_8_64BIT (3 << 22) | |
187 | #define TX_BURST_SIZE_16_64BIT (4 << 22) | |
188 | ||
189 | #if defined(__BIG_ENDIAN) | |
190 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | |
191 | RX_BURST_SIZE_4_64BIT | \ | |
192 | IPG_INT_RX(0) | \ | |
193 | TX_BURST_SIZE_4_64BIT | |
194 | #elif defined(__LITTLE_ENDIAN) | |
195 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | |
196 | RX_BURST_SIZE_4_64BIT | \ | |
197 | BLM_RX_NO_SWAP | \ | |
198 | BLM_TX_NO_SWAP | \ | |
199 | IPG_INT_RX(0) | \ | |
200 | TX_BURST_SIZE_4_64BIT | |
201 | #else | |
202 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | |
203 | #endif | |
204 | ||
205 | /* These macros describe Ethernet Port serial control reg (PSCR) bits */ | |
206 | #define SERIAL_PORT_DISABLE (0 << 0) | |
207 | #define SERIAL_PORT_ENABLE (1 << 0) | |
208 | #define DO_NOT_FORCE_LINK_PASS (0 << 1) | |
209 | #define FORCE_LINK_PASS (1 << 1) | |
210 | #define ENABLE_AUTO_NEG_FOR_DUPLX (0 << 2) | |
211 | #define DISABLE_AUTO_NEG_FOR_DUPLX (1 << 2) | |
212 | #define ENABLE_AUTO_NEG_FOR_FLOW_CTRL (0 << 3) | |
213 | #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3) | |
214 | #define ADV_NO_FLOW_CTRL (0 << 4) | |
215 | #define ADV_SYMMETRIC_FLOW_CTRL (1 << 4) | |
216 | #define FORCE_FC_MODE_NO_PAUSE_DIS_TX (0 << 5) | |
217 | #define FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5) | |
218 | #define FORCE_BP_MODE_NO_JAM (0 << 7) | |
219 | #define FORCE_BP_MODE_JAM_TX (1 << 7) | |
220 | #define FORCE_BP_MODE_JAM_TX_ON_RX_ERR (2 << 7) | |
221 | #define SERIAL_PORT_CONTROL_RESERVED (1 << 9) | |
222 | #define FORCE_LINK_FAIL (0 << 10) | |
223 | #define DO_NOT_FORCE_LINK_FAIL (1 << 10) | |
224 | #define RETRANSMIT_16_ATTEMPTS (0 << 11) | |
225 | #define RETRANSMIT_FOREVER (1 << 11) | |
226 | #define ENABLE_AUTO_NEG_SPEED_GMII (0 << 13) | |
227 | #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13) | |
228 | #define DTE_ADV_0 (0 << 14) | |
229 | #define DTE_ADV_1 (1 << 14) | |
230 | #define DISABLE_AUTO_NEG_BYPASS (0 << 15) | |
231 | #define ENABLE_AUTO_NEG_BYPASS (1 << 15) | |
232 | #define AUTO_NEG_NO_CHANGE (0 << 16) | |
233 | #define RESTART_AUTO_NEG (1 << 16) | |
234 | #define MAX_RX_PACKET_1518BYTE (0 << 17) | |
235 | #define MAX_RX_PACKET_1522BYTE (1 << 17) | |
236 | #define MAX_RX_PACKET_1552BYTE (2 << 17) | |
237 | #define MAX_RX_PACKET_9022BYTE (3 << 17) | |
238 | #define MAX_RX_PACKET_9192BYTE (4 << 17) | |
239 | #define MAX_RX_PACKET_9700BYTE (5 << 17) | |
240 | #define MAX_RX_PACKET_MASK (7 << 17) | |
241 | #define CLR_EXT_LOOPBACK (0 << 20) | |
242 | #define SET_EXT_LOOPBACK (1 << 20) | |
243 | #define SET_HALF_DUPLEX_MODE (0 << 21) | |
244 | #define SET_FULL_DUPLEX_MODE (1 << 21) | |
245 | #define DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (0 << 22) | |
246 | #define ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22) | |
247 | #define SET_GMII_SPEED_TO_10_100 (0 << 23) | |
248 | #define SET_GMII_SPEED_TO_1000 (1 << 23) | |
249 | #define SET_MII_SPEED_TO_10 (0 << 24) | |
250 | #define SET_MII_SPEED_TO_100 (1 << 24) | |
251 | ||
252 | #define PORT_SERIAL_CONTROL_DEFAULT_VALUE \ | |
253 | DO_NOT_FORCE_LINK_PASS | \ | |
254 | ENABLE_AUTO_NEG_FOR_DUPLX | \ | |
255 | DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ | |
256 | ADV_SYMMETRIC_FLOW_CTRL | \ | |
257 | FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ | |
258 | FORCE_BP_MODE_NO_JAM | \ | |
259 | (1 << 9) /* reserved */ | \ | |
260 | DO_NOT_FORCE_LINK_FAIL | \ | |
261 | RETRANSMIT_16_ATTEMPTS | \ | |
262 | ENABLE_AUTO_NEG_SPEED_GMII | \ | |
263 | DTE_ADV_0 | \ | |
264 | DISABLE_AUTO_NEG_BYPASS | \ | |
265 | AUTO_NEG_NO_CHANGE | \ | |
266 | MAX_RX_PACKET_9700BYTE | \ | |
267 | CLR_EXT_LOOPBACK | \ | |
268 | SET_FULL_DUPLEX_MODE | \ | |
269 | ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX | |
270 | ||
271 | /* These macros describe Ethernet Serial Status reg (PSR) bits */ | |
272 | #define PORT_STATUS_MODE_10_BIT (1 << 0) | |
273 | #define PORT_STATUS_LINK_UP (1 << 1) | |
274 | #define PORT_STATUS_FULL_DUPLEX (1 << 2) | |
275 | #define PORT_STATUS_FLOW_CONTROL (1 << 3) | |
276 | #define PORT_STATUS_GMII_1000 (1 << 4) | |
277 | #define PORT_STATUS_MII_100 (1 << 5) | |
278 | /* PSR bit 6 is undocumented */ | |
279 | #define PORT_STATUS_TX_IN_PROGRESS (1 << 7) | |
280 | #define PORT_STATUS_AUTONEG_BYPASSED (1 << 8) | |
281 | #define PORT_STATUS_PARTITION (1 << 9) | |
282 | #define PORT_STATUS_TX_FIFO_EMPTY (1 << 10) | |
283 | /* PSR bits 11-31 are reserved */ | |
284 | ||
285 | #define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800 | |
286 | #define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400 | |
287 | ||
288 | #define DESC_SIZE 64 | |
289 | ||
290 | #define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */ | |
291 | #define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */ | |
292 | ||
293 | #define ETH_INT_CAUSE_RX_DONE (ETH_RX_QUEUES_ENABLED << 2) | |
294 | #define ETH_INT_CAUSE_RX_ERROR (ETH_RX_QUEUES_ENABLED << 9) | |
295 | #define ETH_INT_CAUSE_RX (ETH_INT_CAUSE_RX_DONE | ETH_INT_CAUSE_RX_ERROR) | |
296 | #define ETH_INT_CAUSE_EXT 0x00000002 | |
297 | #define ETH_INT_UNMASK_ALL (ETH_INT_CAUSE_RX | ETH_INT_CAUSE_EXT) | |
298 | ||
299 | #define ETH_INT_CAUSE_TX_DONE (ETH_TX_QUEUES_ENABLED << 0) | |
300 | #define ETH_INT_CAUSE_TX_ERROR (ETH_TX_QUEUES_ENABLED << 8) | |
301 | #define ETH_INT_CAUSE_TX (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR) | |
302 | #define ETH_INT_CAUSE_PHY 0x00010000 | |
303 | #define ETH_INT_CAUSE_STATE 0x00100000 | |
304 | #define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY | \ | |
305 | ETH_INT_CAUSE_STATE) | |
306 | ||
307 | #define ETH_INT_MASK_ALL 0x00000000 | |
308 | #define ETH_INT_MASK_ALL_EXT 0x00000000 | |
309 | ||
310 | #define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */ | |
311 | #define PHY_WAIT_MICRO_SECONDS 10 | |
312 | ||
313 | /* Buffer offset from buffer pointer */ | |
314 | #define RX_BUF_OFFSET 0x2 | |
315 | ||
316 | /* Gigabit Ethernet Unit Global Registers */ | |
317 | ||
318 | /* MIB Counters register definitions */ | |
319 | #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0 | |
320 | #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4 | |
321 | #define ETH_MIB_BAD_OCTETS_RECEIVED 0x8 | |
322 | #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc | |
323 | #define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10 | |
324 | #define ETH_MIB_BAD_FRAMES_RECEIVED 0x14 | |
325 | #define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18 | |
326 | #define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c | |
327 | #define ETH_MIB_FRAMES_64_OCTETS 0x20 | |
328 | #define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24 | |
329 | #define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28 | |
330 | #define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c | |
331 | #define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30 | |
332 | #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 | |
333 | #define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38 | |
334 | #define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c | |
335 | #define ETH_MIB_GOOD_FRAMES_SENT 0x40 | |
336 | #define ETH_MIB_EXCESSIVE_COLLISION 0x44 | |
337 | #define ETH_MIB_MULTICAST_FRAMES_SENT 0x48 | |
338 | #define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c | |
339 | #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50 | |
340 | #define ETH_MIB_FC_SENT 0x54 | |
341 | #define ETH_MIB_GOOD_FC_RECEIVED 0x58 | |
342 | #define ETH_MIB_BAD_FC_RECEIVED 0x5c | |
343 | #define ETH_MIB_UNDERSIZE_RECEIVED 0x60 | |
344 | #define ETH_MIB_FRAGMENTS_RECEIVED 0x64 | |
345 | #define ETH_MIB_OVERSIZE_RECEIVED 0x68 | |
346 | #define ETH_MIB_JABBER_RECEIVED 0x6c | |
347 | #define ETH_MIB_MAC_RECEIVE_ERROR 0x70 | |
348 | #define ETH_MIB_BAD_CRC_EVENT 0x74 | |
349 | #define ETH_MIB_COLLISION 0x78 | |
350 | #define ETH_MIB_LATE_COLLISION 0x7c | |
351 | ||
352 | /* Port serial status reg (PSR) */ | |
353 | #define ETH_INTERFACE_PCM 0x00000001 | |
354 | #define ETH_LINK_IS_UP 0x00000002 | |
355 | #define ETH_PORT_AT_FULL_DUPLEX 0x00000004 | |
356 | #define ETH_RX_FLOW_CTRL_ENABLED 0x00000008 | |
357 | #define ETH_GMII_SPEED_1000 0x00000010 | |
358 | #define ETH_MII_SPEED_100 0x00000020 | |
359 | #define ETH_TX_IN_PROGRESS 0x00000080 | |
360 | #define ETH_BYPASS_ACTIVE 0x00000100 | |
361 | #define ETH_PORT_AT_PARTITION_STATE 0x00000200 | |
362 | #define ETH_PORT_TX_FIFO_EMPTY 0x00000400 | |
363 | ||
364 | /* SMI reg */ | |
365 | #define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */ | |
366 | #define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */ | |
367 | #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */ | |
368 | #define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */ | |
369 | ||
370 | /* Interrupt Cause Register Bit Definitions */ | |
371 | ||
372 | /* SDMA command status fields macros */ | |
373 | ||
374 | /* Tx & Rx descriptors status */ | |
375 | #define ETH_ERROR_SUMMARY 0x00000001 | |
376 | ||
377 | /* Tx & Rx descriptors command */ | |
378 | #define ETH_BUFFER_OWNED_BY_DMA 0x80000000 | |
379 | ||
380 | /* Tx descriptors status */ | |
381 | #define ETH_LC_ERROR 0 | |
382 | #define ETH_UR_ERROR 0x00000002 | |
383 | #define ETH_RL_ERROR 0x00000004 | |
384 | #define ETH_LLC_SNAP_FORMAT 0x00000200 | |
385 | ||
386 | /* Rx descriptors status */ | |
387 | #define ETH_OVERRUN_ERROR 0x00000002 | |
388 | #define ETH_MAX_FRAME_LENGTH_ERROR 0x00000004 | |
389 | #define ETH_RESOURCE_ERROR 0x00000006 | |
390 | #define ETH_VLAN_TAGGED 0x00080000 | |
391 | #define ETH_BPDU_FRAME 0x00100000 | |
392 | #define ETH_UDP_FRAME_OVER_IP_V_4 0x00200000 | |
393 | #define ETH_OTHER_FRAME_TYPE 0x00400000 | |
394 | #define ETH_LAYER_2_IS_ETH_V_2 0x00800000 | |
395 | #define ETH_FRAME_TYPE_IP_V_4 0x01000000 | |
396 | #define ETH_FRAME_HEADER_OK 0x02000000 | |
397 | #define ETH_RX_LAST_DESC 0x04000000 | |
398 | #define ETH_RX_FIRST_DESC 0x08000000 | |
399 | #define ETH_UNKNOWN_DESTINATION_ADDR 0x10000000 | |
400 | #define ETH_RX_ENABLE_INTERRUPT 0x20000000 | |
401 | #define ETH_LAYER_4_CHECKSUM_OK 0x40000000 | |
402 | ||
403 | /* Rx descriptors byte count */ | |
404 | #define ETH_FRAME_FRAGMENTED 0x00000004 | |
405 | ||
406 | /* Tx descriptors command */ | |
407 | #define ETH_LAYER_4_CHECKSUM_FIRST_DESC 0x00000400 | |
408 | #define ETH_FRAME_SET_TO_VLAN 0x00008000 | |
409 | #define ETH_UDP_FRAME 0x00010000 | |
410 | #define ETH_GEN_TCP_UDP_CHECKSUM 0x00020000 | |
411 | #define ETH_GEN_IP_V_4_CHECKSUM 0x00040000 | |
412 | #define ETH_ZERO_PADDING 0x00080000 | |
413 | #define ETH_TX_LAST_DESC 0x00100000 | |
414 | #define ETH_TX_FIRST_DESC 0x00200000 | |
415 | #define ETH_GEN_CRC 0x00400000 | |
416 | #define ETH_TX_ENABLE_INTERRUPT 0x00800000 | |
417 | #define ETH_AUTO_MODE 0x40000000 | |
418 | ||
419 | #define ETH_TX_IHL_SHIFT 11 | |
420 | ||
421 | /* typedefs */ | |
422 | ||
423 | typedef enum _eth_func_ret_status { | |
424 | ETH_OK, /* Returned as expected. */ | |
425 | ETH_ERROR, /* Fundamental error. */ | |
426 | ETH_RETRY, /* Could not process request. Try later.*/ | |
427 | ETH_END_OF_JOB, /* Ring has nothing to process. */ | |
428 | ETH_QUEUE_FULL, /* Ring resource error. */ | |
429 | ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */ | |
430 | } ETH_FUNC_RET_STATUS; | |
431 | ||
fbd6a754 LB |
432 | /* These are for big-endian machines. Little endian needs different |
433 | * definitions. | |
434 | */ | |
435 | #if defined(__BIG_ENDIAN) | |
436 | struct eth_rx_desc { | |
437 | u16 byte_cnt; /* Descriptor buffer byte count */ | |
438 | u16 buf_size; /* Buffer size */ | |
439 | u32 cmd_sts; /* Descriptor command status */ | |
440 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
441 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
442 | }; | |
443 | ||
444 | struct eth_tx_desc { | |
445 | u16 byte_cnt; /* buffer byte count */ | |
446 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
447 | u32 cmd_sts; /* Command/status field */ | |
448 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
449 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
450 | }; | |
451 | #elif defined(__LITTLE_ENDIAN) | |
452 | struct eth_rx_desc { | |
453 | u32 cmd_sts; /* Descriptor command status */ | |
454 | u16 buf_size; /* Buffer size */ | |
455 | u16 byte_cnt; /* Descriptor buffer byte count */ | |
456 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
457 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
458 | }; | |
459 | ||
460 | struct eth_tx_desc { | |
461 | u32 cmd_sts; /* Command/status field */ | |
462 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
463 | u16 byte_cnt; /* buffer byte count */ | |
464 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
465 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
466 | }; | |
467 | #else | |
468 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | |
469 | #endif | |
470 | ||
471 | /* Unified struct for Rx and Tx operations. The user is not required to */ | |
472 | /* be familier with neither Tx nor Rx descriptors. */ | |
473 | struct pkt_info { | |
474 | unsigned short byte_cnt; /* Descriptor buffer byte count */ | |
475 | unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */ | |
476 | unsigned int cmd_sts; /* Descriptor command status */ | |
477 | dma_addr_t buf_ptr; /* Descriptor buffer pointer */ | |
478 | struct sk_buff *return_info; /* User resource return information */ | |
479 | }; | |
480 | ||
481 | /* Ethernet port specific information */ | |
482 | struct mv643xx_mib_counters { | |
483 | u64 good_octets_received; | |
484 | u32 bad_octets_received; | |
485 | u32 internal_mac_transmit_err; | |
486 | u32 good_frames_received; | |
487 | u32 bad_frames_received; | |
488 | u32 broadcast_frames_received; | |
489 | u32 multicast_frames_received; | |
490 | u32 frames_64_octets; | |
491 | u32 frames_65_to_127_octets; | |
492 | u32 frames_128_to_255_octets; | |
493 | u32 frames_256_to_511_octets; | |
494 | u32 frames_512_to_1023_octets; | |
495 | u32 frames_1024_to_max_octets; | |
496 | u64 good_octets_sent; | |
497 | u32 good_frames_sent; | |
498 | u32 excessive_collision; | |
499 | u32 multicast_frames_sent; | |
500 | u32 broadcast_frames_sent; | |
501 | u32 unrec_mac_control_received; | |
502 | u32 fc_sent; | |
503 | u32 good_fc_received; | |
504 | u32 bad_fc_received; | |
505 | u32 undersize_received; | |
506 | u32 fragments_received; | |
507 | u32 oversize_received; | |
508 | u32 jabber_received; | |
509 | u32 mac_receive_error; | |
510 | u32 bad_crc_event; | |
511 | u32 collision; | |
512 | u32 late_collision; | |
513 | }; | |
514 | ||
fa3959f4 LB |
515 | struct mv643xx_shared_private { |
516 | void __iomem *eth_base; | |
517 | ||
518 | /* used to protect SMI_REG, which is shared across ports */ | |
519 | spinlock_t phy_lock; | |
f2ce825d LB |
520 | |
521 | u32 win_protect; | |
c416a41f LB |
522 | |
523 | unsigned int t_clk; | |
fa3959f4 LB |
524 | }; |
525 | ||
fbd6a754 | 526 | struct mv643xx_private { |
fa3959f4 | 527 | struct mv643xx_shared_private *shared; |
fbd6a754 LB |
528 | int port_num; /* User Ethernet port number */ |
529 | ||
ce4e2e45 LB |
530 | struct mv643xx_shared_private *shared_smi; |
531 | ||
fbd6a754 LB |
532 | u32 rx_sram_addr; /* Base address of rx sram area */ |
533 | u32 rx_sram_size; /* Size of rx sram area */ | |
534 | u32 tx_sram_addr; /* Base address of tx sram area */ | |
535 | u32 tx_sram_size; /* Size of tx sram area */ | |
536 | ||
537 | int rx_resource_err; /* Rx ring resource error flag */ | |
538 | ||
539 | /* Tx/Rx rings managment indexes fields. For driver use */ | |
540 | ||
541 | /* Next available and first returning Rx resource */ | |
542 | int rx_curr_desc_q, rx_used_desc_q; | |
543 | ||
544 | /* Next available and first returning Tx resource */ | |
545 | int tx_curr_desc_q, tx_used_desc_q; | |
546 | ||
547 | #ifdef MV643XX_TX_FAST_REFILL | |
548 | u32 tx_clean_threshold; | |
549 | #endif | |
550 | ||
551 | struct eth_rx_desc *p_rx_desc_area; | |
552 | dma_addr_t rx_desc_dma; | |
553 | int rx_desc_area_size; | |
554 | struct sk_buff **rx_skb; | |
555 | ||
556 | struct eth_tx_desc *p_tx_desc_area; | |
557 | dma_addr_t tx_desc_dma; | |
558 | int tx_desc_area_size; | |
559 | struct sk_buff **tx_skb; | |
560 | ||
561 | struct work_struct tx_timeout_task; | |
562 | ||
563 | struct net_device *dev; | |
564 | struct napi_struct napi; | |
565 | struct net_device_stats stats; | |
566 | struct mv643xx_mib_counters mib_counters; | |
567 | spinlock_t lock; | |
568 | /* Size of Tx Ring per queue */ | |
569 | int tx_ring_size; | |
570 | /* Number of tx descriptors in use */ | |
571 | int tx_desc_count; | |
572 | /* Size of Rx Ring per queue */ | |
573 | int rx_ring_size; | |
574 | /* Number of rx descriptors in use */ | |
575 | int rx_desc_count; | |
576 | ||
577 | /* | |
578 | * Used in case RX Ring is empty, which can be caused when | |
579 | * system does not have resources (skb's) | |
580 | */ | |
581 | struct timer_list timeout; | |
582 | ||
583 | u32 rx_int_coal; | |
584 | u32 tx_int_coal; | |
585 | struct mii_if_info mii; | |
586 | }; | |
1da177e4 | 587 | |
1da177e4 | 588 | /* Static function declarations */ |
fbd6a754 | 589 | static void eth_port_init(struct mv643xx_private *mp); |
afdb57a2 | 590 | static void eth_port_reset(struct mv643xx_private *mp); |
fbd6a754 LB |
591 | static void eth_port_start(struct net_device *dev); |
592 | ||
afdb57a2 | 593 | static void ethernet_phy_reset(struct mv643xx_private *mp); |
fbd6a754 | 594 | |
afdb57a2 | 595 | static void eth_port_write_smi_reg(struct mv643xx_private *mp, |
fbd6a754 LB |
596 | unsigned int phy_reg, unsigned int value); |
597 | ||
afdb57a2 | 598 | static void eth_port_read_smi_reg(struct mv643xx_private *mp, |
fbd6a754 LB |
599 | unsigned int phy_reg, unsigned int *value); |
600 | ||
afdb57a2 | 601 | static void eth_clear_mib_counters(struct mv643xx_private *mp); |
fbd6a754 LB |
602 | |
603 | static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp, | |
604 | struct pkt_info *p_pkt_info); | |
605 | static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp, | |
606 | struct pkt_info *p_pkt_info); | |
607 | ||
afdb57a2 LB |
608 | static void eth_port_uc_addr_get(struct mv643xx_private *mp, |
609 | unsigned char *p_addr); | |
610 | static void eth_port_uc_addr_set(struct mv643xx_private *mp, | |
611 | unsigned char *p_addr); | |
16e03018 | 612 | static void eth_port_set_multicast_list(struct net_device *); |
afdb57a2 | 613 | static void mv643xx_eth_port_enable_tx(struct mv643xx_private *mp, |
12a87c64 | 614 | unsigned int queues); |
afdb57a2 | 615 | static void mv643xx_eth_port_enable_rx(struct mv643xx_private *mp, |
12a87c64 | 616 | unsigned int queues); |
afdb57a2 LB |
617 | static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_private *mp); |
618 | static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_private *mp); | |
ab4384a6 DF |
619 | static int mv643xx_eth_open(struct net_device *); |
620 | static int mv643xx_eth_stop(struct net_device *); | |
afdb57a2 | 621 | static void eth_port_init_mac_tables(struct mv643xx_private *mp); |
1da177e4 | 622 | #ifdef MV643XX_NAPI |
bea3348e | 623 | static int mv643xx_poll(struct napi_struct *napi, int budget); |
1da177e4 | 624 | #endif |
afdb57a2 LB |
625 | static int ethernet_phy_get(struct mv643xx_private *mp); |
626 | static void ethernet_phy_set(struct mv643xx_private *mp, int phy_addr); | |
627 | static int ethernet_phy_detect(struct mv643xx_private *mp); | |
c28a4f89 JC |
628 | static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location); |
629 | static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val); | |
d0412d96 | 630 | static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); |
7282d491 | 631 | static const struct ethtool_ops mv643xx_ethtool_ops; |
1da177e4 LT |
632 | |
633 | static char mv643xx_driver_name[] = "mv643xx_eth"; | |
634 | static char mv643xx_driver_version[] = "1.0"; | |
635 | ||
ec69d651 | 636 | static inline u32 rdl(struct mv643xx_private *mp, int offset) |
1da177e4 | 637 | { |
fa3959f4 | 638 | return readl(mp->shared->eth_base + offset); |
1da177e4 LT |
639 | } |
640 | ||
ec69d651 | 641 | static inline void wrl(struct mv643xx_private *mp, int offset, u32 data) |
1da177e4 | 642 | { |
fa3959f4 | 643 | writel(data, mp->shared->eth_base + offset); |
1da177e4 LT |
644 | } |
645 | ||
646 | /* | |
647 | * Changes MTU (maximum transfer unit) of the gigabit ethenret port | |
648 | * | |
649 | * Input : pointer to ethernet interface network device structure | |
650 | * new mtu size | |
651 | * Output : 0 upon success, -EINVAL upon failure | |
652 | */ | |
653 | static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu) | |
654 | { | |
8f518703 | 655 | if ((new_mtu > 9500) || (new_mtu < 64)) |
1da177e4 | 656 | return -EINVAL; |
1da177e4 LT |
657 | |
658 | dev->mtu = new_mtu; | |
c0d0f2ca LB |
659 | if (!netif_running(dev)) |
660 | return 0; | |
661 | ||
1da177e4 | 662 | /* |
c0d0f2ca LB |
663 | * Stop and then re-open the interface. This will allocate RX |
664 | * skbs of the new MTU. | |
665 | * There is a possible danger that the open will not succeed, | |
666 | * due to memory being full, which might fail the open function. | |
1da177e4 | 667 | */ |
c0d0f2ca LB |
668 | mv643xx_eth_stop(dev); |
669 | if (mv643xx_eth_open(dev)) { | |
670 | printk(KERN_ERR "%s: Fatal error on opening device\n", | |
671 | dev->name); | |
1da177e4 LT |
672 | } |
673 | ||
1da177e4 LT |
674 | return 0; |
675 | } | |
676 | ||
677 | /* | |
f78fb474 | 678 | * mv643xx_eth_rx_refill_descs |
1da177e4 LT |
679 | * |
680 | * Fills / refills RX queue on a certain gigabit ethernet port | |
681 | * | |
682 | * Input : pointer to ethernet interface network device structure | |
683 | * Output : N/A | |
684 | */ | |
f78fb474 | 685 | static void mv643xx_eth_rx_refill_descs(struct net_device *dev) |
1da177e4 | 686 | { |
1da177e4 LT |
687 | struct mv643xx_private *mp = netdev_priv(dev); |
688 | struct pkt_info pkt_info; | |
689 | struct sk_buff *skb; | |
b44cd572 | 690 | int unaligned; |
1da177e4 | 691 | |
f78fb474 | 692 | while (mp->rx_desc_count < mp->rx_ring_size) { |
908b637f | 693 | skb = dev_alloc_skb(ETH_RX_SKB_SIZE + dma_get_cache_alignment()); |
1da177e4 LT |
694 | if (!skb) |
695 | break; | |
f98e36f1 | 696 | mp->rx_desc_count++; |
908b637f | 697 | unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1); |
b44cd572 | 698 | if (unaligned) |
908b637f | 699 | skb_reserve(skb, dma_get_cache_alignment() - unaligned); |
1da177e4 | 700 | pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT; |
7303fde8 DF |
701 | pkt_info.byte_cnt = ETH_RX_SKB_SIZE; |
702 | pkt_info.buf_ptr = dma_map_single(NULL, skb->data, | |
703 | ETH_RX_SKB_SIZE, DMA_FROM_DEVICE); | |
1da177e4 LT |
704 | pkt_info.return_info = skb; |
705 | if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) { | |
706 | printk(KERN_ERR | |
707 | "%s: Error allocating RX Ring\n", dev->name); | |
708 | break; | |
709 | } | |
7303fde8 | 710 | skb_reserve(skb, ETH_HW_IP_ALIGN); |
1da177e4 | 711 | } |
1da177e4 LT |
712 | /* |
713 | * If RX ring is empty of SKB, set a timer to try allocating | |
f78fb474 | 714 | * again at a later time. |
1da177e4 | 715 | */ |
f78fb474 | 716 | if (mp->rx_desc_count == 0) { |
1da177e4 | 717 | printk(KERN_INFO "%s: Rx ring is empty\n", dev->name); |
f78fb474 | 718 | mp->timeout.expires = jiffies + (HZ / 10); /* 100 mSec */ |
1da177e4 | 719 | add_timer(&mp->timeout); |
1da177e4 | 720 | } |
1da177e4 LT |
721 | } |
722 | ||
723 | /* | |
f78fb474 | 724 | * mv643xx_eth_rx_refill_descs_timer_wrapper |
1da177e4 LT |
725 | * |
726 | * Timer routine to wake up RX queue filling task. This function is | |
727 | * used only in case the RX queue is empty, and all alloc_skb has | |
728 | * failed (due to out of memory event). | |
729 | * | |
730 | * Input : pointer to ethernet interface network device structure | |
731 | * Output : N/A | |
732 | */ | |
f78fb474 | 733 | static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data) |
1da177e4 | 734 | { |
f78fb474 | 735 | mv643xx_eth_rx_refill_descs((struct net_device *)data); |
1da177e4 LT |
736 | } |
737 | ||
738 | /* | |
739 | * mv643xx_eth_update_mac_address | |
740 | * | |
741 | * Update the MAC address of the port in the address table | |
742 | * | |
743 | * Input : pointer to ethernet interface network device structure | |
744 | * Output : N/A | |
745 | */ | |
746 | static void mv643xx_eth_update_mac_address(struct net_device *dev) | |
747 | { | |
748 | struct mv643xx_private *mp = netdev_priv(dev); | |
1da177e4 | 749 | |
afdb57a2 LB |
750 | eth_port_init_mac_tables(mp); |
751 | eth_port_uc_addr_set(mp, dev->dev_addr); | |
1da177e4 LT |
752 | } |
753 | ||
754 | /* | |
755 | * mv643xx_eth_set_rx_mode | |
756 | * | |
757 | * Change from promiscuos to regular rx mode | |
758 | * | |
759 | * Input : pointer to ethernet interface network device structure | |
760 | * Output : N/A | |
761 | */ | |
762 | static void mv643xx_eth_set_rx_mode(struct net_device *dev) | |
763 | { | |
764 | struct mv643xx_private *mp = netdev_priv(dev); | |
01999873 | 765 | u32 config_reg; |
1da177e4 | 766 | |
ec69d651 | 767 | config_reg = rdl(mp, PORT_CONFIG_REG(mp->port_num)); |
1da177e4 | 768 | if (dev->flags & IFF_PROMISC) |
e4d00fa9 | 769 | config_reg |= (u32) UNICAST_PROMISCUOUS_MODE; |
1da177e4 | 770 | else |
e4d00fa9 | 771 | config_reg &= ~(u32) UNICAST_PROMISCUOUS_MODE; |
ec69d651 | 772 | wrl(mp, PORT_CONFIG_REG(mp->port_num), config_reg); |
16e03018 DF |
773 | |
774 | eth_port_set_multicast_list(dev); | |
1da177e4 LT |
775 | } |
776 | ||
777 | /* | |
778 | * mv643xx_eth_set_mac_address | |
779 | * | |
780 | * Change the interface's mac address. | |
781 | * No special hardware thing should be done because interface is always | |
782 | * put in promiscuous mode. | |
783 | * | |
784 | * Input : pointer to ethernet interface network device structure and | |
785 | * a pointer to the designated entry to be added to the cache. | |
786 | * Output : zero upon success, negative upon failure | |
787 | */ | |
788 | static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr) | |
789 | { | |
790 | int i; | |
791 | ||
792 | for (i = 0; i < 6; i++) | |
793 | /* +2 is for the offset of the HW addr type */ | |
794 | dev->dev_addr[i] = ((unsigned char *)addr)[i + 2]; | |
795 | mv643xx_eth_update_mac_address(dev); | |
796 | return 0; | |
797 | } | |
798 | ||
799 | /* | |
800 | * mv643xx_eth_tx_timeout | |
801 | * | |
802 | * Called upon a timeout on transmitting a packet | |
803 | * | |
804 | * Input : pointer to ethernet interface network device structure. | |
805 | * Output : N/A | |
806 | */ | |
807 | static void mv643xx_eth_tx_timeout(struct net_device *dev) | |
808 | { | |
809 | struct mv643xx_private *mp = netdev_priv(dev); | |
810 | ||
811 | printk(KERN_INFO "%s: TX timeout ", dev->name); | |
812 | ||
813 | /* Do the reset outside of interrupt context */ | |
814 | schedule_work(&mp->tx_timeout_task); | |
815 | } | |
816 | ||
817 | /* | |
818 | * mv643xx_eth_tx_timeout_task | |
819 | * | |
820 | * Actual routine to reset the adapter when a timeout on Tx has occurred | |
821 | */ | |
91c7c568 | 822 | static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly) |
1da177e4 | 823 | { |
91c7c568 AV |
824 | struct mv643xx_private *mp = container_of(ugly, struct mv643xx_private, |
825 | tx_timeout_task); | |
c0d0f2ca | 826 | struct net_device *dev = mp->dev; |
1da177e4 | 827 | |
94843566 DF |
828 | if (!netif_running(dev)) |
829 | return; | |
830 | ||
831 | netif_stop_queue(dev); | |
832 | ||
afdb57a2 | 833 | eth_port_reset(mp); |
ed9b5d45 | 834 | eth_port_start(dev); |
94843566 DF |
835 | |
836 | if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB) | |
837 | netif_wake_queue(dev); | |
1da177e4 LT |
838 | } |
839 | ||
ff561eef DF |
840 | /** |
841 | * mv643xx_eth_free_tx_descs - Free the tx desc data for completed descriptors | |
1da177e4 | 842 | * |
ff561eef | 843 | * If force is non-zero, frees uncompleted descriptors as well |
1da177e4 | 844 | */ |
c0d0f2ca | 845 | static int mv643xx_eth_free_tx_descs(struct net_device *dev, int force) |
1da177e4 LT |
846 | { |
847 | struct mv643xx_private *mp = netdev_priv(dev); | |
ff561eef DF |
848 | struct eth_tx_desc *desc; |
849 | u32 cmd_sts; | |
850 | struct sk_buff *skb; | |
851 | unsigned long flags; | |
852 | int tx_index; | |
853 | dma_addr_t addr; | |
854 | int count; | |
855 | int released = 0; | |
1da177e4 | 856 | |
ff561eef DF |
857 | while (mp->tx_desc_count > 0) { |
858 | spin_lock_irqsave(&mp->lock, flags); | |
d344bff9 DF |
859 | |
860 | /* tx_desc_count might have changed before acquiring the lock */ | |
861 | if (mp->tx_desc_count <= 0) { | |
862 | spin_unlock_irqrestore(&mp->lock, flags); | |
863 | return released; | |
864 | } | |
865 | ||
ff561eef DF |
866 | tx_index = mp->tx_used_desc_q; |
867 | desc = &mp->p_tx_desc_area[tx_index]; | |
868 | cmd_sts = desc->cmd_sts; | |
869 | ||
870 | if (!force && (cmd_sts & ETH_BUFFER_OWNED_BY_DMA)) { | |
871 | spin_unlock_irqrestore(&mp->lock, flags); | |
872 | return released; | |
873 | } | |
874 | ||
875 | mp->tx_used_desc_q = (tx_index + 1) % mp->tx_ring_size; | |
876 | mp->tx_desc_count--; | |
877 | ||
878 | addr = desc->buf_ptr; | |
879 | count = desc->byte_cnt; | |
880 | skb = mp->tx_skb[tx_index]; | |
881 | if (skb) | |
882 | mp->tx_skb[tx_index] = NULL; | |
883 | ||
7303fde8 | 884 | if (cmd_sts & ETH_ERROR_SUMMARY) { |
1da177e4 | 885 | printk("%s: Error in TX\n", dev->name); |
09f75cd7 | 886 | dev->stats.tx_errors++; |
1da177e4 LT |
887 | } |
888 | ||
d344bff9 DF |
889 | spin_unlock_irqrestore(&mp->lock, flags); |
890 | ||
ff561eef DF |
891 | if (cmd_sts & ETH_TX_FIRST_DESC) |
892 | dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE); | |
cb415d30 | 893 | else |
ff561eef | 894 | dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE); |
1da177e4 | 895 | |
ff561eef DF |
896 | if (skb) |
897 | dev_kfree_skb_irq(skb); | |
898 | ||
899 | released = 1; | |
1da177e4 LT |
900 | } |
901 | ||
1da177e4 LT |
902 | return released; |
903 | } | |
904 | ||
ff561eef DF |
905 | static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev) |
906 | { | |
907 | struct mv643xx_private *mp = netdev_priv(dev); | |
908 | ||
909 | if (mv643xx_eth_free_tx_descs(dev, 0) && | |
910 | mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB) | |
911 | netif_wake_queue(dev); | |
912 | } | |
913 | ||
914 | static void mv643xx_eth_free_all_tx_descs(struct net_device *dev) | |
915 | { | |
916 | mv643xx_eth_free_tx_descs(dev, 1); | |
917 | } | |
918 | ||
1da177e4 LT |
919 | /* |
920 | * mv643xx_eth_receive | |
921 | * | |
922 | * This function is forward packets that are received from the port's | |
923 | * queues toward kernel core or FastRoute them to another interface. | |
924 | * | |
925 | * Input : dev - a pointer to the required interface | |
926 | * max - maximum number to receive (0 means unlimted) | |
927 | * | |
928 | * Output : number of served packets | |
929 | */ | |
1da177e4 | 930 | static int mv643xx_eth_receive_queue(struct net_device *dev, int budget) |
1da177e4 LT |
931 | { |
932 | struct mv643xx_private *mp = netdev_priv(dev); | |
09f75cd7 | 933 | struct net_device_stats *stats = &dev->stats; |
1da177e4 LT |
934 | unsigned int received_packets = 0; |
935 | struct sk_buff *skb; | |
936 | struct pkt_info pkt_info; | |
937 | ||
b1dd9ca1 | 938 | while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) { |
54caf44d | 939 | dma_unmap_single(NULL, pkt_info.buf_ptr, ETH_RX_SKB_SIZE, |
71d28725 | 940 | DMA_FROM_DEVICE); |
f98e36f1 | 941 | mp->rx_desc_count--; |
1da177e4 | 942 | received_packets++; |
b1dd9ca1 | 943 | |
468d09f8 DF |
944 | /* |
945 | * Update statistics. | |
946 | * Note byte count includes 4 byte CRC count | |
947 | */ | |
1da177e4 LT |
948 | stats->rx_packets++; |
949 | stats->rx_bytes += pkt_info.byte_cnt; | |
950 | skb = pkt_info.return_info; | |
951 | /* | |
952 | * In case received a packet without first / last bits on OR | |
953 | * the error summary bit is on, the packets needs to be dropeed. | |
954 | */ | |
955 | if (((pkt_info.cmd_sts | |
956 | & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) != | |
957 | (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) | |
958 | || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) { | |
959 | stats->rx_dropped++; | |
960 | if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC | | |
961 | ETH_RX_LAST_DESC)) != | |
962 | (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) { | |
963 | if (net_ratelimit()) | |
964 | printk(KERN_ERR | |
965 | "%s: Received packet spread " | |
966 | "on multiple descriptors\n", | |
967 | dev->name); | |
968 | } | |
969 | if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) | |
970 | stats->rx_errors++; | |
971 | ||
972 | dev_kfree_skb_irq(skb); | |
973 | } else { | |
974 | /* | |
975 | * The -4 is for the CRC in the trailer of the | |
976 | * received packet | |
977 | */ | |
978 | skb_put(skb, pkt_info.byte_cnt - 4); | |
1da177e4 LT |
979 | |
980 | if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) { | |
981 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
982 | skb->csum = htons( | |
983 | (pkt_info.cmd_sts & 0x0007fff8) >> 3); | |
984 | } | |
985 | skb->protocol = eth_type_trans(skb, dev); | |
986 | #ifdef MV643XX_NAPI | |
987 | netif_receive_skb(skb); | |
988 | #else | |
989 | netif_rx(skb); | |
990 | #endif | |
991 | } | |
12ad74f8 | 992 | dev->last_rx = jiffies; |
1da177e4 | 993 | } |
f78fb474 | 994 | mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */ |
1da177e4 LT |
995 | |
996 | return received_packets; | |
997 | } | |
998 | ||
d0412d96 JC |
999 | /* Set the mv643xx port configuration register for the speed/duplex mode. */ |
1000 | static void mv643xx_eth_update_pscr(struct net_device *dev, | |
1001 | struct ethtool_cmd *ecmd) | |
1002 | { | |
1003 | struct mv643xx_private *mp = netdev_priv(dev); | |
1004 | int port_num = mp->port_num; | |
1005 | u32 o_pscr, n_pscr; | |
12a87c64 | 1006 | unsigned int queues; |
d0412d96 | 1007 | |
ec69d651 | 1008 | o_pscr = rdl(mp, PORT_SERIAL_CONTROL_REG(port_num)); |
d0412d96 JC |
1009 | n_pscr = o_pscr; |
1010 | ||
1011 | /* clear speed, duplex and rx buffer size fields */ | |
e4d00fa9 LB |
1012 | n_pscr &= ~(SET_MII_SPEED_TO_100 | |
1013 | SET_GMII_SPEED_TO_1000 | | |
1014 | SET_FULL_DUPLEX_MODE | | |
1015 | MAX_RX_PACKET_MASK); | |
d0412d96 JC |
1016 | |
1017 | if (ecmd->duplex == DUPLEX_FULL) | |
e4d00fa9 | 1018 | n_pscr |= SET_FULL_DUPLEX_MODE; |
d0412d96 JC |
1019 | |
1020 | if (ecmd->speed == SPEED_1000) | |
e4d00fa9 LB |
1021 | n_pscr |= SET_GMII_SPEED_TO_1000 | |
1022 | MAX_RX_PACKET_9700BYTE; | |
d0412d96 JC |
1023 | else { |
1024 | if (ecmd->speed == SPEED_100) | |
e4d00fa9 LB |
1025 | n_pscr |= SET_MII_SPEED_TO_100; |
1026 | n_pscr |= MAX_RX_PACKET_1522BYTE; | |
d0412d96 JC |
1027 | } |
1028 | ||
1029 | if (n_pscr != o_pscr) { | |
e4d00fa9 | 1030 | if ((o_pscr & SERIAL_PORT_ENABLE) == 0) |
ec69d651 | 1031 | wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), n_pscr); |
d0412d96 | 1032 | else { |
afdb57a2 | 1033 | queues = mv643xx_eth_port_disable_tx(mp); |
d0412d96 | 1034 | |
e4d00fa9 | 1035 | o_pscr &= ~SERIAL_PORT_ENABLE; |
ec69d651 LB |
1036 | wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), o_pscr); |
1037 | wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), n_pscr); | |
1038 | wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), n_pscr); | |
12a87c64 | 1039 | if (queues) |
afdb57a2 | 1040 | mv643xx_eth_port_enable_tx(mp, queues); |
d0412d96 JC |
1041 | } |
1042 | } | |
1043 | } | |
1044 | ||
1da177e4 LT |
1045 | /* |
1046 | * mv643xx_eth_int_handler | |
1047 | * | |
1048 | * Main interrupt handler for the gigbit ethernet ports | |
1049 | * | |
1050 | * Input : irq - irq number (not used) | |
1051 | * dev_id - a pointer to the required interface's data structure | |
1052 | * regs - not used | |
1053 | * Output : N/A | |
1054 | */ | |
1055 | ||
7d12e780 | 1056 | static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id) |
1da177e4 LT |
1057 | { |
1058 | struct net_device *dev = (struct net_device *)dev_id; | |
1059 | struct mv643xx_private *mp = netdev_priv(dev); | |
1060 | u32 eth_int_cause, eth_int_cause_ext = 0; | |
1061 | unsigned int port_num = mp->port_num; | |
1062 | ||
1063 | /* Read interrupt cause registers */ | |
ec69d651 | 1064 | eth_int_cause = rdl(mp, INTERRUPT_CAUSE_REG(port_num)) & |
7303fde8 | 1065 | ETH_INT_UNMASK_ALL; |
468d09f8 | 1066 | if (eth_int_cause & ETH_INT_CAUSE_EXT) { |
ec69d651 | 1067 | eth_int_cause_ext = rdl(mp, |
e4d00fa9 | 1068 | INTERRUPT_CAUSE_EXTEND_REG(port_num)) & |
7303fde8 | 1069 | ETH_INT_UNMASK_ALL_EXT; |
ec69d651 | 1070 | wrl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num), |
468d09f8 | 1071 | ~eth_int_cause_ext); |
1da177e4 | 1072 | } |
7303fde8 | 1073 | |
1da177e4 | 1074 | /* PHY status changed */ |
2bcff60f | 1075 | if (eth_int_cause_ext & (ETH_INT_CAUSE_PHY | ETH_INT_CAUSE_STATE)) { |
d0412d96 JC |
1076 | struct ethtool_cmd cmd; |
1077 | ||
c28a4f89 | 1078 | if (mii_link_ok(&mp->mii)) { |
d0412d96 JC |
1079 | mii_ethtool_gset(&mp->mii, &cmd); |
1080 | mv643xx_eth_update_pscr(dev, &cmd); | |
afdb57a2 | 1081 | mv643xx_eth_port_enable_tx(mp, ETH_TX_QUEUES_ENABLED); |
c28a4f89 JC |
1082 | if (!netif_carrier_ok(dev)) { |
1083 | netif_carrier_on(dev); | |
ff561eef DF |
1084 | if (mp->tx_ring_size - mp->tx_desc_count >= |
1085 | MAX_DESCS_PER_SKB) | |
d0412d96 | 1086 | netif_wake_queue(dev); |
c28a4f89 JC |
1087 | } |
1088 | } else if (netif_carrier_ok(dev)) { | |
1da177e4 | 1089 | netif_stop_queue(dev); |
c28a4f89 | 1090 | netif_carrier_off(dev); |
1da177e4 LT |
1091 | } |
1092 | } | |
1093 | ||
468d09f8 DF |
1094 | #ifdef MV643XX_NAPI |
1095 | if (eth_int_cause & ETH_INT_CAUSE_RX) { | |
1096 | /* schedule the NAPI poll routine to maintain port */ | |
ec69d651 | 1097 | wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL); |
e4d00fa9 | 1098 | |
468d09f8 | 1099 | /* wait for previous write to complete */ |
ec69d651 | 1100 | rdl(mp, INTERRUPT_MASK_REG(port_num)); |
468d09f8 | 1101 | |
bea3348e | 1102 | netif_rx_schedule(dev, &mp->napi); |
468d09f8 DF |
1103 | } |
1104 | #else | |
1105 | if (eth_int_cause & ETH_INT_CAUSE_RX) | |
1106 | mv643xx_eth_receive_queue(dev, INT_MAX); | |
5c537408 | 1107 | #endif |
468d09f8 DF |
1108 | if (eth_int_cause_ext & ETH_INT_CAUSE_TX) |
1109 | mv643xx_eth_free_completed_tx_descs(dev); | |
468d09f8 | 1110 | |
1da177e4 LT |
1111 | /* |
1112 | * If no real interrupt occured, exit. | |
1113 | * This can happen when using gigE interrupt coalescing mechanism. | |
1114 | */ | |
1115 | if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0)) | |
1116 | return IRQ_NONE; | |
1117 | ||
1118 | return IRQ_HANDLED; | |
1119 | } | |
1120 | ||
1121 | #ifdef MV643XX_COAL | |
1122 | ||
1123 | /* | |
1124 | * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path | |
1125 | * | |
1126 | * DESCRIPTION: | |
1127 | * This routine sets the RX coalescing interrupt mechanism parameter. | |
1128 | * This parameter is a timeout counter, that counts in 64 t_clk | |
1129 | * chunks ; that when timeout event occurs a maskable interrupt | |
1130 | * occurs. | |
1131 | * The parameter is calculated using the tClk of the MV-643xx chip | |
1132 | * , and the required delay of the interrupt in usec. | |
1133 | * | |
1134 | * INPUT: | |
afdb57a2 | 1135 | * struct mv643xx_private *mp Ethernet port |
1da177e4 LT |
1136 | * unsigned int delay Delay in usec |
1137 | * | |
1138 | * OUTPUT: | |
1139 | * Interrupt coalescing mechanism value is set in MV-643xx chip. | |
1140 | * | |
1141 | * RETURN: | |
1142 | * The interrupt coalescing value set in the gigE port. | |
1143 | * | |
1144 | */ | |
afdb57a2 | 1145 | static unsigned int eth_port_set_rx_coal(struct mv643xx_private *mp, |
c416a41f | 1146 | unsigned int delay) |
1da177e4 | 1147 | { |
afdb57a2 | 1148 | unsigned int port_num = mp->port_num; |
c416a41f | 1149 | unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64; |
1da177e4 LT |
1150 | |
1151 | /* Set RX Coalescing mechanism */ | |
ec69d651 | 1152 | wrl(mp, SDMA_CONFIG_REG(port_num), |
1da177e4 | 1153 | ((coal & 0x3fff) << 8) | |
ec69d651 | 1154 | (rdl(mp, SDMA_CONFIG_REG(port_num)) |
1da177e4 LT |
1155 | & 0xffc000ff)); |
1156 | ||
1157 | return coal; | |
1158 | } | |
1159 | #endif | |
1160 | ||
1161 | /* | |
1162 | * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path | |
1163 | * | |
1164 | * DESCRIPTION: | |
1165 | * This routine sets the TX coalescing interrupt mechanism parameter. | |
1166 | * This parameter is a timeout counter, that counts in 64 t_clk | |
1167 | * chunks ; that when timeout event occurs a maskable interrupt | |
1168 | * occurs. | |
1169 | * The parameter is calculated using the t_cLK frequency of the | |
1170 | * MV-643xx chip and the required delay in the interrupt in uSec | |
1171 | * | |
1172 | * INPUT: | |
afdb57a2 | 1173 | * struct mv643xx_private *mp Ethernet port |
1da177e4 LT |
1174 | * unsigned int delay Delay in uSeconds |
1175 | * | |
1176 | * OUTPUT: | |
1177 | * Interrupt coalescing mechanism value is set in MV-643xx chip. | |
1178 | * | |
1179 | * RETURN: | |
1180 | * The interrupt coalescing value set in the gigE port. | |
1181 | * | |
1182 | */ | |
afdb57a2 | 1183 | static unsigned int eth_port_set_tx_coal(struct mv643xx_private *mp, |
c416a41f | 1184 | unsigned int delay) |
1da177e4 | 1185 | { |
c416a41f | 1186 | unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64; |
afdb57a2 | 1187 | |
1da177e4 | 1188 | /* Set TX Coalescing mechanism */ |
ec69d651 | 1189 | wrl(mp, TX_FIFO_URGENT_THRESHOLD_REG(mp->port_num), coal << 4); |
afdb57a2 | 1190 | |
1da177e4 LT |
1191 | return coal; |
1192 | } | |
1193 | ||
1da177e4 LT |
1194 | /* |
1195 | * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. | |
1196 | * | |
1197 | * DESCRIPTION: | |
1198 | * This function prepares a Rx chained list of descriptors and packet | |
1199 | * buffers in a form of a ring. The routine must be called after port | |
1200 | * initialization routine and before port start routine. | |
1201 | * The Ethernet SDMA engine uses CPU bus addresses to access the various | |
1202 | * devices in the system (i.e. DRAM). This function uses the ethernet | |
1203 | * struct 'virtual to physical' routine (set by the user) to set the ring | |
1204 | * with physical addresses. | |
1205 | * | |
1206 | * INPUT: | |
1207 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
1208 | * | |
1209 | * OUTPUT: | |
1210 | * The routine updates the Ethernet port control struct with information | |
1211 | * regarding the Rx descriptors and buffers. | |
1212 | * | |
1213 | * RETURN: | |
1214 | * None. | |
1215 | */ | |
1216 | static void ether_init_rx_desc_ring(struct mv643xx_private *mp) | |
1217 | { | |
1218 | volatile struct eth_rx_desc *p_rx_desc; | |
1219 | int rx_desc_num = mp->rx_ring_size; | |
1220 | int i; | |
1221 | ||
1222 | /* initialize the next_desc_ptr links in the Rx descriptors ring */ | |
1223 | p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area; | |
1224 | for (i = 0; i < rx_desc_num; i++) { | |
1225 | p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma + | |
1226 | ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc); | |
1227 | } | |
1228 | ||
1229 | /* Save Rx desc pointer to driver struct. */ | |
1230 | mp->rx_curr_desc_q = 0; | |
1231 | mp->rx_used_desc_q = 0; | |
1232 | ||
1233 | mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc); | |
1da177e4 LT |
1234 | } |
1235 | ||
1236 | /* | |
1237 | * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory. | |
1238 | * | |
1239 | * DESCRIPTION: | |
1240 | * This function prepares a Tx chained list of descriptors and packet | |
1241 | * buffers in a form of a ring. The routine must be called after port | |
1242 | * initialization routine and before port start routine. | |
1243 | * The Ethernet SDMA engine uses CPU bus addresses to access the various | |
1244 | * devices in the system (i.e. DRAM). This function uses the ethernet | |
1245 | * struct 'virtual to physical' routine (set by the user) to set the ring | |
1246 | * with physical addresses. | |
1247 | * | |
1248 | * INPUT: | |
1249 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
1250 | * | |
1251 | * OUTPUT: | |
1252 | * The routine updates the Ethernet port control struct with information | |
1253 | * regarding the Tx descriptors and buffers. | |
1254 | * | |
1255 | * RETURN: | |
1256 | * None. | |
1257 | */ | |
1258 | static void ether_init_tx_desc_ring(struct mv643xx_private *mp) | |
1259 | { | |
1260 | int tx_desc_num = mp->tx_ring_size; | |
1261 | struct eth_tx_desc *p_tx_desc; | |
1262 | int i; | |
1263 | ||
1264 | /* Initialize the next_desc_ptr links in the Tx descriptors ring */ | |
1265 | p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area; | |
1266 | for (i = 0; i < tx_desc_num; i++) { | |
1267 | p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma + | |
1268 | ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc); | |
1269 | } | |
1270 | ||
1271 | mp->tx_curr_desc_q = 0; | |
1272 | mp->tx_used_desc_q = 0; | |
1da177e4 LT |
1273 | |
1274 | mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc); | |
1da177e4 LT |
1275 | } |
1276 | ||
d0412d96 JC |
1277 | static int mv643xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
1278 | { | |
1279 | struct mv643xx_private *mp = netdev_priv(dev); | |
1280 | int err; | |
1281 | ||
1282 | spin_lock_irq(&mp->lock); | |
1283 | err = mii_ethtool_sset(&mp->mii, cmd); | |
1284 | spin_unlock_irq(&mp->lock); | |
1285 | ||
1286 | return err; | |
1287 | } | |
1288 | ||
1289 | static int mv643xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1290 | { | |
1291 | struct mv643xx_private *mp = netdev_priv(dev); | |
1292 | int err; | |
1293 | ||
1294 | spin_lock_irq(&mp->lock); | |
1295 | err = mii_ethtool_gset(&mp->mii, cmd); | |
1296 | spin_unlock_irq(&mp->lock); | |
1297 | ||
1298 | /* The PHY may support 1000baseT_Half, but the mv643xx does not */ | |
1299 | cmd->supported &= ~SUPPORTED_1000baseT_Half; | |
1300 | cmd->advertising &= ~ADVERTISED_1000baseT_Half; | |
1301 | ||
1302 | return err; | |
1303 | } | |
1304 | ||
ab4384a6 DF |
1305 | /* |
1306 | * mv643xx_eth_open | |
1307 | * | |
1308 | * This function is called when openning the network device. The function | |
1309 | * should initialize all the hardware, initialize cyclic Rx/Tx | |
1310 | * descriptors chain and buffers and allocate an IRQ to the network | |
1311 | * device. | |
1312 | * | |
1313 | * Input : a pointer to the network device structure | |
1314 | * | |
1315 | * Output : zero of success , nonzero if fails. | |
1316 | */ | |
1317 | ||
1318 | static int mv643xx_eth_open(struct net_device *dev) | |
1da177e4 LT |
1319 | { |
1320 | struct mv643xx_private *mp = netdev_priv(dev); | |
1321 | unsigned int port_num = mp->port_num; | |
1322 | unsigned int size; | |
ab4384a6 DF |
1323 | int err; |
1324 | ||
85cf572c | 1325 | /* Clear any pending ethernet port interrupts */ |
ec69d651 LB |
1326 | wrl(mp, INTERRUPT_CAUSE_REG(port_num), 0); |
1327 | wrl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num), 0); | |
85cf572c | 1328 | /* wait for previous write to complete */ |
ec69d651 | 1329 | rdl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num)); |
85cf572c | 1330 | |
ab4384a6 | 1331 | err = request_irq(dev->irq, mv643xx_eth_int_handler, |
1fb9df5d | 1332 | IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev); |
ab4384a6 | 1333 | if (err) { |
c1b35a28 | 1334 | printk(KERN_ERR "%s: Can not assign IRQ\n", dev->name); |
ab4384a6 DF |
1335 | return -EAGAIN; |
1336 | } | |
1da177e4 | 1337 | |
1da177e4 LT |
1338 | eth_port_init(mp); |
1339 | ||
1da177e4 | 1340 | memset(&mp->timeout, 0, sizeof(struct timer_list)); |
f78fb474 | 1341 | mp->timeout.function = mv643xx_eth_rx_refill_descs_timer_wrapper; |
1da177e4 LT |
1342 | mp->timeout.data = (unsigned long)dev; |
1343 | ||
1da177e4 LT |
1344 | /* Allocate RX and TX skb rings */ |
1345 | mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size, | |
1346 | GFP_KERNEL); | |
1347 | if (!mp->rx_skb) { | |
1348 | printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name); | |
ab4384a6 DF |
1349 | err = -ENOMEM; |
1350 | goto out_free_irq; | |
1da177e4 LT |
1351 | } |
1352 | mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size, | |
1353 | GFP_KERNEL); | |
1354 | if (!mp->tx_skb) { | |
1355 | printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name); | |
ab4384a6 DF |
1356 | err = -ENOMEM; |
1357 | goto out_free_rx_skb; | |
1da177e4 LT |
1358 | } |
1359 | ||
1360 | /* Allocate TX ring */ | |
f98e36f1 | 1361 | mp->tx_desc_count = 0; |
1da177e4 LT |
1362 | size = mp->tx_ring_size * sizeof(struct eth_tx_desc); |
1363 | mp->tx_desc_area_size = size; | |
1364 | ||
1365 | if (mp->tx_sram_size) { | |
1366 | mp->p_tx_desc_area = ioremap(mp->tx_sram_addr, | |
1367 | mp->tx_sram_size); | |
1368 | mp->tx_desc_dma = mp->tx_sram_addr; | |
1369 | } else | |
1370 | mp->p_tx_desc_area = dma_alloc_coherent(NULL, size, | |
1371 | &mp->tx_desc_dma, | |
1372 | GFP_KERNEL); | |
1373 | ||
1374 | if (!mp->p_tx_desc_area) { | |
1375 | printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n", | |
1376 | dev->name, size); | |
ab4384a6 DF |
1377 | err = -ENOMEM; |
1378 | goto out_free_tx_skb; | |
1da177e4 LT |
1379 | } |
1380 | BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */ | |
1381 | memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size); | |
1382 | ||
1383 | ether_init_tx_desc_ring(mp); | |
1384 | ||
1385 | /* Allocate RX ring */ | |
f98e36f1 | 1386 | mp->rx_desc_count = 0; |
1da177e4 LT |
1387 | size = mp->rx_ring_size * sizeof(struct eth_rx_desc); |
1388 | mp->rx_desc_area_size = size; | |
1389 | ||
1390 | if (mp->rx_sram_size) { | |
1391 | mp->p_rx_desc_area = ioremap(mp->rx_sram_addr, | |
1392 | mp->rx_sram_size); | |
1393 | mp->rx_desc_dma = mp->rx_sram_addr; | |
1394 | } else | |
1395 | mp->p_rx_desc_area = dma_alloc_coherent(NULL, size, | |
1396 | &mp->rx_desc_dma, | |
1397 | GFP_KERNEL); | |
1398 | ||
1399 | if (!mp->p_rx_desc_area) { | |
1400 | printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n", | |
1401 | dev->name, size); | |
1402 | printk(KERN_ERR "%s: Freeing previously allocated TX queues...", | |
1403 | dev->name); | |
1404 | if (mp->rx_sram_size) | |
dd09b1de | 1405 | iounmap(mp->p_tx_desc_area); |
1da177e4 LT |
1406 | else |
1407 | dma_free_coherent(NULL, mp->tx_desc_area_size, | |
1408 | mp->p_tx_desc_area, mp->tx_desc_dma); | |
ab4384a6 DF |
1409 | err = -ENOMEM; |
1410 | goto out_free_tx_skb; | |
1da177e4 LT |
1411 | } |
1412 | memset((void *)mp->p_rx_desc_area, 0, size); | |
1413 | ||
1414 | ether_init_rx_desc_ring(mp); | |
1415 | ||
f78fb474 | 1416 | mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */ |
1da177e4 | 1417 | |
bea3348e SH |
1418 | #ifdef MV643XX_NAPI |
1419 | napi_enable(&mp->napi); | |
1420 | #endif | |
1421 | ||
ed9b5d45 | 1422 | eth_port_start(dev); |
1da177e4 LT |
1423 | |
1424 | /* Interrupt Coalescing */ | |
1425 | ||
1426 | #ifdef MV643XX_COAL | |
1427 | mp->rx_int_coal = | |
c416a41f | 1428 | eth_port_set_rx_coal(mp, MV643XX_RX_COAL); |
1da177e4 LT |
1429 | #endif |
1430 | ||
1431 | mp->tx_int_coal = | |
c416a41f | 1432 | eth_port_set_tx_coal(mp, MV643XX_TX_COAL); |
1da177e4 | 1433 | |
8f518703 | 1434 | /* Unmask phy and link status changes interrupts */ |
ec69d651 | 1435 | wrl(mp, INTERRUPT_EXTEND_MASK_REG(port_num), ETH_INT_UNMASK_ALL_EXT); |
1da177e4 | 1436 | |
8f518703 | 1437 | /* Unmask RX buffer and TX end interrupt */ |
ec69d651 | 1438 | wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL); |
d0412d96 | 1439 | |
1da177e4 | 1440 | return 0; |
ab4384a6 DF |
1441 | |
1442 | out_free_tx_skb: | |
1443 | kfree(mp->tx_skb); | |
1444 | out_free_rx_skb: | |
1445 | kfree(mp->rx_skb); | |
1446 | out_free_irq: | |
1447 | free_irq(dev->irq, dev); | |
1448 | ||
1449 | return err; | |
1da177e4 LT |
1450 | } |
1451 | ||
1452 | static void mv643xx_eth_free_tx_rings(struct net_device *dev) | |
1453 | { | |
1454 | struct mv643xx_private *mp = netdev_priv(dev); | |
1da177e4 LT |
1455 | |
1456 | /* Stop Tx Queues */ | |
afdb57a2 | 1457 | mv643xx_eth_port_disable_tx(mp); |
1da177e4 | 1458 | |
ff561eef DF |
1459 | /* Free outstanding skb's on TX ring */ |
1460 | mv643xx_eth_free_all_tx_descs(dev); | |
1461 | ||
1462 | BUG_ON(mp->tx_used_desc_q != mp->tx_curr_desc_q); | |
1da177e4 LT |
1463 | |
1464 | /* Free TX ring */ | |
1465 | if (mp->tx_sram_size) | |
1466 | iounmap(mp->p_tx_desc_area); | |
1467 | else | |
1468 | dma_free_coherent(NULL, mp->tx_desc_area_size, | |
1469 | mp->p_tx_desc_area, mp->tx_desc_dma); | |
1470 | } | |
1471 | ||
1472 | static void mv643xx_eth_free_rx_rings(struct net_device *dev) | |
1473 | { | |
1474 | struct mv643xx_private *mp = netdev_priv(dev); | |
1da177e4 LT |
1475 | int curr; |
1476 | ||
1477 | /* Stop RX Queues */ | |
afdb57a2 | 1478 | mv643xx_eth_port_disable_rx(mp); |
1da177e4 LT |
1479 | |
1480 | /* Free preallocated skb's on RX rings */ | |
f98e36f1 | 1481 | for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) { |
1da177e4 LT |
1482 | if (mp->rx_skb[curr]) { |
1483 | dev_kfree_skb(mp->rx_skb[curr]); | |
f98e36f1 | 1484 | mp->rx_desc_count--; |
1da177e4 LT |
1485 | } |
1486 | } | |
1487 | ||
f98e36f1 | 1488 | if (mp->rx_desc_count) |
1da177e4 LT |
1489 | printk(KERN_ERR |
1490 | "%s: Error in freeing Rx Ring. %d skb's still" | |
1491 | " stuck in RX Ring - ignoring them\n", dev->name, | |
f98e36f1 | 1492 | mp->rx_desc_count); |
1da177e4 LT |
1493 | /* Free RX ring */ |
1494 | if (mp->rx_sram_size) | |
1495 | iounmap(mp->p_rx_desc_area); | |
1496 | else | |
1497 | dma_free_coherent(NULL, mp->rx_desc_area_size, | |
1498 | mp->p_rx_desc_area, mp->rx_desc_dma); | |
1499 | } | |
1500 | ||
1501 | /* | |
1502 | * mv643xx_eth_stop | |
1503 | * | |
1504 | * This function is used when closing the network device. | |
1505 | * It updates the hardware, | |
1506 | * release all memory that holds buffers and descriptors and release the IRQ. | |
1507 | * Input : a pointer to the device structure | |
1508 | * Output : zero if success , nonzero if fails | |
1509 | */ | |
1510 | ||
ab4384a6 | 1511 | static int mv643xx_eth_stop(struct net_device *dev) |
1da177e4 LT |
1512 | { |
1513 | struct mv643xx_private *mp = netdev_priv(dev); | |
1514 | unsigned int port_num = mp->port_num; | |
1515 | ||
c2e5b352 | 1516 | /* Mask all interrupts on ethernet port */ |
ec69d651 | 1517 | wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL); |
c2e5b352 | 1518 | /* wait for previous write to complete */ |
ec69d651 | 1519 | rdl(mp, INTERRUPT_MASK_REG(port_num)); |
8f518703 DF |
1520 | |
1521 | #ifdef MV643XX_NAPI | |
bea3348e | 1522 | napi_disable(&mp->napi); |
8f518703 | 1523 | #endif |
1da177e4 LT |
1524 | netif_carrier_off(dev); |
1525 | netif_stop_queue(dev); | |
1526 | ||
afdb57a2 | 1527 | eth_port_reset(mp); |
1da177e4 | 1528 | |
8f518703 DF |
1529 | mv643xx_eth_free_tx_rings(dev); |
1530 | mv643xx_eth_free_rx_rings(dev); | |
1da177e4 | 1531 | |
1da177e4 | 1532 | free_irq(dev->irq, dev); |
1da177e4 LT |
1533 | |
1534 | return 0; | |
1535 | } | |
1536 | ||
1537 | #ifdef MV643XX_NAPI | |
1da177e4 LT |
1538 | /* |
1539 | * mv643xx_poll | |
1540 | * | |
1541 | * This function is used in case of NAPI | |
1542 | */ | |
bea3348e | 1543 | static int mv643xx_poll(struct napi_struct *napi, int budget) |
1da177e4 | 1544 | { |
bea3348e SH |
1545 | struct mv643xx_private *mp = container_of(napi, struct mv643xx_private, napi); |
1546 | struct net_device *dev = mp->dev; | |
1da177e4 | 1547 | unsigned int port_num = mp->port_num; |
bea3348e | 1548 | int work_done; |
1da177e4 LT |
1549 | |
1550 | #ifdef MV643XX_TX_FAST_REFILL | |
1551 | if (++mp->tx_clean_threshold > 5) { | |
ff561eef | 1552 | mv643xx_eth_free_completed_tx_descs(dev); |
1da177e4 | 1553 | mp->tx_clean_threshold = 0; |
1da177e4 LT |
1554 | } |
1555 | #endif | |
1556 | ||
bea3348e | 1557 | work_done = 0; |
ec69d651 | 1558 | if ((rdl(mp, RX_CURRENT_QUEUE_DESC_PTR_0(port_num))) |
bea3348e SH |
1559 | != (u32) mp->rx_used_desc_q) |
1560 | work_done = mv643xx_eth_receive_queue(dev, budget); | |
1da177e4 | 1561 | |
bea3348e SH |
1562 | if (work_done < budget) { |
1563 | netif_rx_complete(dev, napi); | |
ec69d651 LB |
1564 | wrl(mp, INTERRUPT_CAUSE_REG(port_num), 0); |
1565 | wrl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num), 0); | |
1566 | wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL); | |
1da177e4 LT |
1567 | } |
1568 | ||
bea3348e | 1569 | return work_done; |
1da177e4 LT |
1570 | } |
1571 | #endif | |
1572 | ||
c8aaea25 DF |
1573 | /** |
1574 | * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments | |
1575 | * | |
1576 | * Hardware can't handle unaligned fragments smaller than 9 bytes. | |
f7ea3337 PJ |
1577 | * This helper function detects that case. |
1578 | */ | |
1579 | ||
1580 | static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) | |
1581 | { | |
b4de9051 DF |
1582 | unsigned int frag; |
1583 | skb_frag_t *fragp; | |
f7ea3337 | 1584 | |
b4de9051 DF |
1585 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { |
1586 | fragp = &skb_shinfo(skb)->frags[frag]; | |
1587 | if (fragp->size <= 8 && fragp->page_offset & 0x7) | |
1588 | return 1; | |
1589 | } | |
1590 | return 0; | |
f7ea3337 PJ |
1591 | } |
1592 | ||
c8aaea25 DF |
1593 | /** |
1594 | * eth_alloc_tx_desc_index - return the index of the next available tx desc | |
1595 | */ | |
1596 | static int eth_alloc_tx_desc_index(struct mv643xx_private *mp) | |
1597 | { | |
1598 | int tx_desc_curr; | |
1599 | ||
c8aaea25 | 1600 | BUG_ON(mp->tx_desc_count >= mp->tx_ring_size); |
c8aaea25 | 1601 | |
ff561eef | 1602 | tx_desc_curr = mp->tx_curr_desc_q; |
c8aaea25 DF |
1603 | mp->tx_curr_desc_q = (tx_desc_curr + 1) % mp->tx_ring_size; |
1604 | ||
1605 | BUG_ON(mp->tx_curr_desc_q == mp->tx_used_desc_q); | |
1606 | ||
1607 | return tx_desc_curr; | |
1608 | } | |
1609 | ||
1610 | /** | |
1611 | * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments. | |
1da177e4 | 1612 | * |
c8aaea25 DF |
1613 | * Ensure the data for each fragment to be transmitted is mapped properly, |
1614 | * then fill in descriptors in the tx hw queue. | |
1da177e4 | 1615 | */ |
c8aaea25 DF |
1616 | static void eth_tx_fill_frag_descs(struct mv643xx_private *mp, |
1617 | struct sk_buff *skb) | |
1da177e4 | 1618 | { |
c8aaea25 DF |
1619 | int frag; |
1620 | int tx_index; | |
1621 | struct eth_tx_desc *desc; | |
1da177e4 | 1622 | |
c8aaea25 DF |
1623 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { |
1624 | skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag]; | |
1625 | ||
1626 | tx_index = eth_alloc_tx_desc_index(mp); | |
1627 | desc = &mp->p_tx_desc_area[tx_index]; | |
1628 | ||
1629 | desc->cmd_sts = ETH_BUFFER_OWNED_BY_DMA; | |
1630 | /* Last Frag enables interrupt and frees the skb */ | |
1631 | if (frag == (skb_shinfo(skb)->nr_frags - 1)) { | |
1632 | desc->cmd_sts |= ETH_ZERO_PADDING | | |
1633 | ETH_TX_LAST_DESC | | |
1634 | ETH_TX_ENABLE_INTERRUPT; | |
1635 | mp->tx_skb[tx_index] = skb; | |
1636 | } else | |
05980775 | 1637 | mp->tx_skb[tx_index] = NULL; |
c8aaea25 DF |
1638 | |
1639 | desc = &mp->p_tx_desc_area[tx_index]; | |
1640 | desc->l4i_chk = 0; | |
1641 | desc->byte_cnt = this_frag->size; | |
1642 | desc->buf_ptr = dma_map_page(NULL, this_frag->page, | |
1643 | this_frag->page_offset, | |
1644 | this_frag->size, | |
1645 | DMA_TO_DEVICE); | |
1da177e4 | 1646 | } |
c8aaea25 | 1647 | } |
1da177e4 | 1648 | |
324ff2c1 BB |
1649 | static inline __be16 sum16_as_be(__sum16 sum) |
1650 | { | |
1651 | return (__force __be16)sum; | |
1652 | } | |
1653 | ||
c8aaea25 DF |
1654 | /** |
1655 | * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw | |
1656 | * | |
1657 | * Ensure the data for an skb to be transmitted is mapped properly, | |
1658 | * then fill in descriptors in the tx hw queue and start the hardware. | |
1659 | */ | |
ff561eef DF |
1660 | static void eth_tx_submit_descs_for_skb(struct mv643xx_private *mp, |
1661 | struct sk_buff *skb) | |
c8aaea25 DF |
1662 | { |
1663 | int tx_index; | |
1664 | struct eth_tx_desc *desc; | |
1665 | u32 cmd_sts; | |
1666 | int length; | |
ff561eef | 1667 | int nr_frags = skb_shinfo(skb)->nr_frags; |
1da177e4 | 1668 | |
c8aaea25 | 1669 | cmd_sts = ETH_TX_FIRST_DESC | ETH_GEN_CRC | ETH_BUFFER_OWNED_BY_DMA; |
1da177e4 | 1670 | |
c8aaea25 DF |
1671 | tx_index = eth_alloc_tx_desc_index(mp); |
1672 | desc = &mp->p_tx_desc_area[tx_index]; | |
1673 | ||
ff561eef | 1674 | if (nr_frags) { |
c8aaea25 DF |
1675 | eth_tx_fill_frag_descs(mp, skb); |
1676 | ||
1677 | length = skb_headlen(skb); | |
05980775 | 1678 | mp->tx_skb[tx_index] = NULL; |
c8aaea25 DF |
1679 | } else { |
1680 | cmd_sts |= ETH_ZERO_PADDING | | |
1681 | ETH_TX_LAST_DESC | | |
1682 | ETH_TX_ENABLE_INTERRUPT; | |
1683 | length = skb->len; | |
1684 | mp->tx_skb[tx_index] = skb; | |
f7ea3337 PJ |
1685 | } |
1686 | ||
c8aaea25 DF |
1687 | desc->byte_cnt = length; |
1688 | desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE); | |
1da177e4 | 1689 | |
84fa7933 | 1690 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
324ff2c1 | 1691 | BUG_ON(skb->protocol != htons(ETH_P_IP)); |
c8aaea25 DF |
1692 | |
1693 | cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM | | |
1694 | ETH_GEN_IP_V_4_CHECKSUM | | |
eddc9ec5 | 1695 | ip_hdr(skb)->ihl << ETH_TX_IHL_SHIFT; |
c8aaea25 | 1696 | |
eddc9ec5 | 1697 | switch (ip_hdr(skb)->protocol) { |
c8aaea25 DF |
1698 | case IPPROTO_UDP: |
1699 | cmd_sts |= ETH_UDP_FRAME; | |
324ff2c1 | 1700 | desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check)); |
c8aaea25 DF |
1701 | break; |
1702 | case IPPROTO_TCP: | |
324ff2c1 | 1703 | desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check)); |
c8aaea25 DF |
1704 | break; |
1705 | default: | |
1706 | BUG(); | |
1da177e4 | 1707 | } |
1da177e4 | 1708 | } else { |
c8aaea25 DF |
1709 | /* Errata BTS #50, IHL must be 5 if no HW checksum */ |
1710 | cmd_sts |= 5 << ETH_TX_IHL_SHIFT; | |
1711 | desc->l4i_chk = 0; | |
1712 | } | |
1da177e4 | 1713 | |
c8aaea25 DF |
1714 | /* ensure all other descriptors are written before first cmd_sts */ |
1715 | wmb(); | |
1716 | desc->cmd_sts = cmd_sts; | |
1da177e4 | 1717 | |
c8aaea25 DF |
1718 | /* ensure all descriptors are written before poking hardware */ |
1719 | wmb(); | |
afdb57a2 | 1720 | mv643xx_eth_port_enable_tx(mp, ETH_TX_QUEUES_ENABLED); |
1da177e4 | 1721 | |
ff561eef | 1722 | mp->tx_desc_count += nr_frags + 1; |
c8aaea25 | 1723 | } |
1da177e4 | 1724 | |
c8aaea25 DF |
1725 | /** |
1726 | * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission | |
1727 | * | |
1728 | */ | |
1729 | static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
1730 | { | |
1731 | struct mv643xx_private *mp = netdev_priv(dev); | |
09f75cd7 | 1732 | struct net_device_stats *stats = &dev->stats; |
c8aaea25 | 1733 | unsigned long flags; |
1da177e4 | 1734 | |
c8aaea25 | 1735 | BUG_ON(netif_queue_stopped(dev)); |
94843566 | 1736 | |
4d64e718 LB |
1737 | if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) { |
1738 | stats->tx_dropped++; | |
1739 | printk(KERN_DEBUG "%s: failed to linearize tiny " | |
1740 | "unaligned fragment\n", dev->name); | |
c0d0f2ca | 1741 | return NETDEV_TX_BUSY; |
4d64e718 LB |
1742 | } |
1743 | ||
1744 | spin_lock_irqsave(&mp->lock, flags); | |
1745 | ||
94843566 DF |
1746 | if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) { |
1747 | printk(KERN_ERR "%s: transmit with queue full\n", dev->name); | |
1748 | netif_stop_queue(dev); | |
4d64e718 | 1749 | spin_unlock_irqrestore(&mp->lock, flags); |
c0d0f2ca | 1750 | return NETDEV_TX_BUSY; |
94843566 | 1751 | } |
1da177e4 | 1752 | |
ff561eef | 1753 | eth_tx_submit_descs_for_skb(mp, skb); |
e7e381f6 | 1754 | stats->tx_bytes += skb->len; |
1da177e4 LT |
1755 | stats->tx_packets++; |
1756 | dev->trans_start = jiffies; | |
1757 | ||
c8aaea25 DF |
1758 | if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) |
1759 | netif_stop_queue(dev); | |
1760 | ||
1da177e4 LT |
1761 | spin_unlock_irqrestore(&mp->lock, flags); |
1762 | ||
c0d0f2ca | 1763 | return NETDEV_TX_OK; |
1da177e4 LT |
1764 | } |
1765 | ||
63c9e549 | 1766 | #ifdef CONFIG_NET_POLL_CONTROLLER |
63c9e549 DF |
1767 | static void mv643xx_netpoll(struct net_device *netdev) |
1768 | { | |
1769 | struct mv643xx_private *mp = netdev_priv(netdev); | |
c2e5b352 DF |
1770 | int port_num = mp->port_num; |
1771 | ||
ec69d651 | 1772 | wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL); |
c2e5b352 | 1773 | /* wait for previous write to complete */ |
ec69d651 | 1774 | rdl(mp, INTERRUPT_MASK_REG(port_num)); |
63c9e549 | 1775 | |
9da3b1ad | 1776 | mv643xx_eth_int_handler(netdev->irq, netdev); |
c2e5b352 | 1777 | |
ec69d651 | 1778 | wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL); |
63c9e549 DF |
1779 | } |
1780 | #endif | |
1781 | ||
d0412d96 JC |
1782 | static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address, |
1783 | int speed, int duplex, | |
1784 | struct ethtool_cmd *cmd) | |
1785 | { | |
1786 | struct mv643xx_private *mp = netdev_priv(dev); | |
1787 | ||
1788 | memset(cmd, 0, sizeof(*cmd)); | |
1789 | ||
1790 | cmd->port = PORT_MII; | |
1791 | cmd->transceiver = XCVR_INTERNAL; | |
1792 | cmd->phy_address = phy_address; | |
1793 | ||
1794 | if (speed == 0) { | |
1795 | cmd->autoneg = AUTONEG_ENABLE; | |
1796 | /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */ | |
1797 | cmd->speed = SPEED_100; | |
1798 | cmd->advertising = ADVERTISED_10baseT_Half | | |
1799 | ADVERTISED_10baseT_Full | | |
1800 | ADVERTISED_100baseT_Half | | |
1801 | ADVERTISED_100baseT_Full; | |
1802 | if (mp->mii.supports_gmii) | |
1803 | cmd->advertising |= ADVERTISED_1000baseT_Full; | |
1804 | } else { | |
1805 | cmd->autoneg = AUTONEG_DISABLE; | |
1806 | cmd->speed = speed; | |
1807 | cmd->duplex = duplex; | |
1808 | } | |
1809 | } | |
1810 | ||
1da177e4 LT |
1811 | /*/ |
1812 | * mv643xx_eth_probe | |
1813 | * | |
1814 | * First function called after registering the network device. | |
1815 | * It's purpose is to initialize the device as an ethernet device, | |
1816 | * fill the ethernet device structure with pointers * to functions, | |
1817 | * and set the MAC address of the interface | |
1818 | * | |
1819 | * Input : struct device * | |
1820 | * Output : -ENOMEM if failed , 0 if success | |
1821 | */ | |
3ae5eaec | 1822 | static int mv643xx_eth_probe(struct platform_device *pdev) |
1da177e4 | 1823 | { |
1da177e4 | 1824 | struct mv643xx_eth_platform_data *pd; |
84dd619e | 1825 | int port_num; |
1da177e4 LT |
1826 | struct mv643xx_private *mp; |
1827 | struct net_device *dev; | |
1828 | u8 *p; | |
1829 | struct resource *res; | |
1830 | int err; | |
d0412d96 | 1831 | struct ethtool_cmd cmd; |
01999873 DF |
1832 | int duplex = DUPLEX_HALF; |
1833 | int speed = 0; /* default to auto-negotiation */ | |
c5d6471f | 1834 | DECLARE_MAC_BUF(mac); |
1da177e4 | 1835 | |
84dd619e DF |
1836 | pd = pdev->dev.platform_data; |
1837 | if (pd == NULL) { | |
1838 | printk(KERN_ERR "No mv643xx_eth_platform_data\n"); | |
1839 | return -ENODEV; | |
1840 | } | |
1841 | ||
fa3959f4 LB |
1842 | if (pd->shared == NULL) { |
1843 | printk(KERN_ERR "No mv643xx_eth_platform_data->shared\n"); | |
1844 | return -ENODEV; | |
1845 | } | |
1846 | ||
1da177e4 LT |
1847 | dev = alloc_etherdev(sizeof(struct mv643xx_private)); |
1848 | if (!dev) | |
1849 | return -ENOMEM; | |
1850 | ||
3ae5eaec | 1851 | platform_set_drvdata(pdev, dev); |
1da177e4 LT |
1852 | |
1853 | mp = netdev_priv(dev); | |
bea3348e SH |
1854 | mp->dev = dev; |
1855 | #ifdef MV643XX_NAPI | |
1856 | netif_napi_add(dev, &mp->napi, mv643xx_poll, 64); | |
1857 | #endif | |
1da177e4 LT |
1858 | |
1859 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1860 | BUG_ON(!res); | |
1861 | dev->irq = res->start; | |
1862 | ||
1da177e4 LT |
1863 | dev->open = mv643xx_eth_open; |
1864 | dev->stop = mv643xx_eth_stop; | |
1865 | dev->hard_start_xmit = mv643xx_eth_start_xmit; | |
1da177e4 LT |
1866 | dev->set_mac_address = mv643xx_eth_set_mac_address; |
1867 | dev->set_multicast_list = mv643xx_eth_set_rx_mode; | |
1868 | ||
1869 | /* No need to Tx Timeout */ | |
1870 | dev->tx_timeout = mv643xx_eth_tx_timeout; | |
1da177e4 | 1871 | |
63c9e549 DF |
1872 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1873 | dev->poll_controller = mv643xx_netpoll; | |
1874 | #endif | |
1875 | ||
1da177e4 | 1876 | dev->watchdog_timeo = 2 * HZ; |
1da177e4 LT |
1877 | dev->base_addr = 0; |
1878 | dev->change_mtu = mv643xx_eth_change_mtu; | |
d0412d96 | 1879 | dev->do_ioctl = mv643xx_eth_do_ioctl; |
1da177e4 LT |
1880 | SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops); |
1881 | ||
1882 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX | |
1883 | #ifdef MAX_SKB_FRAGS | |
1884 | /* | |
1885 | * Zero copy can only work if we use Discovery II memory. Else, we will | |
1886 | * have to map the buffers to ISA memory which is only 16 MB | |
1887 | */ | |
63890576 | 1888 | dev->features = NETIF_F_SG | NETIF_F_IP_CSUM; |
1da177e4 LT |
1889 | #endif |
1890 | #endif | |
1891 | ||
1892 | /* Configure the timeout task */ | |
91c7c568 | 1893 | INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task); |
1da177e4 LT |
1894 | |
1895 | spin_lock_init(&mp->lock); | |
1896 | ||
fa3959f4 | 1897 | mp->shared = platform_get_drvdata(pd->shared); |
fadac406 | 1898 | port_num = mp->port_num = pd->port_number; |
84dd619e | 1899 | |
f2ce825d LB |
1900 | if (mp->shared->win_protect) |
1901 | wrl(mp, WINDOW_PROTECT(port_num), mp->shared->win_protect); | |
1902 | ||
ce4e2e45 LB |
1903 | mp->shared_smi = mp->shared; |
1904 | if (pd->shared_smi != NULL) | |
1905 | mp->shared_smi = platform_get_drvdata(pd->shared_smi); | |
1906 | ||
1da177e4 | 1907 | /* set default config values */ |
afdb57a2 | 1908 | eth_port_uc_addr_get(mp, dev->dev_addr); |
e4d00fa9 LB |
1909 | mp->rx_ring_size = PORT_DEFAULT_RECEIVE_QUEUE_SIZE; |
1910 | mp->tx_ring_size = PORT_DEFAULT_TRANSMIT_QUEUE_SIZE; | |
1da177e4 | 1911 | |
84dd619e DF |
1912 | if (is_valid_ether_addr(pd->mac_addr)) |
1913 | memcpy(dev->dev_addr, pd->mac_addr, 6); | |
1da177e4 | 1914 | |
84dd619e | 1915 | if (pd->phy_addr || pd->force_phy_addr) |
afdb57a2 | 1916 | ethernet_phy_set(mp, pd->phy_addr); |
1da177e4 | 1917 | |
84dd619e DF |
1918 | if (pd->rx_queue_size) |
1919 | mp->rx_ring_size = pd->rx_queue_size; | |
1da177e4 | 1920 | |
84dd619e DF |
1921 | if (pd->tx_queue_size) |
1922 | mp->tx_ring_size = pd->tx_queue_size; | |
1da177e4 | 1923 | |
84dd619e DF |
1924 | if (pd->tx_sram_size) { |
1925 | mp->tx_sram_size = pd->tx_sram_size; | |
1926 | mp->tx_sram_addr = pd->tx_sram_addr; | |
1927 | } | |
01999873 | 1928 | |
84dd619e DF |
1929 | if (pd->rx_sram_size) { |
1930 | mp->rx_sram_size = pd->rx_sram_size; | |
1931 | mp->rx_sram_addr = pd->rx_sram_addr; | |
1da177e4 LT |
1932 | } |
1933 | ||
84dd619e DF |
1934 | duplex = pd->duplex; |
1935 | speed = pd->speed; | |
1936 | ||
c28a4f89 JC |
1937 | /* Hook up MII support for ethtool */ |
1938 | mp->mii.dev = dev; | |
1939 | mp->mii.mdio_read = mv643xx_mdio_read; | |
1940 | mp->mii.mdio_write = mv643xx_mdio_write; | |
afdb57a2 | 1941 | mp->mii.phy_id = ethernet_phy_get(mp); |
c28a4f89 JC |
1942 | mp->mii.phy_id_mask = 0x3f; |
1943 | mp->mii.reg_num_mask = 0x1f; | |
1944 | ||
afdb57a2 | 1945 | err = ethernet_phy_detect(mp); |
1da177e4 | 1946 | if (err) { |
c1b35a28 LB |
1947 | pr_debug("%s: No PHY detected at addr %d\n", |
1948 | dev->name, ethernet_phy_get(mp)); | |
d0412d96 | 1949 | goto out; |
1da177e4 LT |
1950 | } |
1951 | ||
afdb57a2 | 1952 | ethernet_phy_reset(mp); |
c28a4f89 | 1953 | mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii); |
d0412d96 JC |
1954 | mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd); |
1955 | mv643xx_eth_update_pscr(dev, &cmd); | |
1956 | mv643xx_set_settings(dev, &cmd); | |
c28a4f89 | 1957 | |
b0b8dab2 | 1958 | SET_NETDEV_DEV(dev, &pdev->dev); |
1da177e4 LT |
1959 | err = register_netdev(dev); |
1960 | if (err) | |
1961 | goto out; | |
1962 | ||
1963 | p = dev->dev_addr; | |
1964 | printk(KERN_NOTICE | |
0795af57 JP |
1965 | "%s: port %d with MAC address %s\n", |
1966 | dev->name, port_num, print_mac(mac, p)); | |
1da177e4 LT |
1967 | |
1968 | if (dev->features & NETIF_F_SG) | |
1969 | printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name); | |
1970 | ||
1971 | if (dev->features & NETIF_F_IP_CSUM) | |
1972 | printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n", | |
1973 | dev->name); | |
1974 | ||
1975 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX | |
1976 | printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name); | |
1977 | #endif | |
1978 | ||
1979 | #ifdef MV643XX_COAL | |
1980 | printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n", | |
1981 | dev->name); | |
1982 | #endif | |
1983 | ||
1984 | #ifdef MV643XX_NAPI | |
1985 | printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name); | |
1986 | #endif | |
1987 | ||
b1529871 ND |
1988 | if (mp->tx_sram_size > 0) |
1989 | printk(KERN_NOTICE "%s: Using SRAM\n", dev->name); | |
1990 | ||
1da177e4 LT |
1991 | return 0; |
1992 | ||
1993 | out: | |
1994 | free_netdev(dev); | |
1995 | ||
1996 | return err; | |
1997 | } | |
1998 | ||
3ae5eaec | 1999 | static int mv643xx_eth_remove(struct platform_device *pdev) |
1da177e4 | 2000 | { |
3ae5eaec | 2001 | struct net_device *dev = platform_get_drvdata(pdev); |
1da177e4 LT |
2002 | |
2003 | unregister_netdev(dev); | |
2004 | flush_scheduled_work(); | |
2005 | ||
2006 | free_netdev(dev); | |
3ae5eaec | 2007 | platform_set_drvdata(pdev, NULL); |
1da177e4 LT |
2008 | return 0; |
2009 | } | |
2010 | ||
f2ce825d LB |
2011 | static void mv643xx_eth_conf_mbus_windows(struct mv643xx_shared_private *msp, |
2012 | struct mbus_dram_target_info *dram) | |
2013 | { | |
2014 | void __iomem *base = msp->eth_base; | |
2015 | u32 win_enable; | |
2016 | u32 win_protect; | |
2017 | int i; | |
2018 | ||
2019 | for (i = 0; i < 6; i++) { | |
2020 | writel(0, base + WINDOW_BASE(i)); | |
2021 | writel(0, base + WINDOW_SIZE(i)); | |
2022 | if (i < 4) | |
2023 | writel(0, base + WINDOW_REMAP_HIGH(i)); | |
2024 | } | |
2025 | ||
2026 | win_enable = 0x3f; | |
2027 | win_protect = 0; | |
2028 | ||
2029 | for (i = 0; i < dram->num_cs; i++) { | |
2030 | struct mbus_dram_window *cs = dram->cs + i; | |
2031 | ||
2032 | writel((cs->base & 0xffff0000) | | |
2033 | (cs->mbus_attr << 8) | | |
2034 | dram->mbus_dram_target_id, base + WINDOW_BASE(i)); | |
2035 | writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); | |
2036 | ||
2037 | win_enable &= ~(1 << i); | |
2038 | win_protect |= 3 << (2 * i); | |
2039 | } | |
2040 | ||
2041 | writel(win_enable, base + WINDOW_BAR_ENABLE); | |
2042 | msp->win_protect = win_protect; | |
2043 | } | |
2044 | ||
3ae5eaec | 2045 | static int mv643xx_eth_shared_probe(struct platform_device *pdev) |
1da177e4 | 2046 | { |
e519abb6 | 2047 | static int mv643xx_version_printed = 0; |
f2ce825d | 2048 | struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data; |
fa3959f4 | 2049 | struct mv643xx_shared_private *msp; |
1da177e4 | 2050 | struct resource *res; |
fa3959f4 | 2051 | int ret; |
1da177e4 | 2052 | |
e519abb6 LB |
2053 | if (!mv643xx_version_printed++) |
2054 | printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n"); | |
1da177e4 | 2055 | |
fa3959f4 | 2056 | ret = -EINVAL; |
1da177e4 LT |
2057 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2058 | if (res == NULL) | |
fa3959f4 | 2059 | goto out; |
1da177e4 | 2060 | |
fa3959f4 LB |
2061 | ret = -ENOMEM; |
2062 | msp = kmalloc(sizeof(*msp), GFP_KERNEL); | |
2063 | if (msp == NULL) | |
2064 | goto out; | |
2065 | memset(msp, 0, sizeof(*msp)); | |
2066 | ||
2067 | msp->eth_base = ioremap(res->start, res->end - res->start + 1); | |
2068 | if (msp->eth_base == NULL) | |
2069 | goto out_free; | |
2070 | ||
2071 | spin_lock_init(&msp->phy_lock); | |
c416a41f | 2072 | msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000; |
fa3959f4 LB |
2073 | |
2074 | platform_set_drvdata(pdev, msp); | |
1da177e4 | 2075 | |
f2ce825d LB |
2076 | /* |
2077 | * (Re-)program MBUS remapping windows if we are asked to. | |
2078 | */ | |
2079 | if (pd != NULL && pd->dram != NULL) | |
2080 | mv643xx_eth_conf_mbus_windows(msp, pd->dram); | |
2081 | ||
1da177e4 LT |
2082 | return 0; |
2083 | ||
fa3959f4 LB |
2084 | out_free: |
2085 | kfree(msp); | |
2086 | out: | |
2087 | return ret; | |
1da177e4 LT |
2088 | } |
2089 | ||
3ae5eaec | 2090 | static int mv643xx_eth_shared_remove(struct platform_device *pdev) |
1da177e4 | 2091 | { |
fa3959f4 LB |
2092 | struct mv643xx_shared_private *msp = platform_get_drvdata(pdev); |
2093 | ||
2094 | iounmap(msp->eth_base); | |
2095 | kfree(msp); | |
1da177e4 LT |
2096 | |
2097 | return 0; | |
2098 | } | |
2099 | ||
d57ab6fd DF |
2100 | static void mv643xx_eth_shutdown(struct platform_device *pdev) |
2101 | { | |
2102 | struct net_device *dev = platform_get_drvdata(pdev); | |
2103 | struct mv643xx_private *mp = netdev_priv(dev); | |
2104 | unsigned int port_num = mp->port_num; | |
2105 | ||
2106 | /* Mask all interrupts on ethernet port */ | |
ec69d651 LB |
2107 | wrl(mp, INTERRUPT_MASK_REG(port_num), 0); |
2108 | rdl(mp, INTERRUPT_MASK_REG(port_num)); | |
d57ab6fd | 2109 | |
afdb57a2 | 2110 | eth_port_reset(mp); |
d57ab6fd DF |
2111 | } |
2112 | ||
3ae5eaec | 2113 | static struct platform_driver mv643xx_eth_driver = { |
1da177e4 LT |
2114 | .probe = mv643xx_eth_probe, |
2115 | .remove = mv643xx_eth_remove, | |
d57ab6fd | 2116 | .shutdown = mv643xx_eth_shutdown, |
3ae5eaec RK |
2117 | .driver = { |
2118 | .name = MV643XX_ETH_NAME, | |
72abb461 | 2119 | .owner = THIS_MODULE, |
3ae5eaec | 2120 | }, |
1da177e4 LT |
2121 | }; |
2122 | ||
3ae5eaec | 2123 | static struct platform_driver mv643xx_eth_shared_driver = { |
1da177e4 LT |
2124 | .probe = mv643xx_eth_shared_probe, |
2125 | .remove = mv643xx_eth_shared_remove, | |
3ae5eaec RK |
2126 | .driver = { |
2127 | .name = MV643XX_ETH_SHARED_NAME, | |
72abb461 | 2128 | .owner = THIS_MODULE, |
3ae5eaec | 2129 | }, |
1da177e4 LT |
2130 | }; |
2131 | ||
2132 | /* | |
2133 | * mv643xx_init_module | |
2134 | * | |
2135 | * Registers the network drivers into the Linux kernel | |
2136 | * | |
2137 | * Input : N/A | |
2138 | * | |
2139 | * Output : N/A | |
2140 | */ | |
2141 | static int __init mv643xx_init_module(void) | |
2142 | { | |
2143 | int rc; | |
2144 | ||
3ae5eaec | 2145 | rc = platform_driver_register(&mv643xx_eth_shared_driver); |
1da177e4 | 2146 | if (!rc) { |
3ae5eaec | 2147 | rc = platform_driver_register(&mv643xx_eth_driver); |
1da177e4 | 2148 | if (rc) |
3ae5eaec | 2149 | platform_driver_unregister(&mv643xx_eth_shared_driver); |
1da177e4 LT |
2150 | } |
2151 | return rc; | |
2152 | } | |
2153 | ||
2154 | /* | |
2155 | * mv643xx_cleanup_module | |
2156 | * | |
2157 | * Registers the network drivers into the Linux kernel | |
2158 | * | |
2159 | * Input : N/A | |
2160 | * | |
2161 | * Output : N/A | |
2162 | */ | |
2163 | static void __exit mv643xx_cleanup_module(void) | |
2164 | { | |
3ae5eaec RK |
2165 | platform_driver_unregister(&mv643xx_eth_driver); |
2166 | platform_driver_unregister(&mv643xx_eth_shared_driver); | |
1da177e4 LT |
2167 | } |
2168 | ||
2169 | module_init(mv643xx_init_module); | |
2170 | module_exit(mv643xx_cleanup_module); | |
2171 | ||
2172 | MODULE_LICENSE("GPL"); | |
2173 | MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani" | |
2174 | " and Dale Farnsworth"); | |
2175 | MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); | |
72abb461 KS |
2176 | MODULE_ALIAS("platform:" MV643XX_ETH_NAME); |
2177 | MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME); | |
1da177e4 LT |
2178 | |
2179 | /* | |
2180 | * The second part is the low level driver of the gigE ethernet ports. | |
2181 | */ | |
2182 | ||
2183 | /* | |
2184 | * Marvell's Gigabit Ethernet controller low level driver | |
2185 | * | |
2186 | * DESCRIPTION: | |
2187 | * This file introduce low level API to Marvell's Gigabit Ethernet | |
2188 | * controller. This Gigabit Ethernet Controller driver API controls | |
2189 | * 1) Operations (i.e. port init, start, reset etc'). | |
2190 | * 2) Data flow (i.e. port send, receive etc'). | |
2191 | * Each Gigabit Ethernet port is controlled via | |
2192 | * struct mv643xx_private. | |
2193 | * This struct includes user configuration information as well as | |
2194 | * driver internal data needed for its operations. | |
2195 | * | |
2196 | * Supported Features: | |
2197 | * - This low level driver is OS independent. Allocating memory for | |
2198 | * the descriptor rings and buffers are not within the scope of | |
2199 | * this driver. | |
2200 | * - The user is free from Rx/Tx queue managing. | |
2201 | * - This low level driver introduce functionality API that enable | |
2202 | * the to operate Marvell's Gigabit Ethernet Controller in a | |
2203 | * convenient way. | |
2204 | * - Simple Gigabit Ethernet port operation API. | |
2205 | * - Simple Gigabit Ethernet port data flow API. | |
2206 | * - Data flow and operation API support per queue functionality. | |
2207 | * - Support cached descriptors for better performance. | |
2208 | * - Enable access to all four DRAM banks and internal SRAM memory | |
2209 | * spaces. | |
2210 | * - PHY access and control API. | |
2211 | * - Port control register configuration API. | |
2212 | * - Full control over Unicast and Multicast MAC configurations. | |
2213 | * | |
2214 | * Operation flow: | |
2215 | * | |
2216 | * Initialization phase | |
2217 | * This phase complete the initialization of the the | |
2218 | * mv643xx_private struct. | |
2219 | * User information regarding port configuration has to be set | |
2220 | * prior to calling the port initialization routine. | |
2221 | * | |
2222 | * In this phase any port Tx/Rx activity is halted, MIB counters | |
2223 | * are cleared, PHY address is set according to user parameter and | |
2224 | * access to DRAM and internal SRAM memory spaces. | |
2225 | * | |
2226 | * Driver ring initialization | |
2227 | * Allocating memory for the descriptor rings and buffers is not | |
2228 | * within the scope of this driver. Thus, the user is required to | |
2229 | * allocate memory for the descriptors ring and buffers. Those | |
2230 | * memory parameters are used by the Rx and Tx ring initialization | |
2231 | * routines in order to curve the descriptor linked list in a form | |
2232 | * of a ring. | |
2233 | * Note: Pay special attention to alignment issues when using | |
2234 | * cached descriptors/buffers. In this phase the driver store | |
2235 | * information in the mv643xx_private struct regarding each queue | |
2236 | * ring. | |
2237 | * | |
2238 | * Driver start | |
2239 | * This phase prepares the Ethernet port for Rx and Tx activity. | |
2240 | * It uses the information stored in the mv643xx_private struct to | |
2241 | * initialize the various port registers. | |
2242 | * | |
2243 | * Data flow: | |
2244 | * All packet references to/from the driver are done using | |
2245 | * struct pkt_info. | |
2246 | * This struct is a unified struct used with Rx and Tx operations. | |
2247 | * This way the user is not required to be familiar with neither | |
2248 | * Tx nor Rx descriptors structures. | |
2249 | * The driver's descriptors rings are management by indexes. | |
2250 | * Those indexes controls the ring resources and used to indicate | |
2251 | * a SW resource error: | |
2252 | * 'current' | |
2253 | * This index points to the current available resource for use. For | |
2254 | * example in Rx process this index will point to the descriptor | |
2255 | * that will be passed to the user upon calling the receive | |
2256 | * routine. In Tx process, this index will point to the descriptor | |
2257 | * that will be assigned with the user packet info and transmitted. | |
2258 | * 'used' | |
2259 | * This index points to the descriptor that need to restore its | |
2260 | * resources. For example in Rx process, using the Rx buffer return | |
2261 | * API will attach the buffer returned in packet info to the | |
2262 | * descriptor pointed by 'used'. In Tx process, using the Tx | |
2263 | * descriptor return will merely return the user packet info with | |
2264 | * the command status of the transmitted buffer pointed by the | |
2265 | * 'used' index. Nevertheless, it is essential to use this routine | |
2266 | * to update the 'used' index. | |
2267 | * 'first' | |
2268 | * This index supports Tx Scatter-Gather. It points to the first | |
2269 | * descriptor of a packet assembled of multiple buffers. For | |
2270 | * example when in middle of Such packet we have a Tx resource | |
2271 | * error the 'curr' index get the value of 'first' to indicate | |
2272 | * that the ring returned to its state before trying to transmit | |
2273 | * this packet. | |
2274 | * | |
2275 | * Receive operation: | |
2276 | * The eth_port_receive API set the packet information struct, | |
2277 | * passed by the caller, with received information from the | |
2278 | * 'current' SDMA descriptor. | |
2279 | * It is the user responsibility to return this resource back | |
2280 | * to the Rx descriptor ring to enable the reuse of this source. | |
2281 | * Return Rx resource is done using the eth_rx_return_buff API. | |
2282 | * | |
1da177e4 LT |
2283 | * Prior to calling the initialization routine eth_port_init() the user |
2284 | * must set the following fields under mv643xx_private struct: | |
2285 | * port_num User Ethernet port number. | |
1da177e4 LT |
2286 | * port_config User port configuration value. |
2287 | * port_config_extend User port config extend value. | |
2288 | * port_sdma_config User port SDMA config value. | |
2289 | * port_serial_control User port serial control value. | |
2290 | * | |
2291 | * This driver data flow is done using the struct pkt_info which | |
2292 | * is a unified struct for Rx and Tx operations: | |
2293 | * | |
2294 | * byte_cnt Tx/Rx descriptor buffer byte count. | |
2295 | * l4i_chk CPU provided TCP Checksum. For Tx operation | |
2296 | * only. | |
2297 | * cmd_sts Tx/Rx descriptor command status. | |
2298 | * buf_ptr Tx/Rx descriptor buffer pointer. | |
2299 | * return_info Tx/Rx user resource return information. | |
2300 | */ | |
2301 | ||
1da177e4 | 2302 | /* Ethernet Port routines */ |
afdb57a2 LB |
2303 | static void eth_port_set_filter_table_entry(struct mv643xx_private *mp, |
2304 | int table, unsigned char entry); | |
1da177e4 LT |
2305 | |
2306 | /* | |
2307 | * eth_port_init - Initialize the Ethernet port driver | |
2308 | * | |
2309 | * DESCRIPTION: | |
2310 | * This function prepares the ethernet port to start its activity: | |
2311 | * 1) Completes the ethernet port driver struct initialization toward port | |
2312 | * start routine. | |
2313 | * 2) Resets the device to a quiescent state in case of warm reboot. | |
2314 | * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM. | |
2315 | * 4) Clean MAC tables. The reset status of those tables is unknown. | |
2316 | * 5) Set PHY address. | |
2317 | * Note: Call this routine prior to eth_port_start routine and after | |
2318 | * setting user values in the user fields of Ethernet port control | |
2319 | * struct. | |
2320 | * | |
2321 | * INPUT: | |
2322 | * struct mv643xx_private *mp Ethernet port control struct | |
2323 | * | |
2324 | * OUTPUT: | |
2325 | * See description. | |
2326 | * | |
2327 | * RETURN: | |
2328 | * None. | |
2329 | */ | |
2330 | static void eth_port_init(struct mv643xx_private *mp) | |
2331 | { | |
1da177e4 | 2332 | mp->rx_resource_err = 0; |
1da177e4 | 2333 | |
afdb57a2 | 2334 | eth_port_reset(mp); |
1da177e4 | 2335 | |
afdb57a2 | 2336 | eth_port_init_mac_tables(mp); |
1da177e4 LT |
2337 | } |
2338 | ||
2339 | /* | |
2340 | * eth_port_start - Start the Ethernet port activity. | |
2341 | * | |
2342 | * DESCRIPTION: | |
2343 | * This routine prepares the Ethernet port for Rx and Tx activity: | |
2344 | * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that | |
2345 | * has been initialized a descriptor's ring (using | |
2346 | * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx) | |
2347 | * 2. Initialize and enable the Ethernet configuration port by writing to | |
2348 | * the port's configuration and command registers. | |
2349 | * 3. Initialize and enable the SDMA by writing to the SDMA's | |
2350 | * configuration and command registers. After completing these steps, | |
2351 | * the ethernet port SDMA can starts to perform Rx and Tx activities. | |
2352 | * | |
2353 | * Note: Each Rx and Tx queue descriptor's list must be initialized prior | |
2354 | * to calling this function (use ether_init_tx_desc_ring for Tx queues | |
2355 | * and ether_init_rx_desc_ring for Rx queues). | |
2356 | * | |
2357 | * INPUT: | |
ed9b5d45 | 2358 | * dev - a pointer to the required interface |
1da177e4 LT |
2359 | * |
2360 | * OUTPUT: | |
2361 | * Ethernet port is ready to receive and transmit. | |
2362 | * | |
2363 | * RETURN: | |
2364 | * None. | |
2365 | */ | |
ed9b5d45 | 2366 | static void eth_port_start(struct net_device *dev) |
1da177e4 | 2367 | { |
ed9b5d45 | 2368 | struct mv643xx_private *mp = netdev_priv(dev); |
1da177e4 LT |
2369 | unsigned int port_num = mp->port_num; |
2370 | int tx_curr_desc, rx_curr_desc; | |
d0412d96 JC |
2371 | u32 pscr; |
2372 | struct ethtool_cmd ethtool_cmd; | |
1da177e4 LT |
2373 | |
2374 | /* Assignment of Tx CTRP of given queue */ | |
2375 | tx_curr_desc = mp->tx_curr_desc_q; | |
ec69d651 | 2376 | wrl(mp, TX_CURRENT_QUEUE_DESC_PTR_0(port_num), |
1da177e4 LT |
2377 | (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc)); |
2378 | ||
2379 | /* Assignment of Rx CRDP of given queue */ | |
2380 | rx_curr_desc = mp->rx_curr_desc_q; | |
ec69d651 | 2381 | wrl(mp, RX_CURRENT_QUEUE_DESC_PTR_0(port_num), |
1da177e4 LT |
2382 | (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc)); |
2383 | ||
2384 | /* Add the assigned Ethernet address to the port's address table */ | |
afdb57a2 | 2385 | eth_port_uc_addr_set(mp, dev->dev_addr); |
1da177e4 LT |
2386 | |
2387 | /* Assign port configuration and command. */ | |
ec69d651 | 2388 | wrl(mp, PORT_CONFIG_REG(port_num), |
e4d00fa9 | 2389 | PORT_CONFIG_DEFAULT_VALUE); |
01999873 | 2390 | |
ec69d651 | 2391 | wrl(mp, PORT_CONFIG_EXTEND_REG(port_num), |
e4d00fa9 | 2392 | PORT_CONFIG_EXTEND_DEFAULT_VALUE); |
1da177e4 | 2393 | |
ec69d651 | 2394 | pscr = rdl(mp, PORT_SERIAL_CONTROL_REG(port_num)); |
01999873 | 2395 | |
e4d00fa9 | 2396 | pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS); |
ec69d651 | 2397 | wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), pscr); |
1da177e4 | 2398 | |
e4d00fa9 LB |
2399 | pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL | |
2400 | DISABLE_AUTO_NEG_SPEED_GMII | | |
2401 | DISABLE_AUTO_NEG_FOR_DUPLX | | |
2402 | DO_NOT_FORCE_LINK_FAIL | | |
2403 | SERIAL_PORT_CONTROL_RESERVED; | |
1da177e4 | 2404 | |
ec69d651 | 2405 | wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), pscr); |
1da177e4 | 2406 | |
e4d00fa9 | 2407 | pscr |= SERIAL_PORT_ENABLE; |
ec69d651 | 2408 | wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), pscr); |
1da177e4 LT |
2409 | |
2410 | /* Assign port SDMA configuration */ | |
ec69d651 | 2411 | wrl(mp, SDMA_CONFIG_REG(port_num), |
e4d00fa9 | 2412 | PORT_SDMA_CONFIG_DEFAULT_VALUE); |
1da177e4 LT |
2413 | |
2414 | /* Enable port Rx. */ | |
afdb57a2 | 2415 | mv643xx_eth_port_enable_rx(mp, ETH_RX_QUEUES_ENABLED); |
8f543718 DF |
2416 | |
2417 | /* Disable port bandwidth limits by clearing MTU register */ | |
ec69d651 | 2418 | wrl(mp, MAXIMUM_TRANSMIT_UNIT(port_num), 0); |
d0412d96 JC |
2419 | |
2420 | /* save phy settings across reset */ | |
2421 | mv643xx_get_settings(dev, ðtool_cmd); | |
afdb57a2 | 2422 | ethernet_phy_reset(mp); |
d0412d96 | 2423 | mv643xx_set_settings(dev, ðtool_cmd); |
1da177e4 LT |
2424 | } |
2425 | ||
2426 | /* | |
144213d7 | 2427 | * eth_port_uc_addr_set - Write a MAC address into the port's hw registers |
1da177e4 | 2428 | */ |
afdb57a2 LB |
2429 | static void eth_port_uc_addr_set(struct mv643xx_private *mp, |
2430 | unsigned char *p_addr) | |
1da177e4 | 2431 | { |
afdb57a2 | 2432 | unsigned int port_num = mp->port_num; |
1da177e4 LT |
2433 | unsigned int mac_h; |
2434 | unsigned int mac_l; | |
cf4086c7 | 2435 | int table; |
1da177e4 LT |
2436 | |
2437 | mac_l = (p_addr[4] << 8) | (p_addr[5]); | |
2438 | mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) | | |
2439 | (p_addr[3] << 0); | |
2440 | ||
ec69d651 LB |
2441 | wrl(mp, MAC_ADDR_LOW(port_num), mac_l); |
2442 | wrl(mp, MAC_ADDR_HIGH(port_num), mac_h); | |
1da177e4 | 2443 | |
144213d7 | 2444 | /* Accept frames with this address */ |
e4d00fa9 | 2445 | table = DA_FILTER_UNICAST_TABLE_BASE(port_num); |
afdb57a2 | 2446 | eth_port_set_filter_table_entry(mp, table, p_addr[5] & 0x0f); |
1da177e4 LT |
2447 | } |
2448 | ||
2449 | /* | |
144213d7 | 2450 | * eth_port_uc_addr_get - Read the MAC address from the port's hw registers |
1da177e4 | 2451 | */ |
afdb57a2 LB |
2452 | static void eth_port_uc_addr_get(struct mv643xx_private *mp, |
2453 | unsigned char *p_addr) | |
1da177e4 | 2454 | { |
afdb57a2 | 2455 | unsigned int port_num = mp->port_num; |
1da177e4 LT |
2456 | unsigned int mac_h; |
2457 | unsigned int mac_l; | |
2458 | ||
ec69d651 LB |
2459 | mac_h = rdl(mp, MAC_ADDR_HIGH(port_num)); |
2460 | mac_l = rdl(mp, MAC_ADDR_LOW(port_num)); | |
1da177e4 LT |
2461 | |
2462 | p_addr[0] = (mac_h >> 24) & 0xff; | |
2463 | p_addr[1] = (mac_h >> 16) & 0xff; | |
2464 | p_addr[2] = (mac_h >> 8) & 0xff; | |
2465 | p_addr[3] = mac_h & 0xff; | |
2466 | p_addr[4] = (mac_l >> 8) & 0xff; | |
2467 | p_addr[5] = mac_l & 0xff; | |
2468 | } | |
2469 | ||
16e03018 DF |
2470 | /* |
2471 | * The entries in each table are indexed by a hash of a packet's MAC | |
2472 | * address. One bit in each entry determines whether the packet is | |
2473 | * accepted. There are 4 entries (each 8 bits wide) in each register | |
2474 | * of the table. The bits in each entry are defined as follows: | |
2475 | * 0 Accept=1, Drop=0 | |
2476 | * 3-1 Queue (ETH_Q0=0) | |
2477 | * 7-4 Reserved = 0; | |
2478 | */ | |
afdb57a2 LB |
2479 | static void eth_port_set_filter_table_entry(struct mv643xx_private *mp, |
2480 | int table, unsigned char entry) | |
16e03018 DF |
2481 | { |
2482 | unsigned int table_reg; | |
2483 | unsigned int tbl_offset; | |
2484 | unsigned int reg_offset; | |
2485 | ||
2486 | tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */ | |
2487 | reg_offset = entry % 4; /* Entry offset within the register */ | |
2488 | ||
2489 | /* Set "accepts frame bit" at specified table entry */ | |
ec69d651 | 2490 | table_reg = rdl(mp, table + tbl_offset); |
16e03018 | 2491 | table_reg |= 0x01 << (8 * reg_offset); |
ec69d651 | 2492 | wrl(mp, table + tbl_offset, table_reg); |
16e03018 DF |
2493 | } |
2494 | ||
2495 | /* | |
2496 | * eth_port_mc_addr - Multicast address settings. | |
2497 | * | |
2498 | * The MV device supports multicast using two tables: | |
2499 | * 1) Special Multicast Table for MAC addresses of the form | |
2500 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF). | |
2501 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast | |
2502 | * Table entries in the DA-Filter table. | |
2503 | * 2) Other Multicast Table for multicast of another type. A CRC-8bit | |
2504 | * is used as an index to the Other Multicast Table entries in the | |
2505 | * DA-Filter table. This function calculates the CRC-8bit value. | |
2506 | * In either case, eth_port_set_filter_table_entry() is then called | |
2507 | * to set to set the actual table entry. | |
2508 | */ | |
afdb57a2 | 2509 | static void eth_port_mc_addr(struct mv643xx_private *mp, unsigned char *p_addr) |
16e03018 | 2510 | { |
afdb57a2 | 2511 | unsigned int port_num = mp->port_num; |
16e03018 DF |
2512 | unsigned int mac_h; |
2513 | unsigned int mac_l; | |
2514 | unsigned char crc_result = 0; | |
2515 | int table; | |
2516 | int mac_array[48]; | |
2517 | int crc[8]; | |
2518 | int i; | |
2519 | ||
2520 | if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) && | |
2521 | (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) { | |
afdb57a2 LB |
2522 | table = DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port_num); |
2523 | eth_port_set_filter_table_entry(mp, table, p_addr[5]); | |
16e03018 DF |
2524 | return; |
2525 | } | |
2526 | ||
2527 | /* Calculate CRC-8 out of the given address */ | |
2528 | mac_h = (p_addr[0] << 8) | (p_addr[1]); | |
2529 | mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) | | |
2530 | (p_addr[4] << 8) | (p_addr[5] << 0); | |
2531 | ||
2532 | for (i = 0; i < 32; i++) | |
2533 | mac_array[i] = (mac_l >> i) & 0x1; | |
2534 | for (i = 32; i < 48; i++) | |
2535 | mac_array[i] = (mac_h >> (i - 32)) & 0x1; | |
2536 | ||
2537 | crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^ | |
2538 | mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^ | |
2539 | mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^ | |
2540 | mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^ | |
2541 | mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0]; | |
2542 | ||
2543 | crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^ | |
2544 | mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^ | |
2545 | mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^ | |
2546 | mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^ | |
2547 | mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^ | |
2548 | mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^ | |
2549 | mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0]; | |
2550 | ||
2551 | crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^ | |
2552 | mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^ | |
2553 | mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^ | |
2554 | mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^ | |
2555 | mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ | |
2556 | mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0]; | |
2557 | ||
2558 | crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^ | |
2559 | mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^ | |
2560 | mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^ | |
2561 | mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ | |
2562 | mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^ | |
2563 | mac_array[3] ^ mac_array[2] ^ mac_array[1]; | |
2564 | ||
2565 | crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^ | |
2566 | mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^ | |
2567 | mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^ | |
2568 | mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^ | |
2569 | mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^ | |
2570 | mac_array[3] ^ mac_array[2]; | |
2571 | ||
2572 | crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^ | |
2573 | mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^ | |
2574 | mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^ | |
2575 | mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^ | |
2576 | mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^ | |
2577 | mac_array[4] ^ mac_array[3]; | |
2578 | ||
2579 | crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^ | |
2580 | mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^ | |
2581 | mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^ | |
2582 | mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^ | |
2583 | mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^ | |
2584 | mac_array[4]; | |
2585 | ||
2586 | crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^ | |
2587 | mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^ | |
2588 | mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^ | |
2589 | mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^ | |
2590 | mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5]; | |
2591 | ||
2592 | for (i = 0; i < 8; i++) | |
2593 | crc_result = crc_result | (crc[i] << i); | |
2594 | ||
afdb57a2 LB |
2595 | table = DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port_num); |
2596 | eth_port_set_filter_table_entry(mp, table, crc_result); | |
16e03018 DF |
2597 | } |
2598 | ||
2599 | /* | |
2600 | * Set the entire multicast list based on dev->mc_list. | |
2601 | */ | |
2602 | static void eth_port_set_multicast_list(struct net_device *dev) | |
2603 | { | |
2604 | ||
2605 | struct dev_mc_list *mc_list; | |
2606 | int i; | |
2607 | int table_index; | |
2608 | struct mv643xx_private *mp = netdev_priv(dev); | |
2609 | unsigned int eth_port_num = mp->port_num; | |
2610 | ||
2611 | /* If the device is in promiscuous mode or in all multicast mode, | |
2612 | * we will fully populate both multicast tables with accept. | |
2613 | * This is guaranteed to yield a match on all multicast addresses... | |
2614 | */ | |
2615 | if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) { | |
2616 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { | |
b4de9051 DF |
2617 | /* Set all entries in DA filter special multicast |
2618 | * table (Ex_dFSMT) | |
2619 | * Set for ETH_Q0 for now | |
2620 | * Bits | |
2621 | * 0 Accept=1, Drop=0 | |
2622 | * 3-1 Queue ETH_Q0=0 | |
2623 | * 7-4 Reserved = 0; | |
2624 | */ | |
ec69d651 | 2625 | wrl(mp, DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101); |
b4de9051 DF |
2626 | |
2627 | /* Set all entries in DA filter other multicast | |
2628 | * table (Ex_dFOMT) | |
2629 | * Set for ETH_Q0 for now | |
2630 | * Bits | |
2631 | * 0 Accept=1, Drop=0 | |
2632 | * 3-1 Queue ETH_Q0=0 | |
2633 | * 7-4 Reserved = 0; | |
2634 | */ | |
ec69d651 | 2635 | wrl(mp, DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101); |
b4de9051 | 2636 | } |
16e03018 DF |
2637 | return; |
2638 | } | |
2639 | ||
2640 | /* We will clear out multicast tables every time we get the list. | |
2641 | * Then add the entire new list... | |
2642 | */ | |
2643 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { | |
2644 | /* Clear DA filter special multicast table (Ex_dFSMT) */ | |
ec69d651 | 2645 | wrl(mp, DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE |
16e03018 DF |
2646 | (eth_port_num) + table_index, 0); |
2647 | ||
2648 | /* Clear DA filter other multicast table (Ex_dFOMT) */ | |
ec69d651 | 2649 | wrl(mp, DA_FILTER_OTHER_MULTICAST_TABLE_BASE |
16e03018 DF |
2650 | (eth_port_num) + table_index, 0); |
2651 | } | |
2652 | ||
2653 | /* Get pointer to net_device multicast list and add each one... */ | |
2654 | for (i = 0, mc_list = dev->mc_list; | |
2655 | (i < 256) && (mc_list != NULL) && (i < dev->mc_count); | |
2656 | i++, mc_list = mc_list->next) | |
2657 | if (mc_list->dmi_addrlen == 6) | |
afdb57a2 | 2658 | eth_port_mc_addr(mp, mc_list->dmi_addr); |
16e03018 DF |
2659 | } |
2660 | ||
1da177e4 LT |
2661 | /* |
2662 | * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables | |
2663 | * | |
2664 | * DESCRIPTION: | |
2665 | * Go through all the DA filter tables (Unicast, Special Multicast & | |
2666 | * Other Multicast) and set each entry to 0. | |
2667 | * | |
2668 | * INPUT: | |
afdb57a2 | 2669 | * struct mv643xx_private *mp Ethernet Port. |
1da177e4 LT |
2670 | * |
2671 | * OUTPUT: | |
2672 | * Multicast and Unicast packets are rejected. | |
2673 | * | |
2674 | * RETURN: | |
2675 | * None. | |
2676 | */ | |
afdb57a2 | 2677 | static void eth_port_init_mac_tables(struct mv643xx_private *mp) |
1da177e4 | 2678 | { |
afdb57a2 | 2679 | unsigned int port_num = mp->port_num; |
1da177e4 LT |
2680 | int table_index; |
2681 | ||
2682 | /* Clear DA filter unicast table (Ex_dFUT) */ | |
2683 | for (table_index = 0; table_index <= 0xC; table_index += 4) | |
ec69d651 | 2684 | wrl(mp, DA_FILTER_UNICAST_TABLE_BASE(port_num) + |
afdb57a2 | 2685 | table_index, 0); |
1da177e4 LT |
2686 | |
2687 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { | |
2688 | /* Clear DA filter special multicast table (Ex_dFSMT) */ | |
ec69d651 | 2689 | wrl(mp, DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port_num) + |
afdb57a2 | 2690 | table_index, 0); |
1da177e4 | 2691 | /* Clear DA filter other multicast table (Ex_dFOMT) */ |
ec69d651 | 2692 | wrl(mp, DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port_num) + |
afdb57a2 | 2693 | table_index, 0); |
1da177e4 LT |
2694 | } |
2695 | } | |
2696 | ||
2697 | /* | |
2698 | * eth_clear_mib_counters - Clear all MIB counters | |
2699 | * | |
2700 | * DESCRIPTION: | |
2701 | * This function clears all MIB counters of a specific ethernet port. | |
2702 | * A read from the MIB counter will reset the counter. | |
2703 | * | |
2704 | * INPUT: | |
afdb57a2 | 2705 | * struct mv643xx_private *mp Ethernet Port. |
1da177e4 LT |
2706 | * |
2707 | * OUTPUT: | |
2708 | * After reading all MIB counters, the counters resets. | |
2709 | * | |
2710 | * RETURN: | |
2711 | * MIB counter value. | |
2712 | * | |
2713 | */ | |
afdb57a2 | 2714 | static void eth_clear_mib_counters(struct mv643xx_private *mp) |
1da177e4 | 2715 | { |
afdb57a2 | 2716 | unsigned int port_num = mp->port_num; |
1da177e4 LT |
2717 | int i; |
2718 | ||
2719 | /* Perform dummy reads from MIB counters */ | |
2720 | for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; | |
2721 | i += 4) | |
ec69d651 | 2722 | rdl(mp, MIB_COUNTERS_BASE(port_num) + i); |
1da177e4 LT |
2723 | } |
2724 | ||
2725 | static inline u32 read_mib(struct mv643xx_private *mp, int offset) | |
2726 | { | |
ec69d651 | 2727 | return rdl(mp, MIB_COUNTERS_BASE(mp->port_num) + offset); |
1da177e4 LT |
2728 | } |
2729 | ||
2730 | static void eth_update_mib_counters(struct mv643xx_private *mp) | |
2731 | { | |
2732 | struct mv643xx_mib_counters *p = &mp->mib_counters; | |
2733 | int offset; | |
2734 | ||
2735 | p->good_octets_received += | |
2736 | read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW); | |
2737 | p->good_octets_received += | |
2738 | (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32; | |
2739 | ||
2740 | for (offset = ETH_MIB_BAD_OCTETS_RECEIVED; | |
2741 | offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS; | |
2742 | offset += 4) | |
70fbf327 | 2743 | *(u32 *)((char *)p + offset) += read_mib(mp, offset); |
1da177e4 LT |
2744 | |
2745 | p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW); | |
2746 | p->good_octets_sent += | |
2747 | (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32; | |
2748 | ||
2749 | for (offset = ETH_MIB_GOOD_FRAMES_SENT; | |
2750 | offset <= ETH_MIB_LATE_COLLISION; | |
2751 | offset += 4) | |
70fbf327 | 2752 | *(u32 *)((char *)p + offset) += read_mib(mp, offset); |
1da177e4 LT |
2753 | } |
2754 | ||
2755 | /* | |
2756 | * ethernet_phy_detect - Detect whether a phy is present | |
2757 | * | |
2758 | * DESCRIPTION: | |
2759 | * This function tests whether there is a PHY present on | |
2760 | * the specified port. | |
2761 | * | |
2762 | * INPUT: | |
afdb57a2 | 2763 | * struct mv643xx_private *mp Ethernet Port. |
1da177e4 LT |
2764 | * |
2765 | * OUTPUT: | |
2766 | * None | |
2767 | * | |
2768 | * RETURN: | |
2769 | * 0 on success | |
2770 | * -ENODEV on failure | |
2771 | * | |
2772 | */ | |
afdb57a2 | 2773 | static int ethernet_phy_detect(struct mv643xx_private *mp) |
1da177e4 LT |
2774 | { |
2775 | unsigned int phy_reg_data0; | |
2776 | int auto_neg; | |
2777 | ||
afdb57a2 | 2778 | eth_port_read_smi_reg(mp, 0, &phy_reg_data0); |
1da177e4 LT |
2779 | auto_neg = phy_reg_data0 & 0x1000; |
2780 | phy_reg_data0 ^= 0x1000; /* invert auto_neg */ | |
afdb57a2 | 2781 | eth_port_write_smi_reg(mp, 0, phy_reg_data0); |
1da177e4 | 2782 | |
afdb57a2 | 2783 | eth_port_read_smi_reg(mp, 0, &phy_reg_data0); |
1da177e4 LT |
2784 | if ((phy_reg_data0 & 0x1000) == auto_neg) |
2785 | return -ENODEV; /* change didn't take */ | |
2786 | ||
2787 | phy_reg_data0 ^= 0x1000; | |
afdb57a2 | 2788 | eth_port_write_smi_reg(mp, 0, phy_reg_data0); |
1da177e4 LT |
2789 | return 0; |
2790 | } | |
2791 | ||
2792 | /* | |
2793 | * ethernet_phy_get - Get the ethernet port PHY address. | |
2794 | * | |
2795 | * DESCRIPTION: | |
2796 | * This routine returns the given ethernet port PHY address. | |
2797 | * | |
2798 | * INPUT: | |
afdb57a2 | 2799 | * struct mv643xx_private *mp Ethernet Port. |
1da177e4 LT |
2800 | * |
2801 | * OUTPUT: | |
2802 | * None. | |
2803 | * | |
2804 | * RETURN: | |
2805 | * PHY address. | |
2806 | * | |
2807 | */ | |
afdb57a2 | 2808 | static int ethernet_phy_get(struct mv643xx_private *mp) |
1da177e4 LT |
2809 | { |
2810 | unsigned int reg_data; | |
2811 | ||
ec69d651 | 2812 | reg_data = rdl(mp, PHY_ADDR_REG); |
1da177e4 | 2813 | |
afdb57a2 | 2814 | return ((reg_data >> (5 * mp->port_num)) & 0x1f); |
1da177e4 LT |
2815 | } |
2816 | ||
2817 | /* | |
2818 | * ethernet_phy_set - Set the ethernet port PHY address. | |
2819 | * | |
2820 | * DESCRIPTION: | |
2821 | * This routine sets the given ethernet port PHY address. | |
2822 | * | |
2823 | * INPUT: | |
afdb57a2 | 2824 | * struct mv643xx_private *mp Ethernet Port. |
1da177e4 LT |
2825 | * int phy_addr PHY address. |
2826 | * | |
2827 | * OUTPUT: | |
2828 | * None. | |
2829 | * | |
2830 | * RETURN: | |
2831 | * None. | |
2832 | * | |
2833 | */ | |
afdb57a2 | 2834 | static void ethernet_phy_set(struct mv643xx_private *mp, int phy_addr) |
1da177e4 LT |
2835 | { |
2836 | u32 reg_data; | |
afdb57a2 | 2837 | int addr_shift = 5 * mp->port_num; |
1da177e4 | 2838 | |
ec69d651 | 2839 | reg_data = rdl(mp, PHY_ADDR_REG); |
1da177e4 LT |
2840 | reg_data &= ~(0x1f << addr_shift); |
2841 | reg_data |= (phy_addr & 0x1f) << addr_shift; | |
ec69d651 | 2842 | wrl(mp, PHY_ADDR_REG, reg_data); |
1da177e4 LT |
2843 | } |
2844 | ||
2845 | /* | |
2846 | * ethernet_phy_reset - Reset Ethernet port PHY. | |
2847 | * | |
2848 | * DESCRIPTION: | |
2849 | * This routine utilizes the SMI interface to reset the ethernet port PHY. | |
2850 | * | |
2851 | * INPUT: | |
afdb57a2 | 2852 | * struct mv643xx_private *mp Ethernet Port. |
1da177e4 LT |
2853 | * |
2854 | * OUTPUT: | |
2855 | * The PHY is reset. | |
2856 | * | |
2857 | * RETURN: | |
2858 | * None. | |
2859 | * | |
2860 | */ | |
afdb57a2 | 2861 | static void ethernet_phy_reset(struct mv643xx_private *mp) |
1da177e4 LT |
2862 | { |
2863 | unsigned int phy_reg_data; | |
2864 | ||
2865 | /* Reset the PHY */ | |
afdb57a2 | 2866 | eth_port_read_smi_reg(mp, 0, &phy_reg_data); |
1da177e4 | 2867 | phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */ |
afdb57a2 | 2868 | eth_port_write_smi_reg(mp, 0, phy_reg_data); |
d0412d96 JC |
2869 | |
2870 | /* wait for PHY to come out of reset */ | |
2871 | do { | |
2872 | udelay(1); | |
afdb57a2 | 2873 | eth_port_read_smi_reg(mp, 0, &phy_reg_data); |
d0412d96 | 2874 | } while (phy_reg_data & 0x8000); |
1da177e4 LT |
2875 | } |
2876 | ||
afdb57a2 | 2877 | static void mv643xx_eth_port_enable_tx(struct mv643xx_private *mp, |
12a87c64 | 2878 | unsigned int queues) |
9f8dd319 | 2879 | { |
ec69d651 | 2880 | wrl(mp, TRANSMIT_QUEUE_COMMAND_REG(mp->port_num), queues); |
9f8dd319 DF |
2881 | } |
2882 | ||
afdb57a2 | 2883 | static void mv643xx_eth_port_enable_rx(struct mv643xx_private *mp, |
12a87c64 | 2884 | unsigned int queues) |
9f8dd319 | 2885 | { |
ec69d651 | 2886 | wrl(mp, RECEIVE_QUEUE_COMMAND_REG(mp->port_num), queues); |
9f8dd319 DF |
2887 | } |
2888 | ||
afdb57a2 | 2889 | static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_private *mp) |
9f8dd319 | 2890 | { |
afdb57a2 | 2891 | unsigned int port_num = mp->port_num; |
12a87c64 | 2892 | u32 queues; |
9f8dd319 DF |
2893 | |
2894 | /* Stop Tx port activity. Check port Tx activity. */ | |
ec69d651 | 2895 | queues = rdl(mp, TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF; |
12a87c64 DF |
2896 | if (queues) { |
2897 | /* Issue stop command for active queues only */ | |
ec69d651 | 2898 | wrl(mp, TRANSMIT_QUEUE_COMMAND_REG(port_num), (queues << 8)); |
9f8dd319 DF |
2899 | |
2900 | /* Wait for all Tx activity to terminate. */ | |
2901 | /* Check port cause register that all Tx queues are stopped */ | |
ec69d651 | 2902 | while (rdl(mp, TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF) |
9f8dd319 DF |
2903 | udelay(PHY_WAIT_MICRO_SECONDS); |
2904 | ||
2905 | /* Wait for Tx FIFO to empty */ | |
ec69d651 | 2906 | while (rdl(mp, PORT_STATUS_REG(port_num)) & |
9f8dd319 DF |
2907 | ETH_PORT_TX_FIFO_EMPTY) |
2908 | udelay(PHY_WAIT_MICRO_SECONDS); | |
2909 | } | |
2910 | ||
12a87c64 | 2911 | return queues; |
9f8dd319 DF |
2912 | } |
2913 | ||
afdb57a2 | 2914 | static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_private *mp) |
9f8dd319 | 2915 | { |
afdb57a2 | 2916 | unsigned int port_num = mp->port_num; |
12a87c64 | 2917 | u32 queues; |
9f8dd319 DF |
2918 | |
2919 | /* Stop Rx port activity. Check port Rx activity. */ | |
ec69d651 | 2920 | queues = rdl(mp, RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF; |
12a87c64 DF |
2921 | if (queues) { |
2922 | /* Issue stop command for active queues only */ | |
ec69d651 | 2923 | wrl(mp, RECEIVE_QUEUE_COMMAND_REG(port_num), (queues << 8)); |
9f8dd319 DF |
2924 | |
2925 | /* Wait for all Rx activity to terminate. */ | |
2926 | /* Check port cause register that all Rx queues are stopped */ | |
ec69d651 | 2927 | while (rdl(mp, RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF) |
9f8dd319 DF |
2928 | udelay(PHY_WAIT_MICRO_SECONDS); |
2929 | } | |
2930 | ||
12a87c64 | 2931 | return queues; |
9f8dd319 DF |
2932 | } |
2933 | ||
1da177e4 LT |
2934 | /* |
2935 | * eth_port_reset - Reset Ethernet port | |
2936 | * | |
2937 | * DESCRIPTION: | |
2938 | * This routine resets the chip by aborting any SDMA engine activity and | |
2939 | * clearing the MIB counters. The Receiver and the Transmit unit are in | |
2940 | * idle state after this command is performed and the port is disabled. | |
2941 | * | |
2942 | * INPUT: | |
afdb57a2 | 2943 | * struct mv643xx_private *mp Ethernet Port. |
1da177e4 LT |
2944 | * |
2945 | * OUTPUT: | |
2946 | * Channel activity is halted. | |
2947 | * | |
2948 | * RETURN: | |
2949 | * None. | |
2950 | * | |
2951 | */ | |
afdb57a2 | 2952 | static void eth_port_reset(struct mv643xx_private *mp) |
1da177e4 | 2953 | { |
afdb57a2 | 2954 | unsigned int port_num = mp->port_num; |
1da177e4 LT |
2955 | unsigned int reg_data; |
2956 | ||
afdb57a2 LB |
2957 | mv643xx_eth_port_disable_tx(mp); |
2958 | mv643xx_eth_port_disable_rx(mp); | |
1da177e4 LT |
2959 | |
2960 | /* Clear all MIB counters */ | |
afdb57a2 | 2961 | eth_clear_mib_counters(mp); |
1da177e4 LT |
2962 | |
2963 | /* Reset the Enable bit in the Configuration Register */ | |
ec69d651 | 2964 | reg_data = rdl(mp, PORT_SERIAL_CONTROL_REG(port_num)); |
e4d00fa9 LB |
2965 | reg_data &= ~(SERIAL_PORT_ENABLE | |
2966 | DO_NOT_FORCE_LINK_FAIL | | |
2967 | FORCE_LINK_PASS); | |
ec69d651 | 2968 | wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), reg_data); |
1da177e4 LT |
2969 | } |
2970 | ||
1da177e4 | 2971 | |
1da177e4 LT |
2972 | /* |
2973 | * eth_port_read_smi_reg - Read PHY registers | |
2974 | * | |
2975 | * DESCRIPTION: | |
2976 | * This routine utilize the SMI interface to interact with the PHY in | |
2977 | * order to perform PHY register read. | |
2978 | * | |
2979 | * INPUT: | |
afdb57a2 | 2980 | * struct mv643xx_private *mp Ethernet Port. |
1da177e4 LT |
2981 | * unsigned int phy_reg PHY register address offset. |
2982 | * unsigned int *value Register value buffer. | |
2983 | * | |
2984 | * OUTPUT: | |
2985 | * Write the value of a specified PHY register into given buffer. | |
2986 | * | |
2987 | * RETURN: | |
2988 | * false if the PHY is busy or read data is not in valid state. | |
2989 | * true otherwise. | |
2990 | * | |
2991 | */ | |
afdb57a2 | 2992 | static void eth_port_read_smi_reg(struct mv643xx_private *mp, |
1da177e4 LT |
2993 | unsigned int phy_reg, unsigned int *value) |
2994 | { | |
ce4e2e45 | 2995 | void __iomem *smi_reg = mp->shared_smi->eth_base + SMI_REG; |
afdb57a2 | 2996 | int phy_addr = ethernet_phy_get(mp); |
1da177e4 LT |
2997 | unsigned long flags; |
2998 | int i; | |
2999 | ||
3000 | /* the SMI register is a shared resource */ | |
ce4e2e45 | 3001 | spin_lock_irqsave(&mp->shared_smi->phy_lock, flags); |
1da177e4 LT |
3002 | |
3003 | /* wait for the SMI register to become available */ | |
ce4e2e45 | 3004 | for (i = 0; readl(smi_reg) & ETH_SMI_BUSY; i++) { |
1da177e4 | 3005 | if (i == PHY_WAIT_ITERATIONS) { |
c1b35a28 | 3006 | printk("%s: PHY busy timeout\n", mp->dev->name); |
1da177e4 LT |
3007 | goto out; |
3008 | } | |
3009 | udelay(PHY_WAIT_MICRO_SECONDS); | |
3010 | } | |
3011 | ||
ce4e2e45 LB |
3012 | writel((phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ, |
3013 | smi_reg); | |
1da177e4 LT |
3014 | |
3015 | /* now wait for the data to be valid */ | |
ce4e2e45 | 3016 | for (i = 0; !(readl(smi_reg) & ETH_SMI_READ_VALID); i++) { |
1da177e4 | 3017 | if (i == PHY_WAIT_ITERATIONS) { |
c1b35a28 | 3018 | printk("%s: PHY read timeout\n", mp->dev->name); |
1da177e4 LT |
3019 | goto out; |
3020 | } | |
3021 | udelay(PHY_WAIT_MICRO_SECONDS); | |
3022 | } | |
3023 | ||
ce4e2e45 | 3024 | *value = readl(smi_reg) & 0xffff; |
1da177e4 | 3025 | out: |
ce4e2e45 | 3026 | spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags); |
1da177e4 LT |
3027 | } |
3028 | ||
3029 | /* | |
3030 | * eth_port_write_smi_reg - Write to PHY registers | |
3031 | * | |
3032 | * DESCRIPTION: | |
3033 | * This routine utilize the SMI interface to interact with the PHY in | |
3034 | * order to perform writes to PHY registers. | |
3035 | * | |
3036 | * INPUT: | |
afdb57a2 | 3037 | * struct mv643xx_private *mp Ethernet Port. |
1da177e4 LT |
3038 | * unsigned int phy_reg PHY register address offset. |
3039 | * unsigned int value Register value. | |
3040 | * | |
3041 | * OUTPUT: | |
3042 | * Write the given value to the specified PHY register. | |
3043 | * | |
3044 | * RETURN: | |
3045 | * false if the PHY is busy. | |
3046 | * true otherwise. | |
3047 | * | |
3048 | */ | |
afdb57a2 | 3049 | static void eth_port_write_smi_reg(struct mv643xx_private *mp, |
1da177e4 LT |
3050 | unsigned int phy_reg, unsigned int value) |
3051 | { | |
ce4e2e45 LB |
3052 | void __iomem *smi_reg = mp->shared_smi->eth_base + SMI_REG; |
3053 | int phy_addr = ethernet_phy_get(mp); | |
1da177e4 | 3054 | unsigned long flags; |
ce4e2e45 | 3055 | int i; |
1da177e4 LT |
3056 | |
3057 | /* the SMI register is a shared resource */ | |
ce4e2e45 | 3058 | spin_lock_irqsave(&mp->shared_smi->phy_lock, flags); |
1da177e4 LT |
3059 | |
3060 | /* wait for the SMI register to become available */ | |
ce4e2e45 | 3061 | for (i = 0; readl(smi_reg) & ETH_SMI_BUSY; i++) { |
1da177e4 | 3062 | if (i == PHY_WAIT_ITERATIONS) { |
c1b35a28 | 3063 | printk("%s: PHY busy timeout\n", mp->dev->name); |
1da177e4 LT |
3064 | goto out; |
3065 | } | |
3066 | udelay(PHY_WAIT_MICRO_SECONDS); | |
3067 | } | |
3068 | ||
ce4e2e45 LB |
3069 | writel((phy_addr << 16) | (phy_reg << 21) | |
3070 | ETH_SMI_OPCODE_WRITE | (value & 0xffff), smi_reg); | |
1da177e4 | 3071 | out: |
ce4e2e45 | 3072 | spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags); |
1da177e4 LT |
3073 | } |
3074 | ||
c28a4f89 JC |
3075 | /* |
3076 | * Wrappers for MII support library. | |
3077 | */ | |
3078 | static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location) | |
3079 | { | |
c28a4f89 | 3080 | struct mv643xx_private *mp = netdev_priv(dev); |
afdb57a2 | 3081 | int val; |
c28a4f89 | 3082 | |
afdb57a2 | 3083 | eth_port_read_smi_reg(mp, location, &val); |
c28a4f89 JC |
3084 | return val; |
3085 | } | |
3086 | ||
3087 | static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val) | |
3088 | { | |
3089 | struct mv643xx_private *mp = netdev_priv(dev); | |
afdb57a2 | 3090 | eth_port_write_smi_reg(mp, location, val); |
c28a4f89 JC |
3091 | } |
3092 | ||
1da177e4 LT |
3093 | /* |
3094 | * eth_port_receive - Get received information from Rx ring. | |
3095 | * | |
3096 | * DESCRIPTION: | |
3097 | * This routine returns the received data to the caller. There is no | |
3098 | * data copying during routine operation. All information is returned | |
3099 | * using pointer to packet information struct passed from the caller. | |
3100 | * If the routine exhausts Rx ring resources then the resource error flag | |
3101 | * is set. | |
3102 | * | |
3103 | * INPUT: | |
3104 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
3105 | * struct pkt_info *p_pkt_info User packet buffer. | |
3106 | * | |
3107 | * OUTPUT: | |
3108 | * Rx ring current and used indexes are updated. | |
3109 | * | |
3110 | * RETURN: | |
3111 | * ETH_ERROR in case the routine can not access Rx desc ring. | |
3112 | * ETH_QUEUE_FULL if Rx ring resources are exhausted. | |
3113 | * ETH_END_OF_JOB if there is no received data. | |
3114 | * ETH_OK otherwise. | |
3115 | */ | |
3116 | static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp, | |
3117 | struct pkt_info *p_pkt_info) | |
3118 | { | |
3119 | int rx_next_curr_desc, rx_curr_desc, rx_used_desc; | |
3120 | volatile struct eth_rx_desc *p_rx_desc; | |
3121 | unsigned int command_status; | |
8f518703 | 3122 | unsigned long flags; |
1da177e4 LT |
3123 | |
3124 | /* Do not process Rx ring in case of Rx ring resource error */ | |
3125 | if (mp->rx_resource_err) | |
3126 | return ETH_QUEUE_FULL; | |
3127 | ||
8f518703 DF |
3128 | spin_lock_irqsave(&mp->lock, flags); |
3129 | ||
1da177e4 LT |
3130 | /* Get the Rx Desc ring 'curr and 'used' indexes */ |
3131 | rx_curr_desc = mp->rx_curr_desc_q; | |
3132 | rx_used_desc = mp->rx_used_desc_q; | |
3133 | ||
3134 | p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc]; | |
3135 | ||
3136 | /* The following parameters are used to save readings from memory */ | |
3137 | command_status = p_rx_desc->cmd_sts; | |
3138 | rmb(); | |
3139 | ||
3140 | /* Nothing to receive... */ | |
8f518703 DF |
3141 | if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { |
3142 | spin_unlock_irqrestore(&mp->lock, flags); | |
1da177e4 | 3143 | return ETH_END_OF_JOB; |
8f518703 | 3144 | } |
1da177e4 LT |
3145 | |
3146 | p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET; | |
3147 | p_pkt_info->cmd_sts = command_status; | |
3148 | p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET; | |
3149 | p_pkt_info->return_info = mp->rx_skb[rx_curr_desc]; | |
3150 | p_pkt_info->l4i_chk = p_rx_desc->buf_size; | |
3151 | ||
b4de9051 DF |
3152 | /* |
3153 | * Clean the return info field to indicate that the | |
3154 | * packet has been moved to the upper layers | |
3155 | */ | |
1da177e4 LT |
3156 | mp->rx_skb[rx_curr_desc] = NULL; |
3157 | ||
3158 | /* Update current index in data structure */ | |
3159 | rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size; | |
3160 | mp->rx_curr_desc_q = rx_next_curr_desc; | |
3161 | ||
3162 | /* Rx descriptors exhausted. Set the Rx ring resource error flag */ | |
3163 | if (rx_next_curr_desc == rx_used_desc) | |
3164 | mp->rx_resource_err = 1; | |
3165 | ||
8f518703 DF |
3166 | spin_unlock_irqrestore(&mp->lock, flags); |
3167 | ||
1da177e4 LT |
3168 | return ETH_OK; |
3169 | } | |
3170 | ||
3171 | /* | |
3172 | * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring. | |
3173 | * | |
3174 | * DESCRIPTION: | |
3175 | * This routine returns a Rx buffer back to the Rx ring. It retrieves the | |
3176 | * next 'used' descriptor and attached the returned buffer to it. | |
3177 | * In case the Rx ring was in "resource error" condition, where there are | |
3178 | * no available Rx resources, the function resets the resource error flag. | |
3179 | * | |
3180 | * INPUT: | |
3181 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
3182 | * struct pkt_info *p_pkt_info Information on returned buffer. | |
3183 | * | |
3184 | * OUTPUT: | |
3185 | * New available Rx resource in Rx descriptor ring. | |
3186 | * | |
3187 | * RETURN: | |
3188 | * ETH_ERROR in case the routine can not access Rx desc ring. | |
3189 | * ETH_OK otherwise. | |
3190 | */ | |
3191 | static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp, | |
3192 | struct pkt_info *p_pkt_info) | |
3193 | { | |
3194 | int used_rx_desc; /* Where to return Rx resource */ | |
3195 | volatile struct eth_rx_desc *p_used_rx_desc; | |
8f518703 DF |
3196 | unsigned long flags; |
3197 | ||
3198 | spin_lock_irqsave(&mp->lock, flags); | |
1da177e4 LT |
3199 | |
3200 | /* Get 'used' Rx descriptor */ | |
3201 | used_rx_desc = mp->rx_used_desc_q; | |
3202 | p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc]; | |
3203 | ||
3204 | p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr; | |
3205 | p_used_rx_desc->buf_size = p_pkt_info->byte_cnt; | |
3206 | mp->rx_skb[used_rx_desc] = p_pkt_info->return_info; | |
3207 | ||
3208 | /* Flush the write pipe */ | |
3209 | ||
3210 | /* Return the descriptor to DMA ownership */ | |
3211 | wmb(); | |
3212 | p_used_rx_desc->cmd_sts = | |
3213 | ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; | |
3214 | wmb(); | |
3215 | ||
3216 | /* Move the used descriptor pointer to the next descriptor */ | |
3217 | mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size; | |
3218 | ||
3219 | /* Any Rx return cancels the Rx resource error status */ | |
3220 | mp->rx_resource_err = 0; | |
3221 | ||
8f518703 DF |
3222 | spin_unlock_irqrestore(&mp->lock, flags); |
3223 | ||
1da177e4 LT |
3224 | return ETH_OK; |
3225 | } | |
3226 | ||
3227 | /************* Begin ethtool support *************************/ | |
3228 | ||
3229 | struct mv643xx_stats { | |
3230 | char stat_string[ETH_GSTRING_LEN]; | |
3231 | int sizeof_stat; | |
3232 | int stat_offset; | |
3233 | }; | |
3234 | ||
7a6d84c1 | 3235 | #define MV643XX_STAT(m) FIELD_SIZEOF(struct mv643xx_private, m), \ |
b4de9051 | 3236 | offsetof(struct mv643xx_private, m) |
1da177e4 LT |
3237 | |
3238 | static const struct mv643xx_stats mv643xx_gstrings_stats[] = { | |
3239 | { "rx_packets", MV643XX_STAT(stats.rx_packets) }, | |
3240 | { "tx_packets", MV643XX_STAT(stats.tx_packets) }, | |
3241 | { "rx_bytes", MV643XX_STAT(stats.rx_bytes) }, | |
3242 | { "tx_bytes", MV643XX_STAT(stats.tx_bytes) }, | |
3243 | { "rx_errors", MV643XX_STAT(stats.rx_errors) }, | |
3244 | { "tx_errors", MV643XX_STAT(stats.tx_errors) }, | |
3245 | { "rx_dropped", MV643XX_STAT(stats.rx_dropped) }, | |
3246 | { "tx_dropped", MV643XX_STAT(stats.tx_dropped) }, | |
3247 | { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) }, | |
3248 | { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) }, | |
3249 | { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) }, | |
3250 | { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) }, | |
3251 | { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) }, | |
3252 | { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) }, | |
3253 | { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) }, | |
3254 | { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) }, | |
3255 | { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) }, | |
3256 | { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) }, | |
3257 | { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) }, | |
3258 | { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) }, | |
3259 | { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) }, | |
3260 | { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) }, | |
3261 | { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) }, | |
3262 | { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) }, | |
3263 | { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) }, | |
3264 | { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) }, | |
3265 | { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) }, | |
3266 | { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) }, | |
3267 | { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) }, | |
3268 | { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) }, | |
3269 | { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) }, | |
3270 | { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) }, | |
3271 | { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) }, | |
3272 | { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) }, | |
3273 | { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) }, | |
3274 | { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) }, | |
3275 | { "collision", MV643XX_STAT(mib_counters.collision) }, | |
3276 | { "late_collision", MV643XX_STAT(mib_counters.late_collision) }, | |
3277 | }; | |
3278 | ||
ff8ac609 | 3279 | #define MV643XX_STATS_LEN ARRAY_SIZE(mv643xx_gstrings_stats) |
1da177e4 | 3280 | |
b4de9051 DF |
3281 | static void mv643xx_get_drvinfo(struct net_device *netdev, |
3282 | struct ethtool_drvinfo *drvinfo) | |
1da177e4 LT |
3283 | { |
3284 | strncpy(drvinfo->driver, mv643xx_driver_name, 32); | |
3285 | strncpy(drvinfo->version, mv643xx_driver_version, 32); | |
3286 | strncpy(drvinfo->fw_version, "N/A", 32); | |
3287 | strncpy(drvinfo->bus_info, "mv643xx", 32); | |
3288 | drvinfo->n_stats = MV643XX_STATS_LEN; | |
3289 | } | |
3290 | ||
b9f2c044 | 3291 | static int mv643xx_get_sset_count(struct net_device *netdev, int sset) |
1da177e4 | 3292 | { |
b9f2c044 JG |
3293 | switch (sset) { |
3294 | case ETH_SS_STATS: | |
3295 | return MV643XX_STATS_LEN; | |
3296 | default: | |
3297 | return -EOPNOTSUPP; | |
3298 | } | |
1da177e4 LT |
3299 | } |
3300 | ||
b4de9051 DF |
3301 | static void mv643xx_get_ethtool_stats(struct net_device *netdev, |
3302 | struct ethtool_stats *stats, uint64_t *data) | |
1da177e4 LT |
3303 | { |
3304 | struct mv643xx_private *mp = netdev->priv; | |
3305 | int i; | |
3306 | ||
3307 | eth_update_mib_counters(mp); | |
3308 | ||
b4de9051 | 3309 | for (i = 0; i < MV643XX_STATS_LEN; i++) { |
6aa20a22 | 3310 | char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset; |
b4de9051 | 3311 | data[i] = (mv643xx_gstrings_stats[i].sizeof_stat == |
1da177e4 LT |
3312 | sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p; |
3313 | } | |
3314 | } | |
3315 | ||
b4de9051 DF |
3316 | static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset, |
3317 | uint8_t *data) | |
1da177e4 LT |
3318 | { |
3319 | int i; | |
3320 | ||
3321 | switch(stringset) { | |
3322 | case ETH_SS_STATS: | |
3323 | for (i=0; i < MV643XX_STATS_LEN; i++) { | |
b4de9051 DF |
3324 | memcpy(data + i * ETH_GSTRING_LEN, |
3325 | mv643xx_gstrings_stats[i].stat_string, | |
3326 | ETH_GSTRING_LEN); | |
1da177e4 LT |
3327 | } |
3328 | break; | |
3329 | } | |
3330 | } | |
3331 | ||
d0412d96 JC |
3332 | static u32 mv643xx_eth_get_link(struct net_device *dev) |
3333 | { | |
3334 | struct mv643xx_private *mp = netdev_priv(dev); | |
3335 | ||
3336 | return mii_link_ok(&mp->mii); | |
3337 | } | |
3338 | ||
3339 | static int mv643xx_eth_nway_restart(struct net_device *dev) | |
3340 | { | |
3341 | struct mv643xx_private *mp = netdev_priv(dev); | |
3342 | ||
3343 | return mii_nway_restart(&mp->mii); | |
3344 | } | |
3345 | ||
3346 | static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
3347 | { | |
3348 | struct mv643xx_private *mp = netdev_priv(dev); | |
3349 | ||
3350 | return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL); | |
3351 | } | |
3352 | ||
7282d491 | 3353 | static const struct ethtool_ops mv643xx_ethtool_ops = { |
1da177e4 | 3354 | .get_settings = mv643xx_get_settings, |
d0412d96 | 3355 | .set_settings = mv643xx_set_settings, |
1da177e4 | 3356 | .get_drvinfo = mv643xx_get_drvinfo, |
d0412d96 | 3357 | .get_link = mv643xx_eth_get_link, |
1da177e4 | 3358 | .set_sg = ethtool_op_set_sg, |
194b2d0e | 3359 | .get_sset_count = mv643xx_get_sset_count, |
1da177e4 | 3360 | .get_ethtool_stats = mv643xx_get_ethtool_stats, |
d0412d96 | 3361 | .get_strings = mv643xx_get_strings, |
d0412d96 | 3362 | .nway_reset = mv643xx_eth_nway_restart, |
1da177e4 LT |
3363 | }; |
3364 | ||
3365 | /************* End ethtool support *************************/ |