Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
9c1bbdfe | 2 | * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports |
1da177e4 LT |
3 | * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com> |
4 | * | |
5 | * Based on the 64360 driver from: | |
4547fa61 LB |
6 | * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il> |
7 | * Rabeeh Khoury <rabeeh@marvell.com> | |
1da177e4 LT |
8 | * |
9 | * Copyright (C) 2003 PMC-Sierra, Inc., | |
3bb8a18a | 10 | * written by Manish Lachwani |
1da177e4 LT |
11 | * |
12 | * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> | |
13 | * | |
c8aaea25 | 14 | * Copyright (C) 2004-2006 MontaVista Software, Inc. |
1da177e4 LT |
15 | * Dale Farnsworth <dale@farnsworth.org> |
16 | * | |
17 | * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com> | |
18 | * <sjhill@realitydiluted.com> | |
19 | * | |
4547fa61 LB |
20 | * Copyright (C) 2007-2008 Marvell Semiconductor |
21 | * Lennert Buytenhek <buytenh@marvell.com> | |
22 | * | |
1da177e4 LT |
23 | * This program is free software; you can redistribute it and/or |
24 | * modify it under the terms of the GNU General Public License | |
25 | * as published by the Free Software Foundation; either version 2 | |
26 | * of the License, or (at your option) any later version. | |
27 | * | |
28 | * This program is distributed in the hope that it will be useful, | |
29 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
30 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
31 | * GNU General Public License for more details. | |
32 | * | |
33 | * You should have received a copy of the GNU General Public License | |
34 | * along with this program; if not, write to the Free Software | |
35 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
36 | */ | |
a779d38c | 37 | |
1da177e4 LT |
38 | #include <linux/init.h> |
39 | #include <linux/dma-mapping.h> | |
b6298c22 | 40 | #include <linux/in.h> |
1da177e4 LT |
41 | #include <linux/tcp.h> |
42 | #include <linux/udp.h> | |
43 | #include <linux/etherdevice.h> | |
1da177e4 LT |
44 | #include <linux/delay.h> |
45 | #include <linux/ethtool.h> | |
d052d1be | 46 | #include <linux/platform_device.h> |
fbd6a754 LB |
47 | #include <linux/module.h> |
48 | #include <linux/kernel.h> | |
49 | #include <linux/spinlock.h> | |
50 | #include <linux/workqueue.h> | |
51 | #include <linux/mii.h> | |
fbd6a754 | 52 | #include <linux/mv643xx_eth.h> |
1da177e4 LT |
53 | #include <asm/io.h> |
54 | #include <asm/types.h> | |
1da177e4 | 55 | #include <asm/system.h> |
fbd6a754 | 56 | |
e5371493 LB |
57 | static char mv643xx_eth_driver_name[] = "mv643xx_eth"; |
58 | static char mv643xx_eth_driver_version[] = "1.0"; | |
c9df406f | 59 | |
e5371493 LB |
60 | #define MV643XX_ETH_CHECKSUM_OFFLOAD_TX |
61 | #define MV643XX_ETH_NAPI | |
62 | #define MV643XX_ETH_TX_FAST_REFILL | |
fbd6a754 | 63 | |
e5371493 | 64 | #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX |
fbd6a754 LB |
65 | #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1) |
66 | #else | |
67 | #define MAX_DESCS_PER_SKB 1 | |
68 | #endif | |
69 | ||
8a578111 | 70 | #define ETH_HW_IP_ALIGN 2 |
fbd6a754 LB |
71 | |
72 | /* | |
73 | * Registers shared between all ports. | |
74 | */ | |
3cb4667c LB |
75 | #define PHY_ADDR 0x0000 |
76 | #define SMI_REG 0x0004 | |
77 | #define WINDOW_BASE(w) (0x0200 + ((w) << 3)) | |
78 | #define WINDOW_SIZE(w) (0x0204 + ((w) << 3)) | |
79 | #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2)) | |
80 | #define WINDOW_BAR_ENABLE 0x0290 | |
81 | #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4)) | |
fbd6a754 LB |
82 | |
83 | /* | |
84 | * Per-port registers. | |
85 | */ | |
3cb4667c | 86 | #define PORT_CONFIG(p) (0x0400 + ((p) << 10)) |
d9a073ea | 87 | #define UNICAST_PROMISCUOUS_MODE 0x00000001 |
3cb4667c LB |
88 | #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10)) |
89 | #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10)) | |
90 | #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10)) | |
91 | #define SDMA_CONFIG(p) (0x041c + ((p) << 10)) | |
92 | #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10)) | |
93 | #define PORT_STATUS(p) (0x0444 + ((p) << 10)) | |
a2a41689 | 94 | #define TX_FIFO_EMPTY 0x00000400 |
3cb4667c LB |
95 | #define TXQ_COMMAND(p) (0x0448 + ((p) << 10)) |
96 | #define TX_BW_MTU(p) (0x0458 + ((p) << 10)) | |
97 | #define INT_CAUSE(p) (0x0460 + ((p) << 10)) | |
073a345c LB |
98 | #define INT_RX 0x00000804 |
99 | #define INT_EXT 0x00000002 | |
3cb4667c | 100 | #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10)) |
073a345c LB |
101 | #define INT_EXT_LINK 0x00100000 |
102 | #define INT_EXT_PHY 0x00010000 | |
103 | #define INT_EXT_TX_ERROR_0 0x00000100 | |
104 | #define INT_EXT_TX_0 0x00000001 | |
105 | #define INT_EXT_TX 0x00000101 | |
3cb4667c LB |
106 | #define INT_MASK(p) (0x0468 + ((p) << 10)) |
107 | #define INT_MASK_EXT(p) (0x046c + ((p) << 10)) | |
108 | #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10)) | |
109 | #define RXQ_CURRENT_DESC_PTR(p) (0x060c + ((p) << 10)) | |
110 | #define RXQ_COMMAND(p) (0x0680 + ((p) << 10)) | |
111 | #define TXQ_CURRENT_DESC_PTR(p) (0x06c0 + ((p) << 10)) | |
112 | #define MIB_COUNTERS(p) (0x1000 + ((p) << 7)) | |
113 | #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10)) | |
114 | #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10)) | |
115 | #define UNICAST_TABLE(p) (0x1600 + ((p) << 10)) | |
fbd6a754 | 116 | |
2679a550 LB |
117 | |
118 | /* | |
119 | * SDMA configuration register. | |
120 | */ | |
fbd6a754 | 121 | #define RX_BURST_SIZE_4_64BIT (2 << 1) |
fbd6a754 | 122 | #define BLM_RX_NO_SWAP (1 << 4) |
fbd6a754 | 123 | #define BLM_TX_NO_SWAP (1 << 5) |
fbd6a754 | 124 | #define TX_BURST_SIZE_4_64BIT (2 << 22) |
fbd6a754 LB |
125 | |
126 | #if defined(__BIG_ENDIAN) | |
127 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | |
128 | RX_BURST_SIZE_4_64BIT | \ | |
fbd6a754 LB |
129 | TX_BURST_SIZE_4_64BIT |
130 | #elif defined(__LITTLE_ENDIAN) | |
131 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | |
132 | RX_BURST_SIZE_4_64BIT | \ | |
133 | BLM_RX_NO_SWAP | \ | |
134 | BLM_TX_NO_SWAP | \ | |
fbd6a754 LB |
135 | TX_BURST_SIZE_4_64BIT |
136 | #else | |
137 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | |
138 | #endif | |
139 | ||
2beff77b LB |
140 | |
141 | /* | |
142 | * Port serial control register. | |
143 | */ | |
144 | #define SET_MII_SPEED_TO_100 (1 << 24) | |
145 | #define SET_GMII_SPEED_TO_1000 (1 << 23) | |
146 | #define SET_FULL_DUPLEX_MODE (1 << 21) | |
fbd6a754 | 147 | #define MAX_RX_PACKET_1522BYTE (1 << 17) |
fbd6a754 LB |
148 | #define MAX_RX_PACKET_9700BYTE (5 << 17) |
149 | #define MAX_RX_PACKET_MASK (7 << 17) | |
2beff77b LB |
150 | #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13) |
151 | #define DO_NOT_FORCE_LINK_FAIL (1 << 10) | |
152 | #define SERIAL_PORT_CONTROL_RESERVED (1 << 9) | |
153 | #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3) | |
154 | #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2) | |
155 | #define FORCE_LINK_PASS (1 << 1) | |
156 | #define SERIAL_PORT_ENABLE (1 << 0) | |
fbd6a754 | 157 | |
cc9754b3 LB |
158 | #define DEFAULT_RX_QUEUE_SIZE 400 |
159 | #define DEFAULT_TX_QUEUE_SIZE 800 | |
fbd6a754 | 160 | |
fbd6a754 | 161 | /* SMI reg */ |
cc9754b3 LB |
162 | #define SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */ |
163 | #define SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */ | |
164 | #define SMI_OPCODE_WRITE 0 /* Completion of Read */ | |
165 | #define SMI_OPCODE_READ 0x04000000 /* Operation is in progress */ | |
fbd6a754 | 166 | |
fbd6a754 | 167 | |
7ca72a3b LB |
168 | /* |
169 | * RX/TX descriptors. | |
fbd6a754 LB |
170 | */ |
171 | #if defined(__BIG_ENDIAN) | |
cc9754b3 | 172 | struct rx_desc { |
fbd6a754 LB |
173 | u16 byte_cnt; /* Descriptor buffer byte count */ |
174 | u16 buf_size; /* Buffer size */ | |
175 | u32 cmd_sts; /* Descriptor command status */ | |
176 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
177 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
178 | }; | |
179 | ||
cc9754b3 | 180 | struct tx_desc { |
fbd6a754 LB |
181 | u16 byte_cnt; /* buffer byte count */ |
182 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
183 | u32 cmd_sts; /* Command/status field */ | |
184 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
185 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
186 | }; | |
187 | #elif defined(__LITTLE_ENDIAN) | |
cc9754b3 | 188 | struct rx_desc { |
fbd6a754 LB |
189 | u32 cmd_sts; /* Descriptor command status */ |
190 | u16 buf_size; /* Buffer size */ | |
191 | u16 byte_cnt; /* Descriptor buffer byte count */ | |
192 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
193 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
194 | }; | |
195 | ||
cc9754b3 | 196 | struct tx_desc { |
fbd6a754 LB |
197 | u32 cmd_sts; /* Command/status field */ |
198 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
199 | u16 byte_cnt; /* buffer byte count */ | |
200 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
201 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
202 | }; | |
203 | #else | |
204 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | |
205 | #endif | |
206 | ||
7ca72a3b | 207 | /* RX & TX descriptor command */ |
cc9754b3 | 208 | #define BUFFER_OWNED_BY_DMA 0x80000000 |
7ca72a3b LB |
209 | |
210 | /* RX & TX descriptor status */ | |
cc9754b3 | 211 | #define ERROR_SUMMARY 0x00000001 |
7ca72a3b LB |
212 | |
213 | /* RX descriptor status */ | |
cc9754b3 LB |
214 | #define LAYER_4_CHECKSUM_OK 0x40000000 |
215 | #define RX_ENABLE_INTERRUPT 0x20000000 | |
216 | #define RX_FIRST_DESC 0x08000000 | |
217 | #define RX_LAST_DESC 0x04000000 | |
7ca72a3b LB |
218 | |
219 | /* TX descriptor command */ | |
cc9754b3 LB |
220 | #define TX_ENABLE_INTERRUPT 0x00800000 |
221 | #define GEN_CRC 0x00400000 | |
222 | #define TX_FIRST_DESC 0x00200000 | |
223 | #define TX_LAST_DESC 0x00100000 | |
224 | #define ZERO_PADDING 0x00080000 | |
225 | #define GEN_IP_V4_CHECKSUM 0x00040000 | |
226 | #define GEN_TCP_UDP_CHECKSUM 0x00020000 | |
227 | #define UDP_FRAME 0x00010000 | |
7ca72a3b | 228 | |
cc9754b3 | 229 | #define TX_IHL_SHIFT 11 |
7ca72a3b LB |
230 | |
231 | ||
c9df406f | 232 | /* global *******************************************************************/ |
e5371493 | 233 | struct mv643xx_eth_shared_private { |
cc9754b3 | 234 | void __iomem *base; |
c9df406f LB |
235 | |
236 | /* used to protect SMI_REG, which is shared across ports */ | |
237 | spinlock_t phy_lock; | |
238 | ||
239 | u32 win_protect; | |
240 | ||
241 | unsigned int t_clk; | |
242 | }; | |
243 | ||
244 | ||
245 | /* per-port *****************************************************************/ | |
e5371493 | 246 | struct mib_counters { |
fbd6a754 LB |
247 | u64 good_octets_received; |
248 | u32 bad_octets_received; | |
249 | u32 internal_mac_transmit_err; | |
250 | u32 good_frames_received; | |
251 | u32 bad_frames_received; | |
252 | u32 broadcast_frames_received; | |
253 | u32 multicast_frames_received; | |
254 | u32 frames_64_octets; | |
255 | u32 frames_65_to_127_octets; | |
256 | u32 frames_128_to_255_octets; | |
257 | u32 frames_256_to_511_octets; | |
258 | u32 frames_512_to_1023_octets; | |
259 | u32 frames_1024_to_max_octets; | |
260 | u64 good_octets_sent; | |
261 | u32 good_frames_sent; | |
262 | u32 excessive_collision; | |
263 | u32 multicast_frames_sent; | |
264 | u32 broadcast_frames_sent; | |
265 | u32 unrec_mac_control_received; | |
266 | u32 fc_sent; | |
267 | u32 good_fc_received; | |
268 | u32 bad_fc_received; | |
269 | u32 undersize_received; | |
270 | u32 fragments_received; | |
271 | u32 oversize_received; | |
272 | u32 jabber_received; | |
273 | u32 mac_receive_error; | |
274 | u32 bad_crc_event; | |
275 | u32 collision; | |
276 | u32 late_collision; | |
277 | }; | |
278 | ||
8a578111 LB |
279 | struct rx_queue { |
280 | int rx_ring_size; | |
281 | ||
282 | int rx_desc_count; | |
283 | int rx_curr_desc; | |
284 | int rx_used_desc; | |
285 | ||
286 | struct rx_desc *rx_desc_area; | |
287 | dma_addr_t rx_desc_dma; | |
288 | int rx_desc_area_size; | |
289 | struct sk_buff **rx_skb; | |
290 | ||
291 | struct timer_list rx_oom; | |
292 | }; | |
293 | ||
13d64285 LB |
294 | struct tx_queue { |
295 | int tx_ring_size; | |
fbd6a754 | 296 | |
13d64285 LB |
297 | int tx_desc_count; |
298 | int tx_curr_desc; | |
299 | int tx_used_desc; | |
fbd6a754 | 300 | |
5daffe94 | 301 | struct tx_desc *tx_desc_area; |
fbd6a754 LB |
302 | dma_addr_t tx_desc_dma; |
303 | int tx_desc_area_size; | |
304 | struct sk_buff **tx_skb; | |
13d64285 LB |
305 | }; |
306 | ||
307 | struct mv643xx_eth_private { | |
308 | struct mv643xx_eth_shared_private *shared; | |
309 | int port_num; /* User Ethernet port number */ | |
310 | ||
311 | struct mv643xx_eth_shared_private *shared_smi; | |
fbd6a754 LB |
312 | |
313 | struct work_struct tx_timeout_task; | |
314 | ||
315 | struct net_device *dev; | |
e5371493 | 316 | struct mib_counters mib_counters; |
fbd6a754 | 317 | spinlock_t lock; |
fbd6a754 | 318 | |
fbd6a754 | 319 | struct mii_if_info mii; |
8a578111 LB |
320 | |
321 | /* | |
322 | * RX state. | |
323 | */ | |
324 | int default_rx_ring_size; | |
325 | unsigned long rx_desc_sram_addr; | |
326 | int rx_desc_sram_size; | |
327 | struct napi_struct napi; | |
328 | struct rx_queue rxq[1]; | |
13d64285 LB |
329 | |
330 | /* | |
331 | * TX state. | |
332 | */ | |
333 | int default_tx_ring_size; | |
334 | unsigned long tx_desc_sram_addr; | |
335 | int tx_desc_sram_size; | |
336 | struct tx_queue txq[1]; | |
337 | #ifdef MV643XX_ETH_TX_FAST_REFILL | |
338 | int tx_clean_threshold; | |
339 | #endif | |
fbd6a754 | 340 | }; |
1da177e4 | 341 | |
fbd6a754 | 342 | |
c9df406f | 343 | /* port register accessors **************************************************/ |
e5371493 | 344 | static inline u32 rdl(struct mv643xx_eth_private *mp, int offset) |
c9df406f | 345 | { |
cc9754b3 | 346 | return readl(mp->shared->base + offset); |
c9df406f | 347 | } |
fbd6a754 | 348 | |
e5371493 | 349 | static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data) |
c9df406f | 350 | { |
cc9754b3 | 351 | writel(data, mp->shared->base + offset); |
c9df406f | 352 | } |
fbd6a754 | 353 | |
fbd6a754 | 354 | |
c9df406f | 355 | /* rxq/txq helper functions *************************************************/ |
8a578111 | 356 | static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq) |
c9df406f | 357 | { |
8a578111 | 358 | return container_of(rxq, struct mv643xx_eth_private, rxq[0]); |
c9df406f | 359 | } |
fbd6a754 | 360 | |
13d64285 LB |
361 | static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq) |
362 | { | |
363 | return container_of(txq, struct mv643xx_eth_private, txq[0]); | |
364 | } | |
365 | ||
8a578111 | 366 | static void rxq_enable(struct rx_queue *rxq) |
c9df406f | 367 | { |
8a578111 LB |
368 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
369 | wrl(mp, RXQ_COMMAND(mp->port_num), 1); | |
370 | } | |
1da177e4 | 371 | |
8a578111 LB |
372 | static void rxq_disable(struct rx_queue *rxq) |
373 | { | |
374 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); | |
375 | u8 mask = 1; | |
1da177e4 | 376 | |
8a578111 LB |
377 | wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8); |
378 | while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask) | |
379 | udelay(10); | |
c9df406f LB |
380 | } |
381 | ||
13d64285 | 382 | static void txq_enable(struct tx_queue *txq) |
1da177e4 | 383 | { |
13d64285 LB |
384 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
385 | wrl(mp, TXQ_COMMAND(mp->port_num), 1); | |
1da177e4 LT |
386 | } |
387 | ||
13d64285 | 388 | static void txq_disable(struct tx_queue *txq) |
1da177e4 | 389 | { |
13d64285 LB |
390 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
391 | u8 mask = 1; | |
c9df406f | 392 | |
13d64285 LB |
393 | wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8); |
394 | while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask) | |
395 | udelay(10); | |
396 | } | |
397 | ||
398 | static void __txq_maybe_wake(struct tx_queue *txq) | |
399 | { | |
400 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
401 | ||
402 | if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB) | |
403 | netif_wake_queue(mp->dev); | |
1da177e4 LT |
404 | } |
405 | ||
c9df406f LB |
406 | |
407 | /* rx ***********************************************************************/ | |
13d64285 | 408 | static void txq_reclaim(struct tx_queue *txq, int force); |
c9df406f | 409 | |
8a578111 | 410 | static void rxq_refill(struct rx_queue *rxq) |
1da177e4 | 411 | { |
8a578111 | 412 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
c9df406f | 413 | unsigned long flags; |
1da177e4 | 414 | |
c9df406f | 415 | spin_lock_irqsave(&mp->lock, flags); |
c0d0f2ca | 416 | |
8a578111 LB |
417 | while (rxq->rx_desc_count < rxq->rx_ring_size) { |
418 | int skb_size; | |
de34f225 LB |
419 | struct sk_buff *skb; |
420 | int unaligned; | |
421 | int rx; | |
422 | ||
8a578111 LB |
423 | /* |
424 | * Reserve 2+14 bytes for an ethernet header (the | |
425 | * hardware automatically prepends 2 bytes of dummy | |
426 | * data to each received packet), 4 bytes for a VLAN | |
427 | * header, and 4 bytes for the trailing FCS -- 24 | |
428 | * bytes total. | |
429 | */ | |
430 | skb_size = mp->dev->mtu + 24; | |
431 | ||
432 | skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1); | |
de34f225 | 433 | if (skb == NULL) |
1da177e4 | 434 | break; |
de34f225 | 435 | |
908b637f | 436 | unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1); |
b44cd572 | 437 | if (unaligned) |
908b637f | 438 | skb_reserve(skb, dma_get_cache_alignment() - unaligned); |
de34f225 | 439 | |
8a578111 LB |
440 | rxq->rx_desc_count++; |
441 | rx = rxq->rx_used_desc; | |
442 | rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size; | |
de34f225 | 443 | |
8a578111 LB |
444 | rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data, |
445 | skb_size, DMA_FROM_DEVICE); | |
446 | rxq->rx_desc_area[rx].buf_size = skb_size; | |
447 | rxq->rx_skb[rx] = skb; | |
de34f225 | 448 | wmb(); |
8a578111 | 449 | rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA | |
de34f225 LB |
450 | RX_ENABLE_INTERRUPT; |
451 | wmb(); | |
452 | ||
7303fde8 | 453 | skb_reserve(skb, ETH_HW_IP_ALIGN); |
1da177e4 | 454 | } |
de34f225 | 455 | |
8a578111 LB |
456 | if (rxq->rx_desc_count == 0) { |
457 | rxq->rx_oom.expires = jiffies + (HZ / 10); | |
458 | add_timer(&rxq->rx_oom); | |
1da177e4 | 459 | } |
de34f225 LB |
460 | |
461 | spin_unlock_irqrestore(&mp->lock, flags); | |
1da177e4 LT |
462 | } |
463 | ||
8a578111 | 464 | static inline void rxq_refill_timer_wrapper(unsigned long data) |
1da177e4 | 465 | { |
8a578111 | 466 | rxq_refill((struct rx_queue *)data); |
1da177e4 LT |
467 | } |
468 | ||
8a578111 | 469 | static int rxq_process(struct rx_queue *rxq, int budget) |
1da177e4 | 470 | { |
8a578111 LB |
471 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
472 | struct net_device_stats *stats = &mp->dev->stats; | |
473 | int rx; | |
1da177e4 | 474 | |
8a578111 LB |
475 | rx = 0; |
476 | while (rx < budget) { | |
96587661 LB |
477 | struct sk_buff *skb; |
478 | volatile struct rx_desc *rx_desc; | |
479 | unsigned int cmd_sts; | |
480 | unsigned long flags; | |
d344bff9 | 481 | |
96587661 | 482 | spin_lock_irqsave(&mp->lock, flags); |
ff561eef | 483 | |
8a578111 | 484 | rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc]; |
1da177e4 | 485 | |
96587661 LB |
486 | cmd_sts = rx_desc->cmd_sts; |
487 | if (cmd_sts & BUFFER_OWNED_BY_DMA) { | |
488 | spin_unlock_irqrestore(&mp->lock, flags); | |
489 | break; | |
490 | } | |
491 | rmb(); | |
1da177e4 | 492 | |
8a578111 LB |
493 | skb = rxq->rx_skb[rxq->rx_curr_desc]; |
494 | rxq->rx_skb[rxq->rx_curr_desc] = NULL; | |
ff561eef | 495 | |
8a578111 | 496 | rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size; |
ff561eef | 497 | |
96587661 | 498 | spin_unlock_irqrestore(&mp->lock, flags); |
1da177e4 | 499 | |
96587661 | 500 | dma_unmap_single(NULL, rx_desc->buf_ptr + ETH_HW_IP_ALIGN, |
8a578111 LB |
501 | mp->dev->mtu + 24, DMA_FROM_DEVICE); |
502 | rxq->rx_desc_count--; | |
503 | rx++; | |
b1dd9ca1 | 504 | |
468d09f8 DF |
505 | /* |
506 | * Update statistics. | |
507 | * Note byte count includes 4 byte CRC count | |
508 | */ | |
1da177e4 | 509 | stats->rx_packets++; |
96587661 LB |
510 | stats->rx_bytes += rx_desc->byte_cnt - ETH_HW_IP_ALIGN; |
511 | ||
1da177e4 LT |
512 | /* |
513 | * In case received a packet without first / last bits on OR | |
514 | * the error summary bit is on, the packets needs to be dropeed. | |
515 | */ | |
96587661 | 516 | if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != |
cc9754b3 | 517 | (RX_FIRST_DESC | RX_LAST_DESC)) |
96587661 | 518 | || (cmd_sts & ERROR_SUMMARY)) { |
1da177e4 | 519 | stats->rx_dropped++; |
96587661 | 520 | if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != |
cc9754b3 | 521 | (RX_FIRST_DESC | RX_LAST_DESC)) { |
1da177e4 LT |
522 | if (net_ratelimit()) |
523 | printk(KERN_ERR | |
524 | "%s: Received packet spread " | |
525 | "on multiple descriptors\n", | |
8a578111 | 526 | mp->dev->name); |
1da177e4 | 527 | } |
96587661 | 528 | if (cmd_sts & ERROR_SUMMARY) |
1da177e4 LT |
529 | stats->rx_errors++; |
530 | ||
531 | dev_kfree_skb_irq(skb); | |
532 | } else { | |
533 | /* | |
534 | * The -4 is for the CRC in the trailer of the | |
535 | * received packet | |
536 | */ | |
96587661 | 537 | skb_put(skb, rx_desc->byte_cnt - ETH_HW_IP_ALIGN - 4); |
1da177e4 | 538 | |
96587661 | 539 | if (cmd_sts & LAYER_4_CHECKSUM_OK) { |
1da177e4 LT |
540 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
541 | skb->csum = htons( | |
96587661 | 542 | (cmd_sts & 0x0007fff8) >> 3); |
1da177e4 | 543 | } |
8a578111 | 544 | skb->protocol = eth_type_trans(skb, mp->dev); |
e5371493 | 545 | #ifdef MV643XX_ETH_NAPI |
1da177e4 LT |
546 | netif_receive_skb(skb); |
547 | #else | |
548 | netif_rx(skb); | |
549 | #endif | |
550 | } | |
8a578111 | 551 | mp->dev->last_rx = jiffies; |
1da177e4 | 552 | } |
8a578111 | 553 | rxq_refill(rxq); |
1da177e4 | 554 | |
8a578111 | 555 | return rx; |
1da177e4 LT |
556 | } |
557 | ||
e5371493 | 558 | #ifdef MV643XX_ETH_NAPI |
e5371493 | 559 | static int mv643xx_eth_poll(struct napi_struct *napi, int budget) |
d0412d96 | 560 | { |
8a578111 LB |
561 | struct mv643xx_eth_private *mp; |
562 | int rx; | |
563 | ||
564 | mp = container_of(napi, struct mv643xx_eth_private, napi); | |
d0412d96 | 565 | |
e5371493 | 566 | #ifdef MV643XX_ETH_TX_FAST_REFILL |
c9df406f | 567 | if (++mp->tx_clean_threshold > 5) { |
13d64285 | 568 | txq_reclaim(mp->txq, 0); |
c9df406f | 569 | mp->tx_clean_threshold = 0; |
d0412d96 | 570 | } |
c9df406f | 571 | #endif |
d0412d96 | 572 | |
8a578111 | 573 | rx = rxq_process(mp->rxq, budget); |
d0412d96 | 574 | |
8a578111 LB |
575 | if (rx < budget) { |
576 | netif_rx_complete(mp->dev, napi); | |
577 | wrl(mp, INT_CAUSE(mp->port_num), 0); | |
578 | wrl(mp, INT_CAUSE_EXT(mp->port_num), 0); | |
579 | wrl(mp, INT_MASK(mp->port_num), INT_RX | INT_EXT); | |
d0412d96 | 580 | } |
c9df406f | 581 | |
8a578111 | 582 | return rx; |
d0412d96 | 583 | } |
c9df406f | 584 | #endif |
d0412d96 | 585 | |
c9df406f LB |
586 | |
587 | /* tx ***********************************************************************/ | |
c9df406f | 588 | static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) |
1da177e4 | 589 | { |
13d64285 | 590 | int frag; |
1da177e4 | 591 | |
c9df406f | 592 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { |
13d64285 LB |
593 | skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag]; |
594 | if (fragp->size <= 8 && fragp->page_offset & 7) | |
c9df406f | 595 | return 1; |
1da177e4 | 596 | } |
13d64285 | 597 | |
c9df406f LB |
598 | return 0; |
599 | } | |
7303fde8 | 600 | |
13d64285 | 601 | static int txq_alloc_desc_index(struct tx_queue *txq) |
c9df406f LB |
602 | { |
603 | int tx_desc_curr; | |
d0412d96 | 604 | |
13d64285 | 605 | BUG_ON(txq->tx_desc_count >= txq->tx_ring_size); |
1da177e4 | 606 | |
13d64285 LB |
607 | tx_desc_curr = txq->tx_curr_desc; |
608 | txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size; | |
e4d00fa9 | 609 | |
13d64285 | 610 | BUG_ON(txq->tx_curr_desc == txq->tx_used_desc); |
468d09f8 | 611 | |
c9df406f LB |
612 | return tx_desc_curr; |
613 | } | |
468d09f8 | 614 | |
13d64285 | 615 | static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb) |
c9df406f | 616 | { |
13d64285 | 617 | int nr_frags = skb_shinfo(skb)->nr_frags; |
c9df406f | 618 | int frag; |
1da177e4 | 619 | |
13d64285 LB |
620 | for (frag = 0; frag < nr_frags; frag++) { |
621 | skb_frag_t *this_frag; | |
622 | int tx_index; | |
623 | struct tx_desc *desc; | |
624 | ||
625 | this_frag = &skb_shinfo(skb)->frags[frag]; | |
626 | tx_index = txq_alloc_desc_index(txq); | |
627 | desc = &txq->tx_desc_area[tx_index]; | |
628 | ||
629 | /* | |
630 | * The last fragment will generate an interrupt | |
631 | * which will free the skb on TX completion. | |
632 | */ | |
633 | if (frag == nr_frags - 1) { | |
634 | desc->cmd_sts = BUFFER_OWNED_BY_DMA | | |
635 | ZERO_PADDING | TX_LAST_DESC | | |
636 | TX_ENABLE_INTERRUPT; | |
637 | txq->tx_skb[tx_index] = skb; | |
638 | } else { | |
639 | desc->cmd_sts = BUFFER_OWNED_BY_DMA; | |
640 | txq->tx_skb[tx_index] = NULL; | |
641 | } | |
642 | ||
c9df406f LB |
643 | desc->l4i_chk = 0; |
644 | desc->byte_cnt = this_frag->size; | |
645 | desc->buf_ptr = dma_map_page(NULL, this_frag->page, | |
646 | this_frag->page_offset, | |
647 | this_frag->size, | |
648 | DMA_TO_DEVICE); | |
649 | } | |
1da177e4 LT |
650 | } |
651 | ||
c9df406f LB |
652 | static inline __be16 sum16_as_be(__sum16 sum) |
653 | { | |
654 | return (__force __be16)sum; | |
655 | } | |
1da177e4 | 656 | |
13d64285 | 657 | static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb) |
1da177e4 | 658 | { |
13d64285 | 659 | int nr_frags = skb_shinfo(skb)->nr_frags; |
c9df406f | 660 | int tx_index; |
cc9754b3 | 661 | struct tx_desc *desc; |
c9df406f LB |
662 | u32 cmd_sts; |
663 | int length; | |
1da177e4 | 664 | |
cc9754b3 | 665 | cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA; |
1da177e4 | 666 | |
13d64285 LB |
667 | tx_index = txq_alloc_desc_index(txq); |
668 | desc = &txq->tx_desc_area[tx_index]; | |
c9df406f LB |
669 | |
670 | if (nr_frags) { | |
13d64285 | 671 | txq_submit_frag_skb(txq, skb); |
c9df406f LB |
672 | |
673 | length = skb_headlen(skb); | |
13d64285 | 674 | txq->tx_skb[tx_index] = NULL; |
c9df406f | 675 | } else { |
cc9754b3 | 676 | cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT; |
c9df406f | 677 | length = skb->len; |
13d64285 | 678 | txq->tx_skb[tx_index] = skb; |
c9df406f LB |
679 | } |
680 | ||
681 | desc->byte_cnt = length; | |
682 | desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE); | |
683 | ||
684 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
685 | BUG_ON(skb->protocol != htons(ETH_P_IP)); | |
686 | ||
cc9754b3 LB |
687 | cmd_sts |= GEN_TCP_UDP_CHECKSUM | |
688 | GEN_IP_V4_CHECKSUM | | |
689 | ip_hdr(skb)->ihl << TX_IHL_SHIFT; | |
c9df406f LB |
690 | |
691 | switch (ip_hdr(skb)->protocol) { | |
692 | case IPPROTO_UDP: | |
cc9754b3 | 693 | cmd_sts |= UDP_FRAME; |
c9df406f LB |
694 | desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check)); |
695 | break; | |
696 | case IPPROTO_TCP: | |
697 | desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check)); | |
698 | break; | |
699 | default: | |
700 | BUG(); | |
701 | } | |
702 | } else { | |
703 | /* Errata BTS #50, IHL must be 5 if no HW checksum */ | |
cc9754b3 | 704 | cmd_sts |= 5 << TX_IHL_SHIFT; |
c9df406f LB |
705 | desc->l4i_chk = 0; |
706 | } | |
707 | ||
708 | /* ensure all other descriptors are written before first cmd_sts */ | |
709 | wmb(); | |
710 | desc->cmd_sts = cmd_sts; | |
711 | ||
712 | /* ensure all descriptors are written before poking hardware */ | |
713 | wmb(); | |
13d64285 | 714 | txq_enable(txq); |
c9df406f | 715 | |
13d64285 | 716 | txq->tx_desc_count += nr_frags + 1; |
1da177e4 | 717 | } |
1da177e4 | 718 | |
c9df406f | 719 | static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 720 | { |
e5371493 | 721 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f | 722 | struct net_device_stats *stats = &dev->stats; |
13d64285 | 723 | struct tx_queue *txq; |
c9df406f | 724 | unsigned long flags; |
afdb57a2 | 725 | |
c9df406f | 726 | BUG_ON(netif_queue_stopped(dev)); |
afdb57a2 | 727 | |
c9df406f LB |
728 | if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) { |
729 | stats->tx_dropped++; | |
730 | printk(KERN_DEBUG "%s: failed to linearize tiny " | |
731 | "unaligned fragment\n", dev->name); | |
732 | return NETDEV_TX_BUSY; | |
733 | } | |
734 | ||
735 | spin_lock_irqsave(&mp->lock, flags); | |
736 | ||
13d64285 LB |
737 | txq = mp->txq; |
738 | ||
739 | if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) { | |
c9df406f LB |
740 | printk(KERN_ERR "%s: transmit with queue full\n", dev->name); |
741 | netif_stop_queue(dev); | |
742 | spin_unlock_irqrestore(&mp->lock, flags); | |
743 | return NETDEV_TX_BUSY; | |
744 | } | |
745 | ||
13d64285 | 746 | txq_submit_skb(txq, skb); |
c9df406f LB |
747 | stats->tx_bytes += skb->len; |
748 | stats->tx_packets++; | |
749 | dev->trans_start = jiffies; | |
750 | ||
13d64285 | 751 | if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) |
c9df406f LB |
752 | netif_stop_queue(dev); |
753 | ||
754 | spin_unlock_irqrestore(&mp->lock, flags); | |
755 | ||
756 | return NETDEV_TX_OK; | |
1da177e4 LT |
757 | } |
758 | ||
c9df406f LB |
759 | |
760 | /* mii management interface *************************************************/ | |
e5371493 | 761 | static int phy_addr_get(struct mv643xx_eth_private *mp); |
c9df406f | 762 | |
e5371493 | 763 | static void read_smi_reg(struct mv643xx_eth_private *mp, |
c9df406f | 764 | unsigned int phy_reg, unsigned int *value) |
1da177e4 | 765 | { |
cc9754b3 LB |
766 | void __iomem *smi_reg = mp->shared_smi->base + SMI_REG; |
767 | int phy_addr = phy_addr_get(mp); | |
c9df406f | 768 | unsigned long flags; |
1da177e4 LT |
769 | int i; |
770 | ||
c9df406f LB |
771 | /* the SMI register is a shared resource */ |
772 | spin_lock_irqsave(&mp->shared_smi->phy_lock, flags); | |
773 | ||
774 | /* wait for the SMI register to become available */ | |
cc9754b3 | 775 | for (i = 0; readl(smi_reg) & SMI_BUSY; i++) { |
e1bea50a | 776 | if (i == 1000) { |
c9df406f LB |
777 | printk("%s: PHY busy timeout\n", mp->dev->name); |
778 | goto out; | |
779 | } | |
e1bea50a | 780 | udelay(10); |
1da177e4 LT |
781 | } |
782 | ||
cc9754b3 | 783 | writel((phy_addr << 16) | (phy_reg << 21) | SMI_OPCODE_READ, smi_reg); |
1da177e4 | 784 | |
c9df406f | 785 | /* now wait for the data to be valid */ |
cc9754b3 | 786 | for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) { |
e1bea50a | 787 | if (i == 1000) { |
c9df406f LB |
788 | printk("%s: PHY read timeout\n", mp->dev->name); |
789 | goto out; | |
790 | } | |
e1bea50a | 791 | udelay(10); |
c9df406f LB |
792 | } |
793 | ||
794 | *value = readl(smi_reg) & 0xffff; | |
795 | out: | |
796 | spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags); | |
1da177e4 LT |
797 | } |
798 | ||
e5371493 | 799 | static void write_smi_reg(struct mv643xx_eth_private *mp, |
c9df406f | 800 | unsigned int phy_reg, unsigned int value) |
1da177e4 | 801 | { |
cc9754b3 LB |
802 | void __iomem *smi_reg = mp->shared_smi->base + SMI_REG; |
803 | int phy_addr = phy_addr_get(mp); | |
c9df406f | 804 | unsigned long flags; |
1da177e4 LT |
805 | int i; |
806 | ||
c9df406f LB |
807 | /* the SMI register is a shared resource */ |
808 | spin_lock_irqsave(&mp->shared_smi->phy_lock, flags); | |
809 | ||
810 | /* wait for the SMI register to become available */ | |
cc9754b3 | 811 | for (i = 0; readl(smi_reg) & SMI_BUSY; i++) { |
e1bea50a | 812 | if (i == 1000) { |
c9df406f LB |
813 | printk("%s: PHY busy timeout\n", mp->dev->name); |
814 | goto out; | |
815 | } | |
e1bea50a | 816 | udelay(10); |
1da177e4 LT |
817 | } |
818 | ||
c9df406f | 819 | writel((phy_addr << 16) | (phy_reg << 21) | |
cc9754b3 | 820 | SMI_OPCODE_WRITE | (value & 0xffff), smi_reg); |
c9df406f LB |
821 | out: |
822 | spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags); | |
823 | } | |
1da177e4 | 824 | |
c9df406f LB |
825 | |
826 | /* mib counters *************************************************************/ | |
e5371493 | 827 | static void clear_mib_counters(struct mv643xx_eth_private *mp) |
c9df406f LB |
828 | { |
829 | unsigned int port_num = mp->port_num; | |
830 | int i; | |
831 | ||
832 | /* Perform dummy reads from MIB counters */ | |
4b8e3655 | 833 | for (i = 0; i < 0x80; i += 4) |
3cb4667c | 834 | rdl(mp, MIB_COUNTERS(port_num) + i); |
1da177e4 LT |
835 | } |
836 | ||
e5371493 | 837 | static inline u32 read_mib(struct mv643xx_eth_private *mp, int offset) |
d0412d96 | 838 | { |
3cb4667c | 839 | return rdl(mp, MIB_COUNTERS(mp->port_num) + offset); |
c9df406f | 840 | } |
d0412d96 | 841 | |
e5371493 | 842 | static void update_mib_counters(struct mv643xx_eth_private *mp) |
c9df406f | 843 | { |
e5371493 | 844 | struct mib_counters *p = &mp->mib_counters; |
4b8e3655 LB |
845 | |
846 | p->good_octets_received += read_mib(mp, 0x00); | |
847 | p->good_octets_received += (u64)read_mib(mp, 0x04) << 32; | |
848 | p->bad_octets_received += read_mib(mp, 0x08); | |
849 | p->internal_mac_transmit_err += read_mib(mp, 0x0c); | |
850 | p->good_frames_received += read_mib(mp, 0x10); | |
851 | p->bad_frames_received += read_mib(mp, 0x14); | |
852 | p->broadcast_frames_received += read_mib(mp, 0x18); | |
853 | p->multicast_frames_received += read_mib(mp, 0x1c); | |
854 | p->frames_64_octets += read_mib(mp, 0x20); | |
855 | p->frames_65_to_127_octets += read_mib(mp, 0x24); | |
856 | p->frames_128_to_255_octets += read_mib(mp, 0x28); | |
857 | p->frames_256_to_511_octets += read_mib(mp, 0x2c); | |
858 | p->frames_512_to_1023_octets += read_mib(mp, 0x30); | |
859 | p->frames_1024_to_max_octets += read_mib(mp, 0x34); | |
860 | p->good_octets_sent += read_mib(mp, 0x38); | |
861 | p->good_octets_sent += (u64)read_mib(mp, 0x3c) << 32; | |
862 | p->good_frames_sent += read_mib(mp, 0x40); | |
863 | p->excessive_collision += read_mib(mp, 0x44); | |
864 | p->multicast_frames_sent += read_mib(mp, 0x48); | |
865 | p->broadcast_frames_sent += read_mib(mp, 0x4c); | |
866 | p->unrec_mac_control_received += read_mib(mp, 0x50); | |
867 | p->fc_sent += read_mib(mp, 0x54); | |
868 | p->good_fc_received += read_mib(mp, 0x58); | |
869 | p->bad_fc_received += read_mib(mp, 0x5c); | |
870 | p->undersize_received += read_mib(mp, 0x60); | |
871 | p->fragments_received += read_mib(mp, 0x64); | |
872 | p->oversize_received += read_mib(mp, 0x68); | |
873 | p->jabber_received += read_mib(mp, 0x6c); | |
874 | p->mac_receive_error += read_mib(mp, 0x70); | |
875 | p->bad_crc_event += read_mib(mp, 0x74); | |
876 | p->collision += read_mib(mp, 0x78); | |
877 | p->late_collision += read_mib(mp, 0x7c); | |
d0412d96 JC |
878 | } |
879 | ||
c9df406f LB |
880 | |
881 | /* ethtool ******************************************************************/ | |
e5371493 | 882 | struct mv643xx_eth_stats { |
c9df406f LB |
883 | char stat_string[ETH_GSTRING_LEN]; |
884 | int sizeof_stat; | |
16820054 LB |
885 | int netdev_off; |
886 | int mp_off; | |
c9df406f LB |
887 | }; |
888 | ||
16820054 LB |
889 | #define SSTAT(m) \ |
890 | { #m, FIELD_SIZEOF(struct net_device_stats, m), \ | |
891 | offsetof(struct net_device, stats.m), -1 } | |
892 | ||
893 | #define MIBSTAT(m) \ | |
894 | { #m, FIELD_SIZEOF(struct mib_counters, m), \ | |
895 | -1, offsetof(struct mv643xx_eth_private, mib_counters.m) } | |
896 | ||
897 | static const struct mv643xx_eth_stats mv643xx_eth_stats[] = { | |
898 | SSTAT(rx_packets), | |
899 | SSTAT(tx_packets), | |
900 | SSTAT(rx_bytes), | |
901 | SSTAT(tx_bytes), | |
902 | SSTAT(rx_errors), | |
903 | SSTAT(tx_errors), | |
904 | SSTAT(rx_dropped), | |
905 | SSTAT(tx_dropped), | |
906 | MIBSTAT(good_octets_received), | |
907 | MIBSTAT(bad_octets_received), | |
908 | MIBSTAT(internal_mac_transmit_err), | |
909 | MIBSTAT(good_frames_received), | |
910 | MIBSTAT(bad_frames_received), | |
911 | MIBSTAT(broadcast_frames_received), | |
912 | MIBSTAT(multicast_frames_received), | |
913 | MIBSTAT(frames_64_octets), | |
914 | MIBSTAT(frames_65_to_127_octets), | |
915 | MIBSTAT(frames_128_to_255_octets), | |
916 | MIBSTAT(frames_256_to_511_octets), | |
917 | MIBSTAT(frames_512_to_1023_octets), | |
918 | MIBSTAT(frames_1024_to_max_octets), | |
919 | MIBSTAT(good_octets_sent), | |
920 | MIBSTAT(good_frames_sent), | |
921 | MIBSTAT(excessive_collision), | |
922 | MIBSTAT(multicast_frames_sent), | |
923 | MIBSTAT(broadcast_frames_sent), | |
924 | MIBSTAT(unrec_mac_control_received), | |
925 | MIBSTAT(fc_sent), | |
926 | MIBSTAT(good_fc_received), | |
927 | MIBSTAT(bad_fc_received), | |
928 | MIBSTAT(undersize_received), | |
929 | MIBSTAT(fragments_received), | |
930 | MIBSTAT(oversize_received), | |
931 | MIBSTAT(jabber_received), | |
932 | MIBSTAT(mac_receive_error), | |
933 | MIBSTAT(bad_crc_event), | |
934 | MIBSTAT(collision), | |
935 | MIBSTAT(late_collision), | |
c9df406f LB |
936 | }; |
937 | ||
e5371493 | 938 | static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
d0412d96 | 939 | { |
e5371493 | 940 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
d0412d96 JC |
941 | int err; |
942 | ||
943 | spin_lock_irq(&mp->lock); | |
944 | err = mii_ethtool_gset(&mp->mii, cmd); | |
945 | spin_unlock_irq(&mp->lock); | |
946 | ||
947 | /* The PHY may support 1000baseT_Half, but the mv643xx does not */ | |
948 | cmd->supported &= ~SUPPORTED_1000baseT_Half; | |
949 | cmd->advertising &= ~ADVERTISED_1000baseT_Half; | |
950 | ||
951 | return err; | |
952 | } | |
953 | ||
e5371493 | 954 | static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 | 955 | { |
e5371493 | 956 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
ab4384a6 DF |
957 | int err; |
958 | ||
c9df406f LB |
959 | spin_lock_irq(&mp->lock); |
960 | err = mii_ethtool_sset(&mp->mii, cmd); | |
961 | spin_unlock_irq(&mp->lock); | |
85cf572c | 962 | |
c9df406f LB |
963 | return err; |
964 | } | |
1da177e4 | 965 | |
e5371493 | 966 | static void mv643xx_eth_get_drvinfo(struct net_device *netdev, |
c9df406f LB |
967 | struct ethtool_drvinfo *drvinfo) |
968 | { | |
e5371493 LB |
969 | strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32); |
970 | strncpy(drvinfo->version, mv643xx_eth_driver_version, 32); | |
c9df406f LB |
971 | strncpy(drvinfo->fw_version, "N/A", 32); |
972 | strncpy(drvinfo->bus_info, "mv643xx", 32); | |
16820054 | 973 | drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats); |
c9df406f | 974 | } |
1da177e4 | 975 | |
c9df406f LB |
976 | static int mv643xx_eth_nway_restart(struct net_device *dev) |
977 | { | |
e5371493 | 978 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 979 | |
c9df406f LB |
980 | return mii_nway_restart(&mp->mii); |
981 | } | |
1da177e4 | 982 | |
c9df406f LB |
983 | static u32 mv643xx_eth_get_link(struct net_device *dev) |
984 | { | |
e5371493 | 985 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 986 | |
c9df406f LB |
987 | return mii_link_ok(&mp->mii); |
988 | } | |
1da177e4 | 989 | |
e5371493 | 990 | static void mv643xx_eth_get_strings(struct net_device *netdev, uint32_t stringset, |
c9df406f LB |
991 | uint8_t *data) |
992 | { | |
993 | int i; | |
1da177e4 | 994 | |
c9df406f LB |
995 | switch(stringset) { |
996 | case ETH_SS_STATS: | |
16820054 | 997 | for (i=0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { |
c9df406f | 998 | memcpy(data + i * ETH_GSTRING_LEN, |
16820054 | 999 | mv643xx_eth_stats[i].stat_string, |
e5371493 | 1000 | ETH_GSTRING_LEN); |
c9df406f LB |
1001 | } |
1002 | break; | |
1003 | } | |
1004 | } | |
1da177e4 | 1005 | |
e5371493 | 1006 | static void mv643xx_eth_get_ethtool_stats(struct net_device *netdev, |
c9df406f LB |
1007 | struct ethtool_stats *stats, uint64_t *data) |
1008 | { | |
e5371493 | 1009 | struct mv643xx_eth_private *mp = netdev->priv; |
c9df406f | 1010 | int i; |
1da177e4 | 1011 | |
cc9754b3 | 1012 | update_mib_counters(mp); |
1da177e4 | 1013 | |
16820054 LB |
1014 | for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { |
1015 | const struct mv643xx_eth_stats *stat; | |
1016 | void *p; | |
1017 | ||
1018 | stat = mv643xx_eth_stats + i; | |
1019 | ||
1020 | if (stat->netdev_off >= 0) | |
1021 | p = ((void *)mp->dev) + stat->netdev_off; | |
1022 | else | |
1023 | p = ((void *)mp) + stat->mp_off; | |
1024 | ||
1025 | data[i] = (stat->sizeof_stat == 8) ? | |
1026 | *(uint64_t *)p : *(uint32_t *)p; | |
1da177e4 | 1027 | } |
c9df406f | 1028 | } |
1da177e4 | 1029 | |
e5371493 | 1030 | static int mv643xx_eth_get_sset_count(struct net_device *netdev, int sset) |
c9df406f LB |
1031 | { |
1032 | switch (sset) { | |
1033 | case ETH_SS_STATS: | |
16820054 | 1034 | return ARRAY_SIZE(mv643xx_eth_stats); |
c9df406f LB |
1035 | default: |
1036 | return -EOPNOTSUPP; | |
1037 | } | |
1038 | } | |
1da177e4 | 1039 | |
e5371493 LB |
1040 | static const struct ethtool_ops mv643xx_eth_ethtool_ops = { |
1041 | .get_settings = mv643xx_eth_get_settings, | |
1042 | .set_settings = mv643xx_eth_set_settings, | |
1043 | .get_drvinfo = mv643xx_eth_get_drvinfo, | |
c9df406f LB |
1044 | .get_link = mv643xx_eth_get_link, |
1045 | .set_sg = ethtool_op_set_sg, | |
e5371493 LB |
1046 | .get_sset_count = mv643xx_eth_get_sset_count, |
1047 | .get_ethtool_stats = mv643xx_eth_get_ethtool_stats, | |
1048 | .get_strings = mv643xx_eth_get_strings, | |
c9df406f LB |
1049 | .nway_reset = mv643xx_eth_nway_restart, |
1050 | }; | |
1da177e4 | 1051 | |
bea3348e | 1052 | |
c9df406f | 1053 | /* address handling *********************************************************/ |
5daffe94 | 1054 | static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr) |
c9df406f LB |
1055 | { |
1056 | unsigned int port_num = mp->port_num; | |
1057 | unsigned int mac_h; | |
1058 | unsigned int mac_l; | |
1da177e4 | 1059 | |
c9df406f LB |
1060 | mac_h = rdl(mp, MAC_ADDR_HIGH(port_num)); |
1061 | mac_l = rdl(mp, MAC_ADDR_LOW(port_num)); | |
1da177e4 | 1062 | |
5daffe94 LB |
1063 | addr[0] = (mac_h >> 24) & 0xff; |
1064 | addr[1] = (mac_h >> 16) & 0xff; | |
1065 | addr[2] = (mac_h >> 8) & 0xff; | |
1066 | addr[3] = mac_h & 0xff; | |
1067 | addr[4] = (mac_l >> 8) & 0xff; | |
1068 | addr[5] = mac_l & 0xff; | |
c9df406f | 1069 | } |
1da177e4 | 1070 | |
e5371493 | 1071 | static void init_mac_tables(struct mv643xx_eth_private *mp) |
c9df406f LB |
1072 | { |
1073 | unsigned int port_num = mp->port_num; | |
1074 | int table_index; | |
1da177e4 | 1075 | |
c9df406f LB |
1076 | /* Clear DA filter unicast table (Ex_dFUT) */ |
1077 | for (table_index = 0; table_index <= 0xC; table_index += 4) | |
3cb4667c | 1078 | wrl(mp, UNICAST_TABLE(port_num) + table_index, 0); |
1da177e4 | 1079 | |
c9df406f LB |
1080 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { |
1081 | /* Clear DA filter special multicast table (Ex_dFSMT) */ | |
3cb4667c | 1082 | wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0); |
c9df406f | 1083 | /* Clear DA filter other multicast table (Ex_dFOMT) */ |
3cb4667c | 1084 | wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0); |
c9df406f LB |
1085 | } |
1086 | } | |
d0412d96 | 1087 | |
e5371493 | 1088 | static void set_filter_table_entry(struct mv643xx_eth_private *mp, |
c9df406f LB |
1089 | int table, unsigned char entry) |
1090 | { | |
1091 | unsigned int table_reg; | |
1092 | unsigned int tbl_offset; | |
1093 | unsigned int reg_offset; | |
ab4384a6 | 1094 | |
c9df406f LB |
1095 | tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */ |
1096 | reg_offset = entry % 4; /* Entry offset within the register */ | |
ab4384a6 | 1097 | |
c9df406f LB |
1098 | /* Set "accepts frame bit" at specified table entry */ |
1099 | table_reg = rdl(mp, table + tbl_offset); | |
1100 | table_reg |= 0x01 << (8 * reg_offset); | |
1101 | wrl(mp, table + tbl_offset, table_reg); | |
1da177e4 LT |
1102 | } |
1103 | ||
5daffe94 | 1104 | static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr) |
1da177e4 | 1105 | { |
c9df406f LB |
1106 | unsigned int port_num = mp->port_num; |
1107 | unsigned int mac_h; | |
1108 | unsigned int mac_l; | |
1109 | int table; | |
1da177e4 | 1110 | |
5daffe94 LB |
1111 | mac_l = (addr[4] << 8) | (addr[5]); |
1112 | mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | | |
1113 | (addr[3] << 0); | |
ff561eef | 1114 | |
c9df406f LB |
1115 | wrl(mp, MAC_ADDR_LOW(port_num), mac_l); |
1116 | wrl(mp, MAC_ADDR_HIGH(port_num), mac_h); | |
1da177e4 | 1117 | |
c9df406f | 1118 | /* Accept frames with this address */ |
3cb4667c | 1119 | table = UNICAST_TABLE(port_num); |
5daffe94 | 1120 | set_filter_table_entry(mp, table, addr[5] & 0x0f); |
1da177e4 LT |
1121 | } |
1122 | ||
c9df406f | 1123 | static void mv643xx_eth_update_mac_address(struct net_device *dev) |
1da177e4 | 1124 | { |
e5371493 | 1125 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 1126 | |
cc9754b3 LB |
1127 | init_mac_tables(mp); |
1128 | uc_addr_set(mp, dev->dev_addr); | |
c9df406f | 1129 | } |
1da177e4 | 1130 | |
c9df406f | 1131 | static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr) |
1da177e4 | 1132 | { |
c9df406f | 1133 | int i; |
1da177e4 | 1134 | |
c9df406f LB |
1135 | for (i = 0; i < 6; i++) |
1136 | /* +2 is for the offset of the HW addr type */ | |
1137 | dev->dev_addr[i] = ((unsigned char *)addr)[i + 2]; | |
1138 | mv643xx_eth_update_mac_address(dev); | |
1da177e4 LT |
1139 | return 0; |
1140 | } | |
1141 | ||
69876569 LB |
1142 | static int addr_crc(unsigned char *addr) |
1143 | { | |
1144 | int crc = 0; | |
1145 | int i; | |
1146 | ||
1147 | for (i = 0; i < 6; i++) { | |
1148 | int j; | |
1149 | ||
1150 | crc = (crc ^ addr[i]) << 8; | |
1151 | for (j = 7; j >= 0; j--) { | |
1152 | if (crc & (0x100 << j)) | |
1153 | crc ^= 0x107 << j; | |
1154 | } | |
1155 | } | |
1156 | ||
1157 | return crc; | |
1158 | } | |
1159 | ||
5daffe94 | 1160 | static void mc_addr(struct mv643xx_eth_private *mp, unsigned char *addr) |
1da177e4 | 1161 | { |
1da177e4 | 1162 | unsigned int port_num = mp->port_num; |
c9df406f | 1163 | int table; |
69876569 | 1164 | int crc; |
1da177e4 | 1165 | |
5daffe94 LB |
1166 | if ((addr[0] == 0x01) && (addr[1] == 0x00) && |
1167 | (addr[2] == 0x5E) && (addr[3] == 0x00) && (addr[4] == 0x00)) { | |
3cb4667c | 1168 | table = SPECIAL_MCAST_TABLE(port_num); |
5daffe94 | 1169 | set_filter_table_entry(mp, table, addr[5]); |
c9df406f | 1170 | return; |
1da177e4 | 1171 | } |
1da177e4 | 1172 | |
69876569 | 1173 | crc = addr_crc(addr); |
c9df406f | 1174 | |
3cb4667c | 1175 | table = OTHER_MCAST_TABLE(port_num); |
69876569 | 1176 | set_filter_table_entry(mp, table, crc); |
c8aaea25 DF |
1177 | } |
1178 | ||
cc9754b3 | 1179 | static void set_multicast_list(struct net_device *dev) |
1da177e4 | 1180 | { |
1da177e4 | 1181 | |
c9df406f LB |
1182 | struct dev_mc_list *mc_list; |
1183 | int i; | |
1184 | int table_index; | |
e5371493 | 1185 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
cc9754b3 | 1186 | unsigned int port_num = mp->port_num; |
c8aaea25 | 1187 | |
c9df406f LB |
1188 | /* If the device is in promiscuous mode or in all multicast mode, |
1189 | * we will fully populate both multicast tables with accept. | |
1190 | * This is guaranteed to yield a match on all multicast addresses... | |
1191 | */ | |
1192 | if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) { | |
1193 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { | |
1194 | /* Set all entries in DA filter special multicast | |
1195 | * table (Ex_dFSMT) | |
1196 | * Set for ETH_Q0 for now | |
1197 | * Bits | |
1198 | * 0 Accept=1, Drop=0 | |
1199 | * 3-1 Queue ETH_Q0=0 | |
1200 | * 7-4 Reserved = 0; | |
1201 | */ | |
cc9754b3 | 1202 | wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0x01010101); |
c8aaea25 | 1203 | |
c9df406f LB |
1204 | /* Set all entries in DA filter other multicast |
1205 | * table (Ex_dFOMT) | |
1206 | * Set for ETH_Q0 for now | |
1207 | * Bits | |
1208 | * 0 Accept=1, Drop=0 | |
1209 | * 3-1 Queue ETH_Q0=0 | |
1210 | * 7-4 Reserved = 0; | |
1211 | */ | |
cc9754b3 | 1212 | wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0x01010101); |
c9df406f LB |
1213 | } |
1214 | return; | |
1215 | } | |
c8aaea25 | 1216 | |
c9df406f LB |
1217 | /* We will clear out multicast tables every time we get the list. |
1218 | * Then add the entire new list... | |
1219 | */ | |
1220 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { | |
1221 | /* Clear DA filter special multicast table (Ex_dFSMT) */ | |
cc9754b3 | 1222 | wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0); |
c9df406f LB |
1223 | |
1224 | /* Clear DA filter other multicast table (Ex_dFOMT) */ | |
cc9754b3 | 1225 | wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0); |
1da177e4 LT |
1226 | } |
1227 | ||
c9df406f LB |
1228 | /* Get pointer to net_device multicast list and add each one... */ |
1229 | for (i = 0, mc_list = dev->mc_list; | |
1230 | (i < 256) && (mc_list != NULL) && (i < dev->mc_count); | |
1231 | i++, mc_list = mc_list->next) | |
1232 | if (mc_list->dmi_addrlen == 6) | |
cc9754b3 | 1233 | mc_addr(mp, mc_list->dmi_addr); |
324ff2c1 BB |
1234 | } |
1235 | ||
c9df406f | 1236 | static void mv643xx_eth_set_rx_mode(struct net_device *dev) |
c8aaea25 | 1237 | { |
e5371493 | 1238 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f | 1239 | u32 config_reg; |
1da177e4 | 1240 | |
3cb4667c | 1241 | config_reg = rdl(mp, PORT_CONFIG(mp->port_num)); |
c9df406f | 1242 | if (dev->flags & IFF_PROMISC) |
d9a073ea | 1243 | config_reg |= UNICAST_PROMISCUOUS_MODE; |
c9df406f | 1244 | else |
d9a073ea | 1245 | config_reg &= ~UNICAST_PROMISCUOUS_MODE; |
3cb4667c | 1246 | wrl(mp, PORT_CONFIG(mp->port_num), config_reg); |
1da177e4 | 1247 | |
cc9754b3 | 1248 | set_multicast_list(dev); |
c9df406f | 1249 | } |
c8aaea25 | 1250 | |
c8aaea25 | 1251 | |
c9df406f | 1252 | /* rx/tx queue initialisation ***********************************************/ |
8a578111 | 1253 | static int rxq_init(struct mv643xx_eth_private *mp) |
c9df406f | 1254 | { |
8a578111 LB |
1255 | struct rx_queue *rxq = mp->rxq; |
1256 | struct rx_desc *rx_desc; | |
1257 | int size; | |
c9df406f LB |
1258 | int i; |
1259 | ||
8a578111 LB |
1260 | rxq->rx_ring_size = mp->default_rx_ring_size; |
1261 | ||
1262 | rxq->rx_desc_count = 0; | |
1263 | rxq->rx_curr_desc = 0; | |
1264 | rxq->rx_used_desc = 0; | |
1265 | ||
1266 | size = rxq->rx_ring_size * sizeof(struct rx_desc); | |
1267 | ||
1268 | if (size <= mp->rx_desc_sram_size) { | |
1269 | rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr, | |
1270 | mp->rx_desc_sram_size); | |
1271 | rxq->rx_desc_dma = mp->rx_desc_sram_addr; | |
1272 | } else { | |
1273 | rxq->rx_desc_area = dma_alloc_coherent(NULL, size, | |
1274 | &rxq->rx_desc_dma, | |
1275 | GFP_KERNEL); | |
f7ea3337 PJ |
1276 | } |
1277 | ||
8a578111 LB |
1278 | if (rxq->rx_desc_area == NULL) { |
1279 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1280 | "can't allocate rx ring (%d bytes)\n", size); | |
1281 | goto out; | |
1282 | } | |
1283 | memset(rxq->rx_desc_area, 0, size); | |
1da177e4 | 1284 | |
8a578111 LB |
1285 | rxq->rx_desc_area_size = size; |
1286 | rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb), | |
1287 | GFP_KERNEL); | |
1288 | if (rxq->rx_skb == NULL) { | |
1289 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1290 | "can't allocate rx skb ring\n"); | |
1291 | goto out_free; | |
1292 | } | |
1293 | ||
1294 | rx_desc = (struct rx_desc *)rxq->rx_desc_area; | |
1295 | for (i = 0; i < rxq->rx_ring_size; i++) { | |
1296 | int nexti = (i + 1) % rxq->rx_ring_size; | |
1297 | rx_desc[i].next_desc_ptr = rxq->rx_desc_dma + | |
1298 | nexti * sizeof(struct rx_desc); | |
1299 | } | |
1300 | ||
1301 | init_timer(&rxq->rx_oom); | |
1302 | rxq->rx_oom.data = (unsigned long)rxq; | |
1303 | rxq->rx_oom.function = rxq_refill_timer_wrapper; | |
1304 | ||
1305 | return 0; | |
1306 | ||
1307 | ||
1308 | out_free: | |
1309 | if (size <= mp->rx_desc_sram_size) | |
1310 | iounmap(rxq->rx_desc_area); | |
1311 | else | |
1312 | dma_free_coherent(NULL, size, | |
1313 | rxq->rx_desc_area, | |
1314 | rxq->rx_desc_dma); | |
1315 | ||
1316 | out: | |
1317 | return -ENOMEM; | |
c9df406f | 1318 | } |
c8aaea25 | 1319 | |
8a578111 | 1320 | static void rxq_deinit(struct rx_queue *rxq) |
c9df406f | 1321 | { |
8a578111 LB |
1322 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
1323 | int i; | |
1324 | ||
1325 | rxq_disable(rxq); | |
c8aaea25 | 1326 | |
8a578111 | 1327 | del_timer_sync(&rxq->rx_oom); |
c9df406f | 1328 | |
8a578111 LB |
1329 | for (i = 0; i < rxq->rx_ring_size; i++) { |
1330 | if (rxq->rx_skb[i]) { | |
1331 | dev_kfree_skb(rxq->rx_skb[i]); | |
1332 | rxq->rx_desc_count--; | |
1da177e4 | 1333 | } |
c8aaea25 | 1334 | } |
1da177e4 | 1335 | |
8a578111 LB |
1336 | if (rxq->rx_desc_count) { |
1337 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1338 | "error freeing rx ring -- %d skbs stuck\n", | |
1339 | rxq->rx_desc_count); | |
1340 | } | |
1341 | ||
1342 | if (rxq->rx_desc_area_size <= mp->rx_desc_sram_size) | |
1343 | iounmap(rxq->rx_desc_area); | |
c9df406f | 1344 | else |
8a578111 LB |
1345 | dma_free_coherent(NULL, rxq->rx_desc_area_size, |
1346 | rxq->rx_desc_area, rxq->rx_desc_dma); | |
1347 | ||
1348 | kfree(rxq->rx_skb); | |
c9df406f | 1349 | } |
1da177e4 | 1350 | |
13d64285 | 1351 | static int txq_init(struct mv643xx_eth_private *mp) |
c9df406f | 1352 | { |
13d64285 LB |
1353 | struct tx_queue *txq = mp->txq; |
1354 | struct tx_desc *tx_desc; | |
1355 | int size; | |
c9df406f | 1356 | int i; |
1da177e4 | 1357 | |
13d64285 LB |
1358 | txq->tx_ring_size = mp->default_tx_ring_size; |
1359 | ||
1360 | txq->tx_desc_count = 0; | |
1361 | txq->tx_curr_desc = 0; | |
1362 | txq->tx_used_desc = 0; | |
1363 | ||
1364 | size = txq->tx_ring_size * sizeof(struct tx_desc); | |
1365 | ||
1366 | if (size <= mp->tx_desc_sram_size) { | |
1367 | txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr, | |
1368 | mp->tx_desc_sram_size); | |
1369 | txq->tx_desc_dma = mp->tx_desc_sram_addr; | |
1370 | } else { | |
1371 | txq->tx_desc_area = dma_alloc_coherent(NULL, size, | |
1372 | &txq->tx_desc_dma, | |
1373 | GFP_KERNEL); | |
1374 | } | |
1375 | ||
1376 | if (txq->tx_desc_area == NULL) { | |
1377 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1378 | "can't allocate tx ring (%d bytes)\n", size); | |
1379 | goto out; | |
c9df406f | 1380 | } |
13d64285 LB |
1381 | memset(txq->tx_desc_area, 0, size); |
1382 | ||
1383 | txq->tx_desc_area_size = size; | |
1384 | txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb), | |
1385 | GFP_KERNEL); | |
1386 | if (txq->tx_skb == NULL) { | |
1387 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1388 | "can't allocate tx skb ring\n"); | |
1389 | goto out_free; | |
1390 | } | |
1391 | ||
1392 | tx_desc = (struct tx_desc *)txq->tx_desc_area; | |
1393 | for (i = 0; i < txq->tx_ring_size; i++) { | |
1394 | int nexti = (i + 1) % txq->tx_ring_size; | |
1395 | tx_desc[i].next_desc_ptr = txq->tx_desc_dma + | |
1396 | nexti * sizeof(struct tx_desc); | |
1397 | } | |
1398 | ||
1399 | return 0; | |
1400 | ||
c9df406f | 1401 | |
13d64285 LB |
1402 | out_free: |
1403 | if (size <= mp->tx_desc_sram_size) | |
1404 | iounmap(txq->tx_desc_area); | |
1405 | else | |
1406 | dma_free_coherent(NULL, size, | |
1407 | txq->tx_desc_area, | |
1408 | txq->tx_desc_dma); | |
c9df406f | 1409 | |
13d64285 LB |
1410 | out: |
1411 | return -ENOMEM; | |
c8aaea25 | 1412 | } |
1da177e4 | 1413 | |
13d64285 | 1414 | static void txq_reclaim(struct tx_queue *txq, int force) |
c8aaea25 | 1415 | { |
13d64285 | 1416 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
c8aaea25 | 1417 | unsigned long flags; |
1da177e4 | 1418 | |
13d64285 LB |
1419 | spin_lock_irqsave(&mp->lock, flags); |
1420 | while (txq->tx_desc_count > 0) { | |
1421 | int tx_index; | |
1422 | struct tx_desc *desc; | |
1423 | u32 cmd_sts; | |
1424 | struct sk_buff *skb; | |
1425 | dma_addr_t addr; | |
1426 | int count; | |
4d64e718 | 1427 | |
13d64285 LB |
1428 | tx_index = txq->tx_used_desc; |
1429 | desc = &txq->tx_desc_area[tx_index]; | |
c9df406f | 1430 | cmd_sts = desc->cmd_sts; |
4d64e718 | 1431 | |
13d64285 LB |
1432 | if (!force && (cmd_sts & BUFFER_OWNED_BY_DMA)) |
1433 | break; | |
1da177e4 | 1434 | |
13d64285 LB |
1435 | txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size; |
1436 | txq->tx_desc_count--; | |
1da177e4 | 1437 | |
c9df406f LB |
1438 | addr = desc->buf_ptr; |
1439 | count = desc->byte_cnt; | |
13d64285 LB |
1440 | skb = txq->tx_skb[tx_index]; |
1441 | txq->tx_skb[tx_index] = NULL; | |
c8aaea25 | 1442 | |
cc9754b3 | 1443 | if (cmd_sts & ERROR_SUMMARY) { |
13d64285 LB |
1444 | dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n"); |
1445 | mp->dev->stats.tx_errors++; | |
c9df406f | 1446 | } |
1da177e4 | 1447 | |
13d64285 LB |
1448 | /* |
1449 | * Drop mp->lock while we free the skb. | |
1450 | */ | |
c9df406f | 1451 | spin_unlock_irqrestore(&mp->lock, flags); |
1da177e4 | 1452 | |
cc9754b3 | 1453 | if (cmd_sts & TX_FIRST_DESC) |
c9df406f LB |
1454 | dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE); |
1455 | else | |
1456 | dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE); | |
c2e5b352 | 1457 | |
c9df406f LB |
1458 | if (skb) |
1459 | dev_kfree_skb_irq(skb); | |
63c9e549 | 1460 | |
13d64285 | 1461 | spin_lock_irqsave(&mp->lock, flags); |
c9df406f | 1462 | } |
13d64285 | 1463 | spin_unlock_irqrestore(&mp->lock, flags); |
c9df406f | 1464 | } |
1da177e4 | 1465 | |
13d64285 | 1466 | static void txq_deinit(struct tx_queue *txq) |
c9df406f | 1467 | { |
13d64285 | 1468 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
fa3959f4 | 1469 | |
13d64285 LB |
1470 | txq_disable(txq); |
1471 | txq_reclaim(txq, 1); | |
1da177e4 | 1472 | |
13d64285 | 1473 | BUG_ON(txq->tx_used_desc != txq->tx_curr_desc); |
1da177e4 | 1474 | |
13d64285 LB |
1475 | if (txq->tx_desc_area_size <= mp->tx_desc_sram_size) |
1476 | iounmap(txq->tx_desc_area); | |
c9df406f | 1477 | else |
13d64285 LB |
1478 | dma_free_coherent(NULL, txq->tx_desc_area_size, |
1479 | txq->tx_desc_area, txq->tx_desc_dma); | |
1480 | ||
1481 | kfree(txq->tx_skb); | |
c9df406f | 1482 | } |
1da177e4 | 1483 | |
1da177e4 | 1484 | |
c9df406f | 1485 | /* netdev ops and related ***************************************************/ |
e5371493 | 1486 | static void port_reset(struct mv643xx_eth_private *mp); |
1da177e4 | 1487 | |
13d64285 | 1488 | static void mv643xx_eth_update_pscr(struct mv643xx_eth_private *mp, |
c9df406f LB |
1489 | struct ethtool_cmd *ecmd) |
1490 | { | |
13d64285 LB |
1491 | u32 pscr_o; |
1492 | u32 pscr_n; | |
1da177e4 | 1493 | |
13d64285 | 1494 | pscr_o = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num)); |
63c9e549 | 1495 | |
c9df406f | 1496 | /* clear speed, duplex and rx buffer size fields */ |
13d64285 LB |
1497 | pscr_n = pscr_o & ~(SET_MII_SPEED_TO_100 | |
1498 | SET_GMII_SPEED_TO_1000 | | |
1499 | SET_FULL_DUPLEX_MODE | | |
1500 | MAX_RX_PACKET_MASK); | |
1da177e4 | 1501 | |
13d64285 LB |
1502 | if (ecmd->speed == SPEED_1000) { |
1503 | pscr_n |= SET_GMII_SPEED_TO_1000 | MAX_RX_PACKET_9700BYTE; | |
1504 | } else { | |
c9df406f | 1505 | if (ecmd->speed == SPEED_100) |
13d64285 LB |
1506 | pscr_n |= SET_MII_SPEED_TO_100; |
1507 | pscr_n |= MAX_RX_PACKET_1522BYTE; | |
c9df406f | 1508 | } |
1da177e4 | 1509 | |
13d64285 LB |
1510 | if (ecmd->duplex == DUPLEX_FULL) |
1511 | pscr_n |= SET_FULL_DUPLEX_MODE; | |
1512 | ||
1513 | if (pscr_n != pscr_o) { | |
1514 | if ((pscr_o & SERIAL_PORT_ENABLE) == 0) | |
1515 | wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n); | |
c9df406f | 1516 | else { |
13d64285 LB |
1517 | txq_disable(mp->txq); |
1518 | pscr_o &= ~SERIAL_PORT_ENABLE; | |
1519 | wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_o); | |
1520 | wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n); | |
1521 | wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n); | |
1522 | txq_enable(mp->txq); | |
c9df406f LB |
1523 | } |
1524 | } | |
1525 | } | |
84dd619e | 1526 | |
c9df406f LB |
1527 | static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id) |
1528 | { | |
1529 | struct net_device *dev = (struct net_device *)dev_id; | |
e5371493 | 1530 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
cc9754b3 | 1531 | u32 int_cause, int_cause_ext = 0; |
ce4e2e45 | 1532 | |
c9df406f | 1533 | /* Read interrupt cause registers */ |
13d64285 | 1534 | int_cause = rdl(mp, INT_CAUSE(mp->port_num)) & (INT_RX | INT_EXT); |
cc9754b3 | 1535 | if (int_cause & INT_EXT) { |
13d64285 | 1536 | int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num)) |
073a345c | 1537 | & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX); |
13d64285 | 1538 | wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext); |
c9df406f | 1539 | } |
1da177e4 | 1540 | |
c9df406f | 1541 | /* PHY status changed */ |
cc9754b3 | 1542 | if (int_cause_ext & (INT_EXT_LINK | INT_EXT_PHY)) { |
c9df406f | 1543 | if (mii_link_ok(&mp->mii)) { |
13d64285 LB |
1544 | struct ethtool_cmd cmd; |
1545 | ||
c9df406f | 1546 | mii_ethtool_gset(&mp->mii, &cmd); |
13d64285 LB |
1547 | mv643xx_eth_update_pscr(mp, &cmd); |
1548 | txq_enable(mp->txq); | |
c9df406f LB |
1549 | if (!netif_carrier_ok(dev)) { |
1550 | netif_carrier_on(dev); | |
13d64285 | 1551 | __txq_maybe_wake(mp->txq); |
c9df406f LB |
1552 | } |
1553 | } else if (netif_carrier_ok(dev)) { | |
1554 | netif_stop_queue(dev); | |
1555 | netif_carrier_off(dev); | |
1556 | } | |
1557 | } | |
1da177e4 | 1558 | |
e5371493 | 1559 | #ifdef MV643XX_ETH_NAPI |
cc9754b3 | 1560 | if (int_cause & INT_RX) { |
c9df406f | 1561 | /* schedule the NAPI poll routine to maintain port */ |
13d64285 | 1562 | wrl(mp, INT_MASK(mp->port_num), 0x00000000); |
1da177e4 | 1563 | |
c9df406f | 1564 | /* wait for previous write to complete */ |
13d64285 | 1565 | rdl(mp, INT_MASK(mp->port_num)); |
1da177e4 | 1566 | |
c9df406f | 1567 | netif_rx_schedule(dev, &mp->napi); |
84dd619e | 1568 | } |
c9df406f | 1569 | #else |
cc9754b3 | 1570 | if (int_cause & INT_RX) |
8a578111 | 1571 | rxq_process(mp->rxq, INT_MAX); |
c9df406f | 1572 | #endif |
13d64285 LB |
1573 | if (int_cause_ext & INT_EXT_TX) { |
1574 | txq_reclaim(mp->txq, 0); | |
1575 | __txq_maybe_wake(mp->txq); | |
1576 | } | |
1da177e4 | 1577 | |
f2ce825d | 1578 | /* |
c9df406f LB |
1579 | * If no real interrupt occured, exit. |
1580 | * This can happen when using gigE interrupt coalescing mechanism. | |
f2ce825d | 1581 | */ |
cc9754b3 | 1582 | if ((int_cause == 0x0) && (int_cause_ext == 0x0)) |
c9df406f | 1583 | return IRQ_NONE; |
1da177e4 | 1584 | |
c9df406f | 1585 | return IRQ_HANDLED; |
1da177e4 LT |
1586 | } |
1587 | ||
e5371493 | 1588 | static void phy_reset(struct mv643xx_eth_private *mp) |
1da177e4 | 1589 | { |
c9df406f | 1590 | unsigned int phy_reg_data; |
1da177e4 | 1591 | |
c9df406f | 1592 | /* Reset the PHY */ |
cc9754b3 | 1593 | read_smi_reg(mp, 0, &phy_reg_data); |
c9df406f | 1594 | phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */ |
cc9754b3 | 1595 | write_smi_reg(mp, 0, phy_reg_data); |
1da177e4 | 1596 | |
c9df406f LB |
1597 | /* wait for PHY to come out of reset */ |
1598 | do { | |
1599 | udelay(1); | |
cc9754b3 | 1600 | read_smi_reg(mp, 0, &phy_reg_data); |
c9df406f | 1601 | } while (phy_reg_data & 0x8000); |
1da177e4 LT |
1602 | } |
1603 | ||
cc9754b3 | 1604 | static void port_start(struct net_device *dev) |
1da177e4 | 1605 | { |
e5371493 | 1606 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
d0412d96 JC |
1607 | u32 pscr; |
1608 | struct ethtool_cmd ethtool_cmd; | |
8a578111 | 1609 | int i; |
1da177e4 | 1610 | |
8a578111 LB |
1611 | /* |
1612 | * Configure basic link parameters. | |
1613 | */ | |
1614 | pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num)); | |
1615 | pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS); | |
1616 | wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr); | |
1617 | pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL | | |
1618 | DISABLE_AUTO_NEG_SPEED_GMII | | |
1619 | DISABLE_AUTO_NEG_FOR_DUPLEX | | |
1620 | DO_NOT_FORCE_LINK_FAIL | | |
1621 | SERIAL_PORT_CONTROL_RESERVED; | |
1622 | wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr); | |
1623 | pscr |= SERIAL_PORT_ENABLE; | |
1624 | wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr); | |
1da177e4 | 1625 | |
8a578111 LB |
1626 | wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE); |
1627 | ||
1628 | mv643xx_eth_get_settings(dev, ðtool_cmd); | |
1629 | phy_reset(mp); | |
1630 | mv643xx_eth_set_settings(dev, ðtool_cmd); | |
1da177e4 | 1631 | |
13d64285 LB |
1632 | /* |
1633 | * Configure TX path and queues. | |
1634 | */ | |
1635 | wrl(mp, TX_BW_MTU(mp->port_num), 0); | |
1636 | for (i = 0; i < 1; i++) { | |
1637 | struct tx_queue *txq = mp->txq; | |
1638 | int off = TXQ_CURRENT_DESC_PTR(mp->port_num); | |
1639 | u32 addr; | |
1640 | ||
1641 | addr = (u32)txq->tx_desc_dma; | |
1642 | addr += txq->tx_curr_desc * sizeof(struct tx_desc); | |
1643 | wrl(mp, off, addr); | |
1644 | } | |
1645 | ||
1da177e4 | 1646 | /* Add the assigned Ethernet address to the port's address table */ |
cc9754b3 | 1647 | uc_addr_set(mp, dev->dev_addr); |
1da177e4 | 1648 | |
d9a073ea LB |
1649 | /* |
1650 | * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast | |
1651 | * frames to RX queue #0. | |
1652 | */ | |
8a578111 | 1653 | wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000); |
01999873 | 1654 | |
376489a2 LB |
1655 | /* |
1656 | * Treat BPDUs as normal multicasts, and disable partition mode. | |
1657 | */ | |
8a578111 | 1658 | wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000); |
01999873 | 1659 | |
8a578111 LB |
1660 | /* |
1661 | * Enable the receive queue. | |
1662 | */ | |
1663 | for (i = 0; i < 1; i++) { | |
1664 | struct rx_queue *rxq = mp->rxq; | |
1665 | int off = RXQ_CURRENT_DESC_PTR(mp->port_num); | |
1666 | u32 addr; | |
1da177e4 | 1667 | |
8a578111 LB |
1668 | addr = (u32)rxq->rx_desc_dma; |
1669 | addr += rxq->rx_curr_desc * sizeof(struct rx_desc); | |
1670 | wrl(mp, off, addr); | |
1da177e4 | 1671 | |
8a578111 LB |
1672 | rxq_enable(rxq); |
1673 | } | |
1da177e4 LT |
1674 | } |
1675 | ||
ffd86bbe | 1676 | static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay) |
1da177e4 | 1677 | { |
afdb57a2 | 1678 | unsigned int port_num = mp->port_num; |
c9df406f | 1679 | unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64; |
1da177e4 | 1680 | |
c9df406f | 1681 | /* Set RX Coalescing mechanism */ |
3cb4667c | 1682 | wrl(mp, SDMA_CONFIG(port_num), |
c9df406f | 1683 | ((coal & 0x3fff) << 8) | |
3cb4667c | 1684 | (rdl(mp, SDMA_CONFIG(port_num)) |
c9df406f | 1685 | & 0xffc000ff)); |
1da177e4 LT |
1686 | } |
1687 | ||
ffd86bbe | 1688 | static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay) |
1da177e4 | 1689 | { |
c9df406f | 1690 | unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64; |
1da177e4 | 1691 | |
c9df406f | 1692 | /* Set TX Coalescing mechanism */ |
3cb4667c | 1693 | wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), coal << 4); |
1da177e4 LT |
1694 | } |
1695 | ||
e5371493 | 1696 | static void port_init(struct mv643xx_eth_private *mp) |
16e03018 | 1697 | { |
cc9754b3 | 1698 | port_reset(mp); |
16e03018 | 1699 | |
cc9754b3 | 1700 | init_mac_tables(mp); |
16e03018 DF |
1701 | } |
1702 | ||
c9df406f | 1703 | static int mv643xx_eth_open(struct net_device *dev) |
16e03018 | 1704 | { |
e5371493 | 1705 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
afdb57a2 | 1706 | unsigned int port_num = mp->port_num; |
c9df406f | 1707 | int err; |
16e03018 | 1708 | |
c9df406f | 1709 | /* Clear any pending ethernet port interrupts */ |
3cb4667c LB |
1710 | wrl(mp, INT_CAUSE(port_num), 0); |
1711 | wrl(mp, INT_CAUSE_EXT(port_num), 0); | |
c9df406f | 1712 | /* wait for previous write to complete */ |
3cb4667c | 1713 | rdl(mp, INT_CAUSE_EXT(port_num)); |
c9df406f LB |
1714 | |
1715 | err = request_irq(dev->irq, mv643xx_eth_int_handler, | |
1716 | IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev); | |
1717 | if (err) { | |
1718 | printk(KERN_ERR "%s: Can not assign IRQ\n", dev->name); | |
1719 | return -EAGAIN; | |
16e03018 DF |
1720 | } |
1721 | ||
cc9754b3 | 1722 | port_init(mp); |
16e03018 | 1723 | |
8a578111 LB |
1724 | err = rxq_init(mp); |
1725 | if (err) | |
c9df406f | 1726 | goto out_free_irq; |
8a578111 LB |
1727 | rxq_refill(mp->rxq); |
1728 | ||
13d64285 LB |
1729 | err = txq_init(mp); |
1730 | if (err) | |
c9df406f | 1731 | goto out_free_rx_skb; |
16e03018 | 1732 | |
e5371493 | 1733 | #ifdef MV643XX_ETH_NAPI |
c9df406f LB |
1734 | napi_enable(&mp->napi); |
1735 | #endif | |
16e03018 | 1736 | |
cc9754b3 | 1737 | port_start(dev); |
16e03018 | 1738 | |
ffd86bbe LB |
1739 | set_rx_coal(mp, 0); |
1740 | set_tx_coal(mp, 0); | |
16e03018 | 1741 | |
c9df406f | 1742 | /* Unmask phy and link status changes interrupts */ |
073a345c | 1743 | wrl(mp, INT_MASK_EXT(port_num), INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX); |
16e03018 | 1744 | |
c9df406f | 1745 | /* Unmask RX buffer and TX end interrupt */ |
073a345c | 1746 | wrl(mp, INT_MASK(port_num), INT_RX | INT_EXT); |
16e03018 | 1747 | |
c9df406f LB |
1748 | return 0; |
1749 | ||
13d64285 | 1750 | |
c9df406f | 1751 | out_free_rx_skb: |
8a578111 | 1752 | rxq_deinit(mp->rxq); |
c9df406f LB |
1753 | out_free_irq: |
1754 | free_irq(dev->irq, dev); | |
1755 | ||
1756 | return err; | |
16e03018 DF |
1757 | } |
1758 | ||
e5371493 | 1759 | static void port_reset(struct mv643xx_eth_private *mp) |
1da177e4 | 1760 | { |
afdb57a2 | 1761 | unsigned int port_num = mp->port_num; |
c9df406f | 1762 | unsigned int reg_data; |
1da177e4 | 1763 | |
13d64285 | 1764 | txq_disable(mp->txq); |
8a578111 | 1765 | rxq_disable(mp->rxq); |
13d64285 LB |
1766 | while (!(rdl(mp, PORT_STATUS(mp->port_num)) & TX_FIFO_EMPTY)) |
1767 | udelay(10); | |
1da177e4 | 1768 | |
c9df406f | 1769 | /* Clear all MIB counters */ |
cc9754b3 | 1770 | clear_mib_counters(mp); |
c9df406f LB |
1771 | |
1772 | /* Reset the Enable bit in the Configuration Register */ | |
3cb4667c | 1773 | reg_data = rdl(mp, PORT_SERIAL_CONTROL(port_num)); |
c9df406f LB |
1774 | reg_data &= ~(SERIAL_PORT_ENABLE | |
1775 | DO_NOT_FORCE_LINK_FAIL | | |
1776 | FORCE_LINK_PASS); | |
3cb4667c | 1777 | wrl(mp, PORT_SERIAL_CONTROL(port_num), reg_data); |
1da177e4 LT |
1778 | } |
1779 | ||
c9df406f | 1780 | static int mv643xx_eth_stop(struct net_device *dev) |
1da177e4 | 1781 | { |
e5371493 | 1782 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
afdb57a2 | 1783 | unsigned int port_num = mp->port_num; |
1da177e4 | 1784 | |
c9df406f | 1785 | /* Mask all interrupts on ethernet port */ |
073a345c | 1786 | wrl(mp, INT_MASK(port_num), 0x00000000); |
c9df406f | 1787 | /* wait for previous write to complete */ |
3cb4667c | 1788 | rdl(mp, INT_MASK(port_num)); |
1da177e4 | 1789 | |
e5371493 | 1790 | #ifdef MV643XX_ETH_NAPI |
c9df406f LB |
1791 | napi_disable(&mp->napi); |
1792 | #endif | |
1793 | netif_carrier_off(dev); | |
1794 | netif_stop_queue(dev); | |
1da177e4 | 1795 | |
cc9754b3 | 1796 | port_reset(mp); |
1da177e4 | 1797 | |
13d64285 | 1798 | txq_deinit(mp->txq); |
8a578111 | 1799 | rxq_deinit(mp->rxq); |
1da177e4 | 1800 | |
c9df406f | 1801 | free_irq(dev->irq, dev); |
1da177e4 | 1802 | |
c9df406f | 1803 | return 0; |
1da177e4 LT |
1804 | } |
1805 | ||
c9df406f | 1806 | static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
1da177e4 | 1807 | { |
e5371493 | 1808 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 1809 | |
c9df406f | 1810 | return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL); |
1da177e4 LT |
1811 | } |
1812 | ||
c9df406f | 1813 | static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu) |
1da177e4 | 1814 | { |
c9df406f LB |
1815 | if ((new_mtu > 9500) || (new_mtu < 64)) |
1816 | return -EINVAL; | |
1da177e4 | 1817 | |
c9df406f LB |
1818 | dev->mtu = new_mtu; |
1819 | if (!netif_running(dev)) | |
1820 | return 0; | |
1da177e4 | 1821 | |
c9df406f LB |
1822 | /* |
1823 | * Stop and then re-open the interface. This will allocate RX | |
1824 | * skbs of the new MTU. | |
1825 | * There is a possible danger that the open will not succeed, | |
1826 | * due to memory being full, which might fail the open function. | |
1827 | */ | |
1828 | mv643xx_eth_stop(dev); | |
1829 | if (mv643xx_eth_open(dev)) { | |
1830 | printk(KERN_ERR "%s: Fatal error on opening device\n", | |
1831 | dev->name); | |
1832 | } | |
1833 | ||
1834 | return 0; | |
1da177e4 LT |
1835 | } |
1836 | ||
c9df406f | 1837 | static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly) |
1da177e4 | 1838 | { |
e5371493 | 1839 | struct mv643xx_eth_private *mp = container_of(ugly, struct mv643xx_eth_private, |
c9df406f LB |
1840 | tx_timeout_task); |
1841 | struct net_device *dev = mp->dev; | |
1da177e4 | 1842 | |
c9df406f LB |
1843 | if (!netif_running(dev)) |
1844 | return; | |
1da177e4 | 1845 | |
c9df406f LB |
1846 | netif_stop_queue(dev); |
1847 | ||
cc9754b3 LB |
1848 | port_reset(mp); |
1849 | port_start(dev); | |
c9df406f | 1850 | |
13d64285 | 1851 | __txq_maybe_wake(mp->txq); |
c9df406f LB |
1852 | } |
1853 | ||
c9df406f | 1854 | static void mv643xx_eth_tx_timeout(struct net_device *dev) |
1da177e4 | 1855 | { |
e5371493 | 1856 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 1857 | |
c9df406f | 1858 | printk(KERN_INFO "%s: TX timeout ", dev->name); |
d0412d96 | 1859 | |
c9df406f LB |
1860 | /* Do the reset outside of interrupt context */ |
1861 | schedule_work(&mp->tx_timeout_task); | |
1da177e4 LT |
1862 | } |
1863 | ||
c9df406f | 1864 | #ifdef CONFIG_NET_POLL_CONTROLLER |
e5371493 | 1865 | static void mv643xx_eth_netpoll(struct net_device *netdev) |
9f8dd319 | 1866 | { |
e5371493 | 1867 | struct mv643xx_eth_private *mp = netdev_priv(netdev); |
c9df406f LB |
1868 | int port_num = mp->port_num; |
1869 | ||
073a345c | 1870 | wrl(mp, INT_MASK(port_num), 0x00000000); |
c9df406f | 1871 | /* wait for previous write to complete */ |
3cb4667c | 1872 | rdl(mp, INT_MASK(port_num)); |
c9df406f LB |
1873 | |
1874 | mv643xx_eth_int_handler(netdev->irq, netdev); | |
1875 | ||
073a345c | 1876 | wrl(mp, INT_MASK(port_num), INT_RX | INT_CAUSE_EXT); |
9f8dd319 | 1877 | } |
c9df406f | 1878 | #endif |
9f8dd319 | 1879 | |
e5371493 | 1880 | static int mv643xx_eth_mdio_read(struct net_device *dev, int phy_id, int location) |
9f8dd319 | 1881 | { |
e5371493 | 1882 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f LB |
1883 | int val; |
1884 | ||
cc9754b3 | 1885 | read_smi_reg(mp, location, &val); |
c9df406f | 1886 | return val; |
9f8dd319 DF |
1887 | } |
1888 | ||
e5371493 | 1889 | static void mv643xx_eth_mdio_write(struct net_device *dev, int phy_id, int location, int val) |
9f8dd319 | 1890 | { |
e5371493 | 1891 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
cc9754b3 | 1892 | write_smi_reg(mp, location, val); |
c9df406f | 1893 | } |
9f8dd319 | 1894 | |
9f8dd319 | 1895 | |
c9df406f | 1896 | /* platform glue ************************************************************/ |
e5371493 LB |
1897 | static void |
1898 | mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp, | |
1899 | struct mbus_dram_target_info *dram) | |
c9df406f | 1900 | { |
cc9754b3 | 1901 | void __iomem *base = msp->base; |
c9df406f LB |
1902 | u32 win_enable; |
1903 | u32 win_protect; | |
1904 | int i; | |
9f8dd319 | 1905 | |
c9df406f LB |
1906 | for (i = 0; i < 6; i++) { |
1907 | writel(0, base + WINDOW_BASE(i)); | |
1908 | writel(0, base + WINDOW_SIZE(i)); | |
1909 | if (i < 4) | |
1910 | writel(0, base + WINDOW_REMAP_HIGH(i)); | |
9f8dd319 DF |
1911 | } |
1912 | ||
c9df406f LB |
1913 | win_enable = 0x3f; |
1914 | win_protect = 0; | |
1915 | ||
1916 | for (i = 0; i < dram->num_cs; i++) { | |
1917 | struct mbus_dram_window *cs = dram->cs + i; | |
1918 | ||
1919 | writel((cs->base & 0xffff0000) | | |
1920 | (cs->mbus_attr << 8) | | |
1921 | dram->mbus_dram_target_id, base + WINDOW_BASE(i)); | |
1922 | writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); | |
1923 | ||
1924 | win_enable &= ~(1 << i); | |
1925 | win_protect |= 3 << (2 * i); | |
1926 | } | |
1927 | ||
1928 | writel(win_enable, base + WINDOW_BAR_ENABLE); | |
1929 | msp->win_protect = win_protect; | |
9f8dd319 DF |
1930 | } |
1931 | ||
c9df406f | 1932 | static int mv643xx_eth_shared_probe(struct platform_device *pdev) |
9f8dd319 | 1933 | { |
e5371493 | 1934 | static int mv643xx_eth_version_printed = 0; |
c9df406f | 1935 | struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data; |
e5371493 | 1936 | struct mv643xx_eth_shared_private *msp; |
c9df406f LB |
1937 | struct resource *res; |
1938 | int ret; | |
9f8dd319 | 1939 | |
e5371493 | 1940 | if (!mv643xx_eth_version_printed++) |
c9df406f | 1941 | printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n"); |
9f8dd319 | 1942 | |
c9df406f LB |
1943 | ret = -EINVAL; |
1944 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1945 | if (res == NULL) | |
1946 | goto out; | |
9f8dd319 | 1947 | |
c9df406f LB |
1948 | ret = -ENOMEM; |
1949 | msp = kmalloc(sizeof(*msp), GFP_KERNEL); | |
1950 | if (msp == NULL) | |
1951 | goto out; | |
1952 | memset(msp, 0, sizeof(*msp)); | |
1953 | ||
cc9754b3 LB |
1954 | msp->base = ioremap(res->start, res->end - res->start + 1); |
1955 | if (msp->base == NULL) | |
c9df406f LB |
1956 | goto out_free; |
1957 | ||
1958 | spin_lock_init(&msp->phy_lock); | |
1959 | msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000; | |
1960 | ||
1961 | platform_set_drvdata(pdev, msp); | |
1962 | ||
1963 | /* | |
1964 | * (Re-)program MBUS remapping windows if we are asked to. | |
1965 | */ | |
1966 | if (pd != NULL && pd->dram != NULL) | |
1967 | mv643xx_eth_conf_mbus_windows(msp, pd->dram); | |
1968 | ||
1969 | return 0; | |
1970 | ||
1971 | out_free: | |
1972 | kfree(msp); | |
1973 | out: | |
1974 | return ret; | |
1975 | } | |
1976 | ||
1977 | static int mv643xx_eth_shared_remove(struct platform_device *pdev) | |
1978 | { | |
e5371493 | 1979 | struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev); |
c9df406f | 1980 | |
cc9754b3 | 1981 | iounmap(msp->base); |
c9df406f LB |
1982 | kfree(msp); |
1983 | ||
1984 | return 0; | |
9f8dd319 DF |
1985 | } |
1986 | ||
c9df406f LB |
1987 | static struct platform_driver mv643xx_eth_shared_driver = { |
1988 | .probe = mv643xx_eth_shared_probe, | |
1989 | .remove = mv643xx_eth_shared_remove, | |
1990 | .driver = { | |
1991 | .name = MV643XX_ETH_SHARED_NAME, | |
1992 | .owner = THIS_MODULE, | |
1993 | }, | |
1994 | }; | |
1995 | ||
e5371493 | 1996 | static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr) |
1da177e4 | 1997 | { |
c9df406f LB |
1998 | u32 reg_data; |
1999 | int addr_shift = 5 * mp->port_num; | |
1da177e4 | 2000 | |
3cb4667c | 2001 | reg_data = rdl(mp, PHY_ADDR); |
c9df406f LB |
2002 | reg_data &= ~(0x1f << addr_shift); |
2003 | reg_data |= (phy_addr & 0x1f) << addr_shift; | |
3cb4667c | 2004 | wrl(mp, PHY_ADDR, reg_data); |
1da177e4 LT |
2005 | } |
2006 | ||
e5371493 | 2007 | static int phy_addr_get(struct mv643xx_eth_private *mp) |
1da177e4 | 2008 | { |
c9df406f | 2009 | unsigned int reg_data; |
1da177e4 | 2010 | |
3cb4667c | 2011 | reg_data = rdl(mp, PHY_ADDR); |
1da177e4 | 2012 | |
c9df406f | 2013 | return ((reg_data >> (5 * mp->port_num)) & 0x1f); |
1da177e4 LT |
2014 | } |
2015 | ||
e5371493 | 2016 | static int phy_detect(struct mv643xx_eth_private *mp) |
1da177e4 | 2017 | { |
c9df406f LB |
2018 | unsigned int phy_reg_data0; |
2019 | int auto_neg; | |
1da177e4 | 2020 | |
cc9754b3 | 2021 | read_smi_reg(mp, 0, &phy_reg_data0); |
c9df406f LB |
2022 | auto_neg = phy_reg_data0 & 0x1000; |
2023 | phy_reg_data0 ^= 0x1000; /* invert auto_neg */ | |
cc9754b3 | 2024 | write_smi_reg(mp, 0, phy_reg_data0); |
1da177e4 | 2025 | |
cc9754b3 | 2026 | read_smi_reg(mp, 0, &phy_reg_data0); |
c9df406f LB |
2027 | if ((phy_reg_data0 & 0x1000) == auto_neg) |
2028 | return -ENODEV; /* change didn't take */ | |
1da177e4 | 2029 | |
c9df406f | 2030 | phy_reg_data0 ^= 0x1000; |
cc9754b3 | 2031 | write_smi_reg(mp, 0, phy_reg_data0); |
c9df406f | 2032 | return 0; |
1da177e4 LT |
2033 | } |
2034 | ||
c9df406f LB |
2035 | static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address, |
2036 | int speed, int duplex, | |
2037 | struct ethtool_cmd *cmd) | |
c28a4f89 | 2038 | { |
e5371493 | 2039 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c28a4f89 | 2040 | |
c9df406f | 2041 | memset(cmd, 0, sizeof(*cmd)); |
c28a4f89 | 2042 | |
c9df406f LB |
2043 | cmd->port = PORT_MII; |
2044 | cmd->transceiver = XCVR_INTERNAL; | |
2045 | cmd->phy_address = phy_address; | |
2046 | ||
2047 | if (speed == 0) { | |
2048 | cmd->autoneg = AUTONEG_ENABLE; | |
2049 | /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */ | |
2050 | cmd->speed = SPEED_100; | |
2051 | cmd->advertising = ADVERTISED_10baseT_Half | | |
2052 | ADVERTISED_10baseT_Full | | |
2053 | ADVERTISED_100baseT_Half | | |
2054 | ADVERTISED_100baseT_Full; | |
2055 | if (mp->mii.supports_gmii) | |
2056 | cmd->advertising |= ADVERTISED_1000baseT_Full; | |
2057 | } else { | |
2058 | cmd->autoneg = AUTONEG_DISABLE; | |
2059 | cmd->speed = speed; | |
2060 | cmd->duplex = duplex; | |
2061 | } | |
c28a4f89 JC |
2062 | } |
2063 | ||
c9df406f | 2064 | static int mv643xx_eth_probe(struct platform_device *pdev) |
1da177e4 | 2065 | { |
c9df406f LB |
2066 | struct mv643xx_eth_platform_data *pd; |
2067 | int port_num; | |
e5371493 | 2068 | struct mv643xx_eth_private *mp; |
c9df406f LB |
2069 | struct net_device *dev; |
2070 | u8 *p; | |
2071 | struct resource *res; | |
2072 | int err; | |
2073 | struct ethtool_cmd cmd; | |
2074 | int duplex = DUPLEX_HALF; | |
2075 | int speed = 0; /* default to auto-negotiation */ | |
2076 | DECLARE_MAC_BUF(mac); | |
1da177e4 | 2077 | |
c9df406f LB |
2078 | pd = pdev->dev.platform_data; |
2079 | if (pd == NULL) { | |
2080 | printk(KERN_ERR "No mv643xx_eth_platform_data\n"); | |
2081 | return -ENODEV; | |
2082 | } | |
1da177e4 | 2083 | |
c9df406f LB |
2084 | if (pd->shared == NULL) { |
2085 | printk(KERN_ERR "No mv643xx_eth_platform_data->shared\n"); | |
2086 | return -ENODEV; | |
2087 | } | |
8f518703 | 2088 | |
e5371493 | 2089 | dev = alloc_etherdev(sizeof(struct mv643xx_eth_private)); |
c9df406f LB |
2090 | if (!dev) |
2091 | return -ENOMEM; | |
1da177e4 | 2092 | |
c9df406f | 2093 | platform_set_drvdata(pdev, dev); |
1da177e4 | 2094 | |
c9df406f LB |
2095 | mp = netdev_priv(dev); |
2096 | mp->dev = dev; | |
e5371493 LB |
2097 | #ifdef MV643XX_ETH_NAPI |
2098 | netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64); | |
c9df406f | 2099 | #endif |
1da177e4 | 2100 | |
c9df406f LB |
2101 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
2102 | BUG_ON(!res); | |
2103 | dev->irq = res->start; | |
1da177e4 | 2104 | |
c9df406f LB |
2105 | dev->open = mv643xx_eth_open; |
2106 | dev->stop = mv643xx_eth_stop; | |
2107 | dev->hard_start_xmit = mv643xx_eth_start_xmit; | |
2108 | dev->set_mac_address = mv643xx_eth_set_mac_address; | |
2109 | dev->set_multicast_list = mv643xx_eth_set_rx_mode; | |
2110 | ||
2111 | /* No need to Tx Timeout */ | |
2112 | dev->tx_timeout = mv643xx_eth_tx_timeout; | |
2113 | ||
2114 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
e5371493 | 2115 | dev->poll_controller = mv643xx_eth_netpoll; |
c9df406f LB |
2116 | #endif |
2117 | ||
2118 | dev->watchdog_timeo = 2 * HZ; | |
2119 | dev->base_addr = 0; | |
2120 | dev->change_mtu = mv643xx_eth_change_mtu; | |
2121 | dev->do_ioctl = mv643xx_eth_do_ioctl; | |
e5371493 | 2122 | SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops); |
1da177e4 | 2123 | |
e5371493 | 2124 | #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX |
c9df406f | 2125 | #ifdef MAX_SKB_FRAGS |
b4de9051 | 2126 | /* |
c9df406f LB |
2127 | * Zero copy can only work if we use Discovery II memory. Else, we will |
2128 | * have to map the buffers to ISA memory which is only 16 MB | |
b4de9051 | 2129 | */ |
c9df406f LB |
2130 | dev->features = NETIF_F_SG | NETIF_F_IP_CSUM; |
2131 | #endif | |
2132 | #endif | |
1da177e4 | 2133 | |
c9df406f LB |
2134 | /* Configure the timeout task */ |
2135 | INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task); | |
1da177e4 | 2136 | |
c9df406f | 2137 | spin_lock_init(&mp->lock); |
1da177e4 | 2138 | |
c9df406f LB |
2139 | mp->shared = platform_get_drvdata(pd->shared); |
2140 | port_num = mp->port_num = pd->port_number; | |
8f518703 | 2141 | |
c9df406f LB |
2142 | if (mp->shared->win_protect) |
2143 | wrl(mp, WINDOW_PROTECT(port_num), mp->shared->win_protect); | |
1da177e4 | 2144 | |
c9df406f LB |
2145 | mp->shared_smi = mp->shared; |
2146 | if (pd->shared_smi != NULL) | |
2147 | mp->shared_smi = platform_get_drvdata(pd->shared_smi); | |
2148 | ||
2149 | /* set default config values */ | |
cc9754b3 | 2150 | uc_addr_get(mp, dev->dev_addr); |
c9df406f LB |
2151 | |
2152 | if (is_valid_ether_addr(pd->mac_addr)) | |
2153 | memcpy(dev->dev_addr, pd->mac_addr, 6); | |
2154 | ||
2155 | if (pd->phy_addr || pd->force_phy_addr) | |
cc9754b3 | 2156 | phy_addr_set(mp, pd->phy_addr); |
8f518703 | 2157 | |
8a578111 | 2158 | mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE; |
c9df406f | 2159 | if (pd->rx_queue_size) |
8a578111 | 2160 | mp->default_rx_ring_size = pd->rx_queue_size; |
1da177e4 | 2161 | |
13d64285 | 2162 | mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE; |
c9df406f | 2163 | if (pd->tx_queue_size) |
13d64285 | 2164 | mp->default_tx_ring_size = pd->tx_queue_size; |
1da177e4 | 2165 | |
c9df406f | 2166 | if (pd->tx_sram_size) { |
13d64285 LB |
2167 | mp->tx_desc_sram_size = pd->tx_sram_size; |
2168 | mp->tx_desc_sram_addr = pd->tx_sram_addr; | |
c9df406f | 2169 | } |
1da177e4 | 2170 | |
c9df406f | 2171 | if (pd->rx_sram_size) { |
8a578111 LB |
2172 | mp->rx_desc_sram_addr = pd->rx_sram_addr; |
2173 | mp->rx_desc_sram_size = pd->rx_sram_size; | |
c9df406f | 2174 | } |
1da177e4 | 2175 | |
c9df406f LB |
2176 | duplex = pd->duplex; |
2177 | speed = pd->speed; | |
1da177e4 | 2178 | |
c9df406f LB |
2179 | /* Hook up MII support for ethtool */ |
2180 | mp->mii.dev = dev; | |
e5371493 LB |
2181 | mp->mii.mdio_read = mv643xx_eth_mdio_read; |
2182 | mp->mii.mdio_write = mv643xx_eth_mdio_write; | |
cc9754b3 | 2183 | mp->mii.phy_id = phy_addr_get(mp); |
c9df406f LB |
2184 | mp->mii.phy_id_mask = 0x3f; |
2185 | mp->mii.reg_num_mask = 0x1f; | |
1da177e4 | 2186 | |
cc9754b3 | 2187 | err = phy_detect(mp); |
c9df406f LB |
2188 | if (err) { |
2189 | pr_debug("%s: No PHY detected at addr %d\n", | |
cc9754b3 | 2190 | dev->name, phy_addr_get(mp)); |
c9df406f LB |
2191 | goto out; |
2192 | } | |
1da177e4 | 2193 | |
cc9754b3 | 2194 | phy_reset(mp); |
c9df406f LB |
2195 | mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii); |
2196 | mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd); | |
13d64285 | 2197 | mv643xx_eth_update_pscr(mp, &cmd); |
e5371493 | 2198 | mv643xx_eth_set_settings(dev, &cmd); |
8f518703 | 2199 | |
c9df406f LB |
2200 | SET_NETDEV_DEV(dev, &pdev->dev); |
2201 | err = register_netdev(dev); | |
2202 | if (err) | |
2203 | goto out; | |
1da177e4 | 2204 | |
c9df406f LB |
2205 | p = dev->dev_addr; |
2206 | printk(KERN_NOTICE | |
2207 | "%s: port %d with MAC address %s\n", | |
2208 | dev->name, port_num, print_mac(mac, p)); | |
1da177e4 | 2209 | |
c9df406f LB |
2210 | if (dev->features & NETIF_F_SG) |
2211 | printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name); | |
1da177e4 | 2212 | |
c9df406f LB |
2213 | if (dev->features & NETIF_F_IP_CSUM) |
2214 | printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n", | |
2215 | dev->name); | |
1da177e4 | 2216 | |
e5371493 | 2217 | #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX |
c9df406f LB |
2218 | printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name); |
2219 | #endif | |
1da177e4 | 2220 | |
e5371493 | 2221 | #ifdef MV643XX_ETH_COAL |
c9df406f LB |
2222 | printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n", |
2223 | dev->name); | |
2224 | #endif | |
1da177e4 | 2225 | |
e5371493 | 2226 | #ifdef MV643XX_ETH_NAPI |
c9df406f LB |
2227 | printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name); |
2228 | #endif | |
1da177e4 | 2229 | |
13d64285 | 2230 | if (mp->tx_desc_sram_size > 0) |
c9df406f | 2231 | printk(KERN_NOTICE "%s: Using SRAM\n", dev->name); |
1da177e4 | 2232 | |
c9df406f | 2233 | return 0; |
1da177e4 | 2234 | |
c9df406f LB |
2235 | out: |
2236 | free_netdev(dev); | |
1da177e4 | 2237 | |
c9df406f | 2238 | return err; |
1da177e4 LT |
2239 | } |
2240 | ||
c9df406f | 2241 | static int mv643xx_eth_remove(struct platform_device *pdev) |
1da177e4 | 2242 | { |
c9df406f | 2243 | struct net_device *dev = platform_get_drvdata(pdev); |
1da177e4 | 2244 | |
c9df406f LB |
2245 | unregister_netdev(dev); |
2246 | flush_scheduled_work(); | |
2247 | ||
2248 | free_netdev(dev); | |
2249 | platform_set_drvdata(pdev, NULL); | |
2250 | return 0; | |
1da177e4 LT |
2251 | } |
2252 | ||
c9df406f | 2253 | static void mv643xx_eth_shutdown(struct platform_device *pdev) |
d0412d96 | 2254 | { |
c9df406f | 2255 | struct net_device *dev = platform_get_drvdata(pdev); |
e5371493 | 2256 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f | 2257 | unsigned int port_num = mp->port_num; |
d0412d96 | 2258 | |
c9df406f | 2259 | /* Mask all interrupts on ethernet port */ |
3cb4667c LB |
2260 | wrl(mp, INT_MASK(port_num), 0); |
2261 | rdl(mp, INT_MASK(port_num)); | |
c9df406f | 2262 | |
cc9754b3 | 2263 | port_reset(mp); |
d0412d96 JC |
2264 | } |
2265 | ||
c9df406f LB |
2266 | static struct platform_driver mv643xx_eth_driver = { |
2267 | .probe = mv643xx_eth_probe, | |
2268 | .remove = mv643xx_eth_remove, | |
2269 | .shutdown = mv643xx_eth_shutdown, | |
2270 | .driver = { | |
2271 | .name = MV643XX_ETH_NAME, | |
2272 | .owner = THIS_MODULE, | |
2273 | }, | |
2274 | }; | |
2275 | ||
e5371493 | 2276 | static int __init mv643xx_eth_init_module(void) |
d0412d96 | 2277 | { |
c9df406f | 2278 | int rc; |
d0412d96 | 2279 | |
c9df406f LB |
2280 | rc = platform_driver_register(&mv643xx_eth_shared_driver); |
2281 | if (!rc) { | |
2282 | rc = platform_driver_register(&mv643xx_eth_driver); | |
2283 | if (rc) | |
2284 | platform_driver_unregister(&mv643xx_eth_shared_driver); | |
2285 | } | |
2286 | return rc; | |
d0412d96 JC |
2287 | } |
2288 | ||
e5371493 | 2289 | static void __exit mv643xx_eth_cleanup_module(void) |
d0412d96 | 2290 | { |
c9df406f LB |
2291 | platform_driver_unregister(&mv643xx_eth_driver); |
2292 | platform_driver_unregister(&mv643xx_eth_shared_driver); | |
d0412d96 JC |
2293 | } |
2294 | ||
e5371493 LB |
2295 | module_init(mv643xx_eth_init_module); |
2296 | module_exit(mv643xx_eth_cleanup_module); | |
1da177e4 | 2297 | |
c9df406f LB |
2298 | MODULE_LICENSE("GPL"); |
2299 | MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani" | |
2300 | " and Dale Farnsworth"); | |
2301 | MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); | |
2302 | MODULE_ALIAS("platform:" MV643XX_ETH_NAME); | |
2303 | MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME); |