[deliverable/linux.git] / drivers / net / mv643xx_eth.h

#ifndef __MV643XX_ETH_H__
#define __MV643XX_ETH_H__

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/workqueue.h>

#include <linux/mv643xx.h>

#define	BIT0	0x00000001
#define	BIT1	0x00000002
#define	BIT2	0x00000004
#define	BIT3	0x00000008
#define	BIT4	0x00000010
#define	BIT5	0x00000020
#define	BIT6	0x00000040
#define	BIT7	0x00000080
#define	BIT8	0x00000100
#define	BIT9	0x00000200
#define	BIT10	0x00000400
#define	BIT11	0x00000800
#define	BIT12	0x00001000
#define	BIT13	0x00002000
#define	BIT14	0x00004000
#define	BIT15	0x00008000
#define	BIT16	0x00010000
#define	BIT17	0x00020000
#define	BIT18	0x00040000
#define	BIT19	0x00080000
#define	BIT20	0x00100000
#define	BIT21	0x00200000
#define	BIT22	0x00400000
#define	BIT23	0x00800000
#define	BIT24	0x01000000
#define	BIT25	0x02000000
#define	BIT26	0x04000000
#define	BIT27	0x08000000
#define	BIT28	0x10000000
#define	BIT29	0x20000000
#define	BIT30	0x40000000
#define	BIT31	0x80000000

/*
 *  The first part is the high level driver of the gigE ethernet ports.
 */

/* Checksum offload for Tx works for most packets, but
 * fails if previous packet sent did not use hw csum
 */
#define	MV643XX_CHECKSUM_OFFLOAD_TX
#define	MV643XX_NAPI
#define	MV643XX_TX_FAST_REFILL
#undef	MV643XX_RX_QUEUE_FILL_ON_TASK	/* Does not work, yet */
#undef	MV643XX_COAL

/*
 * Number of RX / TX descriptors on RX / TX rings.
 * Note that allocating RX descriptors is done by allocating the RX
 * ring AND a preallocated RX buffers (skb's) for each descriptor.
 * The TX descriptors only allocates the TX descriptors ring,
 * with no pre allocated TX buffers (skb's are allocated by higher layers.
 */

/* Default TX ring size is 1000 descriptors */
#define MV643XX_DEFAULT_TX_QUEUE_SIZE 1000

/* Default RX ring size is 400 descriptors */
#define MV643XX_DEFAULT_RX_QUEUE_SIZE 400

#define MV643XX_TX_COAL 100
#ifdef MV643XX_COAL
#define MV643XX_RX_COAL 100
#endif

/*
 * The second part is the low level driver of the gigE ethernet ports.
 */

/*
 * Header File for : MV-643xx network interface header
 *
 * DESCRIPTION:
 *	This header file contains macros typedefs and function declaration for
 *	the Marvell Gig Bit Ethernet Controller.
 *
 * DEPENDENCIES:
 *	None.
 *
 */

/* Buffer offset from buffer pointer */
#define RX_BUF_OFFSET				0x2

/* Gigabit Ethernet Unit Global Registers */

/* MIB Counters register definitions */
#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW	0x0
#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH	0x4
#define ETH_MIB_BAD_OCTETS_RECEIVED		0x8
#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR	0xc
#define ETH_MIB_GOOD_FRAMES_RECEIVED		0x10
#define ETH_MIB_BAD_FRAMES_RECEIVED		0x14
#define ETH_MIB_BROADCAST_FRAMES_RECEIVED	0x18
#define ETH_MIB_MULTICAST_FRAMES_RECEIVED	0x1c
#define ETH_MIB_FRAMES_64_OCTETS		0x20
#define ETH_MIB_FRAMES_65_TO_127_OCTETS		0x24
#define ETH_MIB_FRAMES_128_TO_255_OCTETS	0x28
#define ETH_MIB_FRAMES_256_TO_511_OCTETS	0x2c
#define ETH_MIB_FRAMES_512_TO_1023_OCTETS	0x30
#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS	0x34
#define ETH_MIB_GOOD_OCTETS_SENT_LOW		0x38
#define ETH_MIB_GOOD_OCTETS_SENT_HIGH		0x3c
#define ETH_MIB_GOOD_FRAMES_SENT		0x40
#define ETH_MIB_EXCESSIVE_COLLISION		0x44
#define ETH_MIB_MULTICAST_FRAMES_SENT		0x48
#define ETH_MIB_BROADCAST_FRAMES_SENT		0x4c
#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED	0x50
#define ETH_MIB_FC_SENT				0x54
#define ETH_MIB_GOOD_FC_RECEIVED		0x58
#define ETH_MIB_BAD_FC_RECEIVED			0x5c
#define ETH_MIB_UNDERSIZE_RECEIVED		0x60
#define ETH_MIB_FRAGMENTS_RECEIVED		0x64
#define ETH_MIB_OVERSIZE_RECEIVED		0x68
#define ETH_MIB_JABBER_RECEIVED			0x6c
#define ETH_MIB_MAC_RECEIVE_ERROR		0x70
#define ETH_MIB_BAD_CRC_EVENT			0x74
#define ETH_MIB_COLLISION			0x78
#define ETH_MIB_LATE_COLLISION			0x7c

/* Port serial status reg (PSR) */
#define ETH_INTERFACE_GMII_MII			0
#define ETH_INTERFACE_PCM			BIT0
#define ETH_LINK_IS_DOWN			0
#define ETH_LINK_IS_UP				BIT1
#define ETH_PORT_AT_HALF_DUPLEX			0
#define ETH_PORT_AT_FULL_DUPLEX			BIT2
#define ETH_RX_FLOW_CTRL_DISABLED		0
#define ETH_RX_FLOW_CTRL_ENBALED		BIT3
#define ETH_GMII_SPEED_100_10			0
#define ETH_GMII_SPEED_1000			BIT4
#define ETH_MII_SPEED_10			0
#define ETH_MII_SPEED_100			BIT5
#define ETH_NO_TX				0
#define ETH_TX_IN_PROGRESS			BIT7
#define ETH_BYPASS_NO_ACTIVE			0
#define ETH_BYPASS_ACTIVE			BIT8
#define ETH_PORT_NOT_AT_PARTITION_STATE		0
#define ETH_PORT_AT_PARTITION_STATE		BIT9
#define ETH_PORT_TX_FIFO_NOT_EMPTY		0
#define ETH_PORT_TX_FIFO_EMPTY			BIT10

#define ETH_DEFAULT_RX_BPDU_QUEUE_3		(BIT23 | BIT22)
#define ETH_DEFAULT_RX_BPDU_QUEUE_4		BIT24
#define ETH_DEFAULT_RX_BPDU_QUEUE_5		(BIT24 | BIT22)
#define ETH_DEFAULT_RX_BPDU_QUEUE_6		(BIT24 | BIT23)
#define ETH_DEFAULT_RX_BPDU_QUEUE_7		(BIT24 | BIT23 | BIT22)

/* SMI reg */
#define ETH_SMI_BUSY		BIT28	/* 0 - Write, 1 - Read		*/
#define ETH_SMI_READ_VALID	BIT27	/* 0 - Write, 1 - Read		*/
#define ETH_SMI_OPCODE_WRITE	0	/* Completion of Read operation */
#define ETH_SMI_OPCODE_READ 	BIT26	/* Operation is in progress	*/

/* SDMA command status fields macros */

/* Tx & Rx descriptors status */
#define ETH_ERROR_SUMMARY			(BIT0)

/* Tx & Rx descriptors command */
#define ETH_BUFFER_OWNED_BY_DMA			(BIT31)

/* Tx descriptors status */
#define ETH_LC_ERROR				(0    )
#define ETH_UR_ERROR				(BIT1 )
#define ETH_RL_ERROR				(BIT2 )
#define ETH_LLC_SNAP_FORMAT			(BIT9 )

/* Rx descriptors status */
#define ETH_CRC_ERROR				(0    )
#define ETH_OVERRUN_ERROR			(BIT1 )
#define ETH_MAX_FRAME_LENGTH_ERROR		(BIT2 )
#define ETH_RESOURCE_ERROR			((BIT2 | BIT1))
#define ETH_VLAN_TAGGED				(BIT19)
#define ETH_BPDU_FRAME				(BIT20)
#define ETH_TCP_FRAME_OVER_IP_V_4		(0    )
#define ETH_UDP_FRAME_OVER_IP_V_4		(BIT21)
#define ETH_OTHER_FRAME_TYPE			(BIT22)
#define ETH_LAYER_2_IS_ETH_V_2			(BIT23)
#define ETH_FRAME_TYPE_IP_V_4			(BIT24)
#define ETH_FRAME_HEADER_OK			(BIT25)
#define ETH_RX_LAST_DESC			(BIT26)
#define ETH_RX_FIRST_DESC			(BIT27)
#define ETH_UNKNOWN_DESTINATION_ADDR		(BIT28)
#define ETH_RX_ENABLE_INTERRUPT			(BIT29)
#define ETH_LAYER_4_CHECKSUM_OK			(BIT30)

/* Rx descriptors byte count */
#define ETH_FRAME_FRAGMENTED			(BIT2)

/* Tx descriptors command */
#define ETH_LAYER_4_CHECKSUM_FIRST_DESC		(BIT10)
#define ETH_FRAME_SET_TO_VLAN			(BIT15)
#define ETH_TCP_FRAME				(0    )
#define ETH_UDP_FRAME				(BIT16)
#define ETH_GEN_TCP_UDP_CHECKSUM		(BIT17)
#define ETH_GEN_IP_V_4_CHECKSUM			(BIT18)
#define ETH_ZERO_PADDING			(BIT19)
#define ETH_TX_LAST_DESC			(BIT20)
#define ETH_TX_FIRST_DESC			(BIT21)
#define ETH_GEN_CRC				(BIT22)
#define ETH_TX_ENABLE_INTERRUPT			(BIT23)
#define ETH_AUTO_MODE				(BIT30)

#define ETH_TX_IHL_SHIFT			11

/* typedefs */

typedef enum _eth_func_ret_status {
	ETH_OK,			/* Returned as expected.		*/
	ETH_ERROR,		/* Fundamental error.			*/
	ETH_RETRY,		/* Could not process request. Try later.*/
	ETH_END_OF_JOB,		/* Ring has nothing to process.		*/
	ETH_QUEUE_FULL,		/* Ring resource error.			*/
	ETH_QUEUE_LAST_RESOURCE	/* Ring resources about to exhaust.	*/
} ETH_FUNC_RET_STATUS;

typedef enum _eth_target {
	ETH_TARGET_DRAM,
	ETH_TARGET_DEVICE,
	ETH_TARGET_CBS,
	ETH_TARGET_PCI0,
	ETH_TARGET_PCI1
} ETH_TARGET;

/* These are for big-endian machines.  Little endian needs different
 * definitions.
 */
#if defined(__BIG_ENDIAN)
struct eth_rx_desc {
	u16 byte_cnt;		/* Descriptor buffer byte count		*/
	u16 buf_size;		/* Buffer size				*/
	u32 cmd_sts;		/* Descriptor command status		*/
	u32 next_desc_ptr;	/* Next descriptor pointer		*/
	u32 buf_ptr;		/* Descriptor buffer pointer		*/
};

struct eth_tx_desc {
	u16 byte_cnt;		/* buffer byte count			*/
	u16 l4i_chk;		/* CPU provided TCP checksum		*/
	u32 cmd_sts;		/* Command/status field			*/
	u32 next_desc_ptr;	/* Pointer to next descriptor		*/
	u32 buf_ptr;		/* pointer to buffer for this descriptor*/
};

#elif defined(__LITTLE_ENDIAN)
struct eth_rx_desc {
	u32 cmd_sts;		/* Descriptor command status		*/
	u16 buf_size;		/* Buffer size				*/
	u16 byte_cnt;		/* Descriptor buffer byte count		*/
	u32 buf_ptr;		/* Descriptor buffer pointer		*/
	u32 next_desc_ptr;	/* Next descriptor pointer		*/
};

struct eth_tx_desc {
	u32 cmd_sts;		/* Command/status field			*/
	u16 l4i_chk;		/* CPU provided TCP checksum		*/
	u16 byte_cnt;		/* buffer byte count			*/
	u32 buf_ptr;		/* pointer to buffer for this descriptor*/
	u32 next_desc_ptr;	/* Pointer to next descriptor		*/
};
#else
#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
#endif

/* Unified struct for Rx and Tx operations. The user is not required to	*/
/* be familier with neither Tx nor Rx descriptors.			*/
struct pkt_info {
	unsigned short byte_cnt;	/* Descriptor buffer byte count	*/
	unsigned short l4i_chk;		/* Tx CPU provided TCP Checksum	*/
	unsigned int cmd_sts;		/* Descriptor command status	*/
	dma_addr_t buf_ptr;		/* Descriptor buffer pointer	*/
	struct sk_buff *return_info;	/* User resource return information */
};

/* Ethernet port specific infomation */

struct mv643xx_mib_counters {
	u64 good_octets_received;
	u32 bad_octets_received;
	u32 internal_mac_transmit_err;
	u32 good_frames_received;
	u32 bad_frames_received;
	u32 broadcast_frames_received;
	u32 multicast_frames_received;
	u32 frames_64_octets;
	u32 frames_65_to_127_octets;
	u32 frames_128_to_255_octets;
	u32 frames_256_to_511_octets;
	u32 frames_512_to_1023_octets;
	u32 frames_1024_to_max_octets;
	u64 good_octets_sent;
	u32 good_frames_sent;
	u32 excessive_collision;
	u32 multicast_frames_sent;
	u32 broadcast_frames_sent;
	u32 unrec_mac_control_received;
	u32 fc_sent;
	u32 good_fc_received;
	u32 bad_fc_received;
	u32 undersize_received;
	u32 fragments_received;
	u32 oversize_received;
	u32 jabber_received;
	u32 mac_receive_error;
	u32 bad_crc_event;
	u32 collision;
	u32 late_collision;
};

struct mv643xx_private {
	int port_num;			/* User Ethernet port number	*/
	u32 port_config;		/* User port configuration value*/
	u32 port_config_extend;		/* User port config extend value*/
	u32 port_sdma_config;		/* User port SDMA config value	*/
	u32 port_serial_control;	/* User port serial control value */
	u32 port_tx_queue_command;	/* Port active Tx queues summary*/
	u32 port_rx_queue_command;	/* Port active Rx queues summary*/

	u32 rx_sram_addr;		/* Base address of rx sram area */
	u32 rx_sram_size;		/* Size of rx sram area		*/
	u32 tx_sram_addr;		/* Base address of tx sram area */
	u32 tx_sram_size;		/* Size of tx sram area		*/

	int rx_resource_err;		/* Rx ring resource error flag */
	int tx_resource_err;		/* Tx ring resource error flag */

	/* Tx/Rx rings managment indexes fields. For driver use */

	/* Next available and first returning Rx resource */
	int rx_curr_desc_q, rx_used_desc_q;

	/* Next available and first returning Tx resource */
	int tx_curr_desc_q, tx_used_desc_q;
#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
	int tx_first_desc_q;
	u32 tx_first_command;
#endif

#ifdef MV643XX_TX_FAST_REFILL
	u32 tx_clean_threshold;
#endif

	struct eth_rx_desc *p_rx_desc_area;
	dma_addr_t rx_desc_dma;
	unsigned int rx_desc_area_size;
	struct sk_buff **rx_skb;

	struct eth_tx_desc *p_tx_desc_area;
	dma_addr_t tx_desc_dma;
	unsigned int tx_desc_area_size;
	struct sk_buff **tx_skb;

	struct work_struct tx_timeout_task;

	/*
	 * Former struct mv643xx_eth_priv members start here
	 */
	struct net_device_stats stats;
	struct mv643xx_mib_counters mib_counters;
	spinlock_t lock;
	/* Size of Tx Ring per queue */
	unsigned int tx_ring_size;
	/* Number of tx descriptors in use */
	unsigned int tx_desc_count;
	/* Size of Rx Ring per queue */
	unsigned int rx_ring_size;
	/* Number of rx descriptors in use */
	unsigned int rx_desc_count;

	/*
	 * rx_task used to fill RX ring out of bottom half context
	 */
	struct work_struct rx_task;

	/*
	 * Used in case RX Ring is empty, which can be caused when
	 * system does not have resources (skb's)
	 */
	struct timer_list timeout;
	long rx_task_busy __attribute__ ((aligned(SMP_CACHE_BYTES)));
	unsigned rx_timer_flag;

	u32 rx_int_coal;
	u32 tx_int_coal;
};

/* ethernet.h API list */

/* Port operation control routines */
static void eth_port_init(struct mv643xx_private *mp);
static void eth_port_reset(unsigned int eth_port_num);
static void eth_port_start(struct net_device *dev);

/* Port MAC address routines */
static void eth_port_uc_addr_set(unsigned int eth_port_num,
				 unsigned char *p_addr);

/* PHY and MIB routines */
static void ethernet_phy_reset(unsigned int eth_port_num);

static void eth_port_write_smi_reg(unsigned int eth_port_num,
				   unsigned int phy_reg, unsigned int value);

static void eth_port_read_smi_reg(unsigned int eth_port_num,
				  unsigned int phy_reg, unsigned int *value);

static void eth_clear_mib_counters(unsigned int eth_port_num);

/* Port data flow control routines */
static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
					 struct pkt_info *p_pkt_info);
static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv643xx_private *mp,
					      struct pkt_info *p_pkt_info);
static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
					    struct pkt_info *p_pkt_info);
static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
					      struct pkt_info *p_pkt_info);

#endif				/* __MV643XX_ETH_H__ */
Commit	Line	Data
1da177e4 LT	1	#ifndef __MV643XX_ETH_H__
	2	#define __MV643XX_ETH_H__
	3
1da177e4 LT	4	#include <linux/module.h>
	5	#include <linux/kernel.h>
	6	#include <linux/spinlock.h>
	7	#include <linux/workqueue.h>
	8
	9	#include <linux/mv643xx.h>
	10
	11	#define BIT0 0x00000001
	12	#define BIT1 0x00000002
	13	#define BIT2 0x00000004
	14	#define BIT3 0x00000008
	15	#define BIT4 0x00000010
	16	#define BIT5 0x00000020
	17	#define BIT6 0x00000040
	18	#define BIT7 0x00000080
	19	#define BIT8 0x00000100
	20	#define BIT9 0x00000200
	21	#define BIT10 0x00000400
	22	#define BIT11 0x00000800
	23	#define BIT12 0x00001000
	24	#define BIT13 0x00002000
	25	#define BIT14 0x00004000
	26	#define BIT15 0x00008000
	27	#define BIT16 0x00010000
	28	#define BIT17 0x00020000
	29	#define BIT18 0x00040000
	30	#define BIT19 0x00080000
	31	#define BIT20 0x00100000
	32	#define BIT21 0x00200000
	33	#define BIT22 0x00400000
	34	#define BIT23 0x00800000
	35	#define BIT24 0x01000000
	36	#define BIT25 0x02000000
	37	#define BIT26 0x04000000
	38	#define BIT27 0x08000000
	39	#define BIT28 0x10000000
	40	#define BIT29 0x20000000
	41	#define BIT30 0x40000000
	42	#define BIT31 0x80000000
	43
	44	/*
	45	* The first part is the high level driver of the gigE ethernet ports.
	46	*/
	47
	48	/* Checksum offload for Tx works for most packets, but
	49	* fails if previous packet sent did not use hw csum
	50	*/
26006360	51	#define MV643XX_CHECKSUM_OFFLOAD_TX
1da177e4 LT	52	#define MV643XX_NAPI
	53	#define MV643XX_TX_FAST_REFILL
	54	#undef MV643XX_RX_QUEUE_FILL_ON_TASK /* Does not work, yet */
	55	#undef MV643XX_COAL
	56
	57	/*
	58	* Number of RX / TX descriptors on RX / TX rings.
	59	* Note that allocating RX descriptors is done by allocating the RX
	60	* ring AND a preallocated RX buffers (skb's) for each descriptor.
	61	* The TX descriptors only allocates the TX descriptors ring,
	62	* with no pre allocated TX buffers (skb's are allocated by higher layers.
	63	*/
	64
	65	/* Default TX ring size is 1000 descriptors */
	66	#define MV643XX_DEFAULT_TX_QUEUE_SIZE 1000
	67
	68	/* Default RX ring size is 400 descriptors */
	69	#define MV643XX_DEFAULT_RX_QUEUE_SIZE 400
	70
	71	#define MV643XX_TX_COAL 100
	72	#ifdef MV643XX_COAL
	73	#define MV643XX_RX_COAL 100
	74	#endif
	75
	76	/*
	77	* The second part is the low level driver of the gigE ethernet ports.
	78	*/
	79
	80	/*
	81	* Header File for : MV-643xx network interface header
	82	*
	83	* DESCRIPTION:
	84	* This header file contains macros typedefs and function declaration for
	85	* the Marvell Gig Bit Ethernet Controller.
	86	*
	87	* DEPENDENCIES:
	88	* None.
	89	*
	90	*/
	91
1da177e4 LT	92	/* Buffer offset from buffer pointer */
	93	#define RX_BUF_OFFSET 0x2
	94
	95	/* Gigabit Ethernet Unit Global Registers */
	96
	97	/* MIB Counters register definitions */
	98	#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
	99	#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
	100	#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
	101	#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
	102	#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
	103	#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
	104	#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
	105	#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
	106	#define ETH_MIB_FRAMES_64_OCTETS 0x20
	107	#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
	108	#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
	109	#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
	110	#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
	111	#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
	112	#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
	113	#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
	114	#define ETH_MIB_GOOD_FRAMES_SENT 0x40
	115	#define ETH_MIB_EXCESSIVE_COLLISION 0x44
	116	#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
	117	#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
	118	#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
	119	#define ETH_MIB_FC_SENT 0x54
	120	#define ETH_MIB_GOOD_FC_RECEIVED 0x58
	121	#define ETH_MIB_BAD_FC_RECEIVED 0x5c
	122	#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
	123	#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
	124	#define ETH_MIB_OVERSIZE_RECEIVED 0x68
	125	#define ETH_MIB_JABBER_RECEIVED 0x6c
	126	#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
	127	#define ETH_MIB_BAD_CRC_EVENT 0x74
	128	#define ETH_MIB_COLLISION 0x78
	129	#define ETH_MIB_LATE_COLLISION 0x7c
	130
	131	/* Port serial status reg (PSR) */
	132	#define ETH_INTERFACE_GMII_MII 0
	133	#define ETH_INTERFACE_PCM BIT0
	134	#define ETH_LINK_IS_DOWN 0
	135	#define ETH_LINK_IS_UP BIT1
	136	#define ETH_PORT_AT_HALF_DUPLEX 0
	137	#define ETH_PORT_AT_FULL_DUPLEX BIT2
	138	#define ETH_RX_FLOW_CTRL_DISABLED 0
	139	#define ETH_RX_FLOW_CTRL_ENBALED BIT3
	140	#define ETH_GMII_SPEED_100_10 0
	141	#define ETH_GMII_SPEED_1000 BIT4
	142	#define ETH_MII_SPEED_10 0
	143	#define ETH_MII_SPEED_100 BIT5
	144	#define ETH_NO_TX 0
	145	#define ETH_TX_IN_PROGRESS BIT7
	146	#define ETH_BYPASS_NO_ACTIVE 0
	147	#define ETH_BYPASS_ACTIVE BIT8
	148	#define ETH_PORT_NOT_AT_PARTITION_STATE 0
	149	#define ETH_PORT_AT_PARTITION_STATE BIT9
	150	#define ETH_PORT_TX_FIFO_NOT_EMPTY 0
	151	#define ETH_PORT_TX_FIFO_EMPTY BIT10
	152
	153	#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 \| BIT22)
	154	#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24
	155	#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 \| BIT22)
156	#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 \| BIT23)
157	#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 \| BIT23 \| BIT22)
158
159	/* SMI reg */
160	#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */
161	#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */
162	#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */
163	#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */
164
165	/* SDMA command status fields macros */
166
167	/* Tx & Rx descriptors status */
168	#define ETH_ERROR_SUMMARY (BIT0)
169
170	/* Tx & Rx descriptors command */
171	#define ETH_BUFFER_OWNED_BY_DMA (BIT31)
172
173	/* Tx descriptors status */
174	#define ETH_LC_ERROR (0 )
175	#define ETH_UR_ERROR (BIT1 )
176	#define ETH_RL_ERROR (BIT2 )
177	#define ETH_LLC_SNAP_FORMAT (BIT9 )
178
179	/* Rx descriptors status */
180	#define ETH_CRC_ERROR (0 )
181	#define ETH_OVERRUN_ERROR (BIT1 )
182	#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 )
183	#define ETH_RESOURCE_ERROR ((BIT2 \| BIT1))
184	#define ETH_VLAN_TAGGED (BIT19)
185	#define ETH_BPDU_FRAME (BIT20)
186	#define ETH_TCP_FRAME_OVER_IP_V_4 (0 )
187	#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21)
188	#define ETH_OTHER_FRAME_TYPE (BIT22)
189	#define ETH_LAYER_2_IS_ETH_V_2 (BIT23)
190	#define ETH_FRAME_TYPE_IP_V_4 (BIT24)
191	#define ETH_FRAME_HEADER_OK (BIT25)
192	#define ETH_RX_LAST_DESC (BIT26)
193	#define ETH_RX_FIRST_DESC (BIT27)
194	#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28)
195	#define ETH_RX_ENABLE_INTERRUPT (BIT29)
196	#define ETH_LAYER_4_CHECKSUM_OK (BIT30)
197
198	/* Rx descriptors byte count */
199	#define ETH_FRAME_FRAGMENTED (BIT2)
200
201	/* Tx descriptors command */
202	#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10)
203	#define ETH_FRAME_SET_TO_VLAN (BIT15)
204	#define ETH_TCP_FRAME (0 )
205	#define ETH_UDP_FRAME (BIT16)
206	#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17)
207	#define ETH_GEN_IP_V_4_CHECKSUM (BIT18)
208	#define ETH_ZERO_PADDING (BIT19)
209	#define ETH_TX_LAST_DESC (BIT20)
210	#define ETH_TX_FIRST_DESC (BIT21)
211	#define ETH_GEN_CRC (BIT22)
212	#define ETH_TX_ENABLE_INTERRUPT (BIT23)
213	#define ETH_AUTO_MODE (BIT30)
214
26006360 DF	215	#define ETH_TX_IHL_SHIFT 11
26006360 DF	216
1da177e4 LT	217	/* typedefs */
	218
	219	typedef enum _eth_func_ret_status {
	220	ETH_OK, /* Returned as expected. */
	221	ETH_ERROR, /* Fundamental error. */
	222	ETH_RETRY, /* Could not process request. Try later.*/
	223	ETH_END_OF_JOB, /* Ring has nothing to process. */
	224	ETH_QUEUE_FULL, /* Ring resource error. */
	225	ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
	226	} ETH_FUNC_RET_STATUS;
	227
	228	typedef enum _eth_target {
	229	ETH_TARGET_DRAM,
	230	ETH_TARGET_DEVICE,
	231	ETH_TARGET_CBS,
	232	ETH_TARGET_PCI0,
	233	ETH_TARGET_PCI1
	234	} ETH_TARGET;
	235
	236	/* These are for big-endian machines. Little endian needs different
	237	* definitions.
	238	*/
	239	#if defined(__BIG_ENDIAN)
	240	struct eth_rx_desc {
	241	u16 byte_cnt; /* Descriptor buffer byte count */
	242	u16 buf_size; /* Buffer size */
	243	u32 cmd_sts; /* Descriptor command status */
	244	u32 next_desc_ptr; /* Next descriptor pointer */
	245	u32 buf_ptr; /* Descriptor buffer pointer */
	246	};
	247
	248	struct eth_tx_desc {
	249	u16 byte_cnt; /* buffer byte count */
	250	u16 l4i_chk; /* CPU provided TCP checksum */
	251	u32 cmd_sts; /* Command/status field */
	252	u32 next_desc_ptr; /* Pointer to next descriptor */
	253	u32 buf_ptr; /* pointer to buffer for this descriptor*/
	254	};
	255
	256	#elif defined(__LITTLE_ENDIAN)
	257	struct eth_rx_desc {
	258	u32 cmd_sts; /* Descriptor command status */
	259	u16 buf_size; /* Buffer size */
	260	u16 byte_cnt; /* Descriptor buffer byte count */
	261	u32 buf_ptr; /* Descriptor buffer pointer */
	262	u32 next_desc_ptr; /* Next descriptor pointer */
	263	};
	264
	265	struct eth_tx_desc {
	266	u32 cmd_sts; /* Command/status field */
	267	u16 l4i_chk; /* CPU provided TCP checksum */
	268	u16 byte_cnt; /* buffer byte count */
	269	u32 buf_ptr; /* pointer to buffer for this descriptor*/
	270	u32 next_desc_ptr; /* Pointer to next descriptor */
	271	};
	272	#else
	273	#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
	274	#endif
	275
	276	/* Unified struct for Rx and Tx operations. The user is not required to */
	277	/* be familier with neither Tx nor Rx descriptors. */
	278	struct pkt_info {
	279	unsigned short byte_cnt; /* Descriptor buffer byte count */
	280	unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */
281	unsigned int cmd_sts; /* Descriptor command status */
282	dma_addr_t buf_ptr; /* Descriptor buffer pointer */
283	struct sk_buff return_info; / User resource return information */
284	};
285
286	/* Ethernet port specific infomation */
287
288	struct mv643xx_mib_counters {
289	u64 good_octets_received;
290	u32 bad_octets_received;
291	u32 internal_mac_transmit_err;
292	u32 good_frames_received;
293	u32 bad_frames_received;
294	u32 broadcast_frames_received;
295	u32 multicast_frames_received;
296	u32 frames_64_octets;
297	u32 frames_65_to_127_octets;
298	u32 frames_128_to_255_octets;
299	u32 frames_256_to_511_octets;
300	u32 frames_512_to_1023_octets;
301	u32 frames_1024_to_max_octets;
302	u64 good_octets_sent;
303	u32 good_frames_sent;
304	u32 excessive_collision;
305	u32 multicast_frames_sent;
306	u32 broadcast_frames_sent;
307	u32 unrec_mac_control_received;
308	u32 fc_sent;
309	u32 good_fc_received;
310	u32 bad_fc_received;
311	u32 undersize_received;
312	u32 fragments_received;
313	u32 oversize_received;
314	u32 jabber_received;
315	u32 mac_receive_error;
316	u32 bad_crc_event;
317	u32 collision;
318	u32 late_collision;
319	};
320
321	struct mv643xx_private {
322	int port_num; /* User Ethernet port number */
1da177e4 LT	323	u32 port_config; /* User port configuration value*/
	324	u32 port_config_extend; /* User port config extend value*/
	325	u32 port_sdma_config; /* User port SDMA config value */
	326	u32 port_serial_control; /* User port serial control value */
	327	u32 port_tx_queue_command; /* Port active Tx queues summary*/
	328	u32 port_rx_queue_command; /* Port active Rx queues summary*/
	329
	330	u32 rx_sram_addr; /* Base address of rx sram area */
	331	u32 rx_sram_size; /* Size of rx sram area */
	332	u32 tx_sram_addr; /* Base address of tx sram area */
	333	u32 tx_sram_size; /* Size of tx sram area */
	334
	335	int rx_resource_err; /* Rx ring resource error flag */
	336	int tx_resource_err; /* Tx ring resource error flag */
	337
	338	/* Tx/Rx rings managment indexes fields. For driver use */
	339
	340	/* Next available and first returning Rx resource */
	341	int rx_curr_desc_q, rx_used_desc_q;
	342
	343	/* Next available and first returning Tx resource */
	344	int tx_curr_desc_q, tx_used_desc_q;
	345	#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
	346	int tx_first_desc_q;
	347	u32 tx_first_command;
	348	#endif
	349
	350	#ifdef MV643XX_TX_FAST_REFILL
	351	u32 tx_clean_threshold;
	352	#endif
	353
	354	struct eth_rx_desc *p_rx_desc_area;
	355	dma_addr_t rx_desc_dma;
	356	unsigned int rx_desc_area_size;
	357	struct sk_buff **rx_skb;
	358
	359	struct eth_tx_desc *p_tx_desc_area;
	360	dma_addr_t tx_desc_dma;
	361	unsigned int tx_desc_area_size;
	362	struct sk_buff **tx_skb;
	363
	364	struct work_struct tx_timeout_task;
	365
	366	/*
	367	* Former struct mv643xx_eth_priv members start here
	368	*/
	369	struct net_device_stats stats;
	370	struct mv643xx_mib_counters mib_counters;
	371	spinlock_t lock;
	372	/* Size of Tx Ring per queue */
	373	unsigned int tx_ring_size;
f98e36f1 DF	374	/* Number of tx descriptors in use */
f98e36f1 DF	375	unsigned int tx_desc_count;
1da177e4 LT	376	/* Size of Rx Ring per queue */
1da177e4 LT	377	unsigned int rx_ring_size;
f98e36f1 DF	378	/* Number of rx descriptors in use */
f98e36f1 DF	379	unsigned int rx_desc_count;
1da177e4 LT	380
	381	/*
	382	* rx_task used to fill RX ring out of bottom half context
	383	*/
	384	struct work_struct rx_task;
	385
	386	/*
	387	* Used in case RX Ring is empty, which can be caused when
	388	* system does not have resources (skb's)
	389	*/
	390	struct timer_list timeout;
	391	long rx_task_busy __attribute__ ((aligned(SMP_CACHE_BYTES)));
	392	unsigned rx_timer_flag;
	393
	394	u32 rx_int_coal;
	395	u32 tx_int_coal;
	396	};
	397
	398	/* ethernet.h API list */
	399
	400	/* Port operation control routines */
	401	static void eth_port_init(struct mv643xx_private *mp);
	402	static void eth_port_reset(unsigned int eth_port_num);
ed9b5d45	403	static void eth_port_start(struct net_device *dev);
1da177e4	404
1da177e4 LT	405	/* Port MAC address routines */
	406	static void eth_port_uc_addr_set(unsigned int eth_port_num,
	407	unsigned char *p_addr);
	408
	409	/* PHY and MIB routines */
	410	static void ethernet_phy_reset(unsigned int eth_port_num);
	411
	412	static void eth_port_write_smi_reg(unsigned int eth_port_num,
	413	unsigned int phy_reg, unsigned int value);
	414
	415	static void eth_port_read_smi_reg(unsigned int eth_port_num,
	416	unsigned int phy_reg, unsigned int *value);
	417
	418	static void eth_clear_mib_counters(unsigned int eth_port_num);
	419
	420	/* Port data flow control routines */
	421	static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
	422	struct pkt_info *p_pkt_info);
	423	static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv643xx_private *mp,
	424	struct pkt_info *p_pkt_info);
	425	static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
	426	struct pkt_info *p_pkt_info);
	427	static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
	428	struct pkt_info *p_pkt_info);
	429
	430	#endif /* __MV643XX_ETH_H__ */