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[deliverable/linux.git] / drivers / net / myri10ge / myri10ge.c
CommitLineData
0da34b6d
BG		 1/*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
e3fd5534 4 * Copyright (C) 2005 - 2009 Myricom, Inc.
0da34b6d
BG		 5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
4a2e612a
BG		 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0da34b6d 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4a2e612a
BG		 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
0da34b6d
BG		 30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
78ca90ea
JP		 41#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
42
0da34b6d
BG		 43#include <linux/tcp.h>
44#include <linux/netdevice.h>
45#include <linux/skbuff.h>
46#include <linux/string.h>
47#include <linux/module.h>
48#include <linux/pci.h>
b10c0668 49#include <linux/dma-mapping.h>
0da34b6d
BG		 50#include <linux/etherdevice.h>
51#include <linux/if_ether.h>
52#include <linux/if_vlan.h>
1e6e9342 53#include <linux/inet_lro.h>
981813d8 54#include <linux/dca.h>
0da34b6d
BG		 55#include <linux/ip.h>
56#include <linux/inet.h>
57#include <linux/in.h>
58#include <linux/ethtool.h>
59#include <linux/firmware.h>
60#include <linux/delay.h>
0da34b6d
BG		 61#include <linux/timer.h>
62#include <linux/vmalloc.h>
63#include <linux/crc32.h>
64#include <linux/moduleparam.h>
65#include <linux/io.h>
199126a2 66#include <linux/log2.h>
5a0e3ad6 67#include <linux/slab.h>
0da34b6d 68#include <net/checksum.h>
1e6e9342
AG		 69#include <net/ip.h>
70#include <net/tcp.h>
0da34b6d
BG		 71#include <asm/byteorder.h>
72#include <asm/io.h>
0da34b6d
BG		 73#include <asm/processor.h>
74#ifdef CONFIG_MTRR
75#include <asm/mtrr.h>
76#endif
77
78#include "myri10ge_mcp.h"
79#include "myri10ge_mcp_gen_header.h"
80
2a3f2790 81#define MYRI10GE_VERSION_STR "1.5.2-1.459"
0da34b6d
BG		 82
83MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
84MODULE_AUTHOR("Maintainer: help@myri.com");
85MODULE_VERSION(MYRI10GE_VERSION_STR);
86MODULE_LICENSE("Dual BSD/GPL");
87
88#define MYRI10GE_MAX_ETHER_MTU 9014
89
90#define MYRI10GE_ETH_STOPPED 0
91#define MYRI10GE_ETH_STOPPING 1
92#define MYRI10GE_ETH_STARTING 2
93#define MYRI10GE_ETH_RUNNING 3
94#define MYRI10GE_ETH_OPEN_FAILED 4
95
96#define MYRI10GE_EEPROM_STRINGS_SIZE 256
97#define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
1e6e9342
AG		 98#define MYRI10GE_MAX_LRO_DESCRIPTORS 8
99#define MYRI10GE_LRO_MAX_PKTS 64
0da34b6d 100
40f6cff5 101#define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
0da34b6d
BG		 102#define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
103
dd50f336
BG		 104#define MYRI10GE_ALLOC_ORDER 0
105#define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
106#define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
107
236bb5e6
BG		 108#define MYRI10GE_MAX_SLICES 32
109
0da34b6d 110struct myri10ge_rx_buffer_state {
dd50f336
BG		 111 struct page *page;
112 int page_offset;
c755b4b6
FT		 113 DEFINE_DMA_UNMAP_ADDR(bus);
114 DEFINE_DMA_UNMAP_LEN(len);
0da34b6d
BG		 115};
116
117struct myri10ge_tx_buffer_state {
118 struct sk_buff *skb;
119 int last;
c755b4b6
FT		 120 DEFINE_DMA_UNMAP_ADDR(bus);
121 DEFINE_DMA_UNMAP_LEN(len);
0da34b6d
BG		 122};
123
124struct myri10ge_cmd {
125 u32 data0;
126 u32 data1;
127 u32 data2;
128};
129
130struct myri10ge_rx_buf {
131 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
0da34b6d
BG		 132 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
133 struct myri10ge_rx_buffer_state *info;
dd50f336
BG		 134 struct page *page;
135 dma_addr_t bus;
136 int page_offset;
0da34b6d 137 int cnt;
dd50f336 138 int fill_cnt;
0da34b6d
BG		 139 int alloc_fail;
140 int mask; /* number of rx slots -1 */
dd50f336 141 int watchdog_needed;
0da34b6d
BG		 142};
143
144struct myri10ge_tx_buf {
145 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
236bb5e6
BG		 146 __be32 __iomem *send_go; /* "go" doorbell ptr */
147 __be32 __iomem *send_stop; /* "stop" doorbell ptr */
0da34b6d
BG		 148 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
149 char *req_bytes;
150 struct myri10ge_tx_buffer_state *info;
151 int mask; /* number of transmit slots -1 */
0da34b6d
BG		 152 int req ____cacheline_aligned; /* transmit slots submitted */
153 int pkt_start; /* packets started */
b53bef84
BG		 154 int stop_queue;
155 int linearized;
0da34b6d
BG		 156 int done ____cacheline_aligned; /* transmit slots completed */
157 int pkt_done; /* packets completed */
b53bef84 158 int wake_queue;
236bb5e6 159 int queue_active;
0da34b6d
BG		 160};
161
162struct myri10ge_rx_done {
163 struct mcp_slot *entry;
164 dma_addr_t bus;
165 int cnt;
166 int idx;
1e6e9342
AG		 167 struct net_lro_mgr lro_mgr;
168 struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
0da34b6d
BG		 169};
170
b53bef84
BG		 171struct myri10ge_slice_netstats {
172 unsigned long rx_packets;
173 unsigned long tx_packets;
174 unsigned long rx_bytes;
175 unsigned long tx_bytes;
176 unsigned long rx_dropped;
177 unsigned long tx_dropped;
178};
179
180struct myri10ge_slice_state {
0da34b6d
BG		 181 struct myri10ge_tx_buf tx; /* transmit ring */
182 struct myri10ge_rx_buf rx_small;
183 struct myri10ge_rx_buf rx_big;
184 struct myri10ge_rx_done rx_done;
b53bef84
BG		 185 struct net_device *dev;
186 struct napi_struct napi;
187 struct myri10ge_priv *mgp;
188 struct myri10ge_slice_netstats stats;
189 __be32 __iomem *irq_claim;
190 struct mcp_irq_data *fw_stats;
191 dma_addr_t fw_stats_bus;
192 int watchdog_tx_done;
193 int watchdog_tx_req;
d0234215 194 int watchdog_rx_done;
5dd2d332 195#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 196 int cached_dca_tag;
197 int cpu;
198 __be32 __iomem *dca_tag;
199#endif
0dcffac1 200 char irq_desc[32];
b53bef84
BG		 201};
202
203struct myri10ge_priv {
0dcffac1 204 struct myri10ge_slice_state *ss;
b53bef84 205 int tx_boundary; /* boundary transmits cannot cross */
0dcffac1 206 int num_slices;
b53bef84 207 int running; /* running? */
0da34b6d 208 int small_bytes;
dd50f336 209 int big_bytes;
fa0a90d9 210 int max_intr_slots;
0da34b6d 211 struct net_device *dev;
b53bef84 212 spinlock_t stats_lock;
0da34b6d
BG		 213 u8 __iomem *sram;
214 int sram_size;
215 unsigned long board_span;
216 unsigned long iomem_base;
40f6cff5 217 __be32 __iomem *irq_deassert;
0da34b6d
BG		 218 char *mac_addr_string;
219 struct mcp_cmd_response *cmd;
220 dma_addr_t cmd_bus;
0da34b6d
BG		 221 struct pci_dev *pdev;
222 int msi_enabled;
0dcffac1
BG		 223 int msix_enabled;
224 struct msix_entry *msix_vectors;
5dd2d332 225#ifdef CONFIG_MYRI10GE_DCA
981813d8 226 int dca_enabled;
ef09aadf 227 int relaxed_order;
981813d8 228#endif
66341fff 229 u32 link_state;
0da34b6d
BG		 230 unsigned int rdma_tags_available;
231 int intr_coal_delay;
40f6cff5 232 __be32 __iomem *intr_coal_delay_ptr;
0da34b6d 233 int mtrr;
276e26c3 234 int wc_enabled;
0da34b6d
BG		 235 int down_cnt;
236 wait_queue_head_t down_wq;
237 struct work_struct watchdog_work;
238 struct timer_list watchdog_timer;
0da34b6d 239 int watchdog_resets;
b53bef84 240 int watchdog_pause;
0da34b6d 241 int pause;
7d351035 242 bool fw_name_allocated;
0da34b6d
BG		 243 char *fw_name;
244 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
c0bf8801 245 char *product_code_string;
0da34b6d 246 char fw_version[128];
9dc6f0e7
BG		 247 int fw_ver_major;
248 int fw_ver_minor;
249 int fw_ver_tiny;
250 int adopted_rx_filter_bug;
0da34b6d
BG		 251 u8 mac_addr[6]; /* eeprom mac address */
252 unsigned long serial_number;
253 int vendor_specific_offset;
85a7ea1b 254 int fw_multicast_support;
04ed3e74 255 u32 features;
4f93fde0 256 u32 max_tso6;
0da34b6d
BG		 257 u32 read_dma;
258 u32 write_dma;
259 u32 read_write_dma;
c58ac5ca
BG		 260 u32 link_changes;
261 u32 msg_enable;
2d90b0aa 262 unsigned int board_number;
d0234215 263 int rebooted;
0da34b6d
BG		 264};
265
266static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
267static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
0dcffac1
BG		 268static char *myri10ge_fw_rss_unaligned = "myri10ge_rss_ethp_z8e.dat";
269static char *myri10ge_fw_rss_aligned = "myri10ge_rss_eth_z8e.dat";
b9721d5a
BH		 270MODULE_FIRMWARE("myri10ge_ethp_z8e.dat");
271MODULE_FIRMWARE("myri10ge_eth_z8e.dat");
272MODULE_FIRMWARE("myri10ge_rss_ethp_z8e.dat");
273MODULE_FIRMWARE("myri10ge_rss_eth_z8e.dat");
0da34b6d 274
7d351035 275/* Careful: must be accessed under kparam_block_sysfs_write */
0da34b6d
BG		 276static char *myri10ge_fw_name = NULL;
277module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
d1ce3a0f 278MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
0da34b6d 279
2d90b0aa
BG		 280#define MYRI10GE_MAX_BOARDS 8
281static char *myri10ge_fw_names[MYRI10GE_MAX_BOARDS] =
7fe624f5 282 {[0 ... (MYRI10GE_MAX_BOARDS - 1)] = NULL };
2d90b0aa
BG		 283module_param_array_named(myri10ge_fw_names, myri10ge_fw_names, charp, NULL,
284 0444);
285MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image names per board");
286
0da34b6d
BG		 287static int myri10ge_ecrc_enable = 1;
288module_param(myri10ge_ecrc_enable, int, S_IRUGO);
d1ce3a0f 289MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
0da34b6d 290
0da34b6d
BG		 291static int myri10ge_small_bytes = -1; /* -1 == auto */
292module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
d1ce3a0f 293MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
0da34b6d
BG		 294
295static int myri10ge_msi = 1; /* enable msi by default */
3621cec5 296module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
d1ce3a0f 297MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
0da34b6d 298
f761fae1 299static int myri10ge_intr_coal_delay = 75;
0da34b6d 300module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
d1ce3a0f 301MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
0da34b6d
BG		 302
303static int myri10ge_flow_control = 1;
304module_param(myri10ge_flow_control, int, S_IRUGO);
d1ce3a0f 305MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
0da34b6d
BG		 306
307static int myri10ge_deassert_wait = 1;
308module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
309MODULE_PARM_DESC(myri10ge_deassert_wait,
d1ce3a0f 310 "Wait when deasserting legacy interrupts");
0da34b6d
BG		 311
312static int myri10ge_force_firmware = 0;
313module_param(myri10ge_force_firmware, int, S_IRUGO);
314MODULE_PARM_DESC(myri10ge_force_firmware,
d1ce3a0f 315 "Force firmware to assume aligned completions");
0da34b6d 316
0da34b6d
BG		 317static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
318module_param(myri10ge_initial_mtu, int, S_IRUGO);
d1ce3a0f 319MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
0da34b6d
BG		 320
321static int myri10ge_napi_weight = 64;
322module_param(myri10ge_napi_weight, int, S_IRUGO);
d1ce3a0f 323MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
0da34b6d
BG		 324
325static int myri10ge_watchdog_timeout = 1;
326module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
d1ce3a0f 327MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
0da34b6d
BG		 328
329static int myri10ge_max_irq_loops = 1048576;
330module_param(myri10ge_max_irq_loops, int, S_IRUGO);
331MODULE_PARM_DESC(myri10ge_max_irq_loops,
d1ce3a0f 332 "Set stuck legacy IRQ detection threshold");
0da34b6d 333
c58ac5ca
BG		 334#define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
335
336static int myri10ge_debug = -1; /* defaults above */
337module_param(myri10ge_debug, int, 0);
338MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
339
1e6e9342
AG		 340static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
341module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
d1ce3a0f
BG		 342MODULE_PARM_DESC(myri10ge_lro_max_pkts,
343 "Number of LRO packets to be aggregated");
1e6e9342 344
dd50f336
BG		 345static int myri10ge_fill_thresh = 256;
346module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
d1ce3a0f 347MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
dd50f336 348
f181137f
BG		 349static int myri10ge_reset_recover = 1;
350
0dcffac1
BG		 351static int myri10ge_max_slices = 1;
352module_param(myri10ge_max_slices, int, S_IRUGO);
353MODULE_PARM_DESC(myri10ge_max_slices, "Max tx/rx queues");
354
4b860abf 355static int myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT;
0dcffac1
BG		 356module_param(myri10ge_rss_hash, int, S_IRUGO);
357MODULE_PARM_DESC(myri10ge_rss_hash, "Type of RSS hashing to do");
358
981813d8
BG		 359static int myri10ge_dca = 1;
360module_param(myri10ge_dca, int, S_IRUGO);
361MODULE_PARM_DESC(myri10ge_dca, "Enable DCA if possible");
362
0da34b6d
BG		 363#define MYRI10GE_FW_OFFSET 1024*1024
364#define MYRI10GE_HIGHPART_TO_U32(X) \
365(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
366#define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
367
368#define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
369
2f76216f 370static void myri10ge_set_multicast_list(struct net_device *dev);
61357325
SH		 371static netdev_tx_t myri10ge_sw_tso(struct sk_buff *skb,
372 struct net_device *dev);
2f76216f 373
6250223e 374static inline void put_be32(__be32 val, __be32 __iomem * p)
40f6cff5 375{
6250223e 376 __raw_writel((__force __u32) val, (__force void __iomem *)p);
40f6cff5
AV		 377}
378
59081825
BG		 379static struct net_device_stats *myri10ge_get_stats(struct net_device *dev);
380
7d351035
RR		 381static void set_fw_name(struct myri10ge_priv *mgp, char *name, bool allocated)
382{
383 if (mgp->fw_name_allocated)
384 kfree(mgp->fw_name);
385 mgp->fw_name = name;
386 mgp->fw_name_allocated = allocated;
387}
388
0da34b6d
BG		 389static int
390myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
391 struct myri10ge_cmd *data, int atomic)
392{
393 struct mcp_cmd *buf;
394 char buf_bytes[sizeof(*buf) + 8];
395 struct mcp_cmd_response *response = mgp->cmd;
e700f9f4 396 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
0da34b6d
BG		 397 u32 dma_low, dma_high, result, value;
398 int sleep_total = 0;
399
400 /* ensure buf is aligned to 8 bytes */
401 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
402
403 buf->data0 = htonl(data->data0);
404 buf->data1 = htonl(data->data1);
405 buf->data2 = htonl(data->data2);
406 buf->cmd = htonl(cmd);
407 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
408 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
409
410 buf->response_addr.low = htonl(dma_low);
411 buf->response_addr.high = htonl(dma_high);
40f6cff5 412 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 413 mb();
414 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
415
416 /* wait up to 15ms. Longest command is the DMA benchmark,
417 * which is capped at 5ms, but runs from a timeout handler
418 * that runs every 7.8ms. So a 15ms timeout leaves us with
419 * a 2.2ms margin
420 */
421 if (atomic) {
422 /* if atomic is set, do not sleep,
423 * and try to get the completion quickly
424 * (1ms will be enough for those commands) */
425 for (sleep_total = 0;
8e95a202
JP		 426 sleep_total < 1000 &&
427 response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
bd2db0cf 428 sleep_total += 10) {
0da34b6d 429 udelay(10);
bd2db0cf
BG		 430 mb();
431 }
0da34b6d
BG		 432 } else {
433 /* use msleep for most command */
434 for (sleep_total = 0;
8e95a202
JP		 435 sleep_total < 15 &&
436 response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 437 sleep_total++)
438 msleep(1);
439 }
440
441 result = ntohl(response->result);
442 value = ntohl(response->data);
443 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
444 if (result == 0) {
445 data->data0 = value;
446 return 0;
85a7ea1b
BG		 447 } else if (result == MXGEFW_CMD_UNKNOWN) {
448 return -ENOSYS;
5443e9ea
BG		 449 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
450 return -E2BIG;
236bb5e6
BG		 451 } else if (result == MXGEFW_CMD_ERROR_RANGE &&
452 cmd == MXGEFW_CMD_ENABLE_RSS_QUEUES &&
453 (data->
454 data1 & MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES) !=
455 0) {
456 return -ERANGE;
0da34b6d
BG		 457 } else {
458 dev_err(&mgp->pdev->dev,
459 "command %d failed, result = %d\n",
460 cmd, result);
461 return -ENXIO;
462 }
463 }
464
465 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
466 cmd, result);
467 return -EAGAIN;
468}
469
470/*
471 * The eeprom strings on the lanaiX have the format
472 * SN=x\0
473 * MAC=x:x:x:x:x:x\0
474 * PT:ddd mmm xx xx:xx:xx xx\0
475 * PV:ddd mmm xx xx:xx:xx xx\0
476 */
477static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
478{
479 char *ptr, *limit;
480 int i;
481
482 ptr = mgp->eeprom_strings;
483 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
484
485 while (*ptr != '\0' && ptr < limit) {
486 if (memcmp(ptr, "MAC=", 4) == 0) {
487 ptr += 4;
488 mgp->mac_addr_string = ptr;
489 for (i = 0; i < 6; i++) {
490 if ((ptr + 2) > limit)
491 goto abort;
492 mgp->mac_addr[i] =
493 simple_strtoul(ptr, &ptr, 16);
494 ptr += 1;
495 }
496 }
c0bf8801
BG		 497 if (memcmp(ptr, "PC=", 3) == 0) {
498 ptr += 3;
499 mgp->product_code_string = ptr;
500 }
0da34b6d
BG		 501 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
502 ptr += 3;
503 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
504 }
505 while (ptr < limit && *ptr++) ;
506 }
507
508 return 0;
509
510abort:
511 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
512 return -ENXIO;
513}
514
515/*
516 * Enable or disable periodic RDMAs from the host to make certain
517 * chipsets resend dropped PCIe messages
518 */
519
520static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
521{
522 char __iomem *submit;
f8fd57c1 523 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 524 u32 dma_low, dma_high;
525 int i;
526
527 /* clear confirmation addr */
528 mgp->cmd->data = 0;
529 mb();
530
531 /* send a rdma command to the PCIe engine, and wait for the
532 * response in the confirmation address. The firmware should
533 * write a -1 there to indicate it is alive and well
534 */
535 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
536 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
537
538 buf[0] = htonl(dma_high); /* confirm addr MSW */
539 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 540 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 541 buf[3] = htonl(dma_high); /* dummy addr MSW */
542 buf[4] = htonl(dma_low); /* dummy addr LSW */
543 buf[5] = htonl(enable); /* enable? */
544
e700f9f4 545 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
0da34b6d
BG		 546
547 myri10ge_pio_copy(submit, &buf, sizeof(buf));
548 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
549 msleep(1);
550 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
551 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
552 (enable ? "enable" : "disable"));
553}
554
555static int
556myri10ge_validate_firmware(struct myri10ge_priv *mgp,
557 struct mcp_gen_header *hdr)
558{
559 struct device *dev = &mgp->pdev->dev;
0da34b6d
BG		 560
561 /* check firmware type */
562 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
563 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
564 return -EINVAL;
565 }
566
567 /* save firmware version for ethtool */
568 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
569
9dc6f0e7
BG		 570 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
571 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
0da34b6d 572
8e95a202
JP		 573 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR &&
574 mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
0da34b6d
BG		 575 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
576 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
577 MXGEFW_VERSION_MINOR);
578 return -EINVAL;
579 }
580 return 0;
581}
582
583static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
584{
585 unsigned crc, reread_crc;
586 const struct firmware *fw;
587 struct device *dev = &mgp->pdev->dev;
b0d31d6b 588 unsigned char *fw_readback;
0da34b6d
BG		 589 struct mcp_gen_header *hdr;
590 size_t hdr_offset;
591 int status;
e454358a 592 unsigned i;
0da34b6d
BG		 593
594 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
595 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
596 mgp->fw_name);
597 status = -EINVAL;
598 goto abort_with_nothing;
599 }
600
601 /* check size */
602
603 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
604 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
605 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
606 status = -EINVAL;
607 goto abort_with_fw;
608 }
609
610 /* check id */
40f6cff5 611 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 612 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
613 dev_err(dev, "Bad firmware file\n");
614 status = -EINVAL;
615 goto abort_with_fw;
616 }
617 hdr = (void *)(fw->data + hdr_offset);
618
619 status = myri10ge_validate_firmware(mgp, hdr);
620 if (status != 0)
621 goto abort_with_fw;
622
623 crc = crc32(~0, fw->data, fw->size);
e454358a
BG		 624 for (i = 0; i < fw->size; i += 256) {
625 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
626 fw->data + i,
627 min(256U, (unsigned)(fw->size - i)));
628 mb();
629 readb(mgp->sram);
b10c0668 630 }
b0d31d6b
DW		 631 fw_readback = vmalloc(fw->size);
632 if (!fw_readback) {
633 status = -ENOMEM;
634 goto abort_with_fw;
635 }
0da34b6d 636 /* corruption checking is good for parity recovery and buggy chipset */
b0d31d6b
DW		 637 memcpy_fromio(fw_readback, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
638 reread_crc = crc32(~0, fw_readback, fw->size);
639 vfree(fw_readback);
0da34b6d
BG		 640 if (crc != reread_crc) {
641 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
642 (unsigned)fw->size, reread_crc, crc);
643 status = -EIO;
644 goto abort_with_fw;
645 }
646 *size = (u32) fw->size;
647
648abort_with_fw:
649 release_firmware(fw);
650
651abort_with_nothing:
652 return status;
653}
654
655static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
656{
657 struct mcp_gen_header *hdr;
658 struct device *dev = &mgp->pdev->dev;
659 const size_t bytes = sizeof(struct mcp_gen_header);
660 size_t hdr_offset;
661 int status;
662
663 /* find running firmware header */
66341fff 664 hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 665
666 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
667 dev_err(dev, "Running firmware has bad header offset (%d)\n",
668 (int)hdr_offset);
669 return -EIO;
670 }
671
672 /* copy header of running firmware from SRAM to host memory to
673 * validate firmware */
674 hdr = kmalloc(bytes, GFP_KERNEL);
675 if (hdr == NULL) {
676 dev_err(dev, "could not malloc firmware hdr\n");
677 return -ENOMEM;
678 }
679 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
680 status = myri10ge_validate_firmware(mgp, hdr);
681 kfree(hdr);
9dc6f0e7
BG		 682
683 /* check to see if adopted firmware has bug where adopting
684 * it will cause broadcasts to be filtered unless the NIC
685 * is kept in ALLMULTI mode */
686 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
687 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
688 mgp->adopted_rx_filter_bug = 1;
689 dev_warn(dev, "Adopting fw %d.%d.%d: "
690 "working around rx filter bug\n",
691 mgp->fw_ver_major, mgp->fw_ver_minor,
692 mgp->fw_ver_tiny);
693 }
0da34b6d
BG		 694 return status;
695}
696
0178ec3d 697static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
fa0a90d9
BG		 698{
699 struct myri10ge_cmd cmd;
700 int status;
701
702 /* probe for IPv6 TSO support */
703 mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
704 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
705 &cmd, 0);
706 if (status == 0) {
707 mgp->max_tso6 = cmd.data0;
708 mgp->features |= NETIF_F_TSO6;
709 }
710
711 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
712 if (status != 0) {
713 dev_err(&mgp->pdev->dev,
714 "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
715 return -ENXIO;
716 }
717
718 mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
719
720 return 0;
721}
722
0dcffac1 723static int myri10ge_load_firmware(struct myri10ge_priv *mgp, int adopt)
0da34b6d
BG		 724{
725 char __iomem *submit;
f8fd57c1 726 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 727 u32 dma_low, dma_high, size;
728 int status, i;
729
b10c0668 730 size = 0;
0da34b6d
BG		 731 status = myri10ge_load_hotplug_firmware(mgp, &size);
732 if (status) {
0dcffac1
BG		 733 if (!adopt)
734 return status;
0da34b6d
BG		 735 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
736
737 /* Do not attempt to adopt firmware if there
738 * was a bad crc */
739 if (status == -EIO)
740 return status;
741
742 status = myri10ge_adopt_running_firmware(mgp);
743 if (status != 0) {
744 dev_err(&mgp->pdev->dev,
745 "failed to adopt running firmware\n");
746 return status;
747 }
748 dev_info(&mgp->pdev->dev,
749 "Successfully adopted running firmware\n");
b53bef84 750 if (mgp->tx_boundary == 4096) {
0da34b6d
BG		 751 dev_warn(&mgp->pdev->dev,
752 "Using firmware currently running on NIC"
753 ". For optimal\n");
754 dev_warn(&mgp->pdev->dev,
755 "performance consider loading optimized "
756 "firmware\n");
757 dev_warn(&mgp->pdev->dev, "via hotplug\n");
758 }
759
7d351035 760 set_fw_name(mgp, "adopted", false);
b53bef84 761 mgp->tx_boundary = 2048;
fa0a90d9
BG		 762 myri10ge_dummy_rdma(mgp, 1);
763 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d
BG		 764 return status;
765 }
766
767 /* clear confirmation addr */
768 mgp->cmd->data = 0;
769 mb();
770
771 /* send a reload command to the bootstrap MCP, and wait for the
772 * response in the confirmation address. The firmware should
773 * write a -1 there to indicate it is alive and well
774 */
775 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
776 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
777
778 buf[0] = htonl(dma_high); /* confirm addr MSW */
779 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 780 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 781
782 /* FIX: All newest firmware should un-protect the bottom of
783 * the sram before handoff. However, the very first interfaces
784 * do not. Therefore the handoff copy must skip the first 8 bytes
785 */
786 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
787 buf[4] = htonl(size - 8); /* length of code */
788 buf[5] = htonl(8); /* where to copy to */
789 buf[6] = htonl(0); /* where to jump to */
790
e700f9f4 791 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
0da34b6d
BG		 792
793 myri10ge_pio_copy(submit, &buf, sizeof(buf));
794 mb();
795 msleep(1);
796 mb();
797 i = 0;
d93ca2a4
BG		 798 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
799 msleep(1 << i);
0da34b6d
BG		 800 i++;
801 }
802 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
803 dev_err(&mgp->pdev->dev, "handoff failed\n");
804 return -ENXIO;
805 }
9a71db72 806 myri10ge_dummy_rdma(mgp, 1);
fa0a90d9 807 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d 808
fa0a90d9 809 return status;
0da34b6d
BG		 810}
811
812static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
813{
814 struct myri10ge_cmd cmd;
815 int status;
816
817 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
818 | (addr[2] << 8) | addr[3]);
819
820 cmd.data1 = ((addr[4] << 8) | (addr[5]));
821
822 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
823 return status;
824}
825
826static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
827{
828 struct myri10ge_cmd cmd;
829 int status, ctl;
830
831 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
832 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
833
834 if (status) {
78ca90ea 835 netdev_err(mgp->dev, "Failed to set flow control mode\n");
0da34b6d
BG		 836 return status;
837 }
838 mgp->pause = pause;
839 return 0;
840}
841
842static void
843myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
844{
845 struct myri10ge_cmd cmd;
846 int status, ctl;
847
848 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
849 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
850 if (status)
78ca90ea 851 netdev_err(mgp->dev, "Failed to set promisc mode\n");
0da34b6d
BG		 852}
853
0d6ac257 854static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
0da34b6d
BG		 855{
856 struct myri10ge_cmd cmd;
857 int status;
0da34b6d 858 u32 len;
34fdccea
BG		 859 struct page *dmatest_page;
860 dma_addr_t dmatest_bus;
0d6ac257
BG		 861 char *test = " ";
862
863 dmatest_page = alloc_page(GFP_KERNEL);
864 if (!dmatest_page)
865 return -ENOMEM;
866 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
867 DMA_BIDIRECTIONAL);
868
869 /* Run a small DMA test.
870 * The magic multipliers to the length tell the firmware
871 * to do DMA read, write, or read+write tests. The
872 * results are returned in cmd.data0. The upper 16
873 * bits or the return is the number of transfers completed.
874 * The lower 16 bits is the time in 0.5us ticks that the
875 * transfers took to complete.
876 */
877
b53bef84 878 len = mgp->tx_boundary;
0d6ac257
BG		 879
880 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
881 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
882 cmd.data2 = len * 0x10000;
883 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
884 if (status != 0) {
885 test = "read";
886 goto abort;
887 }
888 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
889 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
890 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
891 cmd.data2 = len * 0x1;
892 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
893 if (status != 0) {
894 test = "write";
895 goto abort;
896 }
897 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
898
899 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
900 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
901 cmd.data2 = len * 0x10001;
902 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
903 if (status != 0) {
904 test = "read/write";
905 goto abort;
906 }
907 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
908 (cmd.data0 & 0xffff);
909
910abort:
911 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
912 put_page(dmatest_page);
913
914 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
915 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
916 test, status);
917
918 return status;
919}
920
921static int myri10ge_reset(struct myri10ge_priv *mgp)
922{
923 struct myri10ge_cmd cmd;
0dcffac1
BG		 924 struct myri10ge_slice_state *ss;
925 int i, status;
0d6ac257 926 size_t bytes;
5dd2d332 927#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 928 unsigned long dca_tag_off;
929#endif
0da34b6d
BG		 930
931 /* try to send a reset command to the card to see if it
932 * is alive */
933 memset(&cmd, 0, sizeof(cmd));
934 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
935 if (status != 0) {
936 dev_err(&mgp->pdev->dev, "failed reset\n");
937 return -ENXIO;
938 }
0d6ac257
BG		 939
940 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
0dcffac1
BG		 941 /*
942 * Use non-ndis mcp_slot (eg, 4 bytes total,
943 * no toeplitz hash value returned. Older firmware will
944 * not understand this command, but will use the correct
945 * sized mcp_slot, so we ignore error returns
946 */
947 cmd.data0 = MXGEFW_RSS_MCP_SLOT_TYPE_MIN;
948 (void)myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, &cmd, 0);
0da34b6d
BG		 949
950 /* Now exchange information about interrupts */
951
0dcffac1 952 bytes = mgp->max_intr_slots * sizeof(*mgp->ss[0].rx_done.entry);
0da34b6d
BG		 953 cmd.data0 = (u32) bytes;
954 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
0dcffac1
BG		 955
956 /*
957 * Even though we already know how many slices are supported
958 * via myri10ge_probe_slices() MXGEFW_CMD_GET_MAX_RSS_QUEUES
959 * has magic side effects, and must be called after a reset.
960 * It must be called prior to calling any RSS related cmds,
961 * including assigning an interrupt queue for anything but
962 * slice 0. It must also be called *after*
963 * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
964 * the firmware to compute offsets.
965 */
966
967 if (mgp->num_slices > 1) {
968
969 /* ask the maximum number of slices it supports */
970 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
971 &cmd, 0);
972 if (status != 0) {
973 dev_err(&mgp->pdev->dev,
974 "failed to get number of slices\n");
975 }
976
977 /*
978 * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
979 * to setting up the interrupt queue DMA
980 */
981
982 cmd.data0 = mgp->num_slices;
236bb5e6
BG		 983 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
984 if (mgp->dev->real_num_tx_queues > 1)
985 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
0dcffac1
BG		 986 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
987 &cmd, 0);
236bb5e6
BG		 988
989 /* Firmware older than 1.4.32 only supports multiple
990 * RX queues, so if we get an error, first retry using a
991 * single TX queue before giving up */
992 if (status != 0 && mgp->dev->real_num_tx_queues > 1) {
c9920268 993 netif_set_real_num_tx_queues(mgp->dev, 1);
236bb5e6
BG		 994 cmd.data0 = mgp->num_slices;
995 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
996 status = myri10ge_send_cmd(mgp,
997 MXGEFW_CMD_ENABLE_RSS_QUEUES,
998 &cmd, 0);
999 }
1000
0dcffac1
BG		 1001 if (status != 0) {
1002 dev_err(&mgp->pdev->dev,
1003 "failed to set number of slices\n");
1004
1005 return status;
1006 }
1007 }
1008 for (i = 0; i < mgp->num_slices; i++) {
1009 ss = &mgp->ss[i];
1010 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->rx_done.bus);
1011 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->rx_done.bus);
1012 cmd.data2 = i;
1013 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA,
1014 &cmd, 0);
1015 };
0da34b6d
BG		 1016
1017 status |=
1018 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
0dcffac1
BG		 1019 for (i = 0; i < mgp->num_slices; i++) {
1020 ss = &mgp->ss[i];
1021 ss->irq_claim =
1022 (__iomem __be32 *) (mgp->sram + cmd.data0 + 8 * i);
1023 }
df30a740
BG		 1024 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
1025 &cmd, 0);
1026 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d 1027
0da34b6d
BG		 1028 status |= myri10ge_send_cmd
1029 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
40f6cff5 1030 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d
BG		 1031 if (status != 0) {
1032 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
1033 return status;
1034 }
40f6cff5 1035 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d 1036
5dd2d332 1037#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1038 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_DCA_OFFSET, &cmd, 0);
1039 dca_tag_off = cmd.data0;
1040 for (i = 0; i < mgp->num_slices; i++) {
1041 ss = &mgp->ss[i];
1042 if (status == 0) {
1043 ss->dca_tag = (__iomem __be32 *)
1044 (mgp->sram + dca_tag_off + 4 * i);
1045 } else {
1046 ss->dca_tag = NULL;
1047 }
1048 }
4ee2ac51 1049#endif /* CONFIG_MYRI10GE_DCA */
981813d8 1050
0da34b6d 1051 /* reset mcp/driver shared state back to 0 */
0dcffac1 1052
c58ac5ca 1053 mgp->link_changes = 0;
0dcffac1
BG		 1054 for (i = 0; i < mgp->num_slices; i++) {
1055 ss = &mgp->ss[i];
1056
1057 memset(ss->rx_done.entry, 0, bytes);
1058 ss->tx.req = 0;
1059 ss->tx.done = 0;
1060 ss->tx.pkt_start = 0;
1061 ss->tx.pkt_done = 0;
1062 ss->rx_big.cnt = 0;
1063 ss->rx_small.cnt = 0;
1064 ss->rx_done.idx = 0;
1065 ss->rx_done.cnt = 0;
1066 ss->tx.wake_queue = 0;
1067 ss->tx.stop_queue = 0;
1068 }
1069
0da34b6d 1070 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
0da34b6d 1071 myri10ge_change_pause(mgp, mgp->pause);
2f76216f 1072 myri10ge_set_multicast_list(mgp->dev);
0da34b6d
BG		 1073 return status;
1074}
1075
5dd2d332 1076#ifdef CONFIG_MYRI10GE_DCA
ef09aadf
AG		 1077static int myri10ge_toggle_relaxed(struct pci_dev *pdev, int on)
1078{
1079 int ret, cap, err;
1080 u16 ctl;
1081
1082 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1083 if (!cap)
1084 return 0;
1085
1086 err = pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
1087 ret = (ctl & PCI_EXP_DEVCTL_RELAX_EN) >> 4;
1088 if (ret != on) {
1089 ctl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1090 ctl |= (on << 4);
1091 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
1092 }
1093 return ret;
1094}
1095
981813d8
BG		 1096static void
1097myri10ge_write_dca(struct myri10ge_slice_state *ss, int cpu, int tag)
1098{
981813d8
BG		 1099 ss->cached_dca_tag = tag;
1100 put_be32(htonl(tag), ss->dca_tag);
1101}
1102
1103static inline void myri10ge_update_dca(struct myri10ge_slice_state *ss)
1104{
1105 int cpu = get_cpu();
1106 int tag;
1107
1108 if (cpu != ss->cpu) {
ef09aadf 1109 tag = dca3_get_tag(&ss->mgp->pdev->dev, cpu);
981813d8
BG		 1110 if (ss->cached_dca_tag != tag)
1111 myri10ge_write_dca(ss, cpu, tag);
ef09aadf 1112 ss->cpu = cpu;
981813d8
BG		 1113 }
1114 put_cpu();
1115}
1116
1117static void myri10ge_setup_dca(struct myri10ge_priv *mgp)
1118{
1119 int err, i;
1120 struct pci_dev *pdev = mgp->pdev;
1121
1122 if (mgp->ss[0].dca_tag == NULL || mgp->dca_enabled)
1123 return;
1124 if (!myri10ge_dca) {
1125 dev_err(&pdev->dev, "dca disabled by administrator\n");
1126 return;
1127 }
1128 err = dca_add_requester(&pdev->dev);
1129 if (err) {
330554cb
BG		 1130 if (err != -ENODEV)
1131 dev_err(&pdev->dev,
1132 "dca_add_requester() failed, err=%d\n", err);
981813d8
BG		 1133 return;
1134 }
ef09aadf 1135 mgp->relaxed_order = myri10ge_toggle_relaxed(pdev, 0);
981813d8 1136 mgp->dca_enabled = 1;
ef09aadf
AG		 1137 for (i = 0; i < mgp->num_slices; i++) {
1138 mgp->ss[i].cpu = -1;
1139 mgp->ss[i].cached_dca_tag = -1;
1140 myri10ge_update_dca(&mgp->ss[i]);
1141 }
981813d8
BG		 1142}
1143
1144static void myri10ge_teardown_dca(struct myri10ge_priv *mgp)
1145{
1146 struct pci_dev *pdev = mgp->pdev;
1147 int err;
1148
1149 if (!mgp->dca_enabled)
1150 return;
1151 mgp->dca_enabled = 0;
ef09aadf
AG		 1152 if (mgp->relaxed_order)
1153 myri10ge_toggle_relaxed(pdev, 1);
981813d8
BG		 1154 err = dca_remove_requester(&pdev->dev);
1155}
1156
1157static int myri10ge_notify_dca_device(struct device *dev, void *data)
1158{
1159 struct myri10ge_priv *mgp;
1160 unsigned long event;
1161
1162 mgp = dev_get_drvdata(dev);
1163 event = *(unsigned long *)data;
1164
1165 if (event == DCA_PROVIDER_ADD)
1166 myri10ge_setup_dca(mgp);
1167 else if (event == DCA_PROVIDER_REMOVE)
1168 myri10ge_teardown_dca(mgp);
1169 return 0;
1170}
4ee2ac51 1171#endif /* CONFIG_MYRI10GE_DCA */
981813d8 1172
0da34b6d
BG		 1173static inline void
1174myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
1175 struct mcp_kreq_ether_recv *src)
1176{
40f6cff5 1177 __be32 low;
0da34b6d
BG		 1178
1179 low = src->addr_low;
284901a9 1180 src->addr_low = htonl(DMA_BIT_MASK(32));
e67bda55
BG		 1181 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
1182 mb();
1183 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
0da34b6d
BG		 1184 mb();
1185 src->addr_low = low;
40f6cff5 1186 put_be32(low, &dst->addr_low);
0da34b6d
BG		 1187 mb();
1188}
1189
40f6cff5 1190static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
0da34b6d
BG		 1191{
1192 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
1193
40f6cff5 1194 if ((skb->protocol == htons(ETH_P_8021Q)) &&
0da34b6d
BG		 1195 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
1196 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
1197 skb->csum = hw_csum;
84fa7933 1198 skb->ip_summed = CHECKSUM_COMPLETE;
0da34b6d
BG		 1199 }
1200}
1201
dd50f336
BG		 1202static inline void
1203myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
1204 struct skb_frag_struct *rx_frags, int len, int hlen)
1205{
1206 struct skb_frag_struct *skb_frags;
1207
1208 skb->len = skb->data_len = len;
1209 skb->truesize = len + sizeof(struct sk_buff);
1210 /* attach the page(s) */
1211
1212 skb_frags = skb_shinfo(skb)->frags;
1213 while (len > 0) {
1214 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
1215 len -= rx_frags->size;
1216 skb_frags++;
1217 rx_frags++;
1218 skb_shinfo(skb)->nr_frags++;
1219 }
1220
1221 /* pskb_may_pull is not available in irq context, but
1222 * skb_pull() (for ether_pad and eth_type_trans()) requires
1223 * the beginning of the packet in skb_headlen(), move it
1224 * manually */
27d7ff46 1225 skb_copy_to_linear_data(skb, va, hlen);
dd50f336
BG		 1226 skb_shinfo(skb)->frags[0].page_offset += hlen;
1227 skb_shinfo(skb)->frags[0].size -= hlen;
1228 skb->data_len -= hlen;
1229 skb->tail += hlen;
1230 skb_pull(skb, MXGEFW_PAD);
1231}
1232
1233static void
1234myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1235 int bytes, int watchdog)
1236{
1237 struct page *page;
1238 int idx;
2a3f2790
BG		 1239#if MYRI10GE_ALLOC_SIZE > 4096
1240 int end_offset;
1241#endif
dd50f336
BG		 1242
1243 if (unlikely(rx->watchdog_needed && !watchdog))
1244 return;
1245
1246 /* try to refill entire ring */
1247 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
1248 idx = rx->fill_cnt & rx->mask;
ae8509b1 1249 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
dd50f336
BG		 1250 /* we can use part of previous page */
1251 get_page(rx->page);
1252 } else {
1253 /* we need a new page */
1254 page =
1255 alloc_pages(GFP_ATOMIC | __GFP_COMP,
1256 MYRI10GE_ALLOC_ORDER);
1257 if (unlikely(page == NULL)) {
1258 if (rx->fill_cnt - rx->cnt < 16)
1259 rx->watchdog_needed = 1;
1260 return;
1261 }
1262 rx->page = page;
1263 rx->page_offset = 0;
1264 rx->bus = pci_map_page(mgp->pdev, page, 0,
1265 MYRI10GE_ALLOC_SIZE,
1266 PCI_DMA_FROMDEVICE);
1267 }
1268 rx->info[idx].page = rx->page;
1269 rx->info[idx].page_offset = rx->page_offset;
1270 /* note that this is the address of the start of the
1271 * page */
c755b4b6 1272 dma_unmap_addr_set(&rx->info[idx], bus, rx->bus);
dd50f336
BG		 1273 rx->shadow[idx].addr_low =
1274 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
1275 rx->shadow[idx].addr_high =
1276 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
1277
1278 /* start next packet on a cacheline boundary */
1279 rx->page_offset += SKB_DATA_ALIGN(bytes);
ae8509b1
BG		 1280
1281#if MYRI10GE_ALLOC_SIZE > 4096
1282 /* don't cross a 4KB boundary */
2a3f2790
BG		 1283 end_offset = rx->page_offset + bytes - 1;
1284 if ((unsigned)(rx->page_offset ^ end_offset) > 4095)
1285 rx->page_offset = end_offset & ~4095;
ae8509b1 1286#endif
dd50f336
BG		 1287 rx->fill_cnt++;
1288
1289 /* copy 8 descriptors to the firmware at a time */
1290 if ((idx & 7) == 7) {
e454e7e2
BG		 1291 myri10ge_submit_8rx(&rx->lanai[idx - 7],
1292 &rx->shadow[idx - 7]);
dd50f336
BG		 1293 }
1294 }
1295}
1296
1297static inline void
1298myri10ge_unmap_rx_page(struct pci_dev *pdev,
1299 struct myri10ge_rx_buffer_state *info, int bytes)
1300{
1301 /* unmap the recvd page if we're the only or last user of it */
1302 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1303 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
c755b4b6 1304 pci_unmap_page(pdev, (dma_unmap_addr(info, bus)
dd50f336
BG		 1305 & ~(MYRI10GE_ALLOC_SIZE - 1)),
1306 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1307 }
1308}
1309
1310#define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
1311 * page into an skb */
1312
1313static inline int
b3cd9657
SG		 1314myri10ge_rx_done(struct myri10ge_slice_state *ss, int len, __wsum csum,
1315 int lro_enabled)
dd50f336 1316{
b53bef84 1317 struct myri10ge_priv *mgp = ss->mgp;
dd50f336
BG		 1318 struct sk_buff *skb;
1319 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
b3cd9657
SG		 1320 struct myri10ge_rx_buf *rx;
1321 int i, idx, hlen, remainder, bytes;
dd50f336
BG		 1322 struct pci_dev *pdev = mgp->pdev;
1323 struct net_device *dev = mgp->dev;
1324 u8 *va;
1325
b3cd9657
SG		 1326 if (len <= mgp->small_bytes) {
1327 rx = &ss->rx_small;
1328 bytes = mgp->small_bytes;
1329 } else {
1330 rx = &ss->rx_big;
1331 bytes = mgp->big_bytes;
1332 }
1333
dd50f336
BG		 1334 len += MXGEFW_PAD;
1335 idx = rx->cnt & rx->mask;
1336 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1337 prefetch(va);
1338 /* Fill skb_frag_struct(s) with data from our receive */
1339 for (i = 0, remainder = len; remainder > 0; i++) {
1340 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1341 rx_frags[i].page = rx->info[idx].page;
1342 rx_frags[i].page_offset = rx->info[idx].page_offset;
1343 if (remainder < MYRI10GE_ALLOC_SIZE)
1344 rx_frags[i].size = remainder;
1345 else
1346 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1347 rx->cnt++;
1348 idx = rx->cnt & rx->mask;
1349 remainder -= MYRI10GE_ALLOC_SIZE;
1350 }
1351
b3cd9657 1352 if (lro_enabled) {
1e6e9342
AG		 1353 rx_frags[0].page_offset += MXGEFW_PAD;
1354 rx_frags[0].size -= MXGEFW_PAD;
1355 len -= MXGEFW_PAD;
b53bef84 1356 lro_receive_frags(&ss->rx_done.lro_mgr, rx_frags,
b53bef84 1357 /* opaque, will come back in get_frag_header */
0dcffac1 1358 len, len,
b53bef84 1359 (void *)(__force unsigned long)csum, csum);
0dcffac1 1360
1e6e9342
AG		 1361 return 1;
1362 }
1363
dd50f336
BG		 1364 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1365
e636b2ea
BG		 1366 /* allocate an skb to attach the page(s) to. This is done
1367 * after trying LRO, so as to avoid skb allocation overheads */
dd50f336
BG		 1368
1369 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1370 if (unlikely(skb == NULL)) {
d6279c88 1371 ss->stats.rx_dropped++;
dd50f336
BG		 1372 do {
1373 i--;
1374 put_page(rx_frags[i].page);
1375 } while (i != 0);
1376 return 0;
1377 }
1378
1379 /* Attach the pages to the skb, and trim off any padding */
1380 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1381 if (skb_shinfo(skb)->frags[0].size <= 0) {
1382 put_page(skb_shinfo(skb)->frags[0].page);
1383 skb_shinfo(skb)->nr_frags = 0;
1384 }
1385 skb->protocol = eth_type_trans(skb, dev);
0c8dfc83 1386 skb_record_rx_queue(skb, ss - &mgp->ss[0]);
dd50f336 1387
47c2cdf5 1388 if (dev->features & NETIF_F_RXCSUM) {
dd50f336
BG		 1389 if ((skb->protocol == htons(ETH_P_IP)) ||
1390 (skb->protocol == htons(ETH_P_IPV6))) {
1391 skb->csum = csum;
1392 skb->ip_summed = CHECKSUM_COMPLETE;
1393 } else
1394 myri10ge_vlan_ip_csum(skb, csum);
1395 }
1396 netif_receive_skb(skb);
dd50f336
BG		 1397 return 1;
1398}
1399
b53bef84
BG		 1400static inline void
1401myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index)
0da34b6d 1402{
b53bef84
BG		 1403 struct pci_dev *pdev = ss->mgp->pdev;
1404 struct myri10ge_tx_buf *tx = &ss->tx;
236bb5e6 1405 struct netdev_queue *dev_queue;
0da34b6d
BG		 1406 struct sk_buff *skb;
1407 int idx, len;
0da34b6d
BG		 1408
1409 while (tx->pkt_done != mcp_index) {
1410 idx = tx->done & tx->mask;
1411 skb = tx->info[idx].skb;
1412
1413 /* Mark as free */
1414 tx->info[idx].skb = NULL;
1415 if (tx->info[idx].last) {
1416 tx->pkt_done++;
1417 tx->info[idx].last = 0;
1418 }
1419 tx->done++;
c755b4b6
FT		 1420 len = dma_unmap_len(&tx->info[idx], len);
1421 dma_unmap_len_set(&tx->info[idx], len, 0);
0da34b6d 1422 if (skb) {
b53bef84
BG		 1423 ss->stats.tx_bytes += skb->len;
1424 ss->stats.tx_packets++;
0da34b6d
BG		 1425 dev_kfree_skb_irq(skb);
1426 if (len)
1427 pci_unmap_single(pdev,
c755b4b6 1428 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 1429 bus), len,
1430 PCI_DMA_TODEVICE);
1431 } else {
1432 if (len)
1433 pci_unmap_page(pdev,
c755b4b6 1434 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 1435 bus), len,
1436 PCI_DMA_TODEVICE);
1437 }
0da34b6d 1438 }
236bb5e6
BG		 1439
1440 dev_queue = netdev_get_tx_queue(ss->dev, ss - ss->mgp->ss);
1441 /*
1442 * Make a minimal effort to prevent the NIC from polling an
1443 * idle tx queue. If we can't get the lock we leave the queue
1444 * active. In this case, either a thread was about to start
1445 * using the queue anyway, or we lost a race and the NIC will
1446 * waste some of its resources polling an inactive queue for a
1447 * while.
1448 */
1449
1450 if ((ss->mgp->dev->real_num_tx_queues > 1) &&
1451 __netif_tx_trylock(dev_queue)) {
1452 if (tx->req == tx->done) {
1453 tx->queue_active = 0;
1454 put_be32(htonl(1), tx->send_stop);
8c2f5fa5 1455 mb();
6824a105 1456 mmiowb();
236bb5e6
BG		 1457 }
1458 __netif_tx_unlock(dev_queue);
1459 }
1460
0da34b6d 1461 /* start the queue if we've stopped it */
8e95a202
JP		 1462 if (netif_tx_queue_stopped(dev_queue) &&
1463 tx->req - tx->done < (tx->mask >> 1)) {
b53bef84 1464 tx->wake_queue++;
236bb5e6 1465 netif_tx_wake_queue(dev_queue);
0da34b6d
BG		 1466 }
1467}
1468
b53bef84
BG		 1469static inline int
1470myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
0da34b6d 1471{
b53bef84
BG		 1472 struct myri10ge_rx_done *rx_done = &ss->rx_done;
1473 struct myri10ge_priv *mgp = ss->mgp;
b3cd9657 1474
0da34b6d
BG		 1475 unsigned long rx_bytes = 0;
1476 unsigned long rx_packets = 0;
1477 unsigned long rx_ok;
1478
1479 int idx = rx_done->idx;
1480 int cnt = rx_done->cnt;
bea3348e 1481 int work_done = 0;
0da34b6d 1482 u16 length;
40f6cff5 1483 __wsum checksum;
0da34b6d 1484
b3cd9657
SG		 1485 /*
1486 * Prevent compiler from generating more than one ->features memory
1487 * access to avoid theoretical race condition with functions that
1488 * change NETIF_F_LRO flag at runtime.
1489 */
1490 bool lro_enabled = ACCESS_ONCE(mgp->dev->features) & NETIF_F_LRO;
1491
c956a240 1492 while (rx_done->entry[idx].length != 0 && work_done < budget) {
0da34b6d
BG		 1493 length = ntohs(rx_done->entry[idx].length);
1494 rx_done->entry[idx].length = 0;
40f6cff5 1495 checksum = csum_unfold(rx_done->entry[idx].checksum);
b3cd9657 1496 rx_ok = myri10ge_rx_done(ss, length, checksum, lro_enabled);
0da34b6d
BG		 1497 rx_packets += rx_ok;
1498 rx_bytes += rx_ok * (unsigned long)length;
1499 cnt++;
014377a1 1500 idx = cnt & (mgp->max_intr_slots - 1);
c956a240 1501 work_done++;
0da34b6d
BG		 1502 }
1503 rx_done->idx = idx;
1504 rx_done->cnt = cnt;
b53bef84
BG		 1505 ss->stats.rx_packets += rx_packets;
1506 ss->stats.rx_bytes += rx_bytes;
c7dab99b 1507
b3cd9657 1508 if (lro_enabled)
1e6e9342
AG		 1509 lro_flush_all(&rx_done->lro_mgr);
1510
c7dab99b 1511 /* restock receive rings if needed */
b53bef84
BG		 1512 if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
1513 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
c7dab99b 1514 mgp->small_bytes + MXGEFW_PAD, 0);
b53bef84
BG		 1515 if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh)
1516 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
c7dab99b 1517
bea3348e 1518 return work_done;
0da34b6d
BG		 1519}
1520
1521static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1522{
0dcffac1 1523 struct mcp_irq_data *stats = mgp->ss[0].fw_stats;
0da34b6d
BG		 1524
1525 if (unlikely(stats->stats_updated)) {
798a95db
BG		 1526 unsigned link_up = ntohl(stats->link_up);
1527 if (mgp->link_state != link_up) {
1528 mgp->link_state = link_up;
1529
1530 if (mgp->link_state == MXGEFW_LINK_UP) {
c58ac5ca 1531 if (netif_msg_link(mgp))
78ca90ea 1532 netdev_info(mgp->dev, "link up\n");
0da34b6d 1533 netif_carrier_on(mgp->dev);
c58ac5ca 1534 mgp->link_changes++;
0da34b6d 1535 } else {
c58ac5ca 1536 if (netif_msg_link(mgp))
78ca90ea
JP		 1537 netdev_info(mgp->dev, "link %s\n",
1538 link_up == MXGEFW_LINK_MYRINET ?
1539 "mismatch (Myrinet detected)" :
1540 "down");
0da34b6d 1541 netif_carrier_off(mgp->dev);
c58ac5ca 1542 mgp->link_changes++;
0da34b6d
BG		 1543 }
1544 }
1545 if (mgp->rdma_tags_available !=
b53bef84 1546 ntohl(stats->rdma_tags_available)) {
0da34b6d 1547 mgp->rdma_tags_available =
b53bef84 1548 ntohl(stats->rdma_tags_available);
78ca90ea
JP		 1549 netdev_warn(mgp->dev, "RDMA timed out! %d tags left\n",
1550 mgp->rdma_tags_available);
0da34b6d
BG		 1551 }
1552 mgp->down_cnt += stats->link_down;
1553 if (stats->link_down)
1554 wake_up(&mgp->down_wq);
1555 }
1556}
1557
bea3348e 1558static int myri10ge_poll(struct napi_struct *napi, int budget)
0da34b6d 1559{
b53bef84
BG		 1560 struct myri10ge_slice_state *ss =
1561 container_of(napi, struct myri10ge_slice_state, napi);
bea3348e 1562 int work_done;
0da34b6d 1563
5dd2d332 1564#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1565 if (ss->mgp->dca_enabled)
1566 myri10ge_update_dca(ss);
1567#endif
1568
0da34b6d 1569 /* process as many rx events as NAPI will allow */
b53bef84 1570 work_done = myri10ge_clean_rx_done(ss, budget);
0da34b6d 1571
4ec24119 1572 if (work_done < budget) {
288379f0 1573 napi_complete(napi);
b53bef84 1574 put_be32(htonl(3), ss->irq_claim);
0da34b6d 1575 }
bea3348e 1576 return work_done;
0da34b6d
BG		 1577}
1578
7d12e780 1579static irqreturn_t myri10ge_intr(int irq, void *arg)
0da34b6d 1580{
b53bef84
BG		 1581 struct myri10ge_slice_state *ss = arg;
1582 struct myri10ge_priv *mgp = ss->mgp;
1583 struct mcp_irq_data *stats = ss->fw_stats;
1584 struct myri10ge_tx_buf *tx = &ss->tx;
0da34b6d
BG		 1585 u32 send_done_count;
1586 int i;
1587
236bb5e6
BG		 1588 /* an interrupt on a non-zero receive-only slice is implicitly
1589 * valid since MSI-X irqs are not shared */
1590 if ((mgp->dev->real_num_tx_queues == 1) && (ss != mgp->ss)) {
288379f0 1591 napi_schedule(&ss->napi);
807540ba 1592 return IRQ_HANDLED;
0dcffac1
BG		 1593 }
1594
0da34b6d
BG		 1595 /* make sure it is our IRQ, and that the DMA has finished */
1596 if (unlikely(!stats->valid))
807540ba 1597 return IRQ_NONE;
0da34b6d
BG		 1598
1599 /* low bit indicates receives are present, so schedule
1600 * napi poll handler */
1601 if (stats->valid & 1)
288379f0 1602 napi_schedule(&ss->napi);
0da34b6d 1603
0dcffac1 1604 if (!mgp->msi_enabled && !mgp->msix_enabled) {
40f6cff5 1605 put_be32(0, mgp->irq_deassert);
0da34b6d
BG		 1606 if (!myri10ge_deassert_wait)
1607 stats->valid = 0;
1608 mb();
1609 } else
1610 stats->valid = 0;
1611
1612 /* Wait for IRQ line to go low, if using INTx */
1613 i = 0;
1614 while (1) {
1615 i++;
1616 /* check for transmit completes and receives */
1617 send_done_count = ntohl(stats->send_done_count);
1618 if (send_done_count != tx->pkt_done)
b53bef84 1619 myri10ge_tx_done(ss, (int)send_done_count);
0da34b6d 1620 if (unlikely(i > myri10ge_max_irq_loops)) {
78ca90ea 1621 netdev_err(mgp->dev, "irq stuck?\n");
0da34b6d
BG		 1622 stats->valid = 0;
1623 schedule_work(&mgp->watchdog_work);
1624 }
1625 if (likely(stats->valid == 0))
1626 break;
1627 cpu_relax();
1628 barrier();
1629 }
1630
236bb5e6
BG		 1631 /* Only slice 0 updates stats */
1632 if (ss == mgp->ss)
1633 myri10ge_check_statblock(mgp);
0da34b6d 1634
b53bef84 1635 put_be32(htonl(3), ss->irq_claim + 1);
807540ba 1636 return IRQ_HANDLED;
0da34b6d
BG		 1637}
1638
1639static int
1640myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1641{
c0bf8801
BG		 1642 struct myri10ge_priv *mgp = netdev_priv(netdev);
1643 char *ptr;
1644 int i;
1645
0da34b6d 1646 cmd->autoneg = AUTONEG_DISABLE;
70739497 1647 ethtool_cmd_speed_set(cmd, SPEED_10000);
0da34b6d 1648 cmd->duplex = DUPLEX_FULL;
c0bf8801
BG		 1649
1650 /*
1651 * parse the product code to deterimine the interface type
1652 * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1653 * after the 3rd dash in the driver's cached copy of the
1654 * EEPROM's product code string.
1655 */
1656 ptr = mgp->product_code_string;
1657 if (ptr == NULL) {
78ca90ea 1658 netdev_err(netdev, "Missing product code\n");
c0bf8801
BG		 1659 return 0;
1660 }
1661 for (i = 0; i < 3; i++, ptr++) {
1662 ptr = strchr(ptr, '-');
1663 if (ptr == NULL) {
78ca90ea
JP		 1664 netdev_err(netdev, "Invalid product code %s\n",
1665 mgp->product_code_string);
c0bf8801
BG		 1666 return 0;
1667 }
1668 }
196f17eb
BG		 1669 if (*ptr == '2')
1670 ptr++;
1671 if (*ptr == 'R' || *ptr == 'Q' || *ptr == 'S') {
1672 /* We've found either an XFP, quad ribbon fiber, or SFP+ */
c0bf8801 1673 cmd->port = PORT_FIBRE;
196f17eb
BG		 1674 cmd->supported |= SUPPORTED_FIBRE;
1675 cmd->advertising |= ADVERTISED_FIBRE;
1676 } else {
1677 cmd->port = PORT_OTHER;
c0bf8801 1678 }
196f17eb
BG		 1679 if (*ptr == 'R' || *ptr == 'S')
1680 cmd->transceiver = XCVR_EXTERNAL;
1681 else
1682 cmd->transceiver = XCVR_INTERNAL;
1683
0da34b6d
BG		 1684 return 0;
1685}
1686
1687static void
1688myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1689{
1690 struct myri10ge_priv *mgp = netdev_priv(netdev);
1691
1692 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1693 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1694 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1695 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1696}
1697
1698static int
1699myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1700{
1701 struct myri10ge_priv *mgp = netdev_priv(netdev);
99f5f87e 1702
0da34b6d
BG		 1703 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1704 return 0;
1705}
1706
1707static int
1708myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1709{
1710 struct myri10ge_priv *mgp = netdev_priv(netdev);
1711
1712 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
40f6cff5 1713 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 1714 return 0;
1715}
1716
1717static void
1718myri10ge_get_pauseparam(struct net_device *netdev,
1719 struct ethtool_pauseparam *pause)
1720{
1721 struct myri10ge_priv *mgp = netdev_priv(netdev);
1722
1723 pause->autoneg = 0;
1724 pause->rx_pause = mgp->pause;
1725 pause->tx_pause = mgp->pause;
1726}
1727
1728static int
1729myri10ge_set_pauseparam(struct net_device *netdev,
1730 struct ethtool_pauseparam *pause)
1731{
1732 struct myri10ge_priv *mgp = netdev_priv(netdev);
1733
1734 if (pause->tx_pause != mgp->pause)
1735 return myri10ge_change_pause(mgp, pause->tx_pause);
1736 if (pause->rx_pause != mgp->pause)
2488f56d 1737 return myri10ge_change_pause(mgp, pause->rx_pause);
0da34b6d
BG		 1738 if (pause->autoneg != 0)
1739 return -EINVAL;
1740 return 0;
1741}
1742
1743static void
1744myri10ge_get_ringparam(struct net_device *netdev,
1745 struct ethtool_ringparam *ring)
1746{
1747 struct myri10ge_priv *mgp = netdev_priv(netdev);
1748
0dcffac1
BG		 1749 ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1;
1750 ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1;
0da34b6d 1751 ring->rx_jumbo_max_pending = 0;
6498be3f 1752 ring->tx_max_pending = mgp->ss[0].tx.mask + 1;
0da34b6d
BG		 1753 ring->rx_mini_pending = ring->rx_mini_max_pending;
1754 ring->rx_pending = ring->rx_max_pending;
1755 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1756 ring->tx_pending = ring->tx_max_pending;
1757}
1758
b53bef84 1759static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
0da34b6d
BG		 1760 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1761 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1762 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1763 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1764 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1765 "tx_heartbeat_errors", "tx_window_errors",
1766 /* device-specific stats */
0dcffac1 1767 "tx_boundary", "WC", "irq", "MSI", "MSIX",
0da34b6d 1768 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
b53bef84 1769 "serial_number", "watchdog_resets",
5dd2d332 1770#ifdef CONFIG_MYRI10GE_DCA
9a6b3b54 1771 "dca_capable_firmware", "dca_device_present",
981813d8 1772#endif
c58ac5ca 1773 "link_changes", "link_up", "dropped_link_overflow",
cee505db
BG		 1774 "dropped_link_error_or_filtered",
1775 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1776 "dropped_unicast_filtered", "dropped_multicast_filtered",
0da34b6d 1777 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
b53bef84
BG		 1778 "dropped_no_big_buffer"
1779};
1780
1781static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1782 "----------- slice ---------",
1783 "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1784 "rx_small_cnt", "rx_big_cnt",
1785 "wake_queue", "stop_queue", "tx_linearized", "LRO aggregated",
1786 "LRO flushed",
1e6e9342 1787 "LRO avg aggr", "LRO no_desc"
0da34b6d
BG		 1788};
1789
1790#define MYRI10GE_NET_STATS_LEN 21
b53bef84
BG		 1791#define MYRI10GE_MAIN_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_main_stats)
1792#define MYRI10GE_SLICE_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_slice_stats)
0da34b6d
BG		 1793
1794static void
1795myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1796{
0dcffac1
BG		 1797 struct myri10ge_priv *mgp = netdev_priv(netdev);
1798 int i;
1799
0da34b6d
BG		 1800 switch (stringset) {
1801 case ETH_SS_STATS:
b53bef84
BG		 1802 memcpy(data, *myri10ge_gstrings_main_stats,
1803 sizeof(myri10ge_gstrings_main_stats));
1804 data += sizeof(myri10ge_gstrings_main_stats);
0dcffac1
BG		 1805 for (i = 0; i < mgp->num_slices; i++) {
1806 memcpy(data, *myri10ge_gstrings_slice_stats,
1807 sizeof(myri10ge_gstrings_slice_stats));
1808 data += sizeof(myri10ge_gstrings_slice_stats);
1809 }
0da34b6d
BG		 1810 break;
1811 }
1812}
1813
b9f2c044 1814static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
0da34b6d 1815{
0dcffac1
BG		 1816 struct myri10ge_priv *mgp = netdev_priv(netdev);
1817
b9f2c044
JG		 1818 switch (sset) {
1819 case ETH_SS_STATS:
0dcffac1
BG		 1820 return MYRI10GE_MAIN_STATS_LEN +
1821 mgp->num_slices * MYRI10GE_SLICE_STATS_LEN;
b9f2c044
JG		 1822 default:
1823 return -EOPNOTSUPP;
1824 }
0da34b6d
BG		 1825}
1826
1827static void
1828myri10ge_get_ethtool_stats(struct net_device *netdev,
1829 struct ethtool_stats *stats, u64 * data)
1830{
1831 struct myri10ge_priv *mgp = netdev_priv(netdev);
b53bef84 1832 struct myri10ge_slice_state *ss;
0dcffac1 1833 int slice;
0da34b6d
BG		 1834 int i;
1835
59081825
BG		 1836 /* force stats update */
1837 (void)myri10ge_get_stats(netdev);
0da34b6d 1838 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
6dc34941 1839 data[i] = ((unsigned long *)&netdev->stats)[i];
0da34b6d 1840
b53bef84 1841 data[i++] = (unsigned int)mgp->tx_boundary;
276e26c3 1842 data[i++] = (unsigned int)mgp->wc_enabled;
2c1a1088
BG		 1843 data[i++] = (unsigned int)mgp->pdev->irq;
1844 data[i++] = (unsigned int)mgp->msi_enabled;
0dcffac1 1845 data[i++] = (unsigned int)mgp->msix_enabled;
0da34b6d
BG		 1846 data[i++] = (unsigned int)mgp->read_dma;
1847 data[i++] = (unsigned int)mgp->write_dma;
1848 data[i++] = (unsigned int)mgp->read_write_dma;
1849 data[i++] = (unsigned int)mgp->serial_number;
0da34b6d 1850 data[i++] = (unsigned int)mgp->watchdog_resets;
5dd2d332 1851#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1852 data[i++] = (unsigned int)(mgp->ss[0].dca_tag != NULL);
1853 data[i++] = (unsigned int)(mgp->dca_enabled);
1854#endif
c58ac5ca 1855 data[i++] = (unsigned int)mgp->link_changes;
b53bef84
BG		 1856
1857 /* firmware stats are useful only in the first slice */
0dcffac1 1858 ss = &mgp->ss[0];
b53bef84
BG		 1859 data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1860 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
cee505db 1861 data[i++] =
b53bef84
BG		 1862 (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered);
1863 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause);
1864 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy);
1865 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32);
1866 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered);
85a7ea1b 1867 data[i++] =
b53bef84
BG		 1868 (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered);
1869 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt);
1870 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun);
1871 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
1872 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
1873
0dcffac1
BG		 1874 for (slice = 0; slice < mgp->num_slices; slice++) {
1875 ss = &mgp->ss[slice];
1876 data[i++] = slice;
1877 data[i++] = (unsigned int)ss->tx.pkt_start;
1878 data[i++] = (unsigned int)ss->tx.pkt_done;
1879 data[i++] = (unsigned int)ss->tx.req;
1880 data[i++] = (unsigned int)ss->tx.done;
1881 data[i++] = (unsigned int)ss->rx_small.cnt;
1882 data[i++] = (unsigned int)ss->rx_big.cnt;
1883 data[i++] = (unsigned int)ss->tx.wake_queue;
1884 data[i++] = (unsigned int)ss->tx.stop_queue;
1885 data[i++] = (unsigned int)ss->tx.linearized;
1886 data[i++] = ss->rx_done.lro_mgr.stats.aggregated;
1887 data[i++] = ss->rx_done.lro_mgr.stats.flushed;
1888 if (ss->rx_done.lro_mgr.stats.flushed)
1889 data[i++] = ss->rx_done.lro_mgr.stats.aggregated /
1890 ss->rx_done.lro_mgr.stats.flushed;
1891 else
1892 data[i++] = 0;
1893 data[i++] = ss->rx_done.lro_mgr.stats.no_desc;
1894 }
0da34b6d
BG		 1895}
1896
c58ac5ca
BG		 1897static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1898{
1899 struct myri10ge_priv *mgp = netdev_priv(netdev);
1900 mgp->msg_enable = value;
1901}
1902
1903static u32 myri10ge_get_msglevel(struct net_device *netdev)
1904{
1905 struct myri10ge_priv *mgp = netdev_priv(netdev);
1906 return mgp->msg_enable;
1907}
1908
7282d491 1909static const struct ethtool_ops myri10ge_ethtool_ops = {
0da34b6d
BG		 1910 .get_settings = myri10ge_get_settings,
1911 .get_drvinfo = myri10ge_get_drvinfo,
1912 .get_coalesce = myri10ge_get_coalesce,
1913 .set_coalesce = myri10ge_set_coalesce,
1914 .get_pauseparam = myri10ge_get_pauseparam,
1915 .set_pauseparam = myri10ge_set_pauseparam,
1916 .get_ringparam = myri10ge_get_ringparam,
6ffdd071 1917 .get_link = ethtool_op_get_link,
0da34b6d 1918 .get_strings = myri10ge_get_strings,
b9f2c044 1919 .get_sset_count = myri10ge_get_sset_count,
c58ac5ca
BG		 1920 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1921 .set_msglevel = myri10ge_set_msglevel,
3a0c7d2d 1922 .get_msglevel = myri10ge_get_msglevel,
0da34b6d
BG		 1923};
1924
b53bef84 1925static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
0da34b6d 1926{
b53bef84 1927 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d 1928 struct myri10ge_cmd cmd;
b53bef84 1929 struct net_device *dev = mgp->dev;
0da34b6d
BG		 1930 int tx_ring_size, rx_ring_size;
1931 int tx_ring_entries, rx_ring_entries;
0dcffac1 1932 int i, slice, status;
0da34b6d
BG		 1933 size_t bytes;
1934
0da34b6d 1935 /* get ring sizes */
0dcffac1
BG		 1936 slice = ss - mgp->ss;
1937 cmd.data0 = slice;
0da34b6d
BG		 1938 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1939 tx_ring_size = cmd.data0;
0dcffac1 1940 cmd.data0 = slice;
0da34b6d 1941 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
355c7265
BG		 1942 if (status != 0)
1943 return status;
0da34b6d
BG		 1944 rx_ring_size = cmd.data0;
1945
1946 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1947 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
b53bef84
BG		 1948 ss->tx.mask = tx_ring_entries - 1;
1949 ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
0da34b6d 1950
355c7265
BG		 1951 status = -ENOMEM;
1952
0da34b6d
BG		 1953 /* allocate the host shadow rings */
1954
1955 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
b53bef84
BG		 1956 * sizeof(*ss->tx.req_list);
1957 ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1958 if (ss->tx.req_bytes == NULL)
0da34b6d
BG		 1959 goto abort_with_nothing;
1960
1961 /* ensure req_list entries are aligned to 8 bytes */
b53bef84
BG		 1962 ss->tx.req_list = (struct mcp_kreq_ether_send *)
1963 ALIGN((unsigned long)ss->tx.req_bytes, 8);
236bb5e6 1964 ss->tx.queue_active = 0;
0da34b6d 1965
b53bef84
BG		 1966 bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow);
1967 ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1968 if (ss->rx_small.shadow == NULL)
0da34b6d
BG		 1969 goto abort_with_tx_req_bytes;
1970
b53bef84
BG		 1971 bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow);
1972 ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1973 if (ss->rx_big.shadow == NULL)
0da34b6d
BG		 1974 goto abort_with_rx_small_shadow;
1975
1976 /* allocate the host info rings */
1977
b53bef84
BG		 1978 bytes = tx_ring_entries * sizeof(*ss->tx.info);
1979 ss->tx.info = kzalloc(bytes, GFP_KERNEL);
1980 if (ss->tx.info == NULL)
0da34b6d
BG		 1981 goto abort_with_rx_big_shadow;
1982
b53bef84
BG		 1983 bytes = rx_ring_entries * sizeof(*ss->rx_small.info);
1984 ss->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1985 if (ss->rx_small.info == NULL)
0da34b6d
BG		 1986 goto abort_with_tx_info;
1987
b53bef84
BG		 1988 bytes = rx_ring_entries * sizeof(*ss->rx_big.info);
1989 ss->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1990 if (ss->rx_big.info == NULL)
0da34b6d
BG		 1991 goto abort_with_rx_small_info;
1992
1993 /* Fill the receive rings */
b53bef84
BG		 1994 ss->rx_big.cnt = 0;
1995 ss->rx_small.cnt = 0;
1996 ss->rx_big.fill_cnt = 0;
1997 ss->rx_small.fill_cnt = 0;
1998 ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1999 ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
2000 ss->rx_small.watchdog_needed = 0;
2001 ss->rx_big.watchdog_needed = 0;
2002 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
c7dab99b 2003 mgp->small_bytes + MXGEFW_PAD, 0);
0da34b6d 2004
b53bef84 2005 if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
78ca90ea
JP		 2006 netdev_err(dev, "slice-%d: alloced only %d small bufs\n",
2007 slice, ss->rx_small.fill_cnt);
c7dab99b 2008 goto abort_with_rx_small_ring;
0da34b6d
BG		 2009 }
2010
b53bef84
BG		 2011 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
2012 if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
78ca90ea
JP		 2013 netdev_err(dev, "slice-%d: alloced only %d big bufs\n",
2014 slice, ss->rx_big.fill_cnt);
c7dab99b 2015 goto abort_with_rx_big_ring;
0da34b6d
BG		 2016 }
2017
2018 return 0;
2019
2020abort_with_rx_big_ring:
b53bef84
BG		 2021 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2022 int idx = i & ss->rx_big.mask;
2023 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 2024 mgp->big_bytes);
b53bef84 2025 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 2026 }
2027
2028abort_with_rx_small_ring:
b53bef84
BG		 2029 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2030 int idx = i & ss->rx_small.mask;
2031 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 2032 mgp->small_bytes + MXGEFW_PAD);
b53bef84 2033 put_page(ss->rx_small.info[idx].page);
0da34b6d 2034 }
c7dab99b 2035
b53bef84 2036 kfree(ss->rx_big.info);
0da34b6d
BG		 2037
2038abort_with_rx_small_info:
b53bef84 2039 kfree(ss->rx_small.info);
0da34b6d
BG		 2040
2041abort_with_tx_info:
b53bef84 2042 kfree(ss->tx.info);
0da34b6d
BG		 2043
2044abort_with_rx_big_shadow:
b53bef84 2045 kfree(ss->rx_big.shadow);
0da34b6d
BG		 2046
2047abort_with_rx_small_shadow:
b53bef84 2048 kfree(ss->rx_small.shadow);
0da34b6d
BG		 2049
2050abort_with_tx_req_bytes:
b53bef84
BG		 2051 kfree(ss->tx.req_bytes);
2052 ss->tx.req_bytes = NULL;
2053 ss->tx.req_list = NULL;
0da34b6d
BG		 2054
2055abort_with_nothing:
2056 return status;
2057}
2058
b53bef84 2059static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
0da34b6d 2060{
b53bef84 2061 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d
BG		 2062 struct sk_buff *skb;
2063 struct myri10ge_tx_buf *tx;
2064 int i, len, idx;
2065
0dcffac1
BG		 2066 /* If not allocated, skip it */
2067 if (ss->tx.req_list == NULL)
2068 return;
2069
b53bef84
BG		 2070 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2071 idx = i & ss->rx_big.mask;
2072 if (i == ss->rx_big.fill_cnt - 1)
2073 ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
2074 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 2075 mgp->big_bytes);
b53bef84 2076 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 2077 }
2078
b53bef84
BG		 2079 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2080 idx = i & ss->rx_small.mask;
2081 if (i == ss->rx_small.fill_cnt - 1)
2082 ss->rx_small.info[idx].page_offset =
c7dab99b 2083 MYRI10GE_ALLOC_SIZE;
b53bef84 2084 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 2085 mgp->small_bytes + MXGEFW_PAD);
b53bef84 2086 put_page(ss->rx_small.info[idx].page);
c7dab99b 2087 }
b53bef84 2088 tx = &ss->tx;
0da34b6d
BG		 2089 while (tx->done != tx->req) {
2090 idx = tx->done & tx->mask;
2091 skb = tx->info[idx].skb;
2092
2093 /* Mark as free */
2094 tx->info[idx].skb = NULL;
2095 tx->done++;
c755b4b6
FT		 2096 len = dma_unmap_len(&tx->info[idx], len);
2097 dma_unmap_len_set(&tx->info[idx], len, 0);
0da34b6d 2098 if (skb) {
b53bef84 2099 ss->stats.tx_dropped++;
0da34b6d
BG		 2100 dev_kfree_skb_any(skb);
2101 if (len)
2102 pci_unmap_single(mgp->pdev,
c755b4b6 2103 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 2104 bus), len,
2105 PCI_DMA_TODEVICE);
2106 } else {
2107 if (len)
2108 pci_unmap_page(mgp->pdev,
c755b4b6 2109 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 2110 bus), len,
2111 PCI_DMA_TODEVICE);
2112 }
2113 }
b53bef84 2114 kfree(ss->rx_big.info);
0da34b6d 2115
b53bef84 2116 kfree(ss->rx_small.info);
0da34b6d 2117
b53bef84 2118 kfree(ss->tx.info);
0da34b6d 2119
b53bef84 2120 kfree(ss->rx_big.shadow);
0da34b6d 2121
b53bef84 2122 kfree(ss->rx_small.shadow);
0da34b6d 2123
b53bef84
BG		 2124 kfree(ss->tx.req_bytes);
2125 ss->tx.req_bytes = NULL;
2126 ss->tx.req_list = NULL;
0da34b6d
BG		 2127}
2128
df30a740
BG		 2129static int myri10ge_request_irq(struct myri10ge_priv *mgp)
2130{
2131 struct pci_dev *pdev = mgp->pdev;
0dcffac1
BG		 2132 struct myri10ge_slice_state *ss;
2133 struct net_device *netdev = mgp->dev;
2134 int i;
df30a740
BG		 2135 int status;
2136
0dcffac1
BG		 2137 mgp->msi_enabled = 0;
2138 mgp->msix_enabled = 0;
2139 status = 0;
df30a740 2140 if (myri10ge_msi) {
0dcffac1
BG		 2141 if (mgp->num_slices > 1) {
2142 status =
2143 pci_enable_msix(pdev, mgp->msix_vectors,
2144 mgp->num_slices);
2145 if (status == 0) {
2146 mgp->msix_enabled = 1;
2147 } else {
2148 dev_err(&pdev->dev,
2149 "Error %d setting up MSI-X\n", status);
2150 return status;
2151 }
2152 }
2153 if (mgp->msix_enabled == 0) {
2154 status = pci_enable_msi(pdev);
2155 if (status != 0) {
2156 dev_err(&pdev->dev,
2157 "Error %d setting up MSI; falling back to xPIC\n",
2158 status);
2159 } else {
2160 mgp->msi_enabled = 1;
2161 }
2162 }
df30a740 2163 }
0dcffac1
BG		 2164 if (mgp->msix_enabled) {
2165 for (i = 0; i < mgp->num_slices; i++) {
2166 ss = &mgp->ss[i];
2167 snprintf(ss->irq_desc, sizeof(ss->irq_desc),
2168 "%s:slice-%d", netdev->name, i);
2169 status = request_irq(mgp->msix_vectors[i].vector,
2170 myri10ge_intr, 0, ss->irq_desc,
2171 ss);
2172 if (status != 0) {
2173 dev_err(&pdev->dev,
2174 "slice %d failed to allocate IRQ\n", i);
2175 i--;
2176 while (i >= 0) {
2177 free_irq(mgp->msix_vectors[i].vector,
2178 &mgp->ss[i]);
2179 i--;
2180 }
2181 pci_disable_msix(pdev);
2182 return status;
2183 }
2184 }
2185 } else {
2186 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2187 mgp->dev->name, &mgp->ss[0]);
2188 if (status != 0) {
2189 dev_err(&pdev->dev, "failed to allocate IRQ\n");
2190 if (mgp->msi_enabled)
2191 pci_disable_msi(pdev);
2192 }
df30a740
BG		 2193 }
2194 return status;
2195}
2196
2197static void myri10ge_free_irq(struct myri10ge_priv *mgp)
2198{
2199 struct pci_dev *pdev = mgp->pdev;
0dcffac1 2200 int i;
df30a740 2201
0dcffac1
BG		 2202 if (mgp->msix_enabled) {
2203 for (i = 0; i < mgp->num_slices; i++)
2204 free_irq(mgp->msix_vectors[i].vector, &mgp->ss[i]);
2205 } else {
2206 free_irq(pdev->irq, &mgp->ss[0]);
2207 }
df30a740
BG		 2208 if (mgp->msi_enabled)
2209 pci_disable_msi(pdev);
0dcffac1
BG		 2210 if (mgp->msix_enabled)
2211 pci_disable_msix(pdev);
df30a740
BG		 2212}
2213
1e6e9342
AG		 2214static int
2215myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
2216 void **ip_hdr, void **tcpudp_hdr,
2217 u64 * hdr_flags, void *priv)
2218{
2219 struct ethhdr *eh;
2220 struct vlan_ethhdr *veh;
2221 struct iphdr *iph;
2222 u8 *va = page_address(frag->page) + frag->page_offset;
2223 unsigned long ll_hlen;
66341fff
AV		 2224 /* passed opaque through lro_receive_frags() */
2225 __wsum csum = (__force __wsum) (unsigned long)priv;
1e6e9342
AG		 2226
2227 /* find the mac header, aborting if not IPv4 */
2228
2229 eh = (struct ethhdr *)va;
2230 *mac_hdr = eh;
2231 ll_hlen = ETH_HLEN;
2232 if (eh->h_proto != htons(ETH_P_IP)) {
2233 if (eh->h_proto == htons(ETH_P_8021Q)) {
2234 veh = (struct vlan_ethhdr *)va;
2235 if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
2236 return -1;
2237
2238 ll_hlen += VLAN_HLEN;
2239
2240 /*
2241 * HW checksum starts ETH_HLEN bytes into
2242 * frame, so we must subtract off the VLAN
2243 * header's checksum before csum can be used
2244 */
2245 csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
2246 VLAN_HLEN, 0));
2247 } else {
2248 return -1;
2249 }
2250 }
2251 *hdr_flags = LRO_IPV4;
2252
2253 iph = (struct iphdr *)(va + ll_hlen);
2254 *ip_hdr = iph;
2255 if (iph->protocol != IPPROTO_TCP)
2256 return -1;
bcb09dc2
BG		 2257 if (iph->frag_off & htons(IP_MF | IP_OFFSET))
2258 return -1;
1e6e9342
AG		 2259 *hdr_flags |= LRO_TCP;
2260 *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
2261
2262 /* verify the IP checksum */
2263 if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
2264 return -1;
2265
2266 /* verify the checksum */
2267 if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
2268 ntohs(iph->tot_len) - (iph->ihl << 2),
2269 IPPROTO_TCP, csum)))
2270 return -1;
2271
2272 return 0;
2273}
2274
77929732
BG		 2275static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
2276{
2277 struct myri10ge_cmd cmd;
2278 struct myri10ge_slice_state *ss;
2279 int status;
2280
2281 ss = &mgp->ss[slice];
236bb5e6
BG		 2282 status = 0;
2283 if (slice == 0 || (mgp->dev->real_num_tx_queues > 1)) {
2284 cmd.data0 = slice;
2285 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET,
2286 &cmd, 0);
2287 ss->tx.lanai = (struct mcp_kreq_ether_send __iomem *)
2288 (mgp->sram + cmd.data0);
2289 }
77929732
BG		 2290 cmd.data0 = slice;
2291 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET,
2292 &cmd, 0);
2293 ss->rx_small.lanai = (struct mcp_kreq_ether_recv __iomem *)
2294 (mgp->sram + cmd.data0);
2295
2296 cmd.data0 = slice;
2297 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
2298 ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *)
2299 (mgp->sram + cmd.data0);
2300
236bb5e6
BG		 2301 ss->tx.send_go = (__iomem __be32 *)
2302 (mgp->sram + MXGEFW_ETH_SEND_GO + 64 * slice);
2303 ss->tx.send_stop = (__iomem __be32 *)
2304 (mgp->sram + MXGEFW_ETH_SEND_STOP + 64 * slice);
77929732
BG		 2305 return status;
2306
2307}
2308
2309static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice)
2310{
2311 struct myri10ge_cmd cmd;
2312 struct myri10ge_slice_state *ss;
2313 int status;
2314
2315 ss = &mgp->ss[slice];
2316 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->fw_stats_bus);
2317 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->fw_stats_bus);
236bb5e6 2318 cmd.data2 = sizeof(struct mcp_irq_data) | (slice << 16);
77929732
BG		 2319 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2320 if (status == -ENOSYS) {
2321 dma_addr_t bus = ss->fw_stats_bus;
2322 if (slice != 0)
2323 return -EINVAL;
2324 bus += offsetof(struct mcp_irq_data, send_done_count);
2325 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2326 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2327 status = myri10ge_send_cmd(mgp,
2328 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2329 &cmd, 0);
2330 /* Firmware cannot support multicast without STATS_DMA_V2 */
2331 mgp->fw_multicast_support = 0;
2332 } else {
2333 mgp->fw_multicast_support = 1;
2334 }
2335 return 0;
2336}
77929732 2337
0da34b6d
BG		 2338static int myri10ge_open(struct net_device *dev)
2339{
0dcffac1 2340 struct myri10ge_slice_state *ss;
b53bef84 2341 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d 2342 struct myri10ge_cmd cmd;
0dcffac1
BG		 2343 int i, status, big_pow2, slice;
2344 u8 *itable;
1e6e9342 2345 struct net_lro_mgr *lro_mgr;
0da34b6d 2346
0da34b6d
BG		 2347 if (mgp->running != MYRI10GE_ETH_STOPPED)
2348 return -EBUSY;
2349
2350 mgp->running = MYRI10GE_ETH_STARTING;
2351 status = myri10ge_reset(mgp);
2352 if (status != 0) {
78ca90ea 2353 netdev_err(dev, "failed reset\n");
df30a740 2354 goto abort_with_nothing;
0da34b6d
BG		 2355 }
2356
0dcffac1
BG		 2357 if (mgp->num_slices > 1) {
2358 cmd.data0 = mgp->num_slices;
236bb5e6
BG		 2359 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
2360 if (mgp->dev->real_num_tx_queues > 1)
2361 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
0dcffac1
BG		 2362 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
2363 &cmd, 0);
2364 if (status != 0) {
78ca90ea 2365 netdev_err(dev, "failed to set number of slices\n");
0dcffac1
BG		 2366 goto abort_with_nothing;
2367 }
2368 /* setup the indirection table */
2369 cmd.data0 = mgp->num_slices;
2370 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
2371 &cmd, 0);
2372
2373 status |= myri10ge_send_cmd(mgp,
2374 MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
2375 &cmd, 0);
2376 if (status != 0) {
78ca90ea 2377 netdev_err(dev, "failed to setup rss tables\n");
236bb5e6 2378 goto abort_with_nothing;
0dcffac1
BG		 2379 }
2380
2381 /* just enable an identity mapping */
2382 itable = mgp->sram + cmd.data0;
2383 for (i = 0; i < mgp->num_slices; i++)
2384 __raw_writeb(i, &itable[i]);
2385
2386 cmd.data0 = 1;
2387 cmd.data1 = myri10ge_rss_hash;
2388 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE,
2389 &cmd, 0);
2390 if (status != 0) {
78ca90ea 2391 netdev_err(dev, "failed to enable slices\n");
0dcffac1
BG		 2392 goto abort_with_nothing;
2393 }
2394 }
2395
df30a740
BG		 2396 status = myri10ge_request_irq(mgp);
2397 if (status != 0)
2398 goto abort_with_nothing;
2399
0da34b6d
BG		 2400 /* decide what small buffer size to use. For good TCP rx
2401 * performance, it is important to not receive 1514 byte
2402 * frames into jumbo buffers, as it confuses the socket buffer
2403 * accounting code, leading to drops and erratic performance.
2404 */
2405
2406 if (dev->mtu <= ETH_DATA_LEN)
c7dab99b
BG		 2407 /* enough for a TCP header */
2408 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
2409 ? (128 - MXGEFW_PAD)
2410 : (SMP_CACHE_BYTES - MXGEFW_PAD);
0da34b6d 2411 else
de3c4507
BG		 2412 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
2413 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
0da34b6d
BG		 2414
2415 /* Override the small buffer size? */
2416 if (myri10ge_small_bytes > 0)
2417 mgp->small_bytes = myri10ge_small_bytes;
2418
0da34b6d
BG		 2419 /* Firmware needs the big buff size as a power of 2. Lie and
2420 * tell him the buffer is larger, because we only use 1
2421 * buffer/pkt, and the mtu will prevent overruns.
2422 */
13348bee 2423 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b 2424 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
199126a2 2425 while (!is_power_of_2(big_pow2))
c7dab99b 2426 big_pow2++;
13348bee 2427 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 2428 } else {
2429 big_pow2 = MYRI10GE_ALLOC_SIZE;
2430 mgp->big_bytes = big_pow2;
2431 }
2432
0dcffac1
BG		 2433 /* setup the per-slice data structures */
2434 for (slice = 0; slice < mgp->num_slices; slice++) {
2435 ss = &mgp->ss[slice];
2436
2437 status = myri10ge_get_txrx(mgp, slice);
2438 if (status != 0) {
78ca90ea 2439 netdev_err(dev, "failed to get ring sizes or locations\n");
0dcffac1
BG		 2440 goto abort_with_rings;
2441 }
2442 status = myri10ge_allocate_rings(ss);
2443 if (status != 0)
2444 goto abort_with_rings;
236bb5e6
BG		 2445
2446 /* only firmware which supports multiple TX queues
2447 * supports setting up the tx stats on non-zero
2448 * slices */
2449 if (slice == 0 || mgp->dev->real_num_tx_queues > 1)
0dcffac1
BG		 2450 status = myri10ge_set_stats(mgp, slice);
2451 if (status) {
78ca90ea 2452 netdev_err(dev, "Couldn't set stats DMA\n");
0dcffac1
BG		 2453 goto abort_with_rings;
2454 }
2455
2456 lro_mgr = &ss->rx_done.lro_mgr;
2457 lro_mgr->dev = dev;
2458 lro_mgr->features = LRO_F_NAPI;
2459 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
2460 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2461 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
2462 lro_mgr->lro_arr = ss->rx_done.lro_desc;
2463 lro_mgr->get_frag_header = myri10ge_get_frag_header;
2464 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
636d2f68 2465 lro_mgr->frag_align_pad = 2;
0dcffac1
BG		 2466 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2467 lro_mgr->max_aggr = MAX_SKB_FRAGS;
2468
2469 /* must happen prior to any irq */
2470 napi_enable(&(ss)->napi);
2471 }
0da34b6d
BG		 2472
2473 /* now give firmware buffers sizes, and MTU */
2474 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
2475 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2476 cmd.data0 = mgp->small_bytes;
2477 status |=
2478 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2479 cmd.data0 = big_pow2;
2480 status |=
2481 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2482 if (status) {
78ca90ea 2483 netdev_err(dev, "Couldn't set buffer sizes\n");
0da34b6d
BG		 2484 goto abort_with_rings;
2485 }
2486
0dcffac1
BG		 2487 /*
2488 * Set Linux style TSO mode; this is needed only on newer
2489 * firmware versions. Older versions default to Linux
2490 * style TSO
2491 */
2492 cmd.data0 = 0;
2493 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd, 0);
2494 if (status && status != -ENOSYS) {
78ca90ea 2495 netdev_err(dev, "Couldn't set TSO mode\n");
0da34b6d
BG		 2496 goto abort_with_rings;
2497 }
2498
66341fff 2499 mgp->link_state = ~0U;
0da34b6d
BG		 2500 mgp->rdma_tags_available = 15;
2501
0da34b6d
BG		 2502 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2503 if (status) {
78ca90ea 2504 netdev_err(dev, "Couldn't bring up link\n");
0da34b6d
BG		 2505 goto abort_with_rings;
2506 }
2507
0da34b6d
BG		 2508 mgp->running = MYRI10GE_ETH_RUNNING;
2509 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2510 add_timer(&mgp->watchdog_timer);
236bb5e6
BG		 2511 netif_tx_wake_all_queues(dev);
2512
0da34b6d
BG		 2513 return 0;
2514
2515abort_with_rings:
051d36f3
BG		 2516 while (slice) {
2517 slice--;
2518 napi_disable(&mgp->ss[slice].napi);
2519 }
0dcffac1
BG		 2520 for (i = 0; i < mgp->num_slices; i++)
2521 myri10ge_free_rings(&mgp->ss[i]);
0da34b6d 2522
df30a740
BG		 2523 myri10ge_free_irq(mgp);
2524
0da34b6d
BG		 2525abort_with_nothing:
2526 mgp->running = MYRI10GE_ETH_STOPPED;
2527 return -ENOMEM;
2528}
2529
2530static int myri10ge_close(struct net_device *dev)
2531{
b53bef84 2532 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d
BG		 2533 struct myri10ge_cmd cmd;
2534 int status, old_down_cnt;
0dcffac1 2535 int i;
0da34b6d 2536
0da34b6d
BG		 2537 if (mgp->running != MYRI10GE_ETH_RUNNING)
2538 return 0;
2539
0dcffac1 2540 if (mgp->ss[0].tx.req_bytes == NULL)
0da34b6d
BG		 2541 return 0;
2542
2543 del_timer_sync(&mgp->watchdog_timer);
2544 mgp->running = MYRI10GE_ETH_STOPPING;
0dcffac1
BG		 2545 for (i = 0; i < mgp->num_slices; i++) {
2546 napi_disable(&mgp->ss[i].napi);
2547 }
0da34b6d 2548 netif_carrier_off(dev);
236bb5e6
BG		 2549
2550 netif_tx_stop_all_queues(dev);
d0234215
BG		 2551 if (mgp->rebooted == 0) {
2552 old_down_cnt = mgp->down_cnt;
2553 mb();
2554 status =
2555 myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2556 if (status)
78ca90ea 2557 netdev_err(dev, "Couldn't bring down link\n");
0da34b6d 2558
d0234215
BG		 2559 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt,
2560 HZ);
2561 if (old_down_cnt == mgp->down_cnt)
78ca90ea 2562 netdev_err(dev, "never got down irq\n");
d0234215 2563 }
0da34b6d 2564 netif_tx_disable(dev);
df30a740 2565 myri10ge_free_irq(mgp);
0dcffac1
BG		 2566 for (i = 0; i < mgp->num_slices; i++)
2567 myri10ge_free_rings(&mgp->ss[i]);
0da34b6d
BG		 2568
2569 mgp->running = MYRI10GE_ETH_STOPPED;
2570 return 0;
2571}
2572
2573/* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2574 * backwards one at a time and handle ring wraps */
2575
2576static inline void
2577myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2578 struct mcp_kreq_ether_send *src, int cnt)
2579{
2580 int idx, starting_slot;
2581 starting_slot = tx->req;
2582 while (cnt > 1) {
2583 cnt--;
2584 idx = (starting_slot + cnt) & tx->mask;
2585 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2586 mb();
2587 }
2588}
2589
2590/*
2591 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2592 * at most 32 bytes at a time, so as to avoid involving the software
2593 * pio handler in the nic. We re-write the first segment's flags
2594 * to mark them valid only after writing the entire chain.
2595 */
2596
2597static inline void
2598myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2599 int cnt)
2600{
2601 int idx, i;
2602 struct mcp_kreq_ether_send __iomem *dstp, *dst;
2603 struct mcp_kreq_ether_send *srcp;
2604 u8 last_flags;
2605
2606 idx = tx->req & tx->mask;
2607
2608 last_flags = src->flags;
2609 src->flags = 0;
2610 mb();
2611 dst = dstp = &tx->lanai[idx];
2612 srcp = src;
2613
2614 if ((idx + cnt) < tx->mask) {
2615 for (i = 0; i < (cnt - 1); i += 2) {
2616 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2617 mb(); /* force write every 32 bytes */
2618 srcp += 2;
2619 dstp += 2;
2620 }
2621 } else {
2622 /* submit all but the first request, and ensure
2623 * that it is submitted below */
2624 myri10ge_submit_req_backwards(tx, src, cnt);
2625 i = 0;
2626 }
2627 if (i < cnt) {
2628 /* submit the first request */
2629 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2630 mb(); /* barrier before setting valid flag */
2631 }
2632
2633 /* re-write the last 32-bits with the valid flags */
2634 src->flags = last_flags;
40f6cff5 2635 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
0da34b6d
BG		 2636 tx->req += cnt;
2637 mb();
2638}
2639
0da34b6d
BG		 2640/*
2641 * Transmit a packet. We need to split the packet so that a single
b53bef84 2642 * segment does not cross myri10ge->tx_boundary, so this makes segment
0da34b6d
BG		 2643 * counting tricky. So rather than try to count segments up front, we
2644 * just give up if there are too few segments to hold a reasonably
2645 * fragmented packet currently available. If we run
2646 * out of segments while preparing a packet for DMA, we just linearize
2647 * it and try again.
2648 */
2649
61357325
SH		 2650static netdev_tx_t myri10ge_xmit(struct sk_buff *skb,
2651 struct net_device *dev)
0da34b6d
BG		 2652{
2653 struct myri10ge_priv *mgp = netdev_priv(dev);
b53bef84 2654 struct myri10ge_slice_state *ss;
0da34b6d 2655 struct mcp_kreq_ether_send *req;
b53bef84 2656 struct myri10ge_tx_buf *tx;
0da34b6d 2657 struct skb_frag_struct *frag;
236bb5e6 2658 struct netdev_queue *netdev_queue;
0da34b6d 2659 dma_addr_t bus;
40f6cff5
AV		 2660 u32 low;
2661 __be32 high_swapped;
0da34b6d
BG		 2662 unsigned int len;
2663 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
236bb5e6 2664 u16 pseudo_hdr_offset, cksum_offset, queue;
0da34b6d
BG		 2665 int cum_len, seglen, boundary, rdma_count;
2666 u8 flags, odd_flag;
2667
236bb5e6 2668 queue = skb_get_queue_mapping(skb);
236bb5e6
BG		 2669 ss = &mgp->ss[queue];
2670 netdev_queue = netdev_get_tx_queue(mgp->dev, queue);
b53bef84 2671 tx = &ss->tx;
236bb5e6 2672
0da34b6d
BG		 2673again:
2674 req = tx->req_list;
2675 avail = tx->mask - 1 - (tx->req - tx->done);
2676
2677 mss = 0;
2678 max_segments = MXGEFW_MAX_SEND_DESC;
2679
917690cd 2680 if (skb_is_gso(skb)) {
7967168c 2681 mss = skb_shinfo(skb)->gso_size;
917690cd 2682 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
0da34b6d 2683 }
0da34b6d
BG		 2684
2685 if ((unlikely(avail < max_segments))) {
2686 /* we are out of transmit resources */
b53bef84 2687 tx->stop_queue++;
236bb5e6 2688 netif_tx_stop_queue(netdev_queue);
5b548140 2689 return NETDEV_TX_BUSY;
0da34b6d
BG		 2690 }
2691
2692 /* Setup checksum offloading, if needed */
2693 cksum_offset = 0;
2694 pseudo_hdr_offset = 0;
2695 odd_flag = 0;
2696 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
84fa7933 2697 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
0d0b1672 2698 cksum_offset = skb_checksum_start_offset(skb);
ff1dcadb 2699 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
0da34b6d
BG		 2700 /* If the headers are excessively large, then we must
2701 * fall back to a software checksum */
4f93fde0
BG		 2702 if (unlikely(!mss && (cksum_offset > 255 ||
2703 pseudo_hdr_offset > 127))) {
84fa7933 2704 if (skb_checksum_help(skb))
0da34b6d
BG		 2705 goto drop;
2706 cksum_offset = 0;
2707 pseudo_hdr_offset = 0;
2708 } else {
0da34b6d
BG		 2709 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2710 flags |= MXGEFW_FLAGS_CKSUM;
2711 }
2712 }
2713
2714 cum_len = 0;
2715
0da34b6d
BG		 2716 if (mss) { /* TSO */
2717 /* this removes any CKSUM flag from before */
2718 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2719
2720 /* negative cum_len signifies to the
2721 * send loop that we are still in the
2722 * header portion of the TSO packet.
4f93fde0 2723 * TSO header can be at most 1KB long */
ab6a5bb6 2724 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
0da34b6d 2725
4f93fde0
BG		 2726 /* for IPv6 TSO, the checksum offset stores the
2727 * TCP header length, to save the firmware from
2728 * the need to parse the headers */
2729 if (skb_is_gso_v6(skb)) {
2730 cksum_offset = tcp_hdrlen(skb);
2731 /* Can only handle headers <= max_tso6 long */
2732 if (unlikely(-cum_len > mgp->max_tso6))
2733 return myri10ge_sw_tso(skb, dev);
2734 }
0da34b6d
BG		 2735 /* for TSO, pseudo_hdr_offset holds mss.
2736 * The firmware figures out where to put
2737 * the checksum by parsing the header. */
40f6cff5 2738 pseudo_hdr_offset = mss;
0da34b6d 2739 } else
0da34b6d
BG		 2740 /* Mark small packets, and pad out tiny packets */
2741 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2742 flags |= MXGEFW_FLAGS_SMALL;
2743
2744 /* pad frames to at least ETH_ZLEN bytes */
2745 if (unlikely(skb->len < ETH_ZLEN)) {
5b057c6b 2746 if (skb_padto(skb, ETH_ZLEN)) {
0da34b6d
BG		 2747 /* The packet is gone, so we must
2748 * return 0 */
b53bef84 2749 ss->stats.tx_dropped += 1;
6ed10654 2750 return NETDEV_TX_OK;
0da34b6d
BG		 2751 }
2752 /* adjust the len to account for the zero pad
2753 * so that the nic can know how long it is */
2754 skb->len = ETH_ZLEN;
2755 }
2756 }
2757
2758 /* map the skb for DMA */
e743d313 2759 len = skb_headlen(skb);
0da34b6d
BG		 2760 idx = tx->req & tx->mask;
2761 tx->info[idx].skb = skb;
2762 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
c755b4b6
FT		 2763 dma_unmap_addr_set(&tx->info[idx], bus, bus);
2764 dma_unmap_len_set(&tx->info[idx], len, len);
0da34b6d
BG		 2765
2766 frag_cnt = skb_shinfo(skb)->nr_frags;
2767 frag_idx = 0;
2768 count = 0;
2769 rdma_count = 0;
2770
2771 /* "rdma_count" is the number of RDMAs belonging to the
2772 * current packet BEFORE the current send request. For
2773 * non-TSO packets, this is equal to "count".
2774 * For TSO packets, rdma_count needs to be reset
2775 * to 0 after a segment cut.
2776 *
2777 * The rdma_count field of the send request is
2778 * the number of RDMAs of the packet starting at
2779 * that request. For TSO send requests with one ore more cuts
2780 * in the middle, this is the number of RDMAs starting
2781 * after the last cut in the request. All previous
2782 * segments before the last cut implicitly have 1 RDMA.
2783 *
2784 * Since the number of RDMAs is not known beforehand,
2785 * it must be filled-in retroactively - after each
2786 * segmentation cut or at the end of the entire packet.
2787 */
2788
2789 while (1) {
2790 /* Break the SKB or Fragment up into pieces which
b53bef84 2791 * do not cross mgp->tx_boundary */
0da34b6d
BG		 2792 low = MYRI10GE_LOWPART_TO_U32(bus);
2793 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2794 while (len) {
2795 u8 flags_next;
2796 int cum_len_next;
2797
2798 if (unlikely(count == max_segments))
2799 goto abort_linearize;
2800
b53bef84
BG		 2801 boundary =
2802 (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
0da34b6d
BG		 2803 seglen = boundary - low;
2804 if (seglen > len)
2805 seglen = len;
2806 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2807 cum_len_next = cum_len + seglen;
0da34b6d
BG		 2808 if (mss) { /* TSO */
2809 (req - rdma_count)->rdma_count = rdma_count + 1;
2810
2811 if (likely(cum_len >= 0)) { /* payload */
2812 int next_is_first, chop;
2813
2814 chop = (cum_len_next > mss);
2815 cum_len_next = cum_len_next % mss;
2816 next_is_first = (cum_len_next == 0);
2817 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2818 flags_next |= next_is_first *
2819 MXGEFW_FLAGS_FIRST;
2820 rdma_count |= -(chop | next_is_first);
2821 rdma_count += chop & !next_is_first;
2822 } else if (likely(cum_len_next >= 0)) { /* header ends */
2823 int small;
2824
2825 rdma_count = -1;
2826 cum_len_next = 0;
2827 seglen = -cum_len;
2828 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2829 flags_next = MXGEFW_FLAGS_TSO_PLD |
2830 MXGEFW_FLAGS_FIRST |
2831 (small * MXGEFW_FLAGS_SMALL);
2832 }
2833 }
0da34b6d
BG		 2834 req->addr_high = high_swapped;
2835 req->addr_low = htonl(low);
40f6cff5 2836 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
0da34b6d
BG		 2837 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2838 req->rdma_count = 1;
2839 req->length = htons(seglen);
2840 req->cksum_offset = cksum_offset;
2841 req->flags = flags | ((cum_len & 1) * odd_flag);
2842
2843 low += seglen;
2844 len -= seglen;
2845 cum_len = cum_len_next;
2846 flags = flags_next;
2847 req++;
2848 count++;
2849 rdma_count++;
4f93fde0
BG		 2850 if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2851 if (unlikely(cksum_offset > seglen))
2852 cksum_offset -= seglen;
2853 else
2854 cksum_offset = 0;
2855 }
0da34b6d
BG		 2856 }
2857 if (frag_idx == frag_cnt)
2858 break;
2859
2860 /* map next fragment for DMA */
2861 idx = (count + tx->req) & tx->mask;
2862 frag = &skb_shinfo(skb)->frags[frag_idx];
2863 frag_idx++;
2864 len = frag->size;
2865 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2866 len, PCI_DMA_TODEVICE);
c755b4b6
FT		 2867 dma_unmap_addr_set(&tx->info[idx], bus, bus);
2868 dma_unmap_len_set(&tx->info[idx], len, len);
0da34b6d
BG		 2869 }
2870
2871 (req - rdma_count)->rdma_count = rdma_count;
0da34b6d
BG		 2872 if (mss)
2873 do {
2874 req--;
2875 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2876 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2877 MXGEFW_FLAGS_FIRST)));
0da34b6d
BG		 2878 idx = ((count - 1) + tx->req) & tx->mask;
2879 tx->info[idx].last = 1;
e454e7e2 2880 myri10ge_submit_req(tx, tx->req_list, count);
236bb5e6
BG		 2881 /* if using multiple tx queues, make sure NIC polls the
2882 * current slice */
2883 if ((mgp->dev->real_num_tx_queues > 1) && tx->queue_active == 0) {
2884 tx->queue_active = 1;
2885 put_be32(htonl(1), tx->send_go);
8c2f5fa5 2886 mb();
6824a105 2887 mmiowb();
236bb5e6 2888 }
0da34b6d
BG		 2889 tx->pkt_start++;
2890 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
b53bef84 2891 tx->stop_queue++;
236bb5e6 2892 netif_tx_stop_queue(netdev_queue);
0da34b6d 2893 }
6ed10654 2894 return NETDEV_TX_OK;
0da34b6d
BG		 2895
2896abort_linearize:
2897 /* Free any DMA resources we've alloced and clear out the skb
2898 * slot so as to not trip up assertions, and to avoid a
2899 * double-free if linearizing fails */
2900
2901 last_idx = (idx + 1) & tx->mask;
2902 idx = tx->req & tx->mask;
2903 tx->info[idx].skb = NULL;
2904 do {
c755b4b6 2905 len = dma_unmap_len(&tx->info[idx], len);
0da34b6d
BG		 2906 if (len) {
2907 if (tx->info[idx].skb != NULL)
2908 pci_unmap_single(mgp->pdev,
c755b4b6 2909 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 2910 bus), len,
2911 PCI_DMA_TODEVICE);
2912 else
2913 pci_unmap_page(mgp->pdev,
c755b4b6 2914 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 2915 bus), len,
2916 PCI_DMA_TODEVICE);
c755b4b6 2917 dma_unmap_len_set(&tx->info[idx], len, 0);
0da34b6d
BG		 2918 tx->info[idx].skb = NULL;
2919 }
2920 idx = (idx + 1) & tx->mask;
2921 } while (idx != last_idx);
89114afd 2922 if (skb_is_gso(skb)) {
78ca90ea 2923 netdev_err(mgp->dev, "TSO but wanted to linearize?!?!?\n");
0da34b6d
BG		 2924 goto drop;
2925 }
2926
bec0e859 2927 if (skb_linearize(skb))
0da34b6d
BG		 2928 goto drop;
2929
b53bef84 2930 tx->linearized++;
0da34b6d
BG		 2931 goto again;
2932
2933drop:
2934 dev_kfree_skb_any(skb);
b53bef84 2935 ss->stats.tx_dropped += 1;
6ed10654 2936 return NETDEV_TX_OK;
0da34b6d
BG		 2937
2938}
2939
61357325
SH		 2940static netdev_tx_t myri10ge_sw_tso(struct sk_buff *skb,
2941 struct net_device *dev)
4f93fde0
BG		 2942{
2943 struct sk_buff *segs, *curr;
b53bef84 2944 struct myri10ge_priv *mgp = netdev_priv(dev);
d6279c88 2945 struct myri10ge_slice_state *ss;
61357325 2946 netdev_tx_t status;
4f93fde0
BG		 2947
2948 segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
801678c5 2949 if (IS_ERR(segs))
4f93fde0
BG		 2950 goto drop;
2951
2952 while (segs) {
2953 curr = segs;
2954 segs = segs->next;
2955 curr->next = NULL;
2956 status = myri10ge_xmit(curr, dev);
2957 if (status != 0) {
2958 dev_kfree_skb_any(curr);
2959 if (segs != NULL) {
2960 curr = segs;
2961 segs = segs->next;
2962 curr->next = NULL;
2963 dev_kfree_skb_any(segs);
2964 }
2965 goto drop;
2966 }
2967 }
2968 dev_kfree_skb_any(skb);
ec634fe3 2969 return NETDEV_TX_OK;
4f93fde0
BG		 2970
2971drop:
d6279c88 2972 ss = &mgp->ss[skb_get_queue_mapping(skb)];
4f93fde0 2973 dev_kfree_skb_any(skb);
d6279c88 2974 ss->stats.tx_dropped += 1;
ec634fe3 2975 return NETDEV_TX_OK;
4f93fde0
BG		 2976}
2977
0da34b6d
BG		 2978static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2979{
2980 struct myri10ge_priv *mgp = netdev_priv(dev);
0dcffac1 2981 struct myri10ge_slice_netstats *slice_stats;
6dc34941 2982 struct net_device_stats *stats = &dev->stats;
0dcffac1
BG		 2983 int i;
2984
59081825 2985 spin_lock(&mgp->stats_lock);
0dcffac1
BG		 2986 memset(stats, 0, sizeof(*stats));
2987 for (i = 0; i < mgp->num_slices; i++) {
2988 slice_stats = &mgp->ss[i].stats;
2989 stats->rx_packets += slice_stats->rx_packets;
2990 stats->tx_packets += slice_stats->tx_packets;
2991 stats->rx_bytes += slice_stats->rx_bytes;
2992 stats->tx_bytes += slice_stats->tx_bytes;
2993 stats->rx_dropped += slice_stats->rx_dropped;
2994 stats->tx_dropped += slice_stats->tx_dropped;
2995 }
59081825 2996 spin_unlock(&mgp->stats_lock);
0dcffac1 2997 return stats;
0da34b6d
BG		 2998}
2999
3000static void myri10ge_set_multicast_list(struct net_device *dev)
3001{
b53bef84 3002 struct myri10ge_priv *mgp = netdev_priv(dev);
85a7ea1b 3003 struct myri10ge_cmd cmd;
22bedad3 3004 struct netdev_hw_addr *ha;
6250223e 3005 __be32 data[2] = { 0, 0 };
85a7ea1b
BG		 3006 int err;
3007
0da34b6d
BG		 3008 /* can be called from atomic contexts,
3009 * pass 1 to force atomicity in myri10ge_send_cmd() */
85a7ea1b
BG		 3010 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
3011
3012 /* This firmware is known to not support multicast */
2f76216f 3013 if (!mgp->fw_multicast_support)
85a7ea1b
BG		 3014 return;
3015
3016 /* Disable multicast filtering */
3017
3018 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
3019 if (err != 0) {
78ca90ea
JP		 3020 netdev_err(dev, "Failed MXGEFW_ENABLE_ALLMULTI, error status: %d\n",
3021 err);
85a7ea1b
BG		 3022 goto abort;
3023 }
3024
2f76216f 3025 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
85a7ea1b
BG		 3026 /* request to disable multicast filtering, so quit here */
3027 return;
3028 }
3029
3030 /* Flush the filters */
3031
3032 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
3033 &cmd, 1);
3034 if (err != 0) {
78ca90ea
JP		 3035 netdev_err(dev, "Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS, error status: %d\n",
3036 err);
85a7ea1b
BG		 3037 goto abort;
3038 }
3039
3040 /* Walk the multicast list, and add each address */
22bedad3
JP		 3041 netdev_for_each_mc_addr(ha, dev) {
3042 memcpy(data, &ha->addr, 6);
40f6cff5
AV		 3043 cmd.data0 = ntohl(data[0]);
3044 cmd.data1 = ntohl(data[1]);
85a7ea1b
BG		 3045 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
3046 &cmd, 1);
3047
3048 if (err != 0) {
78ca90ea 3049 netdev_err(dev, "Failed MXGEFW_JOIN_MULTICAST_GROUP, error status:%d %pM\n",
22bedad3 3050 err, ha->addr);
85a7ea1b
BG		 3051 goto abort;
3052 }
3053 }
3054 /* Enable multicast filtering */
3055 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
3056 if (err != 0) {
78ca90ea
JP		 3057 netdev_err(dev, "Failed MXGEFW_DISABLE_ALLMULTI, error status: %d\n",
3058 err);
85a7ea1b
BG		 3059 goto abort;
3060 }
3061
3062 return;
3063
3064abort:
3065 return;
0da34b6d
BG		 3066}
3067
3068static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
3069{
3070 struct sockaddr *sa = addr;
3071 struct myri10ge_priv *mgp = netdev_priv(dev);
3072 int status;
3073
3074 if (!is_valid_ether_addr(sa->sa_data))
3075 return -EADDRNOTAVAIL;
3076
3077 status = myri10ge_update_mac_address(mgp, sa->sa_data);
3078 if (status != 0) {
78ca90ea
JP		 3079 netdev_err(dev, "changing mac address failed with %d\n",
3080 status);
0da34b6d
BG		 3081 return status;
3082 }
3083
3084 /* change the dev structure */
3085 memcpy(dev->dev_addr, sa->sa_data, 6);
3086 return 0;
3087}
3088
47c2cdf5
MM		 3089static u32 myri10ge_fix_features(struct net_device *dev, u32 features)
3090{
3091 if (!(features & NETIF_F_RXCSUM))
3092 features &= ~NETIF_F_LRO;
3093
3094 return features;
3095}
3096
0da34b6d
BG		 3097static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
3098{
3099 struct myri10ge_priv *mgp = netdev_priv(dev);
3100 int error = 0;
3101
3102 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
78ca90ea 3103 netdev_err(dev, "new mtu (%d) is not valid\n", new_mtu);
0da34b6d
BG		 3104 return -EINVAL;
3105 }
78ca90ea 3106 netdev_info(dev, "changing mtu from %d to %d\n", dev->mtu, new_mtu);
0da34b6d
BG		 3107 if (mgp->running) {
3108 /* if we change the mtu on an active device, we must
3109 * reset the device so the firmware sees the change */
3110 myri10ge_close(dev);
3111 dev->mtu = new_mtu;
3112 myri10ge_open(dev);
3113 } else
3114 dev->mtu = new_mtu;
3115
3116 return error;
3117}
3118
3119/*
3120 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
3121 * Only do it if the bridge is a root port since we don't want to disturb
3122 * any other device, except if forced with myri10ge_ecrc_enable > 1.
3123 */
3124
0da34b6d
BG		 3125static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
3126{
3127 struct pci_dev *bridge = mgp->pdev->bus->self;
3128 struct device *dev = &mgp->pdev->dev;
3129 unsigned cap;
3130 unsigned err_cap;
3131 u16 val;
3132 u8 ext_type;
3133 int ret;
3134
3135 if (!myri10ge_ecrc_enable || !bridge)
3136 return;
3137
3138 /* check that the bridge is a root port */
3139 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
3140 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
3141 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3142 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
3143 if (myri10ge_ecrc_enable > 1) {
eca3fd83 3144 struct pci_dev *prev_bridge, *old_bridge = bridge;
0da34b6d
BG		 3145
3146 /* Walk the hierarchy up to the root port
3147 * where ECRC has to be enabled */
3148 do {
eca3fd83 3149 prev_bridge = bridge;
0da34b6d 3150 bridge = bridge->bus->self;
eca3fd83 3151 if (!bridge || prev_bridge == bridge) {
0da34b6d
BG		 3152 dev_err(dev,
3153 "Failed to find root port"
3154 " to force ECRC\n");
3155 return;
3156 }
3157 cap =
3158 pci_find_capability(bridge, PCI_CAP_ID_EXP);
3159 pci_read_config_word(bridge,
3160 cap + PCI_CAP_FLAGS, &val);
3161 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3162 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
3163
3164 dev_info(dev,
3165 "Forcing ECRC on non-root port %s"
3166 " (enabling on root port %s)\n",
3167 pci_name(old_bridge), pci_name(bridge));
3168 } else {
3169 dev_err(dev,
3170 "Not enabling ECRC on non-root port %s\n",
3171 pci_name(bridge));
3172 return;
3173 }
3174 }
3175
3176 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
0da34b6d
BG		 3177 if (!cap)
3178 return;
3179
3180 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
3181 if (ret) {
3182 dev_err(dev, "failed reading ext-conf-space of %s\n",
3183 pci_name(bridge));
3184 dev_err(dev, "\t pci=nommconf in use? "
3185 "or buggy/incomplete/absent ACPI MCFG attr?\n");
3186 return;
3187 }
3188 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
3189 return;
3190
3191 err_cap |= PCI_ERR_CAP_ECRC_GENE;
3192 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
3193 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
0da34b6d
BG		 3194}
3195
3196/*
3197 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
3198 * when the PCI-E Completion packets are aligned on an 8-byte
3199 * boundary. Some PCI-E chip sets always align Completion packets; on
3200 * the ones that do not, the alignment can be enforced by enabling
3201 * ECRC generation (if supported).
3202 *
3203 * When PCI-E Completion packets are not aligned, it is actually more
3204 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
3205 *
3206 * If the driver can neither enable ECRC nor verify that it has
3207 * already been enabled, then it must use a firmware image which works
0dcffac1 3208 * around unaligned completion packets (myri10ge_rss_ethp_z8e.dat), and it
0da34b6d 3209 * should also ensure that it never gives the device a Read-DMA which is
b53bef84 3210 * larger than 2KB by setting the tx_boundary to 2KB. If ECRC is
0dcffac1 3211 * enabled, then the driver should use the aligned (myri10ge_rss_eth_z8e.dat)
b53bef84 3212 * firmware image, and set tx_boundary to 4KB.
0da34b6d
BG		 3213 */
3214
5443e9ea 3215static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
0da34b6d 3216{
5443e9ea
BG		 3217 struct pci_dev *pdev = mgp->pdev;
3218 struct device *dev = &pdev->dev;
302d242c 3219 int status;
0da34b6d 3220
b53bef84 3221 mgp->tx_boundary = 4096;
5443e9ea
BG		 3222 /*
3223 * Verify the max read request size was set to 4KB
3224 * before trying the test with 4KB.
3225 */
302d242c
BG		 3226 status = pcie_get_readrq(pdev);
3227 if (status < 0) {
5443e9ea
BG		 3228 dev_err(dev, "Couldn't read max read req size: %d\n", status);
3229 goto abort;
3230 }
302d242c
BG		 3231 if (status != 4096) {
3232 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
b53bef84 3233 mgp->tx_boundary = 2048;
5443e9ea
BG		 3234 }
3235 /*
3236 * load the optimized firmware (which assumes aligned PCIe
3237 * completions) in order to see if it works on this host.
3238 */
7d351035 3239 set_fw_name(mgp, myri10ge_fw_aligned, false);
0dcffac1 3240 status = myri10ge_load_firmware(mgp, 1);
5443e9ea
BG		 3241 if (status != 0) {
3242 goto abort;
3243 }
3244
3245 /*
3246 * Enable ECRC if possible
3247 */
3248 myri10ge_enable_ecrc(mgp);
3249
3250 /*
3251 * Run a DMA test which watches for unaligned completions and
3252 * aborts on the first one seen.
3253 */
3254
3255 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
3256 if (status == 0)
3257 return; /* keep the aligned firmware */
3258
3259 if (status != -E2BIG)
3260 dev_warn(dev, "DMA test failed: %d\n", status);
3261 if (status == -ENOSYS)
3262 dev_warn(dev, "Falling back to ethp! "
3263 "Please install up to date fw\n");
3264abort:
3265 /* fall back to using the unaligned firmware */
b53bef84 3266 mgp->tx_boundary = 2048;
7d351035 3267 set_fw_name(mgp, myri10ge_fw_unaligned, false);
0da34b6d 3268
5443e9ea
BG		 3269}
3270
3271static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
3272{
2d90b0aa
BG		 3273 int overridden = 0;
3274
0da34b6d 3275 if (myri10ge_force_firmware == 0) {
ce7f9368
BG		 3276 int link_width, exp_cap;
3277 u16 lnk;
3278
3279 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
3280 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
3281 link_width = (lnk >> 4) & 0x3f;
3282
ce7f9368
BG		 3283 /* Check to see if Link is less than 8 or if the
3284 * upstream bridge is known to provide aligned
3285 * completions */
3286 if (link_width < 8) {
3287 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
3288 link_width);
b53bef84 3289 mgp->tx_boundary = 4096;
7d351035 3290 set_fw_name(mgp, myri10ge_fw_aligned, false);
5443e9ea
BG		 3291 } else {
3292 myri10ge_firmware_probe(mgp);
0da34b6d
BG		 3293 }
3294 } else {
3295 if (myri10ge_force_firmware == 1) {
3296 dev_info(&mgp->pdev->dev,
3297 "Assuming aligned completions (forced)\n");
b53bef84 3298 mgp->tx_boundary = 4096;
7d351035 3299 set_fw_name(mgp, myri10ge_fw_aligned, false);
0da34b6d
BG		 3300 } else {
3301 dev_info(&mgp->pdev->dev,
3302 "Assuming unaligned completions (forced)\n");
b53bef84 3303 mgp->tx_boundary = 2048;
7d351035 3304 set_fw_name(mgp, myri10ge_fw_unaligned, false);
0da34b6d
BG		 3305 }
3306 }
7d351035
RR		 3307
3308 kparam_block_sysfs_write(myri10ge_fw_name);
0da34b6d 3309 if (myri10ge_fw_name != NULL) {
7d351035
RR		 3310 char *fw_name = kstrdup(myri10ge_fw_name, GFP_KERNEL);
3311 if (fw_name) {
3312 overridden = 1;
3313 set_fw_name(mgp, fw_name, true);
3314 }
0da34b6d 3315 }
7d351035
RR		 3316 kparam_unblock_sysfs_write(myri10ge_fw_name);
3317
2d90b0aa
BG		 3318 if (mgp->board_number < MYRI10GE_MAX_BOARDS &&
3319 myri10ge_fw_names[mgp->board_number] != NULL &&
3320 strlen(myri10ge_fw_names[mgp->board_number])) {
7d351035 3321 set_fw_name(mgp, myri10ge_fw_names[mgp->board_number], false);
2d90b0aa
BG		 3322 overridden = 1;
3323 }
3324 if (overridden)
3325 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
3326 mgp->fw_name);
0da34b6d
BG		 3327}
3328
0da34b6d 3329#ifdef CONFIG_PM
0da34b6d
BG		 3330static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
3331{
3332 struct myri10ge_priv *mgp;
3333 struct net_device *netdev;
3334
3335 mgp = pci_get_drvdata(pdev);
3336 if (mgp == NULL)
3337 return -EINVAL;
3338 netdev = mgp->dev;
3339
3340 netif_device_detach(netdev);
3341 if (netif_running(netdev)) {
78ca90ea 3342 netdev_info(netdev, "closing\n");
0da34b6d
BG		 3343 rtnl_lock();
3344 myri10ge_close(netdev);
3345 rtnl_unlock();
3346 }
3347 myri10ge_dummy_rdma(mgp, 0);
83f6e152 3348 pci_save_state(pdev);
0da34b6d 3349 pci_disable_device(pdev);
1a63e846
BG		 3350
3351 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
0da34b6d
BG		 3352}
3353
3354static int myri10ge_resume(struct pci_dev *pdev)
3355{
3356 struct myri10ge_priv *mgp;
3357 struct net_device *netdev;
3358 int status;
3359 u16 vendor;
3360
3361 mgp = pci_get_drvdata(pdev);
3362 if (mgp == NULL)
3363 return -EINVAL;
3364 netdev = mgp->dev;
3365 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
3366 msleep(5); /* give card time to respond */
3367 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3368 if (vendor == 0xffff) {
78ca90ea 3369 netdev_err(mgp->dev, "device disappeared!\n");
0da34b6d
BG		 3370 return -EIO;
3371 }
83f6e152 3372
1d3c16a8 3373 pci_restore_state(pdev);
4c2248cc
BG		 3374
3375 status = pci_enable_device(pdev);
1a63e846 3376 if (status) {
4c2248cc 3377 dev_err(&pdev->dev, "failed to enable device\n");
1a63e846 3378 return status;
4c2248cc
BG		 3379 }
3380
0da34b6d
BG		 3381 pci_set_master(pdev);
3382
0da34b6d 3383 myri10ge_reset(mgp);
013b68bf 3384 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 3385
3386 /* Save configuration space to be restored if the
3387 * nic resets due to a parity error */
83f6e152 3388 pci_save_state(pdev);
0da34b6d
BG		 3389
3390 if (netif_running(netdev)) {
3391 rtnl_lock();
df30a740 3392 status = myri10ge_open(netdev);
0da34b6d 3393 rtnl_unlock();
df30a740
BG		 3394 if (status != 0)
3395 goto abort_with_enabled;
3396
0da34b6d
BG		 3397 }
3398 netif_device_attach(netdev);
3399
3400 return 0;
3401
4c2248cc
BG		 3402abort_with_enabled:
3403 pci_disable_device(pdev);
0da34b6d
BG		 3404 return -EIO;
3405
3406}
0da34b6d
BG		 3407#endif /* CONFIG_PM */
3408
3409static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
3410{
3411 struct pci_dev *pdev = mgp->pdev;
3412 int vs = mgp->vendor_specific_offset;
3413 u32 reboot;
3414
3415 /*enter read32 mode */
3416 pci_write_config_byte(pdev, vs + 0x10, 0x3);
3417
3418 /*read REBOOT_STATUS (0xfffffff0) */
3419 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
3420 pci_read_config_dword(pdev, vs + 0x14, &reboot);
3421 return reboot;
3422}
3423
3424/*
3425 * This watchdog is used to check whether the board has suffered
3426 * from a parity error and needs to be recovered.
3427 */
c4028958 3428static void myri10ge_watchdog(struct work_struct *work)
0da34b6d 3429{
c4028958 3430 struct myri10ge_priv *mgp =
6250223e 3431 container_of(work, struct myri10ge_priv, watchdog_work);
b53bef84 3432 struct myri10ge_tx_buf *tx;
0da34b6d 3433 u32 reboot;
d0234215 3434 int status, rebooted;
0dcffac1 3435 int i;
0da34b6d
BG		 3436 u16 cmd, vendor;
3437
3438 mgp->watchdog_resets++;
3439 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
d0234215 3440 rebooted = 0;
0da34b6d
BG		 3441 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3442 /* Bus master DMA disabled? Check to see
3443 * if the card rebooted due to a parity error
3444 * For now, just report it */
3445 reboot = myri10ge_read_reboot(mgp);
78ca90ea
JP		 3446 netdev_err(mgp->dev, "NIC rebooted (0x%x),%s resetting\n",
3447 reboot,
3448 myri10ge_reset_recover ? "" : " not");
f181137f
BG		 3449 if (myri10ge_reset_recover == 0)
3450 return;
d0234215
BG		 3451 rtnl_lock();
3452 mgp->rebooted = 1;
3453 rebooted = 1;
3454 myri10ge_close(mgp->dev);
f181137f 3455 myri10ge_reset_recover--;
d0234215 3456 mgp->rebooted = 0;
0da34b6d
BG		 3457 /*
3458 * A rebooted nic will come back with config space as
3459 * it was after power was applied to PCIe bus.
3460 * Attempt to restore config space which was saved
3461 * when the driver was loaded, or the last time the
3462 * nic was resumed from power saving mode.
3463 */
83f6e152 3464 pci_restore_state(mgp->pdev);
7adda30c
BG		 3465
3466 /* save state again for accounting reasons */
83f6e152 3467 pci_save_state(mgp->pdev);
7adda30c 3468
0da34b6d
BG		 3469 } else {
3470 /* if we get back -1's from our slot, perhaps somebody
3471 * powered off our card. Don't try to reset it in
3472 * this case */
3473 if (cmd == 0xffff) {
3474 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3475 if (vendor == 0xffff) {
78ca90ea 3476 netdev_err(mgp->dev, "device disappeared!\n");
0da34b6d
BG		 3477 return;
3478 }
3479 }
3480 /* Perhaps it is a software error. Try to reset */
3481
78ca90ea 3482 netdev_err(mgp->dev, "device timeout, resetting\n");
0dcffac1
BG		 3483 for (i = 0; i < mgp->num_slices; i++) {
3484 tx = &mgp->ss[i].tx;
78ca90ea
JP		 3485 netdev_err(mgp->dev, "(%d): %d %d %d %d %d %d\n",
3486 i, tx->queue_active, tx->req,
3487 tx->done, tx->pkt_start, tx->pkt_done,
3488 (int)ntohl(mgp->ss[i].fw_stats->
3489 send_done_count));
0dcffac1 3490 msleep(2000);
78ca90ea
JP		 3491 netdev_info(mgp->dev, "(%d): %d %d %d %d %d %d\n",
3492 i, tx->queue_active, tx->req,
3493 tx->done, tx->pkt_start, tx->pkt_done,
3494 (int)ntohl(mgp->ss[i].fw_stats->
3495 send_done_count));
0dcffac1 3496 }
0da34b6d 3497 }
236bb5e6 3498
d0234215
BG		 3499 if (!rebooted) {
3500 rtnl_lock();
3501 myri10ge_close(mgp->dev);
3502 }
0dcffac1 3503 status = myri10ge_load_firmware(mgp, 1);
0da34b6d 3504 if (status != 0)
78ca90ea 3505 netdev_err(mgp->dev, "failed to load firmware\n");
0da34b6d
BG		 3506 else
3507 myri10ge_open(mgp->dev);
3508 rtnl_unlock();
3509}
3510
3511/*
3512 * We use our own timer routine rather than relying upon
3513 * netdev->tx_timeout because we have a very large hardware transmit
3514 * queue. Due to the large queue, the netdev->tx_timeout function
3515 * cannot detect a NIC with a parity error in a timely fashion if the
3516 * NIC is lightly loaded.
3517 */
3518static void myri10ge_watchdog_timer(unsigned long arg)
3519{
3520 struct myri10ge_priv *mgp;
b53bef84 3521 struct myri10ge_slice_state *ss;
d0234215 3522 int i, reset_needed, busy_slice_cnt;
626fda94 3523 u32 rx_pause_cnt;
d0234215 3524 u16 cmd;
0da34b6d
BG		 3525
3526 mgp = (struct myri10ge_priv *)arg;
c7dab99b 3527
0dcffac1 3528 rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
d0234215 3529 busy_slice_cnt = 0;
0dcffac1
BG		 3530 for (i = 0, reset_needed = 0;
3531 i < mgp->num_slices && reset_needed == 0; ++i) {
b53bef84 3532
0dcffac1
BG		 3533 ss = &mgp->ss[i];
3534 if (ss->rx_small.watchdog_needed) {
3535 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3536 mgp->small_bytes + MXGEFW_PAD,
3537 1);
3538 if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
3539 myri10ge_fill_thresh)
3540 ss->rx_small.watchdog_needed = 0;
3541 }
3542 if (ss->rx_big.watchdog_needed) {
3543 myri10ge_alloc_rx_pages(mgp, &ss->rx_big,
3544 mgp->big_bytes, 1);
3545 if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
3546 myri10ge_fill_thresh)
3547 ss->rx_big.watchdog_needed = 0;
3548 }
3549
3550 if (ss->tx.req != ss->tx.done &&
3551 ss->tx.done == ss->watchdog_tx_done &&
3552 ss->watchdog_tx_req != ss->watchdog_tx_done) {
3553 /* nic seems like it might be stuck.. */
3554 if (rx_pause_cnt != mgp->watchdog_pause) {
3555 if (net_ratelimit())
78ca90ea
JP		 3556 netdev_err(mgp->dev, "slice %d: TX paused, check link partner\n",
3557 i);
0dcffac1 3558 } else {
78ca90ea 3559 netdev_warn(mgp->dev, "slice %d stuck:", i);
0dcffac1
BG		 3560 reset_needed = 1;
3561 }
626fda94 3562 }
d0234215
BG		 3563 if (ss->watchdog_tx_done != ss->tx.done ||
3564 ss->watchdog_rx_done != ss->rx_done.cnt) {
3565 busy_slice_cnt++;
3566 }
0dcffac1
BG		 3567 ss->watchdog_tx_done = ss->tx.done;
3568 ss->watchdog_tx_req = ss->tx.req;
d0234215
BG		 3569 ss->watchdog_rx_done = ss->rx_done.cnt;
3570 }
3571 /* if we've sent or received no traffic, poll the NIC to
3572 * ensure it is still there. Otherwise, we risk not noticing
3573 * an error in a timely fashion */
3574 if (busy_slice_cnt == 0) {
3575 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3576 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3577 reset_needed = 1;
3578 }
626fda94 3579 }
626fda94 3580 mgp->watchdog_pause = rx_pause_cnt;
0dcffac1
BG		 3581
3582 if (reset_needed) {
3583 schedule_work(&mgp->watchdog_work);
3584 } else {
3585 /* rearm timer */
3586 mod_timer(&mgp->watchdog_timer,
3587 jiffies + myri10ge_watchdog_timeout * HZ);
3588 }
0da34b6d
BG		 3589}
3590
77929732
BG		 3591static void myri10ge_free_slices(struct myri10ge_priv *mgp)
3592{
3593 struct myri10ge_slice_state *ss;
3594 struct pci_dev *pdev = mgp->pdev;
3595 size_t bytes;
3596 int i;
3597
3598 if (mgp->ss == NULL)
3599 return;
3600
3601 for (i = 0; i < mgp->num_slices; i++) {
3602 ss = &mgp->ss[i];
3603 if (ss->rx_done.entry != NULL) {
3604 bytes = mgp->max_intr_slots *
3605 sizeof(*ss->rx_done.entry);
3606 dma_free_coherent(&pdev->dev, bytes,
3607 ss->rx_done.entry, ss->rx_done.bus);
3608 ss->rx_done.entry = NULL;
3609 }
3610 if (ss->fw_stats != NULL) {
3611 bytes = sizeof(*ss->fw_stats);
3612 dma_free_coherent(&pdev->dev, bytes,
3613 ss->fw_stats, ss->fw_stats_bus);
3614 ss->fw_stats = NULL;
cda6587c 3615 netif_napi_del(&ss->napi);
77929732
BG		 3616 }
3617 }
3618 kfree(mgp->ss);
3619 mgp->ss = NULL;
3620}
3621
3622static int myri10ge_alloc_slices(struct myri10ge_priv *mgp)
3623{
3624 struct myri10ge_slice_state *ss;
3625 struct pci_dev *pdev = mgp->pdev;
3626 size_t bytes;
3627 int i;
3628
3629 bytes = sizeof(*mgp->ss) * mgp->num_slices;
3630 mgp->ss = kzalloc(bytes, GFP_KERNEL);
3631 if (mgp->ss == NULL) {
3632 return -ENOMEM;
3633 }
3634
3635 for (i = 0; i < mgp->num_slices; i++) {
3636 ss = &mgp->ss[i];
3637 bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry);
3638 ss->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3639 &ss->rx_done.bus,
3640 GFP_KERNEL);
3641 if (ss->rx_done.entry == NULL)
3642 goto abort;
3643 memset(ss->rx_done.entry, 0, bytes);
3644 bytes = sizeof(*ss->fw_stats);
3645 ss->fw_stats = dma_alloc_coherent(&pdev->dev, bytes,
3646 &ss->fw_stats_bus,
3647 GFP_KERNEL);
3648 if (ss->fw_stats == NULL)
3649 goto abort;
3650 ss->mgp = mgp;
3651 ss->dev = mgp->dev;
3652 netif_napi_add(ss->dev, &ss->napi, myri10ge_poll,
3653 myri10ge_napi_weight);
3654 }
3655 return 0;
3656abort:
3657 myri10ge_free_slices(mgp);
3658 return -ENOMEM;
3659}
3660
3661/*
3662 * This function determines the number of slices supported.
25985edc 3663 * The number slices is the minimum of the number of CPUS,
77929732
BG		 3664 * the number of MSI-X irqs supported, the number of slices
3665 * supported by the firmware
3666 */
3667static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3668{
3669 struct myri10ge_cmd cmd;
3670 struct pci_dev *pdev = mgp->pdev;
3671 char *old_fw;
7d351035 3672 bool old_allocated;
77929732
BG		 3673 int i, status, ncpus, msix_cap;
3674
3675 mgp->num_slices = 1;
3676 msix_cap = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3677 ncpus = num_online_cpus();
3678
3679 if (myri10ge_max_slices == 1 || msix_cap == 0 ||
3680 (myri10ge_max_slices == -1 && ncpus < 2))
3681 return;
3682
3683 /* try to load the slice aware rss firmware */
3684 old_fw = mgp->fw_name;
7d351035
RR		 3685 old_allocated = mgp->fw_name_allocated;
3686 /* don't free old_fw if we override it. */
3687 mgp->fw_name_allocated = false;
3688
13b2738c
BG		 3689 if (myri10ge_fw_name != NULL) {
3690 dev_info(&mgp->pdev->dev, "overriding rss firmware to %s\n",
3691 myri10ge_fw_name);
7d351035 3692 set_fw_name(mgp, myri10ge_fw_name, false);
13b2738c 3693 } else if (old_fw == myri10ge_fw_aligned)
7d351035 3694 set_fw_name(mgp, myri10ge_fw_rss_aligned, false);
77929732 3695 else
7d351035 3696 set_fw_name(mgp, myri10ge_fw_rss_unaligned, false);
77929732
BG		 3697 status = myri10ge_load_firmware(mgp, 0);
3698 if (status != 0) {
3699 dev_info(&pdev->dev, "Rss firmware not found\n");
7d351035
RR		 3700 if (old_allocated)
3701 kfree(old_fw);
77929732
BG		 3702 return;
3703 }
3704
3705 /* hit the board with a reset to ensure it is alive */
3706 memset(&cmd, 0, sizeof(cmd));
3707 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
3708 if (status != 0) {
3709 dev_err(&mgp->pdev->dev, "failed reset\n");
3710 goto abort_with_fw;
77929732
BG		 3711 }
3712
3713 mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot);
3714
3715 /* tell it the size of the interrupt queues */
3716 cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot);
3717 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
3718 if (status != 0) {
3719 dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3720 goto abort_with_fw;
3721 }
3722
3723 /* ask the maximum number of slices it supports */
3724 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0);
3725 if (status != 0)
3726 goto abort_with_fw;
3727 else
3728 mgp->num_slices = cmd.data0;
3729
3730 /* Only allow multiple slices if MSI-X is usable */
3731 if (!myri10ge_msi) {
3732 goto abort_with_fw;
3733 }
3734
3735 /* if the admin did not specify a limit to how many
3736 * slices we should use, cap it automatically to the
3737 * number of CPUs currently online */
3738 if (myri10ge_max_slices == -1)
3739 myri10ge_max_slices = ncpus;
3740
3741 if (mgp->num_slices > myri10ge_max_slices)
3742 mgp->num_slices = myri10ge_max_slices;
3743
3744 /* Now try to allocate as many MSI-X vectors as we have
3745 * slices. We give up on MSI-X if we can only get a single
3746 * vector. */
3747
baeb2ffa
JP		 3748 mgp->msix_vectors = kcalloc(mgp->num_slices, sizeof(*mgp->msix_vectors),
3749 GFP_KERNEL);
77929732
BG		 3750 if (mgp->msix_vectors == NULL)
3751 goto disable_msix;
3752 for (i = 0; i < mgp->num_slices; i++) {
3753 mgp->msix_vectors[i].entry = i;
3754 }
3755
3756 while (mgp->num_slices > 1) {
3757 /* make sure it is a power of two */
3758 while (!is_power_of_2(mgp->num_slices))
3759 mgp->num_slices--;
3760 if (mgp->num_slices == 1)
3761 goto disable_msix;
3762 status = pci_enable_msix(pdev, mgp->msix_vectors,
3763 mgp->num_slices);
3764 if (status == 0) {
3765 pci_disable_msix(pdev);
7d351035
RR		 3766 if (old_allocated)
3767 kfree(old_fw);
77929732
BG		 3768 return;
3769 }
3770 if (status > 0)
3771 mgp->num_slices = status;
3772 else
3773 goto disable_msix;
3774 }
3775
3776disable_msix:
3777 if (mgp->msix_vectors != NULL) {
3778 kfree(mgp->msix_vectors);
3779 mgp->msix_vectors = NULL;
3780 }
3781
3782abort_with_fw:
3783 mgp->num_slices = 1;
7d351035 3784 set_fw_name(mgp, old_fw, old_allocated);
77929732
BG		 3785 myri10ge_load_firmware(mgp, 0);
3786}
77929732 3787
8126089f
SH		 3788static const struct net_device_ops myri10ge_netdev_ops = {
3789 .ndo_open = myri10ge_open,
3790 .ndo_stop = myri10ge_close,
3791 .ndo_start_xmit = myri10ge_xmit,
3792 .ndo_get_stats = myri10ge_get_stats,
3793 .ndo_validate_addr = eth_validate_addr,
3794 .ndo_change_mtu = myri10ge_change_mtu,
47c2cdf5 3795 .ndo_fix_features = myri10ge_fix_features,
8126089f
SH		 3796 .ndo_set_multicast_list = myri10ge_set_multicast_list,
3797 .ndo_set_mac_address = myri10ge_set_mac_address,
3798};
3799
0da34b6d
BG		 3800static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3801{
3802 struct net_device *netdev;
3803 struct myri10ge_priv *mgp;
3804 struct device *dev = &pdev->dev;
0da34b6d
BG		 3805 int i;
3806 int status = -ENXIO;
0da34b6d 3807 int dac_enabled;
00b5e505 3808 unsigned hdr_offset, ss_offset;
2d90b0aa 3809 static int board_number;
0da34b6d 3810
236bb5e6 3811 netdev = alloc_etherdev_mq(sizeof(*mgp), MYRI10GE_MAX_SLICES);
0da34b6d
BG		 3812 if (netdev == NULL) {
3813 dev_err(dev, "Could not allocate ethernet device\n");
3814 return -ENOMEM;
3815 }
3816
b245fb67
MH		 3817 SET_NETDEV_DEV(netdev, &pdev->dev);
3818
0da34b6d 3819 mgp = netdev_priv(netdev);
0da34b6d
BG		 3820 mgp->dev = netdev;
3821 mgp->pdev = pdev;
0da34b6d
BG		 3822 mgp->pause = myri10ge_flow_control;
3823 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
c58ac5ca 3824 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
2d90b0aa 3825 mgp->board_number = board_number;
0da34b6d
BG		 3826 init_waitqueue_head(&mgp->down_wq);
3827
3828 if (pci_enable_device(pdev)) {
3829 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3830 status = -ENODEV;
3831 goto abort_with_netdev;
3832 }
0da34b6d
BG		 3833
3834 /* Find the vendor-specific cap so we can check
3835 * the reboot register later on */
3836 mgp->vendor_specific_offset
3837 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3838
3839 /* Set our max read request to 4KB */
302d242c 3840 status = pcie_set_readrq(pdev, 4096);
0da34b6d
BG		 3841 if (status != 0) {
3842 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3843 status);
e3fd5534 3844 goto abort_with_enabled;
0da34b6d
BG		 3845 }
3846
3847 pci_set_master(pdev);
3848 dac_enabled = 1;
6a35528a 3849 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
0da34b6d
BG		 3850 if (status != 0) {
3851 dac_enabled = 0;
3852 dev_err(&pdev->dev,
898eb71c
JP		 3853 "64-bit pci address mask was refused, "
3854 "trying 32-bit\n");
284901a9 3855 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
0da34b6d
BG		 3856 }
3857 if (status != 0) {
3858 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
e3fd5534 3859 goto abort_with_enabled;
0da34b6d 3860 }
6a35528a 3861 (void)pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
b10c0668
BG		 3862 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3863 &mgp->cmd_bus, GFP_KERNEL);
0da34b6d 3864 if (mgp->cmd == NULL)
e3fd5534 3865 goto abort_with_enabled;
0da34b6d 3866
0da34b6d
BG		 3867 mgp->board_span = pci_resource_len(pdev, 0);
3868 mgp->iomem_base = pci_resource_start(pdev, 0);
3869 mgp->mtrr = -1;
276e26c3 3870 mgp->wc_enabled = 0;
0da34b6d
BG		 3871#ifdef CONFIG_MTRR
3872 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3873 MTRR_TYPE_WRCOMB, 1);
276e26c3
BG		 3874 if (mgp->mtrr >= 0)
3875 mgp->wc_enabled = 1;
0da34b6d 3876#endif
c7f80993 3877 mgp->sram = ioremap_wc(mgp->iomem_base, mgp->board_span);
0da34b6d
BG		 3878 if (mgp->sram == NULL) {
3879 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3880 mgp->board_span, mgp->iomem_base);
3881 status = -ENXIO;
c7f80993 3882 goto abort_with_mtrr;
0da34b6d 3883 }
00b5e505
BG		 3884 hdr_offset =
3885 ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET)) & 0xffffc;
3886 ss_offset = hdr_offset + offsetof(struct mcp_gen_header, string_specs);
3887 mgp->sram_size = ntohl(__raw_readl(mgp->sram + ss_offset));
3888 if (mgp->sram_size > mgp->board_span ||
3889 mgp->sram_size <= MYRI10GE_FW_OFFSET) {
3890 dev_err(&pdev->dev,
3891 "invalid sram_size %dB or board span %ldB\n",
3892 mgp->sram_size, mgp->board_span);
3893 goto abort_with_ioremap;
3894 }
0da34b6d 3895 memcpy_fromio(mgp->eeprom_strings,
00b5e505 3896 mgp->sram + mgp->sram_size, MYRI10GE_EEPROM_STRINGS_SIZE);
0da34b6d
BG		 3897 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3898 status = myri10ge_read_mac_addr(mgp);
3899 if (status)
3900 goto abort_with_ioremap;
3901
3902 for (i = 0; i < ETH_ALEN; i++)
3903 netdev->dev_addr[i] = mgp->mac_addr[i];
3904
5443e9ea
BG		 3905 myri10ge_select_firmware(mgp);
3906
0dcffac1 3907 status = myri10ge_load_firmware(mgp, 1);
0da34b6d
BG		 3908 if (status != 0) {
3909 dev_err(&pdev->dev, "failed to load firmware\n");
0dcffac1
BG		 3910 goto abort_with_ioremap;
3911 }
3912 myri10ge_probe_slices(mgp);
3913 status = myri10ge_alloc_slices(mgp);
3914 if (status != 0) {
3915 dev_err(&pdev->dev, "failed to alloc slice state\n");
3916 goto abort_with_firmware;
0da34b6d 3917 }
c9920268
BH		 3918 netif_set_real_num_tx_queues(netdev, mgp->num_slices);
3919 netif_set_real_num_rx_queues(netdev, mgp->num_slices);
0da34b6d
BG		 3920 status = myri10ge_reset(mgp);
3921 if (status != 0) {
3922 dev_err(&pdev->dev, "failed reset\n");
0dcffac1 3923 goto abort_with_slices;
0da34b6d 3924 }
5dd2d332 3925#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 3926 myri10ge_setup_dca(mgp);
3927#endif
0da34b6d
BG		 3928 pci_set_drvdata(pdev, mgp);
3929 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3930 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3931 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3932 myri10ge_initial_mtu = 68;
8126089f
SH		 3933
3934 netdev->netdev_ops = &myri10ge_netdev_ops;
0da34b6d 3935 netdev->mtu = myri10ge_initial_mtu;
0da34b6d 3936 netdev->base_addr = mgp->iomem_base;
47c2cdf5
MM		 3937 netdev->hw_features = mgp->features | NETIF_F_LRO | NETIF_F_RXCSUM;
3938 netdev->features = netdev->hw_features;
236bb5e6 3939
0da34b6d
BG		 3940 if (dac_enabled)
3941 netdev->features |= NETIF_F_HIGHDMA;
0da34b6d 3942
dddc045e
BG		 3943 netdev->vlan_features |= mgp->features;
3944 if (mgp->fw_ver_tiny < 37)
3945 netdev->vlan_features &= ~NETIF_F_TSO6;
3946 if (mgp->fw_ver_tiny < 32)
3947 netdev->vlan_features &= ~NETIF_F_TSO;
3948
21d05db1
BG		 3949 /* make sure we can get an irq, and that MSI can be
3950 * setup (if available). Also ensure netdev->irq
3951 * is set to correct value if MSI is enabled */
3952 status = myri10ge_request_irq(mgp);
3953 if (status != 0)
3954 goto abort_with_firmware;
3955 netdev->irq = pdev->irq;
3956 myri10ge_free_irq(mgp);
3957
0da34b6d
BG		 3958 /* Save configuration space to be restored if the
3959 * nic resets due to a parity error */
83f6e152 3960 pci_save_state(pdev);
0da34b6d
BG		 3961
3962 /* Setup the watchdog timer */
3963 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3964 (unsigned long)mgp);
3965
59081825 3966 spin_lock_init(&mgp->stats_lock);
0da34b6d 3967 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
c4028958 3968 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
0da34b6d
BG		 3969 status = register_netdev(netdev);
3970 if (status != 0) {
3971 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
7adda30c 3972 goto abort_with_state;
0da34b6d 3973 }
0dcffac1
BG		 3974 if (mgp->msix_enabled)
3975 dev_info(dev, "%d MSI-X IRQs, tx bndry %d, fw %s, WC %s\n",
3976 mgp->num_slices, mgp->tx_boundary, mgp->fw_name,
3977 (mgp->wc_enabled ? "Enabled" : "Disabled"));
3978 else
3979 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3980 mgp->msi_enabled ? "MSI" : "xPIC",
3981 netdev->irq, mgp->tx_boundary, mgp->fw_name,
3982 (mgp->wc_enabled ? "Enabled" : "Disabled"));
0da34b6d 3983
2d90b0aa 3984 board_number++;
0da34b6d
BG		 3985 return 0;
3986
7adda30c 3987abort_with_state:
83f6e152 3988 pci_restore_state(pdev);
0da34b6d 3989
0dcffac1
BG		 3990abort_with_slices:
3991 myri10ge_free_slices(mgp);
3992
0da34b6d
BG		 3993abort_with_firmware:
3994 myri10ge_dummy_rdma(mgp, 0);
3995
0da34b6d 3996abort_with_ioremap:
0f840011
BG		 3997 if (mgp->mac_addr_string != NULL)
3998 dev_err(&pdev->dev,
3999 "myri10ge_probe() failed: MAC=%s, SN=%ld\n",
4000 mgp->mac_addr_string, mgp->serial_number);
0da34b6d
BG		 4001 iounmap(mgp->sram);
4002
c7f80993 4003abort_with_mtrr:
0da34b6d
BG		 4004#ifdef CONFIG_MTRR
4005 if (mgp->mtrr >= 0)
4006 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
4007#endif
b10c0668
BG		 4008 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
4009 mgp->cmd, mgp->cmd_bus);
0da34b6d 4010
e3fd5534
BG		 4011abort_with_enabled:
4012 pci_disable_device(pdev);
0da34b6d 4013
e3fd5534 4014abort_with_netdev:
7d351035 4015 set_fw_name(mgp, NULL, false);
0da34b6d
BG		 4016 free_netdev(netdev);
4017 return status;
4018}
4019
4020/*
4021 * myri10ge_remove
4022 *
4023 * Does what is necessary to shutdown one Myrinet device. Called
4024 * once for each Myrinet card by the kernel when a module is
4025 * unloaded.
4026 */
4027static void myri10ge_remove(struct pci_dev *pdev)
4028{
4029 struct myri10ge_priv *mgp;
4030 struct net_device *netdev;
0da34b6d
BG		 4031
4032 mgp = pci_get_drvdata(pdev);
4033 if (mgp == NULL)
4034 return;
4035
23f333a2 4036 cancel_work_sync(&mgp->watchdog_work);
0da34b6d
BG		 4037 netdev = mgp->dev;
4038 unregister_netdev(netdev);
0da34b6d 4039
5dd2d332 4040#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4041 myri10ge_teardown_dca(mgp);
4042#endif
0da34b6d
BG		 4043 myri10ge_dummy_rdma(mgp, 0);
4044
7adda30c 4045 /* avoid a memory leak */
83f6e152 4046 pci_restore_state(pdev);
7adda30c 4047
0da34b6d
BG		 4048 iounmap(mgp->sram);
4049
4050#ifdef CONFIG_MTRR
4051 if (mgp->mtrr >= 0)
4052 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
4053#endif
0dcffac1
BG		 4054 myri10ge_free_slices(mgp);
4055 if (mgp->msix_vectors != NULL)
4056 kfree(mgp->msix_vectors);
b10c0668
BG		 4057 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
4058 mgp->cmd, mgp->cmd_bus);
0da34b6d 4059
7d351035 4060 set_fw_name(mgp, NULL, false);
0da34b6d 4061 free_netdev(netdev);
e3fd5534 4062 pci_disable_device(pdev);
0da34b6d
BG		 4063 pci_set_drvdata(pdev, NULL);
4064}
4065
b10c0668 4066#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
a07bc1ff 4067#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
0da34b6d 4068
a3aa1884 4069static DEFINE_PCI_DEVICE_TABLE(myri10ge_pci_tbl) = {
b10c0668 4070 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
a07bc1ff
BG		 4071 {PCI_DEVICE
4072 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
0da34b6d
BG		 4073 {0},
4074};
4075
97131079
BG		 4076MODULE_DEVICE_TABLE(pci, myri10ge_pci_tbl);
4077
0da34b6d
BG		 4078static struct pci_driver myri10ge_driver = {
4079 .name = "myri10ge",
4080 .probe = myri10ge_probe,
4081 .remove = myri10ge_remove,
4082 .id_table = myri10ge_pci_tbl,
4083#ifdef CONFIG_PM
4084 .suspend = myri10ge_suspend,
4085 .resume = myri10ge_resume,
4086#endif
4087};
4088
5dd2d332 4089#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4090static int
4091myri10ge_notify_dca(struct notifier_block *nb, unsigned long event, void *p)
4092{
4093 int err = driver_for_each_device(&myri10ge_driver.driver,
4094 NULL, &event,
4095 myri10ge_notify_dca_device);
4096
4097 if (err)
4098 return NOTIFY_BAD;
4099 return NOTIFY_DONE;
4100}
4101
4102static struct notifier_block myri10ge_dca_notifier = {
4103 .notifier_call = myri10ge_notify_dca,
4104 .next = NULL,
4105 .priority = 0,
4106};
4ee2ac51 4107#endif /* CONFIG_MYRI10GE_DCA */
981813d8 4108
0da34b6d
BG		 4109static __init int myri10ge_init_module(void)
4110{
78ca90ea 4111 pr_info("Version %s\n", MYRI10GE_VERSION_STR);
0dcffac1 4112
236bb5e6 4113 if (myri10ge_rss_hash > MXGEFW_RSS_HASH_TYPE_MAX) {
78ca90ea
JP		 4114 pr_err("Illegal rssh hash type %d, defaulting to source port\n",
4115 myri10ge_rss_hash);
0dcffac1
BG		 4116 myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
4117 }
5dd2d332 4118#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4119 dca_register_notify(&myri10ge_dca_notifier);
4120#endif
236bb5e6
BG		 4121 if (myri10ge_max_slices > MYRI10GE_MAX_SLICES)
4122 myri10ge_max_slices = MYRI10GE_MAX_SLICES;
0dcffac1 4123
0da34b6d
BG		 4124 return pci_register_driver(&myri10ge_driver);
4125}
4126
4127module_init(myri10ge_init_module);
4128
4129static __exit void myri10ge_cleanup_module(void)
4130{
5dd2d332 4131#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4132 dca_unregister_notify(&myri10ge_dca_notifier);
4133#endif
0da34b6d
BG		 4134 pci_unregister_driver(&myri10ge_driver);
4135}
4136
4137module_exit(myri10ge_cleanup_module);
Linux kernel - Deliverables
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