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myri10ge: fix restoring of multicast list after reset
[deliverable/linux.git] / drivers / net / myri10ge / myri10ge.c
CommitLineData
0da34b6d
BG		 1/*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4a2e612a 4 * Copyright (C) 2005 - 2007 Myricom, Inc.
0da34b6d
BG		 5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
4a2e612a
BG		 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0da34b6d 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4a2e612a
BG		 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
0da34b6d
BG		 30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41#include <linux/tcp.h>
42#include <linux/netdevice.h>
43#include <linux/skbuff.h>
44#include <linux/string.h>
45#include <linux/module.h>
46#include <linux/pci.h>
b10c0668 47#include <linux/dma-mapping.h>
0da34b6d
BG		 48#include <linux/etherdevice.h>
49#include <linux/if_ether.h>
50#include <linux/if_vlan.h>
51#include <linux/ip.h>
52#include <linux/inet.h>
53#include <linux/in.h>
54#include <linux/ethtool.h>
55#include <linux/firmware.h>
56#include <linux/delay.h>
57#include <linux/version.h>
58#include <linux/timer.h>
59#include <linux/vmalloc.h>
60#include <linux/crc32.h>
61#include <linux/moduleparam.h>
62#include <linux/io.h>
63#include <net/checksum.h>
64#include <asm/byteorder.h>
65#include <asm/io.h>
0da34b6d
BG		 66#include <asm/processor.h>
67#ifdef CONFIG_MTRR
68#include <asm/mtrr.h>
69#endif
70
71#include "myri10ge_mcp.h"
72#include "myri10ge_mcp_gen_header.h"
73
4b2281c7 74#define MYRI10GE_VERSION_STR "1.3.0-1.233"
0da34b6d
BG		 75
76MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
77MODULE_AUTHOR("Maintainer: help@myri.com");
78MODULE_VERSION(MYRI10GE_VERSION_STR);
79MODULE_LICENSE("Dual BSD/GPL");
80
81#define MYRI10GE_MAX_ETHER_MTU 9014
82
83#define MYRI10GE_ETH_STOPPED 0
84#define MYRI10GE_ETH_STOPPING 1
85#define MYRI10GE_ETH_STARTING 2
86#define MYRI10GE_ETH_RUNNING 3
87#define MYRI10GE_ETH_OPEN_FAILED 4
88
89#define MYRI10GE_EEPROM_STRINGS_SIZE 256
90#define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
91
40f6cff5 92#define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
0da34b6d
BG		 93#define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
94
dd50f336
BG		 95#define MYRI10GE_ALLOC_ORDER 0
96#define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
97#define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
98
0da34b6d 99struct myri10ge_rx_buffer_state {
dd50f336
BG		 100 struct page *page;
101 int page_offset;
0da34b6d
BG		 102 DECLARE_PCI_UNMAP_ADDR(bus)
103 DECLARE_PCI_UNMAP_LEN(len)
104};
105
106struct myri10ge_tx_buffer_state {
107 struct sk_buff *skb;
108 int last;
109 DECLARE_PCI_UNMAP_ADDR(bus)
110 DECLARE_PCI_UNMAP_LEN(len)
111};
112
113struct myri10ge_cmd {
114 u32 data0;
115 u32 data1;
116 u32 data2;
117};
118
119struct myri10ge_rx_buf {
120 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
121 u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */
122 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
123 struct myri10ge_rx_buffer_state *info;
dd50f336
BG		 124 struct page *page;
125 dma_addr_t bus;
126 int page_offset;
0da34b6d 127 int cnt;
dd50f336 128 int fill_cnt;
0da34b6d
BG		 129 int alloc_fail;
130 int mask; /* number of rx slots -1 */
dd50f336 131 int watchdog_needed;
0da34b6d
BG		 132};
133
134struct myri10ge_tx_buf {
135 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
136 u8 __iomem *wc_fifo; /* w/c send fifo address */
137 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
138 char *req_bytes;
139 struct myri10ge_tx_buffer_state *info;
140 int mask; /* number of transmit slots -1 */
141 int boundary; /* boundary transmits cannot cross */
142 int req ____cacheline_aligned; /* transmit slots submitted */
143 int pkt_start; /* packets started */
144 int done ____cacheline_aligned; /* transmit slots completed */
145 int pkt_done; /* packets completed */
146};
147
148struct myri10ge_rx_done {
149 struct mcp_slot *entry;
150 dma_addr_t bus;
151 int cnt;
152 int idx;
153};
154
155struct myri10ge_priv {
156 int running; /* running? */
157 int csum_flag; /* rx_csums? */
158 struct myri10ge_tx_buf tx; /* transmit ring */
159 struct myri10ge_rx_buf rx_small;
160 struct myri10ge_rx_buf rx_big;
161 struct myri10ge_rx_done rx_done;
162 int small_bytes;
dd50f336 163 int big_bytes;
0da34b6d
BG		 164 struct net_device *dev;
165 struct net_device_stats stats;
166 u8 __iomem *sram;
167 int sram_size;
168 unsigned long board_span;
169 unsigned long iomem_base;
40f6cff5
AV		 170 __be32 __iomem *irq_claim;
171 __be32 __iomem *irq_deassert;
0da34b6d
BG		 172 char *mac_addr_string;
173 struct mcp_cmd_response *cmd;
174 dma_addr_t cmd_bus;
175 struct mcp_irq_data *fw_stats;
176 dma_addr_t fw_stats_bus;
177 struct pci_dev *pdev;
178 int msi_enabled;
40f6cff5 179 __be32 link_state;
0da34b6d
BG		 180 unsigned int rdma_tags_available;
181 int intr_coal_delay;
40f6cff5 182 __be32 __iomem *intr_coal_delay_ptr;
0da34b6d 183 int mtrr;
276e26c3 184 int wc_enabled;
0da34b6d
BG		 185 int wake_queue;
186 int stop_queue;
187 int down_cnt;
188 wait_queue_head_t down_wq;
189 struct work_struct watchdog_work;
190 struct timer_list watchdog_timer;
191 int watchdog_tx_done;
c54772e7 192 int watchdog_tx_req;
0da34b6d
BG		 193 int watchdog_resets;
194 int tx_linearized;
195 int pause;
196 char *fw_name;
197 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
198 char fw_version[128];
9dc6f0e7
BG		 199 int fw_ver_major;
200 int fw_ver_minor;
201 int fw_ver_tiny;
202 int adopted_rx_filter_bug;
0da34b6d
BG		 203 u8 mac_addr[6]; /* eeprom mac address */
204 unsigned long serial_number;
205 int vendor_specific_offset;
85a7ea1b 206 int fw_multicast_support;
0da34b6d
BG		 207 u32 read_dma;
208 u32 write_dma;
209 u32 read_write_dma;
c58ac5ca
BG		 210 u32 link_changes;
211 u32 msg_enable;
0da34b6d
BG		 212};
213
214static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
215static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
216
217static char *myri10ge_fw_name = NULL;
218module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
219MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name\n");
220
221static int myri10ge_ecrc_enable = 1;
222module_param(myri10ge_ecrc_enable, int, S_IRUGO);
223MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E\n");
224
225static int myri10ge_max_intr_slots = 1024;
226module_param(myri10ge_max_intr_slots, int, S_IRUGO);
227MODULE_PARM_DESC(myri10ge_max_intr_slots, "Interrupt queue slots\n");
228
229static int myri10ge_small_bytes = -1; /* -1 == auto */
230module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
231MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets\n");
232
233static int myri10ge_msi = 1; /* enable msi by default */
3621cec5 234module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
0da34b6d
BG		 235MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts\n");
236
f761fae1 237static int myri10ge_intr_coal_delay = 75;
0da34b6d
BG		 238module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
239MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay\n");
240
241static int myri10ge_flow_control = 1;
242module_param(myri10ge_flow_control, int, S_IRUGO);
243MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter\n");
244
245static int myri10ge_deassert_wait = 1;
246module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
247MODULE_PARM_DESC(myri10ge_deassert_wait,
248 "Wait when deasserting legacy interrupts\n");
249
250static int myri10ge_force_firmware = 0;
251module_param(myri10ge_force_firmware, int, S_IRUGO);
252MODULE_PARM_DESC(myri10ge_force_firmware,
253 "Force firmware to assume aligned completions\n");
254
0da34b6d
BG		 255static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
256module_param(myri10ge_initial_mtu, int, S_IRUGO);
257MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU\n");
258
259static int myri10ge_napi_weight = 64;
260module_param(myri10ge_napi_weight, int, S_IRUGO);
261MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight\n");
262
263static int myri10ge_watchdog_timeout = 1;
264module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
265MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout\n");
266
267static int myri10ge_max_irq_loops = 1048576;
268module_param(myri10ge_max_irq_loops, int, S_IRUGO);
269MODULE_PARM_DESC(myri10ge_max_irq_loops,
270 "Set stuck legacy IRQ detection threshold\n");
271
c58ac5ca
BG		 272#define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
273
274static int myri10ge_debug = -1; /* defaults above */
275module_param(myri10ge_debug, int, 0);
276MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
277
dd50f336
BG		 278static int myri10ge_fill_thresh = 256;
279module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
280MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed\n");
281
f761fae1 282static int myri10ge_wcfifo = 0;
6ebc087a
BG		 283module_param(myri10ge_wcfifo, int, S_IRUGO);
284MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled\n");
285
0da34b6d
BG		 286#define MYRI10GE_FW_OFFSET 1024*1024
287#define MYRI10GE_HIGHPART_TO_U32(X) \
288(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
289#define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
290
291#define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
292
2f76216f
BG		 293static void myri10ge_set_multicast_list(struct net_device *dev);
294
6250223e 295static inline void put_be32(__be32 val, __be32 __iomem * p)
40f6cff5 296{
6250223e 297 __raw_writel((__force __u32) val, (__force void __iomem *)p);
40f6cff5
AV		 298}
299
0da34b6d
BG		 300static int
301myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
302 struct myri10ge_cmd *data, int atomic)
303{
304 struct mcp_cmd *buf;
305 char buf_bytes[sizeof(*buf) + 8];
306 struct mcp_cmd_response *response = mgp->cmd;
e700f9f4 307 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
0da34b6d
BG		 308 u32 dma_low, dma_high, result, value;
309 int sleep_total = 0;
310
311 /* ensure buf is aligned to 8 bytes */
312 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
313
314 buf->data0 = htonl(data->data0);
315 buf->data1 = htonl(data->data1);
316 buf->data2 = htonl(data->data2);
317 buf->cmd = htonl(cmd);
318 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
319 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
320
321 buf->response_addr.low = htonl(dma_low);
322 buf->response_addr.high = htonl(dma_high);
40f6cff5 323 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 324 mb();
325 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
326
327 /* wait up to 15ms. Longest command is the DMA benchmark,
328 * which is capped at 5ms, but runs from a timeout handler
329 * that runs every 7.8ms. So a 15ms timeout leaves us with
330 * a 2.2ms margin
331 */
332 if (atomic) {
333 /* if atomic is set, do not sleep,
334 * and try to get the completion quickly
335 * (1ms will be enough for those commands) */
336 for (sleep_total = 0;
337 sleep_total < 1000
40f6cff5 338 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 339 sleep_total += 10)
340 udelay(10);
341 } else {
342 /* use msleep for most command */
343 for (sleep_total = 0;
344 sleep_total < 15
40f6cff5 345 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 346 sleep_total++)
347 msleep(1);
348 }
349
350 result = ntohl(response->result);
351 value = ntohl(response->data);
352 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
353 if (result == 0) {
354 data->data0 = value;
355 return 0;
85a7ea1b
BG		 356 } else if (result == MXGEFW_CMD_UNKNOWN) {
357 return -ENOSYS;
0da34b6d
BG		 358 } else {
359 dev_err(&mgp->pdev->dev,
360 "command %d failed, result = %d\n",
361 cmd, result);
362 return -ENXIO;
363 }
364 }
365
366 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
367 cmd, result);
368 return -EAGAIN;
369}
370
371/*
372 * The eeprom strings on the lanaiX have the format
373 * SN=x\0
374 * MAC=x:x:x:x:x:x\0
375 * PT:ddd mmm xx xx:xx:xx xx\0
376 * PV:ddd mmm xx xx:xx:xx xx\0
377 */
378static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
379{
380 char *ptr, *limit;
381 int i;
382
383 ptr = mgp->eeprom_strings;
384 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
385
386 while (*ptr != '\0' && ptr < limit) {
387 if (memcmp(ptr, "MAC=", 4) == 0) {
388 ptr += 4;
389 mgp->mac_addr_string = ptr;
390 for (i = 0; i < 6; i++) {
391 if ((ptr + 2) > limit)
392 goto abort;
393 mgp->mac_addr[i] =
394 simple_strtoul(ptr, &ptr, 16);
395 ptr += 1;
396 }
397 }
398 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
399 ptr += 3;
400 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
401 }
402 while (ptr < limit && *ptr++) ;
403 }
404
405 return 0;
406
407abort:
408 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
409 return -ENXIO;
410}
411
412/*
413 * Enable or disable periodic RDMAs from the host to make certain
414 * chipsets resend dropped PCIe messages
415 */
416
417static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
418{
419 char __iomem *submit;
40f6cff5 420 __be32 buf[16];
0da34b6d
BG		 421 u32 dma_low, dma_high;
422 int i;
423
424 /* clear confirmation addr */
425 mgp->cmd->data = 0;
426 mb();
427
428 /* send a rdma command to the PCIe engine, and wait for the
429 * response in the confirmation address. The firmware should
430 * write a -1 there to indicate it is alive and well
431 */
432 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
433 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
434
435 buf[0] = htonl(dma_high); /* confirm addr MSW */
436 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 437 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 438 buf[3] = htonl(dma_high); /* dummy addr MSW */
439 buf[4] = htonl(dma_low); /* dummy addr LSW */
440 buf[5] = htonl(enable); /* enable? */
441
e700f9f4 442 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
0da34b6d
BG		 443
444 myri10ge_pio_copy(submit, &buf, sizeof(buf));
445 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
446 msleep(1);
447 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
448 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
449 (enable ? "enable" : "disable"));
450}
451
452static int
453myri10ge_validate_firmware(struct myri10ge_priv *mgp,
454 struct mcp_gen_header *hdr)
455{
456 struct device *dev = &mgp->pdev->dev;
0da34b6d
BG		 457
458 /* check firmware type */
459 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
460 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
461 return -EINVAL;
462 }
463
464 /* save firmware version for ethtool */
465 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
466
9dc6f0e7
BG		 467 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
468 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
0da34b6d 469
9dc6f0e7
BG		 470 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
471 && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
0da34b6d
BG		 472 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
473 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
474 MXGEFW_VERSION_MINOR);
475 return -EINVAL;
476 }
477 return 0;
478}
479
480static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
481{
482 unsigned crc, reread_crc;
483 const struct firmware *fw;
484 struct device *dev = &mgp->pdev->dev;
485 struct mcp_gen_header *hdr;
486 size_t hdr_offset;
487 int status;
e454358a 488 unsigned i;
0da34b6d
BG		 489
490 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
491 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
492 mgp->fw_name);
493 status = -EINVAL;
494 goto abort_with_nothing;
495 }
496
497 /* check size */
498
499 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
500 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
501 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
502 status = -EINVAL;
503 goto abort_with_fw;
504 }
505
506 /* check id */
40f6cff5 507 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 508 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
509 dev_err(dev, "Bad firmware file\n");
510 status = -EINVAL;
511 goto abort_with_fw;
512 }
513 hdr = (void *)(fw->data + hdr_offset);
514
515 status = myri10ge_validate_firmware(mgp, hdr);
516 if (status != 0)
517 goto abort_with_fw;
518
519 crc = crc32(~0, fw->data, fw->size);
e454358a
BG		 520 for (i = 0; i < fw->size; i += 256) {
521 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
522 fw->data + i,
523 min(256U, (unsigned)(fw->size - i)));
524 mb();
525 readb(mgp->sram);
b10c0668 526 }
0da34b6d
BG		 527 /* corruption checking is good for parity recovery and buggy chipset */
528 memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
529 reread_crc = crc32(~0, fw->data, fw->size);
530 if (crc != reread_crc) {
531 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
532 (unsigned)fw->size, reread_crc, crc);
533 status = -EIO;
534 goto abort_with_fw;
535 }
536 *size = (u32) fw->size;
537
538abort_with_fw:
539 release_firmware(fw);
540
541abort_with_nothing:
542 return status;
543}
544
545static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
546{
547 struct mcp_gen_header *hdr;
548 struct device *dev = &mgp->pdev->dev;
549 const size_t bytes = sizeof(struct mcp_gen_header);
550 size_t hdr_offset;
551 int status;
552
553 /* find running firmware header */
554 hdr_offset = ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
555
556 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
557 dev_err(dev, "Running firmware has bad header offset (%d)\n",
558 (int)hdr_offset);
559 return -EIO;
560 }
561
562 /* copy header of running firmware from SRAM to host memory to
563 * validate firmware */
564 hdr = kmalloc(bytes, GFP_KERNEL);
565 if (hdr == NULL) {
566 dev_err(dev, "could not malloc firmware hdr\n");
567 return -ENOMEM;
568 }
569 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
570 status = myri10ge_validate_firmware(mgp, hdr);
571 kfree(hdr);
9dc6f0e7
BG		 572
573 /* check to see if adopted firmware has bug where adopting
574 * it will cause broadcasts to be filtered unless the NIC
575 * is kept in ALLMULTI mode */
576 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
577 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
578 mgp->adopted_rx_filter_bug = 1;
579 dev_warn(dev, "Adopting fw %d.%d.%d: "
580 "working around rx filter bug\n",
581 mgp->fw_ver_major, mgp->fw_ver_minor,
582 mgp->fw_ver_tiny);
583 }
0da34b6d
BG		 584 return status;
585}
586
587static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
588{
589 char __iomem *submit;
40f6cff5 590 __be32 buf[16];
0da34b6d
BG		 591 u32 dma_low, dma_high, size;
592 int status, i;
593
b10c0668 594 size = 0;
0da34b6d
BG		 595 status = myri10ge_load_hotplug_firmware(mgp, &size);
596 if (status) {
597 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
598
599 /* Do not attempt to adopt firmware if there
600 * was a bad crc */
601 if (status == -EIO)
602 return status;
603
604 status = myri10ge_adopt_running_firmware(mgp);
605 if (status != 0) {
606 dev_err(&mgp->pdev->dev,
607 "failed to adopt running firmware\n");
608 return status;
609 }
610 dev_info(&mgp->pdev->dev,
611 "Successfully adopted running firmware\n");
612 if (mgp->tx.boundary == 4096) {
613 dev_warn(&mgp->pdev->dev,
614 "Using firmware currently running on NIC"
615 ". For optimal\n");
616 dev_warn(&mgp->pdev->dev,
617 "performance consider loading optimized "
618 "firmware\n");
619 dev_warn(&mgp->pdev->dev, "via hotplug\n");
620 }
621
622 mgp->fw_name = "adopted";
623 mgp->tx.boundary = 2048;
624 return status;
625 }
626
627 /* clear confirmation addr */
628 mgp->cmd->data = 0;
629 mb();
630
631 /* send a reload command to the bootstrap MCP, and wait for the
632 * response in the confirmation address. The firmware should
633 * write a -1 there to indicate it is alive and well
634 */
635 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
636 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
637
638 buf[0] = htonl(dma_high); /* confirm addr MSW */
639 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 640 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 641
642 /* FIX: All newest firmware should un-protect the bottom of
643 * the sram before handoff. However, the very first interfaces
644 * do not. Therefore the handoff copy must skip the first 8 bytes
645 */
646 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
647 buf[4] = htonl(size - 8); /* length of code */
648 buf[5] = htonl(8); /* where to copy to */
649 buf[6] = htonl(0); /* where to jump to */
650
e700f9f4 651 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
0da34b6d
BG		 652
653 myri10ge_pio_copy(submit, &buf, sizeof(buf));
654 mb();
655 msleep(1);
656 mb();
657 i = 0;
658 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20) {
659 msleep(1);
660 i++;
661 }
662 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
663 dev_err(&mgp->pdev->dev, "handoff failed\n");
664 return -ENXIO;
665 }
666 dev_info(&mgp->pdev->dev, "handoff confirmed\n");
9a71db72 667 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 668
669 return 0;
670}
671
672static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
673{
674 struct myri10ge_cmd cmd;
675 int status;
676
677 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
678 | (addr[2] << 8) | addr[3]);
679
680 cmd.data1 = ((addr[4] << 8) | (addr[5]));
681
682 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
683 return status;
684}
685
686static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
687{
688 struct myri10ge_cmd cmd;
689 int status, ctl;
690
691 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
692 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
693
694 if (status) {
695 printk(KERN_ERR
696 "myri10ge: %s: Failed to set flow control mode\n",
697 mgp->dev->name);
698 return status;
699 }
700 mgp->pause = pause;
701 return 0;
702}
703
704static void
705myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
706{
707 struct myri10ge_cmd cmd;
708 int status, ctl;
709
710 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
711 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
712 if (status)
713 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
714 mgp->dev->name);
715}
716
717static int myri10ge_reset(struct myri10ge_priv *mgp)
718{
719 struct myri10ge_cmd cmd;
720 int status;
721 size_t bytes;
722 u32 len;
34fdccea
BG		 723 struct page *dmatest_page;
724 dma_addr_t dmatest_bus;
0da34b6d
BG		 725
726 /* try to send a reset command to the card to see if it
727 * is alive */
728 memset(&cmd, 0, sizeof(cmd));
729 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
730 if (status != 0) {
731 dev_err(&mgp->pdev->dev, "failed reset\n");
732 return -ENXIO;
733 }
34fdccea
BG		 734 dmatest_page = alloc_page(GFP_KERNEL);
735 if (!dmatest_page)
736 return -ENOMEM;
737 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
738 DMA_BIDIRECTIONAL);
0da34b6d
BG		 739
740 /* Now exchange information about interrupts */
741
742 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
743 memset(mgp->rx_done.entry, 0, bytes);
744 cmd.data0 = (u32) bytes;
745 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
746 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
747 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
748 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0);
749
750 status |=
751 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
40f6cff5 752 mgp->irq_claim = (__iomem __be32 *) (mgp->sram + cmd.data0);
df30a740
BG		 753 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
754 &cmd, 0);
755 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d 756
0da34b6d
BG		 757 status |= myri10ge_send_cmd
758 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
40f6cff5 759 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d
BG		 760 if (status != 0) {
761 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
762 return status;
763 }
40f6cff5 764 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 765
766 /* Run a small DMA test.
767 * The magic multipliers to the length tell the firmware
768 * to do DMA read, write, or read+write tests. The
769 * results are returned in cmd.data0. The upper 16
770 * bits or the return is the number of transfers completed.
771 * The lower 16 bits is the time in 0.5us ticks that the
772 * transfers took to complete.
773 */
774
775 len = mgp->tx.boundary;
776
34fdccea
BG		 777 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
778 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
0da34b6d
BG		 779 cmd.data2 = len * 0x10000;
780 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
781 if (status == 0)
782 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) /
783 (cmd.data0 & 0xffff);
784 else
785 dev_warn(&mgp->pdev->dev, "DMA read benchmark failed: %d\n",
786 status);
34fdccea
BG		 787 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
788 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
0da34b6d
BG		 789 cmd.data2 = len * 0x1;
790 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
791 if (status == 0)
792 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) /
793 (cmd.data0 & 0xffff);
794 else
795 dev_warn(&mgp->pdev->dev, "DMA write benchmark failed: %d\n",
796 status);
797
34fdccea
BG		 798 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
799 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
0da34b6d
BG		 800 cmd.data2 = len * 0x10001;
801 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
802 if (status == 0)
803 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
804 (cmd.data0 & 0xffff);
805 else
806 dev_warn(&mgp->pdev->dev,
807 "DMA read/write benchmark failed: %d\n", status);
808
34fdccea
BG		 809 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
810 put_page(dmatest_page);
811
0da34b6d
BG		 812 memset(mgp->rx_done.entry, 0, bytes);
813
814 /* reset mcp/driver shared state back to 0 */
815 mgp->tx.req = 0;
816 mgp->tx.done = 0;
817 mgp->tx.pkt_start = 0;
818 mgp->tx.pkt_done = 0;
819 mgp->rx_big.cnt = 0;
820 mgp->rx_small.cnt = 0;
821 mgp->rx_done.idx = 0;
822 mgp->rx_done.cnt = 0;
c58ac5ca 823 mgp->link_changes = 0;
0da34b6d 824 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
0da34b6d 825 myri10ge_change_pause(mgp, mgp->pause);
2f76216f 826 myri10ge_set_multicast_list(mgp->dev);
0da34b6d
BG		 827 return status;
828}
829
830static inline void
831myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
832 struct mcp_kreq_ether_recv *src)
833{
40f6cff5 834 __be32 low;
0da34b6d
BG		 835
836 low = src->addr_low;
40f6cff5 837 src->addr_low = htonl(DMA_32BIT_MASK);
e67bda55
BG		 838 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
839 mb();
840 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
0da34b6d
BG		 841 mb();
842 src->addr_low = low;
40f6cff5 843 put_be32(low, &dst->addr_low);
0da34b6d
BG		 844 mb();
845}
846
40f6cff5 847static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
0da34b6d
BG		 848{
849 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
850
40f6cff5 851 if ((skb->protocol == htons(ETH_P_8021Q)) &&
0da34b6d
BG		 852 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
853 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
854 skb->csum = hw_csum;
84fa7933 855 skb->ip_summed = CHECKSUM_COMPLETE;
0da34b6d
BG		 856 }
857}
858
dd50f336
BG		 859static inline void
860myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
861 struct skb_frag_struct *rx_frags, int len, int hlen)
862{
863 struct skb_frag_struct *skb_frags;
864
865 skb->len = skb->data_len = len;
866 skb->truesize = len + sizeof(struct sk_buff);
867 /* attach the page(s) */
868
869 skb_frags = skb_shinfo(skb)->frags;
870 while (len > 0) {
871 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
872 len -= rx_frags->size;
873 skb_frags++;
874 rx_frags++;
875 skb_shinfo(skb)->nr_frags++;
876 }
877
878 /* pskb_may_pull is not available in irq context, but
879 * skb_pull() (for ether_pad and eth_type_trans()) requires
880 * the beginning of the packet in skb_headlen(), move it
881 * manually */
27d7ff46 882 skb_copy_to_linear_data(skb, va, hlen);
dd50f336
BG		 883 skb_shinfo(skb)->frags[0].page_offset += hlen;
884 skb_shinfo(skb)->frags[0].size -= hlen;
885 skb->data_len -= hlen;
886 skb->tail += hlen;
887 skb_pull(skb, MXGEFW_PAD);
888}
889
890static void
891myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
892 int bytes, int watchdog)
893{
894 struct page *page;
895 int idx;
896
897 if (unlikely(rx->watchdog_needed && !watchdog))
898 return;
899
900 /* try to refill entire ring */
901 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
902 idx = rx->fill_cnt & rx->mask;
ae8509b1 903 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
dd50f336
BG		 904 /* we can use part of previous page */
905 get_page(rx->page);
906 } else {
907 /* we need a new page */
908 page =
909 alloc_pages(GFP_ATOMIC | __GFP_COMP,
910 MYRI10GE_ALLOC_ORDER);
911 if (unlikely(page == NULL)) {
912 if (rx->fill_cnt - rx->cnt < 16)
913 rx->watchdog_needed = 1;
914 return;
915 }
916 rx->page = page;
917 rx->page_offset = 0;
918 rx->bus = pci_map_page(mgp->pdev, page, 0,
919 MYRI10GE_ALLOC_SIZE,
920 PCI_DMA_FROMDEVICE);
921 }
922 rx->info[idx].page = rx->page;
923 rx->info[idx].page_offset = rx->page_offset;
924 /* note that this is the address of the start of the
925 * page */
926 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
927 rx->shadow[idx].addr_low =
928 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
929 rx->shadow[idx].addr_high =
930 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
931
932 /* start next packet on a cacheline boundary */
933 rx->page_offset += SKB_DATA_ALIGN(bytes);
ae8509b1
BG		 934
935#if MYRI10GE_ALLOC_SIZE > 4096
936 /* don't cross a 4KB boundary */
937 if ((rx->page_offset >> 12) !=
938 ((rx->page_offset + bytes - 1) >> 12))
939 rx->page_offset = (rx->page_offset + 4096) & ~4095;
940#endif
dd50f336
BG		 941 rx->fill_cnt++;
942
943 /* copy 8 descriptors to the firmware at a time */
944 if ((idx & 7) == 7) {
945 if (rx->wc_fifo == NULL)
946 myri10ge_submit_8rx(&rx->lanai[idx - 7],
947 &rx->shadow[idx - 7]);
948 else {
949 mb();
950 myri10ge_pio_copy(rx->wc_fifo,
951 &rx->shadow[idx - 7], 64);
952 }
953 }
954 }
955}
956
957static inline void
958myri10ge_unmap_rx_page(struct pci_dev *pdev,
959 struct myri10ge_rx_buffer_state *info, int bytes)
960{
961 /* unmap the recvd page if we're the only or last user of it */
962 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
963 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
964 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
965 & ~(MYRI10GE_ALLOC_SIZE - 1)),
966 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
967 }
968}
969
970#define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
971 * page into an skb */
972
973static inline int
52ea6fb3
BG		 974myri10ge_rx_done(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
975 int bytes, int len, __wsum csum)
dd50f336
BG		 976{
977 struct sk_buff *skb;
978 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
979 int i, idx, hlen, remainder;
980 struct pci_dev *pdev = mgp->pdev;
981 struct net_device *dev = mgp->dev;
982 u8 *va;
983
984 len += MXGEFW_PAD;
985 idx = rx->cnt & rx->mask;
986 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
987 prefetch(va);
988 /* Fill skb_frag_struct(s) with data from our receive */
989 for (i = 0, remainder = len; remainder > 0; i++) {
990 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
991 rx_frags[i].page = rx->info[idx].page;
992 rx_frags[i].page_offset = rx->info[idx].page_offset;
993 if (remainder < MYRI10GE_ALLOC_SIZE)
994 rx_frags[i].size = remainder;
995 else
996 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
997 rx->cnt++;
998 idx = rx->cnt & rx->mask;
999 remainder -= MYRI10GE_ALLOC_SIZE;
1000 }
1001
1002 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1003
1004 /* allocate an skb to attach the page(s) to. */
1005
1006 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1007 if (unlikely(skb == NULL)) {
1008 mgp->stats.rx_dropped++;
1009 do {
1010 i--;
1011 put_page(rx_frags[i].page);
1012 } while (i != 0);
1013 return 0;
1014 }
1015
1016 /* Attach the pages to the skb, and trim off any padding */
1017 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1018 if (skb_shinfo(skb)->frags[0].size <= 0) {
1019 put_page(skb_shinfo(skb)->frags[0].page);
1020 skb_shinfo(skb)->nr_frags = 0;
1021 }
1022 skb->protocol = eth_type_trans(skb, dev);
dd50f336
BG		 1023
1024 if (mgp->csum_flag) {
1025 if ((skb->protocol == htons(ETH_P_IP)) ||
1026 (skb->protocol == htons(ETH_P_IPV6))) {
1027 skb->csum = csum;
1028 skb->ip_summed = CHECKSUM_COMPLETE;
1029 } else
1030 myri10ge_vlan_ip_csum(skb, csum);
1031 }
1032 netif_receive_skb(skb);
1033 dev->last_rx = jiffies;
1034 return 1;
1035}
1036
0da34b6d
BG		 1037static inline void myri10ge_tx_done(struct myri10ge_priv *mgp, int mcp_index)
1038{
1039 struct pci_dev *pdev = mgp->pdev;
1040 struct myri10ge_tx_buf *tx = &mgp->tx;
1041 struct sk_buff *skb;
1042 int idx, len;
1043 int limit = 0;
1044
1045 while (tx->pkt_done != mcp_index) {
1046 idx = tx->done & tx->mask;
1047 skb = tx->info[idx].skb;
1048
1049 /* Mark as free */
1050 tx->info[idx].skb = NULL;
1051 if (tx->info[idx].last) {
1052 tx->pkt_done++;
1053 tx->info[idx].last = 0;
1054 }
1055 tx->done++;
1056 len = pci_unmap_len(&tx->info[idx], len);
1057 pci_unmap_len_set(&tx->info[idx], len, 0);
1058 if (skb) {
1059 mgp->stats.tx_bytes += skb->len;
1060 mgp->stats.tx_packets++;
1061 dev_kfree_skb_irq(skb);
1062 if (len)
1063 pci_unmap_single(pdev,
1064 pci_unmap_addr(&tx->info[idx],
1065 bus), len,
1066 PCI_DMA_TODEVICE);
1067 } else {
1068 if (len)
1069 pci_unmap_page(pdev,
1070 pci_unmap_addr(&tx->info[idx],
1071 bus), len,
1072 PCI_DMA_TODEVICE);
1073 }
1074
1075 /* limit potential for livelock by only handling
1076 * 2 full tx rings per call */
1077 if (unlikely(++limit > 2 * tx->mask))
1078 break;
1079 }
1080 /* start the queue if we've stopped it */
1081 if (netif_queue_stopped(mgp->dev)
1082 && tx->req - tx->done < (tx->mask >> 1)) {
1083 mgp->wake_queue++;
1084 netif_wake_queue(mgp->dev);
1085 }
1086}
1087
1088static inline void myri10ge_clean_rx_done(struct myri10ge_priv *mgp, int *limit)
1089{
1090 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1091 unsigned long rx_bytes = 0;
1092 unsigned long rx_packets = 0;
1093 unsigned long rx_ok;
1094
1095 int idx = rx_done->idx;
1096 int cnt = rx_done->cnt;
1097 u16 length;
40f6cff5 1098 __wsum checksum;
0da34b6d
BG		 1099
1100 while (rx_done->entry[idx].length != 0 && *limit != 0) {
1101 length = ntohs(rx_done->entry[idx].length);
1102 rx_done->entry[idx].length = 0;
40f6cff5 1103 checksum = csum_unfold(rx_done->entry[idx].checksum);
0da34b6d 1104 if (length <= mgp->small_bytes)
52ea6fb3
BG		 1105 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_small,
1106 mgp->small_bytes,
1107 length, checksum);
0da34b6d 1108 else
52ea6fb3
BG		 1109 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_big,
1110 mgp->big_bytes,
1111 length, checksum);
0da34b6d
BG		 1112 rx_packets += rx_ok;
1113 rx_bytes += rx_ok * (unsigned long)length;
1114 cnt++;
1115 idx = cnt & (myri10ge_max_intr_slots - 1);
1116
1117 /* limit potential for livelock by only handling a
1118 * limited number of frames. */
1119 (*limit)--;
1120 }
1121 rx_done->idx = idx;
1122 rx_done->cnt = cnt;
1123 mgp->stats.rx_packets += rx_packets;
1124 mgp->stats.rx_bytes += rx_bytes;
c7dab99b
BG		 1125
1126 /* restock receive rings if needed */
1127 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt < myri10ge_fill_thresh)
1128 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1129 mgp->small_bytes + MXGEFW_PAD, 0);
1130 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt < myri10ge_fill_thresh)
1131 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1132
0da34b6d
BG		 1133}
1134
1135static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1136{
1137 struct mcp_irq_data *stats = mgp->fw_stats;
1138
1139 if (unlikely(stats->stats_updated)) {
1140 if (mgp->link_state != stats->link_up) {
1141 mgp->link_state = stats->link_up;
1142 if (mgp->link_state) {
c58ac5ca
BG		 1143 if (netif_msg_link(mgp))
1144 printk(KERN_INFO
1145 "myri10ge: %s: link up\n",
1146 mgp->dev->name);
0da34b6d 1147 netif_carrier_on(mgp->dev);
c58ac5ca 1148 mgp->link_changes++;
0da34b6d 1149 } else {
c58ac5ca
BG		 1150 if (netif_msg_link(mgp))
1151 printk(KERN_INFO
1152 "myri10ge: %s: link down\n",
1153 mgp->dev->name);
0da34b6d 1154 netif_carrier_off(mgp->dev);
c58ac5ca 1155 mgp->link_changes++;
0da34b6d
BG		 1156 }
1157 }
1158 if (mgp->rdma_tags_available !=
1159 ntohl(mgp->fw_stats->rdma_tags_available)) {
1160 mgp->rdma_tags_available =
1161 ntohl(mgp->fw_stats->rdma_tags_available);
1162 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1163 "%d tags left\n", mgp->dev->name,
1164 mgp->rdma_tags_available);
1165 }
1166 mgp->down_cnt += stats->link_down;
1167 if (stats->link_down)
1168 wake_up(&mgp->down_wq);
1169 }
1170}
1171
1172static int myri10ge_poll(struct net_device *netdev, int *budget)
1173{
1174 struct myri10ge_priv *mgp = netdev_priv(netdev);
1175 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1176 int limit, orig_limit, work_done;
1177
1178 /* process as many rx events as NAPI will allow */
1179 limit = min(*budget, netdev->quota);
1180 orig_limit = limit;
1181 myri10ge_clean_rx_done(mgp, &limit);
1182 work_done = orig_limit - limit;
1183 *budget -= work_done;
1184 netdev->quota -= work_done;
1185
1186 if (rx_done->entry[rx_done->idx].length == 0 || !netif_running(netdev)) {
1187 netif_rx_complete(netdev);
40f6cff5 1188 put_be32(htonl(3), mgp->irq_claim);
0da34b6d
BG		 1189 return 0;
1190 }
1191 return 1;
1192}
1193
7d12e780 1194static irqreturn_t myri10ge_intr(int irq, void *arg)
0da34b6d
BG		 1195{
1196 struct myri10ge_priv *mgp = arg;
1197 struct mcp_irq_data *stats = mgp->fw_stats;
1198 struct myri10ge_tx_buf *tx = &mgp->tx;
1199 u32 send_done_count;
1200 int i;
1201
1202 /* make sure it is our IRQ, and that the DMA has finished */
1203 if (unlikely(!stats->valid))
1204 return (IRQ_NONE);
1205
1206 /* low bit indicates receives are present, so schedule
1207 * napi poll handler */
1208 if (stats->valid & 1)
1209 netif_rx_schedule(mgp->dev);
1210
1211 if (!mgp->msi_enabled) {
40f6cff5 1212 put_be32(0, mgp->irq_deassert);
0da34b6d
BG		 1213 if (!myri10ge_deassert_wait)
1214 stats->valid = 0;
1215 mb();
1216 } else
1217 stats->valid = 0;
1218
1219 /* Wait for IRQ line to go low, if using INTx */
1220 i = 0;
1221 while (1) {
1222 i++;
1223 /* check for transmit completes and receives */
1224 send_done_count = ntohl(stats->send_done_count);
1225 if (send_done_count != tx->pkt_done)
1226 myri10ge_tx_done(mgp, (int)send_done_count);
1227 if (unlikely(i > myri10ge_max_irq_loops)) {
1228 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1229 mgp->dev->name);
1230 stats->valid = 0;
1231 schedule_work(&mgp->watchdog_work);
1232 }
1233 if (likely(stats->valid == 0))
1234 break;
1235 cpu_relax();
1236 barrier();
1237 }
1238
1239 myri10ge_check_statblock(mgp);
1240
40f6cff5 1241 put_be32(htonl(3), mgp->irq_claim + 1);
0da34b6d
BG		 1242 return (IRQ_HANDLED);
1243}
1244
1245static int
1246myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1247{
1248 cmd->autoneg = AUTONEG_DISABLE;
1249 cmd->speed = SPEED_10000;
1250 cmd->duplex = DUPLEX_FULL;
1251 return 0;
1252}
1253
1254static void
1255myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1256{
1257 struct myri10ge_priv *mgp = netdev_priv(netdev);
1258
1259 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1260 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1261 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1262 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1263}
1264
1265static int
1266myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1267{
1268 struct myri10ge_priv *mgp = netdev_priv(netdev);
1269 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1270 return 0;
1271}
1272
1273static int
1274myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1275{
1276 struct myri10ge_priv *mgp = netdev_priv(netdev);
1277
1278 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
40f6cff5 1279 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 1280 return 0;
1281}
1282
1283static void
1284myri10ge_get_pauseparam(struct net_device *netdev,
1285 struct ethtool_pauseparam *pause)
1286{
1287 struct myri10ge_priv *mgp = netdev_priv(netdev);
1288
1289 pause->autoneg = 0;
1290 pause->rx_pause = mgp->pause;
1291 pause->tx_pause = mgp->pause;
1292}
1293
1294static int
1295myri10ge_set_pauseparam(struct net_device *netdev,
1296 struct ethtool_pauseparam *pause)
1297{
1298 struct myri10ge_priv *mgp = netdev_priv(netdev);
1299
1300 if (pause->tx_pause != mgp->pause)
1301 return myri10ge_change_pause(mgp, pause->tx_pause);
1302 if (pause->rx_pause != mgp->pause)
1303 return myri10ge_change_pause(mgp, pause->tx_pause);
1304 if (pause->autoneg != 0)
1305 return -EINVAL;
1306 return 0;
1307}
1308
1309static void
1310myri10ge_get_ringparam(struct net_device *netdev,
1311 struct ethtool_ringparam *ring)
1312{
1313 struct myri10ge_priv *mgp = netdev_priv(netdev);
1314
1315 ring->rx_mini_max_pending = mgp->rx_small.mask + 1;
1316 ring->rx_max_pending = mgp->rx_big.mask + 1;
1317 ring->rx_jumbo_max_pending = 0;
1318 ring->tx_max_pending = mgp->rx_small.mask + 1;
1319 ring->rx_mini_pending = ring->rx_mini_max_pending;
1320 ring->rx_pending = ring->rx_max_pending;
1321 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1322 ring->tx_pending = ring->tx_max_pending;
1323}
1324
1325static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1326{
1327 struct myri10ge_priv *mgp = netdev_priv(netdev);
1328 if (mgp->csum_flag)
1329 return 1;
1330 else
1331 return 0;
1332}
1333
1334static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1335{
1336 struct myri10ge_priv *mgp = netdev_priv(netdev);
1337 if (csum_enabled)
1338 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1339 else
1340 mgp->csum_flag = 0;
1341 return 0;
1342}
1343
1344static const char myri10ge_gstrings_stats[][ETH_GSTRING_LEN] = {
1345 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1346 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1347 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1348 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1349 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1350 "tx_heartbeat_errors", "tx_window_errors",
1351 /* device-specific stats */
2c1a1088 1352 "tx_boundary", "WC", "irq", "MSI",
0da34b6d
BG		 1353 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1354 "serial_number", "tx_pkt_start", "tx_pkt_done",
1355 "tx_req", "tx_done", "rx_small_cnt", "rx_big_cnt",
1356 "wake_queue", "stop_queue", "watchdog_resets", "tx_linearized",
c58ac5ca 1357 "link_changes", "link_up", "dropped_link_overflow",
cee505db
BG		 1358 "dropped_link_error_or_filtered",
1359 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1360 "dropped_unicast_filtered", "dropped_multicast_filtered",
0da34b6d
BG		 1361 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1362 "dropped_no_big_buffer"
1363};
1364
1365#define MYRI10GE_NET_STATS_LEN 21
1366#define MYRI10GE_STATS_LEN sizeof(myri10ge_gstrings_stats) / ETH_GSTRING_LEN
1367
1368static void
1369myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1370{
1371 switch (stringset) {
1372 case ETH_SS_STATS:
1373 memcpy(data, *myri10ge_gstrings_stats,
1374 sizeof(myri10ge_gstrings_stats));
1375 break;
1376 }
1377}
1378
1379static int myri10ge_get_stats_count(struct net_device *netdev)
1380{
1381 return MYRI10GE_STATS_LEN;
1382}
1383
1384static void
1385myri10ge_get_ethtool_stats(struct net_device *netdev,
1386 struct ethtool_stats *stats, u64 * data)
1387{
1388 struct myri10ge_priv *mgp = netdev_priv(netdev);
1389 int i;
1390
1391 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1392 data[i] = ((unsigned long *)&mgp->stats)[i];
1393
2c1a1088 1394 data[i++] = (unsigned int)mgp->tx.boundary;
276e26c3 1395 data[i++] = (unsigned int)mgp->wc_enabled;
2c1a1088
BG		 1396 data[i++] = (unsigned int)mgp->pdev->irq;
1397 data[i++] = (unsigned int)mgp->msi_enabled;
0da34b6d
BG		 1398 data[i++] = (unsigned int)mgp->read_dma;
1399 data[i++] = (unsigned int)mgp->write_dma;
1400 data[i++] = (unsigned int)mgp->read_write_dma;
1401 data[i++] = (unsigned int)mgp->serial_number;
1402 data[i++] = (unsigned int)mgp->tx.pkt_start;
1403 data[i++] = (unsigned int)mgp->tx.pkt_done;
1404 data[i++] = (unsigned int)mgp->tx.req;
1405 data[i++] = (unsigned int)mgp->tx.done;
1406 data[i++] = (unsigned int)mgp->rx_small.cnt;
1407 data[i++] = (unsigned int)mgp->rx_big.cnt;
1408 data[i++] = (unsigned int)mgp->wake_queue;
1409 data[i++] = (unsigned int)mgp->stop_queue;
1410 data[i++] = (unsigned int)mgp->watchdog_resets;
1411 data[i++] = (unsigned int)mgp->tx_linearized;
c58ac5ca 1412 data[i++] = (unsigned int)mgp->link_changes;
0da34b6d
BG		 1413 data[i++] = (unsigned int)ntohl(mgp->fw_stats->link_up);
1414 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_link_overflow);
1415 data[i++] =
1416 (unsigned int)ntohl(mgp->fw_stats->dropped_link_error_or_filtered);
cee505db
BG		 1417 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_pause);
1418 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_bad_phy);
1419 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_bad_crc32);
1420 data[i++] =
1421 (unsigned int)ntohl(mgp->fw_stats->dropped_unicast_filtered);
85a7ea1b
BG		 1422 data[i++] =
1423 (unsigned int)ntohl(mgp->fw_stats->dropped_multicast_filtered);
0da34b6d
BG		 1424 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_runt);
1425 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_overrun);
1426 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_small_buffer);
1427 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_big_buffer);
1428}
1429
c58ac5ca
BG		 1430static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1431{
1432 struct myri10ge_priv *mgp = netdev_priv(netdev);
1433 mgp->msg_enable = value;
1434}
1435
1436static u32 myri10ge_get_msglevel(struct net_device *netdev)
1437{
1438 struct myri10ge_priv *mgp = netdev_priv(netdev);
1439 return mgp->msg_enable;
1440}
1441
7282d491 1442static const struct ethtool_ops myri10ge_ethtool_ops = {
0da34b6d
BG		 1443 .get_settings = myri10ge_get_settings,
1444 .get_drvinfo = myri10ge_get_drvinfo,
1445 .get_coalesce = myri10ge_get_coalesce,
1446 .set_coalesce = myri10ge_set_coalesce,
1447 .get_pauseparam = myri10ge_get_pauseparam,
1448 .set_pauseparam = myri10ge_set_pauseparam,
1449 .get_ringparam = myri10ge_get_ringparam,
1450 .get_rx_csum = myri10ge_get_rx_csum,
1451 .set_rx_csum = myri10ge_set_rx_csum,
1452 .get_tx_csum = ethtool_op_get_tx_csum,
b10c0668 1453 .set_tx_csum = ethtool_op_set_tx_hw_csum,
0da34b6d
BG		 1454 .get_sg = ethtool_op_get_sg,
1455 .set_sg = ethtool_op_set_sg,
0da34b6d
BG		 1456 .get_tso = ethtool_op_get_tso,
1457 .set_tso = ethtool_op_set_tso,
0da34b6d
BG		 1458 .get_strings = myri10ge_get_strings,
1459 .get_stats_count = myri10ge_get_stats_count,
c58ac5ca
BG		 1460 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1461 .set_msglevel = myri10ge_set_msglevel,
1462 .get_msglevel = myri10ge_get_msglevel
0da34b6d
BG		 1463};
1464
1465static int myri10ge_allocate_rings(struct net_device *dev)
1466{
1467 struct myri10ge_priv *mgp;
1468 struct myri10ge_cmd cmd;
1469 int tx_ring_size, rx_ring_size;
1470 int tx_ring_entries, rx_ring_entries;
1471 int i, status;
1472 size_t bytes;
1473
1474 mgp = netdev_priv(dev);
1475
1476 /* get ring sizes */
1477
1478 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1479 tx_ring_size = cmd.data0;
1480 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
355c7265
BG		 1481 if (status != 0)
1482 return status;
0da34b6d
BG		 1483 rx_ring_size = cmd.data0;
1484
1485 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1486 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1487 mgp->tx.mask = tx_ring_entries - 1;
1488 mgp->rx_small.mask = mgp->rx_big.mask = rx_ring_entries - 1;
1489
355c7265
BG		 1490 status = -ENOMEM;
1491
0da34b6d
BG		 1492 /* allocate the host shadow rings */
1493
1494 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1495 * sizeof(*mgp->tx.req_list);
1496 mgp->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1497 if (mgp->tx.req_bytes == NULL)
1498 goto abort_with_nothing;
1499
1500 /* ensure req_list entries are aligned to 8 bytes */
1501 mgp->tx.req_list = (struct mcp_kreq_ether_send *)
1502 ALIGN((unsigned long)mgp->tx.req_bytes, 8);
1503
1504 bytes = rx_ring_entries * sizeof(*mgp->rx_small.shadow);
1505 mgp->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1506 if (mgp->rx_small.shadow == NULL)
1507 goto abort_with_tx_req_bytes;
1508
1509 bytes = rx_ring_entries * sizeof(*mgp->rx_big.shadow);
1510 mgp->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1511 if (mgp->rx_big.shadow == NULL)
1512 goto abort_with_rx_small_shadow;
1513
1514 /* allocate the host info rings */
1515
1516 bytes = tx_ring_entries * sizeof(*mgp->tx.info);
1517 mgp->tx.info = kzalloc(bytes, GFP_KERNEL);
1518 if (mgp->tx.info == NULL)
1519 goto abort_with_rx_big_shadow;
1520
1521 bytes = rx_ring_entries * sizeof(*mgp->rx_small.info);
1522 mgp->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1523 if (mgp->rx_small.info == NULL)
1524 goto abort_with_tx_info;
1525
1526 bytes = rx_ring_entries * sizeof(*mgp->rx_big.info);
1527 mgp->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1528 if (mgp->rx_big.info == NULL)
1529 goto abort_with_rx_small_info;
1530
1531 /* Fill the receive rings */
c7dab99b
BG		 1532 mgp->rx_big.cnt = 0;
1533 mgp->rx_small.cnt = 0;
1534 mgp->rx_big.fill_cnt = 0;
1535 mgp->rx_small.fill_cnt = 0;
1536 mgp->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1537 mgp->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1538 mgp->rx_small.watchdog_needed = 0;
1539 mgp->rx_big.watchdog_needed = 0;
1540 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1541 mgp->small_bytes + MXGEFW_PAD, 0);
0da34b6d 1542
c7dab99b
BG		 1543 if (mgp->rx_small.fill_cnt < mgp->rx_small.mask + 1) {
1544 printk(KERN_ERR "myri10ge: %s: alloced only %d small bufs\n",
1545 dev->name, mgp->rx_small.fill_cnt);
1546 goto abort_with_rx_small_ring;
0da34b6d
BG		 1547 }
1548
c7dab99b
BG		 1549 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1550 if (mgp->rx_big.fill_cnt < mgp->rx_big.mask + 1) {
1551 printk(KERN_ERR "myri10ge: %s: alloced only %d big bufs\n",
1552 dev->name, mgp->rx_big.fill_cnt);
1553 goto abort_with_rx_big_ring;
0da34b6d
BG		 1554 }
1555
1556 return 0;
1557
1558abort_with_rx_big_ring:
c7dab99b
BG		 1559 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1560 int idx = i & mgp->rx_big.mask;
1561 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1562 mgp->big_bytes);
1563 put_page(mgp->rx_big.info[idx].page);
0da34b6d
BG		 1564 }
1565
1566abort_with_rx_small_ring:
c7dab99b
BG		 1567 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1568 int idx = i & mgp->rx_small.mask;
1569 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1570 mgp->small_bytes + MXGEFW_PAD);
1571 put_page(mgp->rx_small.info[idx].page);
0da34b6d 1572 }
c7dab99b 1573
0da34b6d
BG		 1574 kfree(mgp->rx_big.info);
1575
1576abort_with_rx_small_info:
1577 kfree(mgp->rx_small.info);
1578
1579abort_with_tx_info:
1580 kfree(mgp->tx.info);
1581
1582abort_with_rx_big_shadow:
1583 kfree(mgp->rx_big.shadow);
1584
1585abort_with_rx_small_shadow:
1586 kfree(mgp->rx_small.shadow);
1587
1588abort_with_tx_req_bytes:
1589 kfree(mgp->tx.req_bytes);
1590 mgp->tx.req_bytes = NULL;
1591 mgp->tx.req_list = NULL;
1592
1593abort_with_nothing:
1594 return status;
1595}
1596
1597static void myri10ge_free_rings(struct net_device *dev)
1598{
1599 struct myri10ge_priv *mgp;
1600 struct sk_buff *skb;
1601 struct myri10ge_tx_buf *tx;
1602 int i, len, idx;
1603
1604 mgp = netdev_priv(dev);
1605
c7dab99b
BG		 1606 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1607 idx = i & mgp->rx_big.mask;
1608 if (i == mgp->rx_big.fill_cnt - 1)
1609 mgp->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
1610 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1611 mgp->big_bytes);
1612 put_page(mgp->rx_big.info[idx].page);
0da34b6d
BG		 1613 }
1614
c7dab99b
BG		 1615 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1616 idx = i & mgp->rx_small.mask;
1617 if (i == mgp->rx_small.fill_cnt - 1)
1618 mgp->rx_small.info[idx].page_offset =
1619 MYRI10GE_ALLOC_SIZE;
1620 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1621 mgp->small_bytes + MXGEFW_PAD);
1622 put_page(mgp->rx_small.info[idx].page);
1623 }
0da34b6d
BG		 1624 tx = &mgp->tx;
1625 while (tx->done != tx->req) {
1626 idx = tx->done & tx->mask;
1627 skb = tx->info[idx].skb;
1628
1629 /* Mark as free */
1630 tx->info[idx].skb = NULL;
1631 tx->done++;
1632 len = pci_unmap_len(&tx->info[idx], len);
1633 pci_unmap_len_set(&tx->info[idx], len, 0);
1634 if (skb) {
1635 mgp->stats.tx_dropped++;
1636 dev_kfree_skb_any(skb);
1637 if (len)
1638 pci_unmap_single(mgp->pdev,
1639 pci_unmap_addr(&tx->info[idx],
1640 bus), len,
1641 PCI_DMA_TODEVICE);
1642 } else {
1643 if (len)
1644 pci_unmap_page(mgp->pdev,
1645 pci_unmap_addr(&tx->info[idx],
1646 bus), len,
1647 PCI_DMA_TODEVICE);
1648 }
1649 }
1650 kfree(mgp->rx_big.info);
1651
1652 kfree(mgp->rx_small.info);
1653
1654 kfree(mgp->tx.info);
1655
1656 kfree(mgp->rx_big.shadow);
1657
1658 kfree(mgp->rx_small.shadow);
1659
1660 kfree(mgp->tx.req_bytes);
1661 mgp->tx.req_bytes = NULL;
1662 mgp->tx.req_list = NULL;
1663}
1664
df30a740
BG		 1665static int myri10ge_request_irq(struct myri10ge_priv *mgp)
1666{
1667 struct pci_dev *pdev = mgp->pdev;
1668 int status;
1669
1670 if (myri10ge_msi) {
1671 status = pci_enable_msi(pdev);
1672 if (status != 0)
1673 dev_err(&pdev->dev,
1674 "Error %d setting up MSI; falling back to xPIC\n",
1675 status);
1676 else
1677 mgp->msi_enabled = 1;
1678 } else {
1679 mgp->msi_enabled = 0;
1680 }
1681 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
1682 mgp->dev->name, mgp);
1683 if (status != 0) {
1684 dev_err(&pdev->dev, "failed to allocate IRQ\n");
1685 if (mgp->msi_enabled)
1686 pci_disable_msi(pdev);
1687 }
1688 return status;
1689}
1690
1691static void myri10ge_free_irq(struct myri10ge_priv *mgp)
1692{
1693 struct pci_dev *pdev = mgp->pdev;
1694
1695 free_irq(pdev->irq, mgp);
1696 if (mgp->msi_enabled)
1697 pci_disable_msi(pdev);
1698}
1699
0da34b6d
BG		 1700static int myri10ge_open(struct net_device *dev)
1701{
1702 struct myri10ge_priv *mgp;
1703 struct myri10ge_cmd cmd;
1704 int status, big_pow2;
1705
1706 mgp = netdev_priv(dev);
1707
1708 if (mgp->running != MYRI10GE_ETH_STOPPED)
1709 return -EBUSY;
1710
1711 mgp->running = MYRI10GE_ETH_STARTING;
1712 status = myri10ge_reset(mgp);
1713 if (status != 0) {
1714 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
df30a740 1715 goto abort_with_nothing;
0da34b6d
BG		 1716 }
1717
df30a740
BG		 1718 status = myri10ge_request_irq(mgp);
1719 if (status != 0)
1720 goto abort_with_nothing;
1721
0da34b6d
BG		 1722 /* decide what small buffer size to use. For good TCP rx
1723 * performance, it is important to not receive 1514 byte
1724 * frames into jumbo buffers, as it confuses the socket buffer
1725 * accounting code, leading to drops and erratic performance.
1726 */
1727
1728 if (dev->mtu <= ETH_DATA_LEN)
c7dab99b
BG		 1729 /* enough for a TCP header */
1730 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
1731 ? (128 - MXGEFW_PAD)
1732 : (SMP_CACHE_BYTES - MXGEFW_PAD);
0da34b6d 1733 else
de3c4507
BG		 1734 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
1735 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
0da34b6d
BG		 1736
1737 /* Override the small buffer size? */
1738 if (myri10ge_small_bytes > 0)
1739 mgp->small_bytes = myri10ge_small_bytes;
1740
0da34b6d
BG		 1741 /* get the lanai pointers to the send and receive rings */
1742
1743 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
1744 mgp->tx.lanai =
1745 (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0);
1746
1747 status |=
1748 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0);
1749 mgp->rx_small.lanai =
1750 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1751
1752 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
1753 mgp->rx_big.lanai =
1754 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1755
1756 if (status != 0) {
1757 printk(KERN_ERR
1758 "myri10ge: %s: failed to get ring sizes or locations\n",
1759 dev->name);
1760 mgp->running = MYRI10GE_ETH_STOPPED;
df30a740 1761 goto abort_with_irq;
0da34b6d
BG		 1762 }
1763
276e26c3 1764 if (myri10ge_wcfifo && mgp->wc_enabled) {
e700f9f4
BG		 1765 mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4;
1766 mgp->rx_small.wc_fifo =
1767 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL;
1768 mgp->rx_big.wc_fifo =
1769 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG;
0da34b6d
BG		 1770 } else {
1771 mgp->tx.wc_fifo = NULL;
1772 mgp->rx_small.wc_fifo = NULL;
1773 mgp->rx_big.wc_fifo = NULL;
1774 }
1775
0da34b6d
BG		 1776 /* Firmware needs the big buff size as a power of 2. Lie and
1777 * tell him the buffer is larger, because we only use 1
1778 * buffer/pkt, and the mtu will prevent overruns.
1779 */
13348bee 1780 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 1781 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
1782 while ((big_pow2 & (big_pow2 - 1)) != 0)
1783 big_pow2++;
13348bee 1784 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 1785 } else {
1786 big_pow2 = MYRI10GE_ALLOC_SIZE;
1787 mgp->big_bytes = big_pow2;
1788 }
1789
1790 status = myri10ge_allocate_rings(dev);
1791 if (status != 0)
df30a740 1792 goto abort_with_irq;
0da34b6d
BG		 1793
1794 /* now give firmware buffers sizes, and MTU */
1795 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
1796 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
1797 cmd.data0 = mgp->small_bytes;
1798 status |=
1799 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
1800 cmd.data0 = big_pow2;
1801 status |=
1802 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
1803 if (status) {
1804 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
1805 dev->name);
1806 goto abort_with_rings;
1807 }
1808
1809 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->fw_stats_bus);
1810 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->fw_stats_bus);
85a7ea1b
BG		 1811 cmd.data2 = sizeof(struct mcp_irq_data);
1812 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
1813 if (status == -ENOSYS) {
1814 dma_addr_t bus = mgp->fw_stats_bus;
1815 bus += offsetof(struct mcp_irq_data, send_done_count);
1816 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
1817 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
1818 status = myri10ge_send_cmd(mgp,
1819 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
1820 &cmd, 0);
1821 /* Firmware cannot support multicast without STATS_DMA_V2 */
1822 mgp->fw_multicast_support = 0;
1823 } else {
1824 mgp->fw_multicast_support = 1;
1825 }
0da34b6d
BG		 1826 if (status) {
1827 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n",
1828 dev->name);
1829 goto abort_with_rings;
1830 }
1831
40f6cff5 1832 mgp->link_state = htonl(~0U);
0da34b6d
BG		 1833 mgp->rdma_tags_available = 15;
1834
1835 netif_poll_enable(mgp->dev); /* must happen prior to any irq */
1836
1837 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
1838 if (status) {
1839 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
1840 dev->name);
1841 goto abort_with_rings;
1842 }
1843
1844 mgp->wake_queue = 0;
1845 mgp->stop_queue = 0;
1846 mgp->running = MYRI10GE_ETH_RUNNING;
1847 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
1848 add_timer(&mgp->watchdog_timer);
1849 netif_wake_queue(dev);
1850 return 0;
1851
1852abort_with_rings:
1853 myri10ge_free_rings(dev);
1854
df30a740
BG		 1855abort_with_irq:
1856 myri10ge_free_irq(mgp);
1857
0da34b6d
BG		 1858abort_with_nothing:
1859 mgp->running = MYRI10GE_ETH_STOPPED;
1860 return -ENOMEM;
1861}
1862
1863static int myri10ge_close(struct net_device *dev)
1864{
1865 struct myri10ge_priv *mgp;
1866 struct myri10ge_cmd cmd;
1867 int status, old_down_cnt;
1868
1869 mgp = netdev_priv(dev);
1870
1871 if (mgp->running != MYRI10GE_ETH_RUNNING)
1872 return 0;
1873
1874 if (mgp->tx.req_bytes == NULL)
1875 return 0;
1876
1877 del_timer_sync(&mgp->watchdog_timer);
1878 mgp->running = MYRI10GE_ETH_STOPPING;
1879 netif_poll_disable(mgp->dev);
1880 netif_carrier_off(dev);
1881 netif_stop_queue(dev);
1882 old_down_cnt = mgp->down_cnt;
1883 mb();
1884 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
1885 if (status)
1886 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
1887 dev->name);
1888
1889 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
1890 if (old_down_cnt == mgp->down_cnt)
1891 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
1892
1893 netif_tx_disable(dev);
df30a740 1894 myri10ge_free_irq(mgp);
0da34b6d
BG		 1895 myri10ge_free_rings(dev);
1896
1897 mgp->running = MYRI10GE_ETH_STOPPED;
1898 return 0;
1899}
1900
1901/* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1902 * backwards one at a time and handle ring wraps */
1903
1904static inline void
1905myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
1906 struct mcp_kreq_ether_send *src, int cnt)
1907{
1908 int idx, starting_slot;
1909 starting_slot = tx->req;
1910 while (cnt > 1) {
1911 cnt--;
1912 idx = (starting_slot + cnt) & tx->mask;
1913 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
1914 mb();
1915 }
1916}
1917
1918/*
1919 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1920 * at most 32 bytes at a time, so as to avoid involving the software
1921 * pio handler in the nic. We re-write the first segment's flags
1922 * to mark them valid only after writing the entire chain.
1923 */
1924
1925static inline void
1926myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
1927 int cnt)
1928{
1929 int idx, i;
1930 struct mcp_kreq_ether_send __iomem *dstp, *dst;
1931 struct mcp_kreq_ether_send *srcp;
1932 u8 last_flags;
1933
1934 idx = tx->req & tx->mask;
1935
1936 last_flags = src->flags;
1937 src->flags = 0;
1938 mb();
1939 dst = dstp = &tx->lanai[idx];
1940 srcp = src;
1941
1942 if ((idx + cnt) < tx->mask) {
1943 for (i = 0; i < (cnt - 1); i += 2) {
1944 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
1945 mb(); /* force write every 32 bytes */
1946 srcp += 2;
1947 dstp += 2;
1948 }
1949 } else {
1950 /* submit all but the first request, and ensure
1951 * that it is submitted below */
1952 myri10ge_submit_req_backwards(tx, src, cnt);
1953 i = 0;
1954 }
1955 if (i < cnt) {
1956 /* submit the first request */
1957 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
1958 mb(); /* barrier before setting valid flag */
1959 }
1960
1961 /* re-write the last 32-bits with the valid flags */
1962 src->flags = last_flags;
40f6cff5 1963 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
0da34b6d
BG		 1964 tx->req += cnt;
1965 mb();
1966}
1967
1968static inline void
1969myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
1970 struct mcp_kreq_ether_send *src, int cnt)
1971{
1972 tx->req += cnt;
1973 mb();
1974 while (cnt >= 4) {
1975 myri10ge_pio_copy(tx->wc_fifo, src, 64);
1976 mb();
1977 src += 4;
1978 cnt -= 4;
1979 }
1980 if (cnt > 0) {
1981 /* pad it to 64 bytes. The src is 64 bytes bigger than it
1982 * needs to be so that we don't overrun it */
e700f9f4
BG		 1983 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
1984 src, 64);
0da34b6d
BG		 1985 mb();
1986 }
1987}
1988
1989/*
1990 * Transmit a packet. We need to split the packet so that a single
1991 * segment does not cross myri10ge->tx.boundary, so this makes segment
1992 * counting tricky. So rather than try to count segments up front, we
1993 * just give up if there are too few segments to hold a reasonably
1994 * fragmented packet currently available. If we run
1995 * out of segments while preparing a packet for DMA, we just linearize
1996 * it and try again.
1997 */
1998
1999static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
2000{
2001 struct myri10ge_priv *mgp = netdev_priv(dev);
2002 struct mcp_kreq_ether_send *req;
2003 struct myri10ge_tx_buf *tx = &mgp->tx;
2004 struct skb_frag_struct *frag;
2005 dma_addr_t bus;
40f6cff5
AV		 2006 u32 low;
2007 __be32 high_swapped;
0da34b6d
BG		 2008 unsigned int len;
2009 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2010 u16 pseudo_hdr_offset, cksum_offset;
2011 int cum_len, seglen, boundary, rdma_count;
2012 u8 flags, odd_flag;
2013
2014again:
2015 req = tx->req_list;
2016 avail = tx->mask - 1 - (tx->req - tx->done);
2017
2018 mss = 0;
2019 max_segments = MXGEFW_MAX_SEND_DESC;
2020
917690cd 2021 if (skb_is_gso(skb)) {
7967168c 2022 mss = skb_shinfo(skb)->gso_size;
917690cd 2023 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
0da34b6d 2024 }
0da34b6d
BG		 2025
2026 if ((unlikely(avail < max_segments))) {
2027 /* we are out of transmit resources */
2028 mgp->stop_queue++;
2029 netif_stop_queue(dev);
2030 return 1;
2031 }
2032
2033 /* Setup checksum offloading, if needed */
2034 cksum_offset = 0;
2035 pseudo_hdr_offset = 0;
2036 odd_flag = 0;
2037 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
84fa7933 2038 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
ea2ae17d 2039 cksum_offset = skb_transport_offset(skb);
ff1dcadb 2040 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
0da34b6d
BG		 2041 /* If the headers are excessively large, then we must
2042 * fall back to a software checksum */
2043 if (unlikely(cksum_offset > 255 || pseudo_hdr_offset > 127)) {
84fa7933 2044 if (skb_checksum_help(skb))
0da34b6d
BG		 2045 goto drop;
2046 cksum_offset = 0;
2047 pseudo_hdr_offset = 0;
2048 } else {
0da34b6d
BG		 2049 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2050 flags |= MXGEFW_FLAGS_CKSUM;
2051 }
2052 }
2053
2054 cum_len = 0;
2055
0da34b6d
BG		 2056 if (mss) { /* TSO */
2057 /* this removes any CKSUM flag from before */
2058 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2059
2060 /* negative cum_len signifies to the
2061 * send loop that we are still in the
2062 * header portion of the TSO packet.
2063 * TSO header must be at most 134 bytes long */
ab6a5bb6 2064 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
0da34b6d
BG		 2065
2066 /* for TSO, pseudo_hdr_offset holds mss.
2067 * The firmware figures out where to put
2068 * the checksum by parsing the header. */
40f6cff5 2069 pseudo_hdr_offset = mss;
0da34b6d 2070 } else
0da34b6d
BG		 2071 /* Mark small packets, and pad out tiny packets */
2072 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2073 flags |= MXGEFW_FLAGS_SMALL;
2074
2075 /* pad frames to at least ETH_ZLEN bytes */
2076 if (unlikely(skb->len < ETH_ZLEN)) {
5b057c6b 2077 if (skb_padto(skb, ETH_ZLEN)) {
0da34b6d
BG		 2078 /* The packet is gone, so we must
2079 * return 0 */
2080 mgp->stats.tx_dropped += 1;
2081 return 0;
2082 }
2083 /* adjust the len to account for the zero pad
2084 * so that the nic can know how long it is */
2085 skb->len = ETH_ZLEN;
2086 }
2087 }
2088
2089 /* map the skb for DMA */
2090 len = skb->len - skb->data_len;
2091 idx = tx->req & tx->mask;
2092 tx->info[idx].skb = skb;
2093 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2094 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2095 pci_unmap_len_set(&tx->info[idx], len, len);
2096
2097 frag_cnt = skb_shinfo(skb)->nr_frags;
2098 frag_idx = 0;
2099 count = 0;
2100 rdma_count = 0;
2101
2102 /* "rdma_count" is the number of RDMAs belonging to the
2103 * current packet BEFORE the current send request. For
2104 * non-TSO packets, this is equal to "count".
2105 * For TSO packets, rdma_count needs to be reset
2106 * to 0 after a segment cut.
2107 *
2108 * The rdma_count field of the send request is
2109 * the number of RDMAs of the packet starting at
2110 * that request. For TSO send requests with one ore more cuts
2111 * in the middle, this is the number of RDMAs starting
2112 * after the last cut in the request. All previous
2113 * segments before the last cut implicitly have 1 RDMA.
2114 *
2115 * Since the number of RDMAs is not known beforehand,
2116 * it must be filled-in retroactively - after each
2117 * segmentation cut or at the end of the entire packet.
2118 */
2119
2120 while (1) {
2121 /* Break the SKB or Fragment up into pieces which
2122 * do not cross mgp->tx.boundary */
2123 low = MYRI10GE_LOWPART_TO_U32(bus);
2124 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2125 while (len) {
2126 u8 flags_next;
2127 int cum_len_next;
2128
2129 if (unlikely(count == max_segments))
2130 goto abort_linearize;
2131
2132 boundary = (low + tx->boundary) & ~(tx->boundary - 1);
2133 seglen = boundary - low;
2134 if (seglen > len)
2135 seglen = len;
2136 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2137 cum_len_next = cum_len + seglen;
0da34b6d
BG		 2138 if (mss) { /* TSO */
2139 (req - rdma_count)->rdma_count = rdma_count + 1;
2140
2141 if (likely(cum_len >= 0)) { /* payload */
2142 int next_is_first, chop;
2143
2144 chop = (cum_len_next > mss);
2145 cum_len_next = cum_len_next % mss;
2146 next_is_first = (cum_len_next == 0);
2147 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2148 flags_next |= next_is_first *
2149 MXGEFW_FLAGS_FIRST;
2150 rdma_count |= -(chop | next_is_first);
2151 rdma_count += chop & !next_is_first;
2152 } else if (likely(cum_len_next >= 0)) { /* header ends */
2153 int small;
2154
2155 rdma_count = -1;
2156 cum_len_next = 0;
2157 seglen = -cum_len;
2158 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2159 flags_next = MXGEFW_FLAGS_TSO_PLD |
2160 MXGEFW_FLAGS_FIRST |
2161 (small * MXGEFW_FLAGS_SMALL);
2162 }
2163 }
0da34b6d
BG		 2164 req->addr_high = high_swapped;
2165 req->addr_low = htonl(low);
40f6cff5 2166 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
0da34b6d
BG		 2167 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2168 req->rdma_count = 1;
2169 req->length = htons(seglen);
2170 req->cksum_offset = cksum_offset;
2171 req->flags = flags | ((cum_len & 1) * odd_flag);
2172
2173 low += seglen;
2174 len -= seglen;
2175 cum_len = cum_len_next;
2176 flags = flags_next;
2177 req++;
2178 count++;
2179 rdma_count++;
2180 if (unlikely(cksum_offset > seglen))
2181 cksum_offset -= seglen;
2182 else
2183 cksum_offset = 0;
2184 }
2185 if (frag_idx == frag_cnt)
2186 break;
2187
2188 /* map next fragment for DMA */
2189 idx = (count + tx->req) & tx->mask;
2190 frag = &skb_shinfo(skb)->frags[frag_idx];
2191 frag_idx++;
2192 len = frag->size;
2193 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2194 len, PCI_DMA_TODEVICE);
2195 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2196 pci_unmap_len_set(&tx->info[idx], len, len);
2197 }
2198
2199 (req - rdma_count)->rdma_count = rdma_count;
0da34b6d
BG		 2200 if (mss)
2201 do {
2202 req--;
2203 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2204 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2205 MXGEFW_FLAGS_FIRST)));
0da34b6d
BG		 2206 idx = ((count - 1) + tx->req) & tx->mask;
2207 tx->info[idx].last = 1;
2208 if (tx->wc_fifo == NULL)
2209 myri10ge_submit_req(tx, tx->req_list, count);
2210 else
2211 myri10ge_submit_req_wc(tx, tx->req_list, count);
2212 tx->pkt_start++;
2213 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2214 mgp->stop_queue++;
2215 netif_stop_queue(dev);
2216 }
2217 dev->trans_start = jiffies;
2218 return 0;
2219
2220abort_linearize:
2221 /* Free any DMA resources we've alloced and clear out the skb
2222 * slot so as to not trip up assertions, and to avoid a
2223 * double-free if linearizing fails */
2224
2225 last_idx = (idx + 1) & tx->mask;
2226 idx = tx->req & tx->mask;
2227 tx->info[idx].skb = NULL;
2228 do {
2229 len = pci_unmap_len(&tx->info[idx], len);
2230 if (len) {
2231 if (tx->info[idx].skb != NULL)
2232 pci_unmap_single(mgp->pdev,
2233 pci_unmap_addr(&tx->info[idx],
2234 bus), len,
2235 PCI_DMA_TODEVICE);
2236 else
2237 pci_unmap_page(mgp->pdev,
2238 pci_unmap_addr(&tx->info[idx],
2239 bus), len,
2240 PCI_DMA_TODEVICE);
2241 pci_unmap_len_set(&tx->info[idx], len, 0);
2242 tx->info[idx].skb = NULL;
2243 }
2244 idx = (idx + 1) & tx->mask;
2245 } while (idx != last_idx);
89114afd 2246 if (skb_is_gso(skb)) {
0da34b6d
BG		 2247 printk(KERN_ERR
2248 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2249 mgp->dev->name);
2250 goto drop;
2251 }
2252
bec0e859 2253 if (skb_linearize(skb))
0da34b6d
BG		 2254 goto drop;
2255
2256 mgp->tx_linearized++;
2257 goto again;
2258
2259drop:
2260 dev_kfree_skb_any(skb);
2261 mgp->stats.tx_dropped += 1;
2262 return 0;
2263
2264}
2265
2266static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2267{
2268 struct myri10ge_priv *mgp = netdev_priv(dev);
2269 return &mgp->stats;
2270}
2271
2272static void myri10ge_set_multicast_list(struct net_device *dev)
2273{
85a7ea1b
BG		 2274 struct myri10ge_cmd cmd;
2275 struct myri10ge_priv *mgp;
2276 struct dev_mc_list *mc_list;
6250223e 2277 __be32 data[2] = { 0, 0 };
85a7ea1b
BG		 2278 int err;
2279
2280 mgp = netdev_priv(dev);
0da34b6d
BG		 2281 /* can be called from atomic contexts,
2282 * pass 1 to force atomicity in myri10ge_send_cmd() */
85a7ea1b
BG		 2283 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2284
2285 /* This firmware is known to not support multicast */
2f76216f 2286 if (!mgp->fw_multicast_support)
85a7ea1b
BG		 2287 return;
2288
2289 /* Disable multicast filtering */
2290
2291 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2292 if (err != 0) {
2293 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
2294 " error status: %d\n", dev->name, err);
2295 goto abort;
2296 }
2297
2f76216f 2298 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
85a7ea1b
BG		 2299 /* request to disable multicast filtering, so quit here */
2300 return;
2301 }
2302
2303 /* Flush the filters */
2304
2305 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2306 &cmd, 1);
2307 if (err != 0) {
2308 printk(KERN_ERR
2309 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
2310 ", error status: %d\n", dev->name, err);
2311 goto abort;
2312 }
2313
2314 /* Walk the multicast list, and add each address */
2315 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
40f6cff5
AV		 2316 memcpy(data, &mc_list->dmi_addr, 6);
2317 cmd.data0 = ntohl(data[0]);
2318 cmd.data1 = ntohl(data[1]);
85a7ea1b
BG		 2319 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2320 &cmd, 1);
2321
2322 if (err != 0) {
2323 printk(KERN_ERR "myri10ge: %s: Failed "
2324 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
2325 "%d\t", dev->name, err);
2326 printk(KERN_ERR "MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
2327 ((unsigned char *)&mc_list->dmi_addr)[0],
2328 ((unsigned char *)&mc_list->dmi_addr)[1],
2329 ((unsigned char *)&mc_list->dmi_addr)[2],
2330 ((unsigned char *)&mc_list->dmi_addr)[3],
2331 ((unsigned char *)&mc_list->dmi_addr)[4],
2332 ((unsigned char *)&mc_list->dmi_addr)[5]
2333 );
2334 goto abort;
2335 }
2336 }
2337 /* Enable multicast filtering */
2338 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
2339 if (err != 0) {
2340 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
2341 "error status: %d\n", dev->name, err);
2342 goto abort;
2343 }
2344
2345 return;
2346
2347abort:
2348 return;
0da34b6d
BG		 2349}
2350
2351static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2352{
2353 struct sockaddr *sa = addr;
2354 struct myri10ge_priv *mgp = netdev_priv(dev);
2355 int status;
2356
2357 if (!is_valid_ether_addr(sa->sa_data))
2358 return -EADDRNOTAVAIL;
2359
2360 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2361 if (status != 0) {
2362 printk(KERN_ERR
2363 "myri10ge: %s: changing mac address failed with %d\n",
2364 dev->name, status);
2365 return status;
2366 }
2367
2368 /* change the dev structure */
2369 memcpy(dev->dev_addr, sa->sa_data, 6);
2370 return 0;
2371}
2372
2373static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2374{
2375 struct myri10ge_priv *mgp = netdev_priv(dev);
2376 int error = 0;
2377
2378 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
2379 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
2380 dev->name, new_mtu);
2381 return -EINVAL;
2382 }
2383 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
2384 dev->name, dev->mtu, new_mtu);
2385 if (mgp->running) {
2386 /* if we change the mtu on an active device, we must
2387 * reset the device so the firmware sees the change */
2388 myri10ge_close(dev);
2389 dev->mtu = new_mtu;
2390 myri10ge_open(dev);
2391 } else
2392 dev->mtu = new_mtu;
2393
2394 return error;
2395}
2396
2397/*
2398 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
2399 * Only do it if the bridge is a root port since we don't want to disturb
2400 * any other device, except if forced with myri10ge_ecrc_enable > 1.
2401 */
2402
0da34b6d
BG		 2403static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2404{
2405 struct pci_dev *bridge = mgp->pdev->bus->self;
2406 struct device *dev = &mgp->pdev->dev;
2407 unsigned cap;
2408 unsigned err_cap;
2409 u16 val;
2410 u8 ext_type;
2411 int ret;
2412
2413 if (!myri10ge_ecrc_enable || !bridge)
2414 return;
2415
2416 /* check that the bridge is a root port */
2417 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
2418 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
2419 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2420 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
2421 if (myri10ge_ecrc_enable > 1) {
2422 struct pci_dev *old_bridge = bridge;
2423
2424 /* Walk the hierarchy up to the root port
2425 * where ECRC has to be enabled */
2426 do {
2427 bridge = bridge->bus->self;
2428 if (!bridge) {
2429 dev_err(dev,
2430 "Failed to find root port"
2431 " to force ECRC\n");
2432 return;
2433 }
2434 cap =
2435 pci_find_capability(bridge, PCI_CAP_ID_EXP);
2436 pci_read_config_word(bridge,
2437 cap + PCI_CAP_FLAGS, &val);
2438 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2439 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
2440
2441 dev_info(dev,
2442 "Forcing ECRC on non-root port %s"
2443 " (enabling on root port %s)\n",
2444 pci_name(old_bridge), pci_name(bridge));
2445 } else {
2446 dev_err(dev,
2447 "Not enabling ECRC on non-root port %s\n",
2448 pci_name(bridge));
2449 return;
2450 }
2451 }
2452
2453 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
0da34b6d
BG		 2454 if (!cap)
2455 return;
2456
2457 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
2458 if (ret) {
2459 dev_err(dev, "failed reading ext-conf-space of %s\n",
2460 pci_name(bridge));
2461 dev_err(dev, "\t pci=nommconf in use? "
2462 "or buggy/incomplete/absent ACPI MCFG attr?\n");
2463 return;
2464 }
2465 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
2466 return;
2467
2468 err_cap |= PCI_ERR_CAP_ECRC_GENE;
2469 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
2470 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
2471 mgp->tx.boundary = 4096;
2472 mgp->fw_name = myri10ge_fw_aligned;
2473}
2474
2475/*
2476 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
2477 * when the PCI-E Completion packets are aligned on an 8-byte
2478 * boundary. Some PCI-E chip sets always align Completion packets; on
2479 * the ones that do not, the alignment can be enforced by enabling
2480 * ECRC generation (if supported).
2481 *
2482 * When PCI-E Completion packets are not aligned, it is actually more
2483 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
2484 *
2485 * If the driver can neither enable ECRC nor verify that it has
2486 * already been enabled, then it must use a firmware image which works
2487 * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it
2488 * should also ensure that it never gives the device a Read-DMA which is
2489 * larger than 2KB by setting the tx.boundary to 2KB. If ECRC is
2490 * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat)
2491 * firmware image, and set tx.boundary to 4KB.
2492 */
2493
ce7f9368
BG		 2494#define PCI_DEVICE_ID_INTEL_E5000_PCIE23 0x25f7
2495#define PCI_DEVICE_ID_INTEL_E5000_PCIE47 0x25fa
f19baaea
BG		 2496#define PCI_DEVICE_ID_INTEL_6300ESB_PCIEE1 0x3510
2497#define PCI_DEVICE_ID_INTEL_6300ESB_PCIEE4 0x351b
2498#define PCI_DEVICE_ID_INTEL_E3000_PCIE 0x2779
2499#define PCI_DEVICE_ID_INTEL_E3010_PCIE 0x277a
aafa70eb
BG		 2500#define PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_FIRST 0x140
2501#define PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_LAST 0x142
0da34b6d
BG		 2502
2503static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2504{
2505 struct pci_dev *bridge = mgp->pdev->bus->self;
2506
2507 mgp->tx.boundary = 2048;
2508 mgp->fw_name = myri10ge_fw_unaligned;
2509
2510 if (myri10ge_force_firmware == 0) {
ce7f9368
BG		 2511 int link_width, exp_cap;
2512 u16 lnk;
2513
2514 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
2515 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
2516 link_width = (lnk >> 4) & 0x3f;
2517
0da34b6d
BG		 2518 myri10ge_enable_ecrc(mgp);
2519
ce7f9368
BG		 2520 /* Check to see if Link is less than 8 or if the
2521 * upstream bridge is known to provide aligned
2522 * completions */
2523 if (link_width < 8) {
2524 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
2525 link_width);
2526 mgp->tx.boundary = 4096;
2527 mgp->fw_name = myri10ge_fw_aligned;
2528 } else if (bridge &&
2529 /* ServerWorks HT2000/HT1000 */
2530 ((bridge->vendor == PCI_VENDOR_ID_SERVERWORKS
2531 && bridge->device ==
2532 PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE)
aafa70eb
BG		 2533 /* ServerWorks HT2100 */
2534 || (bridge->vendor == PCI_VENDOR_ID_SERVERWORKS
2535 && bridge->device >=
2536 PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_FIRST
2537 && bridge->device <=
2538 PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_LAST)
f19baaea
BG		 2539 /* All Intel E3000/E3010 PCIE ports */
2540 || (bridge->vendor == PCI_VENDOR_ID_INTEL
2541 && (bridge->device ==
2542 PCI_DEVICE_ID_INTEL_E3000_PCIE
2543 || bridge->device ==
2544 PCI_DEVICE_ID_INTEL_E3010_PCIE))
2545 /* All Intel 6310/6311/6321ESB PCIE ports */
2546 || (bridge->vendor == PCI_VENDOR_ID_INTEL
2547 && bridge->device >=
2548 PCI_DEVICE_ID_INTEL_6300ESB_PCIEE1
2549 && bridge->device <=
2550 PCI_DEVICE_ID_INTEL_6300ESB_PCIEE4)
ce7f9368
BG		 2551 /* All Intel E5000 PCIE ports */
2552 || (bridge->vendor == PCI_VENDOR_ID_INTEL
2553 && bridge->device >=
2554 PCI_DEVICE_ID_INTEL_E5000_PCIE23
2555 && bridge->device <=
2556 PCI_DEVICE_ID_INTEL_E5000_PCIE47))) {
0da34b6d
BG		 2557 dev_info(&mgp->pdev->dev,
2558 "Assuming aligned completions (0x%x:0x%x)\n",
2559 bridge->vendor, bridge->device);
2560 mgp->tx.boundary = 4096;
2561 mgp->fw_name = myri10ge_fw_aligned;
4c882dd8
BG		 2562 } else if (bridge &&
2563 bridge->vendor == PCI_VENDOR_ID_SGI &&
2564 bridge->device == 0x4002 /* TIOCE pcie-port */ ) {
2565 /* this pcie bridge does not support 4K rdma request */
2566 mgp->tx.boundary = 2048;
2567 mgp->fw_name = myri10ge_fw_aligned;
0da34b6d
BG		 2568 }
2569 } else {
2570 if (myri10ge_force_firmware == 1) {
2571 dev_info(&mgp->pdev->dev,
2572 "Assuming aligned completions (forced)\n");
2573 mgp->tx.boundary = 4096;
2574 mgp->fw_name = myri10ge_fw_aligned;
2575 } else {
2576 dev_info(&mgp->pdev->dev,
2577 "Assuming unaligned completions (forced)\n");
2578 mgp->tx.boundary = 2048;
2579 mgp->fw_name = myri10ge_fw_unaligned;
2580 }
2581 }
2582 if (myri10ge_fw_name != NULL) {
2583 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
2584 myri10ge_fw_name);
2585 mgp->fw_name = myri10ge_fw_name;
2586 }
2587}
2588
0da34b6d
BG		 2589#ifdef CONFIG_PM
2590
2591static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
2592{
2593 struct myri10ge_priv *mgp;
2594 struct net_device *netdev;
2595
2596 mgp = pci_get_drvdata(pdev);
2597 if (mgp == NULL)
2598 return -EINVAL;
2599 netdev = mgp->dev;
2600
2601 netif_device_detach(netdev);
2602 if (netif_running(netdev)) {
2603 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
2604 rtnl_lock();
2605 myri10ge_close(netdev);
2606 rtnl_unlock();
2607 }
2608 myri10ge_dummy_rdma(mgp, 0);
83f6e152 2609 pci_save_state(pdev);
0da34b6d 2610 pci_disable_device(pdev);
1a63e846
BG		 2611
2612 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
0da34b6d
BG		 2613}
2614
2615static int myri10ge_resume(struct pci_dev *pdev)
2616{
2617 struct myri10ge_priv *mgp;
2618 struct net_device *netdev;
2619 int status;
2620 u16 vendor;
2621
2622 mgp = pci_get_drvdata(pdev);
2623 if (mgp == NULL)
2624 return -EINVAL;
2625 netdev = mgp->dev;
2626 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
2627 msleep(5); /* give card time to respond */
2628 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2629 if (vendor == 0xffff) {
2630 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
2631 mgp->dev->name);
2632 return -EIO;
2633 }
83f6e152 2634
1a63e846
BG		 2635 status = pci_restore_state(pdev);
2636 if (status)
2637 return status;
4c2248cc
BG		 2638
2639 status = pci_enable_device(pdev);
1a63e846 2640 if (status) {
4c2248cc 2641 dev_err(&pdev->dev, "failed to enable device\n");
1a63e846 2642 return status;
4c2248cc
BG		 2643 }
2644
0da34b6d
BG		 2645 pci_set_master(pdev);
2646
0da34b6d 2647 myri10ge_reset(mgp);
013b68bf 2648 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 2649
2650 /* Save configuration space to be restored if the
2651 * nic resets due to a parity error */
83f6e152 2652 pci_save_state(pdev);
0da34b6d
BG		 2653
2654 if (netif_running(netdev)) {
2655 rtnl_lock();
df30a740 2656 status = myri10ge_open(netdev);
0da34b6d 2657 rtnl_unlock();
df30a740
BG		 2658 if (status != 0)
2659 goto abort_with_enabled;
2660
0da34b6d
BG		 2661 }
2662 netif_device_attach(netdev);
2663
2664 return 0;
2665
4c2248cc
BG		 2666abort_with_enabled:
2667 pci_disable_device(pdev);
0da34b6d
BG		 2668 return -EIO;
2669
2670}
2671
2672#endif /* CONFIG_PM */
2673
2674static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
2675{
2676 struct pci_dev *pdev = mgp->pdev;
2677 int vs = mgp->vendor_specific_offset;
2678 u32 reboot;
2679
2680 /*enter read32 mode */
2681 pci_write_config_byte(pdev, vs + 0x10, 0x3);
2682
2683 /*read REBOOT_STATUS (0xfffffff0) */
2684 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
2685 pci_read_config_dword(pdev, vs + 0x14, &reboot);
2686 return reboot;
2687}
2688
2689/*
2690 * This watchdog is used to check whether the board has suffered
2691 * from a parity error and needs to be recovered.
2692 */
c4028958 2693static void myri10ge_watchdog(struct work_struct *work)
0da34b6d 2694{
c4028958 2695 struct myri10ge_priv *mgp =
6250223e 2696 container_of(work, struct myri10ge_priv, watchdog_work);
0da34b6d
BG		 2697 u32 reboot;
2698 int status;
2699 u16 cmd, vendor;
2700
2701 mgp->watchdog_resets++;
2702 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
2703 if ((cmd & PCI_COMMAND_MASTER) == 0) {
2704 /* Bus master DMA disabled? Check to see
2705 * if the card rebooted due to a parity error
2706 * For now, just report it */
2707 reboot = myri10ge_read_reboot(mgp);
2708 printk(KERN_ERR
2709 "myri10ge: %s: NIC rebooted (0x%x), resetting\n",
2710 mgp->dev->name, reboot);
2711 /*
2712 * A rebooted nic will come back with config space as
2713 * it was after power was applied to PCIe bus.
2714 * Attempt to restore config space which was saved
2715 * when the driver was loaded, or the last time the
2716 * nic was resumed from power saving mode.
2717 */
83f6e152 2718 pci_restore_state(mgp->pdev);
7adda30c
BG		 2719
2720 /* save state again for accounting reasons */
83f6e152 2721 pci_save_state(mgp->pdev);
7adda30c 2722
0da34b6d
BG		 2723 } else {
2724 /* if we get back -1's from our slot, perhaps somebody
2725 * powered off our card. Don't try to reset it in
2726 * this case */
2727 if (cmd == 0xffff) {
2728 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2729 if (vendor == 0xffff) {
2730 printk(KERN_ERR
2731 "myri10ge: %s: device disappeared!\n",
2732 mgp->dev->name);
2733 return;
2734 }
2735 }
2736 /* Perhaps it is a software error. Try to reset */
2737
2738 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
2739 mgp->dev->name);
2740 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2741 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2742 mgp->tx.pkt_start, mgp->tx.pkt_done,
2743 (int)ntohl(mgp->fw_stats->send_done_count));
2744 msleep(2000);
2745 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2746 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2747 mgp->tx.pkt_start, mgp->tx.pkt_done,
2748 (int)ntohl(mgp->fw_stats->send_done_count));
2749 }
2750 rtnl_lock();
2751 myri10ge_close(mgp->dev);
2752 status = myri10ge_load_firmware(mgp);
2753 if (status != 0)
2754 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
2755 mgp->dev->name);
2756 else
2757 myri10ge_open(mgp->dev);
2758 rtnl_unlock();
2759}
2760
2761/*
2762 * We use our own timer routine rather than relying upon
2763 * netdev->tx_timeout because we have a very large hardware transmit
2764 * queue. Due to the large queue, the netdev->tx_timeout function
2765 * cannot detect a NIC with a parity error in a timely fashion if the
2766 * NIC is lightly loaded.
2767 */
2768static void myri10ge_watchdog_timer(unsigned long arg)
2769{
2770 struct myri10ge_priv *mgp;
2771
2772 mgp = (struct myri10ge_priv *)arg;
c7dab99b
BG		 2773
2774 if (mgp->rx_small.watchdog_needed) {
2775 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
2776 mgp->small_bytes + MXGEFW_PAD, 1);
2777 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt >=
2778 myri10ge_fill_thresh)
2779 mgp->rx_small.watchdog_needed = 0;
2780 }
2781 if (mgp->rx_big.watchdog_needed) {
2782 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 1);
2783 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt >=
2784 myri10ge_fill_thresh)
2785 mgp->rx_big.watchdog_needed = 0;
2786 }
2787
0da34b6d 2788 if (mgp->tx.req != mgp->tx.done &&
c54772e7
BG		 2789 mgp->tx.done == mgp->watchdog_tx_done &&
2790 mgp->watchdog_tx_req != mgp->watchdog_tx_done)
0da34b6d
BG		 2791 /* nic seems like it might be stuck.. */
2792 schedule_work(&mgp->watchdog_work);
2793 else
2794 /* rearm timer */
2795 mod_timer(&mgp->watchdog_timer,
2796 jiffies + myri10ge_watchdog_timeout * HZ);
2797
2798 mgp->watchdog_tx_done = mgp->tx.done;
c54772e7 2799 mgp->watchdog_tx_req = mgp->tx.req;
0da34b6d
BG		 2800}
2801
2802static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2803{
2804 struct net_device *netdev;
2805 struct myri10ge_priv *mgp;
2806 struct device *dev = &pdev->dev;
2807 size_t bytes;
2808 int i;
2809 int status = -ENXIO;
2810 int cap;
2811 int dac_enabled;
2812 u16 val;
2813
2814 netdev = alloc_etherdev(sizeof(*mgp));
2815 if (netdev == NULL) {
2816 dev_err(dev, "Could not allocate ethernet device\n");
2817 return -ENOMEM;
2818 }
2819
2820 mgp = netdev_priv(netdev);
2821 memset(mgp, 0, sizeof(*mgp));
2822 mgp->dev = netdev;
2823 mgp->pdev = pdev;
2824 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
2825 mgp->pause = myri10ge_flow_control;
2826 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
c58ac5ca 2827 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
0da34b6d
BG		 2828 init_waitqueue_head(&mgp->down_wq);
2829
2830 if (pci_enable_device(pdev)) {
2831 dev_err(&pdev->dev, "pci_enable_device call failed\n");
2832 status = -ENODEV;
2833 goto abort_with_netdev;
2834 }
2835 myri10ge_select_firmware(mgp);
2836
2837 /* Find the vendor-specific cap so we can check
2838 * the reboot register later on */
2839 mgp->vendor_specific_offset
2840 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
2841
2842 /* Set our max read request to 4KB */
2843 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2844 if (cap < 64) {
2845 dev_err(&pdev->dev, "Bad PCI_CAP_ID_EXP location %d\n", cap);
2846 goto abort_with_netdev;
2847 }
2848 status = pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &val);
2849 if (status != 0) {
2850 dev_err(&pdev->dev, "Error %d reading PCI_EXP_DEVCTL\n",
2851 status);
2852 goto abort_with_netdev;
2853 }
2854 val = (val & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);
2855 status = pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, val);
2856 if (status != 0) {
2857 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
2858 status);
2859 goto abort_with_netdev;
2860 }
2861
2862 pci_set_master(pdev);
2863 dac_enabled = 1;
2864 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2865 if (status != 0) {
2866 dac_enabled = 0;
2867 dev_err(&pdev->dev,
2868 "64-bit pci address mask was refused, trying 32-bit");
2869 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2870 }
2871 if (status != 0) {
2872 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
2873 goto abort_with_netdev;
2874 }
b10c0668
BG		 2875 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
2876 &mgp->cmd_bus, GFP_KERNEL);
0da34b6d
BG		 2877 if (mgp->cmd == NULL)
2878 goto abort_with_netdev;
2879
b10c0668
BG		 2880 mgp->fw_stats = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2881 &mgp->fw_stats_bus, GFP_KERNEL);
0da34b6d
BG		 2882 if (mgp->fw_stats == NULL)
2883 goto abort_with_cmd;
2884
2885 mgp->board_span = pci_resource_len(pdev, 0);
2886 mgp->iomem_base = pci_resource_start(pdev, 0);
2887 mgp->mtrr = -1;
276e26c3 2888 mgp->wc_enabled = 0;
0da34b6d
BG		 2889#ifdef CONFIG_MTRR
2890 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
2891 MTRR_TYPE_WRCOMB, 1);
276e26c3
BG		 2892 if (mgp->mtrr >= 0)
2893 mgp->wc_enabled = 1;
0da34b6d
BG		 2894#endif
2895 /* Hack. need to get rid of these magic numbers */
2896 mgp->sram_size =
2897 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
2898 if (mgp->sram_size > mgp->board_span) {
2899 dev_err(&pdev->dev, "board span %ld bytes too small\n",
2900 mgp->board_span);
2901 goto abort_with_wc;
2902 }
2903 mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
2904 if (mgp->sram == NULL) {
2905 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
2906 mgp->board_span, mgp->iomem_base);
2907 status = -ENXIO;
2908 goto abort_with_wc;
2909 }
2910 memcpy_fromio(mgp->eeprom_strings,
2911 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
2912 MYRI10GE_EEPROM_STRINGS_SIZE);
2913 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
2914 status = myri10ge_read_mac_addr(mgp);
2915 if (status)
2916 goto abort_with_ioremap;
2917
2918 for (i = 0; i < ETH_ALEN; i++)
2919 netdev->dev_addr[i] = mgp->mac_addr[i];
2920
2921 /* allocate rx done ring */
2922 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 2923 mgp->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
2924 &mgp->rx_done.bus, GFP_KERNEL);
0da34b6d
BG		 2925 if (mgp->rx_done.entry == NULL)
2926 goto abort_with_ioremap;
2927 memset(mgp->rx_done.entry, 0, bytes);
2928
2929 status = myri10ge_load_firmware(mgp);
2930 if (status != 0) {
2931 dev_err(&pdev->dev, "failed to load firmware\n");
2932 goto abort_with_rx_done;
2933 }
2934
2935 status = myri10ge_reset(mgp);
2936 if (status != 0) {
2937 dev_err(&pdev->dev, "failed reset\n");
2938 goto abort_with_firmware;
2939 }
2940
0da34b6d
BG		 2941 pci_set_drvdata(pdev, mgp);
2942 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
2943 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
2944 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
2945 myri10ge_initial_mtu = 68;
2946 netdev->mtu = myri10ge_initial_mtu;
2947 netdev->open = myri10ge_open;
2948 netdev->stop = myri10ge_close;
2949 netdev->hard_start_xmit = myri10ge_xmit;
2950 netdev->get_stats = myri10ge_get_stats;
2951 netdev->base_addr = mgp->iomem_base;
0da34b6d
BG		 2952 netdev->change_mtu = myri10ge_change_mtu;
2953 netdev->set_multicast_list = myri10ge_set_multicast_list;
2954 netdev->set_mac_address = myri10ge_set_mac_address;
2955 netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
2956 if (dac_enabled)
2957 netdev->features |= NETIF_F_HIGHDMA;
2958 netdev->poll = myri10ge_poll;
2959 netdev->weight = myri10ge_napi_weight;
2960
21d05db1
BG		 2961 /* make sure we can get an irq, and that MSI can be
2962 * setup (if available). Also ensure netdev->irq
2963 * is set to correct value if MSI is enabled */
2964 status = myri10ge_request_irq(mgp);
2965 if (status != 0)
2966 goto abort_with_firmware;
2967 netdev->irq = pdev->irq;
2968 myri10ge_free_irq(mgp);
2969
0da34b6d
BG		 2970 /* Save configuration space to be restored if the
2971 * nic resets due to a parity error */
83f6e152 2972 pci_save_state(pdev);
0da34b6d
BG		 2973
2974 /* Setup the watchdog timer */
2975 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
2976 (unsigned long)mgp);
2977
2978 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
c4028958 2979 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
0da34b6d
BG		 2980 status = register_netdev(netdev);
2981 if (status != 0) {
2982 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
7adda30c 2983 goto abort_with_state;
0da34b6d 2984 }
21d05db1
BG		 2985 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
2986 (mgp->msi_enabled ? "MSI" : "xPIC"),
2987 netdev->irq, mgp->tx.boundary, mgp->fw_name,
276e26c3 2988 (mgp->wc_enabled ? "Enabled" : "Disabled"));
0da34b6d
BG		 2989
2990 return 0;
2991
7adda30c 2992abort_with_state:
83f6e152 2993 pci_restore_state(pdev);
0da34b6d
BG		 2994
2995abort_with_firmware:
2996 myri10ge_dummy_rdma(mgp, 0);
2997
2998abort_with_rx_done:
2999 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 3000 dma_free_coherent(&pdev->dev, bytes,
3001 mgp->rx_done.entry, mgp->rx_done.bus);
0da34b6d
BG		 3002
3003abort_with_ioremap:
3004 iounmap(mgp->sram);
3005
3006abort_with_wc:
3007#ifdef CONFIG_MTRR
3008 if (mgp->mtrr >= 0)
3009 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3010#endif
b10c0668
BG		 3011 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3012 mgp->fw_stats, mgp->fw_stats_bus);
0da34b6d
BG		 3013
3014abort_with_cmd:
b10c0668
BG		 3015 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3016 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 3017
3018abort_with_netdev:
3019
3020 free_netdev(netdev);
3021 return status;
3022}
3023
3024/*
3025 * myri10ge_remove
3026 *
3027 * Does what is necessary to shutdown one Myrinet device. Called
3028 * once for each Myrinet card by the kernel when a module is
3029 * unloaded.
3030 */
3031static void myri10ge_remove(struct pci_dev *pdev)
3032{
3033 struct myri10ge_priv *mgp;
3034 struct net_device *netdev;
3035 size_t bytes;
3036
3037 mgp = pci_get_drvdata(pdev);
3038 if (mgp == NULL)
3039 return;
3040
3041 flush_scheduled_work();
3042 netdev = mgp->dev;
3043 unregister_netdev(netdev);
0da34b6d
BG		 3044
3045 myri10ge_dummy_rdma(mgp, 0);
3046
7adda30c 3047 /* avoid a memory leak */
83f6e152 3048 pci_restore_state(pdev);
7adda30c 3049
0da34b6d 3050 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 3051 dma_free_coherent(&pdev->dev, bytes,
3052 mgp->rx_done.entry, mgp->rx_done.bus);
0da34b6d
BG		 3053
3054 iounmap(mgp->sram);
3055
3056#ifdef CONFIG_MTRR
3057 if (mgp->mtrr >= 0)
3058 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3059#endif
b10c0668
BG		 3060 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3061 mgp->fw_stats, mgp->fw_stats_bus);
0da34b6d 3062
b10c0668
BG		 3063 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3064 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 3065
3066 free_netdev(netdev);
3067 pci_set_drvdata(pdev, NULL);
3068}
3069
b10c0668 3070#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
0da34b6d
BG		 3071
3072static struct pci_device_id myri10ge_pci_tbl[] = {
b10c0668 3073 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
0da34b6d
BG		 3074 {0},
3075};
3076
3077static struct pci_driver myri10ge_driver = {
3078 .name = "myri10ge",
3079 .probe = myri10ge_probe,
3080 .remove = myri10ge_remove,
3081 .id_table = myri10ge_pci_tbl,
3082#ifdef CONFIG_PM
3083 .suspend = myri10ge_suspend,
3084 .resume = myri10ge_resume,
3085#endif
3086};
3087
3088static __init int myri10ge_init_module(void)
3089{
3090 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
3091 MYRI10GE_VERSION_STR);
3092 return pci_register_driver(&myri10ge_driver);
3093}
3094
3095module_init(myri10ge_init_module);
3096
3097static __exit void myri10ge_cleanup_module(void)
3098{
3099 pci_unregister_driver(&myri10ge_driver);
3100}
3101
3102module_exit(myri10ge_cleanup_module);
Linux kernel - Deliverables
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