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Merge master.kernel.org:/pub/scm/linux/kernel/git/gregkh/usb-2.6
[deliverable/linux.git] / drivers / net / myri10ge / myri10ge.c
CommitLineData
0da34b6d
BG		 1/*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4 * Copyright (C) 2005, 2006 Myricom, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41#include <linux/tcp.h>
42#include <linux/netdevice.h>
43#include <linux/skbuff.h>
44#include <linux/string.h>
45#include <linux/module.h>
46#include <linux/pci.h>
b10c0668 47#include <linux/dma-mapping.h>
0da34b6d
BG		 48#include <linux/etherdevice.h>
49#include <linux/if_ether.h>
50#include <linux/if_vlan.h>
51#include <linux/ip.h>
52#include <linux/inet.h>
53#include <linux/in.h>
54#include <linux/ethtool.h>
55#include <linux/firmware.h>
56#include <linux/delay.h>
57#include <linux/version.h>
58#include <linux/timer.h>
59#include <linux/vmalloc.h>
60#include <linux/crc32.h>
61#include <linux/moduleparam.h>
62#include <linux/io.h>
63#include <net/checksum.h>
64#include <asm/byteorder.h>
65#include <asm/io.h>
0da34b6d
BG		 66#include <asm/processor.h>
67#ifdef CONFIG_MTRR
68#include <asm/mtrr.h>
69#endif
70
71#include "myri10ge_mcp.h"
72#include "myri10ge_mcp_gen_header.h"
73
b10c0668 74#define MYRI10GE_VERSION_STR "1.0.0"
0da34b6d
BG		 75
76MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
77MODULE_AUTHOR("Maintainer: help@myri.com");
78MODULE_VERSION(MYRI10GE_VERSION_STR);
79MODULE_LICENSE("Dual BSD/GPL");
80
81#define MYRI10GE_MAX_ETHER_MTU 9014
82
83#define MYRI10GE_ETH_STOPPED 0
84#define MYRI10GE_ETH_STOPPING 1
85#define MYRI10GE_ETH_STARTING 2
86#define MYRI10GE_ETH_RUNNING 3
87#define MYRI10GE_ETH_OPEN_FAILED 4
88
89#define MYRI10GE_EEPROM_STRINGS_SIZE 256
90#define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
91
92#define MYRI10GE_NO_CONFIRM_DATA 0xffffffff
93#define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
94
95struct myri10ge_rx_buffer_state {
96 struct sk_buff *skb;
97 DECLARE_PCI_UNMAP_ADDR(bus)
98 DECLARE_PCI_UNMAP_LEN(len)
99};
100
101struct myri10ge_tx_buffer_state {
102 struct sk_buff *skb;
103 int last;
104 DECLARE_PCI_UNMAP_ADDR(bus)
105 DECLARE_PCI_UNMAP_LEN(len)
106};
107
108struct myri10ge_cmd {
109 u32 data0;
110 u32 data1;
111 u32 data2;
112};
113
114struct myri10ge_rx_buf {
115 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
116 u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */
117 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
118 struct myri10ge_rx_buffer_state *info;
119 int cnt;
120 int alloc_fail;
121 int mask; /* number of rx slots -1 */
122};
123
124struct myri10ge_tx_buf {
125 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
126 u8 __iomem *wc_fifo; /* w/c send fifo address */
127 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
128 char *req_bytes;
129 struct myri10ge_tx_buffer_state *info;
130 int mask; /* number of transmit slots -1 */
131 int boundary; /* boundary transmits cannot cross */
132 int req ____cacheline_aligned; /* transmit slots submitted */
133 int pkt_start; /* packets started */
134 int done ____cacheline_aligned; /* transmit slots completed */
135 int pkt_done; /* packets completed */
136};
137
138struct myri10ge_rx_done {
139 struct mcp_slot *entry;
140 dma_addr_t bus;
141 int cnt;
142 int idx;
143};
144
145struct myri10ge_priv {
146 int running; /* running? */
147 int csum_flag; /* rx_csums? */
148 struct myri10ge_tx_buf tx; /* transmit ring */
149 struct myri10ge_rx_buf rx_small;
150 struct myri10ge_rx_buf rx_big;
151 struct myri10ge_rx_done rx_done;
152 int small_bytes;
153 struct net_device *dev;
154 struct net_device_stats stats;
155 u8 __iomem *sram;
156 int sram_size;
157 unsigned long board_span;
158 unsigned long iomem_base;
159 u32 __iomem *irq_claim;
160 u32 __iomem *irq_deassert;
161 char *mac_addr_string;
162 struct mcp_cmd_response *cmd;
163 dma_addr_t cmd_bus;
164 struct mcp_irq_data *fw_stats;
165 dma_addr_t fw_stats_bus;
166 struct pci_dev *pdev;
167 int msi_enabled;
168 unsigned int link_state;
169 unsigned int rdma_tags_available;
170 int intr_coal_delay;
171 u32 __iomem *intr_coal_delay_ptr;
172 int mtrr;
173 int wake_queue;
174 int stop_queue;
175 int down_cnt;
176 wait_queue_head_t down_wq;
177 struct work_struct watchdog_work;
178 struct timer_list watchdog_timer;
179 int watchdog_tx_done;
180 int watchdog_resets;
181 int tx_linearized;
182 int pause;
183 char *fw_name;
184 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
185 char fw_version[128];
186 u8 mac_addr[6]; /* eeprom mac address */
187 unsigned long serial_number;
188 int vendor_specific_offset;
189 u32 devctl;
190 u16 msi_flags;
191 u32 pm_state[16];
192 u32 read_dma;
193 u32 write_dma;
194 u32 read_write_dma;
195};
196
197static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
198static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
199
200static char *myri10ge_fw_name = NULL;
201module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
202MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name\n");
203
204static int myri10ge_ecrc_enable = 1;
205module_param(myri10ge_ecrc_enable, int, S_IRUGO);
206MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E\n");
207
208static int myri10ge_max_intr_slots = 1024;
209module_param(myri10ge_max_intr_slots, int, S_IRUGO);
210MODULE_PARM_DESC(myri10ge_max_intr_slots, "Interrupt queue slots\n");
211
212static int myri10ge_small_bytes = -1; /* -1 == auto */
213module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
214MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets\n");
215
216static int myri10ge_msi = 1; /* enable msi by default */
217module_param(myri10ge_msi, int, S_IRUGO);
218MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts\n");
219
220static int myri10ge_intr_coal_delay = 25;
221module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
222MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay\n");
223
224static int myri10ge_flow_control = 1;
225module_param(myri10ge_flow_control, int, S_IRUGO);
226MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter\n");
227
228static int myri10ge_deassert_wait = 1;
229module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
230MODULE_PARM_DESC(myri10ge_deassert_wait,
231 "Wait when deasserting legacy interrupts\n");
232
233static int myri10ge_force_firmware = 0;
234module_param(myri10ge_force_firmware, int, S_IRUGO);
235MODULE_PARM_DESC(myri10ge_force_firmware,
236 "Force firmware to assume aligned completions\n");
237
238static int myri10ge_skb_cross_4k = 0;
239module_param(myri10ge_skb_cross_4k, int, S_IRUGO | S_IWUSR);
240MODULE_PARM_DESC(myri10ge_skb_cross_4k,
241 "Can a small skb cross a 4KB boundary?\n");
242
243static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
244module_param(myri10ge_initial_mtu, int, S_IRUGO);
245MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU\n");
246
247static int myri10ge_napi_weight = 64;
248module_param(myri10ge_napi_weight, int, S_IRUGO);
249MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight\n");
250
251static int myri10ge_watchdog_timeout = 1;
252module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
253MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout\n");
254
255static int myri10ge_max_irq_loops = 1048576;
256module_param(myri10ge_max_irq_loops, int, S_IRUGO);
257MODULE_PARM_DESC(myri10ge_max_irq_loops,
258 "Set stuck legacy IRQ detection threshold\n");
259
260#define MYRI10GE_FW_OFFSET 1024*1024
261#define MYRI10GE_HIGHPART_TO_U32(X) \
262(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
263#define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
264
265#define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
266
267static int
268myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
269 struct myri10ge_cmd *data, int atomic)
270{
271 struct mcp_cmd *buf;
272 char buf_bytes[sizeof(*buf) + 8];
273 struct mcp_cmd_response *response = mgp->cmd;
274 char __iomem *cmd_addr = mgp->sram + MXGEFW_CMD_OFFSET;
275 u32 dma_low, dma_high, result, value;
276 int sleep_total = 0;
277
278 /* ensure buf is aligned to 8 bytes */
279 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
280
281 buf->data0 = htonl(data->data0);
282 buf->data1 = htonl(data->data1);
283 buf->data2 = htonl(data->data2);
284 buf->cmd = htonl(cmd);
285 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
286 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
287
288 buf->response_addr.low = htonl(dma_low);
289 buf->response_addr.high = htonl(dma_high);
290 response->result = MYRI10GE_NO_RESPONSE_RESULT;
291 mb();
292 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
293
294 /* wait up to 15ms. Longest command is the DMA benchmark,
295 * which is capped at 5ms, but runs from a timeout handler
296 * that runs every 7.8ms. So a 15ms timeout leaves us with
297 * a 2.2ms margin
298 */
299 if (atomic) {
300 /* if atomic is set, do not sleep,
301 * and try to get the completion quickly
302 * (1ms will be enough for those commands) */
303 for (sleep_total = 0;
304 sleep_total < 1000
305 && response->result == MYRI10GE_NO_RESPONSE_RESULT;
306 sleep_total += 10)
307 udelay(10);
308 } else {
309 /* use msleep for most command */
310 for (sleep_total = 0;
311 sleep_total < 15
312 && response->result == MYRI10GE_NO_RESPONSE_RESULT;
313 sleep_total++)
314 msleep(1);
315 }
316
317 result = ntohl(response->result);
318 value = ntohl(response->data);
319 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
320 if (result == 0) {
321 data->data0 = value;
322 return 0;
323 } else {
324 dev_err(&mgp->pdev->dev,
325 "command %d failed, result = %d\n",
326 cmd, result);
327 return -ENXIO;
328 }
329 }
330
331 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
332 cmd, result);
333 return -EAGAIN;
334}
335
336/*
337 * The eeprom strings on the lanaiX have the format
338 * SN=x\0
339 * MAC=x:x:x:x:x:x\0
340 * PT:ddd mmm xx xx:xx:xx xx\0
341 * PV:ddd mmm xx xx:xx:xx xx\0
342 */
343static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
344{
345 char *ptr, *limit;
346 int i;
347
348 ptr = mgp->eeprom_strings;
349 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
350
351 while (*ptr != '\0' && ptr < limit) {
352 if (memcmp(ptr, "MAC=", 4) == 0) {
353 ptr += 4;
354 mgp->mac_addr_string = ptr;
355 for (i = 0; i < 6; i++) {
356 if ((ptr + 2) > limit)
357 goto abort;
358 mgp->mac_addr[i] =
359 simple_strtoul(ptr, &ptr, 16);
360 ptr += 1;
361 }
362 }
363 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
364 ptr += 3;
365 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
366 }
367 while (ptr < limit && *ptr++) ;
368 }
369
370 return 0;
371
372abort:
373 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
374 return -ENXIO;
375}
376
377/*
378 * Enable or disable periodic RDMAs from the host to make certain
379 * chipsets resend dropped PCIe messages
380 */
381
382static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
383{
384 char __iomem *submit;
385 u32 buf[16];
386 u32 dma_low, dma_high;
387 int i;
388
389 /* clear confirmation addr */
390 mgp->cmd->data = 0;
391 mb();
392
393 /* send a rdma command to the PCIe engine, and wait for the
394 * response in the confirmation address. The firmware should
395 * write a -1 there to indicate it is alive and well
396 */
397 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
398 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
399
400 buf[0] = htonl(dma_high); /* confirm addr MSW */
401 buf[1] = htonl(dma_low); /* confirm addr LSW */
402 buf[2] = htonl(MYRI10GE_NO_CONFIRM_DATA); /* confirm data */
403 buf[3] = htonl(dma_high); /* dummy addr MSW */
404 buf[4] = htonl(dma_low); /* dummy addr LSW */
405 buf[5] = htonl(enable); /* enable? */
406
407 submit = mgp->sram + 0xfc01c0;
408
409 myri10ge_pio_copy(submit, &buf, sizeof(buf));
410 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
411 msleep(1);
412 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
413 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
414 (enable ? "enable" : "disable"));
415}
416
417static int
418myri10ge_validate_firmware(struct myri10ge_priv *mgp,
419 struct mcp_gen_header *hdr)
420{
421 struct device *dev = &mgp->pdev->dev;
422 int major, minor;
423
424 /* check firmware type */
425 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
426 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
427 return -EINVAL;
428 }
429
430 /* save firmware version for ethtool */
431 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
432
433 sscanf(mgp->fw_version, "%d.%d", &major, &minor);
434
435 if (!(major == MXGEFW_VERSION_MAJOR && minor == MXGEFW_VERSION_MINOR)) {
436 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
437 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
438 MXGEFW_VERSION_MINOR);
439 return -EINVAL;
440 }
441 return 0;
442}
443
444static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
445{
446 unsigned crc, reread_crc;
447 const struct firmware *fw;
448 struct device *dev = &mgp->pdev->dev;
449 struct mcp_gen_header *hdr;
450 size_t hdr_offset;
451 int status;
452
453 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
454 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
455 mgp->fw_name);
456 status = -EINVAL;
457 goto abort_with_nothing;
458 }
459
460 /* check size */
461
462 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
463 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
464 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
465 status = -EINVAL;
466 goto abort_with_fw;
467 }
468
469 /* check id */
470 hdr_offset = ntohl(*(u32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
471 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
472 dev_err(dev, "Bad firmware file\n");
473 status = -EINVAL;
474 goto abort_with_fw;
475 }
476 hdr = (void *)(fw->data + hdr_offset);
477
478 status = myri10ge_validate_firmware(mgp, hdr);
479 if (status != 0)
480 goto abort_with_fw;
481
482 crc = crc32(~0, fw->data, fw->size);
b10c0668
BG		 483 if (mgp->tx.boundary == 2048) {
484 /* Avoid PCI burst on chipset with unaligned completions. */
485 int i;
486 __iomem u32 *ptr = (__iomem u32 *) (mgp->sram +
487 MYRI10GE_FW_OFFSET);
488 for (i = 0; i < fw->size / 4; i++) {
489 __raw_writel(((u32 *) fw->data)[i], ptr + i);
490 wmb();
491 }
492 } else {
493 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET, fw->data,
494 fw->size);
495 }
0da34b6d
BG		 496 /* corruption checking is good for parity recovery and buggy chipset */
497 memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
498 reread_crc = crc32(~0, fw->data, fw->size);
499 if (crc != reread_crc) {
500 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
501 (unsigned)fw->size, reread_crc, crc);
502 status = -EIO;
503 goto abort_with_fw;
504 }
505 *size = (u32) fw->size;
506
507abort_with_fw:
508 release_firmware(fw);
509
510abort_with_nothing:
511 return status;
512}
513
514static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
515{
516 struct mcp_gen_header *hdr;
517 struct device *dev = &mgp->pdev->dev;
518 const size_t bytes = sizeof(struct mcp_gen_header);
519 size_t hdr_offset;
520 int status;
521
522 /* find running firmware header */
523 hdr_offset = ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
524
525 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
526 dev_err(dev, "Running firmware has bad header offset (%d)\n",
527 (int)hdr_offset);
528 return -EIO;
529 }
530
531 /* copy header of running firmware from SRAM to host memory to
532 * validate firmware */
533 hdr = kmalloc(bytes, GFP_KERNEL);
534 if (hdr == NULL) {
535 dev_err(dev, "could not malloc firmware hdr\n");
536 return -ENOMEM;
537 }
538 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
539 status = myri10ge_validate_firmware(mgp, hdr);
540 kfree(hdr);
541 return status;
542}
543
544static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
545{
546 char __iomem *submit;
547 u32 buf[16];
548 u32 dma_low, dma_high, size;
549 int status, i;
550
b10c0668 551 size = 0;
0da34b6d
BG		 552 status = myri10ge_load_hotplug_firmware(mgp, &size);
553 if (status) {
554 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
555
556 /* Do not attempt to adopt firmware if there
557 * was a bad crc */
558 if (status == -EIO)
559 return status;
560
561 status = myri10ge_adopt_running_firmware(mgp);
562 if (status != 0) {
563 dev_err(&mgp->pdev->dev,
564 "failed to adopt running firmware\n");
565 return status;
566 }
567 dev_info(&mgp->pdev->dev,
568 "Successfully adopted running firmware\n");
569 if (mgp->tx.boundary == 4096) {
570 dev_warn(&mgp->pdev->dev,
571 "Using firmware currently running on NIC"
572 ". For optimal\n");
573 dev_warn(&mgp->pdev->dev,
574 "performance consider loading optimized "
575 "firmware\n");
576 dev_warn(&mgp->pdev->dev, "via hotplug\n");
577 }
578
579 mgp->fw_name = "adopted";
580 mgp->tx.boundary = 2048;
581 return status;
582 }
583
584 /* clear confirmation addr */
585 mgp->cmd->data = 0;
586 mb();
587
588 /* send a reload command to the bootstrap MCP, and wait for the
589 * response in the confirmation address. The firmware should
590 * write a -1 there to indicate it is alive and well
591 */
592 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
593 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
594
595 buf[0] = htonl(dma_high); /* confirm addr MSW */
596 buf[1] = htonl(dma_low); /* confirm addr LSW */
597 buf[2] = htonl(MYRI10GE_NO_CONFIRM_DATA); /* confirm data */
598
599 /* FIX: All newest firmware should un-protect the bottom of
600 * the sram before handoff. However, the very first interfaces
601 * do not. Therefore the handoff copy must skip the first 8 bytes
602 */
603 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
604 buf[4] = htonl(size - 8); /* length of code */
605 buf[5] = htonl(8); /* where to copy to */
606 buf[6] = htonl(0); /* where to jump to */
607
608 submit = mgp->sram + 0xfc0000;
609
610 myri10ge_pio_copy(submit, &buf, sizeof(buf));
611 mb();
612 msleep(1);
613 mb();
614 i = 0;
615 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20) {
616 msleep(1);
617 i++;
618 }
619 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
620 dev_err(&mgp->pdev->dev, "handoff failed\n");
621 return -ENXIO;
622 }
623 dev_info(&mgp->pdev->dev, "handoff confirmed\n");
624 myri10ge_dummy_rdma(mgp, mgp->tx.boundary != 4096);
625
626 return 0;
627}
628
629static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
630{
631 struct myri10ge_cmd cmd;
632 int status;
633
634 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
635 | (addr[2] << 8) | addr[3]);
636
637 cmd.data1 = ((addr[4] << 8) | (addr[5]));
638
639 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
640 return status;
641}
642
643static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
644{
645 struct myri10ge_cmd cmd;
646 int status, ctl;
647
648 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
649 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
650
651 if (status) {
652 printk(KERN_ERR
653 "myri10ge: %s: Failed to set flow control mode\n",
654 mgp->dev->name);
655 return status;
656 }
657 mgp->pause = pause;
658 return 0;
659}
660
661static void
662myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
663{
664 struct myri10ge_cmd cmd;
665 int status, ctl;
666
667 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
668 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
669 if (status)
670 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
671 mgp->dev->name);
672}
673
674static int myri10ge_reset(struct myri10ge_priv *mgp)
675{
676 struct myri10ge_cmd cmd;
677 int status;
678 size_t bytes;
679 u32 len;
680
681 /* try to send a reset command to the card to see if it
682 * is alive */
683 memset(&cmd, 0, sizeof(cmd));
684 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
685 if (status != 0) {
686 dev_err(&mgp->pdev->dev, "failed reset\n");
687 return -ENXIO;
688 }
689
690 /* Now exchange information about interrupts */
691
692 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
693 memset(mgp->rx_done.entry, 0, bytes);
694 cmd.data0 = (u32) bytes;
695 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
696 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
697 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
698 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0);
699
700 status |=
701 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
702 mgp->irq_claim = (__iomem u32 *) (mgp->sram + cmd.data0);
703 if (!mgp->msi_enabled) {
704 status |= myri10ge_send_cmd
705 (mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET, &cmd, 0);
706 mgp->irq_deassert = (__iomem u32 *) (mgp->sram + cmd.data0);
707
708 }
709 status |= myri10ge_send_cmd
710 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
711 mgp->intr_coal_delay_ptr = (__iomem u32 *) (mgp->sram + cmd.data0);
712 if (status != 0) {
713 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
714 return status;
715 }
716 __raw_writel(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
717
718 /* Run a small DMA test.
719 * The magic multipliers to the length tell the firmware
720 * to do DMA read, write, or read+write tests. The
721 * results are returned in cmd.data0. The upper 16
722 * bits or the return is the number of transfers completed.
723 * The lower 16 bits is the time in 0.5us ticks that the
724 * transfers took to complete.
725 */
726
727 len = mgp->tx.boundary;
728
729 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
730 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
731 cmd.data2 = len * 0x10000;
732 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
733 if (status == 0)
734 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) /
735 (cmd.data0 & 0xffff);
736 else
737 dev_warn(&mgp->pdev->dev, "DMA read benchmark failed: %d\n",
738 status);
739 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
740 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
741 cmd.data2 = len * 0x1;
742 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
743 if (status == 0)
744 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) /
745 (cmd.data0 & 0xffff);
746 else
747 dev_warn(&mgp->pdev->dev, "DMA write benchmark failed: %d\n",
748 status);
749
750 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
751 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
752 cmd.data2 = len * 0x10001;
753 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
754 if (status == 0)
755 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
756 (cmd.data0 & 0xffff);
757 else
758 dev_warn(&mgp->pdev->dev,
759 "DMA read/write benchmark failed: %d\n", status);
760
761 memset(mgp->rx_done.entry, 0, bytes);
762
763 /* reset mcp/driver shared state back to 0 */
764 mgp->tx.req = 0;
765 mgp->tx.done = 0;
766 mgp->tx.pkt_start = 0;
767 mgp->tx.pkt_done = 0;
768 mgp->rx_big.cnt = 0;
769 mgp->rx_small.cnt = 0;
770 mgp->rx_done.idx = 0;
771 mgp->rx_done.cnt = 0;
772 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
773 myri10ge_change_promisc(mgp, 0, 0);
774 myri10ge_change_pause(mgp, mgp->pause);
775 return status;
776}
777
778static inline void
779myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
780 struct mcp_kreq_ether_recv *src)
781{
782 u32 low;
783
784 low = src->addr_low;
785 src->addr_low = DMA_32BIT_MASK;
786 myri10ge_pio_copy(dst, src, 8 * sizeof(*src));
787 mb();
788 src->addr_low = low;
789 __raw_writel(low, &dst->addr_low);
790 mb();
791}
792
793/*
b10c0668 794 * Set of routines to get a new receive buffer. Any buffer which
0da34b6d
BG		 795 * crosses a 4KB boundary must start on a 4KB boundary due to PCIe
796 * wdma restrictions. We also try to align any smaller allocation to
797 * at least a 16 byte boundary for efficiency. We assume the linux
798 * memory allocator works by powers of 2, and will not return memory
799 * smaller than 2KB which crosses a 4KB boundary. If it does, we fall
800 * back to allocating 2x as much space as required.
801 *
802 * We intend to replace large (>4KB) skb allocations by using
803 * pages directly and building a fraglist in the near future.
804 */
805
806static inline struct sk_buff *myri10ge_alloc_big(int bytes)
807{
808 struct sk_buff *skb;
809 unsigned long data, roundup;
810
811 skb = dev_alloc_skb(bytes + 4096 + MXGEFW_PAD);
812 if (skb == NULL)
813 return NULL;
814
815 /* Correct skb->truesize so that socket buffer
816 * accounting is not confused the rounding we must
817 * do to satisfy alignment constraints.
818 */
819 skb->truesize -= 4096;
820
821 data = (unsigned long)(skb->data);
822 roundup = (-data) & (4095);
823 skb_reserve(skb, roundup);
824 return skb;
825}
826
827/* Allocate 2x as much space as required and use whichever portion
828 * does not cross a 4KB boundary */
829static inline struct sk_buff *myri10ge_alloc_small_safe(unsigned int bytes)
830{
831 struct sk_buff *skb;
832 unsigned long data, boundary;
833
834 skb = dev_alloc_skb(2 * (bytes + MXGEFW_PAD) - 1);
835 if (unlikely(skb == NULL))
836 return NULL;
837
838 /* Correct skb->truesize so that socket buffer
839 * accounting is not confused the rounding we must
840 * do to satisfy alignment constraints.
841 */
842 skb->truesize -= bytes + MXGEFW_PAD;
843
844 data = (unsigned long)(skb->data);
845 boundary = (data + 4095UL) & ~4095UL;
846 if ((boundary - data) >= (bytes + MXGEFW_PAD))
847 return skb;
848
849 skb_reserve(skb, boundary - data);
850 return skb;
851}
852
853/* Allocate just enough space, and verify that the allocated
854 * space does not cross a 4KB boundary */
855static inline struct sk_buff *myri10ge_alloc_small(int bytes)
856{
857 struct sk_buff *skb;
858 unsigned long roundup, data, end;
859
860 skb = dev_alloc_skb(bytes + 16 + MXGEFW_PAD);
861 if (unlikely(skb == NULL))
862 return NULL;
863
864 /* Round allocated buffer to 16 byte boundary */
865 data = (unsigned long)(skb->data);
866 roundup = (-data) & 15UL;
867 skb_reserve(skb, roundup);
868 /* Verify that the data buffer does not cross a page boundary */
869 data = (unsigned long)(skb->data);
870 end = data + bytes + MXGEFW_PAD - 1;
871 if (unlikely(((end >> 12) != (data >> 12)) && (data & 4095UL))) {
872 printk(KERN_NOTICE
873 "myri10ge_alloc_small: small skb crossed 4KB boundary\n");
874 myri10ge_skb_cross_4k = 1;
875 dev_kfree_skb_any(skb);
876 skb = myri10ge_alloc_small_safe(bytes);
877 }
878 return skb;
879}
880
881static inline int
882myri10ge_getbuf(struct myri10ge_rx_buf *rx, struct pci_dev *pdev, int bytes,
883 int idx)
884{
885 struct sk_buff *skb;
886 dma_addr_t bus;
887 int len, retval = 0;
888
889 bytes += VLAN_HLEN; /* account for 802.1q vlan tag */
890
891 if ((bytes + MXGEFW_PAD) > (4096 - 16) /* linux overhead */ )
892 skb = myri10ge_alloc_big(bytes);
893 else if (myri10ge_skb_cross_4k)
894 skb = myri10ge_alloc_small_safe(bytes);
895 else
896 skb = myri10ge_alloc_small(bytes);
897
898 if (unlikely(skb == NULL)) {
899 rx->alloc_fail++;
900 retval = -ENOBUFS;
901 goto done;
902 }
903
904 /* set len so that it only covers the area we
905 * need mapped for DMA */
906 len = bytes + MXGEFW_PAD;
907
908 bus = pci_map_single(pdev, skb->data, len, PCI_DMA_FROMDEVICE);
909 rx->info[idx].skb = skb;
910 pci_unmap_addr_set(&rx->info[idx], bus, bus);
911 pci_unmap_len_set(&rx->info[idx], len, len);
912 rx->shadow[idx].addr_low = htonl(MYRI10GE_LOWPART_TO_U32(bus));
913 rx->shadow[idx].addr_high = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
914
915done:
916 /* copy 8 descriptors (64-bytes) to the mcp at a time */
917 if ((idx & 7) == 7) {
918 if (rx->wc_fifo == NULL)
919 myri10ge_submit_8rx(&rx->lanai[idx - 7],
920 &rx->shadow[idx - 7]);
921 else {
922 mb();
923 myri10ge_pio_copy(rx->wc_fifo,
924 &rx->shadow[idx - 7], 64);
925 }
926 }
927 return retval;
928}
929
930static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, u16 hw_csum)
931{
932 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
933
934 if ((skb->protocol == ntohs(ETH_P_8021Q)) &&
935 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
936 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
937 skb->csum = hw_csum;
938 skb->ip_summed = CHECKSUM_HW;
939 }
940}
941
942static inline unsigned long
943myri10ge_rx_done(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
944 int bytes, int len, int csum)
945{
946 dma_addr_t bus;
947 struct sk_buff *skb;
948 int idx, unmap_len;
949
950 idx = rx->cnt & rx->mask;
951 rx->cnt++;
952
953 /* save a pointer to the received skb */
954 skb = rx->info[idx].skb;
955 bus = pci_unmap_addr(&rx->info[idx], bus);
956 unmap_len = pci_unmap_len(&rx->info[idx], len);
957
958 /* try to replace the received skb */
959 if (myri10ge_getbuf(rx, mgp->pdev, bytes, idx)) {
960 /* drop the frame -- the old skbuf is re-cycled */
961 mgp->stats.rx_dropped += 1;
962 return 0;
963 }
964
965 /* unmap the recvd skb */
966 pci_unmap_single(mgp->pdev, bus, unmap_len, PCI_DMA_FROMDEVICE);
967
968 /* mcp implicitly skips 1st bytes so that packet is properly
969 * aligned */
970 skb_reserve(skb, MXGEFW_PAD);
971
972 /* set the length of the frame */
973 skb_put(skb, len);
974
975 skb->protocol = eth_type_trans(skb, mgp->dev);
976 skb->dev = mgp->dev;
977 if (mgp->csum_flag) {
978 if ((skb->protocol == ntohs(ETH_P_IP)) ||
979 (skb->protocol == ntohs(ETH_P_IPV6))) {
980 skb->csum = ntohs((u16) csum);
981 skb->ip_summed = CHECKSUM_HW;
982 } else
983 myri10ge_vlan_ip_csum(skb, ntohs((u16) csum));
984 }
985
986 netif_receive_skb(skb);
987 mgp->dev->last_rx = jiffies;
988 return 1;
989}
990
991static inline void myri10ge_tx_done(struct myri10ge_priv *mgp, int mcp_index)
992{
993 struct pci_dev *pdev = mgp->pdev;
994 struct myri10ge_tx_buf *tx = &mgp->tx;
995 struct sk_buff *skb;
996 int idx, len;
997 int limit = 0;
998
999 while (tx->pkt_done != mcp_index) {
1000 idx = tx->done & tx->mask;
1001 skb = tx->info[idx].skb;
1002
1003 /* Mark as free */
1004 tx->info[idx].skb = NULL;
1005 if (tx->info[idx].last) {
1006 tx->pkt_done++;
1007 tx->info[idx].last = 0;
1008 }
1009 tx->done++;
1010 len = pci_unmap_len(&tx->info[idx], len);
1011 pci_unmap_len_set(&tx->info[idx], len, 0);
1012 if (skb) {
1013 mgp->stats.tx_bytes += skb->len;
1014 mgp->stats.tx_packets++;
1015 dev_kfree_skb_irq(skb);
1016 if (len)
1017 pci_unmap_single(pdev,
1018 pci_unmap_addr(&tx->info[idx],
1019 bus), len,
1020 PCI_DMA_TODEVICE);
1021 } else {
1022 if (len)
1023 pci_unmap_page(pdev,
1024 pci_unmap_addr(&tx->info[idx],
1025 bus), len,
1026 PCI_DMA_TODEVICE);
1027 }
1028
1029 /* limit potential for livelock by only handling
1030 * 2 full tx rings per call */
1031 if (unlikely(++limit > 2 * tx->mask))
1032 break;
1033 }
1034 /* start the queue if we've stopped it */
1035 if (netif_queue_stopped(mgp->dev)
1036 && tx->req - tx->done < (tx->mask >> 1)) {
1037 mgp->wake_queue++;
1038 netif_wake_queue(mgp->dev);
1039 }
1040}
1041
1042static inline void myri10ge_clean_rx_done(struct myri10ge_priv *mgp, int *limit)
1043{
1044 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1045 unsigned long rx_bytes = 0;
1046 unsigned long rx_packets = 0;
1047 unsigned long rx_ok;
1048
1049 int idx = rx_done->idx;
1050 int cnt = rx_done->cnt;
1051 u16 length;
1052 u16 checksum;
1053
1054 while (rx_done->entry[idx].length != 0 && *limit != 0) {
1055 length = ntohs(rx_done->entry[idx].length);
1056 rx_done->entry[idx].length = 0;
1057 checksum = ntohs(rx_done->entry[idx].checksum);
1058 if (length <= mgp->small_bytes)
1059 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_small,
1060 mgp->small_bytes,
1061 length, checksum);
1062 else
1063 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_big,
1064 mgp->dev->mtu + ETH_HLEN,
1065 length, checksum);
1066 rx_packets += rx_ok;
1067 rx_bytes += rx_ok * (unsigned long)length;
1068 cnt++;
1069 idx = cnt & (myri10ge_max_intr_slots - 1);
1070
1071 /* limit potential for livelock by only handling a
1072 * limited number of frames. */
1073 (*limit)--;
1074 }
1075 rx_done->idx = idx;
1076 rx_done->cnt = cnt;
1077 mgp->stats.rx_packets += rx_packets;
1078 mgp->stats.rx_bytes += rx_bytes;
1079}
1080
1081static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1082{
1083 struct mcp_irq_data *stats = mgp->fw_stats;
1084
1085 if (unlikely(stats->stats_updated)) {
1086 if (mgp->link_state != stats->link_up) {
1087 mgp->link_state = stats->link_up;
1088 if (mgp->link_state) {
1089 printk(KERN_INFO "myri10ge: %s: link up\n",
1090 mgp->dev->name);
1091 netif_carrier_on(mgp->dev);
1092 } else {
1093 printk(KERN_INFO "myri10ge: %s: link down\n",
1094 mgp->dev->name);
1095 netif_carrier_off(mgp->dev);
1096 }
1097 }
1098 if (mgp->rdma_tags_available !=
1099 ntohl(mgp->fw_stats->rdma_tags_available)) {
1100 mgp->rdma_tags_available =
1101 ntohl(mgp->fw_stats->rdma_tags_available);
1102 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1103 "%d tags left\n", mgp->dev->name,
1104 mgp->rdma_tags_available);
1105 }
1106 mgp->down_cnt += stats->link_down;
1107 if (stats->link_down)
1108 wake_up(&mgp->down_wq);
1109 }
1110}
1111
1112static int myri10ge_poll(struct net_device *netdev, int *budget)
1113{
1114 struct myri10ge_priv *mgp = netdev_priv(netdev);
1115 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1116 int limit, orig_limit, work_done;
1117
1118 /* process as many rx events as NAPI will allow */
1119 limit = min(*budget, netdev->quota);
1120 orig_limit = limit;
1121 myri10ge_clean_rx_done(mgp, &limit);
1122 work_done = orig_limit - limit;
1123 *budget -= work_done;
1124 netdev->quota -= work_done;
1125
1126 if (rx_done->entry[rx_done->idx].length == 0 || !netif_running(netdev)) {
1127 netif_rx_complete(netdev);
1128 __raw_writel(htonl(3), mgp->irq_claim);
1129 return 0;
1130 }
1131 return 1;
1132}
1133
1134static irqreturn_t myri10ge_intr(int irq, void *arg, struct pt_regs *regs)
1135{
1136 struct myri10ge_priv *mgp = arg;
1137 struct mcp_irq_data *stats = mgp->fw_stats;
1138 struct myri10ge_tx_buf *tx = &mgp->tx;
1139 u32 send_done_count;
1140 int i;
1141
1142 /* make sure it is our IRQ, and that the DMA has finished */
1143 if (unlikely(!stats->valid))
1144 return (IRQ_NONE);
1145
1146 /* low bit indicates receives are present, so schedule
1147 * napi poll handler */
1148 if (stats->valid & 1)
1149 netif_rx_schedule(mgp->dev);
1150
1151 if (!mgp->msi_enabled) {
1152 __raw_writel(0, mgp->irq_deassert);
1153 if (!myri10ge_deassert_wait)
1154 stats->valid = 0;
1155 mb();
1156 } else
1157 stats->valid = 0;
1158
1159 /* Wait for IRQ line to go low, if using INTx */
1160 i = 0;
1161 while (1) {
1162 i++;
1163 /* check for transmit completes and receives */
1164 send_done_count = ntohl(stats->send_done_count);
1165 if (send_done_count != tx->pkt_done)
1166 myri10ge_tx_done(mgp, (int)send_done_count);
1167 if (unlikely(i > myri10ge_max_irq_loops)) {
1168 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1169 mgp->dev->name);
1170 stats->valid = 0;
1171 schedule_work(&mgp->watchdog_work);
1172 }
1173 if (likely(stats->valid == 0))
1174 break;
1175 cpu_relax();
1176 barrier();
1177 }
1178
1179 myri10ge_check_statblock(mgp);
1180
1181 __raw_writel(htonl(3), mgp->irq_claim + 1);
1182 return (IRQ_HANDLED);
1183}
1184
1185static int
1186myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1187{
1188 cmd->autoneg = AUTONEG_DISABLE;
1189 cmd->speed = SPEED_10000;
1190 cmd->duplex = DUPLEX_FULL;
1191 return 0;
1192}
1193
1194static void
1195myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1196{
1197 struct myri10ge_priv *mgp = netdev_priv(netdev);
1198
1199 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1200 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1201 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1202 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1203}
1204
1205static int
1206myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1207{
1208 struct myri10ge_priv *mgp = netdev_priv(netdev);
1209 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1210 return 0;
1211}
1212
1213static int
1214myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1215{
1216 struct myri10ge_priv *mgp = netdev_priv(netdev);
1217
1218 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
1219 __raw_writel(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1220 return 0;
1221}
1222
1223static void
1224myri10ge_get_pauseparam(struct net_device *netdev,
1225 struct ethtool_pauseparam *pause)
1226{
1227 struct myri10ge_priv *mgp = netdev_priv(netdev);
1228
1229 pause->autoneg = 0;
1230 pause->rx_pause = mgp->pause;
1231 pause->tx_pause = mgp->pause;
1232}
1233
1234static int
1235myri10ge_set_pauseparam(struct net_device *netdev,
1236 struct ethtool_pauseparam *pause)
1237{
1238 struct myri10ge_priv *mgp = netdev_priv(netdev);
1239
1240 if (pause->tx_pause != mgp->pause)
1241 return myri10ge_change_pause(mgp, pause->tx_pause);
1242 if (pause->rx_pause != mgp->pause)
1243 return myri10ge_change_pause(mgp, pause->tx_pause);
1244 if (pause->autoneg != 0)
1245 return -EINVAL;
1246 return 0;
1247}
1248
1249static void
1250myri10ge_get_ringparam(struct net_device *netdev,
1251 struct ethtool_ringparam *ring)
1252{
1253 struct myri10ge_priv *mgp = netdev_priv(netdev);
1254
1255 ring->rx_mini_max_pending = mgp->rx_small.mask + 1;
1256 ring->rx_max_pending = mgp->rx_big.mask + 1;
1257 ring->rx_jumbo_max_pending = 0;
1258 ring->tx_max_pending = mgp->rx_small.mask + 1;
1259 ring->rx_mini_pending = ring->rx_mini_max_pending;
1260 ring->rx_pending = ring->rx_max_pending;
1261 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1262 ring->tx_pending = ring->tx_max_pending;
1263}
1264
1265static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1266{
1267 struct myri10ge_priv *mgp = netdev_priv(netdev);
1268 if (mgp->csum_flag)
1269 return 1;
1270 else
1271 return 0;
1272}
1273
1274static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1275{
1276 struct myri10ge_priv *mgp = netdev_priv(netdev);
1277 if (csum_enabled)
1278 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1279 else
1280 mgp->csum_flag = 0;
1281 return 0;
1282}
1283
1284static const char myri10ge_gstrings_stats[][ETH_GSTRING_LEN] = {
1285 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1286 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1287 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1288 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1289 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1290 "tx_heartbeat_errors", "tx_window_errors",
1291 /* device-specific stats */
1292 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1293 "serial_number", "tx_pkt_start", "tx_pkt_done",
1294 "tx_req", "tx_done", "rx_small_cnt", "rx_big_cnt",
1295 "wake_queue", "stop_queue", "watchdog_resets", "tx_linearized",
1296 "link_up", "dropped_link_overflow", "dropped_link_error_or_filtered",
1297 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1298 "dropped_no_big_buffer"
1299};
1300
1301#define MYRI10GE_NET_STATS_LEN 21
1302#define MYRI10GE_STATS_LEN sizeof(myri10ge_gstrings_stats) / ETH_GSTRING_LEN
1303
1304static void
1305myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1306{
1307 switch (stringset) {
1308 case ETH_SS_STATS:
1309 memcpy(data, *myri10ge_gstrings_stats,
1310 sizeof(myri10ge_gstrings_stats));
1311 break;
1312 }
1313}
1314
1315static int myri10ge_get_stats_count(struct net_device *netdev)
1316{
1317 return MYRI10GE_STATS_LEN;
1318}
1319
1320static void
1321myri10ge_get_ethtool_stats(struct net_device *netdev,
1322 struct ethtool_stats *stats, u64 * data)
1323{
1324 struct myri10ge_priv *mgp = netdev_priv(netdev);
1325 int i;
1326
1327 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1328 data[i] = ((unsigned long *)&mgp->stats)[i];
1329
1330 data[i++] = (unsigned int)mgp->read_dma;
1331 data[i++] = (unsigned int)mgp->write_dma;
1332 data[i++] = (unsigned int)mgp->read_write_dma;
1333 data[i++] = (unsigned int)mgp->serial_number;
1334 data[i++] = (unsigned int)mgp->tx.pkt_start;
1335 data[i++] = (unsigned int)mgp->tx.pkt_done;
1336 data[i++] = (unsigned int)mgp->tx.req;
1337 data[i++] = (unsigned int)mgp->tx.done;
1338 data[i++] = (unsigned int)mgp->rx_small.cnt;
1339 data[i++] = (unsigned int)mgp->rx_big.cnt;
1340 data[i++] = (unsigned int)mgp->wake_queue;
1341 data[i++] = (unsigned int)mgp->stop_queue;
1342 data[i++] = (unsigned int)mgp->watchdog_resets;
1343 data[i++] = (unsigned int)mgp->tx_linearized;
1344 data[i++] = (unsigned int)ntohl(mgp->fw_stats->link_up);
1345 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_link_overflow);
1346 data[i++] =
1347 (unsigned int)ntohl(mgp->fw_stats->dropped_link_error_or_filtered);
1348 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_runt);
1349 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_overrun);
1350 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_small_buffer);
1351 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_big_buffer);
1352}
1353
1354static struct ethtool_ops myri10ge_ethtool_ops = {
1355 .get_settings = myri10ge_get_settings,
1356 .get_drvinfo = myri10ge_get_drvinfo,
1357 .get_coalesce = myri10ge_get_coalesce,
1358 .set_coalesce = myri10ge_set_coalesce,
1359 .get_pauseparam = myri10ge_get_pauseparam,
1360 .set_pauseparam = myri10ge_set_pauseparam,
1361 .get_ringparam = myri10ge_get_ringparam,
1362 .get_rx_csum = myri10ge_get_rx_csum,
1363 .set_rx_csum = myri10ge_set_rx_csum,
1364 .get_tx_csum = ethtool_op_get_tx_csum,
b10c0668 1365 .set_tx_csum = ethtool_op_set_tx_hw_csum,
0da34b6d
BG		 1366 .get_sg = ethtool_op_get_sg,
1367 .set_sg = ethtool_op_set_sg,
1368#ifdef NETIF_F_TSO
1369 .get_tso = ethtool_op_get_tso,
1370 .set_tso = ethtool_op_set_tso,
1371#endif
1372 .get_strings = myri10ge_get_strings,
1373 .get_stats_count = myri10ge_get_stats_count,
1374 .get_ethtool_stats = myri10ge_get_ethtool_stats
1375};
1376
1377static int myri10ge_allocate_rings(struct net_device *dev)
1378{
1379 struct myri10ge_priv *mgp;
1380 struct myri10ge_cmd cmd;
1381 int tx_ring_size, rx_ring_size;
1382 int tx_ring_entries, rx_ring_entries;
1383 int i, status;
1384 size_t bytes;
1385
1386 mgp = netdev_priv(dev);
1387
1388 /* get ring sizes */
1389
1390 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1391 tx_ring_size = cmd.data0;
1392 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
1393 rx_ring_size = cmd.data0;
1394
1395 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1396 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1397 mgp->tx.mask = tx_ring_entries - 1;
1398 mgp->rx_small.mask = mgp->rx_big.mask = rx_ring_entries - 1;
1399
1400 /* allocate the host shadow rings */
1401
1402 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1403 * sizeof(*mgp->tx.req_list);
1404 mgp->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1405 if (mgp->tx.req_bytes == NULL)
1406 goto abort_with_nothing;
1407
1408 /* ensure req_list entries are aligned to 8 bytes */
1409 mgp->tx.req_list = (struct mcp_kreq_ether_send *)
1410 ALIGN((unsigned long)mgp->tx.req_bytes, 8);
1411
1412 bytes = rx_ring_entries * sizeof(*mgp->rx_small.shadow);
1413 mgp->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1414 if (mgp->rx_small.shadow == NULL)
1415 goto abort_with_tx_req_bytes;
1416
1417 bytes = rx_ring_entries * sizeof(*mgp->rx_big.shadow);
1418 mgp->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1419 if (mgp->rx_big.shadow == NULL)
1420 goto abort_with_rx_small_shadow;
1421
1422 /* allocate the host info rings */
1423
1424 bytes = tx_ring_entries * sizeof(*mgp->tx.info);
1425 mgp->tx.info = kzalloc(bytes, GFP_KERNEL);
1426 if (mgp->tx.info == NULL)
1427 goto abort_with_rx_big_shadow;
1428
1429 bytes = rx_ring_entries * sizeof(*mgp->rx_small.info);
1430 mgp->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1431 if (mgp->rx_small.info == NULL)
1432 goto abort_with_tx_info;
1433
1434 bytes = rx_ring_entries * sizeof(*mgp->rx_big.info);
1435 mgp->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1436 if (mgp->rx_big.info == NULL)
1437 goto abort_with_rx_small_info;
1438
1439 /* Fill the receive rings */
1440
1441 for (i = 0; i <= mgp->rx_small.mask; i++) {
1442 status = myri10ge_getbuf(&mgp->rx_small, mgp->pdev,
1443 mgp->small_bytes, i);
1444 if (status) {
1445 printk(KERN_ERR
1446 "myri10ge: %s: alloced only %d small bufs\n",
1447 dev->name, i);
1448 goto abort_with_rx_small_ring;
1449 }
1450 }
1451
1452 for (i = 0; i <= mgp->rx_big.mask; i++) {
1453 status =
1454 myri10ge_getbuf(&mgp->rx_big, mgp->pdev,
1455 dev->mtu + ETH_HLEN, i);
1456 if (status) {
1457 printk(KERN_ERR
1458 "myri10ge: %s: alloced only %d big bufs\n",
1459 dev->name, i);
1460 goto abort_with_rx_big_ring;
1461 }
1462 }
1463
1464 return 0;
1465
1466abort_with_rx_big_ring:
1467 for (i = 0; i <= mgp->rx_big.mask; i++) {
1468 if (mgp->rx_big.info[i].skb != NULL)
1469 dev_kfree_skb_any(mgp->rx_big.info[i].skb);
1470 if (pci_unmap_len(&mgp->rx_big.info[i], len))
1471 pci_unmap_single(mgp->pdev,
1472 pci_unmap_addr(&mgp->rx_big.info[i],
1473 bus),
1474 pci_unmap_len(&mgp->rx_big.info[i],
1475 len),
1476 PCI_DMA_FROMDEVICE);
1477 }
1478
1479abort_with_rx_small_ring:
1480 for (i = 0; i <= mgp->rx_small.mask; i++) {
1481 if (mgp->rx_small.info[i].skb != NULL)
1482 dev_kfree_skb_any(mgp->rx_small.info[i].skb);
1483 if (pci_unmap_len(&mgp->rx_small.info[i], len))
1484 pci_unmap_single(mgp->pdev,
1485 pci_unmap_addr(&mgp->rx_small.info[i],
1486 bus),
1487 pci_unmap_len(&mgp->rx_small.info[i],
1488 len),
1489 PCI_DMA_FROMDEVICE);
1490 }
1491 kfree(mgp->rx_big.info);
1492
1493abort_with_rx_small_info:
1494 kfree(mgp->rx_small.info);
1495
1496abort_with_tx_info:
1497 kfree(mgp->tx.info);
1498
1499abort_with_rx_big_shadow:
1500 kfree(mgp->rx_big.shadow);
1501
1502abort_with_rx_small_shadow:
1503 kfree(mgp->rx_small.shadow);
1504
1505abort_with_tx_req_bytes:
1506 kfree(mgp->tx.req_bytes);
1507 mgp->tx.req_bytes = NULL;
1508 mgp->tx.req_list = NULL;
1509
1510abort_with_nothing:
1511 return status;
1512}
1513
1514static void myri10ge_free_rings(struct net_device *dev)
1515{
1516 struct myri10ge_priv *mgp;
1517 struct sk_buff *skb;
1518 struct myri10ge_tx_buf *tx;
1519 int i, len, idx;
1520
1521 mgp = netdev_priv(dev);
1522
1523 for (i = 0; i <= mgp->rx_big.mask; i++) {
1524 if (mgp->rx_big.info[i].skb != NULL)
1525 dev_kfree_skb_any(mgp->rx_big.info[i].skb);
1526 if (pci_unmap_len(&mgp->rx_big.info[i], len))
1527 pci_unmap_single(mgp->pdev,
1528 pci_unmap_addr(&mgp->rx_big.info[i],
1529 bus),
1530 pci_unmap_len(&mgp->rx_big.info[i],
1531 len),
1532 PCI_DMA_FROMDEVICE);
1533 }
1534
1535 for (i = 0; i <= mgp->rx_small.mask; i++) {
1536 if (mgp->rx_small.info[i].skb != NULL)
1537 dev_kfree_skb_any(mgp->rx_small.info[i].skb);
1538 if (pci_unmap_len(&mgp->rx_small.info[i], len))
1539 pci_unmap_single(mgp->pdev,
1540 pci_unmap_addr(&mgp->rx_small.info[i],
1541 bus),
1542 pci_unmap_len(&mgp->rx_small.info[i],
1543 len),
1544 PCI_DMA_FROMDEVICE);
1545 }
1546
1547 tx = &mgp->tx;
1548 while (tx->done != tx->req) {
1549 idx = tx->done & tx->mask;
1550 skb = tx->info[idx].skb;
1551
1552 /* Mark as free */
1553 tx->info[idx].skb = NULL;
1554 tx->done++;
1555 len = pci_unmap_len(&tx->info[idx], len);
1556 pci_unmap_len_set(&tx->info[idx], len, 0);
1557 if (skb) {
1558 mgp->stats.tx_dropped++;
1559 dev_kfree_skb_any(skb);
1560 if (len)
1561 pci_unmap_single(mgp->pdev,
1562 pci_unmap_addr(&tx->info[idx],
1563 bus), len,
1564 PCI_DMA_TODEVICE);
1565 } else {
1566 if (len)
1567 pci_unmap_page(mgp->pdev,
1568 pci_unmap_addr(&tx->info[idx],
1569 bus), len,
1570 PCI_DMA_TODEVICE);
1571 }
1572 }
1573 kfree(mgp->rx_big.info);
1574
1575 kfree(mgp->rx_small.info);
1576
1577 kfree(mgp->tx.info);
1578
1579 kfree(mgp->rx_big.shadow);
1580
1581 kfree(mgp->rx_small.shadow);
1582
1583 kfree(mgp->tx.req_bytes);
1584 mgp->tx.req_bytes = NULL;
1585 mgp->tx.req_list = NULL;
1586}
1587
1588static int myri10ge_open(struct net_device *dev)
1589{
1590 struct myri10ge_priv *mgp;
1591 struct myri10ge_cmd cmd;
1592 int status, big_pow2;
1593
1594 mgp = netdev_priv(dev);
1595
1596 if (mgp->running != MYRI10GE_ETH_STOPPED)
1597 return -EBUSY;
1598
1599 mgp->running = MYRI10GE_ETH_STARTING;
1600 status = myri10ge_reset(mgp);
1601 if (status != 0) {
1602 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
1603 mgp->running = MYRI10GE_ETH_STOPPED;
1604 return -ENXIO;
1605 }
1606
1607 /* decide what small buffer size to use. For good TCP rx
1608 * performance, it is important to not receive 1514 byte
1609 * frames into jumbo buffers, as it confuses the socket buffer
1610 * accounting code, leading to drops and erratic performance.
1611 */
1612
1613 if (dev->mtu <= ETH_DATA_LEN)
1614 mgp->small_bytes = 128; /* enough for a TCP header */
1615 else
1616 mgp->small_bytes = ETH_FRAME_LEN; /* enough for an ETH_DATA_LEN frame */
1617
1618 /* Override the small buffer size? */
1619 if (myri10ge_small_bytes > 0)
1620 mgp->small_bytes = myri10ge_small_bytes;
1621
1622 /* If the user sets an obscenely small MTU, adjust the small
1623 * bytes down to nearly nothing */
1624 if (mgp->small_bytes >= (dev->mtu + ETH_HLEN))
1625 mgp->small_bytes = 64;
1626
1627 /* get the lanai pointers to the send and receive rings */
1628
1629 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
1630 mgp->tx.lanai =
1631 (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0);
1632
1633 status |=
1634 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0);
1635 mgp->rx_small.lanai =
1636 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1637
1638 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
1639 mgp->rx_big.lanai =
1640 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1641
1642 if (status != 0) {
1643 printk(KERN_ERR
1644 "myri10ge: %s: failed to get ring sizes or locations\n",
1645 dev->name);
1646 mgp->running = MYRI10GE_ETH_STOPPED;
1647 return -ENXIO;
1648 }
1649
1650 if (mgp->mtrr >= 0) {
1651 mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + 0x200000;
1652 mgp->rx_small.wc_fifo = (u8 __iomem *) mgp->sram + 0x300000;
1653 mgp->rx_big.wc_fifo = (u8 __iomem *) mgp->sram + 0x340000;
1654 } else {
1655 mgp->tx.wc_fifo = NULL;
1656 mgp->rx_small.wc_fifo = NULL;
1657 mgp->rx_big.wc_fifo = NULL;
1658 }
1659
1660 status = myri10ge_allocate_rings(dev);
1661 if (status != 0)
1662 goto abort_with_nothing;
1663
1664 /* Firmware needs the big buff size as a power of 2. Lie and
1665 * tell him the buffer is larger, because we only use 1
1666 * buffer/pkt, and the mtu will prevent overruns.
1667 */
1668 big_pow2 = dev->mtu + ETH_HLEN + MXGEFW_PAD;
1669 while ((big_pow2 & (big_pow2 - 1)) != 0)
1670 big_pow2++;
1671
1672 /* now give firmware buffers sizes, and MTU */
1673 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
1674 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
1675 cmd.data0 = mgp->small_bytes;
1676 status |=
1677 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
1678 cmd.data0 = big_pow2;
1679 status |=
1680 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
1681 if (status) {
1682 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
1683 dev->name);
1684 goto abort_with_rings;
1685 }
1686
1687 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->fw_stats_bus);
1688 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->fw_stats_bus);
1689 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA, &cmd, 0);
1690 if (status) {
1691 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n",
1692 dev->name);
1693 goto abort_with_rings;
1694 }
1695
1696 mgp->link_state = -1;
1697 mgp->rdma_tags_available = 15;
1698
1699 netif_poll_enable(mgp->dev); /* must happen prior to any irq */
1700
1701 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
1702 if (status) {
1703 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
1704 dev->name);
1705 goto abort_with_rings;
1706 }
1707
1708 mgp->wake_queue = 0;
1709 mgp->stop_queue = 0;
1710 mgp->running = MYRI10GE_ETH_RUNNING;
1711 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
1712 add_timer(&mgp->watchdog_timer);
1713 netif_wake_queue(dev);
1714 return 0;
1715
1716abort_with_rings:
1717 myri10ge_free_rings(dev);
1718
1719abort_with_nothing:
1720 mgp->running = MYRI10GE_ETH_STOPPED;
1721 return -ENOMEM;
1722}
1723
1724static int myri10ge_close(struct net_device *dev)
1725{
1726 struct myri10ge_priv *mgp;
1727 struct myri10ge_cmd cmd;
1728 int status, old_down_cnt;
1729
1730 mgp = netdev_priv(dev);
1731
1732 if (mgp->running != MYRI10GE_ETH_RUNNING)
1733 return 0;
1734
1735 if (mgp->tx.req_bytes == NULL)
1736 return 0;
1737
1738 del_timer_sync(&mgp->watchdog_timer);
1739 mgp->running = MYRI10GE_ETH_STOPPING;
1740 netif_poll_disable(mgp->dev);
1741 netif_carrier_off(dev);
1742 netif_stop_queue(dev);
1743 old_down_cnt = mgp->down_cnt;
1744 mb();
1745 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
1746 if (status)
1747 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
1748 dev->name);
1749
1750 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
1751 if (old_down_cnt == mgp->down_cnt)
1752 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
1753
1754 netif_tx_disable(dev);
1755
1756 myri10ge_free_rings(dev);
1757
1758 mgp->running = MYRI10GE_ETH_STOPPED;
1759 return 0;
1760}
1761
1762/* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1763 * backwards one at a time and handle ring wraps */
1764
1765static inline void
1766myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
1767 struct mcp_kreq_ether_send *src, int cnt)
1768{
1769 int idx, starting_slot;
1770 starting_slot = tx->req;
1771 while (cnt > 1) {
1772 cnt--;
1773 idx = (starting_slot + cnt) & tx->mask;
1774 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
1775 mb();
1776 }
1777}
1778
1779/*
1780 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1781 * at most 32 bytes at a time, so as to avoid involving the software
1782 * pio handler in the nic. We re-write the first segment's flags
1783 * to mark them valid only after writing the entire chain.
1784 */
1785
1786static inline void
1787myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
1788 int cnt)
1789{
1790 int idx, i;
1791 struct mcp_kreq_ether_send __iomem *dstp, *dst;
1792 struct mcp_kreq_ether_send *srcp;
1793 u8 last_flags;
1794
1795 idx = tx->req & tx->mask;
1796
1797 last_flags = src->flags;
1798 src->flags = 0;
1799 mb();
1800 dst = dstp = &tx->lanai[idx];
1801 srcp = src;
1802
1803 if ((idx + cnt) < tx->mask) {
1804 for (i = 0; i < (cnt - 1); i += 2) {
1805 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
1806 mb(); /* force write every 32 bytes */
1807 srcp += 2;
1808 dstp += 2;
1809 }
1810 } else {
1811 /* submit all but the first request, and ensure
1812 * that it is submitted below */
1813 myri10ge_submit_req_backwards(tx, src, cnt);
1814 i = 0;
1815 }
1816 if (i < cnt) {
1817 /* submit the first request */
1818 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
1819 mb(); /* barrier before setting valid flag */
1820 }
1821
1822 /* re-write the last 32-bits with the valid flags */
1823 src->flags = last_flags;
1824 __raw_writel(*((u32 *) src + 3), (u32 __iomem *) dst + 3);
1825 tx->req += cnt;
1826 mb();
1827}
1828
1829static inline void
1830myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
1831 struct mcp_kreq_ether_send *src, int cnt)
1832{
1833 tx->req += cnt;
1834 mb();
1835 while (cnt >= 4) {
1836 myri10ge_pio_copy(tx->wc_fifo, src, 64);
1837 mb();
1838 src += 4;
1839 cnt -= 4;
1840 }
1841 if (cnt > 0) {
1842 /* pad it to 64 bytes. The src is 64 bytes bigger than it
1843 * needs to be so that we don't overrun it */
1844 myri10ge_pio_copy(tx->wc_fifo + (cnt << 18), src, 64);
1845 mb();
1846 }
1847}
1848
1849/*
1850 * Transmit a packet. We need to split the packet so that a single
1851 * segment does not cross myri10ge->tx.boundary, so this makes segment
1852 * counting tricky. So rather than try to count segments up front, we
1853 * just give up if there are too few segments to hold a reasonably
1854 * fragmented packet currently available. If we run
1855 * out of segments while preparing a packet for DMA, we just linearize
1856 * it and try again.
1857 */
1858
1859static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
1860{
1861 struct myri10ge_priv *mgp = netdev_priv(dev);
1862 struct mcp_kreq_ether_send *req;
1863 struct myri10ge_tx_buf *tx = &mgp->tx;
1864 struct skb_frag_struct *frag;
1865 dma_addr_t bus;
1866 u32 low, high_swapped;
1867 unsigned int len;
1868 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
1869 u16 pseudo_hdr_offset, cksum_offset;
1870 int cum_len, seglen, boundary, rdma_count;
1871 u8 flags, odd_flag;
1872
1873again:
1874 req = tx->req_list;
1875 avail = tx->mask - 1 - (tx->req - tx->done);
1876
1877 mss = 0;
1878 max_segments = MXGEFW_MAX_SEND_DESC;
1879
1880#ifdef NETIF_F_TSO
1881 if (skb->len > (dev->mtu + ETH_HLEN)) {
1882 mss = skb_shinfo(skb)->tso_size;
1883 if (mss != 0)
1884 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
1885 }
1886#endif /*NETIF_F_TSO */
1887
1888 if ((unlikely(avail < max_segments))) {
1889 /* we are out of transmit resources */
1890 mgp->stop_queue++;
1891 netif_stop_queue(dev);
1892 return 1;
1893 }
1894
1895 /* Setup checksum offloading, if needed */
1896 cksum_offset = 0;
1897 pseudo_hdr_offset = 0;
1898 odd_flag = 0;
1899 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
1900 if (likely(skb->ip_summed == CHECKSUM_HW)) {
1901 cksum_offset = (skb->h.raw - skb->data);
1902 pseudo_hdr_offset = (skb->h.raw + skb->csum) - skb->data;
1903 /* If the headers are excessively large, then we must
1904 * fall back to a software checksum */
1905 if (unlikely(cksum_offset > 255 || pseudo_hdr_offset > 127)) {
1906 if (skb_checksum_help(skb, 0))
1907 goto drop;
1908 cksum_offset = 0;
1909 pseudo_hdr_offset = 0;
1910 } else {
1911 pseudo_hdr_offset = htons(pseudo_hdr_offset);
1912 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
1913 flags |= MXGEFW_FLAGS_CKSUM;
1914 }
1915 }
1916
1917 cum_len = 0;
1918
1919#ifdef NETIF_F_TSO
1920 if (mss) { /* TSO */
1921 /* this removes any CKSUM flag from before */
1922 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
1923
1924 /* negative cum_len signifies to the
1925 * send loop that we are still in the
1926 * header portion of the TSO packet.
1927 * TSO header must be at most 134 bytes long */
1928 cum_len = -((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
1929
1930 /* for TSO, pseudo_hdr_offset holds mss.
1931 * The firmware figures out where to put
1932 * the checksum by parsing the header. */
1933 pseudo_hdr_offset = htons(mss);
1934 } else
1935#endif /*NETIF_F_TSO */
1936 /* Mark small packets, and pad out tiny packets */
1937 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
1938 flags |= MXGEFW_FLAGS_SMALL;
1939
1940 /* pad frames to at least ETH_ZLEN bytes */
1941 if (unlikely(skb->len < ETH_ZLEN)) {
1942 skb = skb_padto(skb, ETH_ZLEN);
1943 if (skb == NULL) {
1944 /* The packet is gone, so we must
1945 * return 0 */
1946 mgp->stats.tx_dropped += 1;
1947 return 0;
1948 }
1949 /* adjust the len to account for the zero pad
1950 * so that the nic can know how long it is */
1951 skb->len = ETH_ZLEN;
1952 }
1953 }
1954
1955 /* map the skb for DMA */
1956 len = skb->len - skb->data_len;
1957 idx = tx->req & tx->mask;
1958 tx->info[idx].skb = skb;
1959 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
1960 pci_unmap_addr_set(&tx->info[idx], bus, bus);
1961 pci_unmap_len_set(&tx->info[idx], len, len);
1962
1963 frag_cnt = skb_shinfo(skb)->nr_frags;
1964 frag_idx = 0;
1965 count = 0;
1966 rdma_count = 0;
1967
1968 /* "rdma_count" is the number of RDMAs belonging to the
1969 * current packet BEFORE the current send request. For
1970 * non-TSO packets, this is equal to "count".
1971 * For TSO packets, rdma_count needs to be reset
1972 * to 0 after a segment cut.
1973 *
1974 * The rdma_count field of the send request is
1975 * the number of RDMAs of the packet starting at
1976 * that request. For TSO send requests with one ore more cuts
1977 * in the middle, this is the number of RDMAs starting
1978 * after the last cut in the request. All previous
1979 * segments before the last cut implicitly have 1 RDMA.
1980 *
1981 * Since the number of RDMAs is not known beforehand,
1982 * it must be filled-in retroactively - after each
1983 * segmentation cut or at the end of the entire packet.
1984 */
1985
1986 while (1) {
1987 /* Break the SKB or Fragment up into pieces which
1988 * do not cross mgp->tx.boundary */
1989 low = MYRI10GE_LOWPART_TO_U32(bus);
1990 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
1991 while (len) {
1992 u8 flags_next;
1993 int cum_len_next;
1994
1995 if (unlikely(count == max_segments))
1996 goto abort_linearize;
1997
1998 boundary = (low + tx->boundary) & ~(tx->boundary - 1);
1999 seglen = boundary - low;
2000 if (seglen > len)
2001 seglen = len;
2002 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2003 cum_len_next = cum_len + seglen;
2004#ifdef NETIF_F_TSO
2005 if (mss) { /* TSO */
2006 (req - rdma_count)->rdma_count = rdma_count + 1;
2007
2008 if (likely(cum_len >= 0)) { /* payload */
2009 int next_is_first, chop;
2010
2011 chop = (cum_len_next > mss);
2012 cum_len_next = cum_len_next % mss;
2013 next_is_first = (cum_len_next == 0);
2014 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2015 flags_next |= next_is_first *
2016 MXGEFW_FLAGS_FIRST;
2017 rdma_count |= -(chop | next_is_first);
2018 rdma_count += chop & !next_is_first;
2019 } else if (likely(cum_len_next >= 0)) { /* header ends */
2020 int small;
2021
2022 rdma_count = -1;
2023 cum_len_next = 0;
2024 seglen = -cum_len;
2025 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2026 flags_next = MXGEFW_FLAGS_TSO_PLD |
2027 MXGEFW_FLAGS_FIRST |
2028 (small * MXGEFW_FLAGS_SMALL);
2029 }
2030 }
2031#endif /* NETIF_F_TSO */
2032 req->addr_high = high_swapped;
2033 req->addr_low = htonl(low);
2034 req->pseudo_hdr_offset = pseudo_hdr_offset;
2035 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2036 req->rdma_count = 1;
2037 req->length = htons(seglen);
2038 req->cksum_offset = cksum_offset;
2039 req->flags = flags | ((cum_len & 1) * odd_flag);
2040
2041 low += seglen;
2042 len -= seglen;
2043 cum_len = cum_len_next;
2044 flags = flags_next;
2045 req++;
2046 count++;
2047 rdma_count++;
2048 if (unlikely(cksum_offset > seglen))
2049 cksum_offset -= seglen;
2050 else
2051 cksum_offset = 0;
2052 }
2053 if (frag_idx == frag_cnt)
2054 break;
2055
2056 /* map next fragment for DMA */
2057 idx = (count + tx->req) & tx->mask;
2058 frag = &skb_shinfo(skb)->frags[frag_idx];
2059 frag_idx++;
2060 len = frag->size;
2061 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2062 len, PCI_DMA_TODEVICE);
2063 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2064 pci_unmap_len_set(&tx->info[idx], len, len);
2065 }
2066
2067 (req - rdma_count)->rdma_count = rdma_count;
2068#ifdef NETIF_F_TSO
2069 if (mss)
2070 do {
2071 req--;
2072 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2073 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2074 MXGEFW_FLAGS_FIRST)));
2075#endif
2076 idx = ((count - 1) + tx->req) & tx->mask;
2077 tx->info[idx].last = 1;
2078 if (tx->wc_fifo == NULL)
2079 myri10ge_submit_req(tx, tx->req_list, count);
2080 else
2081 myri10ge_submit_req_wc(tx, tx->req_list, count);
2082 tx->pkt_start++;
2083 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2084 mgp->stop_queue++;
2085 netif_stop_queue(dev);
2086 }
2087 dev->trans_start = jiffies;
2088 return 0;
2089
2090abort_linearize:
2091 /* Free any DMA resources we've alloced and clear out the skb
2092 * slot so as to not trip up assertions, and to avoid a
2093 * double-free if linearizing fails */
2094
2095 last_idx = (idx + 1) & tx->mask;
2096 idx = tx->req & tx->mask;
2097 tx->info[idx].skb = NULL;
2098 do {
2099 len = pci_unmap_len(&tx->info[idx], len);
2100 if (len) {
2101 if (tx->info[idx].skb != NULL)
2102 pci_unmap_single(mgp->pdev,
2103 pci_unmap_addr(&tx->info[idx],
2104 bus), len,
2105 PCI_DMA_TODEVICE);
2106 else
2107 pci_unmap_page(mgp->pdev,
2108 pci_unmap_addr(&tx->info[idx],
2109 bus), len,
2110 PCI_DMA_TODEVICE);
2111 pci_unmap_len_set(&tx->info[idx], len, 0);
2112 tx->info[idx].skb = NULL;
2113 }
2114 idx = (idx + 1) & tx->mask;
2115 } while (idx != last_idx);
2116 if (skb_shinfo(skb)->tso_size) {
2117 printk(KERN_ERR
2118 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2119 mgp->dev->name);
2120 goto drop;
2121 }
2122
bec0e859 2123 if (skb_linearize(skb))
0da34b6d
BG		 2124 goto drop;
2125
2126 mgp->tx_linearized++;
2127 goto again;
2128
2129drop:
2130 dev_kfree_skb_any(skb);
2131 mgp->stats.tx_dropped += 1;
2132 return 0;
2133
2134}
2135
2136static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2137{
2138 struct myri10ge_priv *mgp = netdev_priv(dev);
2139 return &mgp->stats;
2140}
2141
2142static void myri10ge_set_multicast_list(struct net_device *dev)
2143{
2144 /* can be called from atomic contexts,
2145 * pass 1 to force atomicity in myri10ge_send_cmd() */
2146 myri10ge_change_promisc(netdev_priv(dev), dev->flags & IFF_PROMISC, 1);
2147}
2148
2149static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2150{
2151 struct sockaddr *sa = addr;
2152 struct myri10ge_priv *mgp = netdev_priv(dev);
2153 int status;
2154
2155 if (!is_valid_ether_addr(sa->sa_data))
2156 return -EADDRNOTAVAIL;
2157
2158 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2159 if (status != 0) {
2160 printk(KERN_ERR
2161 "myri10ge: %s: changing mac address failed with %d\n",
2162 dev->name, status);
2163 return status;
2164 }
2165
2166 /* change the dev structure */
2167 memcpy(dev->dev_addr, sa->sa_data, 6);
2168 return 0;
2169}
2170
2171static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2172{
2173 struct myri10ge_priv *mgp = netdev_priv(dev);
2174 int error = 0;
2175
2176 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
2177 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
2178 dev->name, new_mtu);
2179 return -EINVAL;
2180 }
2181 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
2182 dev->name, dev->mtu, new_mtu);
2183 if (mgp->running) {
2184 /* if we change the mtu on an active device, we must
2185 * reset the device so the firmware sees the change */
2186 myri10ge_close(dev);
2187 dev->mtu = new_mtu;
2188 myri10ge_open(dev);
2189 } else
2190 dev->mtu = new_mtu;
2191
2192 return error;
2193}
2194
2195/*
2196 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
2197 * Only do it if the bridge is a root port since we don't want to disturb
2198 * any other device, except if forced with myri10ge_ecrc_enable > 1.
2199 */
2200
2201#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_PCIE 0x005d
2202
2203static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2204{
2205 struct pci_dev *bridge = mgp->pdev->bus->self;
2206 struct device *dev = &mgp->pdev->dev;
2207 unsigned cap;
2208 unsigned err_cap;
2209 u16 val;
2210 u8 ext_type;
2211 int ret;
2212
2213 if (!myri10ge_ecrc_enable || !bridge)
2214 return;
2215
2216 /* check that the bridge is a root port */
2217 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
2218 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
2219 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2220 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
2221 if (myri10ge_ecrc_enable > 1) {
2222 struct pci_dev *old_bridge = bridge;
2223
2224 /* Walk the hierarchy up to the root port
2225 * where ECRC has to be enabled */
2226 do {
2227 bridge = bridge->bus->self;
2228 if (!bridge) {
2229 dev_err(dev,
2230 "Failed to find root port"
2231 " to force ECRC\n");
2232 return;
2233 }
2234 cap =
2235 pci_find_capability(bridge, PCI_CAP_ID_EXP);
2236 pci_read_config_word(bridge,
2237 cap + PCI_CAP_FLAGS, &val);
2238 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2239 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
2240
2241 dev_info(dev,
2242 "Forcing ECRC on non-root port %s"
2243 " (enabling on root port %s)\n",
2244 pci_name(old_bridge), pci_name(bridge));
2245 } else {
2246 dev_err(dev,
2247 "Not enabling ECRC on non-root port %s\n",
2248 pci_name(bridge));
2249 return;
2250 }
2251 }
2252
2253 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
0da34b6d
BG		 2254 if (!cap)
2255 return;
2256
2257 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
2258 if (ret) {
2259 dev_err(dev, "failed reading ext-conf-space of %s\n",
2260 pci_name(bridge));
2261 dev_err(dev, "\t pci=nommconf in use? "
2262 "or buggy/incomplete/absent ACPI MCFG attr?\n");
2263 return;
2264 }
2265 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
2266 return;
2267
2268 err_cap |= PCI_ERR_CAP_ECRC_GENE;
2269 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
2270 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
2271 mgp->tx.boundary = 4096;
2272 mgp->fw_name = myri10ge_fw_aligned;
2273}
2274
2275/*
2276 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
2277 * when the PCI-E Completion packets are aligned on an 8-byte
2278 * boundary. Some PCI-E chip sets always align Completion packets; on
2279 * the ones that do not, the alignment can be enforced by enabling
2280 * ECRC generation (if supported).
2281 *
2282 * When PCI-E Completion packets are not aligned, it is actually more
2283 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
2284 *
2285 * If the driver can neither enable ECRC nor verify that it has
2286 * already been enabled, then it must use a firmware image which works
2287 * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it
2288 * should also ensure that it never gives the device a Read-DMA which is
2289 * larger than 2KB by setting the tx.boundary to 2KB. If ECRC is
2290 * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat)
2291 * firmware image, and set tx.boundary to 4KB.
2292 */
2293
2294#define PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE 0x0132
2295
2296static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2297{
2298 struct pci_dev *bridge = mgp->pdev->bus->self;
2299
2300 mgp->tx.boundary = 2048;
2301 mgp->fw_name = myri10ge_fw_unaligned;
2302
2303 if (myri10ge_force_firmware == 0) {
2304 myri10ge_enable_ecrc(mgp);
2305
2306 /* Check to see if the upstream bridge is known to
2307 * provide aligned completions */
2308 if (bridge
2309 /* ServerWorks HT2000/HT1000 */
2310 && bridge->vendor == PCI_VENDOR_ID_SERVERWORKS
2311 && bridge->device ==
2312 PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE) {
2313 dev_info(&mgp->pdev->dev,
2314 "Assuming aligned completions (0x%x:0x%x)\n",
2315 bridge->vendor, bridge->device);
2316 mgp->tx.boundary = 4096;
2317 mgp->fw_name = myri10ge_fw_aligned;
2318 }
2319 } else {
2320 if (myri10ge_force_firmware == 1) {
2321 dev_info(&mgp->pdev->dev,
2322 "Assuming aligned completions (forced)\n");
2323 mgp->tx.boundary = 4096;
2324 mgp->fw_name = myri10ge_fw_aligned;
2325 } else {
2326 dev_info(&mgp->pdev->dev,
2327 "Assuming unaligned completions (forced)\n");
2328 mgp->tx.boundary = 2048;
2329 mgp->fw_name = myri10ge_fw_unaligned;
2330 }
2331 }
2332 if (myri10ge_fw_name != NULL) {
2333 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
2334 myri10ge_fw_name);
2335 mgp->fw_name = myri10ge_fw_name;
2336 }
2337}
2338
2339static void myri10ge_save_state(struct myri10ge_priv *mgp)
2340{
2341 struct pci_dev *pdev = mgp->pdev;
2342 int cap;
2343
2344 pci_save_state(pdev);
2345 /* now save PCIe and MSI state that Linux will not
2346 * save for us */
2347 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2348 pci_read_config_dword(pdev, cap + PCI_EXP_DEVCTL, &mgp->devctl);
2349 cap = pci_find_capability(pdev, PCI_CAP_ID_MSI);
2350 pci_read_config_word(pdev, cap + PCI_MSI_FLAGS, &mgp->msi_flags);
2351}
2352
2353static void myri10ge_restore_state(struct myri10ge_priv *mgp)
2354{
2355 struct pci_dev *pdev = mgp->pdev;
2356 int cap;
2357
2358 /* restore PCIe and MSI state that linux will not */
2359 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2360 pci_write_config_dword(pdev, cap + PCI_CAP_ID_EXP, mgp->devctl);
2361 cap = pci_find_capability(pdev, PCI_CAP_ID_MSI);
2362 pci_write_config_word(pdev, cap + PCI_MSI_FLAGS, mgp->msi_flags);
2363
2364 pci_restore_state(pdev);
2365}
2366
2367#ifdef CONFIG_PM
2368
2369static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
2370{
2371 struct myri10ge_priv *mgp;
2372 struct net_device *netdev;
2373
2374 mgp = pci_get_drvdata(pdev);
2375 if (mgp == NULL)
2376 return -EINVAL;
2377 netdev = mgp->dev;
2378
2379 netif_device_detach(netdev);
2380 if (netif_running(netdev)) {
2381 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
2382 rtnl_lock();
2383 myri10ge_close(netdev);
2384 rtnl_unlock();
2385 }
2386 myri10ge_dummy_rdma(mgp, 0);
2387 free_irq(pdev->irq, mgp);
2388 myri10ge_save_state(mgp);
2389 pci_disable_device(pdev);
2390 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2391 return 0;
2392}
2393
2394static int myri10ge_resume(struct pci_dev *pdev)
2395{
2396 struct myri10ge_priv *mgp;
2397 struct net_device *netdev;
2398 int status;
2399 u16 vendor;
2400
2401 mgp = pci_get_drvdata(pdev);
2402 if (mgp == NULL)
2403 return -EINVAL;
2404 netdev = mgp->dev;
2405 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
2406 msleep(5); /* give card time to respond */
2407 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2408 if (vendor == 0xffff) {
2409 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
2410 mgp->dev->name);
2411 return -EIO;
2412 }
2413 myri10ge_restore_state(mgp);
2414 pci_enable_device(pdev);
2415 pci_set_master(pdev);
2416
2417 status = request_irq(pdev->irq, myri10ge_intr, SA_SHIRQ,
2418 netdev->name, mgp);
2419 if (status != 0) {
2420 dev_err(&pdev->dev, "failed to allocate IRQ\n");
2421 goto abort_with_msi;
2422 }
2423
2424 myri10ge_reset(mgp);
2425 myri10ge_dummy_rdma(mgp, mgp->tx.boundary != 4096);
2426
2427 /* Save configuration space to be restored if the
2428 * nic resets due to a parity error */
2429 myri10ge_save_state(mgp);
2430
2431 if (netif_running(netdev)) {
2432 rtnl_lock();
2433 myri10ge_open(netdev);
2434 rtnl_unlock();
2435 }
2436 netif_device_attach(netdev);
2437
2438 return 0;
2439
2440abort_with_msi:
2441 return -EIO;
2442
2443}
2444
2445#endif /* CONFIG_PM */
2446
2447static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
2448{
2449 struct pci_dev *pdev = mgp->pdev;
2450 int vs = mgp->vendor_specific_offset;
2451 u32 reboot;
2452
2453 /*enter read32 mode */
2454 pci_write_config_byte(pdev, vs + 0x10, 0x3);
2455
2456 /*read REBOOT_STATUS (0xfffffff0) */
2457 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
2458 pci_read_config_dword(pdev, vs + 0x14, &reboot);
2459 return reboot;
2460}
2461
2462/*
2463 * This watchdog is used to check whether the board has suffered
2464 * from a parity error and needs to be recovered.
2465 */
2466static void myri10ge_watchdog(void *arg)
2467{
2468 struct myri10ge_priv *mgp = arg;
2469 u32 reboot;
2470 int status;
2471 u16 cmd, vendor;
2472
2473 mgp->watchdog_resets++;
2474 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
2475 if ((cmd & PCI_COMMAND_MASTER) == 0) {
2476 /* Bus master DMA disabled? Check to see
2477 * if the card rebooted due to a parity error
2478 * For now, just report it */
2479 reboot = myri10ge_read_reboot(mgp);
2480 printk(KERN_ERR
2481 "myri10ge: %s: NIC rebooted (0x%x), resetting\n",
2482 mgp->dev->name, reboot);
2483 /*
2484 * A rebooted nic will come back with config space as
2485 * it was after power was applied to PCIe bus.
2486 * Attempt to restore config space which was saved
2487 * when the driver was loaded, or the last time the
2488 * nic was resumed from power saving mode.
2489 */
2490 myri10ge_restore_state(mgp);
2491 } else {
2492 /* if we get back -1's from our slot, perhaps somebody
2493 * powered off our card. Don't try to reset it in
2494 * this case */
2495 if (cmd == 0xffff) {
2496 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2497 if (vendor == 0xffff) {
2498 printk(KERN_ERR
2499 "myri10ge: %s: device disappeared!\n",
2500 mgp->dev->name);
2501 return;
2502 }
2503 }
2504 /* Perhaps it is a software error. Try to reset */
2505
2506 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
2507 mgp->dev->name);
2508 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2509 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2510 mgp->tx.pkt_start, mgp->tx.pkt_done,
2511 (int)ntohl(mgp->fw_stats->send_done_count));
2512 msleep(2000);
2513 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2514 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2515 mgp->tx.pkt_start, mgp->tx.pkt_done,
2516 (int)ntohl(mgp->fw_stats->send_done_count));
2517 }
2518 rtnl_lock();
2519 myri10ge_close(mgp->dev);
2520 status = myri10ge_load_firmware(mgp);
2521 if (status != 0)
2522 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
2523 mgp->dev->name);
2524 else
2525 myri10ge_open(mgp->dev);
2526 rtnl_unlock();
2527}
2528
2529/*
2530 * We use our own timer routine rather than relying upon
2531 * netdev->tx_timeout because we have a very large hardware transmit
2532 * queue. Due to the large queue, the netdev->tx_timeout function
2533 * cannot detect a NIC with a parity error in a timely fashion if the
2534 * NIC is lightly loaded.
2535 */
2536static void myri10ge_watchdog_timer(unsigned long arg)
2537{
2538 struct myri10ge_priv *mgp;
2539
2540 mgp = (struct myri10ge_priv *)arg;
2541 if (mgp->tx.req != mgp->tx.done &&
2542 mgp->tx.done == mgp->watchdog_tx_done)
2543 /* nic seems like it might be stuck.. */
2544 schedule_work(&mgp->watchdog_work);
2545 else
2546 /* rearm timer */
2547 mod_timer(&mgp->watchdog_timer,
2548 jiffies + myri10ge_watchdog_timeout * HZ);
2549
2550 mgp->watchdog_tx_done = mgp->tx.done;
2551}
2552
2553static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2554{
2555 struct net_device *netdev;
2556 struct myri10ge_priv *mgp;
2557 struct device *dev = &pdev->dev;
2558 size_t bytes;
2559 int i;
2560 int status = -ENXIO;
2561 int cap;
2562 int dac_enabled;
2563 u16 val;
2564
2565 netdev = alloc_etherdev(sizeof(*mgp));
2566 if (netdev == NULL) {
2567 dev_err(dev, "Could not allocate ethernet device\n");
2568 return -ENOMEM;
2569 }
2570
2571 mgp = netdev_priv(netdev);
2572 memset(mgp, 0, sizeof(*mgp));
2573 mgp->dev = netdev;
2574 mgp->pdev = pdev;
2575 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
2576 mgp->pause = myri10ge_flow_control;
2577 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
2578 init_waitqueue_head(&mgp->down_wq);
2579
2580 if (pci_enable_device(pdev)) {
2581 dev_err(&pdev->dev, "pci_enable_device call failed\n");
2582 status = -ENODEV;
2583 goto abort_with_netdev;
2584 }
2585 myri10ge_select_firmware(mgp);
2586
2587 /* Find the vendor-specific cap so we can check
2588 * the reboot register later on */
2589 mgp->vendor_specific_offset
2590 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
2591
2592 /* Set our max read request to 4KB */
2593 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2594 if (cap < 64) {
2595 dev_err(&pdev->dev, "Bad PCI_CAP_ID_EXP location %d\n", cap);
2596 goto abort_with_netdev;
2597 }
2598 status = pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &val);
2599 if (status != 0) {
2600 dev_err(&pdev->dev, "Error %d reading PCI_EXP_DEVCTL\n",
2601 status);
2602 goto abort_with_netdev;
2603 }
2604 val = (val & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);
2605 status = pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, val);
2606 if (status != 0) {
2607 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
2608 status);
2609 goto abort_with_netdev;
2610 }
2611
2612 pci_set_master(pdev);
2613 dac_enabled = 1;
2614 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2615 if (status != 0) {
2616 dac_enabled = 0;
2617 dev_err(&pdev->dev,
2618 "64-bit pci address mask was refused, trying 32-bit");
2619 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2620 }
2621 if (status != 0) {
2622 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
2623 goto abort_with_netdev;
2624 }
b10c0668
BG		 2625 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
2626 &mgp->cmd_bus, GFP_KERNEL);
0da34b6d
BG		 2627 if (mgp->cmd == NULL)
2628 goto abort_with_netdev;
2629
b10c0668
BG		 2630 mgp->fw_stats = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2631 &mgp->fw_stats_bus, GFP_KERNEL);
0da34b6d
BG		 2632 if (mgp->fw_stats == NULL)
2633 goto abort_with_cmd;
2634
2635 mgp->board_span = pci_resource_len(pdev, 0);
2636 mgp->iomem_base = pci_resource_start(pdev, 0);
2637 mgp->mtrr = -1;
2638#ifdef CONFIG_MTRR
2639 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
2640 MTRR_TYPE_WRCOMB, 1);
2641#endif
2642 /* Hack. need to get rid of these magic numbers */
2643 mgp->sram_size =
2644 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
2645 if (mgp->sram_size > mgp->board_span) {
2646 dev_err(&pdev->dev, "board span %ld bytes too small\n",
2647 mgp->board_span);
2648 goto abort_with_wc;
2649 }
2650 mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
2651 if (mgp->sram == NULL) {
2652 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
2653 mgp->board_span, mgp->iomem_base);
2654 status = -ENXIO;
2655 goto abort_with_wc;
2656 }
2657 memcpy_fromio(mgp->eeprom_strings,
2658 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
2659 MYRI10GE_EEPROM_STRINGS_SIZE);
2660 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
2661 status = myri10ge_read_mac_addr(mgp);
2662 if (status)
2663 goto abort_with_ioremap;
2664
2665 for (i = 0; i < ETH_ALEN; i++)
2666 netdev->dev_addr[i] = mgp->mac_addr[i];
2667
2668 /* allocate rx done ring */
2669 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 2670 mgp->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
2671 &mgp->rx_done.bus, GFP_KERNEL);
0da34b6d
BG		 2672 if (mgp->rx_done.entry == NULL)
2673 goto abort_with_ioremap;
2674 memset(mgp->rx_done.entry, 0, bytes);
2675
2676 status = myri10ge_load_firmware(mgp);
2677 if (status != 0) {
2678 dev_err(&pdev->dev, "failed to load firmware\n");
2679 goto abort_with_rx_done;
2680 }
2681
2682 status = myri10ge_reset(mgp);
2683 if (status != 0) {
2684 dev_err(&pdev->dev, "failed reset\n");
2685 goto abort_with_firmware;
2686 }
2687
2688 if (myri10ge_msi) {
2689 status = pci_enable_msi(pdev);
2690 if (status != 0)
2691 dev_err(&pdev->dev,
2692 "Error %d setting up MSI; falling back to xPIC\n",
2693 status);
2694 else
2695 mgp->msi_enabled = 1;
2696 }
2697
2698 status = request_irq(pdev->irq, myri10ge_intr, SA_SHIRQ,
2699 netdev->name, mgp);
2700 if (status != 0) {
2701 dev_err(&pdev->dev, "failed to allocate IRQ\n");
2702 goto abort_with_firmware;
2703 }
2704
2705 pci_set_drvdata(pdev, mgp);
2706 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
2707 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
2708 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
2709 myri10ge_initial_mtu = 68;
2710 netdev->mtu = myri10ge_initial_mtu;
2711 netdev->open = myri10ge_open;
2712 netdev->stop = myri10ge_close;
2713 netdev->hard_start_xmit = myri10ge_xmit;
2714 netdev->get_stats = myri10ge_get_stats;
2715 netdev->base_addr = mgp->iomem_base;
2716 netdev->irq = pdev->irq;
2717 netdev->change_mtu = myri10ge_change_mtu;
2718 netdev->set_multicast_list = myri10ge_set_multicast_list;
2719 netdev->set_mac_address = myri10ge_set_mac_address;
2720 netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
2721 if (dac_enabled)
2722 netdev->features |= NETIF_F_HIGHDMA;
2723 netdev->poll = myri10ge_poll;
2724 netdev->weight = myri10ge_napi_weight;
2725
2726 /* Save configuration space to be restored if the
2727 * nic resets due to a parity error */
2728 myri10ge_save_state(mgp);
0da34b6d
BG		 2729
2730 /* Setup the watchdog timer */
2731 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
2732 (unsigned long)mgp);
2733
2734 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
2735 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog, mgp);
2736 status = register_netdev(netdev);
2737 if (status != 0) {
2738 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
2739 goto abort_with_irq;
2740 }
2741
2742 printk(KERN_INFO "myri10ge: %s: %s IRQ %d, tx bndry %d, fw %s, WC %s\n",
2743 netdev->name, (mgp->msi_enabled ? "MSI" : "xPIC"),
2744 pdev->irq, mgp->tx.boundary, mgp->fw_name,
2745 (mgp->mtrr >= 0 ? "Enabled" : "Disabled"));
2746
2747 return 0;
2748
2749abort_with_irq:
2750 free_irq(pdev->irq, mgp);
2751 if (mgp->msi_enabled)
2752 pci_disable_msi(pdev);
2753
2754abort_with_firmware:
2755 myri10ge_dummy_rdma(mgp, 0);
2756
2757abort_with_rx_done:
2758 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 2759 dma_free_coherent(&pdev->dev, bytes,
2760 mgp->rx_done.entry, mgp->rx_done.bus);
0da34b6d
BG		 2761
2762abort_with_ioremap:
2763 iounmap(mgp->sram);
2764
2765abort_with_wc:
2766#ifdef CONFIG_MTRR
2767 if (mgp->mtrr >= 0)
2768 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
2769#endif
b10c0668
BG		 2770 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2771 mgp->fw_stats, mgp->fw_stats_bus);
0da34b6d
BG		 2772
2773abort_with_cmd:
b10c0668
BG		 2774 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
2775 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 2776
2777abort_with_netdev:
2778
2779 free_netdev(netdev);
2780 return status;
2781}
2782
2783/*
2784 * myri10ge_remove
2785 *
2786 * Does what is necessary to shutdown one Myrinet device. Called
2787 * once for each Myrinet card by the kernel when a module is
2788 * unloaded.
2789 */
2790static void myri10ge_remove(struct pci_dev *pdev)
2791{
2792 struct myri10ge_priv *mgp;
2793 struct net_device *netdev;
2794 size_t bytes;
2795
2796 mgp = pci_get_drvdata(pdev);
2797 if (mgp == NULL)
2798 return;
2799
2800 flush_scheduled_work();
2801 netdev = mgp->dev;
2802 unregister_netdev(netdev);
2803 free_irq(pdev->irq, mgp);
2804 if (mgp->msi_enabled)
2805 pci_disable_msi(pdev);
2806
2807 myri10ge_dummy_rdma(mgp, 0);
2808
2809 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 2810 dma_free_coherent(&pdev->dev, bytes,
2811 mgp->rx_done.entry, mgp->rx_done.bus);
0da34b6d
BG		 2812
2813 iounmap(mgp->sram);
2814
2815#ifdef CONFIG_MTRR
2816 if (mgp->mtrr >= 0)
2817 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
2818#endif
b10c0668
BG		 2819 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2820 mgp->fw_stats, mgp->fw_stats_bus);
0da34b6d 2821
b10c0668
BG		 2822 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
2823 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 2824
2825 free_netdev(netdev);
2826 pci_set_drvdata(pdev, NULL);
2827}
2828
b10c0668 2829#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
0da34b6d
BG		 2830
2831static struct pci_device_id myri10ge_pci_tbl[] = {
b10c0668 2832 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
0da34b6d
BG		 2833 {0},
2834};
2835
2836static struct pci_driver myri10ge_driver = {
2837 .name = "myri10ge",
2838 .probe = myri10ge_probe,
2839 .remove = myri10ge_remove,
2840 .id_table = myri10ge_pci_tbl,
2841#ifdef CONFIG_PM
2842 .suspend = myri10ge_suspend,
2843 .resume = myri10ge_resume,
2844#endif
2845};
2846
2847static __init int myri10ge_init_module(void)
2848{
2849 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
2850 MYRI10GE_VERSION_STR);
2851 return pci_register_driver(&myri10ge_driver);
2852}
2853
2854module_init(myri10ge_init_module);
2855
2856static __exit void myri10ge_cleanup_module(void)
2857{
2858 pci_unregister_driver(&myri10ge_driver);
2859}
2860
2861module_exit(myri10ge_cleanup_module);
Linux kernel - Deliverables
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