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smc911x: remove duplicate debug printout
[deliverable/linux.git] / drivers / net / myri10ge / myri10ge.c
CommitLineData
0da34b6d
BG		 1/*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4a2e612a 4 * Copyright (C) 2005 - 2007 Myricom, Inc.
0da34b6d
BG		 5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
4a2e612a
BG		 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0da34b6d 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4a2e612a
BG		 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
0da34b6d
BG		 30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41#include <linux/tcp.h>
42#include <linux/netdevice.h>
43#include <linux/skbuff.h>
44#include <linux/string.h>
45#include <linux/module.h>
46#include <linux/pci.h>
b10c0668 47#include <linux/dma-mapping.h>
0da34b6d
BG		 48#include <linux/etherdevice.h>
49#include <linux/if_ether.h>
50#include <linux/if_vlan.h>
1e6e9342 51#include <linux/inet_lro.h>
981813d8 52#include <linux/dca.h>
0da34b6d
BG		 53#include <linux/ip.h>
54#include <linux/inet.h>
55#include <linux/in.h>
56#include <linux/ethtool.h>
57#include <linux/firmware.h>
58#include <linux/delay.h>
0da34b6d
BG		 59#include <linux/timer.h>
60#include <linux/vmalloc.h>
61#include <linux/crc32.h>
62#include <linux/moduleparam.h>
63#include <linux/io.h>
199126a2 64#include <linux/log2.h>
0da34b6d 65#include <net/checksum.h>
1e6e9342
AG		 66#include <net/ip.h>
67#include <net/tcp.h>
0da34b6d
BG		 68#include <asm/byteorder.h>
69#include <asm/io.h>
0da34b6d
BG		 70#include <asm/processor.h>
71#ifdef CONFIG_MTRR
72#include <asm/mtrr.h>
73#endif
74
75#include "myri10ge_mcp.h"
76#include "myri10ge_mcp_gen_header.h"
77
0623807a 78#define MYRI10GE_VERSION_STR "1.4.3-1.358"
0da34b6d
BG		 79
80MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
81MODULE_AUTHOR("Maintainer: help@myri.com");
82MODULE_VERSION(MYRI10GE_VERSION_STR);
83MODULE_LICENSE("Dual BSD/GPL");
84
85#define MYRI10GE_MAX_ETHER_MTU 9014
86
87#define MYRI10GE_ETH_STOPPED 0
88#define MYRI10GE_ETH_STOPPING 1
89#define MYRI10GE_ETH_STARTING 2
90#define MYRI10GE_ETH_RUNNING 3
91#define MYRI10GE_ETH_OPEN_FAILED 4
92
93#define MYRI10GE_EEPROM_STRINGS_SIZE 256
94#define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
1e6e9342
AG		 95#define MYRI10GE_MAX_LRO_DESCRIPTORS 8
96#define MYRI10GE_LRO_MAX_PKTS 64
0da34b6d 97
40f6cff5 98#define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
0da34b6d
BG		 99#define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
100
dd50f336
BG		 101#define MYRI10GE_ALLOC_ORDER 0
102#define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
103#define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
104
0da34b6d 105struct myri10ge_rx_buffer_state {
dd50f336
BG		 106 struct page *page;
107 int page_offset;
0da34b6d
BG		 108 DECLARE_PCI_UNMAP_ADDR(bus)
109 DECLARE_PCI_UNMAP_LEN(len)
110};
111
112struct myri10ge_tx_buffer_state {
113 struct sk_buff *skb;
114 int last;
115 DECLARE_PCI_UNMAP_ADDR(bus)
116 DECLARE_PCI_UNMAP_LEN(len)
117};
118
119struct myri10ge_cmd {
120 u32 data0;
121 u32 data1;
122 u32 data2;
123};
124
125struct myri10ge_rx_buf {
126 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
0da34b6d
BG		 127 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
128 struct myri10ge_rx_buffer_state *info;
dd50f336
BG		 129 struct page *page;
130 dma_addr_t bus;
131 int page_offset;
0da34b6d 132 int cnt;
dd50f336 133 int fill_cnt;
0da34b6d
BG		 134 int alloc_fail;
135 int mask; /* number of rx slots -1 */
dd50f336 136 int watchdog_needed;
0da34b6d
BG		 137};
138
139struct myri10ge_tx_buf {
140 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
0da34b6d
BG		 141 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
142 char *req_bytes;
143 struct myri10ge_tx_buffer_state *info;
144 int mask; /* number of transmit slots -1 */
0da34b6d
BG		 145 int req ____cacheline_aligned; /* transmit slots submitted */
146 int pkt_start; /* packets started */
b53bef84
BG		 147 int stop_queue;
148 int linearized;
0da34b6d
BG		 149 int done ____cacheline_aligned; /* transmit slots completed */
150 int pkt_done; /* packets completed */
b53bef84 151 int wake_queue;
0da34b6d
BG		 152};
153
154struct myri10ge_rx_done {
155 struct mcp_slot *entry;
156 dma_addr_t bus;
157 int cnt;
158 int idx;
1e6e9342
AG		 159 struct net_lro_mgr lro_mgr;
160 struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
0da34b6d
BG		 161};
162
b53bef84
BG		 163struct myri10ge_slice_netstats {
164 unsigned long rx_packets;
165 unsigned long tx_packets;
166 unsigned long rx_bytes;
167 unsigned long tx_bytes;
168 unsigned long rx_dropped;
169 unsigned long tx_dropped;
170};
171
172struct myri10ge_slice_state {
0da34b6d
BG		 173 struct myri10ge_tx_buf tx; /* transmit ring */
174 struct myri10ge_rx_buf rx_small;
175 struct myri10ge_rx_buf rx_big;
176 struct myri10ge_rx_done rx_done;
b53bef84
BG		 177 struct net_device *dev;
178 struct napi_struct napi;
179 struct myri10ge_priv *mgp;
180 struct myri10ge_slice_netstats stats;
181 __be32 __iomem *irq_claim;
182 struct mcp_irq_data *fw_stats;
183 dma_addr_t fw_stats_bus;
184 int watchdog_tx_done;
185 int watchdog_tx_req;
981813d8
BG		 186#ifdef CONFIG_DCA
187 int cached_dca_tag;
188 int cpu;
189 __be32 __iomem *dca_tag;
190#endif
0dcffac1 191 char irq_desc[32];
b53bef84
BG		 192};
193
194struct myri10ge_priv {
0dcffac1 195 struct myri10ge_slice_state *ss;
b53bef84 196 int tx_boundary; /* boundary transmits cannot cross */
0dcffac1 197 int num_slices;
b53bef84
BG		 198 int running; /* running? */
199 int csum_flag; /* rx_csums? */
0da34b6d 200 int small_bytes;
dd50f336 201 int big_bytes;
fa0a90d9 202 int max_intr_slots;
0da34b6d
BG		 203 struct net_device *dev;
204 struct net_device_stats stats;
b53bef84 205 spinlock_t stats_lock;
0da34b6d
BG		 206 u8 __iomem *sram;
207 int sram_size;
208 unsigned long board_span;
209 unsigned long iomem_base;
40f6cff5 210 __be32 __iomem *irq_deassert;
0da34b6d
BG		 211 char *mac_addr_string;
212 struct mcp_cmd_response *cmd;
213 dma_addr_t cmd_bus;
0da34b6d
BG		 214 struct pci_dev *pdev;
215 int msi_enabled;
0dcffac1
BG		 216 int msix_enabled;
217 struct msix_entry *msix_vectors;
981813d8
BG		 218#ifdef CONFIG_DCA
219 int dca_enabled;
220#endif
66341fff 221 u32 link_state;
0da34b6d
BG		 222 unsigned int rdma_tags_available;
223 int intr_coal_delay;
40f6cff5 224 __be32 __iomem *intr_coal_delay_ptr;
0da34b6d 225 int mtrr;
276e26c3 226 int wc_enabled;
0da34b6d
BG		 227 int down_cnt;
228 wait_queue_head_t down_wq;
229 struct work_struct watchdog_work;
230 struct timer_list watchdog_timer;
0da34b6d 231 int watchdog_resets;
b53bef84 232 int watchdog_pause;
0da34b6d
BG		 233 int pause;
234 char *fw_name;
235 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
c0bf8801 236 char *product_code_string;
0da34b6d 237 char fw_version[128];
9dc6f0e7
BG		 238 int fw_ver_major;
239 int fw_ver_minor;
240 int fw_ver_tiny;
241 int adopted_rx_filter_bug;
0da34b6d
BG		 242 u8 mac_addr[6]; /* eeprom mac address */
243 unsigned long serial_number;
244 int vendor_specific_offset;
85a7ea1b 245 int fw_multicast_support;
4f93fde0
BG		 246 unsigned long features;
247 u32 max_tso6;
0da34b6d
BG		 248 u32 read_dma;
249 u32 write_dma;
250 u32 read_write_dma;
c58ac5ca
BG		 251 u32 link_changes;
252 u32 msg_enable;
0da34b6d
BG		 253};
254
255static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
256static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
0dcffac1
BG		 257static char *myri10ge_fw_rss_unaligned = "myri10ge_rss_ethp_z8e.dat";
258static char *myri10ge_fw_rss_aligned = "myri10ge_rss_eth_z8e.dat";
0da34b6d
BG		 259
260static char *myri10ge_fw_name = NULL;
261module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
d1ce3a0f 262MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
0da34b6d
BG		 263
264static int myri10ge_ecrc_enable = 1;
265module_param(myri10ge_ecrc_enable, int, S_IRUGO);
d1ce3a0f 266MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
0da34b6d 267
0da34b6d
BG		 268static int myri10ge_small_bytes = -1; /* -1 == auto */
269module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
d1ce3a0f 270MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
0da34b6d
BG		 271
272static int myri10ge_msi = 1; /* enable msi by default */
3621cec5 273module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
d1ce3a0f 274MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
0da34b6d 275
f761fae1 276static int myri10ge_intr_coal_delay = 75;
0da34b6d 277module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
d1ce3a0f 278MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
0da34b6d
BG		 279
280static int myri10ge_flow_control = 1;
281module_param(myri10ge_flow_control, int, S_IRUGO);
d1ce3a0f 282MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
0da34b6d
BG		 283
284static int myri10ge_deassert_wait = 1;
285module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
286MODULE_PARM_DESC(myri10ge_deassert_wait,
d1ce3a0f 287 "Wait when deasserting legacy interrupts");
0da34b6d
BG		 288
289static int myri10ge_force_firmware = 0;
290module_param(myri10ge_force_firmware, int, S_IRUGO);
291MODULE_PARM_DESC(myri10ge_force_firmware,
d1ce3a0f 292 "Force firmware to assume aligned completions");
0da34b6d 293
0da34b6d
BG		 294static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
295module_param(myri10ge_initial_mtu, int, S_IRUGO);
d1ce3a0f 296MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
0da34b6d
BG		 297
298static int myri10ge_napi_weight = 64;
299module_param(myri10ge_napi_weight, int, S_IRUGO);
d1ce3a0f 300MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
0da34b6d
BG		 301
302static int myri10ge_watchdog_timeout = 1;
303module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
d1ce3a0f 304MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
0da34b6d
BG		 305
306static int myri10ge_max_irq_loops = 1048576;
307module_param(myri10ge_max_irq_loops, int, S_IRUGO);
308MODULE_PARM_DESC(myri10ge_max_irq_loops,
d1ce3a0f 309 "Set stuck legacy IRQ detection threshold");
0da34b6d 310
c58ac5ca
BG		 311#define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
312
313static int myri10ge_debug = -1; /* defaults above */
314module_param(myri10ge_debug, int, 0);
315MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
316
1e6e9342
AG		 317static int myri10ge_lro = 1;
318module_param(myri10ge_lro, int, S_IRUGO);
d1ce3a0f 319MODULE_PARM_DESC(myri10ge_lro, "Enable large receive offload");
1e6e9342
AG		 320
321static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
322module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
d1ce3a0f
BG		 323MODULE_PARM_DESC(myri10ge_lro_max_pkts,
324 "Number of LRO packets to be aggregated");
1e6e9342 325
dd50f336
BG		 326static int myri10ge_fill_thresh = 256;
327module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
d1ce3a0f 328MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
dd50f336 329
f181137f
BG		 330static int myri10ge_reset_recover = 1;
331
0dcffac1
BG		 332static int myri10ge_max_slices = 1;
333module_param(myri10ge_max_slices, int, S_IRUGO);
334MODULE_PARM_DESC(myri10ge_max_slices, "Max tx/rx queues");
335
336static int myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
337module_param(myri10ge_rss_hash, int, S_IRUGO);
338MODULE_PARM_DESC(myri10ge_rss_hash, "Type of RSS hashing to do");
339
981813d8
BG		 340static int myri10ge_dca = 1;
341module_param(myri10ge_dca, int, S_IRUGO);
342MODULE_PARM_DESC(myri10ge_dca, "Enable DCA if possible");
343
0da34b6d
BG		 344#define MYRI10GE_FW_OFFSET 1024*1024
345#define MYRI10GE_HIGHPART_TO_U32(X) \
346(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
347#define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
348
349#define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
350
2f76216f 351static void myri10ge_set_multicast_list(struct net_device *dev);
4f93fde0 352static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev);
2f76216f 353
6250223e 354static inline void put_be32(__be32 val, __be32 __iomem * p)
40f6cff5 355{
6250223e 356 __raw_writel((__force __u32) val, (__force void __iomem *)p);
40f6cff5
AV		 357}
358
0da34b6d
BG		 359static int
360myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
361 struct myri10ge_cmd *data, int atomic)
362{
363 struct mcp_cmd *buf;
364 char buf_bytes[sizeof(*buf) + 8];
365 struct mcp_cmd_response *response = mgp->cmd;
e700f9f4 366 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
0da34b6d
BG		 367 u32 dma_low, dma_high, result, value;
368 int sleep_total = 0;
369
370 /* ensure buf is aligned to 8 bytes */
371 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
372
373 buf->data0 = htonl(data->data0);
374 buf->data1 = htonl(data->data1);
375 buf->data2 = htonl(data->data2);
376 buf->cmd = htonl(cmd);
377 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
378 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
379
380 buf->response_addr.low = htonl(dma_low);
381 buf->response_addr.high = htonl(dma_high);
40f6cff5 382 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 383 mb();
384 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
385
386 /* wait up to 15ms. Longest command is the DMA benchmark,
387 * which is capped at 5ms, but runs from a timeout handler
388 * that runs every 7.8ms. So a 15ms timeout leaves us with
389 * a 2.2ms margin
390 */
391 if (atomic) {
392 /* if atomic is set, do not sleep,
393 * and try to get the completion quickly
394 * (1ms will be enough for those commands) */
395 for (sleep_total = 0;
396 sleep_total < 1000
40f6cff5 397 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
bd2db0cf 398 sleep_total += 10) {
0da34b6d 399 udelay(10);
bd2db0cf
BG		 400 mb();
401 }
0da34b6d
BG		 402 } else {
403 /* use msleep for most command */
404 for (sleep_total = 0;
405 sleep_total < 15
40f6cff5 406 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 407 sleep_total++)
408 msleep(1);
409 }
410
411 result = ntohl(response->result);
412 value = ntohl(response->data);
413 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
414 if (result == 0) {
415 data->data0 = value;
416 return 0;
85a7ea1b
BG		 417 } else if (result == MXGEFW_CMD_UNKNOWN) {
418 return -ENOSYS;
5443e9ea
BG		 419 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
420 return -E2BIG;
0da34b6d
BG		 421 } else {
422 dev_err(&mgp->pdev->dev,
423 "command %d failed, result = %d\n",
424 cmd, result);
425 return -ENXIO;
426 }
427 }
428
429 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
430 cmd, result);
431 return -EAGAIN;
432}
433
434/*
435 * The eeprom strings on the lanaiX have the format
436 * SN=x\0
437 * MAC=x:x:x:x:x:x\0
438 * PT:ddd mmm xx xx:xx:xx xx\0
439 * PV:ddd mmm xx xx:xx:xx xx\0
440 */
441static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
442{
443 char *ptr, *limit;
444 int i;
445
446 ptr = mgp->eeprom_strings;
447 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
448
449 while (*ptr != '\0' && ptr < limit) {
450 if (memcmp(ptr, "MAC=", 4) == 0) {
451 ptr += 4;
452 mgp->mac_addr_string = ptr;
453 for (i = 0; i < 6; i++) {
454 if ((ptr + 2) > limit)
455 goto abort;
456 mgp->mac_addr[i] =
457 simple_strtoul(ptr, &ptr, 16);
458 ptr += 1;
459 }
460 }
c0bf8801
BG		 461 if (memcmp(ptr, "PC=", 3) == 0) {
462 ptr += 3;
463 mgp->product_code_string = ptr;
464 }
0da34b6d
BG		 465 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
466 ptr += 3;
467 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
468 }
469 while (ptr < limit && *ptr++) ;
470 }
471
472 return 0;
473
474abort:
475 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
476 return -ENXIO;
477}
478
479/*
480 * Enable or disable periodic RDMAs from the host to make certain
481 * chipsets resend dropped PCIe messages
482 */
483
484static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
485{
486 char __iomem *submit;
f8fd57c1 487 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 488 u32 dma_low, dma_high;
489 int i;
490
491 /* clear confirmation addr */
492 mgp->cmd->data = 0;
493 mb();
494
495 /* send a rdma command to the PCIe engine, and wait for the
496 * response in the confirmation address. The firmware should
497 * write a -1 there to indicate it is alive and well
498 */
499 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
500 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
501
502 buf[0] = htonl(dma_high); /* confirm addr MSW */
503 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 504 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 505 buf[3] = htonl(dma_high); /* dummy addr MSW */
506 buf[4] = htonl(dma_low); /* dummy addr LSW */
507 buf[5] = htonl(enable); /* enable? */
508
e700f9f4 509 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
0da34b6d
BG		 510
511 myri10ge_pio_copy(submit, &buf, sizeof(buf));
512 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
513 msleep(1);
514 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
515 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
516 (enable ? "enable" : "disable"));
517}
518
519static int
520myri10ge_validate_firmware(struct myri10ge_priv *mgp,
521 struct mcp_gen_header *hdr)
522{
523 struct device *dev = &mgp->pdev->dev;
0da34b6d
BG		 524
525 /* check firmware type */
526 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
527 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
528 return -EINVAL;
529 }
530
531 /* save firmware version for ethtool */
532 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
533
9dc6f0e7
BG		 534 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
535 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
0da34b6d 536
9dc6f0e7
BG		 537 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
538 && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
0da34b6d
BG		 539 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
540 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
541 MXGEFW_VERSION_MINOR);
542 return -EINVAL;
543 }
544 return 0;
545}
546
547static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
548{
549 unsigned crc, reread_crc;
550 const struct firmware *fw;
551 struct device *dev = &mgp->pdev->dev;
b0d31d6b 552 unsigned char *fw_readback;
0da34b6d
BG		 553 struct mcp_gen_header *hdr;
554 size_t hdr_offset;
555 int status;
e454358a 556 unsigned i;
0da34b6d
BG		 557
558 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
559 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
560 mgp->fw_name);
561 status = -EINVAL;
562 goto abort_with_nothing;
563 }
564
565 /* check size */
566
567 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
568 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
569 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
570 status = -EINVAL;
571 goto abort_with_fw;
572 }
573
574 /* check id */
40f6cff5 575 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 576 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
577 dev_err(dev, "Bad firmware file\n");
578 status = -EINVAL;
579 goto abort_with_fw;
580 }
581 hdr = (void *)(fw->data + hdr_offset);
582
583 status = myri10ge_validate_firmware(mgp, hdr);
584 if (status != 0)
585 goto abort_with_fw;
586
587 crc = crc32(~0, fw->data, fw->size);
e454358a
BG		 588 for (i = 0; i < fw->size; i += 256) {
589 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
590 fw->data + i,
591 min(256U, (unsigned)(fw->size - i)));
592 mb();
593 readb(mgp->sram);
b10c0668 594 }
b0d31d6b
DW		 595 fw_readback = vmalloc(fw->size);
596 if (!fw_readback) {
597 status = -ENOMEM;
598 goto abort_with_fw;
599 }
0da34b6d 600 /* corruption checking is good for parity recovery and buggy chipset */
b0d31d6b
DW		 601 memcpy_fromio(fw_readback, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
602 reread_crc = crc32(~0, fw_readback, fw->size);
603 vfree(fw_readback);
0da34b6d
BG		 604 if (crc != reread_crc) {
605 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
606 (unsigned)fw->size, reread_crc, crc);
607 status = -EIO;
608 goto abort_with_fw;
609 }
610 *size = (u32) fw->size;
611
612abort_with_fw:
613 release_firmware(fw);
614
615abort_with_nothing:
616 return status;
617}
618
619static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
620{
621 struct mcp_gen_header *hdr;
622 struct device *dev = &mgp->pdev->dev;
623 const size_t bytes = sizeof(struct mcp_gen_header);
624 size_t hdr_offset;
625 int status;
626
627 /* find running firmware header */
66341fff 628 hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 629
630 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
631 dev_err(dev, "Running firmware has bad header offset (%d)\n",
632 (int)hdr_offset);
633 return -EIO;
634 }
635
636 /* copy header of running firmware from SRAM to host memory to
637 * validate firmware */
638 hdr = kmalloc(bytes, GFP_KERNEL);
639 if (hdr == NULL) {
640 dev_err(dev, "could not malloc firmware hdr\n");
641 return -ENOMEM;
642 }
643 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
644 status = myri10ge_validate_firmware(mgp, hdr);
645 kfree(hdr);
9dc6f0e7
BG		 646
647 /* check to see if adopted firmware has bug where adopting
648 * it will cause broadcasts to be filtered unless the NIC
649 * is kept in ALLMULTI mode */
650 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
651 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
652 mgp->adopted_rx_filter_bug = 1;
653 dev_warn(dev, "Adopting fw %d.%d.%d: "
654 "working around rx filter bug\n",
655 mgp->fw_ver_major, mgp->fw_ver_minor,
656 mgp->fw_ver_tiny);
657 }
0da34b6d
BG		 658 return status;
659}
660
0178ec3d 661static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
fa0a90d9
BG		 662{
663 struct myri10ge_cmd cmd;
664 int status;
665
666 /* probe for IPv6 TSO support */
667 mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
668 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
669 &cmd, 0);
670 if (status == 0) {
671 mgp->max_tso6 = cmd.data0;
672 mgp->features |= NETIF_F_TSO6;
673 }
674
675 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
676 if (status != 0) {
677 dev_err(&mgp->pdev->dev,
678 "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
679 return -ENXIO;
680 }
681
682 mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
683
684 return 0;
685}
686
0dcffac1 687static int myri10ge_load_firmware(struct myri10ge_priv *mgp, int adopt)
0da34b6d
BG		 688{
689 char __iomem *submit;
f8fd57c1 690 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 691 u32 dma_low, dma_high, size;
692 int status, i;
693
b10c0668 694 size = 0;
0da34b6d
BG		 695 status = myri10ge_load_hotplug_firmware(mgp, &size);
696 if (status) {
0dcffac1
BG		 697 if (!adopt)
698 return status;
0da34b6d
BG		 699 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
700
701 /* Do not attempt to adopt firmware if there
702 * was a bad crc */
703 if (status == -EIO)
704 return status;
705
706 status = myri10ge_adopt_running_firmware(mgp);
707 if (status != 0) {
708 dev_err(&mgp->pdev->dev,
709 "failed to adopt running firmware\n");
710 return status;
711 }
712 dev_info(&mgp->pdev->dev,
713 "Successfully adopted running firmware\n");
b53bef84 714 if (mgp->tx_boundary == 4096) {
0da34b6d
BG		 715 dev_warn(&mgp->pdev->dev,
716 "Using firmware currently running on NIC"
717 ". For optimal\n");
718 dev_warn(&mgp->pdev->dev,
719 "performance consider loading optimized "
720 "firmware\n");
721 dev_warn(&mgp->pdev->dev, "via hotplug\n");
722 }
723
724 mgp->fw_name = "adopted";
b53bef84 725 mgp->tx_boundary = 2048;
fa0a90d9
BG		 726 myri10ge_dummy_rdma(mgp, 1);
727 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d
BG		 728 return status;
729 }
730
731 /* clear confirmation addr */
732 mgp->cmd->data = 0;
733 mb();
734
735 /* send a reload command to the bootstrap MCP, and wait for the
736 * response in the confirmation address. The firmware should
737 * write a -1 there to indicate it is alive and well
738 */
739 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
740 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
741
742 buf[0] = htonl(dma_high); /* confirm addr MSW */
743 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 744 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 745
746 /* FIX: All newest firmware should un-protect the bottom of
747 * the sram before handoff. However, the very first interfaces
748 * do not. Therefore the handoff copy must skip the first 8 bytes
749 */
750 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
751 buf[4] = htonl(size - 8); /* length of code */
752 buf[5] = htonl(8); /* where to copy to */
753 buf[6] = htonl(0); /* where to jump to */
754
e700f9f4 755 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
0da34b6d
BG		 756
757 myri10ge_pio_copy(submit, &buf, sizeof(buf));
758 mb();
759 msleep(1);
760 mb();
761 i = 0;
d93ca2a4
BG		 762 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
763 msleep(1 << i);
0da34b6d
BG		 764 i++;
765 }
766 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
767 dev_err(&mgp->pdev->dev, "handoff failed\n");
768 return -ENXIO;
769 }
9a71db72 770 myri10ge_dummy_rdma(mgp, 1);
fa0a90d9 771 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d 772
fa0a90d9 773 return status;
0da34b6d
BG		 774}
775
776static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
777{
778 struct myri10ge_cmd cmd;
779 int status;
780
781 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
782 | (addr[2] << 8) | addr[3]);
783
784 cmd.data1 = ((addr[4] << 8) | (addr[5]));
785
786 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
787 return status;
788}
789
790static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
791{
792 struct myri10ge_cmd cmd;
793 int status, ctl;
794
795 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
796 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
797
798 if (status) {
799 printk(KERN_ERR
800 "myri10ge: %s: Failed to set flow control mode\n",
801 mgp->dev->name);
802 return status;
803 }
804 mgp->pause = pause;
805 return 0;
806}
807
808static void
809myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
810{
811 struct myri10ge_cmd cmd;
812 int status, ctl;
813
814 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
815 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
816 if (status)
817 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
818 mgp->dev->name);
819}
820
0d6ac257 821static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
0da34b6d
BG		 822{
823 struct myri10ge_cmd cmd;
824 int status;
0da34b6d 825 u32 len;
34fdccea
BG		 826 struct page *dmatest_page;
827 dma_addr_t dmatest_bus;
0d6ac257
BG		 828 char *test = " ";
829
830 dmatest_page = alloc_page(GFP_KERNEL);
831 if (!dmatest_page)
832 return -ENOMEM;
833 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
834 DMA_BIDIRECTIONAL);
835
836 /* Run a small DMA test.
837 * The magic multipliers to the length tell the firmware
838 * to do DMA read, write, or read+write tests. The
839 * results are returned in cmd.data0. The upper 16
840 * bits or the return is the number of transfers completed.
841 * The lower 16 bits is the time in 0.5us ticks that the
842 * transfers took to complete.
843 */
844
b53bef84 845 len = mgp->tx_boundary;
0d6ac257
BG		 846
847 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
848 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
849 cmd.data2 = len * 0x10000;
850 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
851 if (status != 0) {
852 test = "read";
853 goto abort;
854 }
855 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
856 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
857 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
858 cmd.data2 = len * 0x1;
859 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
860 if (status != 0) {
861 test = "write";
862 goto abort;
863 }
864 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
865
866 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
867 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
868 cmd.data2 = len * 0x10001;
869 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
870 if (status != 0) {
871 test = "read/write";
872 goto abort;
873 }
874 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
875 (cmd.data0 & 0xffff);
876
877abort:
878 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
879 put_page(dmatest_page);
880
881 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
882 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
883 test, status);
884
885 return status;
886}
887
888static int myri10ge_reset(struct myri10ge_priv *mgp)
889{
890 struct myri10ge_cmd cmd;
0dcffac1
BG		 891 struct myri10ge_slice_state *ss;
892 int i, status;
0d6ac257 893 size_t bytes;
981813d8
BG		 894#ifdef CONFIG_DCA
895 unsigned long dca_tag_off;
896#endif
0da34b6d
BG		 897
898 /* try to send a reset command to the card to see if it
899 * is alive */
900 memset(&cmd, 0, sizeof(cmd));
901 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
902 if (status != 0) {
903 dev_err(&mgp->pdev->dev, "failed reset\n");
904 return -ENXIO;
905 }
0d6ac257
BG		 906
907 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
0dcffac1
BG		 908 /*
909 * Use non-ndis mcp_slot (eg, 4 bytes total,
910 * no toeplitz hash value returned. Older firmware will
911 * not understand this command, but will use the correct
912 * sized mcp_slot, so we ignore error returns
913 */
914 cmd.data0 = MXGEFW_RSS_MCP_SLOT_TYPE_MIN;
915 (void)myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, &cmd, 0);
0da34b6d
BG		 916
917 /* Now exchange information about interrupts */
918
0dcffac1 919 bytes = mgp->max_intr_slots * sizeof(*mgp->ss[0].rx_done.entry);
0da34b6d
BG		 920 cmd.data0 = (u32) bytes;
921 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
0dcffac1
BG		 922
923 /*
924 * Even though we already know how many slices are supported
925 * via myri10ge_probe_slices() MXGEFW_CMD_GET_MAX_RSS_QUEUES
926 * has magic side effects, and must be called after a reset.
927 * It must be called prior to calling any RSS related cmds,
928 * including assigning an interrupt queue for anything but
929 * slice 0. It must also be called *after*
930 * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
931 * the firmware to compute offsets.
932 */
933
934 if (mgp->num_slices > 1) {
935
936 /* ask the maximum number of slices it supports */
937 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
938 &cmd, 0);
939 if (status != 0) {
940 dev_err(&mgp->pdev->dev,
941 "failed to get number of slices\n");
942 }
943
944 /*
945 * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
946 * to setting up the interrupt queue DMA
947 */
948
949 cmd.data0 = mgp->num_slices;
950 cmd.data1 = 1; /* use MSI-X */
951 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
952 &cmd, 0);
953 if (status != 0) {
954 dev_err(&mgp->pdev->dev,
955 "failed to set number of slices\n");
956
957 return status;
958 }
959 }
960 for (i = 0; i < mgp->num_slices; i++) {
961 ss = &mgp->ss[i];
962 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->rx_done.bus);
963 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->rx_done.bus);
964 cmd.data2 = i;
965 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA,
966 &cmd, 0);
967 };
0da34b6d
BG		 968
969 status |=
970 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
0dcffac1
BG		 971 for (i = 0; i < mgp->num_slices; i++) {
972 ss = &mgp->ss[i];
973 ss->irq_claim =
974 (__iomem __be32 *) (mgp->sram + cmd.data0 + 8 * i);
975 }
df30a740
BG		 976 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
977 &cmd, 0);
978 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d 979
0da34b6d
BG		 980 status |= myri10ge_send_cmd
981 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
40f6cff5 982 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d
BG		 983 if (status != 0) {
984 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
985 return status;
986 }
40f6cff5 987 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d 988
981813d8
BG		 989#ifdef CONFIG_DCA
990 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_DCA_OFFSET, &cmd, 0);
991 dca_tag_off = cmd.data0;
992 for (i = 0; i < mgp->num_slices; i++) {
993 ss = &mgp->ss[i];
994 if (status == 0) {
995 ss->dca_tag = (__iomem __be32 *)
996 (mgp->sram + dca_tag_off + 4 * i);
997 } else {
998 ss->dca_tag = NULL;
999 }
1000 }
1001#endif /* CONFIG_DCA */
1002
0da34b6d 1003 /* reset mcp/driver shared state back to 0 */
0dcffac1 1004
c58ac5ca 1005 mgp->link_changes = 0;
0dcffac1
BG		 1006 for (i = 0; i < mgp->num_slices; i++) {
1007 ss = &mgp->ss[i];
1008
1009 memset(ss->rx_done.entry, 0, bytes);
1010 ss->tx.req = 0;
1011 ss->tx.done = 0;
1012 ss->tx.pkt_start = 0;
1013 ss->tx.pkt_done = 0;
1014 ss->rx_big.cnt = 0;
1015 ss->rx_small.cnt = 0;
1016 ss->rx_done.idx = 0;
1017 ss->rx_done.cnt = 0;
1018 ss->tx.wake_queue = 0;
1019 ss->tx.stop_queue = 0;
1020 }
1021
0da34b6d 1022 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
0da34b6d 1023 myri10ge_change_pause(mgp, mgp->pause);
2f76216f 1024 myri10ge_set_multicast_list(mgp->dev);
0da34b6d
BG		 1025 return status;
1026}
1027
981813d8
BG		 1028#ifdef CONFIG_DCA
1029static void
1030myri10ge_write_dca(struct myri10ge_slice_state *ss, int cpu, int tag)
1031{
1032 ss->cpu = cpu;
1033 ss->cached_dca_tag = tag;
1034 put_be32(htonl(tag), ss->dca_tag);
1035}
1036
1037static inline void myri10ge_update_dca(struct myri10ge_slice_state *ss)
1038{
1039 int cpu = get_cpu();
1040 int tag;
1041
1042 if (cpu != ss->cpu) {
1043 tag = dca_get_tag(cpu);
1044 if (ss->cached_dca_tag != tag)
1045 myri10ge_write_dca(ss, cpu, tag);
1046 }
1047 put_cpu();
1048}
1049
1050static void myri10ge_setup_dca(struct myri10ge_priv *mgp)
1051{
1052 int err, i;
1053 struct pci_dev *pdev = mgp->pdev;
1054
1055 if (mgp->ss[0].dca_tag == NULL || mgp->dca_enabled)
1056 return;
1057 if (!myri10ge_dca) {
1058 dev_err(&pdev->dev, "dca disabled by administrator\n");
1059 return;
1060 }
1061 err = dca_add_requester(&pdev->dev);
1062 if (err) {
1063 dev_err(&pdev->dev,
1064 "dca_add_requester() failed, err=%d\n", err);
1065 return;
1066 }
1067 mgp->dca_enabled = 1;
1068 for (i = 0; i < mgp->num_slices; i++)
1069 myri10ge_write_dca(&mgp->ss[i], -1, 0);
1070}
1071
1072static void myri10ge_teardown_dca(struct myri10ge_priv *mgp)
1073{
1074 struct pci_dev *pdev = mgp->pdev;
1075 int err;
1076
1077 if (!mgp->dca_enabled)
1078 return;
1079 mgp->dca_enabled = 0;
1080 err = dca_remove_requester(&pdev->dev);
1081}
1082
1083static int myri10ge_notify_dca_device(struct device *dev, void *data)
1084{
1085 struct myri10ge_priv *mgp;
1086 unsigned long event;
1087
1088 mgp = dev_get_drvdata(dev);
1089 event = *(unsigned long *)data;
1090
1091 if (event == DCA_PROVIDER_ADD)
1092 myri10ge_setup_dca(mgp);
1093 else if (event == DCA_PROVIDER_REMOVE)
1094 myri10ge_teardown_dca(mgp);
1095 return 0;
1096}
1097#endif /* CONFIG_DCA */
1098
0da34b6d
BG		 1099static inline void
1100myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
1101 struct mcp_kreq_ether_recv *src)
1102{
40f6cff5 1103 __be32 low;
0da34b6d
BG		 1104
1105 low = src->addr_low;
40f6cff5 1106 src->addr_low = htonl(DMA_32BIT_MASK);
e67bda55
BG		 1107 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
1108 mb();
1109 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
0da34b6d
BG		 1110 mb();
1111 src->addr_low = low;
40f6cff5 1112 put_be32(low, &dst->addr_low);
0da34b6d
BG		 1113 mb();
1114}
1115
40f6cff5 1116static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
0da34b6d
BG		 1117{
1118 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
1119
40f6cff5 1120 if ((skb->protocol == htons(ETH_P_8021Q)) &&
0da34b6d
BG		 1121 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
1122 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
1123 skb->csum = hw_csum;
84fa7933 1124 skb->ip_summed = CHECKSUM_COMPLETE;
0da34b6d
BG		 1125 }
1126}
1127
dd50f336
BG		 1128static inline void
1129myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
1130 struct skb_frag_struct *rx_frags, int len, int hlen)
1131{
1132 struct skb_frag_struct *skb_frags;
1133
1134 skb->len = skb->data_len = len;
1135 skb->truesize = len + sizeof(struct sk_buff);
1136 /* attach the page(s) */
1137
1138 skb_frags = skb_shinfo(skb)->frags;
1139 while (len > 0) {
1140 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
1141 len -= rx_frags->size;
1142 skb_frags++;
1143 rx_frags++;
1144 skb_shinfo(skb)->nr_frags++;
1145 }
1146
1147 /* pskb_may_pull is not available in irq context, but
1148 * skb_pull() (for ether_pad and eth_type_trans()) requires
1149 * the beginning of the packet in skb_headlen(), move it
1150 * manually */
27d7ff46 1151 skb_copy_to_linear_data(skb, va, hlen);
dd50f336
BG		 1152 skb_shinfo(skb)->frags[0].page_offset += hlen;
1153 skb_shinfo(skb)->frags[0].size -= hlen;
1154 skb->data_len -= hlen;
1155 skb->tail += hlen;
1156 skb_pull(skb, MXGEFW_PAD);
1157}
1158
1159static void
1160myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1161 int bytes, int watchdog)
1162{
1163 struct page *page;
1164 int idx;
1165
1166 if (unlikely(rx->watchdog_needed && !watchdog))
1167 return;
1168
1169 /* try to refill entire ring */
1170 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
1171 idx = rx->fill_cnt & rx->mask;
ae8509b1 1172 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
dd50f336
BG		 1173 /* we can use part of previous page */
1174 get_page(rx->page);
1175 } else {
1176 /* we need a new page */
1177 page =
1178 alloc_pages(GFP_ATOMIC | __GFP_COMP,
1179 MYRI10GE_ALLOC_ORDER);
1180 if (unlikely(page == NULL)) {
1181 if (rx->fill_cnt - rx->cnt < 16)
1182 rx->watchdog_needed = 1;
1183 return;
1184 }
1185 rx->page = page;
1186 rx->page_offset = 0;
1187 rx->bus = pci_map_page(mgp->pdev, page, 0,
1188 MYRI10GE_ALLOC_SIZE,
1189 PCI_DMA_FROMDEVICE);
1190 }
1191 rx->info[idx].page = rx->page;
1192 rx->info[idx].page_offset = rx->page_offset;
1193 /* note that this is the address of the start of the
1194 * page */
1195 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
1196 rx->shadow[idx].addr_low =
1197 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
1198 rx->shadow[idx].addr_high =
1199 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
1200
1201 /* start next packet on a cacheline boundary */
1202 rx->page_offset += SKB_DATA_ALIGN(bytes);
ae8509b1
BG		 1203
1204#if MYRI10GE_ALLOC_SIZE > 4096
1205 /* don't cross a 4KB boundary */
1206 if ((rx->page_offset >> 12) !=
1207 ((rx->page_offset + bytes - 1) >> 12))
1208 rx->page_offset = (rx->page_offset + 4096) & ~4095;
1209#endif
dd50f336
BG		 1210 rx->fill_cnt++;
1211
1212 /* copy 8 descriptors to the firmware at a time */
1213 if ((idx & 7) == 7) {
e454e7e2
BG		 1214 myri10ge_submit_8rx(&rx->lanai[idx - 7],
1215 &rx->shadow[idx - 7]);
dd50f336
BG		 1216 }
1217 }
1218}
1219
1220static inline void
1221myri10ge_unmap_rx_page(struct pci_dev *pdev,
1222 struct myri10ge_rx_buffer_state *info, int bytes)
1223{
1224 /* unmap the recvd page if we're the only or last user of it */
1225 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1226 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1227 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
1228 & ~(MYRI10GE_ALLOC_SIZE - 1)),
1229 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1230 }
1231}
1232
1233#define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
1234 * page into an skb */
1235
1236static inline int
b53bef84 1237myri10ge_rx_done(struct myri10ge_slice_state *ss, struct myri10ge_rx_buf *rx,
52ea6fb3 1238 int bytes, int len, __wsum csum)
dd50f336 1239{
b53bef84 1240 struct myri10ge_priv *mgp = ss->mgp;
dd50f336
BG		 1241 struct sk_buff *skb;
1242 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1243 int i, idx, hlen, remainder;
1244 struct pci_dev *pdev = mgp->pdev;
1245 struct net_device *dev = mgp->dev;
1246 u8 *va;
1247
1248 len += MXGEFW_PAD;
1249 idx = rx->cnt & rx->mask;
1250 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1251 prefetch(va);
1252 /* Fill skb_frag_struct(s) with data from our receive */
1253 for (i = 0, remainder = len; remainder > 0; i++) {
1254 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1255 rx_frags[i].page = rx->info[idx].page;
1256 rx_frags[i].page_offset = rx->info[idx].page_offset;
1257 if (remainder < MYRI10GE_ALLOC_SIZE)
1258 rx_frags[i].size = remainder;
1259 else
1260 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1261 rx->cnt++;
1262 idx = rx->cnt & rx->mask;
1263 remainder -= MYRI10GE_ALLOC_SIZE;
1264 }
1265
1e6e9342
AG		 1266 if (mgp->csum_flag && myri10ge_lro) {
1267 rx_frags[0].page_offset += MXGEFW_PAD;
1268 rx_frags[0].size -= MXGEFW_PAD;
1269 len -= MXGEFW_PAD;
b53bef84 1270 lro_receive_frags(&ss->rx_done.lro_mgr, rx_frags,
b53bef84 1271 /* opaque, will come back in get_frag_header */
0dcffac1 1272 len, len,
b53bef84 1273 (void *)(__force unsigned long)csum, csum);
0dcffac1 1274
1e6e9342
AG		 1275 return 1;
1276 }
1277
dd50f336
BG		 1278 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1279
e636b2ea
BG		 1280 /* allocate an skb to attach the page(s) to. This is done
1281 * after trying LRO, so as to avoid skb allocation overheads */
dd50f336
BG		 1282
1283 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1284 if (unlikely(skb == NULL)) {
1285 mgp->stats.rx_dropped++;
1286 do {
1287 i--;
1288 put_page(rx_frags[i].page);
1289 } while (i != 0);
1290 return 0;
1291 }
1292
1293 /* Attach the pages to the skb, and trim off any padding */
1294 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1295 if (skb_shinfo(skb)->frags[0].size <= 0) {
1296 put_page(skb_shinfo(skb)->frags[0].page);
1297 skb_shinfo(skb)->nr_frags = 0;
1298 }
1299 skb->protocol = eth_type_trans(skb, dev);
dd50f336
BG		 1300
1301 if (mgp->csum_flag) {
1302 if ((skb->protocol == htons(ETH_P_IP)) ||
1303 (skb->protocol == htons(ETH_P_IPV6))) {
1304 skb->csum = csum;
1305 skb->ip_summed = CHECKSUM_COMPLETE;
1306 } else
1307 myri10ge_vlan_ip_csum(skb, csum);
1308 }
1309 netif_receive_skb(skb);
1310 dev->last_rx = jiffies;
1311 return 1;
1312}
1313
b53bef84
BG		 1314static inline void
1315myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index)
0da34b6d 1316{
b53bef84
BG		 1317 struct pci_dev *pdev = ss->mgp->pdev;
1318 struct myri10ge_tx_buf *tx = &ss->tx;
0da34b6d
BG		 1319 struct sk_buff *skb;
1320 int idx, len;
0da34b6d
BG		 1321
1322 while (tx->pkt_done != mcp_index) {
1323 idx = tx->done & tx->mask;
1324 skb = tx->info[idx].skb;
1325
1326 /* Mark as free */
1327 tx->info[idx].skb = NULL;
1328 if (tx->info[idx].last) {
1329 tx->pkt_done++;
1330 tx->info[idx].last = 0;
1331 }
1332 tx->done++;
1333 len = pci_unmap_len(&tx->info[idx], len);
1334 pci_unmap_len_set(&tx->info[idx], len, 0);
1335 if (skb) {
b53bef84
BG		 1336 ss->stats.tx_bytes += skb->len;
1337 ss->stats.tx_packets++;
0da34b6d
BG		 1338 dev_kfree_skb_irq(skb);
1339 if (len)
1340 pci_unmap_single(pdev,
1341 pci_unmap_addr(&tx->info[idx],
1342 bus), len,
1343 PCI_DMA_TODEVICE);
1344 } else {
1345 if (len)
1346 pci_unmap_page(pdev,
1347 pci_unmap_addr(&tx->info[idx],
1348 bus), len,
1349 PCI_DMA_TODEVICE);
1350 }
0da34b6d
BG		 1351 }
1352 /* start the queue if we've stopped it */
b53bef84 1353 if (netif_queue_stopped(ss->dev)
0da34b6d 1354 && tx->req - tx->done < (tx->mask >> 1)) {
b53bef84
BG		 1355 tx->wake_queue++;
1356 netif_wake_queue(ss->dev);
0da34b6d
BG		 1357 }
1358}
1359
b53bef84
BG		 1360static inline int
1361myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
0da34b6d 1362{
b53bef84
BG		 1363 struct myri10ge_rx_done *rx_done = &ss->rx_done;
1364 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d
BG		 1365 unsigned long rx_bytes = 0;
1366 unsigned long rx_packets = 0;
1367 unsigned long rx_ok;
1368
1369 int idx = rx_done->idx;
1370 int cnt = rx_done->cnt;
bea3348e 1371 int work_done = 0;
0da34b6d 1372 u16 length;
40f6cff5 1373 __wsum checksum;
0da34b6d 1374
c956a240 1375 while (rx_done->entry[idx].length != 0 && work_done < budget) {
0da34b6d
BG		 1376 length = ntohs(rx_done->entry[idx].length);
1377 rx_done->entry[idx].length = 0;
40f6cff5 1378 checksum = csum_unfold(rx_done->entry[idx].checksum);
0da34b6d 1379 if (length <= mgp->small_bytes)
b53bef84 1380 rx_ok = myri10ge_rx_done(ss, &ss->rx_small,
52ea6fb3
BG		 1381 mgp->small_bytes,
1382 length, checksum);
0da34b6d 1383 else
b53bef84 1384 rx_ok = myri10ge_rx_done(ss, &ss->rx_big,
52ea6fb3
BG		 1385 mgp->big_bytes,
1386 length, checksum);
0da34b6d
BG		 1387 rx_packets += rx_ok;
1388 rx_bytes += rx_ok * (unsigned long)length;
1389 cnt++;
014377a1 1390 idx = cnt & (mgp->max_intr_slots - 1);
c956a240 1391 work_done++;
0da34b6d
BG		 1392 }
1393 rx_done->idx = idx;
1394 rx_done->cnt = cnt;
b53bef84
BG		 1395 ss->stats.rx_packets += rx_packets;
1396 ss->stats.rx_bytes += rx_bytes;
c7dab99b 1397
1e6e9342
AG		 1398 if (myri10ge_lro)
1399 lro_flush_all(&rx_done->lro_mgr);
1400
c7dab99b 1401 /* restock receive rings if needed */
b53bef84
BG		 1402 if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
1403 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
c7dab99b 1404 mgp->small_bytes + MXGEFW_PAD, 0);
b53bef84
BG		 1405 if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh)
1406 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
c7dab99b 1407
bea3348e 1408 return work_done;
0da34b6d
BG		 1409}
1410
1411static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1412{
0dcffac1 1413 struct mcp_irq_data *stats = mgp->ss[0].fw_stats;
0da34b6d
BG		 1414
1415 if (unlikely(stats->stats_updated)) {
798a95db
BG		 1416 unsigned link_up = ntohl(stats->link_up);
1417 if (mgp->link_state != link_up) {
1418 mgp->link_state = link_up;
1419
1420 if (mgp->link_state == MXGEFW_LINK_UP) {
c58ac5ca
BG		 1421 if (netif_msg_link(mgp))
1422 printk(KERN_INFO
1423 "myri10ge: %s: link up\n",
1424 mgp->dev->name);
0da34b6d 1425 netif_carrier_on(mgp->dev);
c58ac5ca 1426 mgp->link_changes++;
0da34b6d 1427 } else {
c58ac5ca
BG		 1428 if (netif_msg_link(mgp))
1429 printk(KERN_INFO
798a95db
BG		 1430 "myri10ge: %s: link %s\n",
1431 mgp->dev->name,
1432 (link_up == MXGEFW_LINK_MYRINET ?
1433 "mismatch (Myrinet detected)" :
1434 "down"));
0da34b6d 1435 netif_carrier_off(mgp->dev);
c58ac5ca 1436 mgp->link_changes++;
0da34b6d
BG		 1437 }
1438 }
1439 if (mgp->rdma_tags_available !=
b53bef84 1440 ntohl(stats->rdma_tags_available)) {
0da34b6d 1441 mgp->rdma_tags_available =
b53bef84 1442 ntohl(stats->rdma_tags_available);
0da34b6d
BG		 1443 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1444 "%d tags left\n", mgp->dev->name,
1445 mgp->rdma_tags_available);
1446 }
1447 mgp->down_cnt += stats->link_down;
1448 if (stats->link_down)
1449 wake_up(&mgp->down_wq);
1450 }
1451}
1452
bea3348e 1453static int myri10ge_poll(struct napi_struct *napi, int budget)
0da34b6d 1454{
b53bef84
BG		 1455 struct myri10ge_slice_state *ss =
1456 container_of(napi, struct myri10ge_slice_state, napi);
1457 struct net_device *netdev = ss->mgp->dev;
bea3348e 1458 int work_done;
0da34b6d 1459
981813d8
BG		 1460#ifdef CONFIG_DCA
1461 if (ss->mgp->dca_enabled)
1462 myri10ge_update_dca(ss);
1463#endif
1464
0da34b6d 1465 /* process as many rx events as NAPI will allow */
b53bef84 1466 work_done = myri10ge_clean_rx_done(ss, budget);
0da34b6d 1467
4ec24119 1468 if (work_done < budget) {
bea3348e 1469 netif_rx_complete(netdev, napi);
b53bef84 1470 put_be32(htonl(3), ss->irq_claim);
0da34b6d 1471 }
bea3348e 1472 return work_done;
0da34b6d
BG		 1473}
1474
7d12e780 1475static irqreturn_t myri10ge_intr(int irq, void *arg)
0da34b6d 1476{
b53bef84
BG		 1477 struct myri10ge_slice_state *ss = arg;
1478 struct myri10ge_priv *mgp = ss->mgp;
1479 struct mcp_irq_data *stats = ss->fw_stats;
1480 struct myri10ge_tx_buf *tx = &ss->tx;
0da34b6d
BG		 1481 u32 send_done_count;
1482 int i;
1483
0dcffac1
BG		 1484 /* an interrupt on a non-zero slice is implicitly valid
1485 * since MSI-X irqs are not shared */
1486 if (ss != mgp->ss) {
1487 netif_rx_schedule(ss->dev, &ss->napi);
1488 return (IRQ_HANDLED);
1489 }
1490
0da34b6d
BG		 1491 /* make sure it is our IRQ, and that the DMA has finished */
1492 if (unlikely(!stats->valid))
1493 return (IRQ_NONE);
1494
1495 /* low bit indicates receives are present, so schedule
1496 * napi poll handler */
1497 if (stats->valid & 1)
b53bef84 1498 netif_rx_schedule(ss->dev, &ss->napi);
0da34b6d 1499
0dcffac1 1500 if (!mgp->msi_enabled && !mgp->msix_enabled) {
40f6cff5 1501 put_be32(0, mgp->irq_deassert);
0da34b6d
BG		 1502 if (!myri10ge_deassert_wait)
1503 stats->valid = 0;
1504 mb();
1505 } else
1506 stats->valid = 0;
1507
1508 /* Wait for IRQ line to go low, if using INTx */
1509 i = 0;
1510 while (1) {
1511 i++;
1512 /* check for transmit completes and receives */
1513 send_done_count = ntohl(stats->send_done_count);
1514 if (send_done_count != tx->pkt_done)
b53bef84 1515 myri10ge_tx_done(ss, (int)send_done_count);
0da34b6d
BG		 1516 if (unlikely(i > myri10ge_max_irq_loops)) {
1517 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1518 mgp->dev->name);
1519 stats->valid = 0;
1520 schedule_work(&mgp->watchdog_work);
1521 }
1522 if (likely(stats->valid == 0))
1523 break;
1524 cpu_relax();
1525 barrier();
1526 }
1527
1528 myri10ge_check_statblock(mgp);
1529
b53bef84 1530 put_be32(htonl(3), ss->irq_claim + 1);
0da34b6d
BG		 1531 return (IRQ_HANDLED);
1532}
1533
1534static int
1535myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1536{
c0bf8801
BG		 1537 struct myri10ge_priv *mgp = netdev_priv(netdev);
1538 char *ptr;
1539 int i;
1540
0da34b6d
BG		 1541 cmd->autoneg = AUTONEG_DISABLE;
1542 cmd->speed = SPEED_10000;
1543 cmd->duplex = DUPLEX_FULL;
c0bf8801
BG		 1544
1545 /*
1546 * parse the product code to deterimine the interface type
1547 * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1548 * after the 3rd dash in the driver's cached copy of the
1549 * EEPROM's product code string.
1550 */
1551 ptr = mgp->product_code_string;
1552 if (ptr == NULL) {
1553 printk(KERN_ERR "myri10ge: %s: Missing product code\n",
99f5f87e 1554 netdev->name);
c0bf8801
BG		 1555 return 0;
1556 }
1557 for (i = 0; i < 3; i++, ptr++) {
1558 ptr = strchr(ptr, '-');
1559 if (ptr == NULL) {
1560 printk(KERN_ERR "myri10ge: %s: Invalid product "
1561 "code %s\n", netdev->name,
1562 mgp->product_code_string);
1563 return 0;
1564 }
1565 }
1566 if (*ptr == 'R' || *ptr == 'Q') {
1567 /* We've found either an XFP or quad ribbon fiber */
1568 cmd->port = PORT_FIBRE;
1569 }
0da34b6d
BG		 1570 return 0;
1571}
1572
1573static void
1574myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1575{
1576 struct myri10ge_priv *mgp = netdev_priv(netdev);
1577
1578 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1579 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1580 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1581 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1582}
1583
1584static int
1585myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1586{
1587 struct myri10ge_priv *mgp = netdev_priv(netdev);
99f5f87e 1588
0da34b6d
BG		 1589 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1590 return 0;
1591}
1592
1593static int
1594myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1595{
1596 struct myri10ge_priv *mgp = netdev_priv(netdev);
1597
1598 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
40f6cff5 1599 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 1600 return 0;
1601}
1602
1603static void
1604myri10ge_get_pauseparam(struct net_device *netdev,
1605 struct ethtool_pauseparam *pause)
1606{
1607 struct myri10ge_priv *mgp = netdev_priv(netdev);
1608
1609 pause->autoneg = 0;
1610 pause->rx_pause = mgp->pause;
1611 pause->tx_pause = mgp->pause;
1612}
1613
1614static int
1615myri10ge_set_pauseparam(struct net_device *netdev,
1616 struct ethtool_pauseparam *pause)
1617{
1618 struct myri10ge_priv *mgp = netdev_priv(netdev);
1619
1620 if (pause->tx_pause != mgp->pause)
1621 return myri10ge_change_pause(mgp, pause->tx_pause);
1622 if (pause->rx_pause != mgp->pause)
1623 return myri10ge_change_pause(mgp, pause->tx_pause);
1624 if (pause->autoneg != 0)
1625 return -EINVAL;
1626 return 0;
1627}
1628
1629static void
1630myri10ge_get_ringparam(struct net_device *netdev,
1631 struct ethtool_ringparam *ring)
1632{
1633 struct myri10ge_priv *mgp = netdev_priv(netdev);
1634
0dcffac1
BG		 1635 ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1;
1636 ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1;
0da34b6d 1637 ring->rx_jumbo_max_pending = 0;
0dcffac1 1638 ring->tx_max_pending = mgp->ss[0].rx_small.mask + 1;
0da34b6d
BG		 1639 ring->rx_mini_pending = ring->rx_mini_max_pending;
1640 ring->rx_pending = ring->rx_max_pending;
1641 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1642 ring->tx_pending = ring->tx_max_pending;
1643}
1644
1645static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1646{
1647 struct myri10ge_priv *mgp = netdev_priv(netdev);
99f5f87e 1648
0da34b6d
BG		 1649 if (mgp->csum_flag)
1650 return 1;
1651 else
1652 return 0;
1653}
1654
1655static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1656{
1657 struct myri10ge_priv *mgp = netdev_priv(netdev);
99f5f87e 1658
0da34b6d
BG		 1659 if (csum_enabled)
1660 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1661 else
1662 mgp->csum_flag = 0;
1663 return 0;
1664}
1665
4f93fde0
BG		 1666static int myri10ge_set_tso(struct net_device *netdev, u32 tso_enabled)
1667{
1668 struct myri10ge_priv *mgp = netdev_priv(netdev);
1669 unsigned long flags = mgp->features & (NETIF_F_TSO6 | NETIF_F_TSO);
1670
1671 if (tso_enabled)
1672 netdev->features |= flags;
1673 else
1674 netdev->features &= ~flags;
1675 return 0;
1676}
1677
b53bef84 1678static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
0da34b6d
BG		 1679 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1680 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1681 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1682 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1683 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1684 "tx_heartbeat_errors", "tx_window_errors",
1685 /* device-specific stats */
0dcffac1 1686 "tx_boundary", "WC", "irq", "MSI", "MSIX",
0da34b6d 1687 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
b53bef84 1688 "serial_number", "watchdog_resets",
981813d8
BG		 1689#ifdef CONFIG_DCA
1690 "dca_capable", "dca_enabled",
1691#endif
c58ac5ca 1692 "link_changes", "link_up", "dropped_link_overflow",
cee505db
BG		 1693 "dropped_link_error_or_filtered",
1694 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1695 "dropped_unicast_filtered", "dropped_multicast_filtered",
0da34b6d 1696 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
b53bef84
BG		 1697 "dropped_no_big_buffer"
1698};
1699
1700static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1701 "----------- slice ---------",
1702 "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1703 "rx_small_cnt", "rx_big_cnt",
1704 "wake_queue", "stop_queue", "tx_linearized", "LRO aggregated",
1705 "LRO flushed",
1e6e9342 1706 "LRO avg aggr", "LRO no_desc"
0da34b6d
BG		 1707};
1708
1709#define MYRI10GE_NET_STATS_LEN 21
b53bef84
BG		 1710#define MYRI10GE_MAIN_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_main_stats)
1711#define MYRI10GE_SLICE_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_slice_stats)
0da34b6d
BG		 1712
1713static void
1714myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1715{
0dcffac1
BG		 1716 struct myri10ge_priv *mgp = netdev_priv(netdev);
1717 int i;
1718
0da34b6d
BG		 1719 switch (stringset) {
1720 case ETH_SS_STATS:
b53bef84
BG		 1721 memcpy(data, *myri10ge_gstrings_main_stats,
1722 sizeof(myri10ge_gstrings_main_stats));
1723 data += sizeof(myri10ge_gstrings_main_stats);
0dcffac1
BG		 1724 for (i = 0; i < mgp->num_slices; i++) {
1725 memcpy(data, *myri10ge_gstrings_slice_stats,
1726 sizeof(myri10ge_gstrings_slice_stats));
1727 data += sizeof(myri10ge_gstrings_slice_stats);
1728 }
0da34b6d
BG		 1729 break;
1730 }
1731}
1732
b9f2c044 1733static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
0da34b6d 1734{
0dcffac1
BG		 1735 struct myri10ge_priv *mgp = netdev_priv(netdev);
1736
b9f2c044
JG		 1737 switch (sset) {
1738 case ETH_SS_STATS:
0dcffac1
BG		 1739 return MYRI10GE_MAIN_STATS_LEN +
1740 mgp->num_slices * MYRI10GE_SLICE_STATS_LEN;
b9f2c044
JG		 1741 default:
1742 return -EOPNOTSUPP;
1743 }
0da34b6d
BG		 1744}
1745
1746static void
1747myri10ge_get_ethtool_stats(struct net_device *netdev,
1748 struct ethtool_stats *stats, u64 * data)
1749{
1750 struct myri10ge_priv *mgp = netdev_priv(netdev);
b53bef84 1751 struct myri10ge_slice_state *ss;
0dcffac1 1752 int slice;
0da34b6d
BG		 1753 int i;
1754
1755 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1756 data[i] = ((unsigned long *)&mgp->stats)[i];
1757
b53bef84 1758 data[i++] = (unsigned int)mgp->tx_boundary;
276e26c3 1759 data[i++] = (unsigned int)mgp->wc_enabled;
2c1a1088
BG		 1760 data[i++] = (unsigned int)mgp->pdev->irq;
1761 data[i++] = (unsigned int)mgp->msi_enabled;
0dcffac1 1762 data[i++] = (unsigned int)mgp->msix_enabled;
0da34b6d
BG		 1763 data[i++] = (unsigned int)mgp->read_dma;
1764 data[i++] = (unsigned int)mgp->write_dma;
1765 data[i++] = (unsigned int)mgp->read_write_dma;
1766 data[i++] = (unsigned int)mgp->serial_number;
0da34b6d 1767 data[i++] = (unsigned int)mgp->watchdog_resets;
981813d8
BG		 1768#ifdef CONFIG_DCA
1769 data[i++] = (unsigned int)(mgp->ss[0].dca_tag != NULL);
1770 data[i++] = (unsigned int)(mgp->dca_enabled);
1771#endif
c58ac5ca 1772 data[i++] = (unsigned int)mgp->link_changes;
b53bef84
BG		 1773
1774 /* firmware stats are useful only in the first slice */
0dcffac1 1775 ss = &mgp->ss[0];
b53bef84
BG		 1776 data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1777 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
cee505db 1778 data[i++] =
b53bef84
BG		 1779 (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered);
1780 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause);
1781 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy);
1782 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32);
1783 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered);
85a7ea1b 1784 data[i++] =
b53bef84
BG		 1785 (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered);
1786 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt);
1787 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun);
1788 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
1789 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
1790
0dcffac1
BG		 1791 for (slice = 0; slice < mgp->num_slices; slice++) {
1792 ss = &mgp->ss[slice];
1793 data[i++] = slice;
1794 data[i++] = (unsigned int)ss->tx.pkt_start;
1795 data[i++] = (unsigned int)ss->tx.pkt_done;
1796 data[i++] = (unsigned int)ss->tx.req;
1797 data[i++] = (unsigned int)ss->tx.done;
1798 data[i++] = (unsigned int)ss->rx_small.cnt;
1799 data[i++] = (unsigned int)ss->rx_big.cnt;
1800 data[i++] = (unsigned int)ss->tx.wake_queue;
1801 data[i++] = (unsigned int)ss->tx.stop_queue;
1802 data[i++] = (unsigned int)ss->tx.linearized;
1803 data[i++] = ss->rx_done.lro_mgr.stats.aggregated;
1804 data[i++] = ss->rx_done.lro_mgr.stats.flushed;
1805 if (ss->rx_done.lro_mgr.stats.flushed)
1806 data[i++] = ss->rx_done.lro_mgr.stats.aggregated /
1807 ss->rx_done.lro_mgr.stats.flushed;
1808 else
1809 data[i++] = 0;
1810 data[i++] = ss->rx_done.lro_mgr.stats.no_desc;
1811 }
0da34b6d
BG		 1812}
1813
c58ac5ca
BG		 1814static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1815{
1816 struct myri10ge_priv *mgp = netdev_priv(netdev);
1817 mgp->msg_enable = value;
1818}
1819
1820static u32 myri10ge_get_msglevel(struct net_device *netdev)
1821{
1822 struct myri10ge_priv *mgp = netdev_priv(netdev);
1823 return mgp->msg_enable;
1824}
1825
7282d491 1826static const struct ethtool_ops myri10ge_ethtool_ops = {
0da34b6d
BG		 1827 .get_settings = myri10ge_get_settings,
1828 .get_drvinfo = myri10ge_get_drvinfo,
1829 .get_coalesce = myri10ge_get_coalesce,
1830 .set_coalesce = myri10ge_set_coalesce,
1831 .get_pauseparam = myri10ge_get_pauseparam,
1832 .set_pauseparam = myri10ge_set_pauseparam,
1833 .get_ringparam = myri10ge_get_ringparam,
1834 .get_rx_csum = myri10ge_get_rx_csum,
1835 .set_rx_csum = myri10ge_set_rx_csum,
b10c0668 1836 .set_tx_csum = ethtool_op_set_tx_hw_csum,
0da34b6d 1837 .set_sg = ethtool_op_set_sg,
4f93fde0 1838 .set_tso = myri10ge_set_tso,
6ffdd071 1839 .get_link = ethtool_op_get_link,
0da34b6d 1840 .get_strings = myri10ge_get_strings,
b9f2c044 1841 .get_sset_count = myri10ge_get_sset_count,
c58ac5ca
BG		 1842 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1843 .set_msglevel = myri10ge_set_msglevel,
1844 .get_msglevel = myri10ge_get_msglevel
0da34b6d
BG		 1845};
1846
b53bef84 1847static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
0da34b6d 1848{
b53bef84 1849 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d 1850 struct myri10ge_cmd cmd;
b53bef84 1851 struct net_device *dev = mgp->dev;
0da34b6d
BG		 1852 int tx_ring_size, rx_ring_size;
1853 int tx_ring_entries, rx_ring_entries;
0dcffac1 1854 int i, slice, status;
0da34b6d
BG		 1855 size_t bytes;
1856
0da34b6d 1857 /* get ring sizes */
0dcffac1
BG		 1858 slice = ss - mgp->ss;
1859 cmd.data0 = slice;
0da34b6d
BG		 1860 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1861 tx_ring_size = cmd.data0;
0dcffac1 1862 cmd.data0 = slice;
0da34b6d 1863 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
355c7265
BG		 1864 if (status != 0)
1865 return status;
0da34b6d
BG		 1866 rx_ring_size = cmd.data0;
1867
1868 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1869 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
b53bef84
BG		 1870 ss->tx.mask = tx_ring_entries - 1;
1871 ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
0da34b6d 1872
355c7265
BG		 1873 status = -ENOMEM;
1874
0da34b6d
BG		 1875 /* allocate the host shadow rings */
1876
1877 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
b53bef84
BG		 1878 * sizeof(*ss->tx.req_list);
1879 ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1880 if (ss->tx.req_bytes == NULL)
0da34b6d
BG		 1881 goto abort_with_nothing;
1882
1883 /* ensure req_list entries are aligned to 8 bytes */
b53bef84
BG		 1884 ss->tx.req_list = (struct mcp_kreq_ether_send *)
1885 ALIGN((unsigned long)ss->tx.req_bytes, 8);
0da34b6d 1886
b53bef84
BG		 1887 bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow);
1888 ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1889 if (ss->rx_small.shadow == NULL)
0da34b6d
BG		 1890 goto abort_with_tx_req_bytes;
1891
b53bef84
BG		 1892 bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow);
1893 ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1894 if (ss->rx_big.shadow == NULL)
0da34b6d
BG		 1895 goto abort_with_rx_small_shadow;
1896
1897 /* allocate the host info rings */
1898
b53bef84
BG		 1899 bytes = tx_ring_entries * sizeof(*ss->tx.info);
1900 ss->tx.info = kzalloc(bytes, GFP_KERNEL);
1901 if (ss->tx.info == NULL)
0da34b6d
BG		 1902 goto abort_with_rx_big_shadow;
1903
b53bef84
BG		 1904 bytes = rx_ring_entries * sizeof(*ss->rx_small.info);
1905 ss->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1906 if (ss->rx_small.info == NULL)
0da34b6d
BG		 1907 goto abort_with_tx_info;
1908
b53bef84
BG		 1909 bytes = rx_ring_entries * sizeof(*ss->rx_big.info);
1910 ss->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1911 if (ss->rx_big.info == NULL)
0da34b6d
BG		 1912 goto abort_with_rx_small_info;
1913
1914 /* Fill the receive rings */
b53bef84
BG		 1915 ss->rx_big.cnt = 0;
1916 ss->rx_small.cnt = 0;
1917 ss->rx_big.fill_cnt = 0;
1918 ss->rx_small.fill_cnt = 0;
1919 ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1920 ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1921 ss->rx_small.watchdog_needed = 0;
1922 ss->rx_big.watchdog_needed = 0;
1923 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
c7dab99b 1924 mgp->small_bytes + MXGEFW_PAD, 0);
0da34b6d 1925
b53bef84 1926 if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
0dcffac1
BG		 1927 printk(KERN_ERR
1928 "myri10ge: %s:slice-%d: alloced only %d small bufs\n",
1929 dev->name, slice, ss->rx_small.fill_cnt);
c7dab99b 1930 goto abort_with_rx_small_ring;
0da34b6d
BG		 1931 }
1932
b53bef84
BG		 1933 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1934 if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
0dcffac1
BG		 1935 printk(KERN_ERR
1936 "myri10ge: %s:slice-%d: alloced only %d big bufs\n",
1937 dev->name, slice, ss->rx_big.fill_cnt);
c7dab99b 1938 goto abort_with_rx_big_ring;
0da34b6d
BG		 1939 }
1940
1941 return 0;
1942
1943abort_with_rx_big_ring:
b53bef84
BG		 1944 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
1945 int idx = i & ss->rx_big.mask;
1946 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 1947 mgp->big_bytes);
b53bef84 1948 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 1949 }
1950
1951abort_with_rx_small_ring:
b53bef84
BG		 1952 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
1953 int idx = i & ss->rx_small.mask;
1954 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 1955 mgp->small_bytes + MXGEFW_PAD);
b53bef84 1956 put_page(ss->rx_small.info[idx].page);
0da34b6d 1957 }
c7dab99b 1958
b53bef84 1959 kfree(ss->rx_big.info);
0da34b6d
BG		 1960
1961abort_with_rx_small_info:
b53bef84 1962 kfree(ss->rx_small.info);
0da34b6d
BG		 1963
1964abort_with_tx_info:
b53bef84 1965 kfree(ss->tx.info);
0da34b6d
BG		 1966
1967abort_with_rx_big_shadow:
b53bef84 1968 kfree(ss->rx_big.shadow);
0da34b6d
BG		 1969
1970abort_with_rx_small_shadow:
b53bef84 1971 kfree(ss->rx_small.shadow);
0da34b6d
BG		 1972
1973abort_with_tx_req_bytes:
b53bef84
BG		 1974 kfree(ss->tx.req_bytes);
1975 ss->tx.req_bytes = NULL;
1976 ss->tx.req_list = NULL;
0da34b6d
BG		 1977
1978abort_with_nothing:
1979 return status;
1980}
1981
b53bef84 1982static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
0da34b6d 1983{
b53bef84 1984 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d
BG		 1985 struct sk_buff *skb;
1986 struct myri10ge_tx_buf *tx;
1987 int i, len, idx;
1988
0dcffac1
BG		 1989 /* If not allocated, skip it */
1990 if (ss->tx.req_list == NULL)
1991 return;
1992
b53bef84
BG		 1993 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
1994 idx = i & ss->rx_big.mask;
1995 if (i == ss->rx_big.fill_cnt - 1)
1996 ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
1997 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 1998 mgp->big_bytes);
b53bef84 1999 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 2000 }
2001
b53bef84
BG		 2002 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2003 idx = i & ss->rx_small.mask;
2004 if (i == ss->rx_small.fill_cnt - 1)
2005 ss->rx_small.info[idx].page_offset =
c7dab99b 2006 MYRI10GE_ALLOC_SIZE;
b53bef84 2007 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 2008 mgp->small_bytes + MXGEFW_PAD);
b53bef84 2009 put_page(ss->rx_small.info[idx].page);
c7dab99b 2010 }
b53bef84 2011 tx = &ss->tx;
0da34b6d
BG		 2012 while (tx->done != tx->req) {
2013 idx = tx->done & tx->mask;
2014 skb = tx->info[idx].skb;
2015
2016 /* Mark as free */
2017 tx->info[idx].skb = NULL;
2018 tx->done++;
2019 len = pci_unmap_len(&tx->info[idx], len);
2020 pci_unmap_len_set(&tx->info[idx], len, 0);
2021 if (skb) {
b53bef84 2022 ss->stats.tx_dropped++;
0da34b6d
BG		 2023 dev_kfree_skb_any(skb);
2024 if (len)
2025 pci_unmap_single(mgp->pdev,
2026 pci_unmap_addr(&tx->info[idx],
2027 bus), len,
2028 PCI_DMA_TODEVICE);
2029 } else {
2030 if (len)
2031 pci_unmap_page(mgp->pdev,
2032 pci_unmap_addr(&tx->info[idx],
2033 bus), len,
2034 PCI_DMA_TODEVICE);
2035 }
2036 }
b53bef84 2037 kfree(ss->rx_big.info);
0da34b6d 2038
b53bef84 2039 kfree(ss->rx_small.info);
0da34b6d 2040
b53bef84 2041 kfree(ss->tx.info);
0da34b6d 2042
b53bef84 2043 kfree(ss->rx_big.shadow);
0da34b6d 2044
b53bef84 2045 kfree(ss->rx_small.shadow);
0da34b6d 2046
b53bef84
BG		 2047 kfree(ss->tx.req_bytes);
2048 ss->tx.req_bytes = NULL;
2049 ss->tx.req_list = NULL;
0da34b6d
BG		 2050}
2051
df30a740
BG		 2052static int myri10ge_request_irq(struct myri10ge_priv *mgp)
2053{
2054 struct pci_dev *pdev = mgp->pdev;
0dcffac1
BG		 2055 struct myri10ge_slice_state *ss;
2056 struct net_device *netdev = mgp->dev;
2057 int i;
df30a740
BG		 2058 int status;
2059
0dcffac1
BG		 2060 mgp->msi_enabled = 0;
2061 mgp->msix_enabled = 0;
2062 status = 0;
df30a740 2063 if (myri10ge_msi) {
0dcffac1
BG		 2064 if (mgp->num_slices > 1) {
2065 status =
2066 pci_enable_msix(pdev, mgp->msix_vectors,
2067 mgp->num_slices);
2068 if (status == 0) {
2069 mgp->msix_enabled = 1;
2070 } else {
2071 dev_err(&pdev->dev,
2072 "Error %d setting up MSI-X\n", status);
2073 return status;
2074 }
2075 }
2076 if (mgp->msix_enabled == 0) {
2077 status = pci_enable_msi(pdev);
2078 if (status != 0) {
2079 dev_err(&pdev->dev,
2080 "Error %d setting up MSI; falling back to xPIC\n",
2081 status);
2082 } else {
2083 mgp->msi_enabled = 1;
2084 }
2085 }
df30a740 2086 }
0dcffac1
BG		 2087 if (mgp->msix_enabled) {
2088 for (i = 0; i < mgp->num_slices; i++) {
2089 ss = &mgp->ss[i];
2090 snprintf(ss->irq_desc, sizeof(ss->irq_desc),
2091 "%s:slice-%d", netdev->name, i);
2092 status = request_irq(mgp->msix_vectors[i].vector,
2093 myri10ge_intr, 0, ss->irq_desc,
2094 ss);
2095 if (status != 0) {
2096 dev_err(&pdev->dev,
2097 "slice %d failed to allocate IRQ\n", i);
2098 i--;
2099 while (i >= 0) {
2100 free_irq(mgp->msix_vectors[i].vector,
2101 &mgp->ss[i]);
2102 i--;
2103 }
2104 pci_disable_msix(pdev);
2105 return status;
2106 }
2107 }
2108 } else {
2109 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2110 mgp->dev->name, &mgp->ss[0]);
2111 if (status != 0) {
2112 dev_err(&pdev->dev, "failed to allocate IRQ\n");
2113 if (mgp->msi_enabled)
2114 pci_disable_msi(pdev);
2115 }
df30a740
BG		 2116 }
2117 return status;
2118}
2119
2120static void myri10ge_free_irq(struct myri10ge_priv *mgp)
2121{
2122 struct pci_dev *pdev = mgp->pdev;
0dcffac1 2123 int i;
df30a740 2124
0dcffac1
BG		 2125 if (mgp->msix_enabled) {
2126 for (i = 0; i < mgp->num_slices; i++)
2127 free_irq(mgp->msix_vectors[i].vector, &mgp->ss[i]);
2128 } else {
2129 free_irq(pdev->irq, &mgp->ss[0]);
2130 }
df30a740
BG		 2131 if (mgp->msi_enabled)
2132 pci_disable_msi(pdev);
0dcffac1
BG		 2133 if (mgp->msix_enabled)
2134 pci_disable_msix(pdev);
df30a740
BG		 2135}
2136
1e6e9342
AG		 2137static int
2138myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
2139 void **ip_hdr, void **tcpudp_hdr,
2140 u64 * hdr_flags, void *priv)
2141{
2142 struct ethhdr *eh;
2143 struct vlan_ethhdr *veh;
2144 struct iphdr *iph;
2145 u8 *va = page_address(frag->page) + frag->page_offset;
2146 unsigned long ll_hlen;
66341fff
AV		 2147 /* passed opaque through lro_receive_frags() */
2148 __wsum csum = (__force __wsum) (unsigned long)priv;
1e6e9342
AG		 2149
2150 /* find the mac header, aborting if not IPv4 */
2151
2152 eh = (struct ethhdr *)va;
2153 *mac_hdr = eh;
2154 ll_hlen = ETH_HLEN;
2155 if (eh->h_proto != htons(ETH_P_IP)) {
2156 if (eh->h_proto == htons(ETH_P_8021Q)) {
2157 veh = (struct vlan_ethhdr *)va;
2158 if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
2159 return -1;
2160
2161 ll_hlen += VLAN_HLEN;
2162
2163 /*
2164 * HW checksum starts ETH_HLEN bytes into
2165 * frame, so we must subtract off the VLAN
2166 * header's checksum before csum can be used
2167 */
2168 csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
2169 VLAN_HLEN, 0));
2170 } else {
2171 return -1;
2172 }
2173 }
2174 *hdr_flags = LRO_IPV4;
2175
2176 iph = (struct iphdr *)(va + ll_hlen);
2177 *ip_hdr = iph;
2178 if (iph->protocol != IPPROTO_TCP)
2179 return -1;
2180 *hdr_flags |= LRO_TCP;
2181 *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
2182
2183 /* verify the IP checksum */
2184 if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
2185 return -1;
2186
2187 /* verify the checksum */
2188 if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
2189 ntohs(iph->tot_len) - (iph->ihl << 2),
2190 IPPROTO_TCP, csum)))
2191 return -1;
2192
2193 return 0;
2194}
2195
77929732
BG		 2196static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
2197{
2198 struct myri10ge_cmd cmd;
2199 struct myri10ge_slice_state *ss;
2200 int status;
2201
2202 ss = &mgp->ss[slice];
2203 cmd.data0 = 0; /* single slice for now */
2204 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
2205 ss->tx.lanai = (struct mcp_kreq_ether_send __iomem *)
2206 (mgp->sram + cmd.data0);
2207
2208 cmd.data0 = slice;
2209 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET,
2210 &cmd, 0);
2211 ss->rx_small.lanai = (struct mcp_kreq_ether_recv __iomem *)
2212 (mgp->sram + cmd.data0);
2213
2214 cmd.data0 = slice;
2215 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
2216 ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *)
2217 (mgp->sram + cmd.data0);
2218
77929732
BG		 2219 return status;
2220
2221}
2222
2223static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice)
2224{
2225 struct myri10ge_cmd cmd;
2226 struct myri10ge_slice_state *ss;
2227 int status;
2228
2229 ss = &mgp->ss[slice];
2230 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->fw_stats_bus);
2231 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->fw_stats_bus);
2232 cmd.data2 = sizeof(struct mcp_irq_data);
2233 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2234 if (status == -ENOSYS) {
2235 dma_addr_t bus = ss->fw_stats_bus;
2236 if (slice != 0)
2237 return -EINVAL;
2238 bus += offsetof(struct mcp_irq_data, send_done_count);
2239 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2240 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2241 status = myri10ge_send_cmd(mgp,
2242 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2243 &cmd, 0);
2244 /* Firmware cannot support multicast without STATS_DMA_V2 */
2245 mgp->fw_multicast_support = 0;
2246 } else {
2247 mgp->fw_multicast_support = 1;
2248 }
2249 return 0;
2250}
77929732 2251
0da34b6d
BG		 2252static int myri10ge_open(struct net_device *dev)
2253{
0dcffac1 2254 struct myri10ge_slice_state *ss;
b53bef84 2255 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d 2256 struct myri10ge_cmd cmd;
0dcffac1
BG		 2257 int i, status, big_pow2, slice;
2258 u8 *itable;
1e6e9342 2259 struct net_lro_mgr *lro_mgr;
0da34b6d 2260
0da34b6d
BG		 2261 if (mgp->running != MYRI10GE_ETH_STOPPED)
2262 return -EBUSY;
2263
2264 mgp->running = MYRI10GE_ETH_STARTING;
2265 status = myri10ge_reset(mgp);
2266 if (status != 0) {
2267 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
df30a740 2268 goto abort_with_nothing;
0da34b6d
BG		 2269 }
2270
0dcffac1
BG		 2271 if (mgp->num_slices > 1) {
2272 cmd.data0 = mgp->num_slices;
2273 cmd.data1 = 1; /* use MSI-X */
2274 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
2275 &cmd, 0);
2276 if (status != 0) {
2277 printk(KERN_ERR
2278 "myri10ge: %s: failed to set number of slices\n",
2279 dev->name);
2280 goto abort_with_nothing;
2281 }
2282 /* setup the indirection table */
2283 cmd.data0 = mgp->num_slices;
2284 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
2285 &cmd, 0);
2286
2287 status |= myri10ge_send_cmd(mgp,
2288 MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
2289 &cmd, 0);
2290 if (status != 0) {
2291 printk(KERN_ERR
2292 "myri10ge: %s: failed to setup rss tables\n",
2293 dev->name);
2294 }
2295
2296 /* just enable an identity mapping */
2297 itable = mgp->sram + cmd.data0;
2298 for (i = 0; i < mgp->num_slices; i++)
2299 __raw_writeb(i, &itable[i]);
2300
2301 cmd.data0 = 1;
2302 cmd.data1 = myri10ge_rss_hash;
2303 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE,
2304 &cmd, 0);
2305 if (status != 0) {
2306 printk(KERN_ERR
2307 "myri10ge: %s: failed to enable slices\n",
2308 dev->name);
2309 goto abort_with_nothing;
2310 }
2311 }
2312
df30a740
BG		 2313 status = myri10ge_request_irq(mgp);
2314 if (status != 0)
2315 goto abort_with_nothing;
2316
0da34b6d
BG		 2317 /* decide what small buffer size to use. For good TCP rx
2318 * performance, it is important to not receive 1514 byte
2319 * frames into jumbo buffers, as it confuses the socket buffer
2320 * accounting code, leading to drops and erratic performance.
2321 */
2322
2323 if (dev->mtu <= ETH_DATA_LEN)
c7dab99b
BG		 2324 /* enough for a TCP header */
2325 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
2326 ? (128 - MXGEFW_PAD)
2327 : (SMP_CACHE_BYTES - MXGEFW_PAD);
0da34b6d 2328 else
de3c4507
BG		 2329 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
2330 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
0da34b6d
BG		 2331
2332 /* Override the small buffer size? */
2333 if (myri10ge_small_bytes > 0)
2334 mgp->small_bytes = myri10ge_small_bytes;
2335
0da34b6d
BG		 2336 /* Firmware needs the big buff size as a power of 2. Lie and
2337 * tell him the buffer is larger, because we only use 1
2338 * buffer/pkt, and the mtu will prevent overruns.
2339 */
13348bee 2340 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b 2341 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
199126a2 2342 while (!is_power_of_2(big_pow2))
c7dab99b 2343 big_pow2++;
13348bee 2344 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 2345 } else {
2346 big_pow2 = MYRI10GE_ALLOC_SIZE;
2347 mgp->big_bytes = big_pow2;
2348 }
2349
0dcffac1
BG		 2350 /* setup the per-slice data structures */
2351 for (slice = 0; slice < mgp->num_slices; slice++) {
2352 ss = &mgp->ss[slice];
2353
2354 status = myri10ge_get_txrx(mgp, slice);
2355 if (status != 0) {
2356 printk(KERN_ERR
2357 "myri10ge: %s: failed to get ring sizes or locations\n",
2358 dev->name);
2359 goto abort_with_rings;
2360 }
2361 status = myri10ge_allocate_rings(ss);
2362 if (status != 0)
2363 goto abort_with_rings;
2364 if (slice == 0)
2365 status = myri10ge_set_stats(mgp, slice);
2366 if (status) {
2367 printk(KERN_ERR
2368 "myri10ge: %s: Couldn't set stats DMA\n",
2369 dev->name);
2370 goto abort_with_rings;
2371 }
2372
2373 lro_mgr = &ss->rx_done.lro_mgr;
2374 lro_mgr->dev = dev;
2375 lro_mgr->features = LRO_F_NAPI;
2376 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
2377 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2378 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
2379 lro_mgr->lro_arr = ss->rx_done.lro_desc;
2380 lro_mgr->get_frag_header = myri10ge_get_frag_header;
2381 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
2382 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2383 lro_mgr->max_aggr = MAX_SKB_FRAGS;
2384
2385 /* must happen prior to any irq */
2386 napi_enable(&(ss)->napi);
2387 }
0da34b6d
BG		 2388
2389 /* now give firmware buffers sizes, and MTU */
2390 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
2391 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2392 cmd.data0 = mgp->small_bytes;
2393 status |=
2394 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2395 cmd.data0 = big_pow2;
2396 status |=
2397 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2398 if (status) {
2399 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
2400 dev->name);
2401 goto abort_with_rings;
2402 }
2403
0dcffac1
BG		 2404 /*
2405 * Set Linux style TSO mode; this is needed only on newer
2406 * firmware versions. Older versions default to Linux
2407 * style TSO
2408 */
2409 cmd.data0 = 0;
2410 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd, 0);
2411 if (status && status != -ENOSYS) {
2412 printk(KERN_ERR "myri10ge: %s: Couldn't set TSO mode\n",
0da34b6d
BG		 2413 dev->name);
2414 goto abort_with_rings;
2415 }
2416
66341fff 2417 mgp->link_state = ~0U;
0da34b6d
BG		 2418 mgp->rdma_tags_available = 15;
2419
0da34b6d
BG		 2420 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2421 if (status) {
2422 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
2423 dev->name);
2424 goto abort_with_rings;
2425 }
2426
0da34b6d
BG		 2427 mgp->running = MYRI10GE_ETH_RUNNING;
2428 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2429 add_timer(&mgp->watchdog_timer);
2430 netif_wake_queue(dev);
2431 return 0;
2432
2433abort_with_rings:
0dcffac1
BG		 2434 for (i = 0; i < mgp->num_slices; i++)
2435 myri10ge_free_rings(&mgp->ss[i]);
0da34b6d 2436
df30a740
BG		 2437 myri10ge_free_irq(mgp);
2438
0da34b6d
BG		 2439abort_with_nothing:
2440 mgp->running = MYRI10GE_ETH_STOPPED;
2441 return -ENOMEM;
2442}
2443
2444static int myri10ge_close(struct net_device *dev)
2445{
b53bef84 2446 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d
BG		 2447 struct myri10ge_cmd cmd;
2448 int status, old_down_cnt;
0dcffac1 2449 int i;
0da34b6d 2450
0da34b6d
BG		 2451 if (mgp->running != MYRI10GE_ETH_RUNNING)
2452 return 0;
2453
0dcffac1 2454 if (mgp->ss[0].tx.req_bytes == NULL)
0da34b6d
BG		 2455 return 0;
2456
2457 del_timer_sync(&mgp->watchdog_timer);
2458 mgp->running = MYRI10GE_ETH_STOPPING;
0dcffac1
BG		 2459 for (i = 0; i < mgp->num_slices; i++) {
2460 napi_disable(&mgp->ss[i].napi);
2461 }
0da34b6d
BG		 2462 netif_carrier_off(dev);
2463 netif_stop_queue(dev);
2464 old_down_cnt = mgp->down_cnt;
2465 mb();
2466 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2467 if (status)
2468 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
2469 dev->name);
2470
2471 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
2472 if (old_down_cnt == mgp->down_cnt)
2473 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
2474
2475 netif_tx_disable(dev);
df30a740 2476 myri10ge_free_irq(mgp);
0dcffac1
BG		 2477 for (i = 0; i < mgp->num_slices; i++)
2478 myri10ge_free_rings(&mgp->ss[i]);
0da34b6d
BG		 2479
2480 mgp->running = MYRI10GE_ETH_STOPPED;
2481 return 0;
2482}
2483
2484/* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2485 * backwards one at a time and handle ring wraps */
2486
2487static inline void
2488myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2489 struct mcp_kreq_ether_send *src, int cnt)
2490{
2491 int idx, starting_slot;
2492 starting_slot = tx->req;
2493 while (cnt > 1) {
2494 cnt--;
2495 idx = (starting_slot + cnt) & tx->mask;
2496 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2497 mb();
2498 }
2499}
2500
2501/*
2502 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2503 * at most 32 bytes at a time, so as to avoid involving the software
2504 * pio handler in the nic. We re-write the first segment's flags
2505 * to mark them valid only after writing the entire chain.
2506 */
2507
2508static inline void
2509myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2510 int cnt)
2511{
2512 int idx, i;
2513 struct mcp_kreq_ether_send __iomem *dstp, *dst;
2514 struct mcp_kreq_ether_send *srcp;
2515 u8 last_flags;
2516
2517 idx = tx->req & tx->mask;
2518
2519 last_flags = src->flags;
2520 src->flags = 0;
2521 mb();
2522 dst = dstp = &tx->lanai[idx];
2523 srcp = src;
2524
2525 if ((idx + cnt) < tx->mask) {
2526 for (i = 0; i < (cnt - 1); i += 2) {
2527 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2528 mb(); /* force write every 32 bytes */
2529 srcp += 2;
2530 dstp += 2;
2531 }
2532 } else {
2533 /* submit all but the first request, and ensure
2534 * that it is submitted below */
2535 myri10ge_submit_req_backwards(tx, src, cnt);
2536 i = 0;
2537 }
2538 if (i < cnt) {
2539 /* submit the first request */
2540 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2541 mb(); /* barrier before setting valid flag */
2542 }
2543
2544 /* re-write the last 32-bits with the valid flags */
2545 src->flags = last_flags;
40f6cff5 2546 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
0da34b6d
BG		 2547 tx->req += cnt;
2548 mb();
2549}
2550
0da34b6d
BG		 2551/*
2552 * Transmit a packet. We need to split the packet so that a single
b53bef84 2553 * segment does not cross myri10ge->tx_boundary, so this makes segment
0da34b6d
BG		 2554 * counting tricky. So rather than try to count segments up front, we
2555 * just give up if there are too few segments to hold a reasonably
2556 * fragmented packet currently available. If we run
2557 * out of segments while preparing a packet for DMA, we just linearize
2558 * it and try again.
2559 */
2560
2561static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
2562{
2563 struct myri10ge_priv *mgp = netdev_priv(dev);
b53bef84 2564 struct myri10ge_slice_state *ss;
0da34b6d 2565 struct mcp_kreq_ether_send *req;
b53bef84 2566 struct myri10ge_tx_buf *tx;
0da34b6d
BG		 2567 struct skb_frag_struct *frag;
2568 dma_addr_t bus;
40f6cff5
AV		 2569 u32 low;
2570 __be32 high_swapped;
0da34b6d
BG		 2571 unsigned int len;
2572 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2573 u16 pseudo_hdr_offset, cksum_offset;
2574 int cum_len, seglen, boundary, rdma_count;
2575 u8 flags, odd_flag;
2576
b53bef84 2577 /* always transmit through slot 0 */
0dcffac1 2578 ss = mgp->ss;
b53bef84 2579 tx = &ss->tx;
0da34b6d
BG		 2580again:
2581 req = tx->req_list;
2582 avail = tx->mask - 1 - (tx->req - tx->done);
2583
2584 mss = 0;
2585 max_segments = MXGEFW_MAX_SEND_DESC;
2586
917690cd 2587 if (skb_is_gso(skb)) {
7967168c 2588 mss = skb_shinfo(skb)->gso_size;
917690cd 2589 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
0da34b6d 2590 }
0da34b6d
BG		 2591
2592 if ((unlikely(avail < max_segments))) {
2593 /* we are out of transmit resources */
b53bef84 2594 tx->stop_queue++;
0da34b6d
BG		 2595 netif_stop_queue(dev);
2596 return 1;
2597 }
2598
2599 /* Setup checksum offloading, if needed */
2600 cksum_offset = 0;
2601 pseudo_hdr_offset = 0;
2602 odd_flag = 0;
2603 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
84fa7933 2604 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
ea2ae17d 2605 cksum_offset = skb_transport_offset(skb);
ff1dcadb 2606 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
0da34b6d
BG		 2607 /* If the headers are excessively large, then we must
2608 * fall back to a software checksum */
4f93fde0
BG		 2609 if (unlikely(!mss && (cksum_offset > 255 ||
2610 pseudo_hdr_offset > 127))) {
84fa7933 2611 if (skb_checksum_help(skb))
0da34b6d
BG		 2612 goto drop;
2613 cksum_offset = 0;
2614 pseudo_hdr_offset = 0;
2615 } else {
0da34b6d
BG		 2616 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2617 flags |= MXGEFW_FLAGS_CKSUM;
2618 }
2619 }
2620
2621 cum_len = 0;
2622
0da34b6d
BG		 2623 if (mss) { /* TSO */
2624 /* this removes any CKSUM flag from before */
2625 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2626
2627 /* negative cum_len signifies to the
2628 * send loop that we are still in the
2629 * header portion of the TSO packet.
4f93fde0 2630 * TSO header can be at most 1KB long */
ab6a5bb6 2631 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
0da34b6d 2632
4f93fde0
BG		 2633 /* for IPv6 TSO, the checksum offset stores the
2634 * TCP header length, to save the firmware from
2635 * the need to parse the headers */
2636 if (skb_is_gso_v6(skb)) {
2637 cksum_offset = tcp_hdrlen(skb);
2638 /* Can only handle headers <= max_tso6 long */
2639 if (unlikely(-cum_len > mgp->max_tso6))
2640 return myri10ge_sw_tso(skb, dev);
2641 }
0da34b6d
BG		 2642 /* for TSO, pseudo_hdr_offset holds mss.
2643 * The firmware figures out where to put
2644 * the checksum by parsing the header. */
40f6cff5 2645 pseudo_hdr_offset = mss;
0da34b6d 2646 } else
0da34b6d
BG		 2647 /* Mark small packets, and pad out tiny packets */
2648 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2649 flags |= MXGEFW_FLAGS_SMALL;
2650
2651 /* pad frames to at least ETH_ZLEN bytes */
2652 if (unlikely(skb->len < ETH_ZLEN)) {
5b057c6b 2653 if (skb_padto(skb, ETH_ZLEN)) {
0da34b6d
BG		 2654 /* The packet is gone, so we must
2655 * return 0 */
b53bef84 2656 ss->stats.tx_dropped += 1;
0da34b6d
BG		 2657 return 0;
2658 }
2659 /* adjust the len to account for the zero pad
2660 * so that the nic can know how long it is */
2661 skb->len = ETH_ZLEN;
2662 }
2663 }
2664
2665 /* map the skb for DMA */
2666 len = skb->len - skb->data_len;
2667 idx = tx->req & tx->mask;
2668 tx->info[idx].skb = skb;
2669 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2670 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2671 pci_unmap_len_set(&tx->info[idx], len, len);
2672
2673 frag_cnt = skb_shinfo(skb)->nr_frags;
2674 frag_idx = 0;
2675 count = 0;
2676 rdma_count = 0;
2677
2678 /* "rdma_count" is the number of RDMAs belonging to the
2679 * current packet BEFORE the current send request. For
2680 * non-TSO packets, this is equal to "count".
2681 * For TSO packets, rdma_count needs to be reset
2682 * to 0 after a segment cut.
2683 *
2684 * The rdma_count field of the send request is
2685 * the number of RDMAs of the packet starting at
2686 * that request. For TSO send requests with one ore more cuts
2687 * in the middle, this is the number of RDMAs starting
2688 * after the last cut in the request. All previous
2689 * segments before the last cut implicitly have 1 RDMA.
2690 *
2691 * Since the number of RDMAs is not known beforehand,
2692 * it must be filled-in retroactively - after each
2693 * segmentation cut or at the end of the entire packet.
2694 */
2695
2696 while (1) {
2697 /* Break the SKB or Fragment up into pieces which
b53bef84 2698 * do not cross mgp->tx_boundary */
0da34b6d
BG		 2699 low = MYRI10GE_LOWPART_TO_U32(bus);
2700 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2701 while (len) {
2702 u8 flags_next;
2703 int cum_len_next;
2704
2705 if (unlikely(count == max_segments))
2706 goto abort_linearize;
2707
b53bef84
BG		 2708 boundary =
2709 (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
0da34b6d
BG		 2710 seglen = boundary - low;
2711 if (seglen > len)
2712 seglen = len;
2713 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2714 cum_len_next = cum_len + seglen;
0da34b6d
BG		 2715 if (mss) { /* TSO */
2716 (req - rdma_count)->rdma_count = rdma_count + 1;
2717
2718 if (likely(cum_len >= 0)) { /* payload */
2719 int next_is_first, chop;
2720
2721 chop = (cum_len_next > mss);
2722 cum_len_next = cum_len_next % mss;
2723 next_is_first = (cum_len_next == 0);
2724 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2725 flags_next |= next_is_first *
2726 MXGEFW_FLAGS_FIRST;
2727 rdma_count |= -(chop | next_is_first);
2728 rdma_count += chop & !next_is_first;
2729 } else if (likely(cum_len_next >= 0)) { /* header ends */
2730 int small;
2731
2732 rdma_count = -1;
2733 cum_len_next = 0;
2734 seglen = -cum_len;
2735 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2736 flags_next = MXGEFW_FLAGS_TSO_PLD |
2737 MXGEFW_FLAGS_FIRST |
2738 (small * MXGEFW_FLAGS_SMALL);
2739 }
2740 }
0da34b6d
BG		 2741 req->addr_high = high_swapped;
2742 req->addr_low = htonl(low);
40f6cff5 2743 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
0da34b6d
BG		 2744 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2745 req->rdma_count = 1;
2746 req->length = htons(seglen);
2747 req->cksum_offset = cksum_offset;
2748 req->flags = flags | ((cum_len & 1) * odd_flag);
2749
2750 low += seglen;
2751 len -= seglen;
2752 cum_len = cum_len_next;
2753 flags = flags_next;
2754 req++;
2755 count++;
2756 rdma_count++;
4f93fde0
BG		 2757 if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2758 if (unlikely(cksum_offset > seglen))
2759 cksum_offset -= seglen;
2760 else
2761 cksum_offset = 0;
2762 }
0da34b6d
BG		 2763 }
2764 if (frag_idx == frag_cnt)
2765 break;
2766
2767 /* map next fragment for DMA */
2768 idx = (count + tx->req) & tx->mask;
2769 frag = &skb_shinfo(skb)->frags[frag_idx];
2770 frag_idx++;
2771 len = frag->size;
2772 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2773 len, PCI_DMA_TODEVICE);
2774 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2775 pci_unmap_len_set(&tx->info[idx], len, len);
2776 }
2777
2778 (req - rdma_count)->rdma_count = rdma_count;
0da34b6d
BG		 2779 if (mss)
2780 do {
2781 req--;
2782 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2783 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2784 MXGEFW_FLAGS_FIRST)));
0da34b6d
BG		 2785 idx = ((count - 1) + tx->req) & tx->mask;
2786 tx->info[idx].last = 1;
e454e7e2 2787 myri10ge_submit_req(tx, tx->req_list, count);
0da34b6d
BG		 2788 tx->pkt_start++;
2789 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
b53bef84 2790 tx->stop_queue++;
0da34b6d
BG		 2791 netif_stop_queue(dev);
2792 }
2793 dev->trans_start = jiffies;
2794 return 0;
2795
2796abort_linearize:
2797 /* Free any DMA resources we've alloced and clear out the skb
2798 * slot so as to not trip up assertions, and to avoid a
2799 * double-free if linearizing fails */
2800
2801 last_idx = (idx + 1) & tx->mask;
2802 idx = tx->req & tx->mask;
2803 tx->info[idx].skb = NULL;
2804 do {
2805 len = pci_unmap_len(&tx->info[idx], len);
2806 if (len) {
2807 if (tx->info[idx].skb != NULL)
2808 pci_unmap_single(mgp->pdev,
2809 pci_unmap_addr(&tx->info[idx],
2810 bus), len,
2811 PCI_DMA_TODEVICE);
2812 else
2813 pci_unmap_page(mgp->pdev,
2814 pci_unmap_addr(&tx->info[idx],
2815 bus), len,
2816 PCI_DMA_TODEVICE);
2817 pci_unmap_len_set(&tx->info[idx], len, 0);
2818 tx->info[idx].skb = NULL;
2819 }
2820 idx = (idx + 1) & tx->mask;
2821 } while (idx != last_idx);
89114afd 2822 if (skb_is_gso(skb)) {
0da34b6d
BG		 2823 printk(KERN_ERR
2824 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2825 mgp->dev->name);
2826 goto drop;
2827 }
2828
bec0e859 2829 if (skb_linearize(skb))
0da34b6d
BG		 2830 goto drop;
2831
b53bef84 2832 tx->linearized++;
0da34b6d
BG		 2833 goto again;
2834
2835drop:
2836 dev_kfree_skb_any(skb);
b53bef84 2837 ss->stats.tx_dropped += 1;
0da34b6d
BG		 2838 return 0;
2839
2840}
2841
4f93fde0
BG		 2842static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev)
2843{
2844 struct sk_buff *segs, *curr;
b53bef84 2845 struct myri10ge_priv *mgp = netdev_priv(dev);
4f93fde0
BG		 2846 int status;
2847
2848 segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
801678c5 2849 if (IS_ERR(segs))
4f93fde0
BG		 2850 goto drop;
2851
2852 while (segs) {
2853 curr = segs;
2854 segs = segs->next;
2855 curr->next = NULL;
2856 status = myri10ge_xmit(curr, dev);
2857 if (status != 0) {
2858 dev_kfree_skb_any(curr);
2859 if (segs != NULL) {
2860 curr = segs;
2861 segs = segs->next;
2862 curr->next = NULL;
2863 dev_kfree_skb_any(segs);
2864 }
2865 goto drop;
2866 }
2867 }
2868 dev_kfree_skb_any(skb);
2869 return 0;
2870
2871drop:
2872 dev_kfree_skb_any(skb);
2873 mgp->stats.tx_dropped += 1;
2874 return 0;
2875}
2876
0da34b6d
BG		 2877static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2878{
2879 struct myri10ge_priv *mgp = netdev_priv(dev);
0dcffac1
BG		 2880 struct myri10ge_slice_netstats *slice_stats;
2881 struct net_device_stats *stats = &mgp->stats;
2882 int i;
2883
2884 memset(stats, 0, sizeof(*stats));
2885 for (i = 0; i < mgp->num_slices; i++) {
2886 slice_stats = &mgp->ss[i].stats;
2887 stats->rx_packets += slice_stats->rx_packets;
2888 stats->tx_packets += slice_stats->tx_packets;
2889 stats->rx_bytes += slice_stats->rx_bytes;
2890 stats->tx_bytes += slice_stats->tx_bytes;
2891 stats->rx_dropped += slice_stats->rx_dropped;
2892 stats->tx_dropped += slice_stats->tx_dropped;
2893 }
2894 return stats;
0da34b6d
BG		 2895}
2896
2897static void myri10ge_set_multicast_list(struct net_device *dev)
2898{
b53bef84 2899 struct myri10ge_priv *mgp = netdev_priv(dev);
85a7ea1b 2900 struct myri10ge_cmd cmd;
85a7ea1b 2901 struct dev_mc_list *mc_list;
6250223e 2902 __be32 data[2] = { 0, 0 };
85a7ea1b 2903 int err;
0795af57 2904 DECLARE_MAC_BUF(mac);
85a7ea1b 2905
0da34b6d
BG		 2906 /* can be called from atomic contexts,
2907 * pass 1 to force atomicity in myri10ge_send_cmd() */
85a7ea1b
BG		 2908 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2909
2910 /* This firmware is known to not support multicast */
2f76216f 2911 if (!mgp->fw_multicast_support)
85a7ea1b
BG		 2912 return;
2913
2914 /* Disable multicast filtering */
2915
2916 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2917 if (err != 0) {
2918 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
2919 " error status: %d\n", dev->name, err);
2920 goto abort;
2921 }
2922
2f76216f 2923 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
85a7ea1b
BG		 2924 /* request to disable multicast filtering, so quit here */
2925 return;
2926 }
2927
2928 /* Flush the filters */
2929
2930 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2931 &cmd, 1);
2932 if (err != 0) {
2933 printk(KERN_ERR
2934 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
2935 ", error status: %d\n", dev->name, err);
2936 goto abort;
2937 }
2938
2939 /* Walk the multicast list, and add each address */
2940 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
40f6cff5
AV		 2941 memcpy(data, &mc_list->dmi_addr, 6);
2942 cmd.data0 = ntohl(data[0]);
2943 cmd.data1 = ntohl(data[1]);
85a7ea1b
BG		 2944 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2945 &cmd, 1);
2946
2947 if (err != 0) {
2948 printk(KERN_ERR "myri10ge: %s: Failed "
2949 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
2950 "%d\t", dev->name, err);
0795af57
JP		 2951 printk(KERN_ERR "MAC %s\n",
2952 print_mac(mac, mc_list->dmi_addr));
85a7ea1b
BG		 2953 goto abort;
2954 }
2955 }
2956 /* Enable multicast filtering */
2957 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
2958 if (err != 0) {
2959 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
2960 "error status: %d\n", dev->name, err);
2961 goto abort;
2962 }
2963
2964 return;
2965
2966abort:
2967 return;
0da34b6d
BG		 2968}
2969
2970static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2971{
2972 struct sockaddr *sa = addr;
2973 struct myri10ge_priv *mgp = netdev_priv(dev);
2974 int status;
2975
2976 if (!is_valid_ether_addr(sa->sa_data))
2977 return -EADDRNOTAVAIL;
2978
2979 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2980 if (status != 0) {
2981 printk(KERN_ERR
2982 "myri10ge: %s: changing mac address failed with %d\n",
2983 dev->name, status);
2984 return status;
2985 }
2986
2987 /* change the dev structure */
2988 memcpy(dev->dev_addr, sa->sa_data, 6);
2989 return 0;
2990}
2991
2992static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2993{
2994 struct myri10ge_priv *mgp = netdev_priv(dev);
2995 int error = 0;
2996
2997 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
2998 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
2999 dev->name, new_mtu);
3000 return -EINVAL;
3001 }
3002 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
3003 dev->name, dev->mtu, new_mtu);
3004 if (mgp->running) {
3005 /* if we change the mtu on an active device, we must
3006 * reset the device so the firmware sees the change */
3007 myri10ge_close(dev);
3008 dev->mtu = new_mtu;
3009 myri10ge_open(dev);
3010 } else
3011 dev->mtu = new_mtu;
3012
3013 return error;
3014}
3015
3016/*
3017 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
3018 * Only do it if the bridge is a root port since we don't want to disturb
3019 * any other device, except if forced with myri10ge_ecrc_enable > 1.
3020 */
3021
0da34b6d
BG		 3022static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
3023{
3024 struct pci_dev *bridge = mgp->pdev->bus->self;
3025 struct device *dev = &mgp->pdev->dev;
3026 unsigned cap;
3027 unsigned err_cap;
3028 u16 val;
3029 u8 ext_type;
3030 int ret;
3031
3032 if (!myri10ge_ecrc_enable || !bridge)
3033 return;
3034
3035 /* check that the bridge is a root port */
3036 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
3037 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
3038 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3039 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
3040 if (myri10ge_ecrc_enable > 1) {
eca3fd83 3041 struct pci_dev *prev_bridge, *old_bridge = bridge;
0da34b6d
BG		 3042
3043 /* Walk the hierarchy up to the root port
3044 * where ECRC has to be enabled */
3045 do {
eca3fd83 3046 prev_bridge = bridge;
0da34b6d 3047 bridge = bridge->bus->self;
eca3fd83 3048 if (!bridge || prev_bridge == bridge) {
0da34b6d
BG		 3049 dev_err(dev,
3050 "Failed to find root port"
3051 " to force ECRC\n");
3052 return;
3053 }
3054 cap =
3055 pci_find_capability(bridge, PCI_CAP_ID_EXP);
3056 pci_read_config_word(bridge,
3057 cap + PCI_CAP_FLAGS, &val);
3058 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3059 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
3060
3061 dev_info(dev,
3062 "Forcing ECRC on non-root port %s"
3063 " (enabling on root port %s)\n",
3064 pci_name(old_bridge), pci_name(bridge));
3065 } else {
3066 dev_err(dev,
3067 "Not enabling ECRC on non-root port %s\n",
3068 pci_name(bridge));
3069 return;
3070 }
3071 }
3072
3073 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
0da34b6d
BG		 3074 if (!cap)
3075 return;
3076
3077 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
3078 if (ret) {
3079 dev_err(dev, "failed reading ext-conf-space of %s\n",
3080 pci_name(bridge));
3081 dev_err(dev, "\t pci=nommconf in use? "
3082 "or buggy/incomplete/absent ACPI MCFG attr?\n");
3083 return;
3084 }
3085 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
3086 return;
3087
3088 err_cap |= PCI_ERR_CAP_ECRC_GENE;
3089 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
3090 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
0da34b6d
BG		 3091}
3092
3093/*
3094 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
3095 * when the PCI-E Completion packets are aligned on an 8-byte
3096 * boundary. Some PCI-E chip sets always align Completion packets; on
3097 * the ones that do not, the alignment can be enforced by enabling
3098 * ECRC generation (if supported).
3099 *
3100 * When PCI-E Completion packets are not aligned, it is actually more
3101 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
3102 *
3103 * If the driver can neither enable ECRC nor verify that it has
3104 * already been enabled, then it must use a firmware image which works
0dcffac1 3105 * around unaligned completion packets (myri10ge_rss_ethp_z8e.dat), and it
0da34b6d 3106 * should also ensure that it never gives the device a Read-DMA which is
b53bef84 3107 * larger than 2KB by setting the tx_boundary to 2KB. If ECRC is
0dcffac1 3108 * enabled, then the driver should use the aligned (myri10ge_rss_eth_z8e.dat)
b53bef84 3109 * firmware image, and set tx_boundary to 4KB.
0da34b6d
BG		 3110 */
3111
5443e9ea 3112static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
0da34b6d 3113{
5443e9ea
BG		 3114 struct pci_dev *pdev = mgp->pdev;
3115 struct device *dev = &pdev->dev;
302d242c 3116 int status;
0da34b6d 3117
b53bef84 3118 mgp->tx_boundary = 4096;
5443e9ea
BG		 3119 /*
3120 * Verify the max read request size was set to 4KB
3121 * before trying the test with 4KB.
3122 */
302d242c
BG		 3123 status = pcie_get_readrq(pdev);
3124 if (status < 0) {
5443e9ea
BG		 3125 dev_err(dev, "Couldn't read max read req size: %d\n", status);
3126 goto abort;
3127 }
302d242c
BG		 3128 if (status != 4096) {
3129 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
b53bef84 3130 mgp->tx_boundary = 2048;
5443e9ea
BG		 3131 }
3132 /*
3133 * load the optimized firmware (which assumes aligned PCIe
3134 * completions) in order to see if it works on this host.
3135 */
3136 mgp->fw_name = myri10ge_fw_aligned;
0dcffac1 3137 status = myri10ge_load_firmware(mgp, 1);
5443e9ea
BG		 3138 if (status != 0) {
3139 goto abort;
3140 }
3141
3142 /*
3143 * Enable ECRC if possible
3144 */
3145 myri10ge_enable_ecrc(mgp);
3146
3147 /*
3148 * Run a DMA test which watches for unaligned completions and
3149 * aborts on the first one seen.
3150 */
3151
3152 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
3153 if (status == 0)
3154 return; /* keep the aligned firmware */
3155
3156 if (status != -E2BIG)
3157 dev_warn(dev, "DMA test failed: %d\n", status);
3158 if (status == -ENOSYS)
3159 dev_warn(dev, "Falling back to ethp! "
3160 "Please install up to date fw\n");
3161abort:
3162 /* fall back to using the unaligned firmware */
b53bef84 3163 mgp->tx_boundary = 2048;
0da34b6d
BG		 3164 mgp->fw_name = myri10ge_fw_unaligned;
3165
5443e9ea
BG		 3166}
3167
3168static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
3169{
0da34b6d 3170 if (myri10ge_force_firmware == 0) {
ce7f9368
BG		 3171 int link_width, exp_cap;
3172 u16 lnk;
3173
3174 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
3175 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
3176 link_width = (lnk >> 4) & 0x3f;
3177
ce7f9368
BG		 3178 /* Check to see if Link is less than 8 or if the
3179 * upstream bridge is known to provide aligned
3180 * completions */
3181 if (link_width < 8) {
3182 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
3183 link_width);
b53bef84 3184 mgp->tx_boundary = 4096;
ce7f9368 3185 mgp->fw_name = myri10ge_fw_aligned;
5443e9ea
BG		 3186 } else {
3187 myri10ge_firmware_probe(mgp);
0da34b6d
BG		 3188 }
3189 } else {
3190 if (myri10ge_force_firmware == 1) {
3191 dev_info(&mgp->pdev->dev,
3192 "Assuming aligned completions (forced)\n");
b53bef84 3193 mgp->tx_boundary = 4096;
0da34b6d
BG		 3194 mgp->fw_name = myri10ge_fw_aligned;
3195 } else {
3196 dev_info(&mgp->pdev->dev,
3197 "Assuming unaligned completions (forced)\n");
b53bef84 3198 mgp->tx_boundary = 2048;
0da34b6d
BG		 3199 mgp->fw_name = myri10ge_fw_unaligned;
3200 }
3201 }
3202 if (myri10ge_fw_name != NULL) {
3203 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
3204 myri10ge_fw_name);
3205 mgp->fw_name = myri10ge_fw_name;
3206 }
3207}
3208
0da34b6d 3209#ifdef CONFIG_PM
0da34b6d
BG		 3210static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
3211{
3212 struct myri10ge_priv *mgp;
3213 struct net_device *netdev;
3214
3215 mgp = pci_get_drvdata(pdev);
3216 if (mgp == NULL)
3217 return -EINVAL;
3218 netdev = mgp->dev;
3219
3220 netif_device_detach(netdev);
3221 if (netif_running(netdev)) {
3222 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
3223 rtnl_lock();
3224 myri10ge_close(netdev);
3225 rtnl_unlock();
3226 }
3227 myri10ge_dummy_rdma(mgp, 0);
83f6e152 3228 pci_save_state(pdev);
0da34b6d 3229 pci_disable_device(pdev);
1a63e846
BG		 3230
3231 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
0da34b6d
BG		 3232}
3233
3234static int myri10ge_resume(struct pci_dev *pdev)
3235{
3236 struct myri10ge_priv *mgp;
3237 struct net_device *netdev;
3238 int status;
3239 u16 vendor;
3240
3241 mgp = pci_get_drvdata(pdev);
3242 if (mgp == NULL)
3243 return -EINVAL;
3244 netdev = mgp->dev;
3245 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
3246 msleep(5); /* give card time to respond */
3247 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3248 if (vendor == 0xffff) {
3249 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
3250 mgp->dev->name);
3251 return -EIO;
3252 }
83f6e152 3253
1a63e846
BG		 3254 status = pci_restore_state(pdev);
3255 if (status)
3256 return status;
4c2248cc
BG		 3257
3258 status = pci_enable_device(pdev);
1a63e846 3259 if (status) {
4c2248cc 3260 dev_err(&pdev->dev, "failed to enable device\n");
1a63e846 3261 return status;
4c2248cc
BG		 3262 }
3263
0da34b6d
BG		 3264 pci_set_master(pdev);
3265
0da34b6d 3266 myri10ge_reset(mgp);
013b68bf 3267 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 3268
3269 /* Save configuration space to be restored if the
3270 * nic resets due to a parity error */
83f6e152 3271 pci_save_state(pdev);
0da34b6d
BG		 3272
3273 if (netif_running(netdev)) {
3274 rtnl_lock();
df30a740 3275 status = myri10ge_open(netdev);
0da34b6d 3276 rtnl_unlock();
df30a740
BG		 3277 if (status != 0)
3278 goto abort_with_enabled;
3279
0da34b6d
BG		 3280 }
3281 netif_device_attach(netdev);
3282
3283 return 0;
3284
4c2248cc
BG		 3285abort_with_enabled:
3286 pci_disable_device(pdev);
0da34b6d
BG		 3287 return -EIO;
3288
3289}
0da34b6d
BG		 3290#endif /* CONFIG_PM */
3291
3292static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
3293{
3294 struct pci_dev *pdev = mgp->pdev;
3295 int vs = mgp->vendor_specific_offset;
3296 u32 reboot;
3297
3298 /*enter read32 mode */
3299 pci_write_config_byte(pdev, vs + 0x10, 0x3);
3300
3301 /*read REBOOT_STATUS (0xfffffff0) */
3302 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
3303 pci_read_config_dword(pdev, vs + 0x14, &reboot);
3304 return reboot;
3305}
3306
3307/*
3308 * This watchdog is used to check whether the board has suffered
3309 * from a parity error and needs to be recovered.
3310 */
c4028958 3311static void myri10ge_watchdog(struct work_struct *work)
0da34b6d 3312{
c4028958 3313 struct myri10ge_priv *mgp =
6250223e 3314 container_of(work, struct myri10ge_priv, watchdog_work);
b53bef84 3315 struct myri10ge_tx_buf *tx;
0da34b6d
BG		 3316 u32 reboot;
3317 int status;
0dcffac1 3318 int i;
0da34b6d
BG		 3319 u16 cmd, vendor;
3320
3321 mgp->watchdog_resets++;
3322 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3323 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3324 /* Bus master DMA disabled? Check to see
3325 * if the card rebooted due to a parity error
3326 * For now, just report it */
3327 reboot = myri10ge_read_reboot(mgp);
3328 printk(KERN_ERR
f181137f
BG		 3329 "myri10ge: %s: NIC rebooted (0x%x),%s resetting\n",
3330 mgp->dev->name, reboot,
3331 myri10ge_reset_recover ? " " : " not");
3332 if (myri10ge_reset_recover == 0)
3333 return;
3334
3335 myri10ge_reset_recover--;
3336
0da34b6d
BG		 3337 /*
3338 * A rebooted nic will come back with config space as
3339 * it was after power was applied to PCIe bus.
3340 * Attempt to restore config space which was saved
3341 * when the driver was loaded, or the last time the
3342 * nic was resumed from power saving mode.
3343 */
83f6e152 3344 pci_restore_state(mgp->pdev);
7adda30c
BG		 3345
3346 /* save state again for accounting reasons */
83f6e152 3347 pci_save_state(mgp->pdev);
7adda30c 3348
0da34b6d
BG		 3349 } else {
3350 /* if we get back -1's from our slot, perhaps somebody
3351 * powered off our card. Don't try to reset it in
3352 * this case */
3353 if (cmd == 0xffff) {
3354 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3355 if (vendor == 0xffff) {
3356 printk(KERN_ERR
3357 "myri10ge: %s: device disappeared!\n",
3358 mgp->dev->name);
3359 return;
3360 }
3361 }
3362 /* Perhaps it is a software error. Try to reset */
3363
3364 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
3365 mgp->dev->name);
0dcffac1
BG		 3366 for (i = 0; i < mgp->num_slices; i++) {
3367 tx = &mgp->ss[i].tx;
3368 printk(KERN_INFO
3369 "myri10ge: %s: (%d): %d %d %d %d %d\n",
3370 mgp->dev->name, i, tx->req, tx->done,
3371 tx->pkt_start, tx->pkt_done,
3372 (int)ntohl(mgp->ss[i].fw_stats->
3373 send_done_count));
3374 msleep(2000);
3375 printk(KERN_INFO
3376 "myri10ge: %s: (%d): %d %d %d %d %d\n",
3377 mgp->dev->name, i, tx->req, tx->done,
3378 tx->pkt_start, tx->pkt_done,
3379 (int)ntohl(mgp->ss[i].fw_stats->
3380 send_done_count));
3381 }
0da34b6d
BG		 3382 }
3383 rtnl_lock();
3384 myri10ge_close(mgp->dev);
0dcffac1 3385 status = myri10ge_load_firmware(mgp, 1);
0da34b6d
BG		 3386 if (status != 0)
3387 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
3388 mgp->dev->name);
3389 else
3390 myri10ge_open(mgp->dev);
3391 rtnl_unlock();
3392}
3393
3394/*
3395 * We use our own timer routine rather than relying upon
3396 * netdev->tx_timeout because we have a very large hardware transmit
3397 * queue. Due to the large queue, the netdev->tx_timeout function
3398 * cannot detect a NIC with a parity error in a timely fashion if the
3399 * NIC is lightly loaded.
3400 */
3401static void myri10ge_watchdog_timer(unsigned long arg)
3402{
3403 struct myri10ge_priv *mgp;
b53bef84 3404 struct myri10ge_slice_state *ss;
0dcffac1 3405 int i, reset_needed;
626fda94 3406 u32 rx_pause_cnt;
0da34b6d
BG		 3407
3408 mgp = (struct myri10ge_priv *)arg;
c7dab99b 3409
0dcffac1
BG		 3410 rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
3411 for (i = 0, reset_needed = 0;
3412 i < mgp->num_slices && reset_needed == 0; ++i) {
b53bef84 3413
0dcffac1
BG		 3414 ss = &mgp->ss[i];
3415 if (ss->rx_small.watchdog_needed) {
3416 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3417 mgp->small_bytes + MXGEFW_PAD,
3418 1);
3419 if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
3420 myri10ge_fill_thresh)
3421 ss->rx_small.watchdog_needed = 0;
3422 }
3423 if (ss->rx_big.watchdog_needed) {
3424 myri10ge_alloc_rx_pages(mgp, &ss->rx_big,
3425 mgp->big_bytes, 1);
3426 if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
3427 myri10ge_fill_thresh)
3428 ss->rx_big.watchdog_needed = 0;
3429 }
3430
3431 if (ss->tx.req != ss->tx.done &&
3432 ss->tx.done == ss->watchdog_tx_done &&
3433 ss->watchdog_tx_req != ss->watchdog_tx_done) {
3434 /* nic seems like it might be stuck.. */
3435 if (rx_pause_cnt != mgp->watchdog_pause) {
3436 if (net_ratelimit())
3437 printk(KERN_WARNING "myri10ge %s:"
3438 "TX paused, check link partner\n",
3439 mgp->dev->name);
3440 } else {
3441 reset_needed = 1;
3442 }
626fda94 3443 }
0dcffac1
BG		 3444 ss->watchdog_tx_done = ss->tx.done;
3445 ss->watchdog_tx_req = ss->tx.req;
626fda94 3446 }
626fda94 3447 mgp->watchdog_pause = rx_pause_cnt;
0dcffac1
BG		 3448
3449 if (reset_needed) {
3450 schedule_work(&mgp->watchdog_work);
3451 } else {
3452 /* rearm timer */
3453 mod_timer(&mgp->watchdog_timer,
3454 jiffies + myri10ge_watchdog_timeout * HZ);
3455 }
0da34b6d
BG		 3456}
3457
77929732
BG		 3458static void myri10ge_free_slices(struct myri10ge_priv *mgp)
3459{
3460 struct myri10ge_slice_state *ss;
3461 struct pci_dev *pdev = mgp->pdev;
3462 size_t bytes;
3463 int i;
3464
3465 if (mgp->ss == NULL)
3466 return;
3467
3468 for (i = 0; i < mgp->num_slices; i++) {
3469 ss = &mgp->ss[i];
3470 if (ss->rx_done.entry != NULL) {
3471 bytes = mgp->max_intr_slots *
3472 sizeof(*ss->rx_done.entry);
3473 dma_free_coherent(&pdev->dev, bytes,
3474 ss->rx_done.entry, ss->rx_done.bus);
3475 ss->rx_done.entry = NULL;
3476 }
3477 if (ss->fw_stats != NULL) {
3478 bytes = sizeof(*ss->fw_stats);
3479 dma_free_coherent(&pdev->dev, bytes,
3480 ss->fw_stats, ss->fw_stats_bus);
3481 ss->fw_stats = NULL;
3482 }
3483 }
3484 kfree(mgp->ss);
3485 mgp->ss = NULL;
3486}
3487
3488static int myri10ge_alloc_slices(struct myri10ge_priv *mgp)
3489{
3490 struct myri10ge_slice_state *ss;
3491 struct pci_dev *pdev = mgp->pdev;
3492 size_t bytes;
3493 int i;
3494
3495 bytes = sizeof(*mgp->ss) * mgp->num_slices;
3496 mgp->ss = kzalloc(bytes, GFP_KERNEL);
3497 if (mgp->ss == NULL) {
3498 return -ENOMEM;
3499 }
3500
3501 for (i = 0; i < mgp->num_slices; i++) {
3502 ss = &mgp->ss[i];
3503 bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry);
3504 ss->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3505 &ss->rx_done.bus,
3506 GFP_KERNEL);
3507 if (ss->rx_done.entry == NULL)
3508 goto abort;
3509 memset(ss->rx_done.entry, 0, bytes);
3510 bytes = sizeof(*ss->fw_stats);
3511 ss->fw_stats = dma_alloc_coherent(&pdev->dev, bytes,
3512 &ss->fw_stats_bus,
3513 GFP_KERNEL);
3514 if (ss->fw_stats == NULL)
3515 goto abort;
3516 ss->mgp = mgp;
3517 ss->dev = mgp->dev;
3518 netif_napi_add(ss->dev, &ss->napi, myri10ge_poll,
3519 myri10ge_napi_weight);
3520 }
3521 return 0;
3522abort:
3523 myri10ge_free_slices(mgp);
3524 return -ENOMEM;
3525}
3526
3527/*
3528 * This function determines the number of slices supported.
3529 * The number slices is the minumum of the number of CPUS,
3530 * the number of MSI-X irqs supported, the number of slices
3531 * supported by the firmware
3532 */
3533static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3534{
3535 struct myri10ge_cmd cmd;
3536 struct pci_dev *pdev = mgp->pdev;
3537 char *old_fw;
3538 int i, status, ncpus, msix_cap;
3539
3540 mgp->num_slices = 1;
3541 msix_cap = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3542 ncpus = num_online_cpus();
3543
3544 if (myri10ge_max_slices == 1 || msix_cap == 0 ||
3545 (myri10ge_max_slices == -1 && ncpus < 2))
3546 return;
3547
3548 /* try to load the slice aware rss firmware */
3549 old_fw = mgp->fw_name;
13b2738c
BG		 3550 if (myri10ge_fw_name != NULL) {
3551 dev_info(&mgp->pdev->dev, "overriding rss firmware to %s\n",
3552 myri10ge_fw_name);
3553 mgp->fw_name = myri10ge_fw_name;
3554 } else if (old_fw == myri10ge_fw_aligned)
77929732
BG		 3555 mgp->fw_name = myri10ge_fw_rss_aligned;
3556 else
3557 mgp->fw_name = myri10ge_fw_rss_unaligned;
3558 status = myri10ge_load_firmware(mgp, 0);
3559 if (status != 0) {
3560 dev_info(&pdev->dev, "Rss firmware not found\n");
3561 return;
3562 }
3563
3564 /* hit the board with a reset to ensure it is alive */
3565 memset(&cmd, 0, sizeof(cmd));
3566 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
3567 if (status != 0) {
3568 dev_err(&mgp->pdev->dev, "failed reset\n");
3569 goto abort_with_fw;
3570 return;
3571 }
3572
3573 mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot);
3574
3575 /* tell it the size of the interrupt queues */
3576 cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot);
3577 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
3578 if (status != 0) {
3579 dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3580 goto abort_with_fw;
3581 }
3582
3583 /* ask the maximum number of slices it supports */
3584 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0);
3585 if (status != 0)
3586 goto abort_with_fw;
3587 else
3588 mgp->num_slices = cmd.data0;
3589
3590 /* Only allow multiple slices if MSI-X is usable */
3591 if (!myri10ge_msi) {
3592 goto abort_with_fw;
3593 }
3594
3595 /* if the admin did not specify a limit to how many
3596 * slices we should use, cap it automatically to the
3597 * number of CPUs currently online */
3598 if (myri10ge_max_slices == -1)
3599 myri10ge_max_slices = ncpus;
3600
3601 if (mgp->num_slices > myri10ge_max_slices)
3602 mgp->num_slices = myri10ge_max_slices;
3603
3604 /* Now try to allocate as many MSI-X vectors as we have
3605 * slices. We give up on MSI-X if we can only get a single
3606 * vector. */
3607
3608 mgp->msix_vectors = kzalloc(mgp->num_slices *
3609 sizeof(*mgp->msix_vectors), GFP_KERNEL);
3610 if (mgp->msix_vectors == NULL)
3611 goto disable_msix;
3612 for (i = 0; i < mgp->num_slices; i++) {
3613 mgp->msix_vectors[i].entry = i;
3614 }
3615
3616 while (mgp->num_slices > 1) {
3617 /* make sure it is a power of two */
3618 while (!is_power_of_2(mgp->num_slices))
3619 mgp->num_slices--;
3620 if (mgp->num_slices == 1)
3621 goto disable_msix;
3622 status = pci_enable_msix(pdev, mgp->msix_vectors,
3623 mgp->num_slices);
3624 if (status == 0) {
3625 pci_disable_msix(pdev);
3626 return;
3627 }
3628 if (status > 0)
3629 mgp->num_slices = status;
3630 else
3631 goto disable_msix;
3632 }
3633
3634disable_msix:
3635 if (mgp->msix_vectors != NULL) {
3636 kfree(mgp->msix_vectors);
3637 mgp->msix_vectors = NULL;
3638 }
3639
3640abort_with_fw:
3641 mgp->num_slices = 1;
3642 mgp->fw_name = old_fw;
3643 myri10ge_load_firmware(mgp, 0);
3644}
77929732 3645
0da34b6d
BG		 3646static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3647{
3648 struct net_device *netdev;
3649 struct myri10ge_priv *mgp;
3650 struct device *dev = &pdev->dev;
0da34b6d
BG		 3651 int i;
3652 int status = -ENXIO;
0da34b6d 3653 int dac_enabled;
0da34b6d
BG		 3654
3655 netdev = alloc_etherdev(sizeof(*mgp));
3656 if (netdev == NULL) {
3657 dev_err(dev, "Could not allocate ethernet device\n");
3658 return -ENOMEM;
3659 }
3660
b245fb67
MH		 3661 SET_NETDEV_DEV(netdev, &pdev->dev);
3662
0da34b6d 3663 mgp = netdev_priv(netdev);
0da34b6d
BG		 3664 mgp->dev = netdev;
3665 mgp->pdev = pdev;
3666 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3667 mgp->pause = myri10ge_flow_control;
3668 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
c58ac5ca 3669 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
0da34b6d
BG		 3670 init_waitqueue_head(&mgp->down_wq);
3671
3672 if (pci_enable_device(pdev)) {
3673 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3674 status = -ENODEV;
3675 goto abort_with_netdev;
3676 }
0da34b6d
BG		 3677
3678 /* Find the vendor-specific cap so we can check
3679 * the reboot register later on */
3680 mgp->vendor_specific_offset
3681 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3682
3683 /* Set our max read request to 4KB */
302d242c 3684 status = pcie_set_readrq(pdev, 4096);
0da34b6d
BG		 3685 if (status != 0) {
3686 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3687 status);
3688 goto abort_with_netdev;
3689 }
3690
3691 pci_set_master(pdev);
3692 dac_enabled = 1;
3693 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
3694 if (status != 0) {
3695 dac_enabled = 0;
3696 dev_err(&pdev->dev,
898eb71c
JP		 3697 "64-bit pci address mask was refused, "
3698 "trying 32-bit\n");
0da34b6d
BG		 3699 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3700 }
3701 if (status != 0) {
3702 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
3703 goto abort_with_netdev;
3704 }
77970ea5 3705 (void)pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
b10c0668
BG		 3706 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3707 &mgp->cmd_bus, GFP_KERNEL);
0da34b6d
BG		 3708 if (mgp->cmd == NULL)
3709 goto abort_with_netdev;
3710
0da34b6d
BG		 3711 mgp->board_span = pci_resource_len(pdev, 0);
3712 mgp->iomem_base = pci_resource_start(pdev, 0);
3713 mgp->mtrr = -1;
276e26c3 3714 mgp->wc_enabled = 0;
0da34b6d
BG		 3715#ifdef CONFIG_MTRR
3716 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3717 MTRR_TYPE_WRCOMB, 1);
276e26c3
BG		 3718 if (mgp->mtrr >= 0)
3719 mgp->wc_enabled = 1;
0da34b6d
BG		 3720#endif
3721 /* Hack. need to get rid of these magic numbers */
3722 mgp->sram_size =
3723 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
3724 if (mgp->sram_size > mgp->board_span) {
3725 dev_err(&pdev->dev, "board span %ld bytes too small\n",
3726 mgp->board_span);
c7f80993 3727 goto abort_with_mtrr;
0da34b6d 3728 }
c7f80993 3729 mgp->sram = ioremap_wc(mgp->iomem_base, mgp->board_span);
0da34b6d
BG		 3730 if (mgp->sram == NULL) {
3731 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3732 mgp->board_span, mgp->iomem_base);
3733 status = -ENXIO;
c7f80993 3734 goto abort_with_mtrr;
0da34b6d
BG		 3735 }
3736 memcpy_fromio(mgp->eeprom_strings,
3737 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
3738 MYRI10GE_EEPROM_STRINGS_SIZE);
3739 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3740 status = myri10ge_read_mac_addr(mgp);
3741 if (status)
3742 goto abort_with_ioremap;
3743
3744 for (i = 0; i < ETH_ALEN; i++)
3745 netdev->dev_addr[i] = mgp->mac_addr[i];
3746
5443e9ea
BG		 3747 myri10ge_select_firmware(mgp);
3748
0dcffac1 3749 status = myri10ge_load_firmware(mgp, 1);
0da34b6d
BG		 3750 if (status != 0) {
3751 dev_err(&pdev->dev, "failed to load firmware\n");
0dcffac1
BG		 3752 goto abort_with_ioremap;
3753 }
3754 myri10ge_probe_slices(mgp);
3755 status = myri10ge_alloc_slices(mgp);
3756 if (status != 0) {
3757 dev_err(&pdev->dev, "failed to alloc slice state\n");
3758 goto abort_with_firmware;
0da34b6d
BG		 3759 }
3760
3761 status = myri10ge_reset(mgp);
3762 if (status != 0) {
3763 dev_err(&pdev->dev, "failed reset\n");
0dcffac1 3764 goto abort_with_slices;
0da34b6d 3765 }
981813d8
BG		 3766#ifdef CONFIG_DCA
3767 myri10ge_setup_dca(mgp);
3768#endif
0da34b6d
BG		 3769 pci_set_drvdata(pdev, mgp);
3770 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3771 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3772 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3773 myri10ge_initial_mtu = 68;
3774 netdev->mtu = myri10ge_initial_mtu;
3775 netdev->open = myri10ge_open;
3776 netdev->stop = myri10ge_close;
3777 netdev->hard_start_xmit = myri10ge_xmit;
3778 netdev->get_stats = myri10ge_get_stats;
3779 netdev->base_addr = mgp->iomem_base;
0da34b6d
BG		 3780 netdev->change_mtu = myri10ge_change_mtu;
3781 netdev->set_multicast_list = myri10ge_set_multicast_list;
3782 netdev->set_mac_address = myri10ge_set_mac_address;
4f93fde0 3783 netdev->features = mgp->features;
0da34b6d
BG		 3784 if (dac_enabled)
3785 netdev->features |= NETIF_F_HIGHDMA;
0da34b6d 3786
21d05db1
BG		 3787 /* make sure we can get an irq, and that MSI can be
3788 * setup (if available). Also ensure netdev->irq
3789 * is set to correct value if MSI is enabled */
3790 status = myri10ge_request_irq(mgp);
3791 if (status != 0)
3792 goto abort_with_firmware;
3793 netdev->irq = pdev->irq;
3794 myri10ge_free_irq(mgp);
3795
0da34b6d
BG		 3796 /* Save configuration space to be restored if the
3797 * nic resets due to a parity error */
83f6e152 3798 pci_save_state(pdev);
0da34b6d
BG		 3799
3800 /* Setup the watchdog timer */
3801 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3802 (unsigned long)mgp);
3803
3804 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
c4028958 3805 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
0da34b6d
BG		 3806 status = register_netdev(netdev);
3807 if (status != 0) {
3808 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
7adda30c 3809 goto abort_with_state;
0da34b6d 3810 }
0dcffac1
BG		 3811 if (mgp->msix_enabled)
3812 dev_info(dev, "%d MSI-X IRQs, tx bndry %d, fw %s, WC %s\n",
3813 mgp->num_slices, mgp->tx_boundary, mgp->fw_name,
3814 (mgp->wc_enabled ? "Enabled" : "Disabled"));
3815 else
3816 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3817 mgp->msi_enabled ? "MSI" : "xPIC",
3818 netdev->irq, mgp->tx_boundary, mgp->fw_name,
3819 (mgp->wc_enabled ? "Enabled" : "Disabled"));
0da34b6d
BG		 3820
3821 return 0;
3822
7adda30c 3823abort_with_state:
83f6e152 3824 pci_restore_state(pdev);
0da34b6d 3825
0dcffac1
BG		 3826abort_with_slices:
3827 myri10ge_free_slices(mgp);
3828
0da34b6d
BG		 3829abort_with_firmware:
3830 myri10ge_dummy_rdma(mgp, 0);
3831
0da34b6d
BG		 3832abort_with_ioremap:
3833 iounmap(mgp->sram);
3834
c7f80993 3835abort_with_mtrr:
0da34b6d
BG		 3836#ifdef CONFIG_MTRR
3837 if (mgp->mtrr >= 0)
3838 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3839#endif
b10c0668
BG		 3840 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3841 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 3842
3843abort_with_netdev:
3844
3845 free_netdev(netdev);
3846 return status;
3847}
3848
3849/*
3850 * myri10ge_remove
3851 *
3852 * Does what is necessary to shutdown one Myrinet device. Called
3853 * once for each Myrinet card by the kernel when a module is
3854 * unloaded.
3855 */
3856static void myri10ge_remove(struct pci_dev *pdev)
3857{
3858 struct myri10ge_priv *mgp;
3859 struct net_device *netdev;
0da34b6d
BG		 3860
3861 mgp = pci_get_drvdata(pdev);
3862 if (mgp == NULL)
3863 return;
3864
3865 flush_scheduled_work();
3866 netdev = mgp->dev;
3867 unregister_netdev(netdev);
0da34b6d 3868
981813d8
BG		 3869#ifdef CONFIG_DCA
3870 myri10ge_teardown_dca(mgp);
3871#endif
0da34b6d
BG		 3872 myri10ge_dummy_rdma(mgp, 0);
3873
7adda30c 3874 /* avoid a memory leak */
83f6e152 3875 pci_restore_state(pdev);
7adda30c 3876
0da34b6d
BG		 3877 iounmap(mgp->sram);
3878
3879#ifdef CONFIG_MTRR
3880 if (mgp->mtrr >= 0)
3881 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3882#endif
0dcffac1
BG		 3883 myri10ge_free_slices(mgp);
3884 if (mgp->msix_vectors != NULL)
3885 kfree(mgp->msix_vectors);
b10c0668
BG		 3886 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3887 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 3888
3889 free_netdev(netdev);
3890 pci_set_drvdata(pdev, NULL);
3891}
3892
b10c0668 3893#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
a07bc1ff 3894#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
0da34b6d
BG		 3895
3896static struct pci_device_id myri10ge_pci_tbl[] = {
b10c0668 3897 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
a07bc1ff
BG		 3898 {PCI_DEVICE
3899 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
0da34b6d
BG		 3900 {0},
3901};
3902
3903static struct pci_driver myri10ge_driver = {
3904 .name = "myri10ge",
3905 .probe = myri10ge_probe,
3906 .remove = myri10ge_remove,
3907 .id_table = myri10ge_pci_tbl,
3908#ifdef CONFIG_PM
3909 .suspend = myri10ge_suspend,
3910 .resume = myri10ge_resume,
3911#endif
3912};
3913
981813d8
BG		 3914#ifdef CONFIG_DCA
3915static int
3916myri10ge_notify_dca(struct notifier_block *nb, unsigned long event, void *p)
3917{
3918 int err = driver_for_each_device(&myri10ge_driver.driver,
3919 NULL, &event,
3920 myri10ge_notify_dca_device);
3921
3922 if (err)
3923 return NOTIFY_BAD;
3924 return NOTIFY_DONE;
3925}
3926
3927static struct notifier_block myri10ge_dca_notifier = {
3928 .notifier_call = myri10ge_notify_dca,
3929 .next = NULL,
3930 .priority = 0,
3931};
3932#endif /* CONFIG_DCA */
3933
0da34b6d
BG		 3934static __init int myri10ge_init_module(void)
3935{
3936 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
3937 MYRI10GE_VERSION_STR);
0dcffac1
BG		 3938
3939 if (myri10ge_rss_hash > MXGEFW_RSS_HASH_TYPE_SRC_PORT ||
3940 myri10ge_rss_hash < MXGEFW_RSS_HASH_TYPE_IPV4) {
3941 printk(KERN_ERR
3942 "%s: Illegal rssh hash type %d, defaulting to source port\n",
3943 myri10ge_driver.name, myri10ge_rss_hash);
3944 myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
3945 }
981813d8
BG		 3946#ifdef CONFIG_DCA
3947 dca_register_notify(&myri10ge_dca_notifier);
3948#endif
0dcffac1 3949
0da34b6d
BG		 3950 return pci_register_driver(&myri10ge_driver);
3951}
3952
3953module_init(myri10ge_init_module);
3954
3955static __exit void myri10ge_cleanup_module(void)
3956{
981813d8
BG		 3957#ifdef CONFIG_DCA
3958 dca_unregister_notify(&myri10ge_dca_notifier);
3959#endif
0da34b6d
BG		 3960 pci_unregister_driver(&myri10ge_driver);
3961}
3962
3963module_exit(myri10ge_cleanup_module);
Linux kernel - Deliverables
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