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myri10ge: improve parity error detection and recovery
[deliverable/linux.git] / drivers / net / myri10ge / myri10ge.c
CommitLineData
0da34b6d
BG		 1/*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
e3fd5534 4 * Copyright (C) 2005 - 2009 Myricom, Inc.
0da34b6d
BG		 5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
4a2e612a
BG		 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0da34b6d 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4a2e612a
BG		 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
0da34b6d
BG		 30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41#include <linux/tcp.h>
42#include <linux/netdevice.h>
43#include <linux/skbuff.h>
44#include <linux/string.h>
45#include <linux/module.h>
46#include <linux/pci.h>
b10c0668 47#include <linux/dma-mapping.h>
0da34b6d
BG		 48#include <linux/etherdevice.h>
49#include <linux/if_ether.h>
50#include <linux/if_vlan.h>
1e6e9342 51#include <linux/inet_lro.h>
981813d8 52#include <linux/dca.h>
0da34b6d
BG		 53#include <linux/ip.h>
54#include <linux/inet.h>
55#include <linux/in.h>
56#include <linux/ethtool.h>
57#include <linux/firmware.h>
58#include <linux/delay.h>
0da34b6d
BG		 59#include <linux/timer.h>
60#include <linux/vmalloc.h>
61#include <linux/crc32.h>
62#include <linux/moduleparam.h>
63#include <linux/io.h>
199126a2 64#include <linux/log2.h>
0da34b6d 65#include <net/checksum.h>
1e6e9342
AG		 66#include <net/ip.h>
67#include <net/tcp.h>
0da34b6d
BG		 68#include <asm/byteorder.h>
69#include <asm/io.h>
0da34b6d
BG		 70#include <asm/processor.h>
71#ifdef CONFIG_MTRR
72#include <asm/mtrr.h>
73#endif
74
75#include "myri10ge_mcp.h"
76#include "myri10ge_mcp_gen_header.h"
77
d0234215 78#define MYRI10GE_VERSION_STR "1.5.0-1.432"
0da34b6d
BG		 79
80MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
81MODULE_AUTHOR("Maintainer: help@myri.com");
82MODULE_VERSION(MYRI10GE_VERSION_STR);
83MODULE_LICENSE("Dual BSD/GPL");
84
85#define MYRI10GE_MAX_ETHER_MTU 9014
86
87#define MYRI10GE_ETH_STOPPED 0
88#define MYRI10GE_ETH_STOPPING 1
89#define MYRI10GE_ETH_STARTING 2
90#define MYRI10GE_ETH_RUNNING 3
91#define MYRI10GE_ETH_OPEN_FAILED 4
92
93#define MYRI10GE_EEPROM_STRINGS_SIZE 256
94#define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
1e6e9342
AG		 95#define MYRI10GE_MAX_LRO_DESCRIPTORS 8
96#define MYRI10GE_LRO_MAX_PKTS 64
0da34b6d 97
40f6cff5 98#define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
0da34b6d
BG		 99#define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
100
dd50f336
BG		 101#define MYRI10GE_ALLOC_ORDER 0
102#define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
103#define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
104
236bb5e6
BG		 105#define MYRI10GE_MAX_SLICES 32
106
0da34b6d 107struct myri10ge_rx_buffer_state {
dd50f336
BG		 108 struct page *page;
109 int page_offset;
0da34b6d
BG		 110 DECLARE_PCI_UNMAP_ADDR(bus)
111 DECLARE_PCI_UNMAP_LEN(len)
112};
113
114struct myri10ge_tx_buffer_state {
115 struct sk_buff *skb;
116 int last;
117 DECLARE_PCI_UNMAP_ADDR(bus)
118 DECLARE_PCI_UNMAP_LEN(len)
119};
120
121struct myri10ge_cmd {
122 u32 data0;
123 u32 data1;
124 u32 data2;
125};
126
127struct myri10ge_rx_buf {
128 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
0da34b6d
BG		 129 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
130 struct myri10ge_rx_buffer_state *info;
dd50f336
BG		 131 struct page *page;
132 dma_addr_t bus;
133 int page_offset;
0da34b6d 134 int cnt;
dd50f336 135 int fill_cnt;
0da34b6d
BG		 136 int alloc_fail;
137 int mask; /* number of rx slots -1 */
dd50f336 138 int watchdog_needed;
0da34b6d
BG		 139};
140
141struct myri10ge_tx_buf {
142 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
236bb5e6
BG		 143 __be32 __iomem *send_go; /* "go" doorbell ptr */
144 __be32 __iomem *send_stop; /* "stop" doorbell ptr */
0da34b6d
BG		 145 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
146 char *req_bytes;
147 struct myri10ge_tx_buffer_state *info;
148 int mask; /* number of transmit slots -1 */
0da34b6d
BG		 149 int req ____cacheline_aligned; /* transmit slots submitted */
150 int pkt_start; /* packets started */
b53bef84
BG		 151 int stop_queue;
152 int linearized;
0da34b6d
BG		 153 int done ____cacheline_aligned; /* transmit slots completed */
154 int pkt_done; /* packets completed */
b53bef84 155 int wake_queue;
236bb5e6 156 int queue_active;
0da34b6d
BG		 157};
158
159struct myri10ge_rx_done {
160 struct mcp_slot *entry;
161 dma_addr_t bus;
162 int cnt;
163 int idx;
1e6e9342
AG		 164 struct net_lro_mgr lro_mgr;
165 struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
0da34b6d
BG		 166};
167
b53bef84
BG		 168struct myri10ge_slice_netstats {
169 unsigned long rx_packets;
170 unsigned long tx_packets;
171 unsigned long rx_bytes;
172 unsigned long tx_bytes;
173 unsigned long rx_dropped;
174 unsigned long tx_dropped;
175};
176
177struct myri10ge_slice_state {
0da34b6d
BG		 178 struct myri10ge_tx_buf tx; /* transmit ring */
179 struct myri10ge_rx_buf rx_small;
180 struct myri10ge_rx_buf rx_big;
181 struct myri10ge_rx_done rx_done;
b53bef84
BG		 182 struct net_device *dev;
183 struct napi_struct napi;
184 struct myri10ge_priv *mgp;
185 struct myri10ge_slice_netstats stats;
186 __be32 __iomem *irq_claim;
187 struct mcp_irq_data *fw_stats;
188 dma_addr_t fw_stats_bus;
189 int watchdog_tx_done;
190 int watchdog_tx_req;
d0234215 191 int watchdog_rx_done;
5dd2d332 192#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 193 int cached_dca_tag;
194 int cpu;
195 __be32 __iomem *dca_tag;
196#endif
0dcffac1 197 char irq_desc[32];
b53bef84
BG		 198};
199
200struct myri10ge_priv {
0dcffac1 201 struct myri10ge_slice_state *ss;
b53bef84 202 int tx_boundary; /* boundary transmits cannot cross */
0dcffac1 203 int num_slices;
b53bef84
BG		 204 int running; /* running? */
205 int csum_flag; /* rx_csums? */
0da34b6d 206 int small_bytes;
dd50f336 207 int big_bytes;
fa0a90d9 208 int max_intr_slots;
0da34b6d
BG		 209 struct net_device *dev;
210 struct net_device_stats stats;
b53bef84 211 spinlock_t stats_lock;
0da34b6d
BG		 212 u8 __iomem *sram;
213 int sram_size;
214 unsigned long board_span;
215 unsigned long iomem_base;
40f6cff5 216 __be32 __iomem *irq_deassert;
0da34b6d
BG		 217 char *mac_addr_string;
218 struct mcp_cmd_response *cmd;
219 dma_addr_t cmd_bus;
0da34b6d
BG		 220 struct pci_dev *pdev;
221 int msi_enabled;
0dcffac1
BG		 222 int msix_enabled;
223 struct msix_entry *msix_vectors;
5dd2d332 224#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 225 int dca_enabled;
226#endif
66341fff 227 u32 link_state;
0da34b6d
BG		 228 unsigned int rdma_tags_available;
229 int intr_coal_delay;
40f6cff5 230 __be32 __iomem *intr_coal_delay_ptr;
0da34b6d 231 int mtrr;
276e26c3 232 int wc_enabled;
0da34b6d
BG		 233 int down_cnt;
234 wait_queue_head_t down_wq;
235 struct work_struct watchdog_work;
236 struct timer_list watchdog_timer;
0da34b6d 237 int watchdog_resets;
b53bef84 238 int watchdog_pause;
0da34b6d
BG		 239 int pause;
240 char *fw_name;
241 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
c0bf8801 242 char *product_code_string;
0da34b6d 243 char fw_version[128];
9dc6f0e7
BG		 244 int fw_ver_major;
245 int fw_ver_minor;
246 int fw_ver_tiny;
247 int adopted_rx_filter_bug;
0da34b6d
BG		 248 u8 mac_addr[6]; /* eeprom mac address */
249 unsigned long serial_number;
250 int vendor_specific_offset;
85a7ea1b 251 int fw_multicast_support;
4f93fde0
BG		 252 unsigned long features;
253 u32 max_tso6;
0da34b6d
BG		 254 u32 read_dma;
255 u32 write_dma;
256 u32 read_write_dma;
c58ac5ca
BG		 257 u32 link_changes;
258 u32 msg_enable;
2d90b0aa 259 unsigned int board_number;
d0234215 260 int rebooted;
0da34b6d
BG		 261};
262
263static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
264static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
0dcffac1
BG		 265static char *myri10ge_fw_rss_unaligned = "myri10ge_rss_ethp_z8e.dat";
266static char *myri10ge_fw_rss_aligned = "myri10ge_rss_eth_z8e.dat";
0da34b6d
BG		 267
268static char *myri10ge_fw_name = NULL;
269module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
d1ce3a0f 270MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
0da34b6d 271
2d90b0aa
BG		 272#define MYRI10GE_MAX_BOARDS 8
273static char *myri10ge_fw_names[MYRI10GE_MAX_BOARDS] =
7fe624f5 274 {[0 ... (MYRI10GE_MAX_BOARDS - 1)] = NULL };
2d90b0aa
BG		 275module_param_array_named(myri10ge_fw_names, myri10ge_fw_names, charp, NULL,
276 0444);
277MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image names per board");
278
0da34b6d
BG		 279static int myri10ge_ecrc_enable = 1;
280module_param(myri10ge_ecrc_enable, int, S_IRUGO);
d1ce3a0f 281MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
0da34b6d 282
0da34b6d
BG		 283static int myri10ge_small_bytes = -1; /* -1 == auto */
284module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
d1ce3a0f 285MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
0da34b6d
BG		 286
287static int myri10ge_msi = 1; /* enable msi by default */
3621cec5 288module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
d1ce3a0f 289MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
0da34b6d 290
f761fae1 291static int myri10ge_intr_coal_delay = 75;
0da34b6d 292module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
d1ce3a0f 293MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
0da34b6d
BG		 294
295static int myri10ge_flow_control = 1;
296module_param(myri10ge_flow_control, int, S_IRUGO);
d1ce3a0f 297MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
0da34b6d
BG		 298
299static int myri10ge_deassert_wait = 1;
300module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
301MODULE_PARM_DESC(myri10ge_deassert_wait,
d1ce3a0f 302 "Wait when deasserting legacy interrupts");
0da34b6d
BG		 303
304static int myri10ge_force_firmware = 0;
305module_param(myri10ge_force_firmware, int, S_IRUGO);
306MODULE_PARM_DESC(myri10ge_force_firmware,
d1ce3a0f 307 "Force firmware to assume aligned completions");
0da34b6d 308
0da34b6d
BG		 309static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
310module_param(myri10ge_initial_mtu, int, S_IRUGO);
d1ce3a0f 311MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
0da34b6d
BG		 312
313static int myri10ge_napi_weight = 64;
314module_param(myri10ge_napi_weight, int, S_IRUGO);
d1ce3a0f 315MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
0da34b6d
BG		 316
317static int myri10ge_watchdog_timeout = 1;
318module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
d1ce3a0f 319MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
0da34b6d
BG		 320
321static int myri10ge_max_irq_loops = 1048576;
322module_param(myri10ge_max_irq_loops, int, S_IRUGO);
323MODULE_PARM_DESC(myri10ge_max_irq_loops,
d1ce3a0f 324 "Set stuck legacy IRQ detection threshold");
0da34b6d 325
c58ac5ca
BG		 326#define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
327
328static int myri10ge_debug = -1; /* defaults above */
329module_param(myri10ge_debug, int, 0);
330MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
331
1e6e9342
AG		 332static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
333module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
d1ce3a0f
BG		 334MODULE_PARM_DESC(myri10ge_lro_max_pkts,
335 "Number of LRO packets to be aggregated");
1e6e9342 336
dd50f336
BG		 337static int myri10ge_fill_thresh = 256;
338module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
d1ce3a0f 339MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
dd50f336 340
f181137f
BG		 341static int myri10ge_reset_recover = 1;
342
0dcffac1
BG		 343static int myri10ge_max_slices = 1;
344module_param(myri10ge_max_slices, int, S_IRUGO);
345MODULE_PARM_DESC(myri10ge_max_slices, "Max tx/rx queues");
346
347static int myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
348module_param(myri10ge_rss_hash, int, S_IRUGO);
349MODULE_PARM_DESC(myri10ge_rss_hash, "Type of RSS hashing to do");
350
981813d8
BG		 351static int myri10ge_dca = 1;
352module_param(myri10ge_dca, int, S_IRUGO);
353MODULE_PARM_DESC(myri10ge_dca, "Enable DCA if possible");
354
0da34b6d
BG		 355#define MYRI10GE_FW_OFFSET 1024*1024
356#define MYRI10GE_HIGHPART_TO_U32(X) \
357(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
358#define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
359
360#define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
361
2f76216f 362static void myri10ge_set_multicast_list(struct net_device *dev);
4f93fde0 363static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev);
2f76216f 364
6250223e 365static inline void put_be32(__be32 val, __be32 __iomem * p)
40f6cff5 366{
6250223e 367 __raw_writel((__force __u32) val, (__force void __iomem *)p);
40f6cff5
AV		 368}
369
59081825
BG		 370static struct net_device_stats *myri10ge_get_stats(struct net_device *dev);
371
0da34b6d
BG		 372static int
373myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
374 struct myri10ge_cmd *data, int atomic)
375{
376 struct mcp_cmd *buf;
377 char buf_bytes[sizeof(*buf) + 8];
378 struct mcp_cmd_response *response = mgp->cmd;
e700f9f4 379 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
0da34b6d
BG		 380 u32 dma_low, dma_high, result, value;
381 int sleep_total = 0;
382
383 /* ensure buf is aligned to 8 bytes */
384 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
385
386 buf->data0 = htonl(data->data0);
387 buf->data1 = htonl(data->data1);
388 buf->data2 = htonl(data->data2);
389 buf->cmd = htonl(cmd);
390 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
391 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
392
393 buf->response_addr.low = htonl(dma_low);
394 buf->response_addr.high = htonl(dma_high);
40f6cff5 395 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 396 mb();
397 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
398
399 /* wait up to 15ms. Longest command is the DMA benchmark,
400 * which is capped at 5ms, but runs from a timeout handler
401 * that runs every 7.8ms. So a 15ms timeout leaves us with
402 * a 2.2ms margin
403 */
404 if (atomic) {
405 /* if atomic is set, do not sleep,
406 * and try to get the completion quickly
407 * (1ms will be enough for those commands) */
408 for (sleep_total = 0;
409 sleep_total < 1000
40f6cff5 410 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
bd2db0cf 411 sleep_total += 10) {
0da34b6d 412 udelay(10);
bd2db0cf
BG		 413 mb();
414 }
0da34b6d
BG		 415 } else {
416 /* use msleep for most command */
417 for (sleep_total = 0;
418 sleep_total < 15
40f6cff5 419 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 420 sleep_total++)
421 msleep(1);
422 }
423
424 result = ntohl(response->result);
425 value = ntohl(response->data);
426 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
427 if (result == 0) {
428 data->data0 = value;
429 return 0;
85a7ea1b
BG		 430 } else if (result == MXGEFW_CMD_UNKNOWN) {
431 return -ENOSYS;
5443e9ea
BG		 432 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
433 return -E2BIG;
236bb5e6
BG		 434 } else if (result == MXGEFW_CMD_ERROR_RANGE &&
435 cmd == MXGEFW_CMD_ENABLE_RSS_QUEUES &&
436 (data->
437 data1 & MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES) !=
438 0) {
439 return -ERANGE;
0da34b6d
BG		 440 } else {
441 dev_err(&mgp->pdev->dev,
442 "command %d failed, result = %d\n",
443 cmd, result);
444 return -ENXIO;
445 }
446 }
447
448 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
449 cmd, result);
450 return -EAGAIN;
451}
452
453/*
454 * The eeprom strings on the lanaiX have the format
455 * SN=x\0
456 * MAC=x:x:x:x:x:x\0
457 * PT:ddd mmm xx xx:xx:xx xx\0
458 * PV:ddd mmm xx xx:xx:xx xx\0
459 */
460static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
461{
462 char *ptr, *limit;
463 int i;
464
465 ptr = mgp->eeprom_strings;
466 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
467
468 while (*ptr != '\0' && ptr < limit) {
469 if (memcmp(ptr, "MAC=", 4) == 0) {
470 ptr += 4;
471 mgp->mac_addr_string = ptr;
472 for (i = 0; i < 6; i++) {
473 if ((ptr + 2) > limit)
474 goto abort;
475 mgp->mac_addr[i] =
476 simple_strtoul(ptr, &ptr, 16);
477 ptr += 1;
478 }
479 }
c0bf8801
BG		 480 if (memcmp(ptr, "PC=", 3) == 0) {
481 ptr += 3;
482 mgp->product_code_string = ptr;
483 }
0da34b6d
BG		 484 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
485 ptr += 3;
486 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
487 }
488 while (ptr < limit && *ptr++) ;
489 }
490
491 return 0;
492
493abort:
494 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
495 return -ENXIO;
496}
497
498/*
499 * Enable or disable periodic RDMAs from the host to make certain
500 * chipsets resend dropped PCIe messages
501 */
502
503static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
504{
505 char __iomem *submit;
f8fd57c1 506 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 507 u32 dma_low, dma_high;
508 int i;
509
510 /* clear confirmation addr */
511 mgp->cmd->data = 0;
512 mb();
513
514 /* send a rdma command to the PCIe engine, and wait for the
515 * response in the confirmation address. The firmware should
516 * write a -1 there to indicate it is alive and well
517 */
518 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
519 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
520
521 buf[0] = htonl(dma_high); /* confirm addr MSW */
522 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 523 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 524 buf[3] = htonl(dma_high); /* dummy addr MSW */
525 buf[4] = htonl(dma_low); /* dummy addr LSW */
526 buf[5] = htonl(enable); /* enable? */
527
e700f9f4 528 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
0da34b6d
BG		 529
530 myri10ge_pio_copy(submit, &buf, sizeof(buf));
531 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
532 msleep(1);
533 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
534 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
535 (enable ? "enable" : "disable"));
536}
537
538static int
539myri10ge_validate_firmware(struct myri10ge_priv *mgp,
540 struct mcp_gen_header *hdr)
541{
542 struct device *dev = &mgp->pdev->dev;
0da34b6d
BG		 543
544 /* check firmware type */
545 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
546 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
547 return -EINVAL;
548 }
549
550 /* save firmware version for ethtool */
551 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
552
9dc6f0e7
BG		 553 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
554 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
0da34b6d 555
9dc6f0e7
BG		 556 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
557 && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
0da34b6d
BG		 558 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
559 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
560 MXGEFW_VERSION_MINOR);
561 return -EINVAL;
562 }
563 return 0;
564}
565
566static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
567{
568 unsigned crc, reread_crc;
569 const struct firmware *fw;
570 struct device *dev = &mgp->pdev->dev;
b0d31d6b 571 unsigned char *fw_readback;
0da34b6d
BG		 572 struct mcp_gen_header *hdr;
573 size_t hdr_offset;
574 int status;
e454358a 575 unsigned i;
0da34b6d
BG		 576
577 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
578 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
579 mgp->fw_name);
580 status = -EINVAL;
581 goto abort_with_nothing;
582 }
583
584 /* check size */
585
586 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
587 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
588 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
589 status = -EINVAL;
590 goto abort_with_fw;
591 }
592
593 /* check id */
40f6cff5 594 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 595 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
596 dev_err(dev, "Bad firmware file\n");
597 status = -EINVAL;
598 goto abort_with_fw;
599 }
600 hdr = (void *)(fw->data + hdr_offset);
601
602 status = myri10ge_validate_firmware(mgp, hdr);
603 if (status != 0)
604 goto abort_with_fw;
605
606 crc = crc32(~0, fw->data, fw->size);
e454358a
BG		 607 for (i = 0; i < fw->size; i += 256) {
608 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
609 fw->data + i,
610 min(256U, (unsigned)(fw->size - i)));
611 mb();
612 readb(mgp->sram);
b10c0668 613 }
b0d31d6b
DW		 614 fw_readback = vmalloc(fw->size);
615 if (!fw_readback) {
616 status = -ENOMEM;
617 goto abort_with_fw;
618 }
0da34b6d 619 /* corruption checking is good for parity recovery and buggy chipset */
b0d31d6b
DW		 620 memcpy_fromio(fw_readback, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
621 reread_crc = crc32(~0, fw_readback, fw->size);
622 vfree(fw_readback);
0da34b6d
BG		 623 if (crc != reread_crc) {
624 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
625 (unsigned)fw->size, reread_crc, crc);
626 status = -EIO;
627 goto abort_with_fw;
628 }
629 *size = (u32) fw->size;
630
631abort_with_fw:
632 release_firmware(fw);
633
634abort_with_nothing:
635 return status;
636}
637
638static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
639{
640 struct mcp_gen_header *hdr;
641 struct device *dev = &mgp->pdev->dev;
642 const size_t bytes = sizeof(struct mcp_gen_header);
643 size_t hdr_offset;
644 int status;
645
646 /* find running firmware header */
66341fff 647 hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 648
649 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
650 dev_err(dev, "Running firmware has bad header offset (%d)\n",
651 (int)hdr_offset);
652 return -EIO;
653 }
654
655 /* copy header of running firmware from SRAM to host memory to
656 * validate firmware */
657 hdr = kmalloc(bytes, GFP_KERNEL);
658 if (hdr == NULL) {
659 dev_err(dev, "could not malloc firmware hdr\n");
660 return -ENOMEM;
661 }
662 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
663 status = myri10ge_validate_firmware(mgp, hdr);
664 kfree(hdr);
9dc6f0e7
BG		 665
666 /* check to see if adopted firmware has bug where adopting
667 * it will cause broadcasts to be filtered unless the NIC
668 * is kept in ALLMULTI mode */
669 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
670 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
671 mgp->adopted_rx_filter_bug = 1;
672 dev_warn(dev, "Adopting fw %d.%d.%d: "
673 "working around rx filter bug\n",
674 mgp->fw_ver_major, mgp->fw_ver_minor,
675 mgp->fw_ver_tiny);
676 }
0da34b6d
BG		 677 return status;
678}
679
0178ec3d 680static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
fa0a90d9
BG		 681{
682 struct myri10ge_cmd cmd;
683 int status;
684
685 /* probe for IPv6 TSO support */
686 mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
687 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
688 &cmd, 0);
689 if (status == 0) {
690 mgp->max_tso6 = cmd.data0;
691 mgp->features |= NETIF_F_TSO6;
692 }
693
694 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
695 if (status != 0) {
696 dev_err(&mgp->pdev->dev,
697 "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
698 return -ENXIO;
699 }
700
701 mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
702
703 return 0;
704}
705
0dcffac1 706static int myri10ge_load_firmware(struct myri10ge_priv *mgp, int adopt)
0da34b6d
BG		 707{
708 char __iomem *submit;
f8fd57c1 709 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 710 u32 dma_low, dma_high, size;
711 int status, i;
712
b10c0668 713 size = 0;
0da34b6d
BG		 714 status = myri10ge_load_hotplug_firmware(mgp, &size);
715 if (status) {
0dcffac1
BG		 716 if (!adopt)
717 return status;
0da34b6d
BG		 718 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
719
720 /* Do not attempt to adopt firmware if there
721 * was a bad crc */
722 if (status == -EIO)
723 return status;
724
725 status = myri10ge_adopt_running_firmware(mgp);
726 if (status != 0) {
727 dev_err(&mgp->pdev->dev,
728 "failed to adopt running firmware\n");
729 return status;
730 }
731 dev_info(&mgp->pdev->dev,
732 "Successfully adopted running firmware\n");
b53bef84 733 if (mgp->tx_boundary == 4096) {
0da34b6d
BG		 734 dev_warn(&mgp->pdev->dev,
735 "Using firmware currently running on NIC"
736 ". For optimal\n");
737 dev_warn(&mgp->pdev->dev,
738 "performance consider loading optimized "
739 "firmware\n");
740 dev_warn(&mgp->pdev->dev, "via hotplug\n");
741 }
742
743 mgp->fw_name = "adopted";
b53bef84 744 mgp->tx_boundary = 2048;
fa0a90d9
BG		 745 myri10ge_dummy_rdma(mgp, 1);
746 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d
BG		 747 return status;
748 }
749
750 /* clear confirmation addr */
751 mgp->cmd->data = 0;
752 mb();
753
754 /* send a reload command to the bootstrap MCP, and wait for the
755 * response in the confirmation address. The firmware should
756 * write a -1 there to indicate it is alive and well
757 */
758 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
759 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
760
761 buf[0] = htonl(dma_high); /* confirm addr MSW */
762 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 763 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 764
765 /* FIX: All newest firmware should un-protect the bottom of
766 * the sram before handoff. However, the very first interfaces
767 * do not. Therefore the handoff copy must skip the first 8 bytes
768 */
769 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
770 buf[4] = htonl(size - 8); /* length of code */
771 buf[5] = htonl(8); /* where to copy to */
772 buf[6] = htonl(0); /* where to jump to */
773
e700f9f4 774 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
0da34b6d
BG		 775
776 myri10ge_pio_copy(submit, &buf, sizeof(buf));
777 mb();
778 msleep(1);
779 mb();
780 i = 0;
d93ca2a4
BG		 781 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
782 msleep(1 << i);
0da34b6d
BG		 783 i++;
784 }
785 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
786 dev_err(&mgp->pdev->dev, "handoff failed\n");
787 return -ENXIO;
788 }
9a71db72 789 myri10ge_dummy_rdma(mgp, 1);
fa0a90d9 790 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d 791
fa0a90d9 792 return status;
0da34b6d
BG		 793}
794
795static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
796{
797 struct myri10ge_cmd cmd;
798 int status;
799
800 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
801 | (addr[2] << 8) | addr[3]);
802
803 cmd.data1 = ((addr[4] << 8) | (addr[5]));
804
805 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
806 return status;
807}
808
809static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
810{
811 struct myri10ge_cmd cmd;
812 int status, ctl;
813
814 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
815 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
816
817 if (status) {
818 printk(KERN_ERR
819 "myri10ge: %s: Failed to set flow control mode\n",
820 mgp->dev->name);
821 return status;
822 }
823 mgp->pause = pause;
824 return 0;
825}
826
827static void
828myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
829{
830 struct myri10ge_cmd cmd;
831 int status, ctl;
832
833 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
834 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
835 if (status)
836 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
837 mgp->dev->name);
838}
839
0d6ac257 840static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
0da34b6d
BG		 841{
842 struct myri10ge_cmd cmd;
843 int status;
0da34b6d 844 u32 len;
34fdccea
BG		 845 struct page *dmatest_page;
846 dma_addr_t dmatest_bus;
0d6ac257
BG		 847 char *test = " ";
848
849 dmatest_page = alloc_page(GFP_KERNEL);
850 if (!dmatest_page)
851 return -ENOMEM;
852 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
853 DMA_BIDIRECTIONAL);
854
855 /* Run a small DMA test.
856 * The magic multipliers to the length tell the firmware
857 * to do DMA read, write, or read+write tests. The
858 * results are returned in cmd.data0. The upper 16
859 * bits or the return is the number of transfers completed.
860 * The lower 16 bits is the time in 0.5us ticks that the
861 * transfers took to complete.
862 */
863
b53bef84 864 len = mgp->tx_boundary;
0d6ac257
BG		 865
866 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
867 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
868 cmd.data2 = len * 0x10000;
869 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
870 if (status != 0) {
871 test = "read";
872 goto abort;
873 }
874 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
875 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
876 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
877 cmd.data2 = len * 0x1;
878 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
879 if (status != 0) {
880 test = "write";
881 goto abort;
882 }
883 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
884
885 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
886 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
887 cmd.data2 = len * 0x10001;
888 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
889 if (status != 0) {
890 test = "read/write";
891 goto abort;
892 }
893 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
894 (cmd.data0 & 0xffff);
895
896abort:
897 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
898 put_page(dmatest_page);
899
900 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
901 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
902 test, status);
903
904 return status;
905}
906
907static int myri10ge_reset(struct myri10ge_priv *mgp)
908{
909 struct myri10ge_cmd cmd;
0dcffac1
BG		 910 struct myri10ge_slice_state *ss;
911 int i, status;
0d6ac257 912 size_t bytes;
5dd2d332 913#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 914 unsigned long dca_tag_off;
915#endif
0da34b6d
BG		 916
917 /* try to send a reset command to the card to see if it
918 * is alive */
919 memset(&cmd, 0, sizeof(cmd));
920 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
921 if (status != 0) {
922 dev_err(&mgp->pdev->dev, "failed reset\n");
923 return -ENXIO;
924 }
0d6ac257
BG		 925
926 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
0dcffac1
BG		 927 /*
928 * Use non-ndis mcp_slot (eg, 4 bytes total,
929 * no toeplitz hash value returned. Older firmware will
930 * not understand this command, but will use the correct
931 * sized mcp_slot, so we ignore error returns
932 */
933 cmd.data0 = MXGEFW_RSS_MCP_SLOT_TYPE_MIN;
934 (void)myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, &cmd, 0);
0da34b6d
BG		 935
936 /* Now exchange information about interrupts */
937
0dcffac1 938 bytes = mgp->max_intr_slots * sizeof(*mgp->ss[0].rx_done.entry);
0da34b6d
BG		 939 cmd.data0 = (u32) bytes;
940 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
0dcffac1
BG		 941
942 /*
943 * Even though we already know how many slices are supported
944 * via myri10ge_probe_slices() MXGEFW_CMD_GET_MAX_RSS_QUEUES
945 * has magic side effects, and must be called after a reset.
946 * It must be called prior to calling any RSS related cmds,
947 * including assigning an interrupt queue for anything but
948 * slice 0. It must also be called *after*
949 * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
950 * the firmware to compute offsets.
951 */
952
953 if (mgp->num_slices > 1) {
954
955 /* ask the maximum number of slices it supports */
956 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
957 &cmd, 0);
958 if (status != 0) {
959 dev_err(&mgp->pdev->dev,
960 "failed to get number of slices\n");
961 }
962
963 /*
964 * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
965 * to setting up the interrupt queue DMA
966 */
967
968 cmd.data0 = mgp->num_slices;
236bb5e6
BG		 969 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
970 if (mgp->dev->real_num_tx_queues > 1)
971 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
0dcffac1
BG		 972 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
973 &cmd, 0);
236bb5e6
BG		 974
975 /* Firmware older than 1.4.32 only supports multiple
976 * RX queues, so if we get an error, first retry using a
977 * single TX queue before giving up */
978 if (status != 0 && mgp->dev->real_num_tx_queues > 1) {
979 mgp->dev->real_num_tx_queues = 1;
980 cmd.data0 = mgp->num_slices;
981 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
982 status = myri10ge_send_cmd(mgp,
983 MXGEFW_CMD_ENABLE_RSS_QUEUES,
984 &cmd, 0);
985 }
986
0dcffac1
BG		 987 if (status != 0) {
988 dev_err(&mgp->pdev->dev,
989 "failed to set number of slices\n");
990
991 return status;
992 }
993 }
994 for (i = 0; i < mgp->num_slices; i++) {
995 ss = &mgp->ss[i];
996 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->rx_done.bus);
997 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->rx_done.bus);
998 cmd.data2 = i;
999 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA,
1000 &cmd, 0);
1001 };
0da34b6d
BG		 1002
1003 status |=
1004 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
0dcffac1
BG		 1005 for (i = 0; i < mgp->num_slices; i++) {
1006 ss = &mgp->ss[i];
1007 ss->irq_claim =
1008 (__iomem __be32 *) (mgp->sram + cmd.data0 + 8 * i);
1009 }
df30a740
BG		 1010 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
1011 &cmd, 0);
1012 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d 1013
0da34b6d
BG		 1014 status |= myri10ge_send_cmd
1015 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
40f6cff5 1016 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d
BG		 1017 if (status != 0) {
1018 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
1019 return status;
1020 }
40f6cff5 1021 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d 1022
5dd2d332 1023#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1024 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_DCA_OFFSET, &cmd, 0);
1025 dca_tag_off = cmd.data0;
1026 for (i = 0; i < mgp->num_slices; i++) {
1027 ss = &mgp->ss[i];
1028 if (status == 0) {
1029 ss->dca_tag = (__iomem __be32 *)
1030 (mgp->sram + dca_tag_off + 4 * i);
1031 } else {
1032 ss->dca_tag = NULL;
1033 }
1034 }
4ee2ac51 1035#endif /* CONFIG_MYRI10GE_DCA */
981813d8 1036
0da34b6d 1037 /* reset mcp/driver shared state back to 0 */
0dcffac1 1038
c58ac5ca 1039 mgp->link_changes = 0;
0dcffac1
BG		 1040 for (i = 0; i < mgp->num_slices; i++) {
1041 ss = &mgp->ss[i];
1042
1043 memset(ss->rx_done.entry, 0, bytes);
1044 ss->tx.req = 0;
1045 ss->tx.done = 0;
1046 ss->tx.pkt_start = 0;
1047 ss->tx.pkt_done = 0;
1048 ss->rx_big.cnt = 0;
1049 ss->rx_small.cnt = 0;
1050 ss->rx_done.idx = 0;
1051 ss->rx_done.cnt = 0;
1052 ss->tx.wake_queue = 0;
1053 ss->tx.stop_queue = 0;
1054 }
1055
0da34b6d 1056 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
0da34b6d 1057 myri10ge_change_pause(mgp, mgp->pause);
2f76216f 1058 myri10ge_set_multicast_list(mgp->dev);
0da34b6d
BG		 1059 return status;
1060}
1061
5dd2d332 1062#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1063static void
1064myri10ge_write_dca(struct myri10ge_slice_state *ss, int cpu, int tag)
1065{
1066 ss->cpu = cpu;
1067 ss->cached_dca_tag = tag;
1068 put_be32(htonl(tag), ss->dca_tag);
1069}
1070
1071static inline void myri10ge_update_dca(struct myri10ge_slice_state *ss)
1072{
1073 int cpu = get_cpu();
1074 int tag;
1075
1076 if (cpu != ss->cpu) {
1077 tag = dca_get_tag(cpu);
1078 if (ss->cached_dca_tag != tag)
1079 myri10ge_write_dca(ss, cpu, tag);
1080 }
1081 put_cpu();
1082}
1083
1084static void myri10ge_setup_dca(struct myri10ge_priv *mgp)
1085{
1086 int err, i;
1087 struct pci_dev *pdev = mgp->pdev;
1088
1089 if (mgp->ss[0].dca_tag == NULL || mgp->dca_enabled)
1090 return;
1091 if (!myri10ge_dca) {
1092 dev_err(&pdev->dev, "dca disabled by administrator\n");
1093 return;
1094 }
1095 err = dca_add_requester(&pdev->dev);
1096 if (err) {
330554cb
BG		 1097 if (err != -ENODEV)
1098 dev_err(&pdev->dev,
1099 "dca_add_requester() failed, err=%d\n", err);
981813d8
BG		 1100 return;
1101 }
1102 mgp->dca_enabled = 1;
1103 for (i = 0; i < mgp->num_slices; i++)
1104 myri10ge_write_dca(&mgp->ss[i], -1, 0);
1105}
1106
1107static void myri10ge_teardown_dca(struct myri10ge_priv *mgp)
1108{
1109 struct pci_dev *pdev = mgp->pdev;
1110 int err;
1111
1112 if (!mgp->dca_enabled)
1113 return;
1114 mgp->dca_enabled = 0;
1115 err = dca_remove_requester(&pdev->dev);
1116}
1117
1118static int myri10ge_notify_dca_device(struct device *dev, void *data)
1119{
1120 struct myri10ge_priv *mgp;
1121 unsigned long event;
1122
1123 mgp = dev_get_drvdata(dev);
1124 event = *(unsigned long *)data;
1125
1126 if (event == DCA_PROVIDER_ADD)
1127 myri10ge_setup_dca(mgp);
1128 else if (event == DCA_PROVIDER_REMOVE)
1129 myri10ge_teardown_dca(mgp);
1130 return 0;
1131}
4ee2ac51 1132#endif /* CONFIG_MYRI10GE_DCA */
981813d8 1133
0da34b6d
BG		 1134static inline void
1135myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
1136 struct mcp_kreq_ether_recv *src)
1137{
40f6cff5 1138 __be32 low;
0da34b6d
BG		 1139
1140 low = src->addr_low;
284901a9 1141 src->addr_low = htonl(DMA_BIT_MASK(32));
e67bda55
BG		 1142 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
1143 mb();
1144 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
0da34b6d
BG		 1145 mb();
1146 src->addr_low = low;
40f6cff5 1147 put_be32(low, &dst->addr_low);
0da34b6d
BG		 1148 mb();
1149}
1150
40f6cff5 1151static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
0da34b6d
BG		 1152{
1153 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
1154
40f6cff5 1155 if ((skb->protocol == htons(ETH_P_8021Q)) &&
0da34b6d
BG		 1156 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
1157 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
1158 skb->csum = hw_csum;
84fa7933 1159 skb->ip_summed = CHECKSUM_COMPLETE;
0da34b6d
BG		 1160 }
1161}
1162
dd50f336
BG		 1163static inline void
1164myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
1165 struct skb_frag_struct *rx_frags, int len, int hlen)
1166{
1167 struct skb_frag_struct *skb_frags;
1168
1169 skb->len = skb->data_len = len;
1170 skb->truesize = len + sizeof(struct sk_buff);
1171 /* attach the page(s) */
1172
1173 skb_frags = skb_shinfo(skb)->frags;
1174 while (len > 0) {
1175 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
1176 len -= rx_frags->size;
1177 skb_frags++;
1178 rx_frags++;
1179 skb_shinfo(skb)->nr_frags++;
1180 }
1181
1182 /* pskb_may_pull is not available in irq context, but
1183 * skb_pull() (for ether_pad and eth_type_trans()) requires
1184 * the beginning of the packet in skb_headlen(), move it
1185 * manually */
27d7ff46 1186 skb_copy_to_linear_data(skb, va, hlen);
dd50f336
BG		 1187 skb_shinfo(skb)->frags[0].page_offset += hlen;
1188 skb_shinfo(skb)->frags[0].size -= hlen;
1189 skb->data_len -= hlen;
1190 skb->tail += hlen;
1191 skb_pull(skb, MXGEFW_PAD);
1192}
1193
1194static void
1195myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1196 int bytes, int watchdog)
1197{
1198 struct page *page;
1199 int idx;
1200
1201 if (unlikely(rx->watchdog_needed && !watchdog))
1202 return;
1203
1204 /* try to refill entire ring */
1205 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
1206 idx = rx->fill_cnt & rx->mask;
ae8509b1 1207 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
dd50f336
BG		 1208 /* we can use part of previous page */
1209 get_page(rx->page);
1210 } else {
1211 /* we need a new page */
1212 page =
1213 alloc_pages(GFP_ATOMIC | __GFP_COMP,
1214 MYRI10GE_ALLOC_ORDER);
1215 if (unlikely(page == NULL)) {
1216 if (rx->fill_cnt - rx->cnt < 16)
1217 rx->watchdog_needed = 1;
1218 return;
1219 }
1220 rx->page = page;
1221 rx->page_offset = 0;
1222 rx->bus = pci_map_page(mgp->pdev, page, 0,
1223 MYRI10GE_ALLOC_SIZE,
1224 PCI_DMA_FROMDEVICE);
1225 }
1226 rx->info[idx].page = rx->page;
1227 rx->info[idx].page_offset = rx->page_offset;
1228 /* note that this is the address of the start of the
1229 * page */
1230 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
1231 rx->shadow[idx].addr_low =
1232 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
1233 rx->shadow[idx].addr_high =
1234 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
1235
1236 /* start next packet on a cacheline boundary */
1237 rx->page_offset += SKB_DATA_ALIGN(bytes);
ae8509b1
BG		 1238
1239#if MYRI10GE_ALLOC_SIZE > 4096
1240 /* don't cross a 4KB boundary */
1241 if ((rx->page_offset >> 12) !=
1242 ((rx->page_offset + bytes - 1) >> 12))
1243 rx->page_offset = (rx->page_offset + 4096) & ~4095;
1244#endif
dd50f336
BG		 1245 rx->fill_cnt++;
1246
1247 /* copy 8 descriptors to the firmware at a time */
1248 if ((idx & 7) == 7) {
e454e7e2
BG		 1249 myri10ge_submit_8rx(&rx->lanai[idx - 7],
1250 &rx->shadow[idx - 7]);
dd50f336
BG		 1251 }
1252 }
1253}
1254
1255static inline void
1256myri10ge_unmap_rx_page(struct pci_dev *pdev,
1257 struct myri10ge_rx_buffer_state *info, int bytes)
1258{
1259 /* unmap the recvd page if we're the only or last user of it */
1260 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1261 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1262 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
1263 & ~(MYRI10GE_ALLOC_SIZE - 1)),
1264 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1265 }
1266}
1267
1268#define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
1269 * page into an skb */
1270
1271static inline int
b53bef84 1272myri10ge_rx_done(struct myri10ge_slice_state *ss, struct myri10ge_rx_buf *rx,
52ea6fb3 1273 int bytes, int len, __wsum csum)
dd50f336 1274{
b53bef84 1275 struct myri10ge_priv *mgp = ss->mgp;
dd50f336
BG		 1276 struct sk_buff *skb;
1277 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1278 int i, idx, hlen, remainder;
1279 struct pci_dev *pdev = mgp->pdev;
1280 struct net_device *dev = mgp->dev;
1281 u8 *va;
1282
1283 len += MXGEFW_PAD;
1284 idx = rx->cnt & rx->mask;
1285 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1286 prefetch(va);
1287 /* Fill skb_frag_struct(s) with data from our receive */
1288 for (i = 0, remainder = len; remainder > 0; i++) {
1289 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1290 rx_frags[i].page = rx->info[idx].page;
1291 rx_frags[i].page_offset = rx->info[idx].page_offset;
1292 if (remainder < MYRI10GE_ALLOC_SIZE)
1293 rx_frags[i].size = remainder;
1294 else
1295 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1296 rx->cnt++;
1297 idx = rx->cnt & rx->mask;
1298 remainder -= MYRI10GE_ALLOC_SIZE;
1299 }
1300
3a0c7d2d 1301 if (dev->features & NETIF_F_LRO) {
1e6e9342
AG		 1302 rx_frags[0].page_offset += MXGEFW_PAD;
1303 rx_frags[0].size -= MXGEFW_PAD;
1304 len -= MXGEFW_PAD;
b53bef84 1305 lro_receive_frags(&ss->rx_done.lro_mgr, rx_frags,
b53bef84 1306 /* opaque, will come back in get_frag_header */
0dcffac1 1307 len, len,
b53bef84 1308 (void *)(__force unsigned long)csum, csum);
0dcffac1 1309
1e6e9342
AG		 1310 return 1;
1311 }
1312
dd50f336
BG		 1313 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1314
e636b2ea
BG		 1315 /* allocate an skb to attach the page(s) to. This is done
1316 * after trying LRO, so as to avoid skb allocation overheads */
dd50f336
BG		 1317
1318 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1319 if (unlikely(skb == NULL)) {
d6279c88 1320 ss->stats.rx_dropped++;
dd50f336
BG		 1321 do {
1322 i--;
1323 put_page(rx_frags[i].page);
1324 } while (i != 0);
1325 return 0;
1326 }
1327
1328 /* Attach the pages to the skb, and trim off any padding */
1329 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1330 if (skb_shinfo(skb)->frags[0].size <= 0) {
1331 put_page(skb_shinfo(skb)->frags[0].page);
1332 skb_shinfo(skb)->nr_frags = 0;
1333 }
1334 skb->protocol = eth_type_trans(skb, dev);
0c8dfc83 1335 skb_record_rx_queue(skb, ss - &mgp->ss[0]);
dd50f336
BG		 1336
1337 if (mgp->csum_flag) {
1338 if ((skb->protocol == htons(ETH_P_IP)) ||
1339 (skb->protocol == htons(ETH_P_IPV6))) {
1340 skb->csum = csum;
1341 skb->ip_summed = CHECKSUM_COMPLETE;
1342 } else
1343 myri10ge_vlan_ip_csum(skb, csum);
1344 }
1345 netif_receive_skb(skb);
dd50f336
BG		 1346 return 1;
1347}
1348
b53bef84
BG		 1349static inline void
1350myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index)
0da34b6d 1351{
b53bef84
BG		 1352 struct pci_dev *pdev = ss->mgp->pdev;
1353 struct myri10ge_tx_buf *tx = &ss->tx;
236bb5e6 1354 struct netdev_queue *dev_queue;
0da34b6d
BG		 1355 struct sk_buff *skb;
1356 int idx, len;
0da34b6d
BG		 1357
1358 while (tx->pkt_done != mcp_index) {
1359 idx = tx->done & tx->mask;
1360 skb = tx->info[idx].skb;
1361
1362 /* Mark as free */
1363 tx->info[idx].skb = NULL;
1364 if (tx->info[idx].last) {
1365 tx->pkt_done++;
1366 tx->info[idx].last = 0;
1367 }
1368 tx->done++;
1369 len = pci_unmap_len(&tx->info[idx], len);
1370 pci_unmap_len_set(&tx->info[idx], len, 0);
1371 if (skb) {
b53bef84
BG		 1372 ss->stats.tx_bytes += skb->len;
1373 ss->stats.tx_packets++;
0da34b6d
BG		 1374 dev_kfree_skb_irq(skb);
1375 if (len)
1376 pci_unmap_single(pdev,
1377 pci_unmap_addr(&tx->info[idx],
1378 bus), len,
1379 PCI_DMA_TODEVICE);
1380 } else {
1381 if (len)
1382 pci_unmap_page(pdev,
1383 pci_unmap_addr(&tx->info[idx],
1384 bus), len,
1385 PCI_DMA_TODEVICE);
1386 }
0da34b6d 1387 }
236bb5e6
BG		 1388
1389 dev_queue = netdev_get_tx_queue(ss->dev, ss - ss->mgp->ss);
1390 /*
1391 * Make a minimal effort to prevent the NIC from polling an
1392 * idle tx queue. If we can't get the lock we leave the queue
1393 * active. In this case, either a thread was about to start
1394 * using the queue anyway, or we lost a race and the NIC will
1395 * waste some of its resources polling an inactive queue for a
1396 * while.
1397 */
1398
1399 if ((ss->mgp->dev->real_num_tx_queues > 1) &&
1400 __netif_tx_trylock(dev_queue)) {
1401 if (tx->req == tx->done) {
1402 tx->queue_active = 0;
1403 put_be32(htonl(1), tx->send_stop);
8c2f5fa5 1404 mb();
6824a105 1405 mmiowb();
236bb5e6
BG		 1406 }
1407 __netif_tx_unlock(dev_queue);
1408 }
1409
0da34b6d 1410 /* start the queue if we've stopped it */
236bb5e6 1411 if (netif_tx_queue_stopped(dev_queue)
0da34b6d 1412 && tx->req - tx->done < (tx->mask >> 1)) {
b53bef84 1413 tx->wake_queue++;
236bb5e6 1414 netif_tx_wake_queue(dev_queue);
0da34b6d
BG		 1415 }
1416}
1417
b53bef84
BG		 1418static inline int
1419myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
0da34b6d 1420{
b53bef84
BG		 1421 struct myri10ge_rx_done *rx_done = &ss->rx_done;
1422 struct myri10ge_priv *mgp = ss->mgp;
18af3e7c 1423 struct net_device *netdev = mgp->dev;
0da34b6d
BG		 1424 unsigned long rx_bytes = 0;
1425 unsigned long rx_packets = 0;
1426 unsigned long rx_ok;
1427
1428 int idx = rx_done->idx;
1429 int cnt = rx_done->cnt;
bea3348e 1430 int work_done = 0;
0da34b6d 1431 u16 length;
40f6cff5 1432 __wsum checksum;
0da34b6d 1433
c956a240 1434 while (rx_done->entry[idx].length != 0 && work_done < budget) {
0da34b6d
BG		 1435 length = ntohs(rx_done->entry[idx].length);
1436 rx_done->entry[idx].length = 0;
40f6cff5 1437 checksum = csum_unfold(rx_done->entry[idx].checksum);
0da34b6d 1438 if (length <= mgp->small_bytes)
b53bef84 1439 rx_ok = myri10ge_rx_done(ss, &ss->rx_small,
52ea6fb3
BG		 1440 mgp->small_bytes,
1441 length, checksum);
0da34b6d 1442 else
b53bef84 1443 rx_ok = myri10ge_rx_done(ss, &ss->rx_big,
52ea6fb3
BG		 1444 mgp->big_bytes,
1445 length, checksum);
0da34b6d
BG		 1446 rx_packets += rx_ok;
1447 rx_bytes += rx_ok * (unsigned long)length;
1448 cnt++;
014377a1 1449 idx = cnt & (mgp->max_intr_slots - 1);
c956a240 1450 work_done++;
0da34b6d
BG		 1451 }
1452 rx_done->idx = idx;
1453 rx_done->cnt = cnt;
b53bef84
BG		 1454 ss->stats.rx_packets += rx_packets;
1455 ss->stats.rx_bytes += rx_bytes;
c7dab99b 1456
18af3e7c 1457 if (netdev->features & NETIF_F_LRO)
1e6e9342
AG		 1458 lro_flush_all(&rx_done->lro_mgr);
1459
c7dab99b 1460 /* restock receive rings if needed */
b53bef84
BG		 1461 if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
1462 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
c7dab99b 1463 mgp->small_bytes + MXGEFW_PAD, 0);
b53bef84
BG		 1464 if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh)
1465 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
c7dab99b 1466
bea3348e 1467 return work_done;
0da34b6d
BG		 1468}
1469
1470static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1471{
0dcffac1 1472 struct mcp_irq_data *stats = mgp->ss[0].fw_stats;
0da34b6d
BG		 1473
1474 if (unlikely(stats->stats_updated)) {
798a95db
BG		 1475 unsigned link_up = ntohl(stats->link_up);
1476 if (mgp->link_state != link_up) {
1477 mgp->link_state = link_up;
1478
1479 if (mgp->link_state == MXGEFW_LINK_UP) {
c58ac5ca
BG		 1480 if (netif_msg_link(mgp))
1481 printk(KERN_INFO
1482 "myri10ge: %s: link up\n",
1483 mgp->dev->name);
0da34b6d 1484 netif_carrier_on(mgp->dev);
c58ac5ca 1485 mgp->link_changes++;
0da34b6d 1486 } else {
c58ac5ca
BG		 1487 if (netif_msg_link(mgp))
1488 printk(KERN_INFO
798a95db
BG		 1489 "myri10ge: %s: link %s\n",
1490 mgp->dev->name,
1491 (link_up == MXGEFW_LINK_MYRINET ?
1492 "mismatch (Myrinet detected)" :
1493 "down"));
0da34b6d 1494 netif_carrier_off(mgp->dev);
c58ac5ca 1495 mgp->link_changes++;
0da34b6d
BG		 1496 }
1497 }
1498 if (mgp->rdma_tags_available !=
b53bef84 1499 ntohl(stats->rdma_tags_available)) {
0da34b6d 1500 mgp->rdma_tags_available =
b53bef84 1501 ntohl(stats->rdma_tags_available);
0da34b6d
BG		 1502 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1503 "%d tags left\n", mgp->dev->name,
1504 mgp->rdma_tags_available);
1505 }
1506 mgp->down_cnt += stats->link_down;
1507 if (stats->link_down)
1508 wake_up(&mgp->down_wq);
1509 }
1510}
1511
bea3348e 1512static int myri10ge_poll(struct napi_struct *napi, int budget)
0da34b6d 1513{
b53bef84
BG		 1514 struct myri10ge_slice_state *ss =
1515 container_of(napi, struct myri10ge_slice_state, napi);
bea3348e 1516 int work_done;
0da34b6d 1517
5dd2d332 1518#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1519 if (ss->mgp->dca_enabled)
1520 myri10ge_update_dca(ss);
1521#endif
1522
0da34b6d 1523 /* process as many rx events as NAPI will allow */
b53bef84 1524 work_done = myri10ge_clean_rx_done(ss, budget);
0da34b6d 1525
4ec24119 1526 if (work_done < budget) {
288379f0 1527 napi_complete(napi);
b53bef84 1528 put_be32(htonl(3), ss->irq_claim);
0da34b6d 1529 }
bea3348e 1530 return work_done;
0da34b6d
BG		 1531}
1532
7d12e780 1533static irqreturn_t myri10ge_intr(int irq, void *arg)
0da34b6d 1534{
b53bef84
BG		 1535 struct myri10ge_slice_state *ss = arg;
1536 struct myri10ge_priv *mgp = ss->mgp;
1537 struct mcp_irq_data *stats = ss->fw_stats;
1538 struct myri10ge_tx_buf *tx = &ss->tx;
0da34b6d
BG		 1539 u32 send_done_count;
1540 int i;
1541
236bb5e6
BG		 1542 /* an interrupt on a non-zero receive-only slice is implicitly
1543 * valid since MSI-X irqs are not shared */
1544 if ((mgp->dev->real_num_tx_queues == 1) && (ss != mgp->ss)) {
288379f0 1545 napi_schedule(&ss->napi);
0dcffac1
BG		 1546 return (IRQ_HANDLED);
1547 }
1548
0da34b6d
BG		 1549 /* make sure it is our IRQ, and that the DMA has finished */
1550 if (unlikely(!stats->valid))
1551 return (IRQ_NONE);
1552
1553 /* low bit indicates receives are present, so schedule
1554 * napi poll handler */
1555 if (stats->valid & 1)
288379f0 1556 napi_schedule(&ss->napi);
0da34b6d 1557
0dcffac1 1558 if (!mgp->msi_enabled && !mgp->msix_enabled) {
40f6cff5 1559 put_be32(0, mgp->irq_deassert);
0da34b6d
BG		 1560 if (!myri10ge_deassert_wait)
1561 stats->valid = 0;
1562 mb();
1563 } else
1564 stats->valid = 0;
1565
1566 /* Wait for IRQ line to go low, if using INTx */
1567 i = 0;
1568 while (1) {
1569 i++;
1570 /* check for transmit completes and receives */
1571 send_done_count = ntohl(stats->send_done_count);
1572 if (send_done_count != tx->pkt_done)
b53bef84 1573 myri10ge_tx_done(ss, (int)send_done_count);
0da34b6d
BG		 1574 if (unlikely(i > myri10ge_max_irq_loops)) {
1575 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1576 mgp->dev->name);
1577 stats->valid = 0;
1578 schedule_work(&mgp->watchdog_work);
1579 }
1580 if (likely(stats->valid == 0))
1581 break;
1582 cpu_relax();
1583 barrier();
1584 }
1585
236bb5e6
BG		 1586 /* Only slice 0 updates stats */
1587 if (ss == mgp->ss)
1588 myri10ge_check_statblock(mgp);
0da34b6d 1589
b53bef84 1590 put_be32(htonl(3), ss->irq_claim + 1);
0da34b6d
BG		 1591 return (IRQ_HANDLED);
1592}
1593
1594static int
1595myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1596{
c0bf8801
BG		 1597 struct myri10ge_priv *mgp = netdev_priv(netdev);
1598 char *ptr;
1599 int i;
1600
0da34b6d
BG		 1601 cmd->autoneg = AUTONEG_DISABLE;
1602 cmd->speed = SPEED_10000;
1603 cmd->duplex = DUPLEX_FULL;
c0bf8801
BG		 1604
1605 /*
1606 * parse the product code to deterimine the interface type
1607 * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1608 * after the 3rd dash in the driver's cached copy of the
1609 * EEPROM's product code string.
1610 */
1611 ptr = mgp->product_code_string;
1612 if (ptr == NULL) {
1613 printk(KERN_ERR "myri10ge: %s: Missing product code\n",
99f5f87e 1614 netdev->name);
c0bf8801
BG		 1615 return 0;
1616 }
1617 for (i = 0; i < 3; i++, ptr++) {
1618 ptr = strchr(ptr, '-');
1619 if (ptr == NULL) {
1620 printk(KERN_ERR "myri10ge: %s: Invalid product "
1621 "code %s\n", netdev->name,
1622 mgp->product_code_string);
1623 return 0;
1624 }
1625 }
1626 if (*ptr == 'R' || *ptr == 'Q') {
1627 /* We've found either an XFP or quad ribbon fiber */
1628 cmd->port = PORT_FIBRE;
1629 }
0da34b6d
BG		 1630 return 0;
1631}
1632
1633static void
1634myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1635{
1636 struct myri10ge_priv *mgp = netdev_priv(netdev);
1637
1638 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1639 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1640 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1641 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1642}
1643
1644static int
1645myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1646{
1647 struct myri10ge_priv *mgp = netdev_priv(netdev);
99f5f87e 1648
0da34b6d
BG		 1649 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1650 return 0;
1651}
1652
1653static int
1654myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1655{
1656 struct myri10ge_priv *mgp = netdev_priv(netdev);
1657
1658 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
40f6cff5 1659 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 1660 return 0;
1661}
1662
1663static void
1664myri10ge_get_pauseparam(struct net_device *netdev,
1665 struct ethtool_pauseparam *pause)
1666{
1667 struct myri10ge_priv *mgp = netdev_priv(netdev);
1668
1669 pause->autoneg = 0;
1670 pause->rx_pause = mgp->pause;
1671 pause->tx_pause = mgp->pause;
1672}
1673
1674static int
1675myri10ge_set_pauseparam(struct net_device *netdev,
1676 struct ethtool_pauseparam *pause)
1677{
1678 struct myri10ge_priv *mgp = netdev_priv(netdev);
1679
1680 if (pause->tx_pause != mgp->pause)
1681 return myri10ge_change_pause(mgp, pause->tx_pause);
1682 if (pause->rx_pause != mgp->pause)
1683 return myri10ge_change_pause(mgp, pause->tx_pause);
1684 if (pause->autoneg != 0)
1685 return -EINVAL;
1686 return 0;
1687}
1688
1689static void
1690myri10ge_get_ringparam(struct net_device *netdev,
1691 struct ethtool_ringparam *ring)
1692{
1693 struct myri10ge_priv *mgp = netdev_priv(netdev);
1694
0dcffac1
BG		 1695 ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1;
1696 ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1;
0da34b6d 1697 ring->rx_jumbo_max_pending = 0;
6498be3f 1698 ring->tx_max_pending = mgp->ss[0].tx.mask + 1;
0da34b6d
BG		 1699 ring->rx_mini_pending = ring->rx_mini_max_pending;
1700 ring->rx_pending = ring->rx_max_pending;
1701 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1702 ring->tx_pending = ring->tx_max_pending;
1703}
1704
1705static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1706{
1707 struct myri10ge_priv *mgp = netdev_priv(netdev);
99f5f87e 1708
0da34b6d
BG		 1709 if (mgp->csum_flag)
1710 return 1;
1711 else
1712 return 0;
1713}
1714
1715static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1716{
1717 struct myri10ge_priv *mgp = netdev_priv(netdev);
3a0c7d2d 1718 int err = 0;
99f5f87e 1719
0da34b6d
BG		 1720 if (csum_enabled)
1721 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3a0c7d2d
BG		 1722 else {
1723 u32 flags = ethtool_op_get_flags(netdev);
1724 err = ethtool_op_set_flags(netdev, (flags & ~ETH_FLAG_LRO));
0da34b6d 1725 mgp->csum_flag = 0;
3a0c7d2d
BG		 1726
1727 }
1728 return err;
0da34b6d
BG		 1729}
1730
4f93fde0
BG		 1731static int myri10ge_set_tso(struct net_device *netdev, u32 tso_enabled)
1732{
1733 struct myri10ge_priv *mgp = netdev_priv(netdev);
1734 unsigned long flags = mgp->features & (NETIF_F_TSO6 | NETIF_F_TSO);
1735
1736 if (tso_enabled)
1737 netdev->features |= flags;
1738 else
1739 netdev->features &= ~flags;
1740 return 0;
1741}
1742
b53bef84 1743static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
0da34b6d
BG		 1744 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1745 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1746 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1747 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1748 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1749 "tx_heartbeat_errors", "tx_window_errors",
1750 /* device-specific stats */
0dcffac1 1751 "tx_boundary", "WC", "irq", "MSI", "MSIX",
0da34b6d 1752 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
b53bef84 1753 "serial_number", "watchdog_resets",
5dd2d332 1754#ifdef CONFIG_MYRI10GE_DCA
9a6b3b54 1755 "dca_capable_firmware", "dca_device_present",
981813d8 1756#endif
c58ac5ca 1757 "link_changes", "link_up", "dropped_link_overflow",
cee505db
BG		 1758 "dropped_link_error_or_filtered",
1759 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1760 "dropped_unicast_filtered", "dropped_multicast_filtered",
0da34b6d 1761 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
b53bef84
BG		 1762 "dropped_no_big_buffer"
1763};
1764
1765static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1766 "----------- slice ---------",
1767 "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1768 "rx_small_cnt", "rx_big_cnt",
1769 "wake_queue", "stop_queue", "tx_linearized", "LRO aggregated",
1770 "LRO flushed",
1e6e9342 1771 "LRO avg aggr", "LRO no_desc"
0da34b6d
BG		 1772};
1773
1774#define MYRI10GE_NET_STATS_LEN 21
b53bef84
BG		 1775#define MYRI10GE_MAIN_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_main_stats)
1776#define MYRI10GE_SLICE_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_slice_stats)
0da34b6d
BG		 1777
1778static void
1779myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1780{
0dcffac1
BG		 1781 struct myri10ge_priv *mgp = netdev_priv(netdev);
1782 int i;
1783
0da34b6d
BG		 1784 switch (stringset) {
1785 case ETH_SS_STATS:
b53bef84
BG		 1786 memcpy(data, *myri10ge_gstrings_main_stats,
1787 sizeof(myri10ge_gstrings_main_stats));
1788 data += sizeof(myri10ge_gstrings_main_stats);
0dcffac1
BG		 1789 for (i = 0; i < mgp->num_slices; i++) {
1790 memcpy(data, *myri10ge_gstrings_slice_stats,
1791 sizeof(myri10ge_gstrings_slice_stats));
1792 data += sizeof(myri10ge_gstrings_slice_stats);
1793 }
0da34b6d
BG		 1794 break;
1795 }
1796}
1797
b9f2c044 1798static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
0da34b6d 1799{
0dcffac1
BG		 1800 struct myri10ge_priv *mgp = netdev_priv(netdev);
1801
b9f2c044
JG		 1802 switch (sset) {
1803 case ETH_SS_STATS:
0dcffac1
BG		 1804 return MYRI10GE_MAIN_STATS_LEN +
1805 mgp->num_slices * MYRI10GE_SLICE_STATS_LEN;
b9f2c044
JG		 1806 default:
1807 return -EOPNOTSUPP;
1808 }
0da34b6d
BG		 1809}
1810
1811static void
1812myri10ge_get_ethtool_stats(struct net_device *netdev,
1813 struct ethtool_stats *stats, u64 * data)
1814{
1815 struct myri10ge_priv *mgp = netdev_priv(netdev);
b53bef84 1816 struct myri10ge_slice_state *ss;
0dcffac1 1817 int slice;
0da34b6d
BG		 1818 int i;
1819
59081825
BG		 1820 /* force stats update */
1821 (void)myri10ge_get_stats(netdev);
0da34b6d
BG		 1822 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1823 data[i] = ((unsigned long *)&mgp->stats)[i];
1824
b53bef84 1825 data[i++] = (unsigned int)mgp->tx_boundary;
276e26c3 1826 data[i++] = (unsigned int)mgp->wc_enabled;
2c1a1088
BG		 1827 data[i++] = (unsigned int)mgp->pdev->irq;
1828 data[i++] = (unsigned int)mgp->msi_enabled;
0dcffac1 1829 data[i++] = (unsigned int)mgp->msix_enabled;
0da34b6d
BG		 1830 data[i++] = (unsigned int)mgp->read_dma;
1831 data[i++] = (unsigned int)mgp->write_dma;
1832 data[i++] = (unsigned int)mgp->read_write_dma;
1833 data[i++] = (unsigned int)mgp->serial_number;
0da34b6d 1834 data[i++] = (unsigned int)mgp->watchdog_resets;
5dd2d332 1835#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1836 data[i++] = (unsigned int)(mgp->ss[0].dca_tag != NULL);
1837 data[i++] = (unsigned int)(mgp->dca_enabled);
1838#endif
c58ac5ca 1839 data[i++] = (unsigned int)mgp->link_changes;
b53bef84
BG		 1840
1841 /* firmware stats are useful only in the first slice */
0dcffac1 1842 ss = &mgp->ss[0];
b53bef84
BG		 1843 data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1844 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
cee505db 1845 data[i++] =
b53bef84
BG		 1846 (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered);
1847 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause);
1848 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy);
1849 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32);
1850 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered);
85a7ea1b 1851 data[i++] =
b53bef84
BG		 1852 (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered);
1853 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt);
1854 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun);
1855 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
1856 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
1857
0dcffac1
BG		 1858 for (slice = 0; slice < mgp->num_slices; slice++) {
1859 ss = &mgp->ss[slice];
1860 data[i++] = slice;
1861 data[i++] = (unsigned int)ss->tx.pkt_start;
1862 data[i++] = (unsigned int)ss->tx.pkt_done;
1863 data[i++] = (unsigned int)ss->tx.req;
1864 data[i++] = (unsigned int)ss->tx.done;
1865 data[i++] = (unsigned int)ss->rx_small.cnt;
1866 data[i++] = (unsigned int)ss->rx_big.cnt;
1867 data[i++] = (unsigned int)ss->tx.wake_queue;
1868 data[i++] = (unsigned int)ss->tx.stop_queue;
1869 data[i++] = (unsigned int)ss->tx.linearized;
1870 data[i++] = ss->rx_done.lro_mgr.stats.aggregated;
1871 data[i++] = ss->rx_done.lro_mgr.stats.flushed;
1872 if (ss->rx_done.lro_mgr.stats.flushed)
1873 data[i++] = ss->rx_done.lro_mgr.stats.aggregated /
1874 ss->rx_done.lro_mgr.stats.flushed;
1875 else
1876 data[i++] = 0;
1877 data[i++] = ss->rx_done.lro_mgr.stats.no_desc;
1878 }
0da34b6d
BG		 1879}
1880
c58ac5ca
BG		 1881static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1882{
1883 struct myri10ge_priv *mgp = netdev_priv(netdev);
1884 mgp->msg_enable = value;
1885}
1886
1887static u32 myri10ge_get_msglevel(struct net_device *netdev)
1888{
1889 struct myri10ge_priv *mgp = netdev_priv(netdev);
1890 return mgp->msg_enable;
1891}
1892
7282d491 1893static const struct ethtool_ops myri10ge_ethtool_ops = {
0da34b6d
BG		 1894 .get_settings = myri10ge_get_settings,
1895 .get_drvinfo = myri10ge_get_drvinfo,
1896 .get_coalesce = myri10ge_get_coalesce,
1897 .set_coalesce = myri10ge_set_coalesce,
1898 .get_pauseparam = myri10ge_get_pauseparam,
1899 .set_pauseparam = myri10ge_set_pauseparam,
1900 .get_ringparam = myri10ge_get_ringparam,
1901 .get_rx_csum = myri10ge_get_rx_csum,
1902 .set_rx_csum = myri10ge_set_rx_csum,
b10c0668 1903 .set_tx_csum = ethtool_op_set_tx_hw_csum,
0da34b6d 1904 .set_sg = ethtool_op_set_sg,
4f93fde0 1905 .set_tso = myri10ge_set_tso,
6ffdd071 1906 .get_link = ethtool_op_get_link,
0da34b6d 1907 .get_strings = myri10ge_get_strings,
b9f2c044 1908 .get_sset_count = myri10ge_get_sset_count,
c58ac5ca
BG		 1909 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1910 .set_msglevel = myri10ge_set_msglevel,
3a0c7d2d
BG		 1911 .get_msglevel = myri10ge_get_msglevel,
1912 .get_flags = ethtool_op_get_flags,
1913 .set_flags = ethtool_op_set_flags
0da34b6d
BG		 1914};
1915
b53bef84 1916static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
0da34b6d 1917{
b53bef84 1918 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d 1919 struct myri10ge_cmd cmd;
b53bef84 1920 struct net_device *dev = mgp->dev;
0da34b6d
BG		 1921 int tx_ring_size, rx_ring_size;
1922 int tx_ring_entries, rx_ring_entries;
0dcffac1 1923 int i, slice, status;
0da34b6d
BG		 1924 size_t bytes;
1925
0da34b6d 1926 /* get ring sizes */
0dcffac1
BG		 1927 slice = ss - mgp->ss;
1928 cmd.data0 = slice;
0da34b6d
BG		 1929 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1930 tx_ring_size = cmd.data0;
0dcffac1 1931 cmd.data0 = slice;
0da34b6d 1932 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
355c7265
BG		 1933 if (status != 0)
1934 return status;
0da34b6d
BG		 1935 rx_ring_size = cmd.data0;
1936
1937 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1938 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
b53bef84
BG		 1939 ss->tx.mask = tx_ring_entries - 1;
1940 ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
0da34b6d 1941
355c7265
BG		 1942 status = -ENOMEM;
1943
0da34b6d
BG		 1944 /* allocate the host shadow rings */
1945
1946 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
b53bef84
BG		 1947 * sizeof(*ss->tx.req_list);
1948 ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1949 if (ss->tx.req_bytes == NULL)
0da34b6d
BG		 1950 goto abort_with_nothing;
1951
1952 /* ensure req_list entries are aligned to 8 bytes */
b53bef84
BG		 1953 ss->tx.req_list = (struct mcp_kreq_ether_send *)
1954 ALIGN((unsigned long)ss->tx.req_bytes, 8);
236bb5e6 1955 ss->tx.queue_active = 0;
0da34b6d 1956
b53bef84
BG		 1957 bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow);
1958 ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1959 if (ss->rx_small.shadow == NULL)
0da34b6d
BG		 1960 goto abort_with_tx_req_bytes;
1961
b53bef84
BG		 1962 bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow);
1963 ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1964 if (ss->rx_big.shadow == NULL)
0da34b6d
BG		 1965 goto abort_with_rx_small_shadow;
1966
1967 /* allocate the host info rings */
1968
b53bef84
BG		 1969 bytes = tx_ring_entries * sizeof(*ss->tx.info);
1970 ss->tx.info = kzalloc(bytes, GFP_KERNEL);
1971 if (ss->tx.info == NULL)
0da34b6d
BG		 1972 goto abort_with_rx_big_shadow;
1973
b53bef84
BG		 1974 bytes = rx_ring_entries * sizeof(*ss->rx_small.info);
1975 ss->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1976 if (ss->rx_small.info == NULL)
0da34b6d
BG		 1977 goto abort_with_tx_info;
1978
b53bef84
BG		 1979 bytes = rx_ring_entries * sizeof(*ss->rx_big.info);
1980 ss->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1981 if (ss->rx_big.info == NULL)
0da34b6d
BG		 1982 goto abort_with_rx_small_info;
1983
1984 /* Fill the receive rings */
b53bef84
BG		 1985 ss->rx_big.cnt = 0;
1986 ss->rx_small.cnt = 0;
1987 ss->rx_big.fill_cnt = 0;
1988 ss->rx_small.fill_cnt = 0;
1989 ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1990 ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1991 ss->rx_small.watchdog_needed = 0;
1992 ss->rx_big.watchdog_needed = 0;
1993 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
c7dab99b 1994 mgp->small_bytes + MXGEFW_PAD, 0);
0da34b6d 1995
b53bef84 1996 if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
0dcffac1
BG		 1997 printk(KERN_ERR
1998 "myri10ge: %s:slice-%d: alloced only %d small bufs\n",
1999 dev->name, slice, ss->rx_small.fill_cnt);
c7dab99b 2000 goto abort_with_rx_small_ring;
0da34b6d
BG		 2001 }
2002
b53bef84
BG		 2003 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
2004 if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
0dcffac1
BG		 2005 printk(KERN_ERR
2006 "myri10ge: %s:slice-%d: alloced only %d big bufs\n",
2007 dev->name, slice, ss->rx_big.fill_cnt);
c7dab99b 2008 goto abort_with_rx_big_ring;
0da34b6d
BG		 2009 }
2010
2011 return 0;
2012
2013abort_with_rx_big_ring:
b53bef84
BG		 2014 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2015 int idx = i & ss->rx_big.mask;
2016 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 2017 mgp->big_bytes);
b53bef84 2018 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 2019 }
2020
2021abort_with_rx_small_ring:
b53bef84
BG		 2022 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2023 int idx = i & ss->rx_small.mask;
2024 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 2025 mgp->small_bytes + MXGEFW_PAD);
b53bef84 2026 put_page(ss->rx_small.info[idx].page);
0da34b6d 2027 }
c7dab99b 2028
b53bef84 2029 kfree(ss->rx_big.info);
0da34b6d
BG		 2030
2031abort_with_rx_small_info:
b53bef84 2032 kfree(ss->rx_small.info);
0da34b6d
BG		 2033
2034abort_with_tx_info:
b53bef84 2035 kfree(ss->tx.info);
0da34b6d
BG		 2036
2037abort_with_rx_big_shadow:
b53bef84 2038 kfree(ss->rx_big.shadow);
0da34b6d
BG		 2039
2040abort_with_rx_small_shadow:
b53bef84 2041 kfree(ss->rx_small.shadow);
0da34b6d
BG		 2042
2043abort_with_tx_req_bytes:
b53bef84
BG		 2044 kfree(ss->tx.req_bytes);
2045 ss->tx.req_bytes = NULL;
2046 ss->tx.req_list = NULL;
0da34b6d
BG		 2047
2048abort_with_nothing:
2049 return status;
2050}
2051
b53bef84 2052static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
0da34b6d 2053{
b53bef84 2054 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d
BG		 2055 struct sk_buff *skb;
2056 struct myri10ge_tx_buf *tx;
2057 int i, len, idx;
2058
0dcffac1
BG		 2059 /* If not allocated, skip it */
2060 if (ss->tx.req_list == NULL)
2061 return;
2062
b53bef84
BG		 2063 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2064 idx = i & ss->rx_big.mask;
2065 if (i == ss->rx_big.fill_cnt - 1)
2066 ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
2067 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 2068 mgp->big_bytes);
b53bef84 2069 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 2070 }
2071
b53bef84
BG		 2072 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2073 idx = i & ss->rx_small.mask;
2074 if (i == ss->rx_small.fill_cnt - 1)
2075 ss->rx_small.info[idx].page_offset =
c7dab99b 2076 MYRI10GE_ALLOC_SIZE;
b53bef84 2077 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 2078 mgp->small_bytes + MXGEFW_PAD);
b53bef84 2079 put_page(ss->rx_small.info[idx].page);
c7dab99b 2080 }
b53bef84 2081 tx = &ss->tx;
0da34b6d
BG		 2082 while (tx->done != tx->req) {
2083 idx = tx->done & tx->mask;
2084 skb = tx->info[idx].skb;
2085
2086 /* Mark as free */
2087 tx->info[idx].skb = NULL;
2088 tx->done++;
2089 len = pci_unmap_len(&tx->info[idx], len);
2090 pci_unmap_len_set(&tx->info[idx], len, 0);
2091 if (skb) {
b53bef84 2092 ss->stats.tx_dropped++;
0da34b6d
BG		 2093 dev_kfree_skb_any(skb);
2094 if (len)
2095 pci_unmap_single(mgp->pdev,
2096 pci_unmap_addr(&tx->info[idx],
2097 bus), len,
2098 PCI_DMA_TODEVICE);
2099 } else {
2100 if (len)
2101 pci_unmap_page(mgp->pdev,
2102 pci_unmap_addr(&tx->info[idx],
2103 bus), len,
2104 PCI_DMA_TODEVICE);
2105 }
2106 }
b53bef84 2107 kfree(ss->rx_big.info);
0da34b6d 2108
b53bef84 2109 kfree(ss->rx_small.info);
0da34b6d 2110
b53bef84 2111 kfree(ss->tx.info);
0da34b6d 2112
b53bef84 2113 kfree(ss->rx_big.shadow);
0da34b6d 2114
b53bef84 2115 kfree(ss->rx_small.shadow);
0da34b6d 2116
b53bef84
BG		 2117 kfree(ss->tx.req_bytes);
2118 ss->tx.req_bytes = NULL;
2119 ss->tx.req_list = NULL;
0da34b6d
BG		 2120}
2121
df30a740
BG		 2122static int myri10ge_request_irq(struct myri10ge_priv *mgp)
2123{
2124 struct pci_dev *pdev = mgp->pdev;
0dcffac1
BG		 2125 struct myri10ge_slice_state *ss;
2126 struct net_device *netdev = mgp->dev;
2127 int i;
df30a740
BG		 2128 int status;
2129
0dcffac1
BG		 2130 mgp->msi_enabled = 0;
2131 mgp->msix_enabled = 0;
2132 status = 0;
df30a740 2133 if (myri10ge_msi) {
0dcffac1
BG		 2134 if (mgp->num_slices > 1) {
2135 status =
2136 pci_enable_msix(pdev, mgp->msix_vectors,
2137 mgp->num_slices);
2138 if (status == 0) {
2139 mgp->msix_enabled = 1;
2140 } else {
2141 dev_err(&pdev->dev,
2142 "Error %d setting up MSI-X\n", status);
2143 return status;
2144 }
2145 }
2146 if (mgp->msix_enabled == 0) {
2147 status = pci_enable_msi(pdev);
2148 if (status != 0) {
2149 dev_err(&pdev->dev,
2150 "Error %d setting up MSI; falling back to xPIC\n",
2151 status);
2152 } else {
2153 mgp->msi_enabled = 1;
2154 }
2155 }
df30a740 2156 }
0dcffac1
BG		 2157 if (mgp->msix_enabled) {
2158 for (i = 0; i < mgp->num_slices; i++) {
2159 ss = &mgp->ss[i];
2160 snprintf(ss->irq_desc, sizeof(ss->irq_desc),
2161 "%s:slice-%d", netdev->name, i);
2162 status = request_irq(mgp->msix_vectors[i].vector,
2163 myri10ge_intr, 0, ss->irq_desc,
2164 ss);
2165 if (status != 0) {
2166 dev_err(&pdev->dev,
2167 "slice %d failed to allocate IRQ\n", i);
2168 i--;
2169 while (i >= 0) {
2170 free_irq(mgp->msix_vectors[i].vector,
2171 &mgp->ss[i]);
2172 i--;
2173 }
2174 pci_disable_msix(pdev);
2175 return status;
2176 }
2177 }
2178 } else {
2179 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2180 mgp->dev->name, &mgp->ss[0]);
2181 if (status != 0) {
2182 dev_err(&pdev->dev, "failed to allocate IRQ\n");
2183 if (mgp->msi_enabled)
2184 pci_disable_msi(pdev);
2185 }
df30a740
BG		 2186 }
2187 return status;
2188}
2189
2190static void myri10ge_free_irq(struct myri10ge_priv *mgp)
2191{
2192 struct pci_dev *pdev = mgp->pdev;
0dcffac1 2193 int i;
df30a740 2194
0dcffac1
BG		 2195 if (mgp->msix_enabled) {
2196 for (i = 0; i < mgp->num_slices; i++)
2197 free_irq(mgp->msix_vectors[i].vector, &mgp->ss[i]);
2198 } else {
2199 free_irq(pdev->irq, &mgp->ss[0]);
2200 }
df30a740
BG		 2201 if (mgp->msi_enabled)
2202 pci_disable_msi(pdev);
0dcffac1
BG		 2203 if (mgp->msix_enabled)
2204 pci_disable_msix(pdev);
df30a740
BG		 2205}
2206
1e6e9342
AG		 2207static int
2208myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
2209 void **ip_hdr, void **tcpudp_hdr,
2210 u64 * hdr_flags, void *priv)
2211{
2212 struct ethhdr *eh;
2213 struct vlan_ethhdr *veh;
2214 struct iphdr *iph;
2215 u8 *va = page_address(frag->page) + frag->page_offset;
2216 unsigned long ll_hlen;
66341fff
AV		 2217 /* passed opaque through lro_receive_frags() */
2218 __wsum csum = (__force __wsum) (unsigned long)priv;
1e6e9342
AG		 2219
2220 /* find the mac header, aborting if not IPv4 */
2221
2222 eh = (struct ethhdr *)va;
2223 *mac_hdr = eh;
2224 ll_hlen = ETH_HLEN;
2225 if (eh->h_proto != htons(ETH_P_IP)) {
2226 if (eh->h_proto == htons(ETH_P_8021Q)) {
2227 veh = (struct vlan_ethhdr *)va;
2228 if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
2229 return -1;
2230
2231 ll_hlen += VLAN_HLEN;
2232
2233 /*
2234 * HW checksum starts ETH_HLEN bytes into
2235 * frame, so we must subtract off the VLAN
2236 * header's checksum before csum can be used
2237 */
2238 csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
2239 VLAN_HLEN, 0));
2240 } else {
2241 return -1;
2242 }
2243 }
2244 *hdr_flags = LRO_IPV4;
2245
2246 iph = (struct iphdr *)(va + ll_hlen);
2247 *ip_hdr = iph;
2248 if (iph->protocol != IPPROTO_TCP)
2249 return -1;
bcb09dc2
BG		 2250 if (iph->frag_off & htons(IP_MF | IP_OFFSET))
2251 return -1;
1e6e9342
AG		 2252 *hdr_flags |= LRO_TCP;
2253 *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
2254
2255 /* verify the IP checksum */
2256 if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
2257 return -1;
2258
2259 /* verify the checksum */
2260 if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
2261 ntohs(iph->tot_len) - (iph->ihl << 2),
2262 IPPROTO_TCP, csum)))
2263 return -1;
2264
2265 return 0;
2266}
2267
77929732
BG		 2268static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
2269{
2270 struct myri10ge_cmd cmd;
2271 struct myri10ge_slice_state *ss;
2272 int status;
2273
2274 ss = &mgp->ss[slice];
236bb5e6
BG		 2275 status = 0;
2276 if (slice == 0 || (mgp->dev->real_num_tx_queues > 1)) {
2277 cmd.data0 = slice;
2278 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET,
2279 &cmd, 0);
2280 ss->tx.lanai = (struct mcp_kreq_ether_send __iomem *)
2281 (mgp->sram + cmd.data0);
2282 }
77929732
BG		 2283 cmd.data0 = slice;
2284 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET,
2285 &cmd, 0);
2286 ss->rx_small.lanai = (struct mcp_kreq_ether_recv __iomem *)
2287 (mgp->sram + cmd.data0);
2288
2289 cmd.data0 = slice;
2290 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
2291 ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *)
2292 (mgp->sram + cmd.data0);
2293
236bb5e6
BG		 2294 ss->tx.send_go = (__iomem __be32 *)
2295 (mgp->sram + MXGEFW_ETH_SEND_GO + 64 * slice);
2296 ss->tx.send_stop = (__iomem __be32 *)
2297 (mgp->sram + MXGEFW_ETH_SEND_STOP + 64 * slice);
77929732
BG		 2298 return status;
2299
2300}
2301
2302static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice)
2303{
2304 struct myri10ge_cmd cmd;
2305 struct myri10ge_slice_state *ss;
2306 int status;
2307
2308 ss = &mgp->ss[slice];
2309 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->fw_stats_bus);
2310 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->fw_stats_bus);
236bb5e6 2311 cmd.data2 = sizeof(struct mcp_irq_data) | (slice << 16);
77929732
BG		 2312 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2313 if (status == -ENOSYS) {
2314 dma_addr_t bus = ss->fw_stats_bus;
2315 if (slice != 0)
2316 return -EINVAL;
2317 bus += offsetof(struct mcp_irq_data, send_done_count);
2318 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2319 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2320 status = myri10ge_send_cmd(mgp,
2321 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2322 &cmd, 0);
2323 /* Firmware cannot support multicast without STATS_DMA_V2 */
2324 mgp->fw_multicast_support = 0;
2325 } else {
2326 mgp->fw_multicast_support = 1;
2327 }
2328 return 0;
2329}
77929732 2330
0da34b6d
BG		 2331static int myri10ge_open(struct net_device *dev)
2332{
0dcffac1 2333 struct myri10ge_slice_state *ss;
b53bef84 2334 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d 2335 struct myri10ge_cmd cmd;
0dcffac1
BG		 2336 int i, status, big_pow2, slice;
2337 u8 *itable;
1e6e9342 2338 struct net_lro_mgr *lro_mgr;
0da34b6d 2339
0da34b6d
BG		 2340 if (mgp->running != MYRI10GE_ETH_STOPPED)
2341 return -EBUSY;
2342
2343 mgp->running = MYRI10GE_ETH_STARTING;
2344 status = myri10ge_reset(mgp);
2345 if (status != 0) {
2346 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
df30a740 2347 goto abort_with_nothing;
0da34b6d
BG		 2348 }
2349
0dcffac1
BG		 2350 if (mgp->num_slices > 1) {
2351 cmd.data0 = mgp->num_slices;
236bb5e6
BG		 2352 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
2353 if (mgp->dev->real_num_tx_queues > 1)
2354 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
0dcffac1
BG		 2355 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
2356 &cmd, 0);
2357 if (status != 0) {
2358 printk(KERN_ERR
2359 "myri10ge: %s: failed to set number of slices\n",
2360 dev->name);
2361 goto abort_with_nothing;
2362 }
2363 /* setup the indirection table */
2364 cmd.data0 = mgp->num_slices;
2365 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
2366 &cmd, 0);
2367
2368 status |= myri10ge_send_cmd(mgp,
2369 MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
2370 &cmd, 0);
2371 if (status != 0) {
2372 printk(KERN_ERR
2373 "myri10ge: %s: failed to setup rss tables\n",
2374 dev->name);
236bb5e6 2375 goto abort_with_nothing;
0dcffac1
BG		 2376 }
2377
2378 /* just enable an identity mapping */
2379 itable = mgp->sram + cmd.data0;
2380 for (i = 0; i < mgp->num_slices; i++)
2381 __raw_writeb(i, &itable[i]);
2382
2383 cmd.data0 = 1;
2384 cmd.data1 = myri10ge_rss_hash;
2385 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE,
2386 &cmd, 0);
2387 if (status != 0) {
2388 printk(KERN_ERR
2389 "myri10ge: %s: failed to enable slices\n",
2390 dev->name);
2391 goto abort_with_nothing;
2392 }
2393 }
2394
df30a740
BG		 2395 status = myri10ge_request_irq(mgp);
2396 if (status != 0)
2397 goto abort_with_nothing;
2398
0da34b6d
BG		 2399 /* decide what small buffer size to use. For good TCP rx
2400 * performance, it is important to not receive 1514 byte
2401 * frames into jumbo buffers, as it confuses the socket buffer
2402 * accounting code, leading to drops and erratic performance.
2403 */
2404
2405 if (dev->mtu <= ETH_DATA_LEN)
c7dab99b
BG		 2406 /* enough for a TCP header */
2407 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
2408 ? (128 - MXGEFW_PAD)
2409 : (SMP_CACHE_BYTES - MXGEFW_PAD);
0da34b6d 2410 else
de3c4507
BG		 2411 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
2412 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
0da34b6d
BG		 2413
2414 /* Override the small buffer size? */
2415 if (myri10ge_small_bytes > 0)
2416 mgp->small_bytes = myri10ge_small_bytes;
2417
0da34b6d
BG		 2418 /* Firmware needs the big buff size as a power of 2. Lie and
2419 * tell him the buffer is larger, because we only use 1
2420 * buffer/pkt, and the mtu will prevent overruns.
2421 */
13348bee 2422 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b 2423 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
199126a2 2424 while (!is_power_of_2(big_pow2))
c7dab99b 2425 big_pow2++;
13348bee 2426 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 2427 } else {
2428 big_pow2 = MYRI10GE_ALLOC_SIZE;
2429 mgp->big_bytes = big_pow2;
2430 }
2431
0dcffac1
BG		 2432 /* setup the per-slice data structures */
2433 for (slice = 0; slice < mgp->num_slices; slice++) {
2434 ss = &mgp->ss[slice];
2435
2436 status = myri10ge_get_txrx(mgp, slice);
2437 if (status != 0) {
2438 printk(KERN_ERR
2439 "myri10ge: %s: failed to get ring sizes or locations\n",
2440 dev->name);
2441 goto abort_with_rings;
2442 }
2443 status = myri10ge_allocate_rings(ss);
2444 if (status != 0)
2445 goto abort_with_rings;
236bb5e6
BG		 2446
2447 /* only firmware which supports multiple TX queues
2448 * supports setting up the tx stats on non-zero
2449 * slices */
2450 if (slice == 0 || mgp->dev->real_num_tx_queues > 1)
0dcffac1
BG		 2451 status = myri10ge_set_stats(mgp, slice);
2452 if (status) {
2453 printk(KERN_ERR
2454 "myri10ge: %s: Couldn't set stats DMA\n",
2455 dev->name);
2456 goto abort_with_rings;
2457 }
2458
2459 lro_mgr = &ss->rx_done.lro_mgr;
2460 lro_mgr->dev = dev;
2461 lro_mgr->features = LRO_F_NAPI;
2462 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
2463 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2464 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
2465 lro_mgr->lro_arr = ss->rx_done.lro_desc;
2466 lro_mgr->get_frag_header = myri10ge_get_frag_header;
2467 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
636d2f68 2468 lro_mgr->frag_align_pad = 2;
0dcffac1
BG		 2469 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2470 lro_mgr->max_aggr = MAX_SKB_FRAGS;
2471
2472 /* must happen prior to any irq */
2473 napi_enable(&(ss)->napi);
2474 }
0da34b6d
BG		 2475
2476 /* now give firmware buffers sizes, and MTU */
2477 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
2478 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2479 cmd.data0 = mgp->small_bytes;
2480 status |=
2481 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2482 cmd.data0 = big_pow2;
2483 status |=
2484 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2485 if (status) {
2486 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
2487 dev->name);
2488 goto abort_with_rings;
2489 }
2490
0dcffac1
BG		 2491 /*
2492 * Set Linux style TSO mode; this is needed only on newer
2493 * firmware versions. Older versions default to Linux
2494 * style TSO
2495 */
2496 cmd.data0 = 0;
2497 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd, 0);
2498 if (status && status != -ENOSYS) {
2499 printk(KERN_ERR "myri10ge: %s: Couldn't set TSO mode\n",
0da34b6d
BG		 2500 dev->name);
2501 goto abort_with_rings;
2502 }
2503
66341fff 2504 mgp->link_state = ~0U;
0da34b6d
BG		 2505 mgp->rdma_tags_available = 15;
2506
0da34b6d
BG		 2507 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2508 if (status) {
2509 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
2510 dev->name);
2511 goto abort_with_rings;
2512 }
2513
0da34b6d
BG		 2514 mgp->running = MYRI10GE_ETH_RUNNING;
2515 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2516 add_timer(&mgp->watchdog_timer);
236bb5e6
BG		 2517 netif_tx_wake_all_queues(dev);
2518
0da34b6d
BG		 2519 return 0;
2520
2521abort_with_rings:
051d36f3
BG		 2522 while (slice) {
2523 slice--;
2524 napi_disable(&mgp->ss[slice].napi);
2525 }
0dcffac1
BG		 2526 for (i = 0; i < mgp->num_slices; i++)
2527 myri10ge_free_rings(&mgp->ss[i]);
0da34b6d 2528
df30a740
BG		 2529 myri10ge_free_irq(mgp);
2530
0da34b6d
BG		 2531abort_with_nothing:
2532 mgp->running = MYRI10GE_ETH_STOPPED;
2533 return -ENOMEM;
2534}
2535
2536static int myri10ge_close(struct net_device *dev)
2537{
b53bef84 2538 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d
BG		 2539 struct myri10ge_cmd cmd;
2540 int status, old_down_cnt;
0dcffac1 2541 int i;
0da34b6d 2542
0da34b6d
BG		 2543 if (mgp->running != MYRI10GE_ETH_RUNNING)
2544 return 0;
2545
0dcffac1 2546 if (mgp->ss[0].tx.req_bytes == NULL)
0da34b6d
BG		 2547 return 0;
2548
2549 del_timer_sync(&mgp->watchdog_timer);
2550 mgp->running = MYRI10GE_ETH_STOPPING;
0dcffac1
BG		 2551 for (i = 0; i < mgp->num_slices; i++) {
2552 napi_disable(&mgp->ss[i].napi);
2553 }
0da34b6d 2554 netif_carrier_off(dev);
236bb5e6
BG		 2555
2556 netif_tx_stop_all_queues(dev);
d0234215
BG		 2557 if (mgp->rebooted == 0) {
2558 old_down_cnt = mgp->down_cnt;
2559 mb();
2560 status =
2561 myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2562 if (status)
2563 printk(KERN_ERR
2564 "myri10ge: %s: Couldn't bring down link\n",
2565 dev->name);
0da34b6d 2566
d0234215
BG		 2567 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt,
2568 HZ);
2569 if (old_down_cnt == mgp->down_cnt)
2570 printk(KERN_ERR "myri10ge: %s never got down irq\n",
2571 dev->name);
2572 }
0da34b6d 2573 netif_tx_disable(dev);
df30a740 2574 myri10ge_free_irq(mgp);
0dcffac1
BG		 2575 for (i = 0; i < mgp->num_slices; i++)
2576 myri10ge_free_rings(&mgp->ss[i]);
0da34b6d
BG		 2577
2578 mgp->running = MYRI10GE_ETH_STOPPED;
2579 return 0;
2580}
2581
2582/* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2583 * backwards one at a time and handle ring wraps */
2584
2585static inline void
2586myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2587 struct mcp_kreq_ether_send *src, int cnt)
2588{
2589 int idx, starting_slot;
2590 starting_slot = tx->req;
2591 while (cnt > 1) {
2592 cnt--;
2593 idx = (starting_slot + cnt) & tx->mask;
2594 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2595 mb();
2596 }
2597}
2598
2599/*
2600 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2601 * at most 32 bytes at a time, so as to avoid involving the software
2602 * pio handler in the nic. We re-write the first segment's flags
2603 * to mark them valid only after writing the entire chain.
2604 */
2605
2606static inline void
2607myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2608 int cnt)
2609{
2610 int idx, i;
2611 struct mcp_kreq_ether_send __iomem *dstp, *dst;
2612 struct mcp_kreq_ether_send *srcp;
2613 u8 last_flags;
2614
2615 idx = tx->req & tx->mask;
2616
2617 last_flags = src->flags;
2618 src->flags = 0;
2619 mb();
2620 dst = dstp = &tx->lanai[idx];
2621 srcp = src;
2622
2623 if ((idx + cnt) < tx->mask) {
2624 for (i = 0; i < (cnt - 1); i += 2) {
2625 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2626 mb(); /* force write every 32 bytes */
2627 srcp += 2;
2628 dstp += 2;
2629 }
2630 } else {
2631 /* submit all but the first request, and ensure
2632 * that it is submitted below */
2633 myri10ge_submit_req_backwards(tx, src, cnt);
2634 i = 0;
2635 }
2636 if (i < cnt) {
2637 /* submit the first request */
2638 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2639 mb(); /* barrier before setting valid flag */
2640 }
2641
2642 /* re-write the last 32-bits with the valid flags */
2643 src->flags = last_flags;
40f6cff5 2644 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
0da34b6d
BG		 2645 tx->req += cnt;
2646 mb();
2647}
2648
0da34b6d
BG		 2649/*
2650 * Transmit a packet. We need to split the packet so that a single
b53bef84 2651 * segment does not cross myri10ge->tx_boundary, so this makes segment
0da34b6d
BG		 2652 * counting tricky. So rather than try to count segments up front, we
2653 * just give up if there are too few segments to hold a reasonably
2654 * fragmented packet currently available. If we run
2655 * out of segments while preparing a packet for DMA, we just linearize
2656 * it and try again.
2657 */
2658
2659static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
2660{
2661 struct myri10ge_priv *mgp = netdev_priv(dev);
b53bef84 2662 struct myri10ge_slice_state *ss;
0da34b6d 2663 struct mcp_kreq_ether_send *req;
b53bef84 2664 struct myri10ge_tx_buf *tx;
0da34b6d 2665 struct skb_frag_struct *frag;
236bb5e6 2666 struct netdev_queue *netdev_queue;
0da34b6d 2667 dma_addr_t bus;
40f6cff5
AV		 2668 u32 low;
2669 __be32 high_swapped;
0da34b6d
BG		 2670 unsigned int len;
2671 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
236bb5e6 2672 u16 pseudo_hdr_offset, cksum_offset, queue;
0da34b6d
BG		 2673 int cum_len, seglen, boundary, rdma_count;
2674 u8 flags, odd_flag;
2675
236bb5e6 2676 queue = skb_get_queue_mapping(skb);
236bb5e6
BG		 2677 ss = &mgp->ss[queue];
2678 netdev_queue = netdev_get_tx_queue(mgp->dev, queue);
b53bef84 2679 tx = &ss->tx;
236bb5e6 2680
0da34b6d
BG		 2681again:
2682 req = tx->req_list;
2683 avail = tx->mask - 1 - (tx->req - tx->done);
2684
2685 mss = 0;
2686 max_segments = MXGEFW_MAX_SEND_DESC;
2687
917690cd 2688 if (skb_is_gso(skb)) {
7967168c 2689 mss = skb_shinfo(skb)->gso_size;
917690cd 2690 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
0da34b6d 2691 }
0da34b6d
BG		 2692
2693 if ((unlikely(avail < max_segments))) {
2694 /* we are out of transmit resources */
b53bef84 2695 tx->stop_queue++;
236bb5e6 2696 netif_tx_stop_queue(netdev_queue);
5b548140 2697 return NETDEV_TX_BUSY;
0da34b6d
BG		 2698 }
2699
2700 /* Setup checksum offloading, if needed */
2701 cksum_offset = 0;
2702 pseudo_hdr_offset = 0;
2703 odd_flag = 0;
2704 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
84fa7933 2705 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
ea2ae17d 2706 cksum_offset = skb_transport_offset(skb);
ff1dcadb 2707 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
0da34b6d
BG		 2708 /* If the headers are excessively large, then we must
2709 * fall back to a software checksum */
4f93fde0
BG		 2710 if (unlikely(!mss && (cksum_offset > 255 ||
2711 pseudo_hdr_offset > 127))) {
84fa7933 2712 if (skb_checksum_help(skb))
0da34b6d
BG		 2713 goto drop;
2714 cksum_offset = 0;
2715 pseudo_hdr_offset = 0;
2716 } else {
0da34b6d
BG		 2717 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2718 flags |= MXGEFW_FLAGS_CKSUM;
2719 }
2720 }
2721
2722 cum_len = 0;
2723
0da34b6d
BG		 2724 if (mss) { /* TSO */
2725 /* this removes any CKSUM flag from before */
2726 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2727
2728 /* negative cum_len signifies to the
2729 * send loop that we are still in the
2730 * header portion of the TSO packet.
4f93fde0 2731 * TSO header can be at most 1KB long */
ab6a5bb6 2732 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
0da34b6d 2733
4f93fde0
BG		 2734 /* for IPv6 TSO, the checksum offset stores the
2735 * TCP header length, to save the firmware from
2736 * the need to parse the headers */
2737 if (skb_is_gso_v6(skb)) {
2738 cksum_offset = tcp_hdrlen(skb);
2739 /* Can only handle headers <= max_tso6 long */
2740 if (unlikely(-cum_len > mgp->max_tso6))
2741 return myri10ge_sw_tso(skb, dev);
2742 }
0da34b6d
BG		 2743 /* for TSO, pseudo_hdr_offset holds mss.
2744 * The firmware figures out where to put
2745 * the checksum by parsing the header. */
40f6cff5 2746 pseudo_hdr_offset = mss;
0da34b6d 2747 } else
0da34b6d
BG		 2748 /* Mark small packets, and pad out tiny packets */
2749 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2750 flags |= MXGEFW_FLAGS_SMALL;
2751
2752 /* pad frames to at least ETH_ZLEN bytes */
2753 if (unlikely(skb->len < ETH_ZLEN)) {
5b057c6b 2754 if (skb_padto(skb, ETH_ZLEN)) {
0da34b6d
BG		 2755 /* The packet is gone, so we must
2756 * return 0 */
b53bef84 2757 ss->stats.tx_dropped += 1;
6ed10654 2758 return NETDEV_TX_OK;
0da34b6d
BG		 2759 }
2760 /* adjust the len to account for the zero pad
2761 * so that the nic can know how long it is */
2762 skb->len = ETH_ZLEN;
2763 }
2764 }
2765
2766 /* map the skb for DMA */
2767 len = skb->len - skb->data_len;
2768 idx = tx->req & tx->mask;
2769 tx->info[idx].skb = skb;
2770 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2771 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2772 pci_unmap_len_set(&tx->info[idx], len, len);
2773
2774 frag_cnt = skb_shinfo(skb)->nr_frags;
2775 frag_idx = 0;
2776 count = 0;
2777 rdma_count = 0;
2778
2779 /* "rdma_count" is the number of RDMAs belonging to the
2780 * current packet BEFORE the current send request. For
2781 * non-TSO packets, this is equal to "count".
2782 * For TSO packets, rdma_count needs to be reset
2783 * to 0 after a segment cut.
2784 *
2785 * The rdma_count field of the send request is
2786 * the number of RDMAs of the packet starting at
2787 * that request. For TSO send requests with one ore more cuts
2788 * in the middle, this is the number of RDMAs starting
2789 * after the last cut in the request. All previous
2790 * segments before the last cut implicitly have 1 RDMA.
2791 *
2792 * Since the number of RDMAs is not known beforehand,
2793 * it must be filled-in retroactively - after each
2794 * segmentation cut or at the end of the entire packet.
2795 */
2796
2797 while (1) {
2798 /* Break the SKB or Fragment up into pieces which
b53bef84 2799 * do not cross mgp->tx_boundary */
0da34b6d
BG		 2800 low = MYRI10GE_LOWPART_TO_U32(bus);
2801 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2802 while (len) {
2803 u8 flags_next;
2804 int cum_len_next;
2805
2806 if (unlikely(count == max_segments))
2807 goto abort_linearize;
2808
b53bef84
BG		 2809 boundary =
2810 (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
0da34b6d
BG		 2811 seglen = boundary - low;
2812 if (seglen > len)
2813 seglen = len;
2814 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2815 cum_len_next = cum_len + seglen;
0da34b6d
BG		 2816 if (mss) { /* TSO */
2817 (req - rdma_count)->rdma_count = rdma_count + 1;
2818
2819 if (likely(cum_len >= 0)) { /* payload */
2820 int next_is_first, chop;
2821
2822 chop = (cum_len_next > mss);
2823 cum_len_next = cum_len_next % mss;
2824 next_is_first = (cum_len_next == 0);
2825 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2826 flags_next |= next_is_first *
2827 MXGEFW_FLAGS_FIRST;
2828 rdma_count |= -(chop | next_is_first);
2829 rdma_count += chop & !next_is_first;
2830 } else if (likely(cum_len_next >= 0)) { /* header ends */
2831 int small;
2832
2833 rdma_count = -1;
2834 cum_len_next = 0;
2835 seglen = -cum_len;
2836 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2837 flags_next = MXGEFW_FLAGS_TSO_PLD |
2838 MXGEFW_FLAGS_FIRST |
2839 (small * MXGEFW_FLAGS_SMALL);
2840 }
2841 }
0da34b6d
BG		 2842 req->addr_high = high_swapped;
2843 req->addr_low = htonl(low);
40f6cff5 2844 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
0da34b6d
BG		 2845 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2846 req->rdma_count = 1;
2847 req->length = htons(seglen);
2848 req->cksum_offset = cksum_offset;
2849 req->flags = flags | ((cum_len & 1) * odd_flag);
2850
2851 low += seglen;
2852 len -= seglen;
2853 cum_len = cum_len_next;
2854 flags = flags_next;
2855 req++;
2856 count++;
2857 rdma_count++;
4f93fde0
BG		 2858 if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2859 if (unlikely(cksum_offset > seglen))
2860 cksum_offset -= seglen;
2861 else
2862 cksum_offset = 0;
2863 }
0da34b6d
BG		 2864 }
2865 if (frag_idx == frag_cnt)
2866 break;
2867
2868 /* map next fragment for DMA */
2869 idx = (count + tx->req) & tx->mask;
2870 frag = &skb_shinfo(skb)->frags[frag_idx];
2871 frag_idx++;
2872 len = frag->size;
2873 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2874 len, PCI_DMA_TODEVICE);
2875 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2876 pci_unmap_len_set(&tx->info[idx], len, len);
2877 }
2878
2879 (req - rdma_count)->rdma_count = rdma_count;
0da34b6d
BG		 2880 if (mss)
2881 do {
2882 req--;
2883 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2884 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2885 MXGEFW_FLAGS_FIRST)));
0da34b6d
BG		 2886 idx = ((count - 1) + tx->req) & tx->mask;
2887 tx->info[idx].last = 1;
e454e7e2 2888 myri10ge_submit_req(tx, tx->req_list, count);
236bb5e6
BG		 2889 /* if using multiple tx queues, make sure NIC polls the
2890 * current slice */
2891 if ((mgp->dev->real_num_tx_queues > 1) && tx->queue_active == 0) {
2892 tx->queue_active = 1;
2893 put_be32(htonl(1), tx->send_go);
8c2f5fa5 2894 mb();
6824a105 2895 mmiowb();
236bb5e6 2896 }
0da34b6d
BG		 2897 tx->pkt_start++;
2898 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
b53bef84 2899 tx->stop_queue++;
236bb5e6 2900 netif_tx_stop_queue(netdev_queue);
0da34b6d 2901 }
6ed10654 2902 return NETDEV_TX_OK;
0da34b6d
BG		 2903
2904abort_linearize:
2905 /* Free any DMA resources we've alloced and clear out the skb
2906 * slot so as to not trip up assertions, and to avoid a
2907 * double-free if linearizing fails */
2908
2909 last_idx = (idx + 1) & tx->mask;
2910 idx = tx->req & tx->mask;
2911 tx->info[idx].skb = NULL;
2912 do {
2913 len = pci_unmap_len(&tx->info[idx], len);
2914 if (len) {
2915 if (tx->info[idx].skb != NULL)
2916 pci_unmap_single(mgp->pdev,
2917 pci_unmap_addr(&tx->info[idx],
2918 bus), len,
2919 PCI_DMA_TODEVICE);
2920 else
2921 pci_unmap_page(mgp->pdev,
2922 pci_unmap_addr(&tx->info[idx],
2923 bus), len,
2924 PCI_DMA_TODEVICE);
2925 pci_unmap_len_set(&tx->info[idx], len, 0);
2926 tx->info[idx].skb = NULL;
2927 }
2928 idx = (idx + 1) & tx->mask;
2929 } while (idx != last_idx);
89114afd 2930 if (skb_is_gso(skb)) {
0da34b6d
BG		 2931 printk(KERN_ERR
2932 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2933 mgp->dev->name);
2934 goto drop;
2935 }
2936
bec0e859 2937 if (skb_linearize(skb))
0da34b6d
BG		 2938 goto drop;
2939
b53bef84 2940 tx->linearized++;
0da34b6d
BG		 2941 goto again;
2942
2943drop:
2944 dev_kfree_skb_any(skb);
b53bef84 2945 ss->stats.tx_dropped += 1;
6ed10654 2946 return NETDEV_TX_OK;
0da34b6d
BG		 2947
2948}
2949
4f93fde0
BG		 2950static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev)
2951{
2952 struct sk_buff *segs, *curr;
b53bef84 2953 struct myri10ge_priv *mgp = netdev_priv(dev);
d6279c88 2954 struct myri10ge_slice_state *ss;
4f93fde0
BG		 2955 int status;
2956
2957 segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
801678c5 2958 if (IS_ERR(segs))
4f93fde0
BG		 2959 goto drop;
2960
2961 while (segs) {
2962 curr = segs;
2963 segs = segs->next;
2964 curr->next = NULL;
2965 status = myri10ge_xmit(curr, dev);
2966 if (status != 0) {
2967 dev_kfree_skb_any(curr);
2968 if (segs != NULL) {
2969 curr = segs;
2970 segs = segs->next;
2971 curr->next = NULL;
2972 dev_kfree_skb_any(segs);
2973 }
2974 goto drop;
2975 }
2976 }
2977 dev_kfree_skb_any(skb);
ec634fe3 2978 return NETDEV_TX_OK;
4f93fde0
BG		 2979
2980drop:
d6279c88 2981 ss = &mgp->ss[skb_get_queue_mapping(skb)];
4f93fde0 2982 dev_kfree_skb_any(skb);
d6279c88 2983 ss->stats.tx_dropped += 1;
ec634fe3 2984 return NETDEV_TX_OK;
4f93fde0
BG		 2985}
2986
0da34b6d
BG		 2987static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2988{
2989 struct myri10ge_priv *mgp = netdev_priv(dev);
0dcffac1
BG		 2990 struct myri10ge_slice_netstats *slice_stats;
2991 struct net_device_stats *stats = &mgp->stats;
2992 int i;
2993
59081825 2994 spin_lock(&mgp->stats_lock);
0dcffac1
BG		 2995 memset(stats, 0, sizeof(*stats));
2996 for (i = 0; i < mgp->num_slices; i++) {
2997 slice_stats = &mgp->ss[i].stats;
2998 stats->rx_packets += slice_stats->rx_packets;
2999 stats->tx_packets += slice_stats->tx_packets;
3000 stats->rx_bytes += slice_stats->rx_bytes;
3001 stats->tx_bytes += slice_stats->tx_bytes;
3002 stats->rx_dropped += slice_stats->rx_dropped;
3003 stats->tx_dropped += slice_stats->tx_dropped;
3004 }
59081825 3005 spin_unlock(&mgp->stats_lock);
0dcffac1 3006 return stats;
0da34b6d
BG		 3007}
3008
3009static void myri10ge_set_multicast_list(struct net_device *dev)
3010{
b53bef84 3011 struct myri10ge_priv *mgp = netdev_priv(dev);
85a7ea1b 3012 struct myri10ge_cmd cmd;
85a7ea1b 3013 struct dev_mc_list *mc_list;
6250223e 3014 __be32 data[2] = { 0, 0 };
85a7ea1b
BG		 3015 int err;
3016
0da34b6d
BG		 3017 /* can be called from atomic contexts,
3018 * pass 1 to force atomicity in myri10ge_send_cmd() */
85a7ea1b
BG		 3019 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
3020
3021 /* This firmware is known to not support multicast */
2f76216f 3022 if (!mgp->fw_multicast_support)
85a7ea1b
BG		 3023 return;
3024
3025 /* Disable multicast filtering */
3026
3027 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
3028 if (err != 0) {
3029 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
3030 " error status: %d\n", dev->name, err);
3031 goto abort;
3032 }
3033
2f76216f 3034 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
85a7ea1b
BG		 3035 /* request to disable multicast filtering, so quit here */
3036 return;
3037 }
3038
3039 /* Flush the filters */
3040
3041 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
3042 &cmd, 1);
3043 if (err != 0) {
3044 printk(KERN_ERR
3045 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
3046 ", error status: %d\n", dev->name, err);
3047 goto abort;
3048 }
3049
3050 /* Walk the multicast list, and add each address */
3051 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
40f6cff5
AV		 3052 memcpy(data, &mc_list->dmi_addr, 6);
3053 cmd.data0 = ntohl(data[0]);
3054 cmd.data1 = ntohl(data[1]);
85a7ea1b
BG		 3055 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
3056 &cmd, 1);
3057
3058 if (err != 0) {
3059 printk(KERN_ERR "myri10ge: %s: Failed "
3060 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
3061 "%d\t", dev->name, err);
e174961c 3062 printk(KERN_ERR "MAC %pM\n", mc_list->dmi_addr);
85a7ea1b
BG		 3063 goto abort;
3064 }
3065 }
3066 /* Enable multicast filtering */
3067 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
3068 if (err != 0) {
3069 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
3070 "error status: %d\n", dev->name, err);
3071 goto abort;
3072 }
3073
3074 return;
3075
3076abort:
3077 return;
0da34b6d
BG		 3078}
3079
3080static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
3081{
3082 struct sockaddr *sa = addr;
3083 struct myri10ge_priv *mgp = netdev_priv(dev);
3084 int status;
3085
3086 if (!is_valid_ether_addr(sa->sa_data))
3087 return -EADDRNOTAVAIL;
3088
3089 status = myri10ge_update_mac_address(mgp, sa->sa_data);
3090 if (status != 0) {
3091 printk(KERN_ERR
3092 "myri10ge: %s: changing mac address failed with %d\n",
3093 dev->name, status);
3094 return status;
3095 }
3096
3097 /* change the dev structure */
3098 memcpy(dev->dev_addr, sa->sa_data, 6);
3099 return 0;
3100}
3101
3102static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
3103{
3104 struct myri10ge_priv *mgp = netdev_priv(dev);
3105 int error = 0;
3106
3107 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
3108 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
3109 dev->name, new_mtu);
3110 return -EINVAL;
3111 }
3112 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
3113 dev->name, dev->mtu, new_mtu);
3114 if (mgp->running) {
3115 /* if we change the mtu on an active device, we must
3116 * reset the device so the firmware sees the change */
3117 myri10ge_close(dev);
3118 dev->mtu = new_mtu;
3119 myri10ge_open(dev);
3120 } else
3121 dev->mtu = new_mtu;
3122
3123 return error;
3124}
3125
3126/*
3127 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
3128 * Only do it if the bridge is a root port since we don't want to disturb
3129 * any other device, except if forced with myri10ge_ecrc_enable > 1.
3130 */
3131
0da34b6d
BG		 3132static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
3133{
3134 struct pci_dev *bridge = mgp->pdev->bus->self;
3135 struct device *dev = &mgp->pdev->dev;
3136 unsigned cap;
3137 unsigned err_cap;
3138 u16 val;
3139 u8 ext_type;
3140 int ret;
3141
3142 if (!myri10ge_ecrc_enable || !bridge)
3143 return;
3144
3145 /* check that the bridge is a root port */
3146 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
3147 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
3148 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3149 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
3150 if (myri10ge_ecrc_enable > 1) {
eca3fd83 3151 struct pci_dev *prev_bridge, *old_bridge = bridge;
0da34b6d
BG		 3152
3153 /* Walk the hierarchy up to the root port
3154 * where ECRC has to be enabled */
3155 do {
eca3fd83 3156 prev_bridge = bridge;
0da34b6d 3157 bridge = bridge->bus->self;
eca3fd83 3158 if (!bridge || prev_bridge == bridge) {
0da34b6d
BG		 3159 dev_err(dev,
3160 "Failed to find root port"
3161 " to force ECRC\n");
3162 return;
3163 }
3164 cap =
3165 pci_find_capability(bridge, PCI_CAP_ID_EXP);
3166 pci_read_config_word(bridge,
3167 cap + PCI_CAP_FLAGS, &val);
3168 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3169 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
3170
3171 dev_info(dev,
3172 "Forcing ECRC on non-root port %s"
3173 " (enabling on root port %s)\n",
3174 pci_name(old_bridge), pci_name(bridge));
3175 } else {
3176 dev_err(dev,
3177 "Not enabling ECRC on non-root port %s\n",
3178 pci_name(bridge));
3179 return;
3180 }
3181 }
3182
3183 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
0da34b6d
BG		 3184 if (!cap)
3185 return;
3186
3187 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
3188 if (ret) {
3189 dev_err(dev, "failed reading ext-conf-space of %s\n",
3190 pci_name(bridge));
3191 dev_err(dev, "\t pci=nommconf in use? "
3192 "or buggy/incomplete/absent ACPI MCFG attr?\n");
3193 return;
3194 }
3195 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
3196 return;
3197
3198 err_cap |= PCI_ERR_CAP_ECRC_GENE;
3199 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
3200 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
0da34b6d
BG		 3201}
3202
3203/*
3204 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
3205 * when the PCI-E Completion packets are aligned on an 8-byte
3206 * boundary. Some PCI-E chip sets always align Completion packets; on
3207 * the ones that do not, the alignment can be enforced by enabling
3208 * ECRC generation (if supported).
3209 *
3210 * When PCI-E Completion packets are not aligned, it is actually more
3211 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
3212 *
3213 * If the driver can neither enable ECRC nor verify that it has
3214 * already been enabled, then it must use a firmware image which works
0dcffac1 3215 * around unaligned completion packets (myri10ge_rss_ethp_z8e.dat), and it
0da34b6d 3216 * should also ensure that it never gives the device a Read-DMA which is
b53bef84 3217 * larger than 2KB by setting the tx_boundary to 2KB. If ECRC is
0dcffac1 3218 * enabled, then the driver should use the aligned (myri10ge_rss_eth_z8e.dat)
b53bef84 3219 * firmware image, and set tx_boundary to 4KB.
0da34b6d
BG		 3220 */
3221
5443e9ea 3222static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
0da34b6d 3223{
5443e9ea
BG		 3224 struct pci_dev *pdev = mgp->pdev;
3225 struct device *dev = &pdev->dev;
302d242c 3226 int status;
0da34b6d 3227
b53bef84 3228 mgp->tx_boundary = 4096;
5443e9ea
BG		 3229 /*
3230 * Verify the max read request size was set to 4KB
3231 * before trying the test with 4KB.
3232 */
302d242c
BG		 3233 status = pcie_get_readrq(pdev);
3234 if (status < 0) {
5443e9ea
BG		 3235 dev_err(dev, "Couldn't read max read req size: %d\n", status);
3236 goto abort;
3237 }
302d242c
BG		 3238 if (status != 4096) {
3239 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
b53bef84 3240 mgp->tx_boundary = 2048;
5443e9ea
BG		 3241 }
3242 /*
3243 * load the optimized firmware (which assumes aligned PCIe
3244 * completions) in order to see if it works on this host.
3245 */
3246 mgp->fw_name = myri10ge_fw_aligned;
0dcffac1 3247 status = myri10ge_load_firmware(mgp, 1);
5443e9ea
BG		 3248 if (status != 0) {
3249 goto abort;
3250 }
3251
3252 /*
3253 * Enable ECRC if possible
3254 */
3255 myri10ge_enable_ecrc(mgp);
3256
3257 /*
3258 * Run a DMA test which watches for unaligned completions and
3259 * aborts on the first one seen.
3260 */
3261
3262 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
3263 if (status == 0)
3264 return; /* keep the aligned firmware */
3265
3266 if (status != -E2BIG)
3267 dev_warn(dev, "DMA test failed: %d\n", status);
3268 if (status == -ENOSYS)
3269 dev_warn(dev, "Falling back to ethp! "
3270 "Please install up to date fw\n");
3271abort:
3272 /* fall back to using the unaligned firmware */
b53bef84 3273 mgp->tx_boundary = 2048;
0da34b6d
BG		 3274 mgp->fw_name = myri10ge_fw_unaligned;
3275
5443e9ea
BG		 3276}
3277
3278static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
3279{
2d90b0aa
BG		 3280 int overridden = 0;
3281
0da34b6d 3282 if (myri10ge_force_firmware == 0) {
ce7f9368
BG		 3283 int link_width, exp_cap;
3284 u16 lnk;
3285
3286 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
3287 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
3288 link_width = (lnk >> 4) & 0x3f;
3289
ce7f9368
BG		 3290 /* Check to see if Link is less than 8 or if the
3291 * upstream bridge is known to provide aligned
3292 * completions */
3293 if (link_width < 8) {
3294 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
3295 link_width);
b53bef84 3296 mgp->tx_boundary = 4096;
ce7f9368 3297 mgp->fw_name = myri10ge_fw_aligned;
5443e9ea
BG		 3298 } else {
3299 myri10ge_firmware_probe(mgp);
0da34b6d
BG		 3300 }
3301 } else {
3302 if (myri10ge_force_firmware == 1) {
3303 dev_info(&mgp->pdev->dev,
3304 "Assuming aligned completions (forced)\n");
b53bef84 3305 mgp->tx_boundary = 4096;
0da34b6d
BG		 3306 mgp->fw_name = myri10ge_fw_aligned;
3307 } else {
3308 dev_info(&mgp->pdev->dev,
3309 "Assuming unaligned completions (forced)\n");
b53bef84 3310 mgp->tx_boundary = 2048;
0da34b6d
BG		 3311 mgp->fw_name = myri10ge_fw_unaligned;
3312 }
3313 }
3314 if (myri10ge_fw_name != NULL) {
2d90b0aa 3315 overridden = 1;
0da34b6d
BG		 3316 mgp->fw_name = myri10ge_fw_name;
3317 }
2d90b0aa
BG		 3318 if (mgp->board_number < MYRI10GE_MAX_BOARDS &&
3319 myri10ge_fw_names[mgp->board_number] != NULL &&
3320 strlen(myri10ge_fw_names[mgp->board_number])) {
3321 mgp->fw_name = myri10ge_fw_names[mgp->board_number];
3322 overridden = 1;
3323 }
3324 if (overridden)
3325 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
3326 mgp->fw_name);
0da34b6d
BG		 3327}
3328
0da34b6d 3329#ifdef CONFIG_PM
0da34b6d
BG		 3330static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
3331{
3332 struct myri10ge_priv *mgp;
3333 struct net_device *netdev;
3334
3335 mgp = pci_get_drvdata(pdev);
3336 if (mgp == NULL)
3337 return -EINVAL;
3338 netdev = mgp->dev;
3339
3340 netif_device_detach(netdev);
3341 if (netif_running(netdev)) {
3342 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
3343 rtnl_lock();
3344 myri10ge_close(netdev);
3345 rtnl_unlock();
3346 }
3347 myri10ge_dummy_rdma(mgp, 0);
83f6e152 3348 pci_save_state(pdev);
0da34b6d 3349 pci_disable_device(pdev);
1a63e846
BG		 3350
3351 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
0da34b6d
BG		 3352}
3353
3354static int myri10ge_resume(struct pci_dev *pdev)
3355{
3356 struct myri10ge_priv *mgp;
3357 struct net_device *netdev;
3358 int status;
3359 u16 vendor;
3360
3361 mgp = pci_get_drvdata(pdev);
3362 if (mgp == NULL)
3363 return -EINVAL;
3364 netdev = mgp->dev;
3365 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
3366 msleep(5); /* give card time to respond */
3367 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3368 if (vendor == 0xffff) {
3369 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
3370 mgp->dev->name);
3371 return -EIO;
3372 }
83f6e152 3373
1a63e846
BG		 3374 status = pci_restore_state(pdev);
3375 if (status)
3376 return status;
4c2248cc
BG		 3377
3378 status = pci_enable_device(pdev);
1a63e846 3379 if (status) {
4c2248cc 3380 dev_err(&pdev->dev, "failed to enable device\n");
1a63e846 3381 return status;
4c2248cc
BG		 3382 }
3383
0da34b6d
BG		 3384 pci_set_master(pdev);
3385
0da34b6d 3386 myri10ge_reset(mgp);
013b68bf 3387 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 3388
3389 /* Save configuration space to be restored if the
3390 * nic resets due to a parity error */
83f6e152 3391 pci_save_state(pdev);
0da34b6d
BG		 3392
3393 if (netif_running(netdev)) {
3394 rtnl_lock();
df30a740 3395 status = myri10ge_open(netdev);
0da34b6d 3396 rtnl_unlock();
df30a740
BG		 3397 if (status != 0)
3398 goto abort_with_enabled;
3399
0da34b6d
BG		 3400 }
3401 netif_device_attach(netdev);
3402
3403 return 0;
3404
4c2248cc
BG		 3405abort_with_enabled:
3406 pci_disable_device(pdev);
0da34b6d
BG		 3407 return -EIO;
3408
3409}
0da34b6d
BG		 3410#endif /* CONFIG_PM */
3411
3412static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
3413{
3414 struct pci_dev *pdev = mgp->pdev;
3415 int vs = mgp->vendor_specific_offset;
3416 u32 reboot;
3417
3418 /*enter read32 mode */
3419 pci_write_config_byte(pdev, vs + 0x10, 0x3);
3420
3421 /*read REBOOT_STATUS (0xfffffff0) */
3422 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
3423 pci_read_config_dword(pdev, vs + 0x14, &reboot);
3424 return reboot;
3425}
3426
3427/*
3428 * This watchdog is used to check whether the board has suffered
3429 * from a parity error and needs to be recovered.
3430 */
c4028958 3431static void myri10ge_watchdog(struct work_struct *work)
0da34b6d 3432{
c4028958 3433 struct myri10ge_priv *mgp =
6250223e 3434 container_of(work, struct myri10ge_priv, watchdog_work);
b53bef84 3435 struct myri10ge_tx_buf *tx;
0da34b6d 3436 u32 reboot;
d0234215 3437 int status, rebooted;
0dcffac1 3438 int i;
0da34b6d
BG		 3439 u16 cmd, vendor;
3440
3441 mgp->watchdog_resets++;
3442 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
d0234215 3443 rebooted = 0;
0da34b6d
BG		 3444 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3445 /* Bus master DMA disabled? Check to see
3446 * if the card rebooted due to a parity error
3447 * For now, just report it */
3448 reboot = myri10ge_read_reboot(mgp);
3449 printk(KERN_ERR
f181137f
BG		 3450 "myri10ge: %s: NIC rebooted (0x%x),%s resetting\n",
3451 mgp->dev->name, reboot,
3452 myri10ge_reset_recover ? " " : " not");
3453 if (myri10ge_reset_recover == 0)
3454 return;
d0234215
BG		 3455 rtnl_lock();
3456 mgp->rebooted = 1;
3457 rebooted = 1;
3458 myri10ge_close(mgp->dev);
f181137f 3459 myri10ge_reset_recover--;
d0234215 3460 mgp->rebooted = 0;
0da34b6d
BG		 3461 /*
3462 * A rebooted nic will come back with config space as
3463 * it was after power was applied to PCIe bus.
3464 * Attempt to restore config space which was saved
3465 * when the driver was loaded, or the last time the
3466 * nic was resumed from power saving mode.
3467 */
83f6e152 3468 pci_restore_state(mgp->pdev);
7adda30c
BG		 3469
3470 /* save state again for accounting reasons */
83f6e152 3471 pci_save_state(mgp->pdev);
7adda30c 3472
0da34b6d
BG		 3473 } else {
3474 /* if we get back -1's from our slot, perhaps somebody
3475 * powered off our card. Don't try to reset it in
3476 * this case */
3477 if (cmd == 0xffff) {
3478 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3479 if (vendor == 0xffff) {
3480 printk(KERN_ERR
3481 "myri10ge: %s: device disappeared!\n",
3482 mgp->dev->name);
3483 return;
3484 }
3485 }
3486 /* Perhaps it is a software error. Try to reset */
3487
3488 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
3489 mgp->dev->name);
0dcffac1
BG		 3490 for (i = 0; i < mgp->num_slices; i++) {
3491 tx = &mgp->ss[i].tx;
3492 printk(KERN_INFO
236bb5e6
BG		 3493 "myri10ge: %s: (%d): %d %d %d %d %d %d\n",
3494 mgp->dev->name, i, tx->queue_active, tx->req,
3495 tx->done, tx->pkt_start, tx->pkt_done,
0dcffac1
BG		 3496 (int)ntohl(mgp->ss[i].fw_stats->
3497 send_done_count));
3498 msleep(2000);
3499 printk(KERN_INFO
236bb5e6
BG		 3500 "myri10ge: %s: (%d): %d %d %d %d %d %d\n",
3501 mgp->dev->name, i, tx->queue_active, tx->req,
3502 tx->done, tx->pkt_start, tx->pkt_done,
0dcffac1
BG		 3503 (int)ntohl(mgp->ss[i].fw_stats->
3504 send_done_count));
3505 }
0da34b6d 3506 }
236bb5e6 3507
d0234215
BG		 3508 if (!rebooted) {
3509 rtnl_lock();
3510 myri10ge_close(mgp->dev);
3511 }
0dcffac1 3512 status = myri10ge_load_firmware(mgp, 1);
0da34b6d
BG		 3513 if (status != 0)
3514 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
3515 mgp->dev->name);
3516 else
3517 myri10ge_open(mgp->dev);
3518 rtnl_unlock();
3519}
3520
3521/*
3522 * We use our own timer routine rather than relying upon
3523 * netdev->tx_timeout because we have a very large hardware transmit
3524 * queue. Due to the large queue, the netdev->tx_timeout function
3525 * cannot detect a NIC with a parity error in a timely fashion if the
3526 * NIC is lightly loaded.
3527 */
3528static void myri10ge_watchdog_timer(unsigned long arg)
3529{
3530 struct myri10ge_priv *mgp;
b53bef84 3531 struct myri10ge_slice_state *ss;
d0234215 3532 int i, reset_needed, busy_slice_cnt;
626fda94 3533 u32 rx_pause_cnt;
d0234215 3534 u16 cmd;
0da34b6d
BG		 3535
3536 mgp = (struct myri10ge_priv *)arg;
c7dab99b 3537
0dcffac1 3538 rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
d0234215 3539 busy_slice_cnt = 0;
0dcffac1
BG		 3540 for (i = 0, reset_needed = 0;
3541 i < mgp->num_slices && reset_needed == 0; ++i) {
b53bef84 3542
0dcffac1
BG		 3543 ss = &mgp->ss[i];
3544 if (ss->rx_small.watchdog_needed) {
3545 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3546 mgp->small_bytes + MXGEFW_PAD,
3547 1);
3548 if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
3549 myri10ge_fill_thresh)
3550 ss->rx_small.watchdog_needed = 0;
3551 }
3552 if (ss->rx_big.watchdog_needed) {
3553 myri10ge_alloc_rx_pages(mgp, &ss->rx_big,
3554 mgp->big_bytes, 1);
3555 if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
3556 myri10ge_fill_thresh)
3557 ss->rx_big.watchdog_needed = 0;
3558 }
3559
3560 if (ss->tx.req != ss->tx.done &&
3561 ss->tx.done == ss->watchdog_tx_done &&
3562 ss->watchdog_tx_req != ss->watchdog_tx_done) {
3563 /* nic seems like it might be stuck.. */
3564 if (rx_pause_cnt != mgp->watchdog_pause) {
3565 if (net_ratelimit())
236bb5e6
BG		 3566 printk(KERN_WARNING
3567 "myri10ge %s slice %d:"
0dcffac1 3568 "TX paused, check link partner\n",
236bb5e6 3569 mgp->dev->name, i);
0dcffac1 3570 } else {
236bb5e6
BG		 3571 printk(KERN_WARNING
3572 "myri10ge %s slice %d stuck:",
3573 mgp->dev->name, i);
0dcffac1
BG		 3574 reset_needed = 1;
3575 }
626fda94 3576 }
d0234215
BG		 3577 if (ss->watchdog_tx_done != ss->tx.done ||
3578 ss->watchdog_rx_done != ss->rx_done.cnt) {
3579 busy_slice_cnt++;
3580 }
0dcffac1
BG		 3581 ss->watchdog_tx_done = ss->tx.done;
3582 ss->watchdog_tx_req = ss->tx.req;
d0234215
BG		 3583 ss->watchdog_rx_done = ss->rx_done.cnt;
3584 }
3585 /* if we've sent or received no traffic, poll the NIC to
3586 * ensure it is still there. Otherwise, we risk not noticing
3587 * an error in a timely fashion */
3588 if (busy_slice_cnt == 0) {
3589 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3590 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3591 reset_needed = 1;
3592 }
626fda94 3593 }
626fda94 3594 mgp->watchdog_pause = rx_pause_cnt;
0dcffac1
BG		 3595
3596 if (reset_needed) {
3597 schedule_work(&mgp->watchdog_work);
3598 } else {
3599 /* rearm timer */
3600 mod_timer(&mgp->watchdog_timer,
3601 jiffies + myri10ge_watchdog_timeout * HZ);
3602 }
0da34b6d
BG		 3603}
3604
77929732
BG		 3605static void myri10ge_free_slices(struct myri10ge_priv *mgp)
3606{
3607 struct myri10ge_slice_state *ss;
3608 struct pci_dev *pdev = mgp->pdev;
3609 size_t bytes;
3610 int i;
3611
3612 if (mgp->ss == NULL)
3613 return;
3614
3615 for (i = 0; i < mgp->num_slices; i++) {
3616 ss = &mgp->ss[i];
3617 if (ss->rx_done.entry != NULL) {
3618 bytes = mgp->max_intr_slots *
3619 sizeof(*ss->rx_done.entry);
3620 dma_free_coherent(&pdev->dev, bytes,
3621 ss->rx_done.entry, ss->rx_done.bus);
3622 ss->rx_done.entry = NULL;
3623 }
3624 if (ss->fw_stats != NULL) {
3625 bytes = sizeof(*ss->fw_stats);
3626 dma_free_coherent(&pdev->dev, bytes,
3627 ss->fw_stats, ss->fw_stats_bus);
3628 ss->fw_stats = NULL;
3629 }
3630 }
3631 kfree(mgp->ss);
3632 mgp->ss = NULL;
3633}
3634
3635static int myri10ge_alloc_slices(struct myri10ge_priv *mgp)
3636{
3637 struct myri10ge_slice_state *ss;
3638 struct pci_dev *pdev = mgp->pdev;
3639 size_t bytes;
3640 int i;
3641
3642 bytes = sizeof(*mgp->ss) * mgp->num_slices;
3643 mgp->ss = kzalloc(bytes, GFP_KERNEL);
3644 if (mgp->ss == NULL) {
3645 return -ENOMEM;
3646 }
3647
3648 for (i = 0; i < mgp->num_slices; i++) {
3649 ss = &mgp->ss[i];
3650 bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry);
3651 ss->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3652 &ss->rx_done.bus,
3653 GFP_KERNEL);
3654 if (ss->rx_done.entry == NULL)
3655 goto abort;
3656 memset(ss->rx_done.entry, 0, bytes);
3657 bytes = sizeof(*ss->fw_stats);
3658 ss->fw_stats = dma_alloc_coherent(&pdev->dev, bytes,
3659 &ss->fw_stats_bus,
3660 GFP_KERNEL);
3661 if (ss->fw_stats == NULL)
3662 goto abort;
3663 ss->mgp = mgp;
3664 ss->dev = mgp->dev;
3665 netif_napi_add(ss->dev, &ss->napi, myri10ge_poll,
3666 myri10ge_napi_weight);
3667 }
3668 return 0;
3669abort:
3670 myri10ge_free_slices(mgp);
3671 return -ENOMEM;
3672}
3673
3674/*
3675 * This function determines the number of slices supported.
3676 * The number slices is the minumum of the number of CPUS,
3677 * the number of MSI-X irqs supported, the number of slices
3678 * supported by the firmware
3679 */
3680static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3681{
3682 struct myri10ge_cmd cmd;
3683 struct pci_dev *pdev = mgp->pdev;
3684 char *old_fw;
3685 int i, status, ncpus, msix_cap;
3686
3687 mgp->num_slices = 1;
3688 msix_cap = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3689 ncpus = num_online_cpus();
3690
3691 if (myri10ge_max_slices == 1 || msix_cap == 0 ||
3692 (myri10ge_max_slices == -1 && ncpus < 2))
3693 return;
3694
3695 /* try to load the slice aware rss firmware */
3696 old_fw = mgp->fw_name;
13b2738c
BG		 3697 if (myri10ge_fw_name != NULL) {
3698 dev_info(&mgp->pdev->dev, "overriding rss firmware to %s\n",
3699 myri10ge_fw_name);
3700 mgp->fw_name = myri10ge_fw_name;
3701 } else if (old_fw == myri10ge_fw_aligned)
77929732
BG		 3702 mgp->fw_name = myri10ge_fw_rss_aligned;
3703 else
3704 mgp->fw_name = myri10ge_fw_rss_unaligned;
3705 status = myri10ge_load_firmware(mgp, 0);
3706 if (status != 0) {
3707 dev_info(&pdev->dev, "Rss firmware not found\n");
3708 return;
3709 }
3710
3711 /* hit the board with a reset to ensure it is alive */
3712 memset(&cmd, 0, sizeof(cmd));
3713 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
3714 if (status != 0) {
3715 dev_err(&mgp->pdev->dev, "failed reset\n");
3716 goto abort_with_fw;
3717 return;
3718 }
3719
3720 mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot);
3721
3722 /* tell it the size of the interrupt queues */
3723 cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot);
3724 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
3725 if (status != 0) {
3726 dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3727 goto abort_with_fw;
3728 }
3729
3730 /* ask the maximum number of slices it supports */
3731 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0);
3732 if (status != 0)
3733 goto abort_with_fw;
3734 else
3735 mgp->num_slices = cmd.data0;
3736
3737 /* Only allow multiple slices if MSI-X is usable */
3738 if (!myri10ge_msi) {
3739 goto abort_with_fw;
3740 }
3741
3742 /* if the admin did not specify a limit to how many
3743 * slices we should use, cap it automatically to the
3744 * number of CPUs currently online */
3745 if (myri10ge_max_slices == -1)
3746 myri10ge_max_slices = ncpus;
3747
3748 if (mgp->num_slices > myri10ge_max_slices)
3749 mgp->num_slices = myri10ge_max_slices;
3750
3751 /* Now try to allocate as many MSI-X vectors as we have
3752 * slices. We give up on MSI-X if we can only get a single
3753 * vector. */
3754
3755 mgp->msix_vectors = kzalloc(mgp->num_slices *
3756 sizeof(*mgp->msix_vectors), GFP_KERNEL);
3757 if (mgp->msix_vectors == NULL)
3758 goto disable_msix;
3759 for (i = 0; i < mgp->num_slices; i++) {
3760 mgp->msix_vectors[i].entry = i;
3761 }
3762
3763 while (mgp->num_slices > 1) {
3764 /* make sure it is a power of two */
3765 while (!is_power_of_2(mgp->num_slices))
3766 mgp->num_slices--;
3767 if (mgp->num_slices == 1)
3768 goto disable_msix;
3769 status = pci_enable_msix(pdev, mgp->msix_vectors,
3770 mgp->num_slices);
3771 if (status == 0) {
3772 pci_disable_msix(pdev);
3773 return;
3774 }
3775 if (status > 0)
3776 mgp->num_slices = status;
3777 else
3778 goto disable_msix;
3779 }
3780
3781disable_msix:
3782 if (mgp->msix_vectors != NULL) {
3783 kfree(mgp->msix_vectors);
3784 mgp->msix_vectors = NULL;
3785 }
3786
3787abort_with_fw:
3788 mgp->num_slices = 1;
3789 mgp->fw_name = old_fw;
3790 myri10ge_load_firmware(mgp, 0);
3791}
77929732 3792
8126089f
SH		 3793static const struct net_device_ops myri10ge_netdev_ops = {
3794 .ndo_open = myri10ge_open,
3795 .ndo_stop = myri10ge_close,
3796 .ndo_start_xmit = myri10ge_xmit,
3797 .ndo_get_stats = myri10ge_get_stats,
3798 .ndo_validate_addr = eth_validate_addr,
3799 .ndo_change_mtu = myri10ge_change_mtu,
3800 .ndo_set_multicast_list = myri10ge_set_multicast_list,
3801 .ndo_set_mac_address = myri10ge_set_mac_address,
3802};
3803
0da34b6d
BG		 3804static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3805{
3806 struct net_device *netdev;
3807 struct myri10ge_priv *mgp;
3808 struct device *dev = &pdev->dev;
0da34b6d
BG		 3809 int i;
3810 int status = -ENXIO;
0da34b6d 3811 int dac_enabled;
00b5e505 3812 unsigned hdr_offset, ss_offset;
2d90b0aa 3813 static int board_number;
0da34b6d 3814
236bb5e6 3815 netdev = alloc_etherdev_mq(sizeof(*mgp), MYRI10GE_MAX_SLICES);
0da34b6d
BG		 3816 if (netdev == NULL) {
3817 dev_err(dev, "Could not allocate ethernet device\n");
3818 return -ENOMEM;
3819 }
3820
b245fb67
MH		 3821 SET_NETDEV_DEV(netdev, &pdev->dev);
3822
0da34b6d 3823 mgp = netdev_priv(netdev);
0da34b6d
BG		 3824 mgp->dev = netdev;
3825 mgp->pdev = pdev;
3826 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3827 mgp->pause = myri10ge_flow_control;
3828 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
c58ac5ca 3829 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
2d90b0aa 3830 mgp->board_number = board_number;
0da34b6d
BG		 3831 init_waitqueue_head(&mgp->down_wq);
3832
3833 if (pci_enable_device(pdev)) {
3834 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3835 status = -ENODEV;
3836 goto abort_with_netdev;
3837 }
0da34b6d
BG		 3838
3839 /* Find the vendor-specific cap so we can check
3840 * the reboot register later on */
3841 mgp->vendor_specific_offset
3842 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3843
3844 /* Set our max read request to 4KB */
302d242c 3845 status = pcie_set_readrq(pdev, 4096);
0da34b6d
BG		 3846 if (status != 0) {
3847 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3848 status);
e3fd5534 3849 goto abort_with_enabled;
0da34b6d
BG		 3850 }
3851
3852 pci_set_master(pdev);
3853 dac_enabled = 1;
6a35528a 3854 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
0da34b6d
BG		 3855 if (status != 0) {
3856 dac_enabled = 0;
3857 dev_err(&pdev->dev,
898eb71c
JP		 3858 "64-bit pci address mask was refused, "
3859 "trying 32-bit\n");
284901a9 3860 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
0da34b6d
BG		 3861 }
3862 if (status != 0) {
3863 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
e3fd5534 3864 goto abort_with_enabled;
0da34b6d 3865 }
6a35528a 3866 (void)pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
b10c0668
BG		 3867 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3868 &mgp->cmd_bus, GFP_KERNEL);
0da34b6d 3869 if (mgp->cmd == NULL)
e3fd5534 3870 goto abort_with_enabled;
0da34b6d 3871
0da34b6d
BG		 3872 mgp->board_span = pci_resource_len(pdev, 0);
3873 mgp->iomem_base = pci_resource_start(pdev, 0);
3874 mgp->mtrr = -1;
276e26c3 3875 mgp->wc_enabled = 0;
0da34b6d
BG		 3876#ifdef CONFIG_MTRR
3877 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3878 MTRR_TYPE_WRCOMB, 1);
276e26c3
BG		 3879 if (mgp->mtrr >= 0)
3880 mgp->wc_enabled = 1;
0da34b6d 3881#endif
c7f80993 3882 mgp->sram = ioremap_wc(mgp->iomem_base, mgp->board_span);
0da34b6d
BG		 3883 if (mgp->sram == NULL) {
3884 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3885 mgp->board_span, mgp->iomem_base);
3886 status = -ENXIO;
c7f80993 3887 goto abort_with_mtrr;
0da34b6d 3888 }
00b5e505
BG		 3889 hdr_offset =
3890 ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET)) & 0xffffc;
3891 ss_offset = hdr_offset + offsetof(struct mcp_gen_header, string_specs);
3892 mgp->sram_size = ntohl(__raw_readl(mgp->sram + ss_offset));
3893 if (mgp->sram_size > mgp->board_span ||
3894 mgp->sram_size <= MYRI10GE_FW_OFFSET) {
3895 dev_err(&pdev->dev,
3896 "invalid sram_size %dB or board span %ldB\n",
3897 mgp->sram_size, mgp->board_span);
3898 goto abort_with_ioremap;
3899 }
0da34b6d 3900 memcpy_fromio(mgp->eeprom_strings,
00b5e505 3901 mgp->sram + mgp->sram_size, MYRI10GE_EEPROM_STRINGS_SIZE);
0da34b6d
BG		 3902 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3903 status = myri10ge_read_mac_addr(mgp);
3904 if (status)
3905 goto abort_with_ioremap;
3906
3907 for (i = 0; i < ETH_ALEN; i++)
3908 netdev->dev_addr[i] = mgp->mac_addr[i];
3909
5443e9ea
BG		 3910 myri10ge_select_firmware(mgp);
3911
0dcffac1 3912 status = myri10ge_load_firmware(mgp, 1);
0da34b6d
BG		 3913 if (status != 0) {
3914 dev_err(&pdev->dev, "failed to load firmware\n");
0dcffac1
BG		 3915 goto abort_with_ioremap;
3916 }
3917 myri10ge_probe_slices(mgp);
3918 status = myri10ge_alloc_slices(mgp);
3919 if (status != 0) {
3920 dev_err(&pdev->dev, "failed to alloc slice state\n");
3921 goto abort_with_firmware;
0da34b6d 3922 }
236bb5e6 3923 netdev->real_num_tx_queues = mgp->num_slices;
0da34b6d
BG		 3924 status = myri10ge_reset(mgp);
3925 if (status != 0) {
3926 dev_err(&pdev->dev, "failed reset\n");
0dcffac1 3927 goto abort_with_slices;
0da34b6d 3928 }
5dd2d332 3929#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 3930 myri10ge_setup_dca(mgp);
3931#endif
0da34b6d
BG		 3932 pci_set_drvdata(pdev, mgp);
3933 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3934 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3935 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3936 myri10ge_initial_mtu = 68;
8126089f
SH		 3937
3938 netdev->netdev_ops = &myri10ge_netdev_ops;
0da34b6d 3939 netdev->mtu = myri10ge_initial_mtu;
0da34b6d 3940 netdev->base_addr = mgp->iomem_base;
4f93fde0 3941 netdev->features = mgp->features;
236bb5e6 3942
0da34b6d
BG		 3943 if (dac_enabled)
3944 netdev->features |= NETIF_F_HIGHDMA;
2552c31b 3945 netdev->features |= NETIF_F_LRO;
0da34b6d 3946
dddc045e
BG		 3947 netdev->vlan_features |= mgp->features;
3948 if (mgp->fw_ver_tiny < 37)
3949 netdev->vlan_features &= ~NETIF_F_TSO6;
3950 if (mgp->fw_ver_tiny < 32)
3951 netdev->vlan_features &= ~NETIF_F_TSO;
3952
21d05db1
BG		 3953 /* make sure we can get an irq, and that MSI can be
3954 * setup (if available). Also ensure netdev->irq
3955 * is set to correct value if MSI is enabled */
3956 status = myri10ge_request_irq(mgp);
3957 if (status != 0)
3958 goto abort_with_firmware;
3959 netdev->irq = pdev->irq;
3960 myri10ge_free_irq(mgp);
3961
0da34b6d
BG		 3962 /* Save configuration space to be restored if the
3963 * nic resets due to a parity error */
83f6e152 3964 pci_save_state(pdev);
0da34b6d
BG		 3965
3966 /* Setup the watchdog timer */
3967 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3968 (unsigned long)mgp);
3969
59081825 3970 spin_lock_init(&mgp->stats_lock);
0da34b6d 3971 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
c4028958 3972 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
0da34b6d
BG		 3973 status = register_netdev(netdev);
3974 if (status != 0) {
3975 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
7adda30c 3976 goto abort_with_state;
0da34b6d 3977 }
0dcffac1
BG		 3978 if (mgp->msix_enabled)
3979 dev_info(dev, "%d MSI-X IRQs, tx bndry %d, fw %s, WC %s\n",
3980 mgp->num_slices, mgp->tx_boundary, mgp->fw_name,
3981 (mgp->wc_enabled ? "Enabled" : "Disabled"));
3982 else
3983 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3984 mgp->msi_enabled ? "MSI" : "xPIC",
3985 netdev->irq, mgp->tx_boundary, mgp->fw_name,
3986 (mgp->wc_enabled ? "Enabled" : "Disabled"));
0da34b6d 3987
2d90b0aa 3988 board_number++;
0da34b6d
BG		 3989 return 0;
3990
7adda30c 3991abort_with_state:
83f6e152 3992 pci_restore_state(pdev);
0da34b6d 3993
0dcffac1
BG		 3994abort_with_slices:
3995 myri10ge_free_slices(mgp);
3996
0da34b6d
BG		 3997abort_with_firmware:
3998 myri10ge_dummy_rdma(mgp, 0);
3999
0da34b6d 4000abort_with_ioremap:
0f840011
BG		 4001 if (mgp->mac_addr_string != NULL)
4002 dev_err(&pdev->dev,
4003 "myri10ge_probe() failed: MAC=%s, SN=%ld\n",
4004 mgp->mac_addr_string, mgp->serial_number);
0da34b6d
BG		 4005 iounmap(mgp->sram);
4006
c7f80993 4007abort_with_mtrr:
0da34b6d
BG		 4008#ifdef CONFIG_MTRR
4009 if (mgp->mtrr >= 0)
4010 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
4011#endif
b10c0668
BG		 4012 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
4013 mgp->cmd, mgp->cmd_bus);
0da34b6d 4014
e3fd5534
BG		 4015abort_with_enabled:
4016 pci_disable_device(pdev);
0da34b6d 4017
e3fd5534 4018abort_with_netdev:
0da34b6d
BG		 4019 free_netdev(netdev);
4020 return status;
4021}
4022
4023/*
4024 * myri10ge_remove
4025 *
4026 * Does what is necessary to shutdown one Myrinet device. Called
4027 * once for each Myrinet card by the kernel when a module is
4028 * unloaded.
4029 */
4030static void myri10ge_remove(struct pci_dev *pdev)
4031{
4032 struct myri10ge_priv *mgp;
4033 struct net_device *netdev;
0da34b6d
BG		 4034
4035 mgp = pci_get_drvdata(pdev);
4036 if (mgp == NULL)
4037 return;
4038
4039 flush_scheduled_work();
4040 netdev = mgp->dev;
4041 unregister_netdev(netdev);
0da34b6d 4042
5dd2d332 4043#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4044 myri10ge_teardown_dca(mgp);
4045#endif
0da34b6d
BG		 4046 myri10ge_dummy_rdma(mgp, 0);
4047
7adda30c 4048 /* avoid a memory leak */
83f6e152 4049 pci_restore_state(pdev);
7adda30c 4050
0da34b6d
BG		 4051 iounmap(mgp->sram);
4052
4053#ifdef CONFIG_MTRR
4054 if (mgp->mtrr >= 0)
4055 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
4056#endif
0dcffac1
BG		 4057 myri10ge_free_slices(mgp);
4058 if (mgp->msix_vectors != NULL)
4059 kfree(mgp->msix_vectors);
b10c0668
BG		 4060 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
4061 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 4062
4063 free_netdev(netdev);
e3fd5534 4064 pci_disable_device(pdev);
0da34b6d
BG		 4065 pci_set_drvdata(pdev, NULL);
4066}
4067
b10c0668 4068#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
a07bc1ff 4069#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
0da34b6d
BG		 4070
4071static struct pci_device_id myri10ge_pci_tbl[] = {
b10c0668 4072 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
a07bc1ff
BG		 4073 {PCI_DEVICE
4074 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
0da34b6d
BG		 4075 {0},
4076};
4077
97131079
BG		 4078MODULE_DEVICE_TABLE(pci, myri10ge_pci_tbl);
4079
0da34b6d
BG		 4080static struct pci_driver myri10ge_driver = {
4081 .name = "myri10ge",
4082 .probe = myri10ge_probe,
4083 .remove = myri10ge_remove,
4084 .id_table = myri10ge_pci_tbl,
4085#ifdef CONFIG_PM
4086 .suspend = myri10ge_suspend,
4087 .resume = myri10ge_resume,
4088#endif
4089};
4090
5dd2d332 4091#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4092static int
4093myri10ge_notify_dca(struct notifier_block *nb, unsigned long event, void *p)
4094{
4095 int err = driver_for_each_device(&myri10ge_driver.driver,
4096 NULL, &event,
4097 myri10ge_notify_dca_device);
4098
4099 if (err)
4100 return NOTIFY_BAD;
4101 return NOTIFY_DONE;
4102}
4103
4104static struct notifier_block myri10ge_dca_notifier = {
4105 .notifier_call = myri10ge_notify_dca,
4106 .next = NULL,
4107 .priority = 0,
4108};
4ee2ac51 4109#endif /* CONFIG_MYRI10GE_DCA */
981813d8 4110
0da34b6d
BG		 4111static __init int myri10ge_init_module(void)
4112{
4113 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
4114 MYRI10GE_VERSION_STR);
0dcffac1 4115
236bb5e6 4116 if (myri10ge_rss_hash > MXGEFW_RSS_HASH_TYPE_MAX) {
0dcffac1
BG		 4117 printk(KERN_ERR
4118 "%s: Illegal rssh hash type %d, defaulting to source port\n",
4119 myri10ge_driver.name, myri10ge_rss_hash);
4120 myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
4121 }
5dd2d332 4122#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4123 dca_register_notify(&myri10ge_dca_notifier);
4124#endif
236bb5e6
BG		 4125 if (myri10ge_max_slices > MYRI10GE_MAX_SLICES)
4126 myri10ge_max_slices = MYRI10GE_MAX_SLICES;
0dcffac1 4127
0da34b6d
BG		 4128 return pci_register_driver(&myri10ge_driver);
4129}
4130
4131module_init(myri10ge_init_module);
4132
4133static __exit void myri10ge_cleanup_module(void)
4134{
5dd2d332 4135#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4136 dca_unregister_notify(&myri10ge_dca_notifier);
4137#endif
0da34b6d
BG		 4138 pci_unregister_driver(&myri10ge_driver);
4139}
4140
4141module_exit(myri10ge_cleanup_module);
Linux kernel - Deliverables
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