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Merge branch 'batman-adv/next' of git://git.open-mesh.org/ecsv/linux-merge
[deliverable/linux.git] / drivers / net / myri10ge / myri10ge.c
CommitLineData
0da34b6d
BG		 1/*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
e3fd5534 4 * Copyright (C) 2005 - 2009 Myricom, Inc.
0da34b6d
BG		 5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
4a2e612a
BG		 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0da34b6d 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4a2e612a
BG		 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
0da34b6d
BG		 30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
78ca90ea
JP		 41#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
42
0da34b6d
BG		 43#include <linux/tcp.h>
44#include <linux/netdevice.h>
45#include <linux/skbuff.h>
46#include <linux/string.h>
47#include <linux/module.h>
48#include <linux/pci.h>
b10c0668 49#include <linux/dma-mapping.h>
0da34b6d
BG		 50#include <linux/etherdevice.h>
51#include <linux/if_ether.h>
52#include <linux/if_vlan.h>
1e6e9342 53#include <linux/inet_lro.h>
981813d8 54#include <linux/dca.h>
0da34b6d
BG		 55#include <linux/ip.h>
56#include <linux/inet.h>
57#include <linux/in.h>
58#include <linux/ethtool.h>
59#include <linux/firmware.h>
60#include <linux/delay.h>
0da34b6d
BG		 61#include <linux/timer.h>
62#include <linux/vmalloc.h>
63#include <linux/crc32.h>
64#include <linux/moduleparam.h>
65#include <linux/io.h>
199126a2 66#include <linux/log2.h>
5a0e3ad6 67#include <linux/slab.h>
70c71606 68#include <linux/prefetch.h>
0da34b6d 69#include <net/checksum.h>
1e6e9342
AG		 70#include <net/ip.h>
71#include <net/tcp.h>
0da34b6d
BG		 72#include <asm/byteorder.h>
73#include <asm/io.h>
0da34b6d
BG		 74#include <asm/processor.h>
75#ifdef CONFIG_MTRR
76#include <asm/mtrr.h>
77#endif
78
79#include "myri10ge_mcp.h"
80#include "myri10ge_mcp_gen_header.h"
81
2a3f2790 82#define MYRI10GE_VERSION_STR "1.5.2-1.459"
0da34b6d
BG		 83
84MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
85MODULE_AUTHOR("Maintainer: help@myri.com");
86MODULE_VERSION(MYRI10GE_VERSION_STR);
87MODULE_LICENSE("Dual BSD/GPL");
88
89#define MYRI10GE_MAX_ETHER_MTU 9014
90
91#define MYRI10GE_ETH_STOPPED 0
92#define MYRI10GE_ETH_STOPPING 1
93#define MYRI10GE_ETH_STARTING 2
94#define MYRI10GE_ETH_RUNNING 3
95#define MYRI10GE_ETH_OPEN_FAILED 4
96
97#define MYRI10GE_EEPROM_STRINGS_SIZE 256
98#define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
1e6e9342
AG		 99#define MYRI10GE_MAX_LRO_DESCRIPTORS 8
100#define MYRI10GE_LRO_MAX_PKTS 64
0da34b6d 101
40f6cff5 102#define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
0da34b6d
BG		 103#define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
104
dd50f336
BG		 105#define MYRI10GE_ALLOC_ORDER 0
106#define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
107#define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
108
236bb5e6
BG		 109#define MYRI10GE_MAX_SLICES 32
110
0da34b6d 111struct myri10ge_rx_buffer_state {
dd50f336
BG		 112 struct page *page;
113 int page_offset;
c755b4b6
FT		 114 DEFINE_DMA_UNMAP_ADDR(bus);
115 DEFINE_DMA_UNMAP_LEN(len);
0da34b6d
BG		 116};
117
118struct myri10ge_tx_buffer_state {
119 struct sk_buff *skb;
120 int last;
c755b4b6
FT		 121 DEFINE_DMA_UNMAP_ADDR(bus);
122 DEFINE_DMA_UNMAP_LEN(len);
0da34b6d
BG		 123};
124
125struct myri10ge_cmd {
126 u32 data0;
127 u32 data1;
128 u32 data2;
129};
130
131struct myri10ge_rx_buf {
132 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
0da34b6d
BG		 133 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
134 struct myri10ge_rx_buffer_state *info;
dd50f336
BG		 135 struct page *page;
136 dma_addr_t bus;
137 int page_offset;
0da34b6d 138 int cnt;
dd50f336 139 int fill_cnt;
0da34b6d
BG		 140 int alloc_fail;
141 int mask; /* number of rx slots -1 */
dd50f336 142 int watchdog_needed;
0da34b6d
BG		 143};
144
145struct myri10ge_tx_buf {
146 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
236bb5e6
BG		 147 __be32 __iomem *send_go; /* "go" doorbell ptr */
148 __be32 __iomem *send_stop; /* "stop" doorbell ptr */
0da34b6d
BG		 149 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
150 char *req_bytes;
151 struct myri10ge_tx_buffer_state *info;
152 int mask; /* number of transmit slots -1 */
0da34b6d
BG		 153 int req ____cacheline_aligned; /* transmit slots submitted */
154 int pkt_start; /* packets started */
b53bef84
BG		 155 int stop_queue;
156 int linearized;
0da34b6d
BG		 157 int done ____cacheline_aligned; /* transmit slots completed */
158 int pkt_done; /* packets completed */
b53bef84 159 int wake_queue;
236bb5e6 160 int queue_active;
0da34b6d
BG		 161};
162
163struct myri10ge_rx_done {
164 struct mcp_slot *entry;
165 dma_addr_t bus;
166 int cnt;
167 int idx;
1e6e9342
AG		 168 struct net_lro_mgr lro_mgr;
169 struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
0da34b6d
BG		 170};
171
b53bef84
BG		 172struct myri10ge_slice_netstats {
173 unsigned long rx_packets;
174 unsigned long tx_packets;
175 unsigned long rx_bytes;
176 unsigned long tx_bytes;
177 unsigned long rx_dropped;
178 unsigned long tx_dropped;
179};
180
181struct myri10ge_slice_state {
0da34b6d
BG		 182 struct myri10ge_tx_buf tx; /* transmit ring */
183 struct myri10ge_rx_buf rx_small;
184 struct myri10ge_rx_buf rx_big;
185 struct myri10ge_rx_done rx_done;
b53bef84
BG		 186 struct net_device *dev;
187 struct napi_struct napi;
188 struct myri10ge_priv *mgp;
189 struct myri10ge_slice_netstats stats;
190 __be32 __iomem *irq_claim;
191 struct mcp_irq_data *fw_stats;
192 dma_addr_t fw_stats_bus;
193 int watchdog_tx_done;
194 int watchdog_tx_req;
d0234215 195 int watchdog_rx_done;
5dd2d332 196#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 197 int cached_dca_tag;
198 int cpu;
199 __be32 __iomem *dca_tag;
200#endif
0dcffac1 201 char irq_desc[32];
b53bef84
BG		 202};
203
204struct myri10ge_priv {
0dcffac1 205 struct myri10ge_slice_state *ss;
b53bef84 206 int tx_boundary; /* boundary transmits cannot cross */
0dcffac1 207 int num_slices;
b53bef84 208 int running; /* running? */
0da34b6d 209 int small_bytes;
dd50f336 210 int big_bytes;
fa0a90d9 211 int max_intr_slots;
0da34b6d 212 struct net_device *dev;
b53bef84 213 spinlock_t stats_lock;
0da34b6d
BG		 214 u8 __iomem *sram;
215 int sram_size;
216 unsigned long board_span;
217 unsigned long iomem_base;
40f6cff5 218 __be32 __iomem *irq_deassert;
0da34b6d
BG		 219 char *mac_addr_string;
220 struct mcp_cmd_response *cmd;
221 dma_addr_t cmd_bus;
0da34b6d
BG		 222 struct pci_dev *pdev;
223 int msi_enabled;
0dcffac1
BG		 224 int msix_enabled;
225 struct msix_entry *msix_vectors;
5dd2d332 226#ifdef CONFIG_MYRI10GE_DCA
981813d8 227 int dca_enabled;
ef09aadf 228 int relaxed_order;
981813d8 229#endif
66341fff 230 u32 link_state;
0da34b6d
BG		 231 unsigned int rdma_tags_available;
232 int intr_coal_delay;
40f6cff5 233 __be32 __iomem *intr_coal_delay_ptr;
0da34b6d 234 int mtrr;
276e26c3 235 int wc_enabled;
0da34b6d
BG		 236 int down_cnt;
237 wait_queue_head_t down_wq;
238 struct work_struct watchdog_work;
239 struct timer_list watchdog_timer;
0da34b6d 240 int watchdog_resets;
b53bef84 241 int watchdog_pause;
0da34b6d 242 int pause;
7d351035 243 bool fw_name_allocated;
0da34b6d
BG		 244 char *fw_name;
245 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
c0bf8801 246 char *product_code_string;
0da34b6d 247 char fw_version[128];
9dc6f0e7
BG		 248 int fw_ver_major;
249 int fw_ver_minor;
250 int fw_ver_tiny;
251 int adopted_rx_filter_bug;
0da34b6d
BG		 252 u8 mac_addr[6]; /* eeprom mac address */
253 unsigned long serial_number;
254 int vendor_specific_offset;
85a7ea1b 255 int fw_multicast_support;
04ed3e74 256 u32 features;
4f93fde0 257 u32 max_tso6;
0da34b6d
BG		 258 u32 read_dma;
259 u32 write_dma;
260 u32 read_write_dma;
c58ac5ca
BG		 261 u32 link_changes;
262 u32 msg_enable;
2d90b0aa 263 unsigned int board_number;
d0234215 264 int rebooted;
0da34b6d
BG		 265};
266
267static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
268static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
0dcffac1
BG		 269static char *myri10ge_fw_rss_unaligned = "myri10ge_rss_ethp_z8e.dat";
270static char *myri10ge_fw_rss_aligned = "myri10ge_rss_eth_z8e.dat";
b9721d5a
BH		 271MODULE_FIRMWARE("myri10ge_ethp_z8e.dat");
272MODULE_FIRMWARE("myri10ge_eth_z8e.dat");
273MODULE_FIRMWARE("myri10ge_rss_ethp_z8e.dat");
274MODULE_FIRMWARE("myri10ge_rss_eth_z8e.dat");
0da34b6d 275
7d351035 276/* Careful: must be accessed under kparam_block_sysfs_write */
0da34b6d
BG		 277static char *myri10ge_fw_name = NULL;
278module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
d1ce3a0f 279MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
0da34b6d 280
2d90b0aa
BG		 281#define MYRI10GE_MAX_BOARDS 8
282static char *myri10ge_fw_names[MYRI10GE_MAX_BOARDS] =
7fe624f5 283 {[0 ... (MYRI10GE_MAX_BOARDS - 1)] = NULL };
2d90b0aa
BG		 284module_param_array_named(myri10ge_fw_names, myri10ge_fw_names, charp, NULL,
285 0444);
286MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image names per board");
287
0da34b6d
BG		 288static int myri10ge_ecrc_enable = 1;
289module_param(myri10ge_ecrc_enable, int, S_IRUGO);
d1ce3a0f 290MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
0da34b6d 291
0da34b6d
BG		 292static int myri10ge_small_bytes = -1; /* -1 == auto */
293module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
d1ce3a0f 294MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
0da34b6d
BG		 295
296static int myri10ge_msi = 1; /* enable msi by default */
3621cec5 297module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
d1ce3a0f 298MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
0da34b6d 299
f761fae1 300static int myri10ge_intr_coal_delay = 75;
0da34b6d 301module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
d1ce3a0f 302MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
0da34b6d
BG		 303
304static int myri10ge_flow_control = 1;
305module_param(myri10ge_flow_control, int, S_IRUGO);
d1ce3a0f 306MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
0da34b6d
BG		 307
308static int myri10ge_deassert_wait = 1;
309module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
310MODULE_PARM_DESC(myri10ge_deassert_wait,
d1ce3a0f 311 "Wait when deasserting legacy interrupts");
0da34b6d
BG		 312
313static int myri10ge_force_firmware = 0;
314module_param(myri10ge_force_firmware, int, S_IRUGO);
315MODULE_PARM_DESC(myri10ge_force_firmware,
d1ce3a0f 316 "Force firmware to assume aligned completions");
0da34b6d 317
0da34b6d
BG		 318static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
319module_param(myri10ge_initial_mtu, int, S_IRUGO);
d1ce3a0f 320MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
0da34b6d
BG		 321
322static int myri10ge_napi_weight = 64;
323module_param(myri10ge_napi_weight, int, S_IRUGO);
d1ce3a0f 324MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
0da34b6d
BG		 325
326static int myri10ge_watchdog_timeout = 1;
327module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
d1ce3a0f 328MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
0da34b6d
BG		 329
330static int myri10ge_max_irq_loops = 1048576;
331module_param(myri10ge_max_irq_loops, int, S_IRUGO);
332MODULE_PARM_DESC(myri10ge_max_irq_loops,
d1ce3a0f 333 "Set stuck legacy IRQ detection threshold");
0da34b6d 334
c58ac5ca
BG		 335#define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
336
337static int myri10ge_debug = -1; /* defaults above */
338module_param(myri10ge_debug, int, 0);
339MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
340
1e6e9342
AG		 341static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
342module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
d1ce3a0f
BG		 343MODULE_PARM_DESC(myri10ge_lro_max_pkts,
344 "Number of LRO packets to be aggregated");
1e6e9342 345
dd50f336
BG		 346static int myri10ge_fill_thresh = 256;
347module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
d1ce3a0f 348MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
dd50f336 349
f181137f
BG		 350static int myri10ge_reset_recover = 1;
351
0dcffac1
BG		 352static int myri10ge_max_slices = 1;
353module_param(myri10ge_max_slices, int, S_IRUGO);
354MODULE_PARM_DESC(myri10ge_max_slices, "Max tx/rx queues");
355
4b860abf 356static int myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT;
0dcffac1
BG		 357module_param(myri10ge_rss_hash, int, S_IRUGO);
358MODULE_PARM_DESC(myri10ge_rss_hash, "Type of RSS hashing to do");
359
981813d8
BG		 360static int myri10ge_dca = 1;
361module_param(myri10ge_dca, int, S_IRUGO);
362MODULE_PARM_DESC(myri10ge_dca, "Enable DCA if possible");
363
0da34b6d
BG		 364#define MYRI10GE_FW_OFFSET 1024*1024
365#define MYRI10GE_HIGHPART_TO_U32(X) \
366(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
367#define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
368
369#define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
370
2f76216f 371static void myri10ge_set_multicast_list(struct net_device *dev);
61357325
SH		 372static netdev_tx_t myri10ge_sw_tso(struct sk_buff *skb,
373 struct net_device *dev);
2f76216f 374
6250223e 375static inline void put_be32(__be32 val, __be32 __iomem * p)
40f6cff5 376{
6250223e 377 __raw_writel((__force __u32) val, (__force void __iomem *)p);
40f6cff5
AV		 378}
379
c5f7ef72 380static struct rtnl_link_stats64 *myri10ge_get_stats(struct net_device *dev,
381 struct rtnl_link_stats64 *stats);
59081825 382
7d351035
RR		 383static void set_fw_name(struct myri10ge_priv *mgp, char *name, bool allocated)
384{
385 if (mgp->fw_name_allocated)
386 kfree(mgp->fw_name);
387 mgp->fw_name = name;
388 mgp->fw_name_allocated = allocated;
389}
390
0da34b6d
BG		 391static int
392myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
393 struct myri10ge_cmd *data, int atomic)
394{
395 struct mcp_cmd *buf;
396 char buf_bytes[sizeof(*buf) + 8];
397 struct mcp_cmd_response *response = mgp->cmd;
e700f9f4 398 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
0da34b6d
BG		 399 u32 dma_low, dma_high, result, value;
400 int sleep_total = 0;
401
402 /* ensure buf is aligned to 8 bytes */
403 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
404
405 buf->data0 = htonl(data->data0);
406 buf->data1 = htonl(data->data1);
407 buf->data2 = htonl(data->data2);
408 buf->cmd = htonl(cmd);
409 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
410 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
411
412 buf->response_addr.low = htonl(dma_low);
413 buf->response_addr.high = htonl(dma_high);
40f6cff5 414 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 415 mb();
416 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
417
418 /* wait up to 15ms. Longest command is the DMA benchmark,
419 * which is capped at 5ms, but runs from a timeout handler
420 * that runs every 7.8ms. So a 15ms timeout leaves us with
421 * a 2.2ms margin
422 */
423 if (atomic) {
424 /* if atomic is set, do not sleep,
425 * and try to get the completion quickly
426 * (1ms will be enough for those commands) */
427 for (sleep_total = 0;
8e95a202
JP		 428 sleep_total < 1000 &&
429 response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
bd2db0cf 430 sleep_total += 10) {
0da34b6d 431 udelay(10);
bd2db0cf
BG		 432 mb();
433 }
0da34b6d
BG		 434 } else {
435 /* use msleep for most command */
436 for (sleep_total = 0;
8e95a202
JP		 437 sleep_total < 15 &&
438 response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 439 sleep_total++)
440 msleep(1);
441 }
442
443 result = ntohl(response->result);
444 value = ntohl(response->data);
445 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
446 if (result == 0) {
447 data->data0 = value;
448 return 0;
85a7ea1b
BG		 449 } else if (result == MXGEFW_CMD_UNKNOWN) {
450 return -ENOSYS;
5443e9ea
BG		 451 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
452 return -E2BIG;
236bb5e6
BG		 453 } else if (result == MXGEFW_CMD_ERROR_RANGE &&
454 cmd == MXGEFW_CMD_ENABLE_RSS_QUEUES &&
455 (data->
456 data1 & MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES) !=
457 0) {
458 return -ERANGE;
0da34b6d
BG		 459 } else {
460 dev_err(&mgp->pdev->dev,
461 "command %d failed, result = %d\n",
462 cmd, result);
463 return -ENXIO;
464 }
465 }
466
467 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
468 cmd, result);
469 return -EAGAIN;
470}
471
472/*
473 * The eeprom strings on the lanaiX have the format
474 * SN=x\0
475 * MAC=x:x:x:x:x:x\0
476 * PT:ddd mmm xx xx:xx:xx xx\0
477 * PV:ddd mmm xx xx:xx:xx xx\0
478 */
479static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
480{
481 char *ptr, *limit;
482 int i;
483
484 ptr = mgp->eeprom_strings;
485 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
486
487 while (*ptr != '\0' && ptr < limit) {
488 if (memcmp(ptr, "MAC=", 4) == 0) {
489 ptr += 4;
490 mgp->mac_addr_string = ptr;
491 for (i = 0; i < 6; i++) {
492 if ((ptr + 2) > limit)
493 goto abort;
494 mgp->mac_addr[i] =
495 simple_strtoul(ptr, &ptr, 16);
496 ptr += 1;
497 }
498 }
c0bf8801
BG		 499 if (memcmp(ptr, "PC=", 3) == 0) {
500 ptr += 3;
501 mgp->product_code_string = ptr;
502 }
0da34b6d
BG		 503 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
504 ptr += 3;
505 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
506 }
507 while (ptr < limit && *ptr++) ;
508 }
509
510 return 0;
511
512abort:
513 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
514 return -ENXIO;
515}
516
517/*
518 * Enable or disable periodic RDMAs from the host to make certain
519 * chipsets resend dropped PCIe messages
520 */
521
522static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
523{
524 char __iomem *submit;
f8fd57c1 525 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 526 u32 dma_low, dma_high;
527 int i;
528
529 /* clear confirmation addr */
530 mgp->cmd->data = 0;
531 mb();
532
533 /* send a rdma command to the PCIe engine, and wait for the
534 * response in the confirmation address. The firmware should
535 * write a -1 there to indicate it is alive and well
536 */
537 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
538 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
539
540 buf[0] = htonl(dma_high); /* confirm addr MSW */
541 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 542 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 543 buf[3] = htonl(dma_high); /* dummy addr MSW */
544 buf[4] = htonl(dma_low); /* dummy addr LSW */
545 buf[5] = htonl(enable); /* enable? */
546
e700f9f4 547 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
0da34b6d
BG		 548
549 myri10ge_pio_copy(submit, &buf, sizeof(buf));
550 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
551 msleep(1);
552 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
553 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
554 (enable ? "enable" : "disable"));
555}
556
557static int
558myri10ge_validate_firmware(struct myri10ge_priv *mgp,
559 struct mcp_gen_header *hdr)
560{
561 struct device *dev = &mgp->pdev->dev;
0da34b6d
BG		 562
563 /* check firmware type */
564 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
565 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
566 return -EINVAL;
567 }
568
569 /* save firmware version for ethtool */
570 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
571
9dc6f0e7
BG		 572 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
573 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
0da34b6d 574
8e95a202
JP		 575 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR &&
576 mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
0da34b6d
BG		 577 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
578 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
579 MXGEFW_VERSION_MINOR);
580 return -EINVAL;
581 }
582 return 0;
583}
584
585static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
586{
587 unsigned crc, reread_crc;
588 const struct firmware *fw;
589 struct device *dev = &mgp->pdev->dev;
b0d31d6b 590 unsigned char *fw_readback;
0da34b6d
BG		 591 struct mcp_gen_header *hdr;
592 size_t hdr_offset;
593 int status;
e454358a 594 unsigned i;
0da34b6d
BG		 595
596 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
597 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
598 mgp->fw_name);
599 status = -EINVAL;
600 goto abort_with_nothing;
601 }
602
603 /* check size */
604
605 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
606 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
607 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
608 status = -EINVAL;
609 goto abort_with_fw;
610 }
611
612 /* check id */
40f6cff5 613 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 614 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
615 dev_err(dev, "Bad firmware file\n");
616 status = -EINVAL;
617 goto abort_with_fw;
618 }
619 hdr = (void *)(fw->data + hdr_offset);
620
621 status = myri10ge_validate_firmware(mgp, hdr);
622 if (status != 0)
623 goto abort_with_fw;
624
625 crc = crc32(~0, fw->data, fw->size);
e454358a
BG		 626 for (i = 0; i < fw->size; i += 256) {
627 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
628 fw->data + i,
629 min(256U, (unsigned)(fw->size - i)));
630 mb();
631 readb(mgp->sram);
b10c0668 632 }
b0d31d6b
DW		 633 fw_readback = vmalloc(fw->size);
634 if (!fw_readback) {
635 status = -ENOMEM;
636 goto abort_with_fw;
637 }
0da34b6d 638 /* corruption checking is good for parity recovery and buggy chipset */
b0d31d6b
DW		 639 memcpy_fromio(fw_readback, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
640 reread_crc = crc32(~0, fw_readback, fw->size);
641 vfree(fw_readback);
0da34b6d
BG		 642 if (crc != reread_crc) {
643 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
644 (unsigned)fw->size, reread_crc, crc);
645 status = -EIO;
646 goto abort_with_fw;
647 }
648 *size = (u32) fw->size;
649
650abort_with_fw:
651 release_firmware(fw);
652
653abort_with_nothing:
654 return status;
655}
656
657static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
658{
659 struct mcp_gen_header *hdr;
660 struct device *dev = &mgp->pdev->dev;
661 const size_t bytes = sizeof(struct mcp_gen_header);
662 size_t hdr_offset;
663 int status;
664
665 /* find running firmware header */
66341fff 666 hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 667
668 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
669 dev_err(dev, "Running firmware has bad header offset (%d)\n",
670 (int)hdr_offset);
671 return -EIO;
672 }
673
674 /* copy header of running firmware from SRAM to host memory to
675 * validate firmware */
676 hdr = kmalloc(bytes, GFP_KERNEL);
677 if (hdr == NULL) {
678 dev_err(dev, "could not malloc firmware hdr\n");
679 return -ENOMEM;
680 }
681 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
682 status = myri10ge_validate_firmware(mgp, hdr);
683 kfree(hdr);
9dc6f0e7
BG		 684
685 /* check to see if adopted firmware has bug where adopting
686 * it will cause broadcasts to be filtered unless the NIC
687 * is kept in ALLMULTI mode */
688 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
689 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
690 mgp->adopted_rx_filter_bug = 1;
691 dev_warn(dev, "Adopting fw %d.%d.%d: "
692 "working around rx filter bug\n",
693 mgp->fw_ver_major, mgp->fw_ver_minor,
694 mgp->fw_ver_tiny);
695 }
0da34b6d
BG		 696 return status;
697}
698
0178ec3d 699static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
fa0a90d9
BG		 700{
701 struct myri10ge_cmd cmd;
702 int status;
703
704 /* probe for IPv6 TSO support */
705 mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
706 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
707 &cmd, 0);
708 if (status == 0) {
709 mgp->max_tso6 = cmd.data0;
710 mgp->features |= NETIF_F_TSO6;
711 }
712
713 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
714 if (status != 0) {
715 dev_err(&mgp->pdev->dev,
716 "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
717 return -ENXIO;
718 }
719
720 mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
721
722 return 0;
723}
724
0dcffac1 725static int myri10ge_load_firmware(struct myri10ge_priv *mgp, int adopt)
0da34b6d
BG		 726{
727 char __iomem *submit;
f8fd57c1 728 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 729 u32 dma_low, dma_high, size;
730 int status, i;
731
b10c0668 732 size = 0;
0da34b6d
BG		 733 status = myri10ge_load_hotplug_firmware(mgp, &size);
734 if (status) {
0dcffac1
BG		 735 if (!adopt)
736 return status;
0da34b6d
BG		 737 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
738
739 /* Do not attempt to adopt firmware if there
740 * was a bad crc */
741 if (status == -EIO)
742 return status;
743
744 status = myri10ge_adopt_running_firmware(mgp);
745 if (status != 0) {
746 dev_err(&mgp->pdev->dev,
747 "failed to adopt running firmware\n");
748 return status;
749 }
750 dev_info(&mgp->pdev->dev,
751 "Successfully adopted running firmware\n");
b53bef84 752 if (mgp->tx_boundary == 4096) {
0da34b6d
BG		 753 dev_warn(&mgp->pdev->dev,
754 "Using firmware currently running on NIC"
755 ". For optimal\n");
756 dev_warn(&mgp->pdev->dev,
757 "performance consider loading optimized "
758 "firmware\n");
759 dev_warn(&mgp->pdev->dev, "via hotplug\n");
760 }
761
7d351035 762 set_fw_name(mgp, "adopted", false);
b53bef84 763 mgp->tx_boundary = 2048;
fa0a90d9
BG		 764 myri10ge_dummy_rdma(mgp, 1);
765 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d
BG		 766 return status;
767 }
768
769 /* clear confirmation addr */
770 mgp->cmd->data = 0;
771 mb();
772
773 /* send a reload command to the bootstrap MCP, and wait for the
774 * response in the confirmation address. The firmware should
775 * write a -1 there to indicate it is alive and well
776 */
777 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
778 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
779
780 buf[0] = htonl(dma_high); /* confirm addr MSW */
781 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 782 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 783
784 /* FIX: All newest firmware should un-protect the bottom of
785 * the sram before handoff. However, the very first interfaces
786 * do not. Therefore the handoff copy must skip the first 8 bytes
787 */
788 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
789 buf[4] = htonl(size - 8); /* length of code */
790 buf[5] = htonl(8); /* where to copy to */
791 buf[6] = htonl(0); /* where to jump to */
792
e700f9f4 793 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
0da34b6d
BG		 794
795 myri10ge_pio_copy(submit, &buf, sizeof(buf));
796 mb();
797 msleep(1);
798 mb();
799 i = 0;
d93ca2a4
BG		 800 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
801 msleep(1 << i);
0da34b6d
BG		 802 i++;
803 }
804 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
805 dev_err(&mgp->pdev->dev, "handoff failed\n");
806 return -ENXIO;
807 }
9a71db72 808 myri10ge_dummy_rdma(mgp, 1);
fa0a90d9 809 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d 810
fa0a90d9 811 return status;
0da34b6d
BG		 812}
813
814static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
815{
816 struct myri10ge_cmd cmd;
817 int status;
818
819 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
820 | (addr[2] << 8) | addr[3]);
821
822 cmd.data1 = ((addr[4] << 8) | (addr[5]));
823
824 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
825 return status;
826}
827
828static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
829{
830 struct myri10ge_cmd cmd;
831 int status, ctl;
832
833 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
834 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
835
836 if (status) {
78ca90ea 837 netdev_err(mgp->dev, "Failed to set flow control mode\n");
0da34b6d
BG		 838 return status;
839 }
840 mgp->pause = pause;
841 return 0;
842}
843
844static void
845myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
846{
847 struct myri10ge_cmd cmd;
848 int status, ctl;
849
850 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
851 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
852 if (status)
78ca90ea 853 netdev_err(mgp->dev, "Failed to set promisc mode\n");
0da34b6d
BG		 854}
855
0d6ac257 856static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
0da34b6d
BG		 857{
858 struct myri10ge_cmd cmd;
859 int status;
0da34b6d 860 u32 len;
34fdccea
BG		 861 struct page *dmatest_page;
862 dma_addr_t dmatest_bus;
0d6ac257
BG		 863 char *test = " ";
864
865 dmatest_page = alloc_page(GFP_KERNEL);
866 if (!dmatest_page)
867 return -ENOMEM;
868 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
869 DMA_BIDIRECTIONAL);
870
871 /* Run a small DMA test.
872 * The magic multipliers to the length tell the firmware
873 * to do DMA read, write, or read+write tests. The
874 * results are returned in cmd.data0. The upper 16
875 * bits or the return is the number of transfers completed.
876 * The lower 16 bits is the time in 0.5us ticks that the
877 * transfers took to complete.
878 */
879
b53bef84 880 len = mgp->tx_boundary;
0d6ac257
BG		 881
882 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
883 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
884 cmd.data2 = len * 0x10000;
885 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
886 if (status != 0) {
887 test = "read";
888 goto abort;
889 }
890 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
891 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
892 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
893 cmd.data2 = len * 0x1;
894 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
895 if (status != 0) {
896 test = "write";
897 goto abort;
898 }
899 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
900
901 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
902 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
903 cmd.data2 = len * 0x10001;
904 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
905 if (status != 0) {
906 test = "read/write";
907 goto abort;
908 }
909 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
910 (cmd.data0 & 0xffff);
911
912abort:
913 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
914 put_page(dmatest_page);
915
916 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
917 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
918 test, status);
919
920 return status;
921}
922
923static int myri10ge_reset(struct myri10ge_priv *mgp)
924{
925 struct myri10ge_cmd cmd;
0dcffac1
BG		 926 struct myri10ge_slice_state *ss;
927 int i, status;
0d6ac257 928 size_t bytes;
5dd2d332 929#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 930 unsigned long dca_tag_off;
931#endif
0da34b6d
BG		 932
933 /* try to send a reset command to the card to see if it
934 * is alive */
935 memset(&cmd, 0, sizeof(cmd));
936 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
937 if (status != 0) {
938 dev_err(&mgp->pdev->dev, "failed reset\n");
939 return -ENXIO;
940 }
0d6ac257
BG		 941
942 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
0dcffac1
BG		 943 /*
944 * Use non-ndis mcp_slot (eg, 4 bytes total,
945 * no toeplitz hash value returned. Older firmware will
946 * not understand this command, but will use the correct
947 * sized mcp_slot, so we ignore error returns
948 */
949 cmd.data0 = MXGEFW_RSS_MCP_SLOT_TYPE_MIN;
950 (void)myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, &cmd, 0);
0da34b6d
BG		 951
952 /* Now exchange information about interrupts */
953
0dcffac1 954 bytes = mgp->max_intr_slots * sizeof(*mgp->ss[0].rx_done.entry);
0da34b6d
BG		 955 cmd.data0 = (u32) bytes;
956 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
0dcffac1
BG		 957
958 /*
959 * Even though we already know how many slices are supported
960 * via myri10ge_probe_slices() MXGEFW_CMD_GET_MAX_RSS_QUEUES
961 * has magic side effects, and must be called after a reset.
962 * It must be called prior to calling any RSS related cmds,
963 * including assigning an interrupt queue for anything but
964 * slice 0. It must also be called *after*
965 * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
966 * the firmware to compute offsets.
967 */
968
969 if (mgp->num_slices > 1) {
970
971 /* ask the maximum number of slices it supports */
972 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
973 &cmd, 0);
974 if (status != 0) {
975 dev_err(&mgp->pdev->dev,
976 "failed to get number of slices\n");
977 }
978
979 /*
980 * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
981 * to setting up the interrupt queue DMA
982 */
983
984 cmd.data0 = mgp->num_slices;
236bb5e6
BG		 985 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
986 if (mgp->dev->real_num_tx_queues > 1)
987 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
0dcffac1
BG		 988 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
989 &cmd, 0);
236bb5e6
BG		 990
991 /* Firmware older than 1.4.32 only supports multiple
992 * RX queues, so if we get an error, first retry using a
993 * single TX queue before giving up */
994 if (status != 0 && mgp->dev->real_num_tx_queues > 1) {
c9920268 995 netif_set_real_num_tx_queues(mgp->dev, 1);
236bb5e6
BG		 996 cmd.data0 = mgp->num_slices;
997 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
998 status = myri10ge_send_cmd(mgp,
999 MXGEFW_CMD_ENABLE_RSS_QUEUES,
1000 &cmd, 0);
1001 }
1002
0dcffac1
BG		 1003 if (status != 0) {
1004 dev_err(&mgp->pdev->dev,
1005 "failed to set number of slices\n");
1006
1007 return status;
1008 }
1009 }
1010 for (i = 0; i < mgp->num_slices; i++) {
1011 ss = &mgp->ss[i];
1012 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->rx_done.bus);
1013 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->rx_done.bus);
1014 cmd.data2 = i;
1015 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA,
1016 &cmd, 0);
6403eab1 1017 }
0da34b6d
BG		 1018
1019 status |=
1020 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
0dcffac1
BG		 1021 for (i = 0; i < mgp->num_slices; i++) {
1022 ss = &mgp->ss[i];
1023 ss->irq_claim =
1024 (__iomem __be32 *) (mgp->sram + cmd.data0 + 8 * i);
1025 }
df30a740
BG		 1026 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
1027 &cmd, 0);
1028 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d 1029
0da34b6d
BG		 1030 status |= myri10ge_send_cmd
1031 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
40f6cff5 1032 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d
BG		 1033 if (status != 0) {
1034 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
1035 return status;
1036 }
40f6cff5 1037 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d 1038
5dd2d332 1039#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1040 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_DCA_OFFSET, &cmd, 0);
1041 dca_tag_off = cmd.data0;
1042 for (i = 0; i < mgp->num_slices; i++) {
1043 ss = &mgp->ss[i];
1044 if (status == 0) {
1045 ss->dca_tag = (__iomem __be32 *)
1046 (mgp->sram + dca_tag_off + 4 * i);
1047 } else {
1048 ss->dca_tag = NULL;
1049 }
1050 }
4ee2ac51 1051#endif /* CONFIG_MYRI10GE_DCA */
981813d8 1052
0da34b6d 1053 /* reset mcp/driver shared state back to 0 */
0dcffac1 1054
c58ac5ca 1055 mgp->link_changes = 0;
0dcffac1
BG		 1056 for (i = 0; i < mgp->num_slices; i++) {
1057 ss = &mgp->ss[i];
1058
1059 memset(ss->rx_done.entry, 0, bytes);
1060 ss->tx.req = 0;
1061 ss->tx.done = 0;
1062 ss->tx.pkt_start = 0;
1063 ss->tx.pkt_done = 0;
1064 ss->rx_big.cnt = 0;
1065 ss->rx_small.cnt = 0;
1066 ss->rx_done.idx = 0;
1067 ss->rx_done.cnt = 0;
1068 ss->tx.wake_queue = 0;
1069 ss->tx.stop_queue = 0;
1070 }
1071
0da34b6d 1072 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
0da34b6d 1073 myri10ge_change_pause(mgp, mgp->pause);
2f76216f 1074 myri10ge_set_multicast_list(mgp->dev);
0da34b6d
BG		 1075 return status;
1076}
1077
5dd2d332 1078#ifdef CONFIG_MYRI10GE_DCA
ef09aadf
AG		 1079static int myri10ge_toggle_relaxed(struct pci_dev *pdev, int on)
1080{
1081 int ret, cap, err;
1082 u16 ctl;
1083
1084 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1085 if (!cap)
1086 return 0;
1087
1088 err = pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
1089 ret = (ctl & PCI_EXP_DEVCTL_RELAX_EN) >> 4;
1090 if (ret != on) {
1091 ctl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1092 ctl |= (on << 4);
1093 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
1094 }
1095 return ret;
1096}
1097
981813d8
BG		 1098static void
1099myri10ge_write_dca(struct myri10ge_slice_state *ss, int cpu, int tag)
1100{
981813d8
BG		 1101 ss->cached_dca_tag = tag;
1102 put_be32(htonl(tag), ss->dca_tag);
1103}
1104
1105static inline void myri10ge_update_dca(struct myri10ge_slice_state *ss)
1106{
1107 int cpu = get_cpu();
1108 int tag;
1109
1110 if (cpu != ss->cpu) {
ef09aadf 1111 tag = dca3_get_tag(&ss->mgp->pdev->dev, cpu);
981813d8
BG		 1112 if (ss->cached_dca_tag != tag)
1113 myri10ge_write_dca(ss, cpu, tag);
ef09aadf 1114 ss->cpu = cpu;
981813d8
BG		 1115 }
1116 put_cpu();
1117}
1118
1119static void myri10ge_setup_dca(struct myri10ge_priv *mgp)
1120{
1121 int err, i;
1122 struct pci_dev *pdev = mgp->pdev;
1123
1124 if (mgp->ss[0].dca_tag == NULL || mgp->dca_enabled)
1125 return;
1126 if (!myri10ge_dca) {
1127 dev_err(&pdev->dev, "dca disabled by administrator\n");
1128 return;
1129 }
1130 err = dca_add_requester(&pdev->dev);
1131 if (err) {
330554cb
BG		 1132 if (err != -ENODEV)
1133 dev_err(&pdev->dev,
1134 "dca_add_requester() failed, err=%d\n", err);
981813d8
BG		 1135 return;
1136 }
ef09aadf 1137 mgp->relaxed_order = myri10ge_toggle_relaxed(pdev, 0);
981813d8 1138 mgp->dca_enabled = 1;
ef09aadf
AG		 1139 for (i = 0; i < mgp->num_slices; i++) {
1140 mgp->ss[i].cpu = -1;
1141 mgp->ss[i].cached_dca_tag = -1;
1142 myri10ge_update_dca(&mgp->ss[i]);
1143 }
981813d8
BG		 1144}
1145
1146static void myri10ge_teardown_dca(struct myri10ge_priv *mgp)
1147{
1148 struct pci_dev *pdev = mgp->pdev;
1149 int err;
1150
1151 if (!mgp->dca_enabled)
1152 return;
1153 mgp->dca_enabled = 0;
ef09aadf
AG		 1154 if (mgp->relaxed_order)
1155 myri10ge_toggle_relaxed(pdev, 1);
981813d8
BG		 1156 err = dca_remove_requester(&pdev->dev);
1157}
1158
1159static int myri10ge_notify_dca_device(struct device *dev, void *data)
1160{
1161 struct myri10ge_priv *mgp;
1162 unsigned long event;
1163
1164 mgp = dev_get_drvdata(dev);
1165 event = *(unsigned long *)data;
1166
1167 if (event == DCA_PROVIDER_ADD)
1168 myri10ge_setup_dca(mgp);
1169 else if (event == DCA_PROVIDER_REMOVE)
1170 myri10ge_teardown_dca(mgp);
1171 return 0;
1172}
4ee2ac51 1173#endif /* CONFIG_MYRI10GE_DCA */
981813d8 1174
0da34b6d
BG		 1175static inline void
1176myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
1177 struct mcp_kreq_ether_recv *src)
1178{
40f6cff5 1179 __be32 low;
0da34b6d
BG		 1180
1181 low = src->addr_low;
284901a9 1182 src->addr_low = htonl(DMA_BIT_MASK(32));
e67bda55
BG		 1183 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
1184 mb();
1185 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
0da34b6d
BG		 1186 mb();
1187 src->addr_low = low;
40f6cff5 1188 put_be32(low, &dst->addr_low);
0da34b6d
BG		 1189 mb();
1190}
1191
40f6cff5 1192static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
0da34b6d
BG		 1193{
1194 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
1195
40f6cff5 1196 if ((skb->protocol == htons(ETH_P_8021Q)) &&
0da34b6d
BG		 1197 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
1198 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
1199 skb->csum = hw_csum;
84fa7933 1200 skb->ip_summed = CHECKSUM_COMPLETE;
0da34b6d
BG		 1201 }
1202}
1203
dd50f336
BG		 1204static inline void
1205myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
1206 struct skb_frag_struct *rx_frags, int len, int hlen)
1207{
1208 struct skb_frag_struct *skb_frags;
1209
1210 skb->len = skb->data_len = len;
1211 skb->truesize = len + sizeof(struct sk_buff);
1212 /* attach the page(s) */
1213
1214 skb_frags = skb_shinfo(skb)->frags;
1215 while (len > 0) {
1216 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
1217 len -= rx_frags->size;
1218 skb_frags++;
1219 rx_frags++;
1220 skb_shinfo(skb)->nr_frags++;
1221 }
1222
1223 /* pskb_may_pull is not available in irq context, but
1224 * skb_pull() (for ether_pad and eth_type_trans()) requires
1225 * the beginning of the packet in skb_headlen(), move it
1226 * manually */
27d7ff46 1227 skb_copy_to_linear_data(skb, va, hlen);
dd50f336
BG		 1228 skb_shinfo(skb)->frags[0].page_offset += hlen;
1229 skb_shinfo(skb)->frags[0].size -= hlen;
1230 skb->data_len -= hlen;
1231 skb->tail += hlen;
1232 skb_pull(skb, MXGEFW_PAD);
1233}
1234
1235static void
1236myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1237 int bytes, int watchdog)
1238{
1239 struct page *page;
1240 int idx;
2a3f2790
BG		 1241#if MYRI10GE_ALLOC_SIZE > 4096
1242 int end_offset;
1243#endif
dd50f336
BG		 1244
1245 if (unlikely(rx->watchdog_needed && !watchdog))
1246 return;
1247
1248 /* try to refill entire ring */
1249 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
1250 idx = rx->fill_cnt & rx->mask;
ae8509b1 1251 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
dd50f336
BG		 1252 /* we can use part of previous page */
1253 get_page(rx->page);
1254 } else {
1255 /* we need a new page */
1256 page =
1257 alloc_pages(GFP_ATOMIC | __GFP_COMP,
1258 MYRI10GE_ALLOC_ORDER);
1259 if (unlikely(page == NULL)) {
1260 if (rx->fill_cnt - rx->cnt < 16)
1261 rx->watchdog_needed = 1;
1262 return;
1263 }
1264 rx->page = page;
1265 rx->page_offset = 0;
1266 rx->bus = pci_map_page(mgp->pdev, page, 0,
1267 MYRI10GE_ALLOC_SIZE,
1268 PCI_DMA_FROMDEVICE);
1269 }
1270 rx->info[idx].page = rx->page;
1271 rx->info[idx].page_offset = rx->page_offset;
1272 /* note that this is the address of the start of the
1273 * page */
c755b4b6 1274 dma_unmap_addr_set(&rx->info[idx], bus, rx->bus);
dd50f336
BG		 1275 rx->shadow[idx].addr_low =
1276 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
1277 rx->shadow[idx].addr_high =
1278 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
1279
1280 /* start next packet on a cacheline boundary */
1281 rx->page_offset += SKB_DATA_ALIGN(bytes);
ae8509b1
BG		 1282
1283#if MYRI10GE_ALLOC_SIZE > 4096
1284 /* don't cross a 4KB boundary */
2a3f2790
BG		 1285 end_offset = rx->page_offset + bytes - 1;
1286 if ((unsigned)(rx->page_offset ^ end_offset) > 4095)
1287 rx->page_offset = end_offset & ~4095;
ae8509b1 1288#endif
dd50f336
BG		 1289 rx->fill_cnt++;
1290
1291 /* copy 8 descriptors to the firmware at a time */
1292 if ((idx & 7) == 7) {
e454e7e2
BG		 1293 myri10ge_submit_8rx(&rx->lanai[idx - 7],
1294 &rx->shadow[idx - 7]);
dd50f336
BG		 1295 }
1296 }
1297}
1298
1299static inline void
1300myri10ge_unmap_rx_page(struct pci_dev *pdev,
1301 struct myri10ge_rx_buffer_state *info, int bytes)
1302{
1303 /* unmap the recvd page if we're the only or last user of it */
1304 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1305 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
c755b4b6 1306 pci_unmap_page(pdev, (dma_unmap_addr(info, bus)
dd50f336
BG		 1307 & ~(MYRI10GE_ALLOC_SIZE - 1)),
1308 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1309 }
1310}
1311
1312#define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
1313 * page into an skb */
1314
1315static inline int
b3cd9657
SG		 1316myri10ge_rx_done(struct myri10ge_slice_state *ss, int len, __wsum csum,
1317 int lro_enabled)
dd50f336 1318{
b53bef84 1319 struct myri10ge_priv *mgp = ss->mgp;
dd50f336
BG		 1320 struct sk_buff *skb;
1321 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
b3cd9657
SG		 1322 struct myri10ge_rx_buf *rx;
1323 int i, idx, hlen, remainder, bytes;
dd50f336
BG		 1324 struct pci_dev *pdev = mgp->pdev;
1325 struct net_device *dev = mgp->dev;
1326 u8 *va;
1327
b3cd9657
SG		 1328 if (len <= mgp->small_bytes) {
1329 rx = &ss->rx_small;
1330 bytes = mgp->small_bytes;
1331 } else {
1332 rx = &ss->rx_big;
1333 bytes = mgp->big_bytes;
1334 }
1335
dd50f336
BG		 1336 len += MXGEFW_PAD;
1337 idx = rx->cnt & rx->mask;
1338 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1339 prefetch(va);
1340 /* Fill skb_frag_struct(s) with data from our receive */
1341 for (i = 0, remainder = len; remainder > 0; i++) {
1342 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1343 rx_frags[i].page = rx->info[idx].page;
1344 rx_frags[i].page_offset = rx->info[idx].page_offset;
1345 if (remainder < MYRI10GE_ALLOC_SIZE)
1346 rx_frags[i].size = remainder;
1347 else
1348 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1349 rx->cnt++;
1350 idx = rx->cnt & rx->mask;
1351 remainder -= MYRI10GE_ALLOC_SIZE;
1352 }
1353
b3cd9657 1354 if (lro_enabled) {
1e6e9342
AG		 1355 rx_frags[0].page_offset += MXGEFW_PAD;
1356 rx_frags[0].size -= MXGEFW_PAD;
1357 len -= MXGEFW_PAD;
b53bef84 1358 lro_receive_frags(&ss->rx_done.lro_mgr, rx_frags,
b53bef84 1359 /* opaque, will come back in get_frag_header */
0dcffac1 1360 len, len,
b53bef84 1361 (void *)(__force unsigned long)csum, csum);
0dcffac1 1362
1e6e9342
AG		 1363 return 1;
1364 }
1365
dd50f336
BG		 1366 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1367
e636b2ea
BG		 1368 /* allocate an skb to attach the page(s) to. This is done
1369 * after trying LRO, so as to avoid skb allocation overheads */
dd50f336
BG		 1370
1371 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1372 if (unlikely(skb == NULL)) {
d6279c88 1373 ss->stats.rx_dropped++;
dd50f336
BG		 1374 do {
1375 i--;
1376 put_page(rx_frags[i].page);
1377 } while (i != 0);
1378 return 0;
1379 }
1380
1381 /* Attach the pages to the skb, and trim off any padding */
1382 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1383 if (skb_shinfo(skb)->frags[0].size <= 0) {
1384 put_page(skb_shinfo(skb)->frags[0].page);
1385 skb_shinfo(skb)->nr_frags = 0;
1386 }
1387 skb->protocol = eth_type_trans(skb, dev);
0c8dfc83 1388 skb_record_rx_queue(skb, ss - &mgp->ss[0]);
dd50f336 1389
47c2cdf5 1390 if (dev->features & NETIF_F_RXCSUM) {
dd50f336
BG		 1391 if ((skb->protocol == htons(ETH_P_IP)) ||
1392 (skb->protocol == htons(ETH_P_IPV6))) {
1393 skb->csum = csum;
1394 skb->ip_summed = CHECKSUM_COMPLETE;
1395 } else
1396 myri10ge_vlan_ip_csum(skb, csum);
1397 }
1398 netif_receive_skb(skb);
dd50f336
BG		 1399 return 1;
1400}
1401
b53bef84
BG		 1402static inline void
1403myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index)
0da34b6d 1404{
b53bef84
BG		 1405 struct pci_dev *pdev = ss->mgp->pdev;
1406 struct myri10ge_tx_buf *tx = &ss->tx;
236bb5e6 1407 struct netdev_queue *dev_queue;
0da34b6d
BG		 1408 struct sk_buff *skb;
1409 int idx, len;
0da34b6d
BG		 1410
1411 while (tx->pkt_done != mcp_index) {
1412 idx = tx->done & tx->mask;
1413 skb = tx->info[idx].skb;
1414
1415 /* Mark as free */
1416 tx->info[idx].skb = NULL;
1417 if (tx->info[idx].last) {
1418 tx->pkt_done++;
1419 tx->info[idx].last = 0;
1420 }
1421 tx->done++;
c755b4b6
FT		 1422 len = dma_unmap_len(&tx->info[idx], len);
1423 dma_unmap_len_set(&tx->info[idx], len, 0);
0da34b6d 1424 if (skb) {
b53bef84
BG		 1425 ss->stats.tx_bytes += skb->len;
1426 ss->stats.tx_packets++;
0da34b6d
BG		 1427 dev_kfree_skb_irq(skb);
1428 if (len)
1429 pci_unmap_single(pdev,
c755b4b6 1430 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 1431 bus), len,
1432 PCI_DMA_TODEVICE);
1433 } else {
1434 if (len)
1435 pci_unmap_page(pdev,
c755b4b6 1436 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 1437 bus), len,
1438 PCI_DMA_TODEVICE);
1439 }
0da34b6d 1440 }
236bb5e6
BG		 1441
1442 dev_queue = netdev_get_tx_queue(ss->dev, ss - ss->mgp->ss);
1443 /*
1444 * Make a minimal effort to prevent the NIC from polling an
1445 * idle tx queue. If we can't get the lock we leave the queue
1446 * active. In this case, either a thread was about to start
1447 * using the queue anyway, or we lost a race and the NIC will
1448 * waste some of its resources polling an inactive queue for a
1449 * while.
1450 */
1451
1452 if ((ss->mgp->dev->real_num_tx_queues > 1) &&
1453 __netif_tx_trylock(dev_queue)) {
1454 if (tx->req == tx->done) {
1455 tx->queue_active = 0;
1456 put_be32(htonl(1), tx->send_stop);
8c2f5fa5 1457 mb();
6824a105 1458 mmiowb();
236bb5e6
BG		 1459 }
1460 __netif_tx_unlock(dev_queue);
1461 }
1462
0da34b6d 1463 /* start the queue if we've stopped it */
8e95a202
JP		 1464 if (netif_tx_queue_stopped(dev_queue) &&
1465 tx->req - tx->done < (tx->mask >> 1)) {
b53bef84 1466 tx->wake_queue++;
236bb5e6 1467 netif_tx_wake_queue(dev_queue);
0da34b6d
BG		 1468 }
1469}
1470
b53bef84
BG		 1471static inline int
1472myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
0da34b6d 1473{
b53bef84
BG		 1474 struct myri10ge_rx_done *rx_done = &ss->rx_done;
1475 struct myri10ge_priv *mgp = ss->mgp;
b3cd9657 1476
0da34b6d
BG		 1477 unsigned long rx_bytes = 0;
1478 unsigned long rx_packets = 0;
1479 unsigned long rx_ok;
1480
1481 int idx = rx_done->idx;
1482 int cnt = rx_done->cnt;
bea3348e 1483 int work_done = 0;
0da34b6d 1484 u16 length;
40f6cff5 1485 __wsum checksum;
0da34b6d 1486
b3cd9657
SG		 1487 /*
1488 * Prevent compiler from generating more than one ->features memory
1489 * access to avoid theoretical race condition with functions that
1490 * change NETIF_F_LRO flag at runtime.
1491 */
1492 bool lro_enabled = ACCESS_ONCE(mgp->dev->features) & NETIF_F_LRO;
1493
c956a240 1494 while (rx_done->entry[idx].length != 0 && work_done < budget) {
0da34b6d
BG		 1495 length = ntohs(rx_done->entry[idx].length);
1496 rx_done->entry[idx].length = 0;
40f6cff5 1497 checksum = csum_unfold(rx_done->entry[idx].checksum);
b3cd9657 1498 rx_ok = myri10ge_rx_done(ss, length, checksum, lro_enabled);
0da34b6d
BG		 1499 rx_packets += rx_ok;
1500 rx_bytes += rx_ok * (unsigned long)length;
1501 cnt++;
014377a1 1502 idx = cnt & (mgp->max_intr_slots - 1);
c956a240 1503 work_done++;
0da34b6d
BG		 1504 }
1505 rx_done->idx = idx;
1506 rx_done->cnt = cnt;
b53bef84
BG		 1507 ss->stats.rx_packets += rx_packets;
1508 ss->stats.rx_bytes += rx_bytes;
c7dab99b 1509
b3cd9657 1510 if (lro_enabled)
1e6e9342
AG		 1511 lro_flush_all(&rx_done->lro_mgr);
1512
c7dab99b 1513 /* restock receive rings if needed */
b53bef84
BG		 1514 if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
1515 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
c7dab99b 1516 mgp->small_bytes + MXGEFW_PAD, 0);
b53bef84
BG		 1517 if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh)
1518 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
c7dab99b 1519
bea3348e 1520 return work_done;
0da34b6d
BG		 1521}
1522
1523static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1524{
0dcffac1 1525 struct mcp_irq_data *stats = mgp->ss[0].fw_stats;
0da34b6d
BG		 1526
1527 if (unlikely(stats->stats_updated)) {
798a95db
BG		 1528 unsigned link_up = ntohl(stats->link_up);
1529 if (mgp->link_state != link_up) {
1530 mgp->link_state = link_up;
1531
1532 if (mgp->link_state == MXGEFW_LINK_UP) {
c58ac5ca 1533 if (netif_msg_link(mgp))
78ca90ea 1534 netdev_info(mgp->dev, "link up\n");
0da34b6d 1535 netif_carrier_on(mgp->dev);
c58ac5ca 1536 mgp->link_changes++;
0da34b6d 1537 } else {
c58ac5ca 1538 if (netif_msg_link(mgp))
78ca90ea
JP		 1539 netdev_info(mgp->dev, "link %s\n",
1540 link_up == MXGEFW_LINK_MYRINET ?
1541 "mismatch (Myrinet detected)" :
1542 "down");
0da34b6d 1543 netif_carrier_off(mgp->dev);
c58ac5ca 1544 mgp->link_changes++;
0da34b6d
BG		 1545 }
1546 }
1547 if (mgp->rdma_tags_available !=
b53bef84 1548 ntohl(stats->rdma_tags_available)) {
0da34b6d 1549 mgp->rdma_tags_available =
b53bef84 1550 ntohl(stats->rdma_tags_available);
78ca90ea
JP		 1551 netdev_warn(mgp->dev, "RDMA timed out! %d tags left\n",
1552 mgp->rdma_tags_available);
0da34b6d
BG		 1553 }
1554 mgp->down_cnt += stats->link_down;
1555 if (stats->link_down)
1556 wake_up(&mgp->down_wq);
1557 }
1558}
1559
bea3348e 1560static int myri10ge_poll(struct napi_struct *napi, int budget)
0da34b6d 1561{
b53bef84
BG		 1562 struct myri10ge_slice_state *ss =
1563 container_of(napi, struct myri10ge_slice_state, napi);
bea3348e 1564 int work_done;
0da34b6d 1565
5dd2d332 1566#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1567 if (ss->mgp->dca_enabled)
1568 myri10ge_update_dca(ss);
1569#endif
1570
0da34b6d 1571 /* process as many rx events as NAPI will allow */
b53bef84 1572 work_done = myri10ge_clean_rx_done(ss, budget);
0da34b6d 1573
4ec24119 1574 if (work_done < budget) {
288379f0 1575 napi_complete(napi);
b53bef84 1576 put_be32(htonl(3), ss->irq_claim);
0da34b6d 1577 }
bea3348e 1578 return work_done;
0da34b6d
BG		 1579}
1580
7d12e780 1581static irqreturn_t myri10ge_intr(int irq, void *arg)
0da34b6d 1582{
b53bef84
BG		 1583 struct myri10ge_slice_state *ss = arg;
1584 struct myri10ge_priv *mgp = ss->mgp;
1585 struct mcp_irq_data *stats = ss->fw_stats;
1586 struct myri10ge_tx_buf *tx = &ss->tx;
0da34b6d
BG		 1587 u32 send_done_count;
1588 int i;
1589
236bb5e6
BG		 1590 /* an interrupt on a non-zero receive-only slice is implicitly
1591 * valid since MSI-X irqs are not shared */
1592 if ((mgp->dev->real_num_tx_queues == 1) && (ss != mgp->ss)) {
288379f0 1593 napi_schedule(&ss->napi);
807540ba 1594 return IRQ_HANDLED;
0dcffac1
BG		 1595 }
1596
0da34b6d
BG		 1597 /* make sure it is our IRQ, and that the DMA has finished */
1598 if (unlikely(!stats->valid))
807540ba 1599 return IRQ_NONE;
0da34b6d
BG		 1600
1601 /* low bit indicates receives are present, so schedule
1602 * napi poll handler */
1603 if (stats->valid & 1)
288379f0 1604 napi_schedule(&ss->napi);
0da34b6d 1605
0dcffac1 1606 if (!mgp->msi_enabled && !mgp->msix_enabled) {
40f6cff5 1607 put_be32(0, mgp->irq_deassert);
0da34b6d
BG		 1608 if (!myri10ge_deassert_wait)
1609 stats->valid = 0;
1610 mb();
1611 } else
1612 stats->valid = 0;
1613
1614 /* Wait for IRQ line to go low, if using INTx */
1615 i = 0;
1616 while (1) {
1617 i++;
1618 /* check for transmit completes and receives */
1619 send_done_count = ntohl(stats->send_done_count);
1620 if (send_done_count != tx->pkt_done)
b53bef84 1621 myri10ge_tx_done(ss, (int)send_done_count);
0da34b6d 1622 if (unlikely(i > myri10ge_max_irq_loops)) {
78ca90ea 1623 netdev_err(mgp->dev, "irq stuck?\n");
0da34b6d
BG		 1624 stats->valid = 0;
1625 schedule_work(&mgp->watchdog_work);
1626 }
1627 if (likely(stats->valid == 0))
1628 break;
1629 cpu_relax();
1630 barrier();
1631 }
1632
236bb5e6
BG		 1633 /* Only slice 0 updates stats */
1634 if (ss == mgp->ss)
1635 myri10ge_check_statblock(mgp);
0da34b6d 1636
b53bef84 1637 put_be32(htonl(3), ss->irq_claim + 1);
807540ba 1638 return IRQ_HANDLED;
0da34b6d
BG		 1639}
1640
1641static int
1642myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1643{
c0bf8801
BG		 1644 struct myri10ge_priv *mgp = netdev_priv(netdev);
1645 char *ptr;
1646 int i;
1647
0da34b6d 1648 cmd->autoneg = AUTONEG_DISABLE;
70739497 1649 ethtool_cmd_speed_set(cmd, SPEED_10000);
0da34b6d 1650 cmd->duplex = DUPLEX_FULL;
c0bf8801
BG		 1651
1652 /*
1653 * parse the product code to deterimine the interface type
1654 * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1655 * after the 3rd dash in the driver's cached copy of the
1656 * EEPROM's product code string.
1657 */
1658 ptr = mgp->product_code_string;
1659 if (ptr == NULL) {
78ca90ea 1660 netdev_err(netdev, "Missing product code\n");
c0bf8801
BG		 1661 return 0;
1662 }
1663 for (i = 0; i < 3; i++, ptr++) {
1664 ptr = strchr(ptr, '-');
1665 if (ptr == NULL) {
78ca90ea
JP		 1666 netdev_err(netdev, "Invalid product code %s\n",
1667 mgp->product_code_string);
c0bf8801
BG		 1668 return 0;
1669 }
1670 }
196f17eb
BG		 1671 if (*ptr == '2')
1672 ptr++;
1673 if (*ptr == 'R' || *ptr == 'Q' || *ptr == 'S') {
1674 /* We've found either an XFP, quad ribbon fiber, or SFP+ */
c0bf8801 1675 cmd->port = PORT_FIBRE;
196f17eb
BG		 1676 cmd->supported |= SUPPORTED_FIBRE;
1677 cmd->advertising |= ADVERTISED_FIBRE;
1678 } else {
1679 cmd->port = PORT_OTHER;
c0bf8801 1680 }
196f17eb
BG		 1681 if (*ptr == 'R' || *ptr == 'S')
1682 cmd->transceiver = XCVR_EXTERNAL;
1683 else
1684 cmd->transceiver = XCVR_INTERNAL;
1685
0da34b6d
BG		 1686 return 0;
1687}
1688
1689static void
1690myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1691{
1692 struct myri10ge_priv *mgp = netdev_priv(netdev);
1693
1694 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1695 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1696 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1697 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1698}
1699
1700static int
1701myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1702{
1703 struct myri10ge_priv *mgp = netdev_priv(netdev);
99f5f87e 1704
0da34b6d
BG		 1705 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1706 return 0;
1707}
1708
1709static int
1710myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1711{
1712 struct myri10ge_priv *mgp = netdev_priv(netdev);
1713
1714 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
40f6cff5 1715 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 1716 return 0;
1717}
1718
1719static void
1720myri10ge_get_pauseparam(struct net_device *netdev,
1721 struct ethtool_pauseparam *pause)
1722{
1723 struct myri10ge_priv *mgp = netdev_priv(netdev);
1724
1725 pause->autoneg = 0;
1726 pause->rx_pause = mgp->pause;
1727 pause->tx_pause = mgp->pause;
1728}
1729
1730static int
1731myri10ge_set_pauseparam(struct net_device *netdev,
1732 struct ethtool_pauseparam *pause)
1733{
1734 struct myri10ge_priv *mgp = netdev_priv(netdev);
1735
1736 if (pause->tx_pause != mgp->pause)
1737 return myri10ge_change_pause(mgp, pause->tx_pause);
1738 if (pause->rx_pause != mgp->pause)
2488f56d 1739 return myri10ge_change_pause(mgp, pause->rx_pause);
0da34b6d
BG		 1740 if (pause->autoneg != 0)
1741 return -EINVAL;
1742 return 0;
1743}
1744
1745static void
1746myri10ge_get_ringparam(struct net_device *netdev,
1747 struct ethtool_ringparam *ring)
1748{
1749 struct myri10ge_priv *mgp = netdev_priv(netdev);
1750
0dcffac1
BG		 1751 ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1;
1752 ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1;
0da34b6d 1753 ring->rx_jumbo_max_pending = 0;
6498be3f 1754 ring->tx_max_pending = mgp->ss[0].tx.mask + 1;
0da34b6d
BG		 1755 ring->rx_mini_pending = ring->rx_mini_max_pending;
1756 ring->rx_pending = ring->rx_max_pending;
1757 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1758 ring->tx_pending = ring->tx_max_pending;
1759}
1760
b53bef84 1761static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
0da34b6d
BG		 1762 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1763 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1764 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1765 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1766 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1767 "tx_heartbeat_errors", "tx_window_errors",
1768 /* device-specific stats */
0dcffac1 1769 "tx_boundary", "WC", "irq", "MSI", "MSIX",
0da34b6d 1770 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
b53bef84 1771 "serial_number", "watchdog_resets",
5dd2d332 1772#ifdef CONFIG_MYRI10GE_DCA
9a6b3b54 1773 "dca_capable_firmware", "dca_device_present",
981813d8 1774#endif
c58ac5ca 1775 "link_changes", "link_up", "dropped_link_overflow",
cee505db
BG		 1776 "dropped_link_error_or_filtered",
1777 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1778 "dropped_unicast_filtered", "dropped_multicast_filtered",
0da34b6d 1779 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
b53bef84
BG		 1780 "dropped_no_big_buffer"
1781};
1782
1783static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1784 "----------- slice ---------",
1785 "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1786 "rx_small_cnt", "rx_big_cnt",
1787 "wake_queue", "stop_queue", "tx_linearized", "LRO aggregated",
1788 "LRO flushed",
1e6e9342 1789 "LRO avg aggr", "LRO no_desc"
0da34b6d
BG		 1790};
1791
1792#define MYRI10GE_NET_STATS_LEN 21
b53bef84
BG		 1793#define MYRI10GE_MAIN_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_main_stats)
1794#define MYRI10GE_SLICE_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_slice_stats)
0da34b6d
BG		 1795
1796static void
1797myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1798{
0dcffac1
BG		 1799 struct myri10ge_priv *mgp = netdev_priv(netdev);
1800 int i;
1801
0da34b6d
BG		 1802 switch (stringset) {
1803 case ETH_SS_STATS:
b53bef84
BG		 1804 memcpy(data, *myri10ge_gstrings_main_stats,
1805 sizeof(myri10ge_gstrings_main_stats));
1806 data += sizeof(myri10ge_gstrings_main_stats);
0dcffac1
BG		 1807 for (i = 0; i < mgp->num_slices; i++) {
1808 memcpy(data, *myri10ge_gstrings_slice_stats,
1809 sizeof(myri10ge_gstrings_slice_stats));
1810 data += sizeof(myri10ge_gstrings_slice_stats);
1811 }
0da34b6d
BG		 1812 break;
1813 }
1814}
1815
b9f2c044 1816static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
0da34b6d 1817{
0dcffac1
BG		 1818 struct myri10ge_priv *mgp = netdev_priv(netdev);
1819
b9f2c044
JG		 1820 switch (sset) {
1821 case ETH_SS_STATS:
0dcffac1
BG		 1822 return MYRI10GE_MAIN_STATS_LEN +
1823 mgp->num_slices * MYRI10GE_SLICE_STATS_LEN;
b9f2c044
JG		 1824 default:
1825 return -EOPNOTSUPP;
1826 }
0da34b6d
BG		 1827}
1828
1829static void
1830myri10ge_get_ethtool_stats(struct net_device *netdev,
1831 struct ethtool_stats *stats, u64 * data)
1832{
1833 struct myri10ge_priv *mgp = netdev_priv(netdev);
b53bef84 1834 struct myri10ge_slice_state *ss;
c5f7ef72 1835 struct rtnl_link_stats64 link_stats;
0dcffac1 1836 int slice;
0da34b6d
BG		 1837 int i;
1838
59081825 1839 /* force stats update */
c5f7ef72 1840 (void)myri10ge_get_stats(netdev, &link_stats);
0da34b6d 1841 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
c5f7ef72 1842 data[i] = ((u64 *)&link_stats)[i];
0da34b6d 1843
b53bef84 1844 data[i++] = (unsigned int)mgp->tx_boundary;
276e26c3 1845 data[i++] = (unsigned int)mgp->wc_enabled;
2c1a1088
BG		 1846 data[i++] = (unsigned int)mgp->pdev->irq;
1847 data[i++] = (unsigned int)mgp->msi_enabled;
0dcffac1 1848 data[i++] = (unsigned int)mgp->msix_enabled;
0da34b6d
BG		 1849 data[i++] = (unsigned int)mgp->read_dma;
1850 data[i++] = (unsigned int)mgp->write_dma;
1851 data[i++] = (unsigned int)mgp->read_write_dma;
1852 data[i++] = (unsigned int)mgp->serial_number;
0da34b6d 1853 data[i++] = (unsigned int)mgp->watchdog_resets;
5dd2d332 1854#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1855 data[i++] = (unsigned int)(mgp->ss[0].dca_tag != NULL);
1856 data[i++] = (unsigned int)(mgp->dca_enabled);
1857#endif
c58ac5ca 1858 data[i++] = (unsigned int)mgp->link_changes;
b53bef84
BG		 1859
1860 /* firmware stats are useful only in the first slice */
0dcffac1 1861 ss = &mgp->ss[0];
b53bef84
BG		 1862 data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1863 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
cee505db 1864 data[i++] =
b53bef84
BG		 1865 (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered);
1866 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause);
1867 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy);
1868 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32);
1869 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered);
85a7ea1b 1870 data[i++] =
b53bef84
BG		 1871 (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered);
1872 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt);
1873 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun);
1874 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
1875 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
1876
0dcffac1
BG		 1877 for (slice = 0; slice < mgp->num_slices; slice++) {
1878 ss = &mgp->ss[slice];
1879 data[i++] = slice;
1880 data[i++] = (unsigned int)ss->tx.pkt_start;
1881 data[i++] = (unsigned int)ss->tx.pkt_done;
1882 data[i++] = (unsigned int)ss->tx.req;
1883 data[i++] = (unsigned int)ss->tx.done;
1884 data[i++] = (unsigned int)ss->rx_small.cnt;
1885 data[i++] = (unsigned int)ss->rx_big.cnt;
1886 data[i++] = (unsigned int)ss->tx.wake_queue;
1887 data[i++] = (unsigned int)ss->tx.stop_queue;
1888 data[i++] = (unsigned int)ss->tx.linearized;
1889 data[i++] = ss->rx_done.lro_mgr.stats.aggregated;
1890 data[i++] = ss->rx_done.lro_mgr.stats.flushed;
1891 if (ss->rx_done.lro_mgr.stats.flushed)
1892 data[i++] = ss->rx_done.lro_mgr.stats.aggregated /
1893 ss->rx_done.lro_mgr.stats.flushed;
1894 else
1895 data[i++] = 0;
1896 data[i++] = ss->rx_done.lro_mgr.stats.no_desc;
1897 }
0da34b6d
BG		 1898}
1899
c58ac5ca
BG		 1900static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1901{
1902 struct myri10ge_priv *mgp = netdev_priv(netdev);
1903 mgp->msg_enable = value;
1904}
1905
1906static u32 myri10ge_get_msglevel(struct net_device *netdev)
1907{
1908 struct myri10ge_priv *mgp = netdev_priv(netdev);
1909 return mgp->msg_enable;
1910}
1911
7282d491 1912static const struct ethtool_ops myri10ge_ethtool_ops = {
0da34b6d
BG		 1913 .get_settings = myri10ge_get_settings,
1914 .get_drvinfo = myri10ge_get_drvinfo,
1915 .get_coalesce = myri10ge_get_coalesce,
1916 .set_coalesce = myri10ge_set_coalesce,
1917 .get_pauseparam = myri10ge_get_pauseparam,
1918 .set_pauseparam = myri10ge_set_pauseparam,
1919 .get_ringparam = myri10ge_get_ringparam,
6ffdd071 1920 .get_link = ethtool_op_get_link,
0da34b6d 1921 .get_strings = myri10ge_get_strings,
b9f2c044 1922 .get_sset_count = myri10ge_get_sset_count,
c58ac5ca
BG		 1923 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1924 .set_msglevel = myri10ge_set_msglevel,
3a0c7d2d 1925 .get_msglevel = myri10ge_get_msglevel,
0da34b6d
BG		 1926};
1927
b53bef84 1928static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
0da34b6d 1929{
b53bef84 1930 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d 1931 struct myri10ge_cmd cmd;
b53bef84 1932 struct net_device *dev = mgp->dev;
0da34b6d
BG		 1933 int tx_ring_size, rx_ring_size;
1934 int tx_ring_entries, rx_ring_entries;
0dcffac1 1935 int i, slice, status;
0da34b6d
BG		 1936 size_t bytes;
1937
0da34b6d 1938 /* get ring sizes */
0dcffac1
BG		 1939 slice = ss - mgp->ss;
1940 cmd.data0 = slice;
0da34b6d
BG		 1941 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1942 tx_ring_size = cmd.data0;
0dcffac1 1943 cmd.data0 = slice;
0da34b6d 1944 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
355c7265
BG		 1945 if (status != 0)
1946 return status;
0da34b6d
BG		 1947 rx_ring_size = cmd.data0;
1948
1949 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1950 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
b53bef84
BG		 1951 ss->tx.mask = tx_ring_entries - 1;
1952 ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
0da34b6d 1953
355c7265
BG		 1954 status = -ENOMEM;
1955
0da34b6d
BG		 1956 /* allocate the host shadow rings */
1957
1958 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
b53bef84
BG		 1959 * sizeof(*ss->tx.req_list);
1960 ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1961 if (ss->tx.req_bytes == NULL)
0da34b6d
BG		 1962 goto abort_with_nothing;
1963
1964 /* ensure req_list entries are aligned to 8 bytes */
b53bef84
BG		 1965 ss->tx.req_list = (struct mcp_kreq_ether_send *)
1966 ALIGN((unsigned long)ss->tx.req_bytes, 8);
236bb5e6 1967 ss->tx.queue_active = 0;
0da34b6d 1968
b53bef84
BG		 1969 bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow);
1970 ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1971 if (ss->rx_small.shadow == NULL)
0da34b6d
BG		 1972 goto abort_with_tx_req_bytes;
1973
b53bef84
BG		 1974 bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow);
1975 ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1976 if (ss->rx_big.shadow == NULL)
0da34b6d
BG		 1977 goto abort_with_rx_small_shadow;
1978
1979 /* allocate the host info rings */
1980
b53bef84
BG		 1981 bytes = tx_ring_entries * sizeof(*ss->tx.info);
1982 ss->tx.info = kzalloc(bytes, GFP_KERNEL);
1983 if (ss->tx.info == NULL)
0da34b6d
BG		 1984 goto abort_with_rx_big_shadow;
1985
b53bef84
BG		 1986 bytes = rx_ring_entries * sizeof(*ss->rx_small.info);
1987 ss->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1988 if (ss->rx_small.info == NULL)
0da34b6d
BG		 1989 goto abort_with_tx_info;
1990
b53bef84
BG		 1991 bytes = rx_ring_entries * sizeof(*ss->rx_big.info);
1992 ss->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1993 if (ss->rx_big.info == NULL)
0da34b6d
BG		 1994 goto abort_with_rx_small_info;
1995
1996 /* Fill the receive rings */
b53bef84
BG		 1997 ss->rx_big.cnt = 0;
1998 ss->rx_small.cnt = 0;
1999 ss->rx_big.fill_cnt = 0;
2000 ss->rx_small.fill_cnt = 0;
2001 ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
2002 ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
2003 ss->rx_small.watchdog_needed = 0;
2004 ss->rx_big.watchdog_needed = 0;
2005 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
c7dab99b 2006 mgp->small_bytes + MXGEFW_PAD, 0);
0da34b6d 2007
b53bef84 2008 if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
78ca90ea
JP		 2009 netdev_err(dev, "slice-%d: alloced only %d small bufs\n",
2010 slice, ss->rx_small.fill_cnt);
c7dab99b 2011 goto abort_with_rx_small_ring;
0da34b6d
BG		 2012 }
2013
b53bef84
BG		 2014 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
2015 if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
78ca90ea
JP		 2016 netdev_err(dev, "slice-%d: alloced only %d big bufs\n",
2017 slice, ss->rx_big.fill_cnt);
c7dab99b 2018 goto abort_with_rx_big_ring;
0da34b6d
BG		 2019 }
2020
2021 return 0;
2022
2023abort_with_rx_big_ring:
b53bef84
BG		 2024 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2025 int idx = i & ss->rx_big.mask;
2026 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 2027 mgp->big_bytes);
b53bef84 2028 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 2029 }
2030
2031abort_with_rx_small_ring:
b53bef84
BG		 2032 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2033 int idx = i & ss->rx_small.mask;
2034 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 2035 mgp->small_bytes + MXGEFW_PAD);
b53bef84 2036 put_page(ss->rx_small.info[idx].page);
0da34b6d 2037 }
c7dab99b 2038
b53bef84 2039 kfree(ss->rx_big.info);
0da34b6d
BG		 2040
2041abort_with_rx_small_info:
b53bef84 2042 kfree(ss->rx_small.info);
0da34b6d
BG		 2043
2044abort_with_tx_info:
b53bef84 2045 kfree(ss->tx.info);
0da34b6d
BG		 2046
2047abort_with_rx_big_shadow:
b53bef84 2048 kfree(ss->rx_big.shadow);
0da34b6d
BG		 2049
2050abort_with_rx_small_shadow:
b53bef84 2051 kfree(ss->rx_small.shadow);
0da34b6d
BG		 2052
2053abort_with_tx_req_bytes:
b53bef84
BG		 2054 kfree(ss->tx.req_bytes);
2055 ss->tx.req_bytes = NULL;
2056 ss->tx.req_list = NULL;
0da34b6d
BG		 2057
2058abort_with_nothing:
2059 return status;
2060}
2061
b53bef84 2062static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
0da34b6d 2063{
b53bef84 2064 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d
BG		 2065 struct sk_buff *skb;
2066 struct myri10ge_tx_buf *tx;
2067 int i, len, idx;
2068
0dcffac1
BG		 2069 /* If not allocated, skip it */
2070 if (ss->tx.req_list == NULL)
2071 return;
2072
b53bef84
BG		 2073 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2074 idx = i & ss->rx_big.mask;
2075 if (i == ss->rx_big.fill_cnt - 1)
2076 ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
2077 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 2078 mgp->big_bytes);
b53bef84 2079 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 2080 }
2081
b53bef84
BG		 2082 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2083 idx = i & ss->rx_small.mask;
2084 if (i == ss->rx_small.fill_cnt - 1)
2085 ss->rx_small.info[idx].page_offset =
c7dab99b 2086 MYRI10GE_ALLOC_SIZE;
b53bef84 2087 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 2088 mgp->small_bytes + MXGEFW_PAD);
b53bef84 2089 put_page(ss->rx_small.info[idx].page);
c7dab99b 2090 }
b53bef84 2091 tx = &ss->tx;
0da34b6d
BG		 2092 while (tx->done != tx->req) {
2093 idx = tx->done & tx->mask;
2094 skb = tx->info[idx].skb;
2095
2096 /* Mark as free */
2097 tx->info[idx].skb = NULL;
2098 tx->done++;
c755b4b6
FT		 2099 len = dma_unmap_len(&tx->info[idx], len);
2100 dma_unmap_len_set(&tx->info[idx], len, 0);
0da34b6d 2101 if (skb) {
b53bef84 2102 ss->stats.tx_dropped++;
0da34b6d
BG		 2103 dev_kfree_skb_any(skb);
2104 if (len)
2105 pci_unmap_single(mgp->pdev,
c755b4b6 2106 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 2107 bus), len,
2108 PCI_DMA_TODEVICE);
2109 } else {
2110 if (len)
2111 pci_unmap_page(mgp->pdev,
c755b4b6 2112 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 2113 bus), len,
2114 PCI_DMA_TODEVICE);
2115 }
2116 }
b53bef84 2117 kfree(ss->rx_big.info);
0da34b6d 2118
b53bef84 2119 kfree(ss->rx_small.info);
0da34b6d 2120
b53bef84 2121 kfree(ss->tx.info);
0da34b6d 2122
b53bef84 2123 kfree(ss->rx_big.shadow);
0da34b6d 2124
b53bef84 2125 kfree(ss->rx_small.shadow);
0da34b6d 2126
b53bef84
BG		 2127 kfree(ss->tx.req_bytes);
2128 ss->tx.req_bytes = NULL;
2129 ss->tx.req_list = NULL;
0da34b6d
BG		 2130}
2131
df30a740
BG		 2132static int myri10ge_request_irq(struct myri10ge_priv *mgp)
2133{
2134 struct pci_dev *pdev = mgp->pdev;
0dcffac1
BG		 2135 struct myri10ge_slice_state *ss;
2136 struct net_device *netdev = mgp->dev;
2137 int i;
df30a740
BG		 2138 int status;
2139
0dcffac1
BG		 2140 mgp->msi_enabled = 0;
2141 mgp->msix_enabled = 0;
2142 status = 0;
df30a740 2143 if (myri10ge_msi) {
0dcffac1
BG		 2144 if (mgp->num_slices > 1) {
2145 status =
2146 pci_enable_msix(pdev, mgp->msix_vectors,
2147 mgp->num_slices);
2148 if (status == 0) {
2149 mgp->msix_enabled = 1;
2150 } else {
2151 dev_err(&pdev->dev,
2152 "Error %d setting up MSI-X\n", status);
2153 return status;
2154 }
2155 }
2156 if (mgp->msix_enabled == 0) {
2157 status = pci_enable_msi(pdev);
2158 if (status != 0) {
2159 dev_err(&pdev->dev,
2160 "Error %d setting up MSI; falling back to xPIC\n",
2161 status);
2162 } else {
2163 mgp->msi_enabled = 1;
2164 }
2165 }
df30a740 2166 }
0dcffac1
BG		 2167 if (mgp->msix_enabled) {
2168 for (i = 0; i < mgp->num_slices; i++) {
2169 ss = &mgp->ss[i];
2170 snprintf(ss->irq_desc, sizeof(ss->irq_desc),
2171 "%s:slice-%d", netdev->name, i);
2172 status = request_irq(mgp->msix_vectors[i].vector,
2173 myri10ge_intr, 0, ss->irq_desc,
2174 ss);
2175 if (status != 0) {
2176 dev_err(&pdev->dev,
2177 "slice %d failed to allocate IRQ\n", i);
2178 i--;
2179 while (i >= 0) {
2180 free_irq(mgp->msix_vectors[i].vector,
2181 &mgp->ss[i]);
2182 i--;
2183 }
2184 pci_disable_msix(pdev);
2185 return status;
2186 }
2187 }
2188 } else {
2189 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2190 mgp->dev->name, &mgp->ss[0]);
2191 if (status != 0) {
2192 dev_err(&pdev->dev, "failed to allocate IRQ\n");
2193 if (mgp->msi_enabled)
2194 pci_disable_msi(pdev);
2195 }
df30a740
BG		 2196 }
2197 return status;
2198}
2199
2200static void myri10ge_free_irq(struct myri10ge_priv *mgp)
2201{
2202 struct pci_dev *pdev = mgp->pdev;
0dcffac1 2203 int i;
df30a740 2204
0dcffac1
BG		 2205 if (mgp->msix_enabled) {
2206 for (i = 0; i < mgp->num_slices; i++)
2207 free_irq(mgp->msix_vectors[i].vector, &mgp->ss[i]);
2208 } else {
2209 free_irq(pdev->irq, &mgp->ss[0]);
2210 }
df30a740
BG		 2211 if (mgp->msi_enabled)
2212 pci_disable_msi(pdev);
0dcffac1
BG		 2213 if (mgp->msix_enabled)
2214 pci_disable_msix(pdev);
df30a740
BG		 2215}
2216
1e6e9342
AG		 2217static int
2218myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
2219 void **ip_hdr, void **tcpudp_hdr,
2220 u64 * hdr_flags, void *priv)
2221{
2222 struct ethhdr *eh;
2223 struct vlan_ethhdr *veh;
2224 struct iphdr *iph;
2225 u8 *va = page_address(frag->page) + frag->page_offset;
2226 unsigned long ll_hlen;
66341fff
AV		 2227 /* passed opaque through lro_receive_frags() */
2228 __wsum csum = (__force __wsum) (unsigned long)priv;
1e6e9342
AG		 2229
2230 /* find the mac header, aborting if not IPv4 */
2231
2232 eh = (struct ethhdr *)va;
2233 *mac_hdr = eh;
2234 ll_hlen = ETH_HLEN;
2235 if (eh->h_proto != htons(ETH_P_IP)) {
2236 if (eh->h_proto == htons(ETH_P_8021Q)) {
2237 veh = (struct vlan_ethhdr *)va;
2238 if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
2239 return -1;
2240
2241 ll_hlen += VLAN_HLEN;
2242
2243 /*
2244 * HW checksum starts ETH_HLEN bytes into
2245 * frame, so we must subtract off the VLAN
2246 * header's checksum before csum can be used
2247 */
2248 csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
2249 VLAN_HLEN, 0));
2250 } else {
2251 return -1;
2252 }
2253 }
2254 *hdr_flags = LRO_IPV4;
2255
2256 iph = (struct iphdr *)(va + ll_hlen);
2257 *ip_hdr = iph;
2258 if (iph->protocol != IPPROTO_TCP)
2259 return -1;
bcb09dc2
BG		 2260 if (iph->frag_off & htons(IP_MF | IP_OFFSET))
2261 return -1;
1e6e9342
AG		 2262 *hdr_flags |= LRO_TCP;
2263 *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
2264
2265 /* verify the IP checksum */
2266 if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
2267 return -1;
2268
2269 /* verify the checksum */
2270 if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
2271 ntohs(iph->tot_len) - (iph->ihl << 2),
2272 IPPROTO_TCP, csum)))
2273 return -1;
2274
2275 return 0;
2276}
2277
77929732
BG		 2278static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
2279{
2280 struct myri10ge_cmd cmd;
2281 struct myri10ge_slice_state *ss;
2282 int status;
2283
2284 ss = &mgp->ss[slice];
236bb5e6
BG		 2285 status = 0;
2286 if (slice == 0 || (mgp->dev->real_num_tx_queues > 1)) {
2287 cmd.data0 = slice;
2288 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET,
2289 &cmd, 0);
2290 ss->tx.lanai = (struct mcp_kreq_ether_send __iomem *)
2291 (mgp->sram + cmd.data0);
2292 }
77929732
BG		 2293 cmd.data0 = slice;
2294 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET,
2295 &cmd, 0);
2296 ss->rx_small.lanai = (struct mcp_kreq_ether_recv __iomem *)
2297 (mgp->sram + cmd.data0);
2298
2299 cmd.data0 = slice;
2300 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
2301 ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *)
2302 (mgp->sram + cmd.data0);
2303
236bb5e6
BG		 2304 ss->tx.send_go = (__iomem __be32 *)
2305 (mgp->sram + MXGEFW_ETH_SEND_GO + 64 * slice);
2306 ss->tx.send_stop = (__iomem __be32 *)
2307 (mgp->sram + MXGEFW_ETH_SEND_STOP + 64 * slice);
77929732
BG		 2308 return status;
2309
2310}
2311
2312static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice)
2313{
2314 struct myri10ge_cmd cmd;
2315 struct myri10ge_slice_state *ss;
2316 int status;
2317
2318 ss = &mgp->ss[slice];
2319 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->fw_stats_bus);
2320 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->fw_stats_bus);
236bb5e6 2321 cmd.data2 = sizeof(struct mcp_irq_data) | (slice << 16);
77929732
BG		 2322 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2323 if (status == -ENOSYS) {
2324 dma_addr_t bus = ss->fw_stats_bus;
2325 if (slice != 0)
2326 return -EINVAL;
2327 bus += offsetof(struct mcp_irq_data, send_done_count);
2328 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2329 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2330 status = myri10ge_send_cmd(mgp,
2331 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2332 &cmd, 0);
2333 /* Firmware cannot support multicast without STATS_DMA_V2 */
2334 mgp->fw_multicast_support = 0;
2335 } else {
2336 mgp->fw_multicast_support = 1;
2337 }
2338 return 0;
2339}
77929732 2340
0da34b6d
BG		 2341static int myri10ge_open(struct net_device *dev)
2342{
0dcffac1 2343 struct myri10ge_slice_state *ss;
b53bef84 2344 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d 2345 struct myri10ge_cmd cmd;
0dcffac1
BG		 2346 int i, status, big_pow2, slice;
2347 u8 *itable;
1e6e9342 2348 struct net_lro_mgr *lro_mgr;
0da34b6d 2349
0da34b6d
BG		 2350 if (mgp->running != MYRI10GE_ETH_STOPPED)
2351 return -EBUSY;
2352
2353 mgp->running = MYRI10GE_ETH_STARTING;
2354 status = myri10ge_reset(mgp);
2355 if (status != 0) {
78ca90ea 2356 netdev_err(dev, "failed reset\n");
df30a740 2357 goto abort_with_nothing;
0da34b6d
BG		 2358 }
2359
0dcffac1
BG		 2360 if (mgp->num_slices > 1) {
2361 cmd.data0 = mgp->num_slices;
236bb5e6
BG		 2362 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
2363 if (mgp->dev->real_num_tx_queues > 1)
2364 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
0dcffac1
BG		 2365 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
2366 &cmd, 0);
2367 if (status != 0) {
78ca90ea 2368 netdev_err(dev, "failed to set number of slices\n");
0dcffac1
BG		 2369 goto abort_with_nothing;
2370 }
2371 /* setup the indirection table */
2372 cmd.data0 = mgp->num_slices;
2373 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
2374 &cmd, 0);
2375
2376 status |= myri10ge_send_cmd(mgp,
2377 MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
2378 &cmd, 0);
2379 if (status != 0) {
78ca90ea 2380 netdev_err(dev, "failed to setup rss tables\n");
236bb5e6 2381 goto abort_with_nothing;
0dcffac1
BG		 2382 }
2383
2384 /* just enable an identity mapping */
2385 itable = mgp->sram + cmd.data0;
2386 for (i = 0; i < mgp->num_slices; i++)
2387 __raw_writeb(i, &itable[i]);
2388
2389 cmd.data0 = 1;
2390 cmd.data1 = myri10ge_rss_hash;
2391 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE,
2392 &cmd, 0);
2393 if (status != 0) {
78ca90ea 2394 netdev_err(dev, "failed to enable slices\n");
0dcffac1
BG		 2395 goto abort_with_nothing;
2396 }
2397 }
2398
df30a740
BG		 2399 status = myri10ge_request_irq(mgp);
2400 if (status != 0)
2401 goto abort_with_nothing;
2402
0da34b6d
BG		 2403 /* decide what small buffer size to use. For good TCP rx
2404 * performance, it is important to not receive 1514 byte
2405 * frames into jumbo buffers, as it confuses the socket buffer
2406 * accounting code, leading to drops and erratic performance.
2407 */
2408
2409 if (dev->mtu <= ETH_DATA_LEN)
c7dab99b
BG		 2410 /* enough for a TCP header */
2411 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
2412 ? (128 - MXGEFW_PAD)
2413 : (SMP_CACHE_BYTES - MXGEFW_PAD);
0da34b6d 2414 else
de3c4507
BG		 2415 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
2416 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
0da34b6d
BG		 2417
2418 /* Override the small buffer size? */
2419 if (myri10ge_small_bytes > 0)
2420 mgp->small_bytes = myri10ge_small_bytes;
2421
0da34b6d
BG		 2422 /* Firmware needs the big buff size as a power of 2. Lie and
2423 * tell him the buffer is larger, because we only use 1
2424 * buffer/pkt, and the mtu will prevent overruns.
2425 */
13348bee 2426 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b 2427 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
199126a2 2428 while (!is_power_of_2(big_pow2))
c7dab99b 2429 big_pow2++;
13348bee 2430 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 2431 } else {
2432 big_pow2 = MYRI10GE_ALLOC_SIZE;
2433 mgp->big_bytes = big_pow2;
2434 }
2435
0dcffac1
BG		 2436 /* setup the per-slice data structures */
2437 for (slice = 0; slice < mgp->num_slices; slice++) {
2438 ss = &mgp->ss[slice];
2439
2440 status = myri10ge_get_txrx(mgp, slice);
2441 if (status != 0) {
78ca90ea 2442 netdev_err(dev, "failed to get ring sizes or locations\n");
0dcffac1
BG		 2443 goto abort_with_rings;
2444 }
2445 status = myri10ge_allocate_rings(ss);
2446 if (status != 0)
2447 goto abort_with_rings;
236bb5e6
BG		 2448
2449 /* only firmware which supports multiple TX queues
2450 * supports setting up the tx stats on non-zero
2451 * slices */
2452 if (slice == 0 || mgp->dev->real_num_tx_queues > 1)
0dcffac1
BG		 2453 status = myri10ge_set_stats(mgp, slice);
2454 if (status) {
78ca90ea 2455 netdev_err(dev, "Couldn't set stats DMA\n");
0dcffac1
BG		 2456 goto abort_with_rings;
2457 }
2458
2459 lro_mgr = &ss->rx_done.lro_mgr;
2460 lro_mgr->dev = dev;
2461 lro_mgr->features = LRO_F_NAPI;
2462 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
2463 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2464 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
2465 lro_mgr->lro_arr = ss->rx_done.lro_desc;
2466 lro_mgr->get_frag_header = myri10ge_get_frag_header;
2467 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
636d2f68 2468 lro_mgr->frag_align_pad = 2;
0dcffac1
BG		 2469 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2470 lro_mgr->max_aggr = MAX_SKB_FRAGS;
2471
2472 /* must happen prior to any irq */
2473 napi_enable(&(ss)->napi);
2474 }
0da34b6d
BG		 2475
2476 /* now give firmware buffers sizes, and MTU */
2477 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
2478 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2479 cmd.data0 = mgp->small_bytes;
2480 status |=
2481 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2482 cmd.data0 = big_pow2;
2483 status |=
2484 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2485 if (status) {
78ca90ea 2486 netdev_err(dev, "Couldn't set buffer sizes\n");
0da34b6d
BG		 2487 goto abort_with_rings;
2488 }
2489
0dcffac1
BG		 2490 /*
2491 * Set Linux style TSO mode; this is needed only on newer
2492 * firmware versions. Older versions default to Linux
2493 * style TSO
2494 */
2495 cmd.data0 = 0;
2496 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd, 0);
2497 if (status && status != -ENOSYS) {
78ca90ea 2498 netdev_err(dev, "Couldn't set TSO mode\n");
0da34b6d
BG		 2499 goto abort_with_rings;
2500 }
2501
66341fff 2502 mgp->link_state = ~0U;
0da34b6d
BG		 2503 mgp->rdma_tags_available = 15;
2504
0da34b6d
BG		 2505 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2506 if (status) {
78ca90ea 2507 netdev_err(dev, "Couldn't bring up link\n");
0da34b6d
BG		 2508 goto abort_with_rings;
2509 }
2510
0da34b6d
BG		 2511 mgp->running = MYRI10GE_ETH_RUNNING;
2512 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2513 add_timer(&mgp->watchdog_timer);
236bb5e6
BG		 2514 netif_tx_wake_all_queues(dev);
2515
0da34b6d
BG		 2516 return 0;
2517
2518abort_with_rings:
051d36f3
BG		 2519 while (slice) {
2520 slice--;
2521 napi_disable(&mgp->ss[slice].napi);
2522 }
0dcffac1
BG		 2523 for (i = 0; i < mgp->num_slices; i++)
2524 myri10ge_free_rings(&mgp->ss[i]);
0da34b6d 2525
df30a740
BG		 2526 myri10ge_free_irq(mgp);
2527
0da34b6d
BG		 2528abort_with_nothing:
2529 mgp->running = MYRI10GE_ETH_STOPPED;
2530 return -ENOMEM;
2531}
2532
2533static int myri10ge_close(struct net_device *dev)
2534{
b53bef84 2535 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d
BG		 2536 struct myri10ge_cmd cmd;
2537 int status, old_down_cnt;
0dcffac1 2538 int i;
0da34b6d 2539
0da34b6d
BG		 2540 if (mgp->running != MYRI10GE_ETH_RUNNING)
2541 return 0;
2542
0dcffac1 2543 if (mgp->ss[0].tx.req_bytes == NULL)
0da34b6d
BG		 2544 return 0;
2545
2546 del_timer_sync(&mgp->watchdog_timer);
2547 mgp->running = MYRI10GE_ETH_STOPPING;
0dcffac1
BG		 2548 for (i = 0; i < mgp->num_slices; i++) {
2549 napi_disable(&mgp->ss[i].napi);
2550 }
0da34b6d 2551 netif_carrier_off(dev);
236bb5e6
BG		 2552
2553 netif_tx_stop_all_queues(dev);
d0234215
BG		 2554 if (mgp->rebooted == 0) {
2555 old_down_cnt = mgp->down_cnt;
2556 mb();
2557 status =
2558 myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2559 if (status)
78ca90ea 2560 netdev_err(dev, "Couldn't bring down link\n");
0da34b6d 2561
d0234215
BG		 2562 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt,
2563 HZ);
2564 if (old_down_cnt == mgp->down_cnt)
78ca90ea 2565 netdev_err(dev, "never got down irq\n");
d0234215 2566 }
0da34b6d 2567 netif_tx_disable(dev);
df30a740 2568 myri10ge_free_irq(mgp);
0dcffac1
BG		 2569 for (i = 0; i < mgp->num_slices; i++)
2570 myri10ge_free_rings(&mgp->ss[i]);
0da34b6d
BG		 2571
2572 mgp->running = MYRI10GE_ETH_STOPPED;
2573 return 0;
2574}
2575
2576/* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2577 * backwards one at a time and handle ring wraps */
2578
2579static inline void
2580myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2581 struct mcp_kreq_ether_send *src, int cnt)
2582{
2583 int idx, starting_slot;
2584 starting_slot = tx->req;
2585 while (cnt > 1) {
2586 cnt--;
2587 idx = (starting_slot + cnt) & tx->mask;
2588 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2589 mb();
2590 }
2591}
2592
2593/*
2594 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2595 * at most 32 bytes at a time, so as to avoid involving the software
2596 * pio handler in the nic. We re-write the first segment's flags
2597 * to mark them valid only after writing the entire chain.
2598 */
2599
2600static inline void
2601myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2602 int cnt)
2603{
2604 int idx, i;
2605 struct mcp_kreq_ether_send __iomem *dstp, *dst;
2606 struct mcp_kreq_ether_send *srcp;
2607 u8 last_flags;
2608
2609 idx = tx->req & tx->mask;
2610
2611 last_flags = src->flags;
2612 src->flags = 0;
2613 mb();
2614 dst = dstp = &tx->lanai[idx];
2615 srcp = src;
2616
2617 if ((idx + cnt) < tx->mask) {
2618 for (i = 0; i < (cnt - 1); i += 2) {
2619 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2620 mb(); /* force write every 32 bytes */
2621 srcp += 2;
2622 dstp += 2;
2623 }
2624 } else {
2625 /* submit all but the first request, and ensure
2626 * that it is submitted below */
2627 myri10ge_submit_req_backwards(tx, src, cnt);
2628 i = 0;
2629 }
2630 if (i < cnt) {
2631 /* submit the first request */
2632 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2633 mb(); /* barrier before setting valid flag */
2634 }
2635
2636 /* re-write the last 32-bits with the valid flags */
2637 src->flags = last_flags;
40f6cff5 2638 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
0da34b6d
BG		 2639 tx->req += cnt;
2640 mb();
2641}
2642
0da34b6d
BG		 2643/*
2644 * Transmit a packet. We need to split the packet so that a single
b53bef84 2645 * segment does not cross myri10ge->tx_boundary, so this makes segment
0da34b6d
BG		 2646 * counting tricky. So rather than try to count segments up front, we
2647 * just give up if there are too few segments to hold a reasonably
2648 * fragmented packet currently available. If we run
2649 * out of segments while preparing a packet for DMA, we just linearize
2650 * it and try again.
2651 */
2652
61357325
SH		 2653static netdev_tx_t myri10ge_xmit(struct sk_buff *skb,
2654 struct net_device *dev)
0da34b6d
BG		 2655{
2656 struct myri10ge_priv *mgp = netdev_priv(dev);
b53bef84 2657 struct myri10ge_slice_state *ss;
0da34b6d 2658 struct mcp_kreq_ether_send *req;
b53bef84 2659 struct myri10ge_tx_buf *tx;
0da34b6d 2660 struct skb_frag_struct *frag;
236bb5e6 2661 struct netdev_queue *netdev_queue;
0da34b6d 2662 dma_addr_t bus;
40f6cff5
AV		 2663 u32 low;
2664 __be32 high_swapped;
0da34b6d
BG		 2665 unsigned int len;
2666 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
236bb5e6 2667 u16 pseudo_hdr_offset, cksum_offset, queue;
0da34b6d
BG		 2668 int cum_len, seglen, boundary, rdma_count;
2669 u8 flags, odd_flag;
2670
236bb5e6 2671 queue = skb_get_queue_mapping(skb);
236bb5e6
BG		 2672 ss = &mgp->ss[queue];
2673 netdev_queue = netdev_get_tx_queue(mgp->dev, queue);
b53bef84 2674 tx = &ss->tx;
236bb5e6 2675
0da34b6d
BG		 2676again:
2677 req = tx->req_list;
2678 avail = tx->mask - 1 - (tx->req - tx->done);
2679
2680 mss = 0;
2681 max_segments = MXGEFW_MAX_SEND_DESC;
2682
917690cd 2683 if (skb_is_gso(skb)) {
7967168c 2684 mss = skb_shinfo(skb)->gso_size;
917690cd 2685 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
0da34b6d 2686 }
0da34b6d
BG		 2687
2688 if ((unlikely(avail < max_segments))) {
2689 /* we are out of transmit resources */
b53bef84 2690 tx->stop_queue++;
236bb5e6 2691 netif_tx_stop_queue(netdev_queue);
5b548140 2692 return NETDEV_TX_BUSY;
0da34b6d
BG		 2693 }
2694
2695 /* Setup checksum offloading, if needed */
2696 cksum_offset = 0;
2697 pseudo_hdr_offset = 0;
2698 odd_flag = 0;
2699 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
84fa7933 2700 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
0d0b1672 2701 cksum_offset = skb_checksum_start_offset(skb);
ff1dcadb 2702 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
0da34b6d
BG		 2703 /* If the headers are excessively large, then we must
2704 * fall back to a software checksum */
4f93fde0
BG		 2705 if (unlikely(!mss && (cksum_offset > 255 ||
2706 pseudo_hdr_offset > 127))) {
84fa7933 2707 if (skb_checksum_help(skb))
0da34b6d
BG		 2708 goto drop;
2709 cksum_offset = 0;
2710 pseudo_hdr_offset = 0;
2711 } else {
0da34b6d
BG		 2712 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2713 flags |= MXGEFW_FLAGS_CKSUM;
2714 }
2715 }
2716
2717 cum_len = 0;
2718
0da34b6d
BG		 2719 if (mss) { /* TSO */
2720 /* this removes any CKSUM flag from before */
2721 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2722
2723 /* negative cum_len signifies to the
2724 * send loop that we are still in the
2725 * header portion of the TSO packet.
4f93fde0 2726 * TSO header can be at most 1KB long */
ab6a5bb6 2727 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
0da34b6d 2728
4f93fde0
BG		 2729 /* for IPv6 TSO, the checksum offset stores the
2730 * TCP header length, to save the firmware from
2731 * the need to parse the headers */
2732 if (skb_is_gso_v6(skb)) {
2733 cksum_offset = tcp_hdrlen(skb);
2734 /* Can only handle headers <= max_tso6 long */
2735 if (unlikely(-cum_len > mgp->max_tso6))
2736 return myri10ge_sw_tso(skb, dev);
2737 }
0da34b6d
BG		 2738 /* for TSO, pseudo_hdr_offset holds mss.
2739 * The firmware figures out where to put
2740 * the checksum by parsing the header. */
40f6cff5 2741 pseudo_hdr_offset = mss;
0da34b6d 2742 } else
0da34b6d
BG		 2743 /* Mark small packets, and pad out tiny packets */
2744 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2745 flags |= MXGEFW_FLAGS_SMALL;
2746
2747 /* pad frames to at least ETH_ZLEN bytes */
2748 if (unlikely(skb->len < ETH_ZLEN)) {
5b057c6b 2749 if (skb_padto(skb, ETH_ZLEN)) {
0da34b6d
BG		 2750 /* The packet is gone, so we must
2751 * return 0 */
b53bef84 2752 ss->stats.tx_dropped += 1;
6ed10654 2753 return NETDEV_TX_OK;
0da34b6d
BG		 2754 }
2755 /* adjust the len to account for the zero pad
2756 * so that the nic can know how long it is */
2757 skb->len = ETH_ZLEN;
2758 }
2759 }
2760
2761 /* map the skb for DMA */
e743d313 2762 len = skb_headlen(skb);
0da34b6d
BG		 2763 idx = tx->req & tx->mask;
2764 tx->info[idx].skb = skb;
2765 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
c755b4b6
FT		 2766 dma_unmap_addr_set(&tx->info[idx], bus, bus);
2767 dma_unmap_len_set(&tx->info[idx], len, len);
0da34b6d
BG		 2768
2769 frag_cnt = skb_shinfo(skb)->nr_frags;
2770 frag_idx = 0;
2771 count = 0;
2772 rdma_count = 0;
2773
2774 /* "rdma_count" is the number of RDMAs belonging to the
2775 * current packet BEFORE the current send request. For
2776 * non-TSO packets, this is equal to "count".
2777 * For TSO packets, rdma_count needs to be reset
2778 * to 0 after a segment cut.
2779 *
2780 * The rdma_count field of the send request is
2781 * the number of RDMAs of the packet starting at
2782 * that request. For TSO send requests with one ore more cuts
2783 * in the middle, this is the number of RDMAs starting
2784 * after the last cut in the request. All previous
2785 * segments before the last cut implicitly have 1 RDMA.
2786 *
2787 * Since the number of RDMAs is not known beforehand,
2788 * it must be filled-in retroactively - after each
2789 * segmentation cut or at the end of the entire packet.
2790 */
2791
2792 while (1) {
2793 /* Break the SKB or Fragment up into pieces which
b53bef84 2794 * do not cross mgp->tx_boundary */
0da34b6d
BG		 2795 low = MYRI10GE_LOWPART_TO_U32(bus);
2796 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2797 while (len) {
2798 u8 flags_next;
2799 int cum_len_next;
2800
2801 if (unlikely(count == max_segments))
2802 goto abort_linearize;
2803
b53bef84
BG		 2804 boundary =
2805 (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
0da34b6d
BG		 2806 seglen = boundary - low;
2807 if (seglen > len)
2808 seglen = len;
2809 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2810 cum_len_next = cum_len + seglen;
0da34b6d
BG		 2811 if (mss) { /* TSO */
2812 (req - rdma_count)->rdma_count = rdma_count + 1;
2813
2814 if (likely(cum_len >= 0)) { /* payload */
2815 int next_is_first, chop;
2816
2817 chop = (cum_len_next > mss);
2818 cum_len_next = cum_len_next % mss;
2819 next_is_first = (cum_len_next == 0);
2820 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2821 flags_next |= next_is_first *
2822 MXGEFW_FLAGS_FIRST;
2823 rdma_count |= -(chop | next_is_first);
2824 rdma_count += chop & !next_is_first;
2825 } else if (likely(cum_len_next >= 0)) { /* header ends */
2826 int small;
2827
2828 rdma_count = -1;
2829 cum_len_next = 0;
2830 seglen = -cum_len;
2831 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2832 flags_next = MXGEFW_FLAGS_TSO_PLD |
2833 MXGEFW_FLAGS_FIRST |
2834 (small * MXGEFW_FLAGS_SMALL);
2835 }
2836 }
0da34b6d
BG		 2837 req->addr_high = high_swapped;
2838 req->addr_low = htonl(low);
40f6cff5 2839 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
0da34b6d
BG		 2840 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2841 req->rdma_count = 1;
2842 req->length = htons(seglen);
2843 req->cksum_offset = cksum_offset;
2844 req->flags = flags | ((cum_len & 1) * odd_flag);
2845
2846 low += seglen;
2847 len -= seglen;
2848 cum_len = cum_len_next;
2849 flags = flags_next;
2850 req++;
2851 count++;
2852 rdma_count++;
4f93fde0
BG		 2853 if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2854 if (unlikely(cksum_offset > seglen))
2855 cksum_offset -= seglen;
2856 else
2857 cksum_offset = 0;
2858 }
0da34b6d
BG		 2859 }
2860 if (frag_idx == frag_cnt)
2861 break;
2862
2863 /* map next fragment for DMA */
2864 idx = (count + tx->req) & tx->mask;
2865 frag = &skb_shinfo(skb)->frags[frag_idx];
2866 frag_idx++;
2867 len = frag->size;
2868 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2869 len, PCI_DMA_TODEVICE);
c755b4b6
FT		 2870 dma_unmap_addr_set(&tx->info[idx], bus, bus);
2871 dma_unmap_len_set(&tx->info[idx], len, len);
0da34b6d
BG		 2872 }
2873
2874 (req - rdma_count)->rdma_count = rdma_count;
0da34b6d
BG		 2875 if (mss)
2876 do {
2877 req--;
2878 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2879 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2880 MXGEFW_FLAGS_FIRST)));
0da34b6d
BG		 2881 idx = ((count - 1) + tx->req) & tx->mask;
2882 tx->info[idx].last = 1;
e454e7e2 2883 myri10ge_submit_req(tx, tx->req_list, count);
236bb5e6
BG		 2884 /* if using multiple tx queues, make sure NIC polls the
2885 * current slice */
2886 if ((mgp->dev->real_num_tx_queues > 1) && tx->queue_active == 0) {
2887 tx->queue_active = 1;
2888 put_be32(htonl(1), tx->send_go);
8c2f5fa5 2889 mb();
6824a105 2890 mmiowb();
236bb5e6 2891 }
0da34b6d
BG		 2892 tx->pkt_start++;
2893 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
b53bef84 2894 tx->stop_queue++;
236bb5e6 2895 netif_tx_stop_queue(netdev_queue);
0da34b6d 2896 }
6ed10654 2897 return NETDEV_TX_OK;
0da34b6d
BG		 2898
2899abort_linearize:
2900 /* Free any DMA resources we've alloced and clear out the skb
2901 * slot so as to not trip up assertions, and to avoid a
2902 * double-free if linearizing fails */
2903
2904 last_idx = (idx + 1) & tx->mask;
2905 idx = tx->req & tx->mask;
2906 tx->info[idx].skb = NULL;
2907 do {
c755b4b6 2908 len = dma_unmap_len(&tx->info[idx], len);
0da34b6d
BG		 2909 if (len) {
2910 if (tx->info[idx].skb != NULL)
2911 pci_unmap_single(mgp->pdev,
c755b4b6 2912 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 2913 bus), len,
2914 PCI_DMA_TODEVICE);
2915 else
2916 pci_unmap_page(mgp->pdev,
c755b4b6 2917 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 2918 bus), len,
2919 PCI_DMA_TODEVICE);
c755b4b6 2920 dma_unmap_len_set(&tx->info[idx], len, 0);
0da34b6d
BG		 2921 tx->info[idx].skb = NULL;
2922 }
2923 idx = (idx + 1) & tx->mask;
2924 } while (idx != last_idx);
89114afd 2925 if (skb_is_gso(skb)) {
78ca90ea 2926 netdev_err(mgp->dev, "TSO but wanted to linearize?!?!?\n");
0da34b6d
BG		 2927 goto drop;
2928 }
2929
bec0e859 2930 if (skb_linearize(skb))
0da34b6d
BG		 2931 goto drop;
2932
b53bef84 2933 tx->linearized++;
0da34b6d
BG		 2934 goto again;
2935
2936drop:
2937 dev_kfree_skb_any(skb);
b53bef84 2938 ss->stats.tx_dropped += 1;
6ed10654 2939 return NETDEV_TX_OK;
0da34b6d
BG		 2940
2941}
2942
61357325
SH		 2943static netdev_tx_t myri10ge_sw_tso(struct sk_buff *skb,
2944 struct net_device *dev)
4f93fde0
BG		 2945{
2946 struct sk_buff *segs, *curr;
b53bef84 2947 struct myri10ge_priv *mgp = netdev_priv(dev);
d6279c88 2948 struct myri10ge_slice_state *ss;
61357325 2949 netdev_tx_t status;
4f93fde0
BG		 2950
2951 segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
801678c5 2952 if (IS_ERR(segs))
4f93fde0
BG		 2953 goto drop;
2954
2955 while (segs) {
2956 curr = segs;
2957 segs = segs->next;
2958 curr->next = NULL;
2959 status = myri10ge_xmit(curr, dev);
2960 if (status != 0) {
2961 dev_kfree_skb_any(curr);
2962 if (segs != NULL) {
2963 curr = segs;
2964 segs = segs->next;
2965 curr->next = NULL;
2966 dev_kfree_skb_any(segs);
2967 }
2968 goto drop;
2969 }
2970 }
2971 dev_kfree_skb_any(skb);
ec634fe3 2972 return NETDEV_TX_OK;
4f93fde0
BG		 2973
2974drop:
d6279c88 2975 ss = &mgp->ss[skb_get_queue_mapping(skb)];
4f93fde0 2976 dev_kfree_skb_any(skb);
d6279c88 2977 ss->stats.tx_dropped += 1;
ec634fe3 2978 return NETDEV_TX_OK;
4f93fde0
BG		 2979}
2980
c5f7ef72 2981static struct rtnl_link_stats64 *myri10ge_get_stats(struct net_device *dev,
2982 struct rtnl_link_stats64 *stats)
0da34b6d
BG		 2983{
2984 struct myri10ge_priv *mgp = netdev_priv(dev);
0dcffac1 2985 struct myri10ge_slice_netstats *slice_stats;
0dcffac1
BG		 2986 int i;
2987
59081825 2988 spin_lock(&mgp->stats_lock);
0dcffac1
BG		 2989 memset(stats, 0, sizeof(*stats));
2990 for (i = 0; i < mgp->num_slices; i++) {
2991 slice_stats = &mgp->ss[i].stats;
2992 stats->rx_packets += slice_stats->rx_packets;
2993 stats->tx_packets += slice_stats->tx_packets;
2994 stats->rx_bytes += slice_stats->rx_bytes;
2995 stats->tx_bytes += slice_stats->tx_bytes;
2996 stats->rx_dropped += slice_stats->rx_dropped;
2997 stats->tx_dropped += slice_stats->tx_dropped;
2998 }
59081825 2999 spin_unlock(&mgp->stats_lock);
0dcffac1 3000 return stats;
0da34b6d
BG		 3001}
3002
3003static void myri10ge_set_multicast_list(struct net_device *dev)
3004{
b53bef84 3005 struct myri10ge_priv *mgp = netdev_priv(dev);
85a7ea1b 3006 struct myri10ge_cmd cmd;
22bedad3 3007 struct netdev_hw_addr *ha;
6250223e 3008 __be32 data[2] = { 0, 0 };
85a7ea1b
BG		 3009 int err;
3010
0da34b6d
BG		 3011 /* can be called from atomic contexts,
3012 * pass 1 to force atomicity in myri10ge_send_cmd() */
85a7ea1b
BG		 3013 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
3014
3015 /* This firmware is known to not support multicast */
2f76216f 3016 if (!mgp->fw_multicast_support)
85a7ea1b
BG		 3017 return;
3018
3019 /* Disable multicast filtering */
3020
3021 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
3022 if (err != 0) {
78ca90ea
JP		 3023 netdev_err(dev, "Failed MXGEFW_ENABLE_ALLMULTI, error status: %d\n",
3024 err);
85a7ea1b
BG		 3025 goto abort;
3026 }
3027
2f76216f 3028 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
85a7ea1b
BG		 3029 /* request to disable multicast filtering, so quit here */
3030 return;
3031 }
3032
3033 /* Flush the filters */
3034
3035 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
3036 &cmd, 1);
3037 if (err != 0) {
78ca90ea
JP		 3038 netdev_err(dev, "Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS, error status: %d\n",
3039 err);
85a7ea1b
BG		 3040 goto abort;
3041 }
3042
3043 /* Walk the multicast list, and add each address */
22bedad3
JP		 3044 netdev_for_each_mc_addr(ha, dev) {
3045 memcpy(data, &ha->addr, 6);
40f6cff5
AV		 3046 cmd.data0 = ntohl(data[0]);
3047 cmd.data1 = ntohl(data[1]);
85a7ea1b
BG		 3048 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
3049 &cmd, 1);
3050
3051 if (err != 0) {
78ca90ea 3052 netdev_err(dev, "Failed MXGEFW_JOIN_MULTICAST_GROUP, error status:%d %pM\n",
22bedad3 3053 err, ha->addr);
85a7ea1b
BG		 3054 goto abort;
3055 }
3056 }
3057 /* Enable multicast filtering */
3058 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
3059 if (err != 0) {
78ca90ea
JP		 3060 netdev_err(dev, "Failed MXGEFW_DISABLE_ALLMULTI, error status: %d\n",
3061 err);
85a7ea1b
BG		 3062 goto abort;
3063 }
3064
3065 return;
3066
3067abort:
3068 return;
0da34b6d
BG		 3069}
3070
3071static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
3072{
3073 struct sockaddr *sa = addr;
3074 struct myri10ge_priv *mgp = netdev_priv(dev);
3075 int status;
3076
3077 if (!is_valid_ether_addr(sa->sa_data))
3078 return -EADDRNOTAVAIL;
3079
3080 status = myri10ge_update_mac_address(mgp, sa->sa_data);
3081 if (status != 0) {
78ca90ea
JP		 3082 netdev_err(dev, "changing mac address failed with %d\n",
3083 status);
0da34b6d
BG		 3084 return status;
3085 }
3086
3087 /* change the dev structure */
3088 memcpy(dev->dev_addr, sa->sa_data, 6);
3089 return 0;
3090}
3091
47c2cdf5
MM		 3092static u32 myri10ge_fix_features(struct net_device *dev, u32 features)
3093{
3094 if (!(features & NETIF_F_RXCSUM))
3095 features &= ~NETIF_F_LRO;
3096
3097 return features;
3098}
3099
0da34b6d
BG		 3100static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
3101{
3102 struct myri10ge_priv *mgp = netdev_priv(dev);
3103 int error = 0;
3104
3105 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
78ca90ea 3106 netdev_err(dev, "new mtu (%d) is not valid\n", new_mtu);
0da34b6d
BG		 3107 return -EINVAL;
3108 }
78ca90ea 3109 netdev_info(dev, "changing mtu from %d to %d\n", dev->mtu, new_mtu);
0da34b6d
BG		 3110 if (mgp->running) {
3111 /* if we change the mtu on an active device, we must
3112 * reset the device so the firmware sees the change */
3113 myri10ge_close(dev);
3114 dev->mtu = new_mtu;
3115 myri10ge_open(dev);
3116 } else
3117 dev->mtu = new_mtu;
3118
3119 return error;
3120}
3121
3122/*
3123 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
3124 * Only do it if the bridge is a root port since we don't want to disturb
3125 * any other device, except if forced with myri10ge_ecrc_enable > 1.
3126 */
3127
0da34b6d
BG		 3128static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
3129{
3130 struct pci_dev *bridge = mgp->pdev->bus->self;
3131 struct device *dev = &mgp->pdev->dev;
3132 unsigned cap;
3133 unsigned err_cap;
3134 u16 val;
3135 u8 ext_type;
3136 int ret;
3137
3138 if (!myri10ge_ecrc_enable || !bridge)
3139 return;
3140
3141 /* check that the bridge is a root port */
3142 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
3143 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
3144 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3145 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
3146 if (myri10ge_ecrc_enable > 1) {
eca3fd83 3147 struct pci_dev *prev_bridge, *old_bridge = bridge;
0da34b6d
BG		 3148
3149 /* Walk the hierarchy up to the root port
3150 * where ECRC has to be enabled */
3151 do {
eca3fd83 3152 prev_bridge = bridge;
0da34b6d 3153 bridge = bridge->bus->self;
eca3fd83 3154 if (!bridge || prev_bridge == bridge) {
0da34b6d
BG		 3155 dev_err(dev,
3156 "Failed to find root port"
3157 " to force ECRC\n");
3158 return;
3159 }
3160 cap =
3161 pci_find_capability(bridge, PCI_CAP_ID_EXP);
3162 pci_read_config_word(bridge,
3163 cap + PCI_CAP_FLAGS, &val);
3164 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3165 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
3166
3167 dev_info(dev,
3168 "Forcing ECRC on non-root port %s"
3169 " (enabling on root port %s)\n",
3170 pci_name(old_bridge), pci_name(bridge));
3171 } else {
3172 dev_err(dev,
3173 "Not enabling ECRC on non-root port %s\n",
3174 pci_name(bridge));
3175 return;
3176 }
3177 }
3178
3179 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
0da34b6d
BG		 3180 if (!cap)
3181 return;
3182
3183 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
3184 if (ret) {
3185 dev_err(dev, "failed reading ext-conf-space of %s\n",
3186 pci_name(bridge));
3187 dev_err(dev, "\t pci=nommconf in use? "
3188 "or buggy/incomplete/absent ACPI MCFG attr?\n");
3189 return;
3190 }
3191 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
3192 return;
3193
3194 err_cap |= PCI_ERR_CAP_ECRC_GENE;
3195 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
3196 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
0da34b6d
BG		 3197}
3198
3199/*
3200 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
3201 * when the PCI-E Completion packets are aligned on an 8-byte
3202 * boundary. Some PCI-E chip sets always align Completion packets; on
3203 * the ones that do not, the alignment can be enforced by enabling
3204 * ECRC generation (if supported).
3205 *
3206 * When PCI-E Completion packets are not aligned, it is actually more
3207 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
3208 *
3209 * If the driver can neither enable ECRC nor verify that it has
3210 * already been enabled, then it must use a firmware image which works
0dcffac1 3211 * around unaligned completion packets (myri10ge_rss_ethp_z8e.dat), and it
0da34b6d 3212 * should also ensure that it never gives the device a Read-DMA which is
b53bef84 3213 * larger than 2KB by setting the tx_boundary to 2KB. If ECRC is
0dcffac1 3214 * enabled, then the driver should use the aligned (myri10ge_rss_eth_z8e.dat)
b53bef84 3215 * firmware image, and set tx_boundary to 4KB.
0da34b6d
BG		 3216 */
3217
5443e9ea 3218static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
0da34b6d 3219{
5443e9ea
BG		 3220 struct pci_dev *pdev = mgp->pdev;
3221 struct device *dev = &pdev->dev;
302d242c 3222 int status;
0da34b6d 3223
b53bef84 3224 mgp->tx_boundary = 4096;
5443e9ea
BG		 3225 /*
3226 * Verify the max read request size was set to 4KB
3227 * before trying the test with 4KB.
3228 */
302d242c
BG		 3229 status = pcie_get_readrq(pdev);
3230 if (status < 0) {
5443e9ea
BG		 3231 dev_err(dev, "Couldn't read max read req size: %d\n", status);
3232 goto abort;
3233 }
302d242c
BG		 3234 if (status != 4096) {
3235 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
b53bef84 3236 mgp->tx_boundary = 2048;
5443e9ea
BG		 3237 }
3238 /*
3239 * load the optimized firmware (which assumes aligned PCIe
3240 * completions) in order to see if it works on this host.
3241 */
7d351035 3242 set_fw_name(mgp, myri10ge_fw_aligned, false);
0dcffac1 3243 status = myri10ge_load_firmware(mgp, 1);
5443e9ea
BG		 3244 if (status != 0) {
3245 goto abort;
3246 }
3247
3248 /*
3249 * Enable ECRC if possible
3250 */
3251 myri10ge_enable_ecrc(mgp);
3252
3253 /*
3254 * Run a DMA test which watches for unaligned completions and
3255 * aborts on the first one seen.
3256 */
3257
3258 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
3259 if (status == 0)
3260 return; /* keep the aligned firmware */
3261
3262 if (status != -E2BIG)
3263 dev_warn(dev, "DMA test failed: %d\n", status);
3264 if (status == -ENOSYS)
3265 dev_warn(dev, "Falling back to ethp! "
3266 "Please install up to date fw\n");
3267abort:
3268 /* fall back to using the unaligned firmware */
b53bef84 3269 mgp->tx_boundary = 2048;
7d351035 3270 set_fw_name(mgp, myri10ge_fw_unaligned, false);
0da34b6d 3271
5443e9ea
BG		 3272}
3273
3274static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
3275{
2d90b0aa
BG		 3276 int overridden = 0;
3277
0da34b6d 3278 if (myri10ge_force_firmware == 0) {
ce7f9368
BG		 3279 int link_width, exp_cap;
3280 u16 lnk;
3281
3282 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
3283 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
3284 link_width = (lnk >> 4) & 0x3f;
3285
ce7f9368
BG		 3286 /* Check to see if Link is less than 8 or if the
3287 * upstream bridge is known to provide aligned
3288 * completions */
3289 if (link_width < 8) {
3290 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
3291 link_width);
b53bef84 3292 mgp->tx_boundary = 4096;
7d351035 3293 set_fw_name(mgp, myri10ge_fw_aligned, false);
5443e9ea
BG		 3294 } else {
3295 myri10ge_firmware_probe(mgp);
0da34b6d
BG		 3296 }
3297 } else {
3298 if (myri10ge_force_firmware == 1) {
3299 dev_info(&mgp->pdev->dev,
3300 "Assuming aligned completions (forced)\n");
b53bef84 3301 mgp->tx_boundary = 4096;
7d351035 3302 set_fw_name(mgp, myri10ge_fw_aligned, false);
0da34b6d
BG		 3303 } else {
3304 dev_info(&mgp->pdev->dev,
3305 "Assuming unaligned completions (forced)\n");
b53bef84 3306 mgp->tx_boundary = 2048;
7d351035 3307 set_fw_name(mgp, myri10ge_fw_unaligned, false);
0da34b6d
BG		 3308 }
3309 }
7d351035
RR		 3310
3311 kparam_block_sysfs_write(myri10ge_fw_name);
0da34b6d 3312 if (myri10ge_fw_name != NULL) {
7d351035
RR		 3313 char *fw_name = kstrdup(myri10ge_fw_name, GFP_KERNEL);
3314 if (fw_name) {
3315 overridden = 1;
3316 set_fw_name(mgp, fw_name, true);
3317 }
0da34b6d 3318 }
7d351035
RR		 3319 kparam_unblock_sysfs_write(myri10ge_fw_name);
3320
2d90b0aa
BG		 3321 if (mgp->board_number < MYRI10GE_MAX_BOARDS &&
3322 myri10ge_fw_names[mgp->board_number] != NULL &&
3323 strlen(myri10ge_fw_names[mgp->board_number])) {
7d351035 3324 set_fw_name(mgp, myri10ge_fw_names[mgp->board_number], false);
2d90b0aa
BG		 3325 overridden = 1;
3326 }
3327 if (overridden)
3328 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
3329 mgp->fw_name);
0da34b6d
BG		 3330}
3331
0da34b6d 3332#ifdef CONFIG_PM
0da34b6d
BG		 3333static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
3334{
3335 struct myri10ge_priv *mgp;
3336 struct net_device *netdev;
3337
3338 mgp = pci_get_drvdata(pdev);
3339 if (mgp == NULL)
3340 return -EINVAL;
3341 netdev = mgp->dev;
3342
3343 netif_device_detach(netdev);
3344 if (netif_running(netdev)) {
78ca90ea 3345 netdev_info(netdev, "closing\n");
0da34b6d
BG		 3346 rtnl_lock();
3347 myri10ge_close(netdev);
3348 rtnl_unlock();
3349 }
3350 myri10ge_dummy_rdma(mgp, 0);
83f6e152 3351 pci_save_state(pdev);
0da34b6d 3352 pci_disable_device(pdev);
1a63e846
BG		 3353
3354 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
0da34b6d
BG		 3355}
3356
3357static int myri10ge_resume(struct pci_dev *pdev)
3358{
3359 struct myri10ge_priv *mgp;
3360 struct net_device *netdev;
3361 int status;
3362 u16 vendor;
3363
3364 mgp = pci_get_drvdata(pdev);
3365 if (mgp == NULL)
3366 return -EINVAL;
3367 netdev = mgp->dev;
3368 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
3369 msleep(5); /* give card time to respond */
3370 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3371 if (vendor == 0xffff) {
78ca90ea 3372 netdev_err(mgp->dev, "device disappeared!\n");
0da34b6d
BG		 3373 return -EIO;
3374 }
83f6e152 3375
1d3c16a8 3376 pci_restore_state(pdev);
4c2248cc
BG		 3377
3378 status = pci_enable_device(pdev);
1a63e846 3379 if (status) {
4c2248cc 3380 dev_err(&pdev->dev, "failed to enable device\n");
1a63e846 3381 return status;
4c2248cc
BG		 3382 }
3383
0da34b6d
BG		 3384 pci_set_master(pdev);
3385
0da34b6d 3386 myri10ge_reset(mgp);
013b68bf 3387 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 3388
3389 /* Save configuration space to be restored if the
3390 * nic resets due to a parity error */
83f6e152 3391 pci_save_state(pdev);
0da34b6d
BG		 3392
3393 if (netif_running(netdev)) {
3394 rtnl_lock();
df30a740 3395 status = myri10ge_open(netdev);
0da34b6d 3396 rtnl_unlock();
df30a740
BG		 3397 if (status != 0)
3398 goto abort_with_enabled;
3399
0da34b6d
BG		 3400 }
3401 netif_device_attach(netdev);
3402
3403 return 0;
3404
4c2248cc
BG		 3405abort_with_enabled:
3406 pci_disable_device(pdev);
0da34b6d
BG		 3407 return -EIO;
3408
3409}
0da34b6d
BG		 3410#endif /* CONFIG_PM */
3411
3412static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
3413{
3414 struct pci_dev *pdev = mgp->pdev;
3415 int vs = mgp->vendor_specific_offset;
3416 u32 reboot;
3417
3418 /*enter read32 mode */
3419 pci_write_config_byte(pdev, vs + 0x10, 0x3);
3420
3421 /*read REBOOT_STATUS (0xfffffff0) */
3422 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
3423 pci_read_config_dword(pdev, vs + 0x14, &reboot);
3424 return reboot;
3425}
3426
3427/*
3428 * This watchdog is used to check whether the board has suffered
3429 * from a parity error and needs to be recovered.
3430 */
c4028958 3431static void myri10ge_watchdog(struct work_struct *work)
0da34b6d 3432{
c4028958 3433 struct myri10ge_priv *mgp =
6250223e 3434 container_of(work, struct myri10ge_priv, watchdog_work);
b53bef84 3435 struct myri10ge_tx_buf *tx;
0da34b6d 3436 u32 reboot;
d0234215 3437 int status, rebooted;
0dcffac1 3438 int i;
0da34b6d
BG		 3439 u16 cmd, vendor;
3440
3441 mgp->watchdog_resets++;
3442 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
d0234215 3443 rebooted = 0;
0da34b6d
BG		 3444 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3445 /* Bus master DMA disabled? Check to see
3446 * if the card rebooted due to a parity error
3447 * For now, just report it */
3448 reboot = myri10ge_read_reboot(mgp);
78ca90ea
JP		 3449 netdev_err(mgp->dev, "NIC rebooted (0x%x),%s resetting\n",
3450 reboot,
3451 myri10ge_reset_recover ? "" : " not");
f181137f
BG		 3452 if (myri10ge_reset_recover == 0)
3453 return;
d0234215
BG		 3454 rtnl_lock();
3455 mgp->rebooted = 1;
3456 rebooted = 1;
3457 myri10ge_close(mgp->dev);
f181137f 3458 myri10ge_reset_recover--;
d0234215 3459 mgp->rebooted = 0;
0da34b6d
BG		 3460 /*
3461 * A rebooted nic will come back with config space as
3462 * it was after power was applied to PCIe bus.
3463 * Attempt to restore config space which was saved
3464 * when the driver was loaded, or the last time the
3465 * nic was resumed from power saving mode.
3466 */
83f6e152 3467 pci_restore_state(mgp->pdev);
7adda30c
BG		 3468
3469 /* save state again for accounting reasons */
83f6e152 3470 pci_save_state(mgp->pdev);
7adda30c 3471
0da34b6d
BG		 3472 } else {
3473 /* if we get back -1's from our slot, perhaps somebody
3474 * powered off our card. Don't try to reset it in
3475 * this case */
3476 if (cmd == 0xffff) {
3477 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3478 if (vendor == 0xffff) {
78ca90ea 3479 netdev_err(mgp->dev, "device disappeared!\n");
0da34b6d
BG		 3480 return;
3481 }
3482 }
3483 /* Perhaps it is a software error. Try to reset */
3484
78ca90ea 3485 netdev_err(mgp->dev, "device timeout, resetting\n");
0dcffac1
BG		 3486 for (i = 0; i < mgp->num_slices; i++) {
3487 tx = &mgp->ss[i].tx;
78ca90ea
JP		 3488 netdev_err(mgp->dev, "(%d): %d %d %d %d %d %d\n",
3489 i, tx->queue_active, tx->req,
3490 tx->done, tx->pkt_start, tx->pkt_done,
3491 (int)ntohl(mgp->ss[i].fw_stats->
3492 send_done_count));
0dcffac1 3493 msleep(2000);
78ca90ea
JP		 3494 netdev_info(mgp->dev, "(%d): %d %d %d %d %d %d\n",
3495 i, tx->queue_active, tx->req,
3496 tx->done, tx->pkt_start, tx->pkt_done,
3497 (int)ntohl(mgp->ss[i].fw_stats->
3498 send_done_count));
0dcffac1 3499 }
0da34b6d 3500 }
236bb5e6 3501
d0234215
BG		 3502 if (!rebooted) {
3503 rtnl_lock();
3504 myri10ge_close(mgp->dev);
3505 }
0dcffac1 3506 status = myri10ge_load_firmware(mgp, 1);
0da34b6d 3507 if (status != 0)
78ca90ea 3508 netdev_err(mgp->dev, "failed to load firmware\n");
0da34b6d
BG		 3509 else
3510 myri10ge_open(mgp->dev);
3511 rtnl_unlock();
3512}
3513
3514/*
3515 * We use our own timer routine rather than relying upon
3516 * netdev->tx_timeout because we have a very large hardware transmit
3517 * queue. Due to the large queue, the netdev->tx_timeout function
3518 * cannot detect a NIC with a parity error in a timely fashion if the
3519 * NIC is lightly loaded.
3520 */
3521static void myri10ge_watchdog_timer(unsigned long arg)
3522{
3523 struct myri10ge_priv *mgp;
b53bef84 3524 struct myri10ge_slice_state *ss;
d0234215 3525 int i, reset_needed, busy_slice_cnt;
626fda94 3526 u32 rx_pause_cnt;
d0234215 3527 u16 cmd;
0da34b6d
BG		 3528
3529 mgp = (struct myri10ge_priv *)arg;
c7dab99b 3530
0dcffac1 3531 rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
d0234215 3532 busy_slice_cnt = 0;
0dcffac1
BG		 3533 for (i = 0, reset_needed = 0;
3534 i < mgp->num_slices && reset_needed == 0; ++i) {
b53bef84 3535
0dcffac1
BG		 3536 ss = &mgp->ss[i];
3537 if (ss->rx_small.watchdog_needed) {
3538 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3539 mgp->small_bytes + MXGEFW_PAD,
3540 1);
3541 if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
3542 myri10ge_fill_thresh)
3543 ss->rx_small.watchdog_needed = 0;
3544 }
3545 if (ss->rx_big.watchdog_needed) {
3546 myri10ge_alloc_rx_pages(mgp, &ss->rx_big,
3547 mgp->big_bytes, 1);
3548 if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
3549 myri10ge_fill_thresh)
3550 ss->rx_big.watchdog_needed = 0;
3551 }
3552
3553 if (ss->tx.req != ss->tx.done &&
3554 ss->tx.done == ss->watchdog_tx_done &&
3555 ss->watchdog_tx_req != ss->watchdog_tx_done) {
3556 /* nic seems like it might be stuck.. */
3557 if (rx_pause_cnt != mgp->watchdog_pause) {
3558 if (net_ratelimit())
78ca90ea
JP		 3559 netdev_err(mgp->dev, "slice %d: TX paused, check link partner\n",
3560 i);
0dcffac1 3561 } else {
78ca90ea 3562 netdev_warn(mgp->dev, "slice %d stuck:", i);
0dcffac1
BG		 3563 reset_needed = 1;
3564 }
626fda94 3565 }
d0234215
BG		 3566 if (ss->watchdog_tx_done != ss->tx.done ||
3567 ss->watchdog_rx_done != ss->rx_done.cnt) {
3568 busy_slice_cnt++;
3569 }
0dcffac1
BG		 3570 ss->watchdog_tx_done = ss->tx.done;
3571 ss->watchdog_tx_req = ss->tx.req;
d0234215
BG		 3572 ss->watchdog_rx_done = ss->rx_done.cnt;
3573 }
3574 /* if we've sent or received no traffic, poll the NIC to
3575 * ensure it is still there. Otherwise, we risk not noticing
3576 * an error in a timely fashion */
3577 if (busy_slice_cnt == 0) {
3578 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3579 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3580 reset_needed = 1;
3581 }
626fda94 3582 }
626fda94 3583 mgp->watchdog_pause = rx_pause_cnt;
0dcffac1
BG		 3584
3585 if (reset_needed) {
3586 schedule_work(&mgp->watchdog_work);
3587 } else {
3588 /* rearm timer */
3589 mod_timer(&mgp->watchdog_timer,
3590 jiffies + myri10ge_watchdog_timeout * HZ);
3591 }
0da34b6d
BG		 3592}
3593
77929732
BG		 3594static void myri10ge_free_slices(struct myri10ge_priv *mgp)
3595{
3596 struct myri10ge_slice_state *ss;
3597 struct pci_dev *pdev = mgp->pdev;
3598 size_t bytes;
3599 int i;
3600
3601 if (mgp->ss == NULL)
3602 return;
3603
3604 for (i = 0; i < mgp->num_slices; i++) {
3605 ss = &mgp->ss[i];
3606 if (ss->rx_done.entry != NULL) {
3607 bytes = mgp->max_intr_slots *
3608 sizeof(*ss->rx_done.entry);
3609 dma_free_coherent(&pdev->dev, bytes,
3610 ss->rx_done.entry, ss->rx_done.bus);
3611 ss->rx_done.entry = NULL;
3612 }
3613 if (ss->fw_stats != NULL) {
3614 bytes = sizeof(*ss->fw_stats);
3615 dma_free_coherent(&pdev->dev, bytes,
3616 ss->fw_stats, ss->fw_stats_bus);
3617 ss->fw_stats = NULL;
cda6587c 3618 netif_napi_del(&ss->napi);
77929732
BG		 3619 }
3620 }
3621 kfree(mgp->ss);
3622 mgp->ss = NULL;
3623}
3624
3625static int myri10ge_alloc_slices(struct myri10ge_priv *mgp)
3626{
3627 struct myri10ge_slice_state *ss;
3628 struct pci_dev *pdev = mgp->pdev;
3629 size_t bytes;
3630 int i;
3631
3632 bytes = sizeof(*mgp->ss) * mgp->num_slices;
3633 mgp->ss = kzalloc(bytes, GFP_KERNEL);
3634 if (mgp->ss == NULL) {
3635 return -ENOMEM;
3636 }
3637
3638 for (i = 0; i < mgp->num_slices; i++) {
3639 ss = &mgp->ss[i];
3640 bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry);
3641 ss->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3642 &ss->rx_done.bus,
3643 GFP_KERNEL);
3644 if (ss->rx_done.entry == NULL)
3645 goto abort;
3646 memset(ss->rx_done.entry, 0, bytes);
3647 bytes = sizeof(*ss->fw_stats);
3648 ss->fw_stats = dma_alloc_coherent(&pdev->dev, bytes,
3649 &ss->fw_stats_bus,
3650 GFP_KERNEL);
3651 if (ss->fw_stats == NULL)
3652 goto abort;
3653 ss->mgp = mgp;
3654 ss->dev = mgp->dev;
3655 netif_napi_add(ss->dev, &ss->napi, myri10ge_poll,
3656 myri10ge_napi_weight);
3657 }
3658 return 0;
3659abort:
3660 myri10ge_free_slices(mgp);
3661 return -ENOMEM;
3662}
3663
3664/*
3665 * This function determines the number of slices supported.
25985edc 3666 * The number slices is the minimum of the number of CPUS,
77929732
BG		 3667 * the number of MSI-X irqs supported, the number of slices
3668 * supported by the firmware
3669 */
3670static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3671{
3672 struct myri10ge_cmd cmd;
3673 struct pci_dev *pdev = mgp->pdev;
3674 char *old_fw;
7d351035 3675 bool old_allocated;
77929732
BG		 3676 int i, status, ncpus, msix_cap;
3677
3678 mgp->num_slices = 1;
3679 msix_cap = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3680 ncpus = num_online_cpus();
3681
3682 if (myri10ge_max_slices == 1 || msix_cap == 0 ||
3683 (myri10ge_max_slices == -1 && ncpus < 2))
3684 return;
3685
3686 /* try to load the slice aware rss firmware */
3687 old_fw = mgp->fw_name;
7d351035
RR		 3688 old_allocated = mgp->fw_name_allocated;
3689 /* don't free old_fw if we override it. */
3690 mgp->fw_name_allocated = false;
3691
13b2738c
BG		 3692 if (myri10ge_fw_name != NULL) {
3693 dev_info(&mgp->pdev->dev, "overriding rss firmware to %s\n",
3694 myri10ge_fw_name);
7d351035 3695 set_fw_name(mgp, myri10ge_fw_name, false);
13b2738c 3696 } else if (old_fw == myri10ge_fw_aligned)
7d351035 3697 set_fw_name(mgp, myri10ge_fw_rss_aligned, false);
77929732 3698 else
7d351035 3699 set_fw_name(mgp, myri10ge_fw_rss_unaligned, false);
77929732
BG		 3700 status = myri10ge_load_firmware(mgp, 0);
3701 if (status != 0) {
3702 dev_info(&pdev->dev, "Rss firmware not found\n");
7d351035
RR		 3703 if (old_allocated)
3704 kfree(old_fw);
77929732
BG		 3705 return;
3706 }
3707
3708 /* hit the board with a reset to ensure it is alive */
3709 memset(&cmd, 0, sizeof(cmd));
3710 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
3711 if (status != 0) {
3712 dev_err(&mgp->pdev->dev, "failed reset\n");
3713 goto abort_with_fw;
77929732
BG		 3714 }
3715
3716 mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot);
3717
3718 /* tell it the size of the interrupt queues */
3719 cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot);
3720 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
3721 if (status != 0) {
3722 dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3723 goto abort_with_fw;
3724 }
3725
3726 /* ask the maximum number of slices it supports */
3727 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0);
3728 if (status != 0)
3729 goto abort_with_fw;
3730 else
3731 mgp->num_slices = cmd.data0;
3732
3733 /* Only allow multiple slices if MSI-X is usable */
3734 if (!myri10ge_msi) {
3735 goto abort_with_fw;
3736 }
3737
3738 /* if the admin did not specify a limit to how many
3739 * slices we should use, cap it automatically to the
3740 * number of CPUs currently online */
3741 if (myri10ge_max_slices == -1)
3742 myri10ge_max_slices = ncpus;
3743
3744 if (mgp->num_slices > myri10ge_max_slices)
3745 mgp->num_slices = myri10ge_max_slices;
3746
3747 /* Now try to allocate as many MSI-X vectors as we have
3748 * slices. We give up on MSI-X if we can only get a single
3749 * vector. */
3750
baeb2ffa
JP		 3751 mgp->msix_vectors = kcalloc(mgp->num_slices, sizeof(*mgp->msix_vectors),
3752 GFP_KERNEL);
77929732
BG		 3753 if (mgp->msix_vectors == NULL)
3754 goto disable_msix;
3755 for (i = 0; i < mgp->num_slices; i++) {
3756 mgp->msix_vectors[i].entry = i;
3757 }
3758
3759 while (mgp->num_slices > 1) {
3760 /* make sure it is a power of two */
3761 while (!is_power_of_2(mgp->num_slices))
3762 mgp->num_slices--;
3763 if (mgp->num_slices == 1)
3764 goto disable_msix;
3765 status = pci_enable_msix(pdev, mgp->msix_vectors,
3766 mgp->num_slices);
3767 if (status == 0) {
3768 pci_disable_msix(pdev);
7d351035
RR		 3769 if (old_allocated)
3770 kfree(old_fw);
77929732
BG		 3771 return;
3772 }
3773 if (status > 0)
3774 mgp->num_slices = status;
3775 else
3776 goto disable_msix;
3777 }
3778
3779disable_msix:
3780 if (mgp->msix_vectors != NULL) {
3781 kfree(mgp->msix_vectors);
3782 mgp->msix_vectors = NULL;
3783 }
3784
3785abort_with_fw:
3786 mgp->num_slices = 1;
7d351035 3787 set_fw_name(mgp, old_fw, old_allocated);
77929732
BG		 3788 myri10ge_load_firmware(mgp, 0);
3789}
77929732 3790
8126089f
SH		 3791static const struct net_device_ops myri10ge_netdev_ops = {
3792 .ndo_open = myri10ge_open,
3793 .ndo_stop = myri10ge_close,
3794 .ndo_start_xmit = myri10ge_xmit,
c5f7ef72 3795 .ndo_get_stats64 = myri10ge_get_stats,
8126089f
SH		 3796 .ndo_validate_addr = eth_validate_addr,
3797 .ndo_change_mtu = myri10ge_change_mtu,
47c2cdf5 3798 .ndo_fix_features = myri10ge_fix_features,
8126089f
SH		 3799 .ndo_set_multicast_list = myri10ge_set_multicast_list,
3800 .ndo_set_mac_address = myri10ge_set_mac_address,
3801};
3802
0da34b6d
BG		 3803static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3804{
3805 struct net_device *netdev;
3806 struct myri10ge_priv *mgp;
3807 struct device *dev = &pdev->dev;
0da34b6d
BG		 3808 int i;
3809 int status = -ENXIO;
0da34b6d 3810 int dac_enabled;
00b5e505 3811 unsigned hdr_offset, ss_offset;
2d90b0aa 3812 static int board_number;
0da34b6d 3813
236bb5e6 3814 netdev = alloc_etherdev_mq(sizeof(*mgp), MYRI10GE_MAX_SLICES);
0da34b6d
BG		 3815 if (netdev == NULL) {
3816 dev_err(dev, "Could not allocate ethernet device\n");
3817 return -ENOMEM;
3818 }
3819
b245fb67
MH		 3820 SET_NETDEV_DEV(netdev, &pdev->dev);
3821
0da34b6d 3822 mgp = netdev_priv(netdev);
0da34b6d
BG		 3823 mgp->dev = netdev;
3824 mgp->pdev = pdev;
0da34b6d
BG		 3825 mgp->pause = myri10ge_flow_control;
3826 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
c58ac5ca 3827 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
2d90b0aa 3828 mgp->board_number = board_number;
0da34b6d
BG		 3829 init_waitqueue_head(&mgp->down_wq);
3830
3831 if (pci_enable_device(pdev)) {
3832 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3833 status = -ENODEV;
3834 goto abort_with_netdev;
3835 }
0da34b6d
BG		 3836
3837 /* Find the vendor-specific cap so we can check
3838 * the reboot register later on */
3839 mgp->vendor_specific_offset
3840 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3841
3842 /* Set our max read request to 4KB */
302d242c 3843 status = pcie_set_readrq(pdev, 4096);
0da34b6d
BG		 3844 if (status != 0) {
3845 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3846 status);
e3fd5534 3847 goto abort_with_enabled;
0da34b6d
BG		 3848 }
3849
3850 pci_set_master(pdev);
3851 dac_enabled = 1;
6a35528a 3852 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
0da34b6d
BG		 3853 if (status != 0) {
3854 dac_enabled = 0;
3855 dev_err(&pdev->dev,
898eb71c
JP		 3856 "64-bit pci address mask was refused, "
3857 "trying 32-bit\n");
284901a9 3858 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
0da34b6d
BG		 3859 }
3860 if (status != 0) {
3861 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
e3fd5534 3862 goto abort_with_enabled;
0da34b6d 3863 }
6a35528a 3864 (void)pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
b10c0668
BG		 3865 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3866 &mgp->cmd_bus, GFP_KERNEL);
0da34b6d 3867 if (mgp->cmd == NULL)
e3fd5534 3868 goto abort_with_enabled;
0da34b6d 3869
0da34b6d
BG		 3870 mgp->board_span = pci_resource_len(pdev, 0);
3871 mgp->iomem_base = pci_resource_start(pdev, 0);
3872 mgp->mtrr = -1;
276e26c3 3873 mgp->wc_enabled = 0;
0da34b6d
BG		 3874#ifdef CONFIG_MTRR
3875 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3876 MTRR_TYPE_WRCOMB, 1);
276e26c3
BG		 3877 if (mgp->mtrr >= 0)
3878 mgp->wc_enabled = 1;
0da34b6d 3879#endif
c7f80993 3880 mgp->sram = ioremap_wc(mgp->iomem_base, mgp->board_span);
0da34b6d
BG		 3881 if (mgp->sram == NULL) {
3882 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3883 mgp->board_span, mgp->iomem_base);
3884 status = -ENXIO;
c7f80993 3885 goto abort_with_mtrr;
0da34b6d 3886 }
00b5e505
BG		 3887 hdr_offset =
3888 ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET)) & 0xffffc;
3889 ss_offset = hdr_offset + offsetof(struct mcp_gen_header, string_specs);
3890 mgp->sram_size = ntohl(__raw_readl(mgp->sram + ss_offset));
3891 if (mgp->sram_size > mgp->board_span ||
3892 mgp->sram_size <= MYRI10GE_FW_OFFSET) {
3893 dev_err(&pdev->dev,
3894 "invalid sram_size %dB or board span %ldB\n",
3895 mgp->sram_size, mgp->board_span);
3896 goto abort_with_ioremap;
3897 }
0da34b6d 3898 memcpy_fromio(mgp->eeprom_strings,
00b5e505 3899 mgp->sram + mgp->sram_size, MYRI10GE_EEPROM_STRINGS_SIZE);
0da34b6d
BG		 3900 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3901 status = myri10ge_read_mac_addr(mgp);
3902 if (status)
3903 goto abort_with_ioremap;
3904
3905 for (i = 0; i < ETH_ALEN; i++)
3906 netdev->dev_addr[i] = mgp->mac_addr[i];
3907
5443e9ea
BG		 3908 myri10ge_select_firmware(mgp);
3909
0dcffac1 3910 status = myri10ge_load_firmware(mgp, 1);
0da34b6d
BG		 3911 if (status != 0) {
3912 dev_err(&pdev->dev, "failed to load firmware\n");
0dcffac1
BG		 3913 goto abort_with_ioremap;
3914 }
3915 myri10ge_probe_slices(mgp);
3916 status = myri10ge_alloc_slices(mgp);
3917 if (status != 0) {
3918 dev_err(&pdev->dev, "failed to alloc slice state\n");
3919 goto abort_with_firmware;
0da34b6d 3920 }
c9920268
BH		 3921 netif_set_real_num_tx_queues(netdev, mgp->num_slices);
3922 netif_set_real_num_rx_queues(netdev, mgp->num_slices);
0da34b6d
BG		 3923 status = myri10ge_reset(mgp);
3924 if (status != 0) {
3925 dev_err(&pdev->dev, "failed reset\n");
0dcffac1 3926 goto abort_with_slices;
0da34b6d 3927 }
5dd2d332 3928#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 3929 myri10ge_setup_dca(mgp);
3930#endif
0da34b6d
BG		 3931 pci_set_drvdata(pdev, mgp);
3932 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3933 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3934 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3935 myri10ge_initial_mtu = 68;
8126089f
SH		 3936
3937 netdev->netdev_ops = &myri10ge_netdev_ops;
0da34b6d 3938 netdev->mtu = myri10ge_initial_mtu;
0da34b6d 3939 netdev->base_addr = mgp->iomem_base;
47c2cdf5
MM		 3940 netdev->hw_features = mgp->features | NETIF_F_LRO | NETIF_F_RXCSUM;
3941 netdev->features = netdev->hw_features;
236bb5e6 3942
0da34b6d
BG		 3943 if (dac_enabled)
3944 netdev->features |= NETIF_F_HIGHDMA;
0da34b6d 3945
dddc045e
BG		 3946 netdev->vlan_features |= mgp->features;
3947 if (mgp->fw_ver_tiny < 37)
3948 netdev->vlan_features &= ~NETIF_F_TSO6;
3949 if (mgp->fw_ver_tiny < 32)
3950 netdev->vlan_features &= ~NETIF_F_TSO;
3951
21d05db1
BG		 3952 /* make sure we can get an irq, and that MSI can be
3953 * setup (if available). Also ensure netdev->irq
3954 * is set to correct value if MSI is enabled */
3955 status = myri10ge_request_irq(mgp);
3956 if (status != 0)
3957 goto abort_with_firmware;
3958 netdev->irq = pdev->irq;
3959 myri10ge_free_irq(mgp);
3960
0da34b6d
BG		 3961 /* Save configuration space to be restored if the
3962 * nic resets due to a parity error */
83f6e152 3963 pci_save_state(pdev);
0da34b6d
BG		 3964
3965 /* Setup the watchdog timer */
3966 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3967 (unsigned long)mgp);
3968
59081825 3969 spin_lock_init(&mgp->stats_lock);
0da34b6d 3970 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
c4028958 3971 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
0da34b6d
BG		 3972 status = register_netdev(netdev);
3973 if (status != 0) {
3974 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
7adda30c 3975 goto abort_with_state;
0da34b6d 3976 }
0dcffac1
BG		 3977 if (mgp->msix_enabled)
3978 dev_info(dev, "%d MSI-X IRQs, tx bndry %d, fw %s, WC %s\n",
3979 mgp->num_slices, mgp->tx_boundary, mgp->fw_name,
3980 (mgp->wc_enabled ? "Enabled" : "Disabled"));
3981 else
3982 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3983 mgp->msi_enabled ? "MSI" : "xPIC",
3984 netdev->irq, mgp->tx_boundary, mgp->fw_name,
3985 (mgp->wc_enabled ? "Enabled" : "Disabled"));
0da34b6d 3986
2d90b0aa 3987 board_number++;
0da34b6d
BG		 3988 return 0;
3989
7adda30c 3990abort_with_state:
83f6e152 3991 pci_restore_state(pdev);
0da34b6d 3992
0dcffac1
BG		 3993abort_with_slices:
3994 myri10ge_free_slices(mgp);
3995
0da34b6d
BG		 3996abort_with_firmware:
3997 myri10ge_dummy_rdma(mgp, 0);
3998
0da34b6d 3999abort_with_ioremap:
0f840011
BG		 4000 if (mgp->mac_addr_string != NULL)
4001 dev_err(&pdev->dev,
4002 "myri10ge_probe() failed: MAC=%s, SN=%ld\n",
4003 mgp->mac_addr_string, mgp->serial_number);
0da34b6d
BG		 4004 iounmap(mgp->sram);
4005
c7f80993 4006abort_with_mtrr:
0da34b6d
BG		 4007#ifdef CONFIG_MTRR
4008 if (mgp->mtrr >= 0)
4009 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
4010#endif
b10c0668
BG		 4011 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
4012 mgp->cmd, mgp->cmd_bus);
0da34b6d 4013
e3fd5534
BG		 4014abort_with_enabled:
4015 pci_disable_device(pdev);
0da34b6d 4016
e3fd5534 4017abort_with_netdev:
7d351035 4018 set_fw_name(mgp, NULL, false);
0da34b6d
BG		 4019 free_netdev(netdev);
4020 return status;
4021}
4022
4023/*
4024 * myri10ge_remove
4025 *
4026 * Does what is necessary to shutdown one Myrinet device. Called
4027 * once for each Myrinet card by the kernel when a module is
4028 * unloaded.
4029 */
4030static void myri10ge_remove(struct pci_dev *pdev)
4031{
4032 struct myri10ge_priv *mgp;
4033 struct net_device *netdev;
0da34b6d
BG		 4034
4035 mgp = pci_get_drvdata(pdev);
4036 if (mgp == NULL)
4037 return;
4038
23f333a2 4039 cancel_work_sync(&mgp->watchdog_work);
0da34b6d
BG		 4040 netdev = mgp->dev;
4041 unregister_netdev(netdev);
0da34b6d 4042
5dd2d332 4043#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4044 myri10ge_teardown_dca(mgp);
4045#endif
0da34b6d
BG		 4046 myri10ge_dummy_rdma(mgp, 0);
4047
7adda30c 4048 /* avoid a memory leak */
83f6e152 4049 pci_restore_state(pdev);
7adda30c 4050
0da34b6d
BG		 4051 iounmap(mgp->sram);
4052
4053#ifdef CONFIG_MTRR
4054 if (mgp->mtrr >= 0)
4055 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
4056#endif
0dcffac1
BG		 4057 myri10ge_free_slices(mgp);
4058 if (mgp->msix_vectors != NULL)
4059 kfree(mgp->msix_vectors);
b10c0668
BG		 4060 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
4061 mgp->cmd, mgp->cmd_bus);
0da34b6d 4062
7d351035 4063 set_fw_name(mgp, NULL, false);
0da34b6d 4064 free_netdev(netdev);
e3fd5534 4065 pci_disable_device(pdev);
0da34b6d
BG		 4066 pci_set_drvdata(pdev, NULL);
4067}
4068
b10c0668 4069#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
a07bc1ff 4070#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
0da34b6d 4071
a3aa1884 4072static DEFINE_PCI_DEVICE_TABLE(myri10ge_pci_tbl) = {
b10c0668 4073 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
a07bc1ff
BG		 4074 {PCI_DEVICE
4075 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
0da34b6d
BG		 4076 {0},
4077};
4078
97131079
BG		 4079MODULE_DEVICE_TABLE(pci, myri10ge_pci_tbl);
4080
0da34b6d
BG		 4081static struct pci_driver myri10ge_driver = {
4082 .name = "myri10ge",
4083 .probe = myri10ge_probe,
4084 .remove = myri10ge_remove,
4085 .id_table = myri10ge_pci_tbl,
4086#ifdef CONFIG_PM
4087 .suspend = myri10ge_suspend,
4088 .resume = myri10ge_resume,
4089#endif
4090};
4091
5dd2d332 4092#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4093static int
4094myri10ge_notify_dca(struct notifier_block *nb, unsigned long event, void *p)
4095{
4096 int err = driver_for_each_device(&myri10ge_driver.driver,
4097 NULL, &event,
4098 myri10ge_notify_dca_device);
4099
4100 if (err)
4101 return NOTIFY_BAD;
4102 return NOTIFY_DONE;
4103}
4104
4105static struct notifier_block myri10ge_dca_notifier = {
4106 .notifier_call = myri10ge_notify_dca,
4107 .next = NULL,
4108 .priority = 0,
4109};
4ee2ac51 4110#endif /* CONFIG_MYRI10GE_DCA */
981813d8 4111
0da34b6d
BG		 4112static __init int myri10ge_init_module(void)
4113{
78ca90ea 4114 pr_info("Version %s\n", MYRI10GE_VERSION_STR);
0dcffac1 4115
236bb5e6 4116 if (myri10ge_rss_hash > MXGEFW_RSS_HASH_TYPE_MAX) {
78ca90ea
JP		 4117 pr_err("Illegal rssh hash type %d, defaulting to source port\n",
4118 myri10ge_rss_hash);
0dcffac1
BG		 4119 myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
4120 }
5dd2d332 4121#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4122 dca_register_notify(&myri10ge_dca_notifier);
4123#endif
236bb5e6
BG		 4124 if (myri10ge_max_slices > MYRI10GE_MAX_SLICES)
4125 myri10ge_max_slices = MYRI10GE_MAX_SLICES;
0dcffac1 4126
0da34b6d
BG		 4127 return pci_register_driver(&myri10ge_driver);
4128}
4129
4130module_init(myri10ge_init_module);
4131
4132static __exit void myri10ge_cleanup_module(void)
4133{
5dd2d332 4134#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4135 dca_unregister_notify(&myri10ge_dca_notifier);
4136#endif
0da34b6d
BG		 4137 pci_unregister_driver(&myri10ge_driver);
4138}
4139
4140module_exit(myri10ge_cleanup_module);
Linux kernel - Deliverables
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