[deliverable/linux.git] / drivers / net / myri10ge / myri10ge_mcp.h

#ifndef __MYRI10GE_MCP_H__
#define __MYRI10GE_MCP_H__

#define MXGEFW_VERSION_MAJOR	1
#define MXGEFW_VERSION_MINOR	4

/* 8 Bytes */
struct mcp_dma_addr {
	__be32 high;
	__be32 low;
};

/* 4 Bytes */
struct mcp_slot {
	__sum16 checksum;
	__be16 length;
};

/* 64 Bytes */
struct mcp_cmd {
	__be32 cmd;
	__be32 data0;		/* will be low portion if data > 32 bits */
	/* 8 */
	__be32 data1;		/* will be high portion if data > 32 bits */
	__be32 data2;		/* currently unused.. */
	/* 16 */
	struct mcp_dma_addr response_addr;
	/* 24 */
	u8 pad[40];
};

/* 8 Bytes */
struct mcp_cmd_response {
	__be32 data;
	__be32 result;
};

/*
 * flags used in mcp_kreq_ether_send_t:
 *
 * The SMALL flag is only needed in the first segment. It is raised
 * for packets that are total less or equal 512 bytes.
 *
 * The CKSUM flag must be set in all segments.
 *
 * The PADDED flags is set if the packet needs to be padded, and it
 * must be set for all segments.
 *
 * The  MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative
 * length of all previous segments was odd.
 */

#define MXGEFW_FLAGS_SMALL      0x1
#define MXGEFW_FLAGS_TSO_HDR    0x1
#define MXGEFW_FLAGS_FIRST      0x2
#define MXGEFW_FLAGS_ALIGN_ODD  0x4
#define MXGEFW_FLAGS_CKSUM      0x8
#define MXGEFW_FLAGS_TSO_LAST   0x8
#define MXGEFW_FLAGS_NO_TSO     0x10
#define MXGEFW_FLAGS_TSO_CHOP   0x10
#define MXGEFW_FLAGS_TSO_PLD    0x20

#define MXGEFW_SEND_SMALL_SIZE  1520
#define MXGEFW_MAX_MTU          9400

union mcp_pso_or_cumlen {
	u16 pseudo_hdr_offset;
	u16 cum_len;
};

#define	MXGEFW_MAX_SEND_DESC 12
#define MXGEFW_PAD	    2

/* 16 Bytes */
struct mcp_kreq_ether_send {
	__be32 addr_high;
	__be32 addr_low;
	__be16 pseudo_hdr_offset;
	__be16 length;
	u8 pad;
	u8 rdma_count;
	u8 cksum_offset;	/* where to start computing cksum */
	u8 flags;		/* as defined above */
};

/* 8 Bytes */
struct mcp_kreq_ether_recv {
	__be32 addr_high;
	__be32 addr_low;
};

/* Commands */

#define	MXGEFW_BOOT_HANDOFF	0xfc0000
#define	MXGEFW_BOOT_DUMMY_RDMA	0xfc01c0

#define	MXGEFW_ETH_CMD		0xf80000
#define	MXGEFW_ETH_SEND_4	0x200000
#define	MXGEFW_ETH_SEND_1	0x240000
#define	MXGEFW_ETH_SEND_2	0x280000
#define	MXGEFW_ETH_SEND_3	0x2c0000
#define	MXGEFW_ETH_RECV_SMALL	0x300000
#define	MXGEFW_ETH_RECV_BIG	0x340000

#define	MXGEFW_ETH_SEND(n)		(0x200000 + (((n) & 0x03) * 0x40000))
#define	MXGEFW_ETH_SEND_OFFSET(n)	(MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4)

enum myri10ge_mcp_cmd_type {
	MXGEFW_CMD_NONE = 0,
	/* Reset the mcp, it is left in a safe state, waiting
	 * for the driver to set all its parameters */
	MXGEFW_CMD_RESET,

	/* get the version number of the current firmware..
	 * (may be available in the eeprom strings..? */
	MXGEFW_GET_MCP_VERSION,

	/* Parameters which must be set by the driver before it can
	 * issue MXGEFW_CMD_ETHERNET_UP. They persist until the next
	 * MXGEFW_CMD_RESET is issued */

	MXGEFW_CMD_SET_INTRQ_DMA,
	MXGEFW_CMD_SET_BIG_BUFFER_SIZE,	/* in bytes, power of 2 */
	MXGEFW_CMD_SET_SMALL_BUFFER_SIZE,	/* in bytes */

	/* Parameters which refer to lanai SRAM addresses where the
	 * driver must issue PIO writes for various things */

	MXGEFW_CMD_GET_SEND_OFFSET,
	MXGEFW_CMD_GET_SMALL_RX_OFFSET,
	MXGEFW_CMD_GET_BIG_RX_OFFSET,
	MXGEFW_CMD_GET_IRQ_ACK_OFFSET,
	MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,

	/* Parameters which refer to rings stored on the MCP,
	 * and whose size is controlled by the mcp */

	MXGEFW_CMD_GET_SEND_RING_SIZE,	/* in bytes */
	MXGEFW_CMD_GET_RX_RING_SIZE,	/* in bytes */

	/* Parameters which refer to rings stored in the host,
	 * and whose size is controlled by the host.  Note that
	 * all must be physically contiguous and must contain
	 * a power of 2 number of entries.  */

	MXGEFW_CMD_SET_INTRQ_SIZE,	/* in bytes */

	/* command to bring ethernet interface up.  Above parameters
	 * (plus mtu & mac address) must have been exchanged prior
	 * to issuing this command  */
	MXGEFW_CMD_ETHERNET_UP,

	/* command to bring ethernet interface down.  No further sends
	 * or receives may be processed until an MXGEFW_CMD_ETHERNET_UP
	 * is issued, and all interrupt queues must be flushed prior
	 * to ack'ing this command */

	MXGEFW_CMD_ETHERNET_DOWN,

	/* commands the driver may issue live, without resetting
	 * the nic.  Note that increasing the mtu "live" should
	 * only be done if the driver has already supplied buffers
	 * sufficiently large to handle the new mtu.  Decreasing
	 * the mtu live is safe */

	MXGEFW_CMD_SET_MTU,
	MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET,	/* in microseconds */
	MXGEFW_CMD_SET_STATS_INTERVAL,	/* in microseconds */
	MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,	/* replaced by SET_STATS_DMA_V2 */

	MXGEFW_ENABLE_PROMISC,
	MXGEFW_DISABLE_PROMISC,
	MXGEFW_SET_MAC_ADDRESS,

	MXGEFW_ENABLE_FLOW_CONTROL,
	MXGEFW_DISABLE_FLOW_CONTROL,

	/* do a DMA test
	 * data0,data1 = DMA address
	 * data2       = RDMA length (MSH), WDMA length (LSH)
	 * command return data = repetitions (MSH), 0.5-ms ticks (LSH)
	 */
	MXGEFW_DMA_TEST,

	MXGEFW_ENABLE_ALLMULTI,
	MXGEFW_DISABLE_ALLMULTI,

	/* returns MXGEFW_CMD_ERROR_MULTICAST
	 * if there is no room in the cache
	 * data0,MSH(data1) = multicast group address */
	MXGEFW_JOIN_MULTICAST_GROUP,
	/* returns MXGEFW_CMD_ERROR_MULTICAST
	 * if the address is not in the cache,
	 * or is equal to FF-FF-FF-FF-FF-FF
	 * data0,MSH(data1) = multicast group address */
	MXGEFW_LEAVE_MULTICAST_GROUP,
	MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,

	MXGEFW_CMD_SET_STATS_DMA_V2,
	/* data0, data1 = bus addr,
	 * data2 = sizeof(struct mcp_irq_data) from driver point of view, allows
	 * adding new stuff to mcp_irq_data without changing the ABI */
};

enum myri10ge_mcp_cmd_status {
	MXGEFW_CMD_OK = 0,
	MXGEFW_CMD_UNKNOWN,
	MXGEFW_CMD_ERROR_RANGE,
	MXGEFW_CMD_ERROR_BUSY,
	MXGEFW_CMD_ERROR_EMPTY,
	MXGEFW_CMD_ERROR_CLOSED,
	MXGEFW_CMD_ERROR_HASH_ERROR,
	MXGEFW_CMD_ERROR_BAD_PORT,
	MXGEFW_CMD_ERROR_RESOURCES,
	MXGEFW_CMD_ERROR_MULTICAST
};

#define MXGEFW_OLD_IRQ_DATA_LEN 40

struct mcp_irq_data {
	/* add new counters at the beginning */
	__be32 future_use[5];
	__be32 dropped_multicast_filtered;
	/* 40 Bytes */
	__be32 send_done_count;

	__be32 link_up;
	__be32 dropped_link_overflow;
	__be32 dropped_link_error_or_filtered;
	__be32 dropped_runt;
	__be32 dropped_overrun;
	__be32 dropped_no_small_buffer;
	__be32 dropped_no_big_buffer;
	__be32 rdma_tags_available;

	u8 tx_stopped;
	u8 link_down;
	u8 stats_updated;
	u8 valid;
};

#endif				/* __MYRI10GE_MCP_H__ */
Commit	Line	Data
0da34b6d BG	1	#ifndef __MYRI10GE_MCP_H__
	2	#define __MYRI10GE_MCP_H__
	3
	4	#define MXGEFW_VERSION_MAJOR 1
	5	#define MXGEFW_VERSION_MINOR 4
	6
	7	/* 8 Bytes */
	8	struct mcp_dma_addr {
40f6cff5 AV	9	__be32 high;
40f6cff5 AV	10	__be32 low;
0da34b6d BG	11	};
	12
	13	/* 4 Bytes */
	14	struct mcp_slot {
40f6cff5 AV	15	__sum16 checksum;
40f6cff5 AV	16	__be16 length;
0da34b6d BG	17	};
	18
	19	/* 64 Bytes */
	20	struct mcp_cmd {
40f6cff5 AV	21	__be32 cmd;
40f6cff5 AV	22	__be32 data0; /* will be low portion if data > 32 bits */
0da34b6d	23	/* 8 */
40f6cff5 AV	24	__be32 data1; /* will be high portion if data > 32 bits */
40f6cff5 AV	25	__be32 data2; /* currently unused.. */
0da34b6d BG	26	/* 16 */
	27	struct mcp_dma_addr response_addr;
	28	/* 24 */
	29	u8 pad[40];
	30	};
	31
	32	/* 8 Bytes */
	33	struct mcp_cmd_response {
40f6cff5 AV	34	__be32 data;
40f6cff5 AV	35	__be32 result;
0da34b6d BG	36	};
0da34b6d BG	37
6ed14254	38	/*
0da34b6d	39	* flags used in mcp_kreq_ether_send_t:
6ed14254	40	*
0da34b6d BG	41	* The SMALL flag is only needed in the first segment. It is raised
0da34b6d BG	42	* for packets that are total less or equal 512 bytes.
6ed14254	43	*
0da34b6d	44	* The CKSUM flag must be set in all segments.
6ed14254	45	*
0da34b6d BG	46	* The PADDED flags is set if the packet needs to be padded, and it
0da34b6d BG	47	* must be set for all segments.
6ed14254	48	*
0da34b6d BG	49	* The MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative
	50	* length of all previous segments was odd.
	51	*/
	52
	53	#define MXGEFW_FLAGS_SMALL 0x1
	54	#define MXGEFW_FLAGS_TSO_HDR 0x1
	55	#define MXGEFW_FLAGS_FIRST 0x2
	56	#define MXGEFW_FLAGS_ALIGN_ODD 0x4
	57	#define MXGEFW_FLAGS_CKSUM 0x8
	58	#define MXGEFW_FLAGS_TSO_LAST 0x8
	59	#define MXGEFW_FLAGS_NO_TSO 0x10
	60	#define MXGEFW_FLAGS_TSO_CHOP 0x10
	61	#define MXGEFW_FLAGS_TSO_PLD 0x20
	62
	63	#define MXGEFW_SEND_SMALL_SIZE 1520
	64	#define MXGEFW_MAX_MTU 9400
	65
	66	union mcp_pso_or_cumlen {
	67	u16 pseudo_hdr_offset;
	68	u16 cum_len;
	69	};
	70
	71	#define MXGEFW_MAX_SEND_DESC 12
	72	#define MXGEFW_PAD 2
	73
	74	/* 16 Bytes */
	75	struct mcp_kreq_ether_send {
40f6cff5 AV	76	__be32 addr_high;
	77	__be32 addr_low;
	78	__be16 pseudo_hdr_offset;
	79	__be16 length;
0da34b6d BG	80	u8 pad;
	81	u8 rdma_count;
	82	u8 cksum_offset; /* where to start computing cksum */
	83	u8 flags; /* as defined above */
	84	};
	85
	86	/* 8 Bytes */
	87	struct mcp_kreq_ether_recv {
40f6cff5 AV	88	__be32 addr_high;
40f6cff5 AV	89	__be32 addr_low;
0da34b6d BG	90	};
	91
	92	/* Commands */
	93
e700f9f4 BG	94	#define MXGEFW_BOOT_HANDOFF 0xfc0000
	95	#define MXGEFW_BOOT_DUMMY_RDMA 0xfc01c0
	96
	97	#define MXGEFW_ETH_CMD 0xf80000
	98	#define MXGEFW_ETH_SEND_4 0x200000
	99	#define MXGEFW_ETH_SEND_1 0x240000
	100	#define MXGEFW_ETH_SEND_2 0x280000
	101	#define MXGEFW_ETH_SEND_3 0x2c0000
	102	#define MXGEFW_ETH_RECV_SMALL 0x300000
	103	#define MXGEFW_ETH_RECV_BIG 0x340000
	104
	105	#define MXGEFW_ETH_SEND(n) (0x200000 + (((n) & 0x03) * 0x40000))
	106	#define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4)
0da34b6d BG	107
	108	enum myri10ge_mcp_cmd_type {
	109	MXGEFW_CMD_NONE = 0,
	110	/* Reset the mcp, it is left in a safe state, waiting
	111	* for the driver to set all its parameters */
	112	MXGEFW_CMD_RESET,
	113
	114	/* get the version number of the current firmware..
	115	* (may be available in the eeprom strings..? */
	116	MXGEFW_GET_MCP_VERSION,
	117
	118	/* Parameters which must be set by the driver before it can
	119	* issue MXGEFW_CMD_ETHERNET_UP. They persist until the next
	120	* MXGEFW_CMD_RESET is issued */
	121
	122	MXGEFW_CMD_SET_INTRQ_DMA,
	123	MXGEFW_CMD_SET_BIG_BUFFER_SIZE, /* in bytes, power of 2 */
	124	MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, /* in bytes */
	125
6ed14254	126	/* Parameters which refer to lanai SRAM addresses where the
0da34b6d BG	127	* driver must issue PIO writes for various things */
	128
	129	MXGEFW_CMD_GET_SEND_OFFSET,
	130	MXGEFW_CMD_GET_SMALL_RX_OFFSET,
	131	MXGEFW_CMD_GET_BIG_RX_OFFSET,
	132	MXGEFW_CMD_GET_IRQ_ACK_OFFSET,
	133	MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
	134
	135	/* Parameters which refer to rings stored on the MCP,
	136	* and whose size is controlled by the mcp */
	137
	138	MXGEFW_CMD_GET_SEND_RING_SIZE, /* in bytes */
	139	MXGEFW_CMD_GET_RX_RING_SIZE, /* in bytes */
	140
	141	/* Parameters which refer to rings stored in the host,
	142	* and whose size is controlled by the host. Note that
6ed14254	143	* all must be physically contiguous and must contain
0da34b6d BG	144	* a power of 2 number of entries. */
	145
	146	MXGEFW_CMD_SET_INTRQ_SIZE, /* in bytes */
	147
	148	/* command to bring ethernet interface up. Above parameters
	149	* (plus mtu & mac address) must have been exchanged prior
	150	* to issuing this command */
	151	MXGEFW_CMD_ETHERNET_UP,
	152
	153	/* command to bring ethernet interface down. No further sends
	154	* or receives may be processed until an MXGEFW_CMD_ETHERNET_UP
	155	* is issued, and all interrupt queues must be flushed prior
	156	* to ack'ing this command */
	157
	158	MXGEFW_CMD_ETHERNET_DOWN,
	159
	160	/* commands the driver may issue live, without resetting
	161	* the nic. Note that increasing the mtu "live" should
	162	* only be done if the driver has already supplied buffers
	163	* sufficiently large to handle the new mtu. Decreasing
	164	* the mtu live is safe */
	165
	166	MXGEFW_CMD_SET_MTU,
	167	MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, /* in microseconds */
	168	MXGEFW_CMD_SET_STATS_INTERVAL, /* in microseconds */
85a7ea1b	169	MXGEFW_CMD_SET_STATS_DMA_OBSOLETE, /* replaced by SET_STATS_DMA_V2 */
0da34b6d BG	170
	171	MXGEFW_ENABLE_PROMISC,
	172	MXGEFW_DISABLE_PROMISC,
	173	MXGEFW_SET_MAC_ADDRESS,
	174
	175	MXGEFW_ENABLE_FLOW_CONTROL,
	176	MXGEFW_DISABLE_FLOW_CONTROL,
	177
	178	/* do a DMA test
	179	* data0,data1 = DMA address
	180	* data2 = RDMA length (MSH), WDMA length (LSH)
	181	* command return data = repetitions (MSH), 0.5-ms ticks (LSH)
	182	*/
85a7ea1b BG	183	MXGEFW_DMA_TEST,
	184
	185	MXGEFW_ENABLE_ALLMULTI,
	186	MXGEFW_DISABLE_ALLMULTI,
	187
	188	/* returns MXGEFW_CMD_ERROR_MULTICAST
	189	* if there is no room in the cache
	190	* data0,MSH(data1) = multicast group address */
	191	MXGEFW_JOIN_MULTICAST_GROUP,
	192	/* returns MXGEFW_CMD_ERROR_MULTICAST
	193	* if the address is not in the cache,
	194	* or is equal to FF-FF-FF-FF-FF-FF
	195	* data0,MSH(data1) = multicast group address */
	196	MXGEFW_LEAVE_MULTICAST_GROUP,
	197	MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
	198
	199	MXGEFW_CMD_SET_STATS_DMA_V2,
	200	/* data0, data1 = bus addr,
	201	* data2 = sizeof(struct mcp_irq_data) from driver point of view, allows
	202	* adding new stuff to mcp_irq_data without changing the ABI */
0da34b6d BG	203	};
	204
	205	enum myri10ge_mcp_cmd_status {
	206	MXGEFW_CMD_OK = 0,
	207	MXGEFW_CMD_UNKNOWN,
	208	MXGEFW_CMD_ERROR_RANGE,
	209	MXGEFW_CMD_ERROR_BUSY,
	210	MXGEFW_CMD_ERROR_EMPTY,
	211	MXGEFW_CMD_ERROR_CLOSED,
	212	MXGEFW_CMD_ERROR_HASH_ERROR,
	213	MXGEFW_CMD_ERROR_BAD_PORT,
85a7ea1b BG	214	MXGEFW_CMD_ERROR_RESOURCES,
85a7ea1b BG	215	MXGEFW_CMD_ERROR_MULTICAST
0da34b6d BG	216	};
0da34b6d BG	217
85a7ea1b BG	218	#define MXGEFW_OLD_IRQ_DATA_LEN 40
85a7ea1b BG	219
0da34b6d	220	struct mcp_irq_data {
85a7ea1b	221	/* add new counters at the beginning */
40f6cff5 AV	222	__be32 future_use[5];
40f6cff5 AV	223	__be32 dropped_multicast_filtered;
85a7ea1b	224	/* 40 Bytes */
40f6cff5 AV	225	__be32 send_done_count;
	226
	227	__be32 link_up;
	228	__be32 dropped_link_overflow;
	229	__be32 dropped_link_error_or_filtered;
	230	__be32 dropped_runt;
	231	__be32 dropped_overrun;
	232	__be32 dropped_no_small_buffer;
	233	__be32 dropped_no_big_buffer;
	234	__be32 rdma_tags_available;
0da34b6d BG	235
	236	u8 tx_stopped;
	237	u8 link_down;
	238	u8 stats_updated;
	239	u8 valid;
	240	};
	241
	242	#endif /* __MYRI10GE_MCP_H__ */