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sparc32: Implement more generic dma_*() interfaces.
[deliverable/linux.git] / drivers / net / myri_sbus.c
CommitLineData
a46c30fd 1/* myri_sbus.c: MyriCOM MyriNET SBUS card driver.
1da177e4 2 *
a46c30fd 3 * Copyright (C) 1996, 1999, 2006 David S. Miller (davem@davemloft.net)
1da177e4
LT		 4 */
5
6static char version[] =
a46c30fd 7 "myri_sbus.c:v2.0 June 23, 2006 David S. Miller (davem@davemloft.net)\n";
1da177e4
LT		 8
9#include <linux/module.h>
1da177e4
LT		 10#include <linux/errno.h>
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/fcntl.h>
14#include <linux/interrupt.h>
15#include <linux/ioport.h>
16#include <linux/in.h>
17#include <linux/slab.h>
18#include <linux/string.h>
19#include <linux/delay.h>
20#include <linux/init.h>
21#include <linux/netdevice.h>
22#include <linux/etherdevice.h>
23#include <linux/skbuff.h>
24#include <linux/bitops.h>
25
26#include <net/dst.h>
27#include <net/arp.h>
28#include <net/sock.h>
29#include <net/ipv6.h>
30
31#include <asm/system.h>
32#include <asm/io.h>
33#include <asm/dma.h>
34#include <asm/byteorder.h>
35#include <asm/idprom.h>
36#include <asm/sbus.h>
37#include <asm/openprom.h>
38#include <asm/oplib.h>
39#include <asm/auxio.h>
40#include <asm/pgtable.h>
41#include <asm/irq.h>
1da177e4
LT		 42
43#include "myri_sbus.h"
44#include "myri_code.h"
45
46/* #define DEBUG_DETECT */
47/* #define DEBUG_IRQ */
48/* #define DEBUG_TRANSMIT */
49/* #define DEBUG_RECEIVE */
50/* #define DEBUG_HEADER */
51
52#ifdef DEBUG_DETECT
53#define DET(x) printk x
54#else
55#define DET(x)
56#endif
57
58#ifdef DEBUG_IRQ
59#define DIRQ(x) printk x
60#else
61#define DIRQ(x)
62#endif
63
64#ifdef DEBUG_TRANSMIT
65#define DTX(x) printk x
66#else
67#define DTX(x)
68#endif
69
70#ifdef DEBUG_RECEIVE
71#define DRX(x) printk x
72#else
73#define DRX(x)
74#endif
75
76#ifdef DEBUG_HEADER
77#define DHDR(x) printk x
78#else
79#define DHDR(x)
80#endif
81
1da177e4
LT		 82static void myri_reset_off(void __iomem *lp, void __iomem *cregs)
83{
84 /* Clear IRQ mask. */
85 sbus_writel(0, lp + LANAI_EIMASK);
86
87 /* Turn RESET function off. */
88 sbus_writel(CONTROL_ROFF, cregs + MYRICTRL_CTRL);
89}
90
91static void myri_reset_on(void __iomem *cregs)
92{
93 /* Enable RESET function. */
94 sbus_writel(CONTROL_RON, cregs + MYRICTRL_CTRL);
95
96 /* Disable IRQ's. */
97 sbus_writel(CONTROL_DIRQ, cregs + MYRICTRL_CTRL);
98}
99
100static void myri_disable_irq(void __iomem *lp, void __iomem *cregs)
101{
102 sbus_writel(CONTROL_DIRQ, cregs + MYRICTRL_CTRL);
103 sbus_writel(0, lp + LANAI_EIMASK);
104 sbus_writel(ISTAT_HOST, lp + LANAI_ISTAT);
105}
106
107static void myri_enable_irq(void __iomem *lp, void __iomem *cregs)
108{
109 sbus_writel(CONTROL_EIRQ, cregs + MYRICTRL_CTRL);
110 sbus_writel(ISTAT_HOST, lp + LANAI_EIMASK);
111}
112
113static inline void bang_the_chip(struct myri_eth *mp)
114{
115 struct myri_shmem __iomem *shmem = mp->shmem;
116 void __iomem *cregs = mp->cregs;
117
118 sbus_writel(1, &shmem->send);
119 sbus_writel(CONTROL_WON, cregs + MYRICTRL_CTRL);
120}
121
122static int myri_do_handshake(struct myri_eth *mp)
123{
124 struct myri_shmem __iomem *shmem = mp->shmem;
125 void __iomem *cregs = mp->cregs;
126 struct myri_channel __iomem *chan = &shmem->channel;
127 int tick = 0;
128
129 DET(("myri_do_handshake: "));
130 if (sbus_readl(&chan->state) == STATE_READY) {
131 DET(("Already STATE_READY, failed.\n"));
132 return -1; /* We're hosed... */
133 }
134
135 myri_disable_irq(mp->lregs, cregs);
136
9db7720c 137 while (tick++ < 25) {
1da177e4
LT		 138 u32 softstate;
139
140 /* Wake it up. */
141 DET(("shakedown, CONTROL_WON, "));
142 sbus_writel(1, &shmem->shakedown);
143 sbus_writel(CONTROL_WON, cregs + MYRICTRL_CTRL);
144
145 softstate = sbus_readl(&chan->state);
146 DET(("chanstate[%08x] ", softstate));
147 if (softstate == STATE_READY) {
148 DET(("wakeup successful, "));
149 break;
150 }
151
152 if (softstate != STATE_WFN) {
153 DET(("not WFN setting that, "));
154 sbus_writel(STATE_WFN, &chan->state);
155 }
156
157 udelay(20);
158 }
159
160 myri_enable_irq(mp->lregs, cregs);
161
162 if (tick > 25) {
163 DET(("25 ticks we lose, failure.\n"));
164 return -1;
165 }
166 DET(("success\n"));
167 return 0;
168}
169
b48194bf 170static int __devinit myri_load_lanai(struct myri_eth *mp)
1da177e4
LT		 171{
172 struct net_device *dev = mp->dev;
173 struct myri_shmem __iomem *shmem = mp->shmem;
174 void __iomem *rptr;
175 int i;
176
177 myri_disable_irq(mp->lregs, mp->cregs);
178 myri_reset_on(mp->cregs);
179
180 rptr = mp->lanai;
181 for (i = 0; i < mp->eeprom.ramsz; i++)
182 sbus_writeb(0, rptr + i);
183
184 if (mp->eeprom.cpuvers >= CPUVERS_3_0)
185 sbus_writel(mp->eeprom.cval, mp->lregs + LANAI_CVAL);
186
187 /* Load executable code. */
188 for (i = 0; i < sizeof(lanai4_code); i++)
189 sbus_writeb(lanai4_code[i], rptr + (lanai4_code_off * 2) + i);
190
191 /* Load data segment. */
192 for (i = 0; i < sizeof(lanai4_data); i++)
193 sbus_writeb(lanai4_data[i], rptr + (lanai4_data_off * 2) + i);
194
195 /* Set device address. */
196 sbus_writeb(0, &shmem->addr[0]);
197 sbus_writeb(0, &shmem->addr[1]);
198 for (i = 0; i < 6; i++)
199 sbus_writeb(dev->dev_addr[i],
200 &shmem->addr[i + 2]);
201
202 /* Set SBUS bursts and interrupt mask. */
203 sbus_writel(((mp->myri_bursts & 0xf8) >> 3), &shmem->burst);
204 sbus_writel(SHMEM_IMASK_RX, &shmem->imask);
205
206 /* Release the LANAI. */
207 myri_disable_irq(mp->lregs, mp->cregs);
208 myri_reset_off(mp->lregs, mp->cregs);
209 myri_disable_irq(mp->lregs, mp->cregs);
210
211 /* Wait for the reset to complete. */
212 for (i = 0; i < 5000; i++) {
213 if (sbus_readl(&shmem->channel.state) != STATE_READY)
214 break;
215 else
216 udelay(10);
217 }
218
219 if (i == 5000)
220 printk(KERN_ERR "myricom: Chip would not reset after firmware load.\n");
221
222 i = myri_do_handshake(mp);
223 if (i)
224 printk(KERN_ERR "myricom: Handshake with LANAI failed.\n");
225
226 if (mp->eeprom.cpuvers == CPUVERS_4_0)
227 sbus_writel(0, mp->lregs + LANAI_VERS);
228
229 return i;
230}
231
232static void myri_clean_rings(struct myri_eth *mp)
233{
234 struct sendq __iomem *sq = mp->sq;
235 struct recvq __iomem *rq = mp->rq;
236 int i;
237
238 sbus_writel(0, &rq->tail);
239 sbus_writel(0, &rq->head);
240 for (i = 0; i < (RX_RING_SIZE+1); i++) {
241 if (mp->rx_skbs[i] != NULL) {
242 struct myri_rxd __iomem *rxd = &rq->myri_rxd[i];
243 u32 dma_addr;
244
245 dma_addr = sbus_readl(&rxd->myri_scatters[0].addr);
7a715f46
DM		 246 sbus_unmap_single(&mp->myri_sdev->ofdev.dev, dma_addr,
247 RX_ALLOC_SIZE, SBUS_DMA_FROMDEVICE);
1da177e4
LT		 248 dev_kfree_skb(mp->rx_skbs[i]);
249 mp->rx_skbs[i] = NULL;
250 }
251 }
252
253 mp->tx_old = 0;
254 sbus_writel(0, &sq->tail);
255 sbus_writel(0, &sq->head);
256 for (i = 0; i < TX_RING_SIZE; i++) {
257 if (mp->tx_skbs[i] != NULL) {
258 struct sk_buff *skb = mp->tx_skbs[i];
259 struct myri_txd __iomem *txd = &sq->myri_txd[i];
260 u32 dma_addr;
261
262 dma_addr = sbus_readl(&txd->myri_gathers[0].addr);
7a715f46
DM		 263 sbus_unmap_single(&mp->myri_sdev->ofdev.dev, dma_addr,
264 (skb->len + 3) & ~3,
265 SBUS_DMA_TODEVICE);
1da177e4
LT		 266 dev_kfree_skb(mp->tx_skbs[i]);
267 mp->tx_skbs[i] = NULL;
268 }
269 }
270}
271
272static void myri_init_rings(struct myri_eth *mp, int from_irq)
273{
274 struct recvq __iomem *rq = mp->rq;
275 struct myri_rxd __iomem *rxd = &rq->myri_rxd[0];
276 struct net_device *dev = mp->dev;
9e24974d 277 gfp_t gfp_flags = GFP_KERNEL;
1da177e4
LT		 278 int i;
279
280 if (from_irq || in_interrupt())
281 gfp_flags = GFP_ATOMIC;
282
283 myri_clean_rings(mp);
284 for (i = 0; i < RX_RING_SIZE; i++) {
285 struct sk_buff *skb = myri_alloc_skb(RX_ALLOC_SIZE, gfp_flags);
286 u32 dma_addr;
287
288 if (!skb)
289 continue;
290 mp->rx_skbs[i] = skb;
291 skb->dev = dev;
292 skb_put(skb, RX_ALLOC_SIZE);
293
7a715f46
DM		 294 dma_addr = sbus_map_single(&mp->myri_sdev->ofdev.dev,
295 skb->data, RX_ALLOC_SIZE,
296 SBUS_DMA_FROMDEVICE);
1da177e4
LT		 297 sbus_writel(dma_addr, &rxd[i].myri_scatters[0].addr);
298 sbus_writel(RX_ALLOC_SIZE, &rxd[i].myri_scatters[0].len);
299 sbus_writel(i, &rxd[i].ctx);
300 sbus_writel(1, &rxd[i].num_sg);
301 }
302 sbus_writel(0, &rq->head);
303 sbus_writel(RX_RING_SIZE, &rq->tail);
304}
305
306static int myri_init(struct myri_eth *mp, int from_irq)
307{
308 myri_init_rings(mp, from_irq);
309 return 0;
310}
311
312static void myri_is_not_so_happy(struct myri_eth *mp)
313{
314}
315
316#ifdef DEBUG_HEADER
317static void dump_ehdr(struct ethhdr *ehdr)
318{
0795af57
JP		 319 DECLARE_MAC_BUF(mac);
320 DECLARE_MAC_BUF(mac2);
321 printk("ehdr[h_dst(%s)"
322 "h_source(%s)"
323 "h_proto(%04x)]\n",
324 print_mac(mac, ehdr->h_dest), print_mac(mac2, ehdr->h_source),
1da177e4
LT		 325 ehdr->h_proto);
326}
327
328static void dump_ehdr_and_myripad(unsigned char *stuff)
329{
330 struct ethhdr *ehdr = (struct ethhdr *) (stuff + 2);
331
332 printk("pad[%02x:%02x]", stuff[0], stuff[1]);
0795af57 333 dump_ehdr(ehdr);
1da177e4
LT		 334}
335#endif
336
337static void myri_tx(struct myri_eth *mp, struct net_device *dev)
338{
339 struct sendq __iomem *sq= mp->sq;
340 int entry = mp->tx_old;
341 int limit = sbus_readl(&sq->head);
342
343 DTX(("entry[%d] limit[%d] ", entry, limit));
344 if (entry == limit)
345 return;
346 while (entry != limit) {
347 struct sk_buff *skb = mp->tx_skbs[entry];
348 u32 dma_addr;
349
350 DTX(("SKB[%d] ", entry));
351 dma_addr = sbus_readl(&sq->myri_txd[entry].myri_gathers[0].addr);
7a715f46
DM		 352 sbus_unmap_single(&mp->myri_sdev->ofdev.dev, dma_addr,
353 skb->len, SBUS_DMA_TODEVICE);
1da177e4
LT		 354 dev_kfree_skb(skb);
355 mp->tx_skbs[entry] = NULL;
09f75cd7 356 dev->stats.tx_packets++;
1da177e4
LT		 357 entry = NEXT_TX(entry);
358 }
359 mp->tx_old = entry;
360}
361
6aa20a22 362/* Determine the packet's protocol ID. The rule here is that we
1da177e4
LT		 363 * assume 802.3 if the type field is short enough to be a length.
364 * This is normal practice and works for any 'now in use' protocol.
365 */
ab611487 366static __be16 myri_type_trans(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 367{
368 struct ethhdr *eth;
369 unsigned char *rawp;
6aa20a22 370
48d49d0c 371 skb_set_mac_header(skb, MYRI_PAD_LEN);
1da177e4
LT		 372 skb_pull(skb, dev->hard_header_len);
373 eth = eth_hdr(skb);
6aa20a22 374
1da177e4
LT		 375#ifdef DEBUG_HEADER
376 DHDR(("myri_type_trans: "));
377 dump_ehdr(eth);
378#endif
379 if (*eth->h_dest & 1) {
380 if (memcmp(eth->h_dest, dev->broadcast, ETH_ALEN)==0)
381 skb->pkt_type = PACKET_BROADCAST;
382 else
383 skb->pkt_type = PACKET_MULTICAST;
384 } else if (dev->flags & (IFF_PROMISC|IFF_ALLMULTI)) {
385 if (memcmp(eth->h_dest, dev->dev_addr, ETH_ALEN))
386 skb->pkt_type = PACKET_OTHERHOST;
387 }
6aa20a22 388
1da177e4
LT		 389 if (ntohs(eth->h_proto) >= 1536)
390 return eth->h_proto;
6aa20a22 391
1da177e4 392 rawp = skb->data;
6aa20a22 393
1da177e4
LT		 394 /* This is a magic hack to spot IPX packets. Older Novell breaks
395 * the protocol design and runs IPX over 802.3 without an 802.2 LLC
396 * layer. We look for FFFF which isn't a used 802.2 SSAP/DSAP. This
397 * won't work for fault tolerant netware but does for the rest.
398 */
399 if (*(unsigned short *)rawp == 0xFFFF)
400 return htons(ETH_P_802_3);
6aa20a22 401
1da177e4
LT		 402 /* Real 802.2 LLC */
403 return htons(ETH_P_802_2);
404}
405
406static void myri_rx(struct myri_eth *mp, struct net_device *dev)
407{
408 struct recvq __iomem *rq = mp->rq;
409 struct recvq __iomem *rqa = mp->rqack;
410 int entry = sbus_readl(&rqa->head);
411 int limit = sbus_readl(&rqa->tail);
412 int drops;
413
414 DRX(("entry[%d] limit[%d] ", entry, limit));
415 if (entry == limit)
416 return;
417 drops = 0;
418 DRX(("\n"));
419 while (entry != limit) {
420 struct myri_rxd __iomem *rxdack = &rqa->myri_rxd[entry];
421 u32 csum = sbus_readl(&rxdack->csum);
422 int len = sbus_readl(&rxdack->myri_scatters[0].len);
423 int index = sbus_readl(&rxdack->ctx);
424 struct myri_rxd __iomem *rxd = &rq->myri_rxd[sbus_readl(&rq->tail)];
425 struct sk_buff *skb = mp->rx_skbs[index];
426
427 /* Ack it. */
428 sbus_writel(NEXT_RX(entry), &rqa->head);
429
430 /* Check for errors. */
431 DRX(("rxd[%d]: %p len[%d] csum[%08x] ", entry, rxd, len, csum));
7a715f46 432 sbus_dma_sync_single_for_cpu(&mp->myri_sdev->ofdev.dev,
1da177e4
LT		 433 sbus_readl(&rxd->myri_scatters[0].addr),
434 RX_ALLOC_SIZE, SBUS_DMA_FROMDEVICE);
435 if (len < (ETH_HLEN + MYRI_PAD_LEN) || (skb->data[0] != MYRI_PAD_LEN)) {
436 DRX(("ERROR["));
09f75cd7 437 dev->stats.rx_errors++;
1da177e4
LT		 438 if (len < (ETH_HLEN + MYRI_PAD_LEN)) {
439 DRX(("BAD_LENGTH] "));
09f75cd7 440 dev->stats.rx_length_errors++;
1da177e4
LT		 441 } else {
442 DRX(("NO_PADDING] "));
09f75cd7 443 dev->stats.rx_frame_errors++;
1da177e4
LT		 444 }
445
446 /* Return it to the LANAI. */
447 drop_it:
448 drops++;
449 DRX(("DROP "));
09f75cd7 450 dev->stats.rx_dropped++;
7a715f46 451 sbus_dma_sync_single_for_device(&mp->myri_sdev->ofdev.dev,
1da177e4
LT		 452 sbus_readl(&rxd->myri_scatters[0].addr),
453 RX_ALLOC_SIZE,
454 SBUS_DMA_FROMDEVICE);
455 sbus_writel(RX_ALLOC_SIZE, &rxd->myri_scatters[0].len);
456 sbus_writel(index, &rxd->ctx);
457 sbus_writel(1, &rxd->num_sg);
458 sbus_writel(NEXT_RX(sbus_readl(&rq->tail)), &rq->tail);
459 goto next;
460 }
461
462 DRX(("len[%d] ", len));
463 if (len > RX_COPY_THRESHOLD) {
464 struct sk_buff *new_skb;
465 u32 dma_addr;
466
467 DRX(("BIGBUFF "));
468 new_skb = myri_alloc_skb(RX_ALLOC_SIZE, GFP_ATOMIC);
469 if (new_skb == NULL) {
470 DRX(("skb_alloc(FAILED) "));
471 goto drop_it;
472 }
7a715f46 473 sbus_unmap_single(&mp->myri_sdev->ofdev.dev,
1da177e4
LT		 474 sbus_readl(&rxd->myri_scatters[0].addr),
475 RX_ALLOC_SIZE,
476 SBUS_DMA_FROMDEVICE);
477 mp->rx_skbs[index] = new_skb;
478 new_skb->dev = dev;
479 skb_put(new_skb, RX_ALLOC_SIZE);
7a715f46 480 dma_addr = sbus_map_single(&mp->myri_sdev->ofdev.dev,
1da177e4
LT		 481 new_skb->data,
482 RX_ALLOC_SIZE,
483 SBUS_DMA_FROMDEVICE);
484 sbus_writel(dma_addr, &rxd->myri_scatters[0].addr);
485 sbus_writel(RX_ALLOC_SIZE, &rxd->myri_scatters[0].len);
486 sbus_writel(index, &rxd->ctx);
487 sbus_writel(1, &rxd->num_sg);
488 sbus_writel(NEXT_RX(sbus_readl(&rq->tail)), &rq->tail);
489
490 /* Trim the original skb for the netif. */
491 DRX(("trim(%d) ", len));
492 skb_trim(skb, len);
493 } else {
494 struct sk_buff *copy_skb = dev_alloc_skb(len);
495
496 DRX(("SMALLBUFF "));
497 if (copy_skb == NULL) {
498 DRX(("dev_alloc_skb(FAILED) "));
499 goto drop_it;
500 }
501 /* DMA sync already done above. */
502 copy_skb->dev = dev;
503 DRX(("resv_and_put "));
504 skb_put(copy_skb, len);
d626f62b 505 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 506
507 /* Reuse original ring buffer. */
508 DRX(("reuse "));
7a715f46 509 sbus_dma_sync_single_for_device(&mp->myri_sdev->ofdev.dev,
1da177e4
LT		 510 sbus_readl(&rxd->myri_scatters[0].addr),
511 RX_ALLOC_SIZE,
512 SBUS_DMA_FROMDEVICE);
513 sbus_writel(RX_ALLOC_SIZE, &rxd->myri_scatters[0].len);
514 sbus_writel(index, &rxd->ctx);
515 sbus_writel(1, &rxd->num_sg);
516 sbus_writel(NEXT_RX(sbus_readl(&rq->tail)), &rq->tail);
517
518 skb = copy_skb;
519 }
520
521 /* Just like the happy meal we get checksums from this card. */
522 skb->csum = csum;
523 skb->ip_summed = CHECKSUM_UNNECESSARY; /* XXX */
524
525 skb->protocol = myri_type_trans(skb, dev);
526 DRX(("prot[%04x] netif_rx ", skb->protocol));
527 netif_rx(skb);
528
529 dev->last_rx = jiffies;
09f75cd7
JG		 530 dev->stats.rx_packets++;
531 dev->stats.rx_bytes += len;
1da177e4
LT		 532 next:
533 DRX(("NEXT\n"));
534 entry = NEXT_RX(entry);
535 }
536}
537
7d12e780 538static irqreturn_t myri_interrupt(int irq, void *dev_id)
1da177e4
LT		 539{
540 struct net_device *dev = (struct net_device *) dev_id;
541 struct myri_eth *mp = (struct myri_eth *) dev->priv;
542 void __iomem *lregs = mp->lregs;
543 struct myri_channel __iomem *chan = &mp->shmem->channel;
544 unsigned long flags;
545 u32 status;
546 int handled = 0;
547
548 spin_lock_irqsave(&mp->irq_lock, flags);
549
550 status = sbus_readl(lregs + LANAI_ISTAT);
551 DIRQ(("myri_interrupt: status[%08x] ", status));
552 if (status & ISTAT_HOST) {
553 u32 softstate;
554
555 handled = 1;
556 DIRQ(("IRQ_DISAB "));
557 myri_disable_irq(lregs, mp->cregs);
558 softstate = sbus_readl(&chan->state);
559 DIRQ(("state[%08x] ", softstate));
560 if (softstate != STATE_READY) {
561 DIRQ(("myri_not_so_happy "));
562 myri_is_not_so_happy(mp);
563 }
564 DIRQ(("\nmyri_rx: "));
565 myri_rx(mp, dev);
566 DIRQ(("\nistat=ISTAT_HOST "));
567 sbus_writel(ISTAT_HOST, lregs + LANAI_ISTAT);
568 DIRQ(("IRQ_ENAB "));
569 myri_enable_irq(lregs, mp->cregs);
570 }
571 DIRQ(("\n"));
572
573 spin_unlock_irqrestore(&mp->irq_lock, flags);
574
575 return IRQ_RETVAL(handled);
576}
577
578static int myri_open(struct net_device *dev)
579{
580 struct myri_eth *mp = (struct myri_eth *) dev->priv;
581
582 return myri_init(mp, in_interrupt());
583}
584
585static int myri_close(struct net_device *dev)
586{
587 struct myri_eth *mp = (struct myri_eth *) dev->priv;
588
589 myri_clean_rings(mp);
590 return 0;
591}
592
593static void myri_tx_timeout(struct net_device *dev)
594{
595 struct myri_eth *mp = (struct myri_eth *) dev->priv;
596
597 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
598
09f75cd7 599 dev->stats.tx_errors++;
1da177e4
LT		 600 myri_init(mp, 0);
601 netif_wake_queue(dev);
602}
603
604static int myri_start_xmit(struct sk_buff *skb, struct net_device *dev)
605{
606 struct myri_eth *mp = (struct myri_eth *) dev->priv;
607 struct sendq __iomem *sq = mp->sq;
608 struct myri_txd __iomem *txd;
609 unsigned long flags;
610 unsigned int head, tail;
611 int len, entry;
612 u32 dma_addr;
613
614 DTX(("myri_start_xmit: "));
615
616 myri_tx(mp, dev);
617
618 netif_stop_queue(dev);
619
620 /* This is just to prevent multiple PIO reads for TX_BUFFS_AVAIL. */
621 head = sbus_readl(&sq->head);
622 tail = sbus_readl(&sq->tail);
623
624 if (!TX_BUFFS_AVAIL(head, tail)) {
625 DTX(("no buffs available, returning 1\n"));
626 return 1;
627 }
628
629 spin_lock_irqsave(&mp->irq_lock, flags);
630
631 DHDR(("xmit[skbdata(%p)]\n", skb->data));
632#ifdef DEBUG_HEADER
633 dump_ehdr_and_myripad(((unsigned char *) skb->data));
634#endif
635
636 /* XXX Maybe this can go as well. */
637 len = skb->len;
638 if (len & 3) {
639 DTX(("len&3 "));
640 len = (len + 4) & (~3);
641 }
642
643 entry = sbus_readl(&sq->tail);
644
645 txd = &sq->myri_txd[entry];
646 mp->tx_skbs[entry] = skb;
647
648 /* Must do this before we sbus map it. */
649 if (skb->data[MYRI_PAD_LEN] & 0x1) {
650 sbus_writew(0xffff, &txd->addr[0]);
651 sbus_writew(0xffff, &txd->addr[1]);
652 sbus_writew(0xffff, &txd->addr[2]);
653 sbus_writew(0xffff, &txd->addr[3]);
654 } else {
655 sbus_writew(0xffff, &txd->addr[0]);
656 sbus_writew((skb->data[0] << 8) | skb->data[1], &txd->addr[1]);
657 sbus_writew((skb->data[2] << 8) | skb->data[3], &txd->addr[2]);
658 sbus_writew((skb->data[4] << 8) | skb->data[5], &txd->addr[3]);
659 }
660
7a715f46
DM		 661 dma_addr = sbus_map_single(&mp->myri_sdev->ofdev.dev, skb->data,
662 len, SBUS_DMA_TODEVICE);
1da177e4
LT		 663 sbus_writel(dma_addr, &txd->myri_gathers[0].addr);
664 sbus_writel(len, &txd->myri_gathers[0].len);
665 sbus_writel(1, &txd->num_sg);
666 sbus_writel(KERNEL_CHANNEL, &txd->chan);
667 sbus_writel(len, &txd->len);
668 sbus_writel((u32)-1, &txd->csum_off);
669 sbus_writel(0, &txd->csum_field);
670
671 sbus_writel(NEXT_TX(entry), &sq->tail);
672 DTX(("BangTheChip "));
673 bang_the_chip(mp);
674
675 DTX(("tbusy=0, returning 0\n"));
676 netif_start_queue(dev);
677 spin_unlock_irqrestore(&mp->irq_lock, flags);
678 return 0;
679}
680
6aa20a22 681/* Create the MyriNet MAC header for an arbitrary protocol layer
1da177e4
LT		 682 *
683 * saddr=NULL means use device source address
684 * daddr=NULL means leave destination address (eg unresolved arp)
685 */
3b04ddde
SH		 686static int myri_header(struct sk_buff *skb, struct net_device *dev,
687 unsigned short type, const void *daddr,
688 const void *saddr, unsigned len)
1da177e4
LT		 689{
690 struct ethhdr *eth = (struct ethhdr *) skb_push(skb, ETH_HLEN);
691 unsigned char *pad = (unsigned char *) skb_push(skb, MYRI_PAD_LEN);
692
693#ifdef DEBUG_HEADER
694 DHDR(("myri_header: pad[%02x,%02x] ", pad[0], pad[1]));
695 dump_ehdr(eth);
696#endif
697
698 /* Set the MyriNET padding identifier. */
699 pad[0] = MYRI_PAD_LEN;
700 pad[1] = 0xab;
701
702 /* Set the protocol type. For a packet of type ETH_P_802_3 we put the length
703 * in here instead. It is up to the 802.2 layer to carry protocol information.
704 */
6aa20a22 705 if (type != ETH_P_802_3)
1da177e4
LT		 706 eth->h_proto = htons(type);
707 else
708 eth->h_proto = htons(len);
709
710 /* Set the source hardware address. */
711 if (saddr)
712 memcpy(eth->h_source, saddr, dev->addr_len);
713 else
714 memcpy(eth->h_source, dev->dev_addr, dev->addr_len);
715
716 /* Anyway, the loopback-device should never use this function... */
717 if (dev->flags & IFF_LOOPBACK) {
718 int i;
719 for (i = 0; i < dev->addr_len; i++)
720 eth->h_dest[i] = 0;
721 return(dev->hard_header_len);
722 }
6aa20a22 723
1da177e4
LT		 724 if (daddr) {
725 memcpy(eth->h_dest, daddr, dev->addr_len);
726 return dev->hard_header_len;
727 }
728 return -dev->hard_header_len;
729}
730
731/* Rebuild the MyriNet MAC header. This is called after an ARP
732 * (or in future other address resolution) has completed on this
733 * sk_buff. We now let ARP fill in the other fields.
734 */
735static int myri_rebuild_header(struct sk_buff *skb)
736{
737 unsigned char *pad = (unsigned char *) skb->data;
738 struct ethhdr *eth = (struct ethhdr *) (pad + MYRI_PAD_LEN);
739 struct net_device *dev = skb->dev;
740
741#ifdef DEBUG_HEADER
742 DHDR(("myri_rebuild_header: pad[%02x,%02x] ", pad[0], pad[1]));
743 dump_ehdr(eth);
744#endif
745
746 /* Refill MyriNet padding identifiers, this is just being anal. */
747 pad[0] = MYRI_PAD_LEN;
748 pad[1] = 0xab;
749
750 switch (eth->h_proto)
751 {
752#ifdef CONFIG_INET
753 case __constant_htons(ETH_P_IP):
754 return arp_find(eth->h_dest, skb);
755#endif
756
757 default:
6aa20a22
JG		 758 printk(KERN_DEBUG
759 "%s: unable to resolve type %X addresses.\n",
1da177e4 760 dev->name, (int)eth->h_proto);
6aa20a22 761
1da177e4
LT		 762 memcpy(eth->h_source, dev->dev_addr, dev->addr_len);
763 return 0;
764 break;
765 }
766
6aa20a22 767 return 0;
1da177e4
LT		 768}
769
3b04ddde 770static int myri_header_cache(const struct neighbour *neigh, struct hh_cache *hh)
1da177e4
LT		 771{
772 unsigned short type = hh->hh_type;
773 unsigned char *pad;
774 struct ethhdr *eth;
3b04ddde 775 const struct net_device *dev = neigh->dev;
1da177e4
LT		 776
777 pad = ((unsigned char *) hh->hh_data) +
778 HH_DATA_OFF(sizeof(*eth) + MYRI_PAD_LEN);
779 eth = (struct ethhdr *) (pad + MYRI_PAD_LEN);
780
3b04ddde 781 if (type == htons(ETH_P_802_3))
1da177e4
LT		 782 return -1;
783
784 /* Refill MyriNet padding identifiers, this is just being anal. */
785 pad[0] = MYRI_PAD_LEN;
786 pad[1] = 0xab;
787
788 eth->h_proto = type;
789 memcpy(eth->h_source, dev->dev_addr, dev->addr_len);
790 memcpy(eth->h_dest, neigh->ha, dev->addr_len);
791 hh->hh_len = 16;
792 return 0;
793}
794
795
796/* Called by Address Resolution module to notify changes in address. */
3b04ddde
SH		 797void myri_header_cache_update(struct hh_cache *hh,
798 const struct net_device *dev,
799 const unsigned char * haddr)
1da177e4
LT		 800{
801 memcpy(((u8*)hh->hh_data) + HH_DATA_OFF(sizeof(struct ethhdr)),
802 haddr, dev->addr_len);
803}
804
805static int myri_change_mtu(struct net_device *dev, int new_mtu)
806{
807 if ((new_mtu < (ETH_HLEN + MYRI_PAD_LEN)) || (new_mtu > MYRINET_MTU))
808 return -EINVAL;
809 dev->mtu = new_mtu;
810 return 0;
811}
812
1da177e4
LT		 813static void myri_set_multicast(struct net_device *dev)
814{
815 /* Do nothing, all MyriCOM nodes transmit multicast frames
816 * as broadcast packets...
817 */
818}
819
820static inline void set_boardid_from_idprom(struct myri_eth *mp, int num)
821{
822 mp->eeprom.id[0] = 0;
823 mp->eeprom.id[1] = idprom->id_machtype;
824 mp->eeprom.id[2] = (idprom->id_sernum >> 16) & 0xff;
825 mp->eeprom.id[3] = (idprom->id_sernum >> 8) & 0xff;
826 mp->eeprom.id[4] = (idprom->id_sernum >> 0) & 0xff;
827 mp->eeprom.id[5] = num;
828}
829
830static inline void determine_reg_space_size(struct myri_eth *mp)
831{
832 switch(mp->eeprom.cpuvers) {
833 case CPUVERS_2_3:
834 case CPUVERS_3_0:
835 case CPUVERS_3_1:
836 case CPUVERS_3_2:
837 mp->reg_size = (3 * 128 * 1024) + 4096;
838 break;
839
840 case CPUVERS_4_0:
841 case CPUVERS_4_1:
842 mp->reg_size = ((4096<<1) + mp->eeprom.ramsz);
843 break;
844
845 case CPUVERS_4_2:
846 case CPUVERS_5_0:
847 default:
848 printk("myricom: AIEEE weird cpu version %04x assuming pre4.0\n",
849 mp->eeprom.cpuvers);
850 mp->reg_size = (3 * 128 * 1024) + 4096;
851 };
852}
853
854#ifdef DEBUG_DETECT
855static void dump_eeprom(struct myri_eth *mp)
856{
857 printk("EEPROM: clockval[%08x] cpuvers[%04x] "
858 "id[%02x,%02x,%02x,%02x,%02x,%02x]\n",
859 mp->eeprom.cval, mp->eeprom.cpuvers,
860 mp->eeprom.id[0], mp->eeprom.id[1], mp->eeprom.id[2],
861 mp->eeprom.id[3], mp->eeprom.id[4], mp->eeprom.id[5]);
862 printk("EEPROM: ramsz[%08x]\n", mp->eeprom.ramsz);
863 printk("EEPROM: fvers[%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n",
864 mp->eeprom.fvers[0], mp->eeprom.fvers[1], mp->eeprom.fvers[2],
865 mp->eeprom.fvers[3], mp->eeprom.fvers[4], mp->eeprom.fvers[5],
866 mp->eeprom.fvers[6], mp->eeprom.fvers[7]);
867 printk("EEPROM: %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n",
868 mp->eeprom.fvers[8], mp->eeprom.fvers[9], mp->eeprom.fvers[10],
869 mp->eeprom.fvers[11], mp->eeprom.fvers[12], mp->eeprom.fvers[13],
870 mp->eeprom.fvers[14], mp->eeprom.fvers[15]);
871 printk("EEPROM: %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n",
872 mp->eeprom.fvers[16], mp->eeprom.fvers[17], mp->eeprom.fvers[18],
873 mp->eeprom.fvers[19], mp->eeprom.fvers[20], mp->eeprom.fvers[21],
874 mp->eeprom.fvers[22], mp->eeprom.fvers[23]);
875 printk("EEPROM: %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x]\n",
876 mp->eeprom.fvers[24], mp->eeprom.fvers[25], mp->eeprom.fvers[26],
877 mp->eeprom.fvers[27], mp->eeprom.fvers[28], mp->eeprom.fvers[29],
878 mp->eeprom.fvers[30], mp->eeprom.fvers[31]);
879 printk("EEPROM: mvers[%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n",
880 mp->eeprom.mvers[0], mp->eeprom.mvers[1], mp->eeprom.mvers[2],
881 mp->eeprom.mvers[3], mp->eeprom.mvers[4], mp->eeprom.mvers[5],
882 mp->eeprom.mvers[6], mp->eeprom.mvers[7]);
883 printk("EEPROM: %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x]\n",
884 mp->eeprom.mvers[8], mp->eeprom.mvers[9], mp->eeprom.mvers[10],
885 mp->eeprom.mvers[11], mp->eeprom.mvers[12], mp->eeprom.mvers[13],
886 mp->eeprom.mvers[14], mp->eeprom.mvers[15]);
887 printk("EEPROM: dlval[%04x] brd_type[%04x] bus_type[%04x] prod_code[%04x]\n",
888 mp->eeprom.dlval, mp->eeprom.brd_type, mp->eeprom.bus_type,
889 mp->eeprom.prod_code);
890 printk("EEPROM: serial_num[%08x]\n", mp->eeprom.serial_num);
891}
892#endif
893
3b04ddde
SH		 894static const struct header_ops myri_header_ops = {
895 .create = myri_header,
896 .rebuild = myri_rebuild_header,
897 .cache = myri_header_cache,
898 .cache_update = myri_header_cache_update,
899};
900
b48194bf 901static int __devinit myri_ether_init(struct sbus_dev *sdev)
1da177e4 902{
a46c30fd 903 static int num;
1da177e4
LT		 904 static unsigned version_printed;
905 struct net_device *dev;
906 struct myri_eth *mp;
907 unsigned char prop_buf[32];
908 int i;
0795af57 909 DECLARE_MAC_BUF(mac);
1da177e4
LT		 910
911 DET(("myri_ether_init(%p,%d):\n", sdev, num));
912 dev = alloc_etherdev(sizeof(struct myri_eth));
913
914 if (!dev)
915 return -ENOMEM;
916
917 if (version_printed++ == 0)
918 printk(version);
919
a46c30fd
DM		 920 SET_NETDEV_DEV(dev, &sdev->ofdev.dev);
921
1da177e4
LT		 922 mp = (struct myri_eth *) dev->priv;
923 spin_lock_init(&mp->irq_lock);
924 mp->myri_sdev = sdev;
925
926 /* Clean out skb arrays. */
927 for (i = 0; i < (RX_RING_SIZE + 1); i++)
928 mp->rx_skbs[i] = NULL;
929
930 for (i = 0; i < TX_RING_SIZE; i++)
931 mp->tx_skbs[i] = NULL;
932
933 /* First check for EEPROM information. */
934 i = prom_getproperty(sdev->prom_node, "myrinet-eeprom-info",
935 (char *)&mp->eeprom, sizeof(struct myri_eeprom));
936 DET(("prom_getprop(myrinet-eeprom-info) returns %d\n", i));
937 if (i == 0 || i == -1) {
938 /* No eeprom property, must cook up the values ourselves. */
939 DET(("No EEPROM: "));
940 mp->eeprom.bus_type = BUS_TYPE_SBUS;
941 mp->eeprom.cpuvers = prom_getintdefault(sdev->prom_node,"cpu_version",0);
942 mp->eeprom.cval = prom_getintdefault(sdev->prom_node,"clock_value",0);
943 mp->eeprom.ramsz = prom_getintdefault(sdev->prom_node,"sram_size",0);
944 DET(("cpuvers[%d] cval[%d] ramsz[%d]\n", mp->eeprom.cpuvers,
945 mp->eeprom.cval, mp->eeprom.ramsz));
946 if (mp->eeprom.cpuvers == 0) {
947 DET(("EEPROM: cpuvers was zero, setting to %04x\n",CPUVERS_2_3));
948 mp->eeprom.cpuvers = CPUVERS_2_3;
949 }
950 if (mp->eeprom.cpuvers < CPUVERS_3_0) {
951 DET(("EEPROM: cpuvers < CPUVERS_3_0, clockval set to zero.\n"));
952 mp->eeprom.cval = 0;
953 }
954 if (mp->eeprom.ramsz == 0) {
955 DET(("EEPROM: ramsz == 0, setting to 128k\n"));
956 mp->eeprom.ramsz = (128 * 1024);
957 }
958 i = prom_getproperty(sdev->prom_node, "myrinet-board-id",
959 &prop_buf[0], 10);
960 DET(("EEPROM: prom_getprop(myrinet-board-id) returns %d\n", i));
961 if ((i != 0) && (i != -1))
962 memcpy(&mp->eeprom.id[0], &prop_buf[0], 6);
963 else
964 set_boardid_from_idprom(mp, num);
965 i = prom_getproperty(sdev->prom_node, "fpga_version",
966 &mp->eeprom.fvers[0], 32);
967 DET(("EEPROM: prom_getprop(fpga_version) returns %d\n", i));
968 if (i == 0 || i == -1)
969 memset(&mp->eeprom.fvers[0], 0, 32);
970
971 if (mp->eeprom.cpuvers == CPUVERS_4_1) {
972 DET(("EEPROM: cpuvers CPUVERS_4_1, "));
973 if (mp->eeprom.ramsz == (128 * 1024)) {
974 DET(("ramsize 128k, setting to 256k, "));
975 mp->eeprom.ramsz = (256 * 1024);
976 }
977 if ((mp->eeprom.cval==0x40414041)||(mp->eeprom.cval==0x90449044)){
978 DET(("changing cval from %08x to %08x ",
979 mp->eeprom.cval, 0x50e450e4));
980 mp->eeprom.cval = 0x50e450e4;
981 }
982 DET(("\n"));
983 }
984 }
985#ifdef DEBUG_DETECT
986 dump_eeprom(mp);
987#endif
988
989 for (i = 0; i < 6; i++)
990 dev->dev_addr[i] = mp->eeprom.id[i];
991
992 determine_reg_space_size(mp);
993
994 /* Map in the MyriCOM register/localram set. */
995 if (mp->eeprom.cpuvers < CPUVERS_4_0) {
996 /* XXX Makes no sense, if control reg is non-existant this
997 * XXX driver cannot function at all... maybe pre-4.0 is
998 * XXX only a valid version for PCI cards? Ask feldy...
999 */
1000 DET(("Mapping regs for cpuvers < CPUVERS_4_0\n"));
1001 mp->regs = sbus_ioremap(&sdev->resource[0], 0,
1002 mp->reg_size, "MyriCOM Regs");
1003 if (!mp->regs) {
1004 printk("MyriCOM: Cannot map MyriCOM registers.\n");
1005 goto err;
1006 }
1007 mp->lanai = mp->regs + (256 * 1024);
1008 mp->lregs = mp->lanai + (0x10000 * 2);
1009 } else {
1010 DET(("Mapping regs for cpuvers >= CPUVERS_4_0\n"));
1011 mp->cregs = sbus_ioremap(&sdev->resource[0], 0,
1012 PAGE_SIZE, "MyriCOM Control Regs");
1013 mp->lregs = sbus_ioremap(&sdev->resource[0], (256 * 1024),
1014 PAGE_SIZE, "MyriCOM LANAI Regs");
1015 mp->lanai =
1016 sbus_ioremap(&sdev->resource[0], (512 * 1024),
1017 mp->eeprom.ramsz, "MyriCOM SRAM");
1018 }
1019 DET(("Registers mapped: cregs[%p] lregs[%p] lanai[%p]\n",
1020 mp->cregs, mp->lregs, mp->lanai));
1021
1022 if (mp->eeprom.cpuvers >= CPUVERS_4_0)
1023 mp->shmem_base = 0xf000;
1024 else
1025 mp->shmem_base = 0x8000;
1026
1027 DET(("Shared memory base is %04x, ", mp->shmem_base));
1028
1029 mp->shmem = (struct myri_shmem __iomem *)
1030 (mp->lanai + (mp->shmem_base * 2));
1031 DET(("shmem mapped at %p\n", mp->shmem));
1032
1033 mp->rqack = &mp->shmem->channel.recvqa;
1034 mp->rq = &mp->shmem->channel.recvq;
1035 mp->sq = &mp->shmem->channel.sendq;
1036
1037 /* Reset the board. */
1038 DET(("Resetting LANAI\n"));
1039 myri_reset_off(mp->lregs, mp->cregs);
1040 myri_reset_on(mp->cregs);
1041
1042 /* Turn IRQ's off. */
1043 myri_disable_irq(mp->lregs, mp->cregs);
1044
1045 /* Reset once more. */
1046 myri_reset_on(mp->cregs);
1047
1048 /* Get the supported DVMA burst sizes from our SBUS. */
1049 mp->myri_bursts = prom_getintdefault(mp->myri_sdev->bus->prom_node,
1050 "burst-sizes", 0x00);
1051
1052 if (!sbus_can_burst64(sdev))
1053 mp->myri_bursts &= ~(DMA_BURST64);
1054
1055 DET(("MYRI bursts %02x\n", mp->myri_bursts));
1056
1057 /* Encode SBUS interrupt level in second control register. */
1058 i = prom_getint(sdev->prom_node, "interrupts");
1059 if (i == 0)
1060 i = 4;
1061 DET(("prom_getint(interrupts)==%d, irqlvl set to %04x\n",
1062 i, (1 << i)));
1063
1064 sbus_writel((1 << i), mp->cregs + MYRICTRL_IRQLVL);
1065
1066 mp->dev = dev;
1067 dev->open = &myri_open;
1068 dev->stop = &myri_close;
1069 dev->hard_start_xmit = &myri_start_xmit;
1070 dev->tx_timeout = &myri_tx_timeout;
1071 dev->watchdog_timeo = 5*HZ;
1da177e4
LT		 1072 dev->set_multicast_list = &myri_set_multicast;
1073 dev->irq = sdev->irqs[0];
1074
1075 /* Register interrupt handler now. */
1076 DET(("Requesting MYRIcom IRQ line.\n"));
1077 if (request_irq(dev->irq, &myri_interrupt,
1fb9df5d 1078 IRQF_SHARED, "MyriCOM Ethernet", (void *) dev)) {
1da177e4
LT		 1079 printk("MyriCOM: Cannot register interrupt handler.\n");
1080 goto err;
1081 }
1082
1083 dev->mtu = MYRINET_MTU;
1084 dev->change_mtu = myri_change_mtu;
3b04ddde
SH		 1085 dev->header_ops = &myri_header_ops;
1086
1da177e4 1087 dev->hard_header_len = (ETH_HLEN + MYRI_PAD_LEN);
1da177e4
LT		 1088
1089 /* Load code onto the LANai. */
1090 DET(("Loading LANAI firmware\n"));
1091 myri_load_lanai(mp);
1092
1093 if (register_netdev(dev)) {
1094 printk("MyriCOM: Cannot register device.\n");
1095 goto err_free_irq;
1096 }
1097
a46c30fd
DM		 1098 dev_set_drvdata(&sdev->ofdev.dev, mp);
1099
1100 num++;
1da177e4 1101
0795af57
JP		 1102 printk("%s: MyriCOM MyriNET Ethernet %s\n",
1103 dev->name, print_mac(mac, dev->dev_addr));
1da177e4
LT		 1104
1105 return 0;
1106
1107err_free_irq:
1108 free_irq(dev->irq, dev);
1109err:
1110 /* This will also free the co-allocated 'dev->priv' */
1111 free_netdev(dev);
1112 return -ENODEV;
1113}
1114
1da177e4 1115
a46c30fd
DM		 1116static int __devinit myri_sbus_probe(struct of_device *dev, const struct of_device_id *match)
1117{
1118 struct sbus_dev *sdev = to_sbus_device(&dev->dev);
1da177e4 1119
a46c30fd 1120 return myri_ether_init(sdev);
1da177e4
LT		 1121}
1122
a46c30fd 1123static int __devexit myri_sbus_remove(struct of_device *dev)
1da177e4 1124{
a46c30fd
DM		 1125 struct myri_eth *mp = dev_get_drvdata(&dev->dev);
1126 struct net_device *net_dev = mp->dev;
1da177e4 1127
a46c30fd 1128 unregister_netdevice(net_dev);
1da177e4 1129
a46c30fd
DM		 1130 free_irq(net_dev->irq, net_dev);
1131
1132 if (mp->eeprom.cpuvers < CPUVERS_4_0) {
1133 sbus_iounmap(mp->regs, mp->reg_size);
1134 } else {
1135 sbus_iounmap(mp->cregs, PAGE_SIZE);
1136 sbus_iounmap(mp->lregs, (256 * 1024));
1137 sbus_iounmap(mp->lanai, (512 * 1024));
1da177e4 1138 }
a46c30fd
DM		 1139
1140 free_netdev(net_dev);
1141
1142 dev_set_drvdata(&dev->dev, NULL);
1143
1da177e4
LT		 1144 return 0;
1145}
1146
a46c30fd
DM		 1147static struct of_device_id myri_sbus_match[] = {
1148 {
1149 .name = "MYRICOM,mlanai",
1150 },
1151 {
1152 .name = "myri",
1153 },
1154 {},
1155};
1156
1157MODULE_DEVICE_TABLE(of, myri_sbus_match);
1158
1159static struct of_platform_driver myri_sbus_driver = {
1160 .name = "myri",
1161 .match_table = myri_sbus_match,
1162 .probe = myri_sbus_probe,
1163 .remove = __devexit_p(myri_sbus_remove),
1164};
1165
1166static int __init myri_sbus_init(void)
1167{
1168 return of_register_driver(&myri_sbus_driver, &sbus_bus_type);
1169}
1170
1171static void __exit myri_sbus_exit(void)
1da177e4 1172{
a46c30fd 1173 of_unregister_driver(&myri_sbus_driver);
1da177e4
LT		 1174}
1175
a46c30fd
DM		 1176module_init(myri_sbus_init);
1177module_exit(myri_sbus_exit);
1178
1da177e4 1179MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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