projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
PHYLIB: Locking fixes for PHY I/O potentially sleeping
[deliverable/linux.git] / drivers / net / natsemi.c
CommitLineData
1da177e4
LT		 1/* natsemi.c: A Linux PCI Ethernet driver for the NatSemi DP8381x series. */
2/*
3 Written/copyright 1999-2001 by Donald Becker.
4 Portions copyright (c) 2001,2002 Sun Microsystems (thockin@sun.com)
5 Portions copyright 2001,2002 Manfred Spraul (manfred@colorfullife.com)
b27a16b7 6 Portions copyright 2004 Harald Welte <laforge@gnumonks.org>
1da177e4
LT		 7
8 This software may be used and distributed according to the terms of
9 the GNU General Public License (GPL), incorporated herein by reference.
10 Drivers based on or derived from this code fall under the GPL and must
11 retain the authorship, copyright and license notice. This file is not
12 a complete program and may only be used when the entire operating
13 system is licensed under the GPL. License for under other terms may be
14 available. Contact the original author for details.
15
16 The original author may be reached as becker@scyld.com, or at
17 Scyld Computing Corporation
18 410 Severn Ave., Suite 210
19 Annapolis MD 21403
20
21 Support information and updates available at
22 http://www.scyld.com/network/netsemi.html
03a8c661 23 [link no longer provides useful info -jgarzik]
1da177e4
LT		 24
25
1da177e4
LT		 26 TODO:
27 * big endian support with CFG:BEM instead of cpu_to_le32
1da177e4
LT		 28*/
29
1da177e4
LT		 30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/string.h>
33#include <linux/timer.h>
34#include <linux/errno.h>
35#include <linux/ioport.h>
36#include <linux/slab.h>
37#include <linux/interrupt.h>
38#include <linux/pci.h>
39#include <linux/netdevice.h>
40#include <linux/etherdevice.h>
41#include <linux/skbuff.h>
42#include <linux/init.h>
43#include <linux/spinlock.h>
44#include <linux/ethtool.h>
45#include <linux/delay.h>
46#include <linux/rtnetlink.h>
47#include <linux/mii.h>
48#include <linux/crc32.h>
49#include <linux/bitops.h>
b27a16b7 50#include <linux/prefetch.h>
1da177e4
LT		 51#include <asm/processor.h> /* Processor type for cache alignment. */
52#include <asm/io.h>
53#include <asm/irq.h>
54#include <asm/uaccess.h>
55
56#define DRV_NAME "natsemi"
d5b20697
AG		 57#define DRV_VERSION "2.1"
58#define DRV_RELDATE "Sept 11, 2006"
1da177e4
LT		 59
60#define RX_OFFSET 2
61
62/* Updated to recommendations in pci-skeleton v2.03. */
63
64/* The user-configurable values.
65 These may be modified when a driver module is loaded.*/
66
67#define NATSEMI_DEF_MSG (NETIF_MSG_DRV | \
68 NETIF_MSG_LINK | \
69 NETIF_MSG_WOL | \
70 NETIF_MSG_RX_ERR | \
71 NETIF_MSG_TX_ERR)
72static int debug = -1;
73
1da177e4
LT		 74static int mtu;
75
76/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
77 This chip uses a 512 element hash table based on the Ethernet CRC. */
f71e1309 78static const int multicast_filter_limit = 100;
1da177e4
LT		 79
80/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
81 Setting to > 1518 effectively disables this feature. */
82static int rx_copybreak;
83
1a147809
MB		 84static int dspcfg_workaround = 1;
85
1da177e4
LT		 86/* Used to pass the media type, etc.
87 Both 'options[]' and 'full_duplex[]' should exist for driver
88 interoperability.
89 The media type is usually passed in 'options[]'.
90*/
91#define MAX_UNITS 8 /* More are supported, limit only on options */
92static int options[MAX_UNITS];
93static int full_duplex[MAX_UNITS];
94
95/* Operational parameters that are set at compile time. */
96
97/* Keep the ring sizes a power of two for compile efficiency.
98 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
99 Making the Tx ring too large decreases the effectiveness of channel
100 bonding and packet priority.
101 There are no ill effects from too-large receive rings. */
102#define TX_RING_SIZE 16
103#define TX_QUEUE_LEN 10 /* Limit ring entries actually used, min 4. */
104#define RX_RING_SIZE 32
105
106/* Operational parameters that usually are not changed. */
107/* Time in jiffies before concluding the transmitter is hung. */
108#define TX_TIMEOUT (2*HZ)
109
110#define NATSEMI_HW_TIMEOUT 400
f2cade13 111#define NATSEMI_TIMER_FREQ 5*HZ
1da177e4
LT		 112#define NATSEMI_PG0_NREGS 64
113#define NATSEMI_RFDR_NREGS 8
114#define NATSEMI_PG1_NREGS 4
115#define NATSEMI_NREGS (NATSEMI_PG0_NREGS + NATSEMI_RFDR_NREGS + \
116 NATSEMI_PG1_NREGS)
117#define NATSEMI_REGS_VER 1 /* v1 added RFDR registers */
118#define NATSEMI_REGS_SIZE (NATSEMI_NREGS * sizeof(u32))
1da177e4
LT		 119
120/* Buffer sizes:
121 * The nic writes 32-bit values, even if the upper bytes of
122 * a 32-bit value are beyond the end of the buffer.
123 */
124#define NATSEMI_HEADERS 22 /* 2*mac,type,vlan,crc */
125#define NATSEMI_PADDING 16 /* 2 bytes should be sufficient */
126#define NATSEMI_LONGPKT 1518 /* limit for normal packets */
127#define NATSEMI_RX_LIMIT 2046 /* maximum supported by hardware */
128
129/* These identify the driver base version and may not be removed. */
e19360f2 130static const char version[] __devinitdata =
1da177e4
LT		 131 KERN_INFO DRV_NAME " dp8381x driver, version "
132 DRV_VERSION ", " DRV_RELDATE "\n"
133 KERN_INFO " originally by Donald Becker <becker@scyld.com>\n"
1da177e4
LT		 134 KERN_INFO " 2.4.x kernel port by Jeff Garzik, Tjeerd Mulder\n";
135
136MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
137MODULE_DESCRIPTION("National Semiconductor DP8381x series PCI Ethernet driver");
138MODULE_LICENSE("GPL");
139
1da177e4
LT		 140module_param(mtu, int, 0);
141module_param(debug, int, 0);
142module_param(rx_copybreak, int, 0);
1a147809 143module_param(dspcfg_workaround, int, 1);
1da177e4
LT		 144module_param_array(options, int, NULL, 0);
145module_param_array(full_duplex, int, NULL, 0);
1da177e4
LT		 146MODULE_PARM_DESC(mtu, "DP8381x MTU (all boards)");
147MODULE_PARM_DESC(debug, "DP8381x default debug level");
6aa20a22 148MODULE_PARM_DESC(rx_copybreak,
1da177e4 149 "DP8381x copy breakpoint for copy-only-tiny-frames");
1a147809 150MODULE_PARM_DESC(dspcfg_workaround, "DP8381x: control DspCfg workaround");
6aa20a22 151MODULE_PARM_DESC(options,
1da177e4
LT		 152 "DP8381x: Bits 0-3: media type, bit 17: full duplex");
153MODULE_PARM_DESC(full_duplex, "DP8381x full duplex setting(s) (1)");
154
155/*
156 Theory of Operation
157
158I. Board Compatibility
159
160This driver is designed for National Semiconductor DP83815 PCI Ethernet NIC.
161It also works with other chips in in the DP83810 series.
162
163II. Board-specific settings
164
165This driver requires the PCI interrupt line to be valid.
166It honors the EEPROM-set values.
167
168III. Driver operation
169
170IIIa. Ring buffers
171
172This driver uses two statically allocated fixed-size descriptor lists
173formed into rings by a branch from the final descriptor to the beginning of
174the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
175The NatSemi design uses a 'next descriptor' pointer that the driver forms
176into a list.
177
178IIIb/c. Transmit/Receive Structure
179
180This driver uses a zero-copy receive and transmit scheme.
181The driver allocates full frame size skbuffs for the Rx ring buffers at
182open() time and passes the skb->data field to the chip as receive data
183buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
184a fresh skbuff is allocated and the frame is copied to the new skbuff.
185When the incoming frame is larger, the skbuff is passed directly up the
186protocol stack. Buffers consumed this way are replaced by newly allocated
187skbuffs in a later phase of receives.
188
189The RX_COPYBREAK value is chosen to trade-off the memory wasted by
190using a full-sized skbuff for small frames vs. the copying costs of larger
191frames. New boards are typically used in generously configured machines
192and the underfilled buffers have negligible impact compared to the benefit of
193a single allocation size, so the default value of zero results in never
194copying packets. When copying is done, the cost is usually mitigated by using
195a combined copy/checksum routine. Copying also preloads the cache, which is
196most useful with small frames.
197
198A subtle aspect of the operation is that unaligned buffers are not permitted
199by the hardware. Thus the IP header at offset 14 in an ethernet frame isn't
200longword aligned for further processing. On copies frames are put into the
201skbuff at an offset of "+2", 16-byte aligning the IP header.
202
203IIId. Synchronization
204
205Most operations are synchronized on the np->lock irq spinlock, except the
206performance critical codepaths:
207
208The rx process only runs in the interrupt handler. Access from outside
209the interrupt handler is only permitted after disable_irq().
210
932ff279 211The rx process usually runs under the netif_tx_lock. If np->intr_tx_reap
1da177e4
LT		 212is set, then access is permitted under spin_lock_irq(&np->lock).
213
214Thus configuration functions that want to access everything must call
215 disable_irq(dev->irq);
932ff279 216 netif_tx_lock_bh(dev);
1da177e4
LT		 217 spin_lock_irq(&np->lock);
218
219IV. Notes
220
221NatSemi PCI network controllers are very uncommon.
222
223IVb. References
224
225http://www.scyld.com/expert/100mbps.html
226http://www.scyld.com/expert/NWay.html
227Datasheet is available from:
228http://www.national.com/pf/DP/DP83815.html
229
230IVc. Errata
231
232None characterised.
233*/
234
235
236
1da177e4
LT		 237/*
238 * Support for fibre connections on Am79C874:
239 * This phy needs a special setup when connected to a fibre cable.
240 * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/22235.pdf
241 */
242#define PHYID_AM79C874 0x0022561b
243
a2b524b2
JG		 244enum {
245 MII_MCTRL = 0x15, /* mode control register */
246 MII_FX_SEL = 0x0001, /* 100BASE-FX (fiber) */
247 MII_EN_SCRM = 0x0004, /* enable scrambler (tp) */
248};
1da177e4 249
6aab4447
MB		 250enum {
251 NATSEMI_FLAG_IGNORE_PHY = 0x1,
252};
6aa20a22 253
1da177e4 254/* array of board data directly indexed by pci_tbl[x].driver_data */
f71e1309 255static const struct {
1da177e4
LT		 256 const char *name;
257 unsigned long flags;
a2b524b2 258 unsigned int eeprom_size;
1da177e4 259} natsemi_pci_info[] __devinitdata = {
6aab4447 260 { "Aculab E1/T1 PMXc cPCI carrier card", NATSEMI_FLAG_IGNORE_PHY, 128 },
a2b524b2 261 { "NatSemi DP8381[56]", 0, 24 },
1da177e4
LT		 262};
263
a2b524b2 264static const struct pci_device_id natsemi_pci_tbl[] __devinitdata = {
6aab4447 265 { PCI_VENDOR_ID_NS, 0x0020, 0x12d9, 0x000c, 0, 0, 0 },
36c843d5 266 { PCI_VENDOR_ID_NS, 0x0020, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
a2b524b2 267 { } /* terminate list */
1da177e4
LT		 268};
269MODULE_DEVICE_TABLE(pci, natsemi_pci_tbl);
270
271/* Offsets to the device registers.
272 Unlike software-only systems, device drivers interact with complex hardware.
273 It's not useful to define symbolic names for every register bit in the
274 device.
275*/
276enum register_offsets {
277 ChipCmd = 0x00,
278 ChipConfig = 0x04,
279 EECtrl = 0x08,
280 PCIBusCfg = 0x0C,
281 IntrStatus = 0x10,
282 IntrMask = 0x14,
283 IntrEnable = 0x18,
284 IntrHoldoff = 0x1C, /* DP83816 only */
285 TxRingPtr = 0x20,
286 TxConfig = 0x24,
287 RxRingPtr = 0x30,
288 RxConfig = 0x34,
289 ClkRun = 0x3C,
290 WOLCmd = 0x40,
291 PauseCmd = 0x44,
292 RxFilterAddr = 0x48,
293 RxFilterData = 0x4C,
294 BootRomAddr = 0x50,
295 BootRomData = 0x54,
296 SiliconRev = 0x58,
297 StatsCtrl = 0x5C,
298 StatsData = 0x60,
299 RxPktErrs = 0x60,
300 RxMissed = 0x68,
301 RxCRCErrs = 0x64,
302 BasicControl = 0x80,
303 BasicStatus = 0x84,
304 AnegAdv = 0x90,
305 AnegPeer = 0x94,
306 PhyStatus = 0xC0,
307 MIntrCtrl = 0xC4,
308 MIntrStatus = 0xC8,
309 PhyCtrl = 0xE4,
310
311 /* These are from the spec, around page 78... on a separate table.
312 * The meaning of these registers depend on the value of PGSEL. */
313 PGSEL = 0xCC,
314 PMDCSR = 0xE4,
315 TSTDAT = 0xFC,
316 DSPCFG = 0xF4,
317 SDCFG = 0xF8
318};
319/* the values for the 'magic' registers above (PGSEL=1) */
320#define PMDCSR_VAL 0x189c /* enable preferred adaptation circuitry */
321#define TSTDAT_VAL 0x0
322#define DSPCFG_VAL 0x5040
323#define SDCFG_VAL 0x008c /* set voltage thresholds for Signal Detect */
324#define DSPCFG_LOCK 0x20 /* coefficient lock bit in DSPCFG */
325#define DSPCFG_COEF 0x1000 /* see coefficient (in TSTDAT) bit in DSPCFG */
326#define TSTDAT_FIXED 0xe8 /* magic number for bad coefficients */
327
328/* misc PCI space registers */
329enum pci_register_offsets {
330 PCIPM = 0x44,
331};
332
333enum ChipCmd_bits {
334 ChipReset = 0x100,
335 RxReset = 0x20,
336 TxReset = 0x10,
337 RxOff = 0x08,
338 RxOn = 0x04,
339 TxOff = 0x02,
340 TxOn = 0x01,
341};
342
343enum ChipConfig_bits {
344 CfgPhyDis = 0x200,
345 CfgPhyRst = 0x400,
346 CfgExtPhy = 0x1000,
347 CfgAnegEnable = 0x2000,
348 CfgAneg100 = 0x4000,
349 CfgAnegFull = 0x8000,
350 CfgAnegDone = 0x8000000,
351 CfgFullDuplex = 0x20000000,
352 CfgSpeed100 = 0x40000000,
353 CfgLink = 0x80000000,
354};
355
356enum EECtrl_bits {
357 EE_ShiftClk = 0x04,
358 EE_DataIn = 0x01,
359 EE_ChipSelect = 0x08,
360 EE_DataOut = 0x02,
361 MII_Data = 0x10,
362 MII_Write = 0x20,
363 MII_ShiftClk = 0x40,
364};
365
366enum PCIBusCfg_bits {
367 EepromReload = 0x4,
368};
369
370/* Bits in the interrupt status/mask registers. */
371enum IntrStatus_bits {
372 IntrRxDone = 0x0001,
373 IntrRxIntr = 0x0002,
374 IntrRxErr = 0x0004,
375 IntrRxEarly = 0x0008,
376 IntrRxIdle = 0x0010,
377 IntrRxOverrun = 0x0020,
378 IntrTxDone = 0x0040,
379 IntrTxIntr = 0x0080,
380 IntrTxErr = 0x0100,
381 IntrTxIdle = 0x0200,
382 IntrTxUnderrun = 0x0400,
383 StatsMax = 0x0800,
384 SWInt = 0x1000,
385 WOLPkt = 0x2000,
386 LinkChange = 0x4000,
387 IntrHighBits = 0x8000,
388 RxStatusFIFOOver = 0x10000,
389 IntrPCIErr = 0xf00000,
390 RxResetDone = 0x1000000,
391 TxResetDone = 0x2000000,
392 IntrAbnormalSummary = 0xCD20,
393};
394
395/*
396 * Default Interrupts:
397 * Rx OK, Rx Packet Error, Rx Overrun,
398 * Tx OK, Tx Packet Error, Tx Underrun,
399 * MIB Service, Phy Interrupt, High Bits,
400 * Rx Status FIFO overrun,
401 * Received Target Abort, Received Master Abort,
402 * Signalled System Error, Received Parity Error
403 */
404#define DEFAULT_INTR 0x00f1cd65
405
406enum TxConfig_bits {
407 TxDrthMask = 0x3f,
408 TxFlthMask = 0x3f00,
409 TxMxdmaMask = 0x700000,
410 TxMxdma_512 = 0x0,
411 TxMxdma_4 = 0x100000,
412 TxMxdma_8 = 0x200000,
413 TxMxdma_16 = 0x300000,
414 TxMxdma_32 = 0x400000,
415 TxMxdma_64 = 0x500000,
416 TxMxdma_128 = 0x600000,
417 TxMxdma_256 = 0x700000,
418 TxCollRetry = 0x800000,
419 TxAutoPad = 0x10000000,
420 TxMacLoop = 0x20000000,
421 TxHeartIgn = 0x40000000,
422 TxCarrierIgn = 0x80000000
423};
424
6aa20a22 425/*
1da177e4
LT		 426 * Tx Configuration:
427 * - 256 byte DMA burst length
428 * - fill threshold 512 bytes (i.e. restart DMA when 512 bytes are free)
429 * - 64 bytes initial drain threshold (i.e. begin actual transmission
430 * when 64 byte are in the fifo)
431 * - on tx underruns, increase drain threshold by 64.
432 * - at most use a drain threshold of 1472 bytes: The sum of the fill
433 * threshold and the drain threshold must be less than 2016 bytes.
434 *
435 */
436#define TX_FLTH_VAL ((512/32) << 8)
437#define TX_DRTH_VAL_START (64/32)
438#define TX_DRTH_VAL_INC 2
439#define TX_DRTH_VAL_LIMIT (1472/32)
440
441enum RxConfig_bits {
442 RxDrthMask = 0x3e,
443 RxMxdmaMask = 0x700000,
444 RxMxdma_512 = 0x0,
445 RxMxdma_4 = 0x100000,
446 RxMxdma_8 = 0x200000,
447 RxMxdma_16 = 0x300000,
448 RxMxdma_32 = 0x400000,
449 RxMxdma_64 = 0x500000,
450 RxMxdma_128 = 0x600000,
451 RxMxdma_256 = 0x700000,
452 RxAcceptLong = 0x8000000,
453 RxAcceptTx = 0x10000000,
454 RxAcceptRunt = 0x40000000,
455 RxAcceptErr = 0x80000000
456};
457#define RX_DRTH_VAL (128/8)
458
459enum ClkRun_bits {
460 PMEEnable = 0x100,
461 PMEStatus = 0x8000,
462};
463
464enum WolCmd_bits {
465 WakePhy = 0x1,
466 WakeUnicast = 0x2,
467 WakeMulticast = 0x4,
468 WakeBroadcast = 0x8,
469 WakeArp = 0x10,
470 WakePMatch0 = 0x20,
471 WakePMatch1 = 0x40,
472 WakePMatch2 = 0x80,
473 WakePMatch3 = 0x100,
474 WakeMagic = 0x200,
475 WakeMagicSecure = 0x400,
476 SecureHack = 0x100000,
477 WokePhy = 0x400000,
478 WokeUnicast = 0x800000,
479 WokeMulticast = 0x1000000,
480 WokeBroadcast = 0x2000000,
481 WokeArp = 0x4000000,
482 WokePMatch0 = 0x8000000,
483 WokePMatch1 = 0x10000000,
484 WokePMatch2 = 0x20000000,
485 WokePMatch3 = 0x40000000,
486 WokeMagic = 0x80000000,
487 WakeOptsSummary = 0x7ff
488};
489
490enum RxFilterAddr_bits {
491 RFCRAddressMask = 0x3ff,
492 AcceptMulticast = 0x00200000,
493 AcceptMyPhys = 0x08000000,
494 AcceptAllPhys = 0x10000000,
495 AcceptAllMulticast = 0x20000000,
496 AcceptBroadcast = 0x40000000,
497 RxFilterEnable = 0x80000000
498};
499
500enum StatsCtrl_bits {
501 StatsWarn = 0x1,
502 StatsFreeze = 0x2,
503 StatsClear = 0x4,
504 StatsStrobe = 0x8,
505};
506
507enum MIntrCtrl_bits {
508 MICRIntEn = 0x2,
509};
510
511enum PhyCtrl_bits {
512 PhyAddrMask = 0x1f,
513};
514
515#define PHY_ADDR_NONE 32
516#define PHY_ADDR_INTERNAL 1
517
518/* values we might find in the silicon revision register */
519#define SRR_DP83815_C 0x0302
520#define SRR_DP83815_D 0x0403
521#define SRR_DP83816_A4 0x0504
522#define SRR_DP83816_A5 0x0505
523
524/* The Rx and Tx buffer descriptors. */
525/* Note that using only 32 bit fields simplifies conversion to big-endian
526 architectures. */
527struct netdev_desc {
528 u32 next_desc;
529 s32 cmd_status;
530 u32 addr;
531 u32 software_use;
532};
533
534/* Bits in network_desc.status */
535enum desc_status_bits {
536 DescOwn=0x80000000, DescMore=0x40000000, DescIntr=0x20000000,
537 DescNoCRC=0x10000000, DescPktOK=0x08000000,
538 DescSizeMask=0xfff,
539
540 DescTxAbort=0x04000000, DescTxFIFO=0x02000000,
541 DescTxCarrier=0x01000000, DescTxDefer=0x00800000,
542 DescTxExcDefer=0x00400000, DescTxOOWCol=0x00200000,
543 DescTxExcColl=0x00100000, DescTxCollCount=0x000f0000,
544
545 DescRxAbort=0x04000000, DescRxOver=0x02000000,
546 DescRxDest=0x01800000, DescRxLong=0x00400000,
547 DescRxRunt=0x00200000, DescRxInvalid=0x00100000,
548 DescRxCRC=0x00080000, DescRxAlign=0x00040000,
549 DescRxLoop=0x00020000, DesRxColl=0x00010000,
550};
551
552struct netdev_private {
553 /* Descriptor rings first for alignment */
554 dma_addr_t ring_dma;
555 struct netdev_desc *rx_ring;
556 struct netdev_desc *tx_ring;
557 /* The addresses of receive-in-place skbuffs */
558 struct sk_buff *rx_skbuff[RX_RING_SIZE];
559 dma_addr_t rx_dma[RX_RING_SIZE];
560 /* address of a sent-in-place packet/buffer, for later free() */
561 struct sk_buff *tx_skbuff[TX_RING_SIZE];
562 dma_addr_t tx_dma[TX_RING_SIZE];
bea3348e
SH		 563 struct net_device *dev;
564 struct napi_struct napi;
1da177e4
LT		 565 struct net_device_stats stats;
566 /* Media monitoring timer */
567 struct timer_list timer;
568 /* Frequently used values: keep some adjacent for cache effect */
569 struct pci_dev *pci_dev;
570 struct netdev_desc *rx_head_desc;
571 /* Producer/consumer ring indices */
572 unsigned int cur_rx, dirty_rx;
573 unsigned int cur_tx, dirty_tx;
574 /* Based on MTU+slack. */
575 unsigned int rx_buf_sz;
576 int oom;
b27a16b7
MB		 577 /* Interrupt status */
578 u32 intr_status;
1da177e4
LT		 579 /* Do not touch the nic registers */
580 int hands_off;
68c90166
MB		 581 /* Don't pay attention to the reported link state. */
582 int ignore_phy;
1da177e4
LT		 583 /* external phy that is used: only valid if dev->if_port != PORT_TP */
584 int mii;
585 int phy_addr_external;
586 unsigned int full_duplex;
587 /* Rx filter */
588 u32 cur_rx_mode;
589 u32 rx_filter[16];
590 /* FIFO and PCI burst thresholds */
591 u32 tx_config, rx_config;
592 /* original contents of ClkRun register */
593 u32 SavedClkRun;
594 /* silicon revision */
595 u32 srr;
596 /* expected DSPCFG value */
597 u16 dspcfg;
1a147809 598 int dspcfg_workaround;
1da177e4
LT		 599 /* parms saved in ethtool format */
600 u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */
601 u8 duplex; /* Duplex, half or full */
602 u8 autoneg; /* Autonegotiation enabled */
603 /* MII transceiver section */
604 u16 advertising;
605 unsigned int iosize;
606 spinlock_t lock;
607 u32 msg_enable;
a8b4cf42
MB		 608 /* EEPROM data */
609 int eeprom_size;
1da177e4
LT		 610};
611
612static void move_int_phy(struct net_device *dev, int addr);
613static int eeprom_read(void __iomem *ioaddr, int location);
614static int mdio_read(struct net_device *dev, int reg);
615static void mdio_write(struct net_device *dev, int reg, u16 data);
616static void init_phy_fixup(struct net_device *dev);
617static int miiport_read(struct net_device *dev, int phy_id, int reg);
618static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data);
619static int find_mii(struct net_device *dev);
620static void natsemi_reset(struct net_device *dev);
621static void natsemi_reload_eeprom(struct net_device *dev);
622static void natsemi_stop_rxtx(struct net_device *dev);
623static int netdev_open(struct net_device *dev);
624static void do_cable_magic(struct net_device *dev);
625static void undo_cable_magic(struct net_device *dev);
626static void check_link(struct net_device *dev);
627static void netdev_timer(unsigned long data);
628static void dump_ring(struct net_device *dev);
629static void tx_timeout(struct net_device *dev);
630static int alloc_ring(struct net_device *dev);
631static void refill_rx(struct net_device *dev);
632static void init_ring(struct net_device *dev);
633static void drain_tx(struct net_device *dev);
634static void drain_ring(struct net_device *dev);
635static void free_ring(struct net_device *dev);
636static void reinit_ring(struct net_device *dev);
637static void init_registers(struct net_device *dev);
638static int start_tx(struct sk_buff *skb, struct net_device *dev);
7d12e780 639static irqreturn_t intr_handler(int irq, void *dev_instance);
1da177e4 640static void netdev_error(struct net_device *dev, int intr_status);
bea3348e 641static int natsemi_poll(struct napi_struct *napi, int budget);
b27a16b7 642static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do);
1da177e4
LT		 643static void netdev_tx_done(struct net_device *dev);
644static int natsemi_change_mtu(struct net_device *dev, int new_mtu);
645#ifdef CONFIG_NET_POLL_CONTROLLER
646static void natsemi_poll_controller(struct net_device *dev);
647#endif
648static void __set_rx_mode(struct net_device *dev);
649static void set_rx_mode(struct net_device *dev);
650static void __get_stats(struct net_device *dev);
651static struct net_device_stats *get_stats(struct net_device *dev);
652static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
653static int netdev_set_wol(struct net_device *dev, u32 newval);
654static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur);
655static int netdev_set_sopass(struct net_device *dev, u8 *newval);
656static int netdev_get_sopass(struct net_device *dev, u8 *data);
657static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
658static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
659static void enable_wol_mode(struct net_device *dev, int enable_intr);
660static int netdev_close(struct net_device *dev);
661static int netdev_get_regs(struct net_device *dev, u8 *buf);
662static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
7282d491 663static const struct ethtool_ops ethtool_ops;
1da177e4 664
1a147809
MB		 665#define NATSEMI_ATTR(_name) \
666static ssize_t natsemi_show_##_name(struct device *dev, \
667 struct device_attribute *attr, char *buf); \
668 static ssize_t natsemi_set_##_name(struct device *dev, \
669 struct device_attribute *attr, \
670 const char *buf, size_t count); \
671 static DEVICE_ATTR(_name, 0644, natsemi_show_##_name, natsemi_set_##_name)
672
673#define NATSEMI_CREATE_FILE(_dev, _name) \
674 device_create_file(&_dev->dev, &dev_attr_##_name)
675#define NATSEMI_REMOVE_FILE(_dev, _name) \
f6c42865 676 device_remove_file(&_dev->dev, &dev_attr_##_name)
1a147809
MB		 677
678NATSEMI_ATTR(dspcfg_workaround);
679
680static ssize_t natsemi_show_dspcfg_workaround(struct device *dev,
681 struct device_attribute *attr,
682 char *buf)
683{
684 struct netdev_private *np = netdev_priv(to_net_dev(dev));
685
686 return sprintf(buf, "%s\n", np->dspcfg_workaround ? "on" : "off");
687}
688
689static ssize_t natsemi_set_dspcfg_workaround(struct device *dev,
690 struct device_attribute *attr,
691 const char *buf, size_t count)
692{
693 struct netdev_private *np = netdev_priv(to_net_dev(dev));
694 int new_setting;
d41f2d17 695 unsigned long flags;
1a147809
MB		 696
697 /* Find out the new setting */
698 if (!strncmp("on", buf, count - 1) || !strncmp("1", buf, count - 1))
699 new_setting = 1;
700 else if (!strncmp("off", buf, count - 1)
701 || !strncmp("0", buf, count - 1))
702 new_setting = 0;
703 else
704 return count;
705
706 spin_lock_irqsave(&np->lock, flags);
707
708 np->dspcfg_workaround = new_setting;
709
710 spin_unlock_irqrestore(&np->lock, flags);
711
712 return count;
713}
714
1da177e4
LT		 715static inline void __iomem *ns_ioaddr(struct net_device *dev)
716{
717 return (void __iomem *) dev->base_addr;
718}
719
b27a16b7
MB		 720static inline void natsemi_irq_enable(struct net_device *dev)
721{
722 writel(1, ns_ioaddr(dev) + IntrEnable);
723 readl(ns_ioaddr(dev) + IntrEnable);
724}
725
726static inline void natsemi_irq_disable(struct net_device *dev)
727{
728 writel(0, ns_ioaddr(dev) + IntrEnable);
729 readl(ns_ioaddr(dev) + IntrEnable);
730}
731
1da177e4
LT		 732static void move_int_phy(struct net_device *dev, int addr)
733{
734 struct netdev_private *np = netdev_priv(dev);
735 void __iomem *ioaddr = ns_ioaddr(dev);
736 int target = 31;
737
6aa20a22 738 /*
1da177e4
LT		 739 * The internal phy is visible on the external mii bus. Therefore we must
740 * move it away before we can send commands to an external phy.
741 * There are two addresses we must avoid:
742 * - the address on the external phy that is used for transmission.
743 * - the address that we want to access. User space can access phys
744 * on the mii bus with SIOCGMIIREG/SIOCSMIIREG, independant from the
745 * phy that is used for transmission.
746 */
747
748 if (target == addr)
749 target--;
750 if (target == np->phy_addr_external)
751 target--;
752 writew(target, ioaddr + PhyCtrl);
753 readw(ioaddr + PhyCtrl);
754 udelay(1);
755}
756
5a40f09b
JG		 757static void __devinit natsemi_init_media (struct net_device *dev)
758{
759 struct netdev_private *np = netdev_priv(dev);
760 u32 tmp;
761
68c90166
MB		 762 if (np->ignore_phy)
763 netif_carrier_on(dev);
764 else
765 netif_carrier_off(dev);
5a40f09b
JG		 766
767 /* get the initial settings from hardware */
768 tmp = mdio_read(dev, MII_BMCR);
769 np->speed = (tmp & BMCR_SPEED100)? SPEED_100 : SPEED_10;
770 np->duplex = (tmp & BMCR_FULLDPLX)? DUPLEX_FULL : DUPLEX_HALF;
771 np->autoneg = (tmp & BMCR_ANENABLE)? AUTONEG_ENABLE: AUTONEG_DISABLE;
772 np->advertising= mdio_read(dev, MII_ADVERTISE);
773
774 if ((np->advertising & ADVERTISE_ALL) != ADVERTISE_ALL
775 && netif_msg_probe(np)) {
776 printk(KERN_INFO "natsemi %s: Transceiver default autonegotiation %s "
777 "10%s %s duplex.\n",
778 pci_name(np->pci_dev),
779 (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE)?
780 "enabled, advertise" : "disabled, force",
781 (np->advertising &
782 (ADVERTISE_100FULL|ADVERTISE_100HALF))?
783 "0" : "",
784 (np->advertising &
785 (ADVERTISE_100FULL|ADVERTISE_10FULL))?
786 "full" : "half");
787 }
788 if (netif_msg_probe(np))
789 printk(KERN_INFO
790 "natsemi %s: Transceiver status %#04x advertising %#04x.\n",
791 pci_name(np->pci_dev), mdio_read(dev, MII_BMSR),
792 np->advertising);
793
794}
795
1da177e4
LT		 796static int __devinit natsemi_probe1 (struct pci_dev *pdev,
797 const struct pci_device_id *ent)
798{
799 struct net_device *dev;
800 struct netdev_private *np;
801 int i, option, irq, chip_idx = ent->driver_data;
802 static int find_cnt = -1;
803 unsigned long iostart, iosize;
804 void __iomem *ioaddr;
805 const int pcibar = 1; /* PCI base address register */
806 int prev_eedata;
807 u32 tmp;
0795af57 808 DECLARE_MAC_BUF(mac);
1da177e4
LT		 809
810/* when built into the kernel, we only print version if device is found */
811#ifndef MODULE
812 static int printed_version;
813 if (!printed_version++)
814 printk(version);
815#endif
816
817 i = pci_enable_device(pdev);
818 if (i) return i;
819
820 /* natsemi has a non-standard PM control register
821 * in PCI config space. Some boards apparently need
822 * to be brought to D0 in this manner.
823 */
824 pci_read_config_dword(pdev, PCIPM, &tmp);
825 if (tmp & PCI_PM_CTRL_STATE_MASK) {
826 /* D0 state, disable PME assertion */
827 u32 newtmp = tmp & ~PCI_PM_CTRL_STATE_MASK;
828 pci_write_config_dword(pdev, PCIPM, newtmp);
829 }
830
831 find_cnt++;
832 iostart = pci_resource_start(pdev, pcibar);
833 iosize = pci_resource_len(pdev, pcibar);
834 irq = pdev->irq;
835
a2b524b2 836 pci_set_master(pdev);
1da177e4
LT		 837
838 dev = alloc_etherdev(sizeof (struct netdev_private));
839 if (!dev)
840 return -ENOMEM;
1da177e4
LT		 841 SET_NETDEV_DEV(dev, &pdev->dev);
842
843 i = pci_request_regions(pdev, DRV_NAME);
844 if (i)
845 goto err_pci_request_regions;
846
847 ioaddr = ioremap(iostart, iosize);
848 if (!ioaddr) {
849 i = -ENOMEM;
850 goto err_ioremap;
851 }
852
853 /* Work around the dropped serial bit. */
854 prev_eedata = eeprom_read(ioaddr, 6);
855 for (i = 0; i < 3; i++) {
856 int eedata = eeprom_read(ioaddr, i + 7);
857 dev->dev_addr[i*2] = (eedata << 1) + (prev_eedata >> 15);
858 dev->dev_addr[i*2+1] = eedata >> 7;
859 prev_eedata = eedata;
860 }
861
862 dev->base_addr = (unsigned long __force) ioaddr;
863 dev->irq = irq;
864
865 np = netdev_priv(dev);
bea3348e 866 netif_napi_add(dev, &np->napi, natsemi_poll, 64);
bbbab5ca 867 np->dev = dev;
1da177e4
LT		 868
869 np->pci_dev = pdev;
870 pci_set_drvdata(pdev, dev);
871 np->iosize = iosize;
872 spin_lock_init(&np->lock);
873 np->msg_enable = (debug >= 0) ? (1<<debug)-1 : NATSEMI_DEF_MSG;
874 np->hands_off = 0;
b27a16b7 875 np->intr_status = 0;
a2b524b2 876 np->eeprom_size = natsemi_pci_info[chip_idx].eeprom_size;
6aab4447
MB		 877 if (natsemi_pci_info[chip_idx].flags & NATSEMI_FLAG_IGNORE_PHY)
878 np->ignore_phy = 1;
879 else
880 np->ignore_phy = 0;
1a147809 881 np->dspcfg_workaround = dspcfg_workaround;
1da177e4
LT		 882
883 /* Initial port:
68c90166 884 * - If configured to ignore the PHY set up for external.
1da177e4
LT		 885 * - If the nic was configured to use an external phy and if find_mii
886 * finds a phy: use external port, first phy that replies.
887 * - Otherwise: internal port.
888 * Note that the phy address for the internal phy doesn't matter:
889 * The address would be used to access a phy over the mii bus, but
890 * the internal phy is accessed through mapped registers.
891 */
68c90166 892 if (np->ignore_phy || readl(ioaddr + ChipConfig) & CfgExtPhy)
1da177e4
LT		 893 dev->if_port = PORT_MII;
894 else
895 dev->if_port = PORT_TP;
896 /* Reset the chip to erase previous misconfiguration. */
897 natsemi_reload_eeprom(dev);
898 natsemi_reset(dev);
899
900 if (dev->if_port != PORT_TP) {
901 np->phy_addr_external = find_mii(dev);
68c90166
MB		 902 /* If we're ignoring the PHY it doesn't matter if we can't
903 * find one. */
904 if (!np->ignore_phy && np->phy_addr_external == PHY_ADDR_NONE) {
1da177e4
LT		 905 dev->if_port = PORT_TP;
906 np->phy_addr_external = PHY_ADDR_INTERNAL;
907 }
908 } else {
909 np->phy_addr_external = PHY_ADDR_INTERNAL;
910 }
911
912 option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
913 if (dev->mem_start)
914 option = dev->mem_start;
915
916 /* The lower four bits are the media type. */
917 if (option) {
918 if (option & 0x200)
919 np->full_duplex = 1;
920 if (option & 15)
921 printk(KERN_INFO
922 "natsemi %s: ignoring user supplied media type %d",
923 pci_name(np->pci_dev), option & 15);
924 }
925 if (find_cnt < MAX_UNITS && full_duplex[find_cnt])
926 np->full_duplex = 1;
927
928 /* The chip-specific entries in the device structure. */
929 dev->open = &netdev_open;
930 dev->hard_start_xmit = &start_tx;
931 dev->stop = &netdev_close;
932 dev->get_stats = &get_stats;
933 dev->set_multicast_list = &set_rx_mode;
934 dev->change_mtu = &natsemi_change_mtu;
935 dev->do_ioctl = &netdev_ioctl;
936 dev->tx_timeout = &tx_timeout;
937 dev->watchdog_timeo = TX_TIMEOUT;
b27a16b7 938
1da177e4
LT		 939#ifdef CONFIG_NET_POLL_CONTROLLER
940 dev->poll_controller = &natsemi_poll_controller;
941#endif
942 SET_ETHTOOL_OPS(dev, &ethtool_ops);
943
944 if (mtu)
945 dev->mtu = mtu;
946
5a40f09b 947 natsemi_init_media(dev);
1da177e4
LT		 948
949 /* save the silicon revision for later querying */
950 np->srr = readl(ioaddr + SiliconRev);
951 if (netif_msg_hw(np))
952 printk(KERN_INFO "natsemi %s: silicon revision %#04x.\n",
953 pci_name(np->pci_dev), np->srr);
954
955 i = register_netdev(dev);
956 if (i)
957 goto err_register_netdev;
958
1a147809
MB		 959 if (NATSEMI_CREATE_FILE(pdev, dspcfg_workaround))
960 goto err_create_file;
961
1da177e4 962 if (netif_msg_drv(np)) {
0795af57
JP		 963 printk(KERN_INFO "natsemi %s: %s at %#08lx "
964 "(%s), %s, IRQ %d",
965 dev->name, natsemi_pci_info[chip_idx].name, iostart,
966 pci_name(np->pci_dev), print_mac(mac, dev->dev_addr), irq);
1da177e4
LT		 967 if (dev->if_port == PORT_TP)
968 printk(", port TP.\n");
68c90166
MB		 969 else if (np->ignore_phy)
970 printk(", port MII, ignoring PHY\n");
1da177e4
LT		 971 else
972 printk(", port MII, phy ad %d.\n", np->phy_addr_external);
973 }
974 return 0;
975
1a147809
MB		 976 err_create_file:
977 unregister_netdev(dev);
978
1da177e4
LT		 979 err_register_netdev:
980 iounmap(ioaddr);
981
982 err_ioremap:
983 pci_release_regions(pdev);
984 pci_set_drvdata(pdev, NULL);
985
986 err_pci_request_regions:
987 free_netdev(dev);
988 return i;
989}
990
991
992/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces.
993 The EEPROM code is for the common 93c06/46 EEPROMs with 6 bit addresses. */
994
995/* Delay between EEPROM clock transitions.
996 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
997 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
998 made udelay() unreliable.
999 The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is
405bbe9f 1000 deprecated.
1da177e4
LT		 1001*/
1002#define eeprom_delay(ee_addr) readl(ee_addr)
1003
1004#define EE_Write0 (EE_ChipSelect)
1005#define EE_Write1 (EE_ChipSelect | EE_DataIn)
1006
1007/* The EEPROM commands include the alway-set leading bit. */
1008enum EEPROM_Cmds {
1009 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
1010};
1011
1012static int eeprom_read(void __iomem *addr, int location)
1013{
1014 int i;
1015 int retval = 0;
1016 void __iomem *ee_addr = addr + EECtrl;
1017 int read_cmd = location | EE_ReadCmd;
1018
1019 writel(EE_Write0, ee_addr);
1020
1021 /* Shift the read command bits out. */
1022 for (i = 10; i >= 0; i--) {
1023 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
1024 writel(dataval, ee_addr);
1025 eeprom_delay(ee_addr);
1026 writel(dataval | EE_ShiftClk, ee_addr);
1027 eeprom_delay(ee_addr);
1028 }
1029 writel(EE_ChipSelect, ee_addr);
1030 eeprom_delay(ee_addr);
1031
1032 for (i = 0; i < 16; i++) {
1033 writel(EE_ChipSelect | EE_ShiftClk, ee_addr);
1034 eeprom_delay(ee_addr);
1035 retval |= (readl(ee_addr) & EE_DataOut) ? 1 << i : 0;
1036 writel(EE_ChipSelect, ee_addr);
1037 eeprom_delay(ee_addr);
1038 }
1039
1040 /* Terminate the EEPROM access. */
1041 writel(EE_Write0, ee_addr);
1042 writel(0, ee_addr);
1043 return retval;
1044}
1045
1046/* MII transceiver control section.
1047 * The 83815 series has an internal transceiver, and we present the
1048 * internal management registers as if they were MII connected.
1049 * External Phy registers are referenced through the MII interface.
1050 */
1051
1052/* clock transitions >= 20ns (25MHz)
1053 * One readl should be good to PCI @ 100MHz
1054 */
1055#define mii_delay(ioaddr) readl(ioaddr + EECtrl)
1056
1057static int mii_getbit (struct net_device *dev)
1058{
1059 int data;
1060 void __iomem *ioaddr = ns_ioaddr(dev);
1061
1062 writel(MII_ShiftClk, ioaddr + EECtrl);
1063 data = readl(ioaddr + EECtrl);
1064 writel(0, ioaddr + EECtrl);
1065 mii_delay(ioaddr);
1066 return (data & MII_Data)? 1 : 0;
1067}
1068
1069static void mii_send_bits (struct net_device *dev, u32 data, int len)
1070{
1071 u32 i;
1072 void __iomem *ioaddr = ns_ioaddr(dev);
1073
1074 for (i = (1 << (len-1)); i; i >>= 1)
1075 {
1076 u32 mdio_val = MII_Write | ((data & i)? MII_Data : 0);
1077 writel(mdio_val, ioaddr + EECtrl);
1078 mii_delay(ioaddr);
1079 writel(mdio_val | MII_ShiftClk, ioaddr + EECtrl);
1080 mii_delay(ioaddr);
1081 }
1082 writel(0, ioaddr + EECtrl);
1083 mii_delay(ioaddr);
1084}
1085
1086static int miiport_read(struct net_device *dev, int phy_id, int reg)
1087{
1088 u32 cmd;
1089 int i;
1090 u32 retval = 0;
1091
1092 /* Ensure sync */
1093 mii_send_bits (dev, 0xffffffff, 32);
1094 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1095 /* ST,OP = 0110'b for read operation */
1096 cmd = (0x06 << 10) | (phy_id << 5) | reg;
1097 mii_send_bits (dev, cmd, 14);
1098 /* Turnaround */
1099 if (mii_getbit (dev))
1100 return 0;
1101 /* Read data */
1102 for (i = 0; i < 16; i++) {
1103 retval <<= 1;
1104 retval |= mii_getbit (dev);
1105 }
1106 /* End cycle */
1107 mii_getbit (dev);
1108 return retval;
1109}
1110
1111static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data)
1112{
1113 u32 cmd;
1114
1115 /* Ensure sync */
1116 mii_send_bits (dev, 0xffffffff, 32);
1117 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1118 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1119 cmd = (0x5002 << 16) | (phy_id << 23) | (reg << 18) | data;
1120 mii_send_bits (dev, cmd, 32);
1121 /* End cycle */
1122 mii_getbit (dev);
1123}
1124
1125static int mdio_read(struct net_device *dev, int reg)
1126{
1127 struct netdev_private *np = netdev_priv(dev);
1128 void __iomem *ioaddr = ns_ioaddr(dev);
1129
1130 /* The 83815 series has two ports:
1131 * - an internal transceiver
1132 * - an external mii bus
1133 */
1134 if (dev->if_port == PORT_TP)
1135 return readw(ioaddr+BasicControl+(reg<<2));
1136 else
1137 return miiport_read(dev, np->phy_addr_external, reg);
1138}
1139
1140static void mdio_write(struct net_device *dev, int reg, u16 data)
1141{
1142 struct netdev_private *np = netdev_priv(dev);
1143 void __iomem *ioaddr = ns_ioaddr(dev);
1144
1145 /* The 83815 series has an internal transceiver; handle separately */
1146 if (dev->if_port == PORT_TP)
1147 writew(data, ioaddr+BasicControl+(reg<<2));
1148 else
1149 miiport_write(dev, np->phy_addr_external, reg, data);
1150}
1151
1152static void init_phy_fixup(struct net_device *dev)
1153{
1154 struct netdev_private *np = netdev_priv(dev);
1155 void __iomem *ioaddr = ns_ioaddr(dev);
1156 int i;
1157 u32 cfg;
1158 u16 tmp;
1159
1160 /* restore stuff lost when power was out */
1161 tmp = mdio_read(dev, MII_BMCR);
1162 if (np->autoneg == AUTONEG_ENABLE) {
1163 /* renegotiate if something changed */
1164 if ((tmp & BMCR_ANENABLE) == 0
1165 || np->advertising != mdio_read(dev, MII_ADVERTISE))
1166 {
1167 /* turn on autonegotiation and force negotiation */
1168 tmp |= (BMCR_ANENABLE | BMCR_ANRESTART);
1169 mdio_write(dev, MII_ADVERTISE, np->advertising);
1170 }
1171 } else {
1172 /* turn off auto negotiation, set speed and duplexity */
1173 tmp &= ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX);
1174 if (np->speed == SPEED_100)
1175 tmp |= BMCR_SPEED100;
1176 if (np->duplex == DUPLEX_FULL)
1177 tmp |= BMCR_FULLDPLX;
6aa20a22 1178 /*
1da177e4
LT		 1179 * Note: there is no good way to inform the link partner
1180 * that our capabilities changed. The user has to unplug
1181 * and replug the network cable after some changes, e.g.
1182 * after switching from 10HD, autoneg off to 100 HD,
1183 * autoneg off.
1184 */
1185 }
1186 mdio_write(dev, MII_BMCR, tmp);
1187 readl(ioaddr + ChipConfig);
1188 udelay(1);
1189
1190 /* find out what phy this is */
1191 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1192 + mdio_read(dev, MII_PHYSID2);
1193
1194 /* handle external phys here */
1195 switch (np->mii) {
1196 case PHYID_AM79C874:
1197 /* phy specific configuration for fibre/tp operation */
1198 tmp = mdio_read(dev, MII_MCTRL);
1199 tmp &= ~(MII_FX_SEL | MII_EN_SCRM);
1200 if (dev->if_port == PORT_FIBRE)
1201 tmp |= MII_FX_SEL;
1202 else
1203 tmp |= MII_EN_SCRM;
1204 mdio_write(dev, MII_MCTRL, tmp);
1205 break;
1206 default:
1207 break;
1208 }
1209 cfg = readl(ioaddr + ChipConfig);
1210 if (cfg & CfgExtPhy)
1211 return;
1212
1213 /* On page 78 of the spec, they recommend some settings for "optimum
1214 performance" to be done in sequence. These settings optimize some
1215 of the 100Mbit autodetection circuitry. They say we only want to
1216 do this for rev C of the chip, but engineers at NSC (Bradley
1217 Kennedy) recommends always setting them. If you don't, you get
1218 errors on some autonegotiations that make the device unusable.
1219
1220 It seems that the DSP needs a few usec to reinitialize after
1221 the start of the phy. Just retry writing these values until they
1222 stick.
1223 */
1224 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1225
1226 int dspcfg;
1227 writew(1, ioaddr + PGSEL);
1228 writew(PMDCSR_VAL, ioaddr + PMDCSR);
1229 writew(TSTDAT_VAL, ioaddr + TSTDAT);
1230 np->dspcfg = (np->srr <= SRR_DP83815_C)?
1231 DSPCFG_VAL : (DSPCFG_COEF | readw(ioaddr + DSPCFG));
1232 writew(np->dspcfg, ioaddr + DSPCFG);
1233 writew(SDCFG_VAL, ioaddr + SDCFG);
1234 writew(0, ioaddr + PGSEL);
1235 readl(ioaddr + ChipConfig);
1236 udelay(10);
1237
1238 writew(1, ioaddr + PGSEL);
1239 dspcfg = readw(ioaddr + DSPCFG);
1240 writew(0, ioaddr + PGSEL);
1241 if (np->dspcfg == dspcfg)
1242 break;
1243 }
1244
1245 if (netif_msg_link(np)) {
1246 if (i==NATSEMI_HW_TIMEOUT) {
1247 printk(KERN_INFO
1248 "%s: DSPCFG mismatch after retrying for %d usec.\n",
1249 dev->name, i*10);
1250 } else {
1251 printk(KERN_INFO
1252 "%s: DSPCFG accepted after %d usec.\n",
1253 dev->name, i*10);
1254 }
1255 }
1256 /*
1257 * Enable PHY Specific event based interrupts. Link state change
1258 * and Auto-Negotiation Completion are among the affected.
1259 * Read the intr status to clear it (needed for wake events).
1260 */
1261 readw(ioaddr + MIntrStatus);
1262 writew(MICRIntEn, ioaddr + MIntrCtrl);
1263}
1264
1265static int switch_port_external(struct net_device *dev)
1266{
1267 struct netdev_private *np = netdev_priv(dev);
1268 void __iomem *ioaddr = ns_ioaddr(dev);
1269 u32 cfg;
1270
1271 cfg = readl(ioaddr + ChipConfig);
1272 if (cfg & CfgExtPhy)
1273 return 0;
1274
1275 if (netif_msg_link(np)) {
1276 printk(KERN_INFO "%s: switching to external transceiver.\n",
1277 dev->name);
1278 }
1279
1280 /* 1) switch back to external phy */
1281 writel(cfg | (CfgExtPhy | CfgPhyDis), ioaddr + ChipConfig);
1282 readl(ioaddr + ChipConfig);
1283 udelay(1);
1284
1285 /* 2) reset the external phy: */
1286 /* resetting the external PHY has been known to cause a hub supplying
1287 * power over Ethernet to kill the power. We don't want to kill
1288 * power to this computer, so we avoid resetting the phy.
1289 */
1290
1291 /* 3) reinit the phy fixup, it got lost during power down. */
1292 move_int_phy(dev, np->phy_addr_external);
1293 init_phy_fixup(dev);
1294
1295 return 1;
1296}
1297
1298static int switch_port_internal(struct net_device *dev)
1299{
1300 struct netdev_private *np = netdev_priv(dev);
1301 void __iomem *ioaddr = ns_ioaddr(dev);
1302 int i;
1303 u32 cfg;
1304 u16 bmcr;
1305
1306 cfg = readl(ioaddr + ChipConfig);
1307 if (!(cfg &CfgExtPhy))
1308 return 0;
1309
1310 if (netif_msg_link(np)) {
1311 printk(KERN_INFO "%s: switching to internal transceiver.\n",
1312 dev->name);
1313 }
1314 /* 1) switch back to internal phy: */
1315 cfg = cfg & ~(CfgExtPhy | CfgPhyDis);
1316 writel(cfg, ioaddr + ChipConfig);
1317 readl(ioaddr + ChipConfig);
1318 udelay(1);
6aa20a22 1319
1da177e4
LT		 1320 /* 2) reset the internal phy: */
1321 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1322 writel(bmcr | BMCR_RESET, ioaddr+BasicControl+(MII_BMCR<<2));
1323 readl(ioaddr + ChipConfig);
1324 udelay(10);
1325 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1326 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1327 if (!(bmcr & BMCR_RESET))
1328 break;
1329 udelay(10);
1330 }
1331 if (i==NATSEMI_HW_TIMEOUT && netif_msg_link(np)) {
1332 printk(KERN_INFO
1333 "%s: phy reset did not complete in %d usec.\n",
1334 dev->name, i*10);
1335 }
1336 /* 3) reinit the phy fixup, it got lost during power down. */
1337 init_phy_fixup(dev);
1338
1339 return 1;
1340}
1341
1342/* Scan for a PHY on the external mii bus.
1343 * There are two tricky points:
1344 * - Do not scan while the internal phy is enabled. The internal phy will
1345 * crash: e.g. reads from the DSPCFG register will return odd values and
1346 * the nasty random phy reset code will reset the nic every few seconds.
1347 * - The internal phy must be moved around, an external phy could
1348 * have the same address as the internal phy.
1349 */
1350static int find_mii(struct net_device *dev)
1351{
1352 struct netdev_private *np = netdev_priv(dev);
1353 int tmp;
1354 int i;
1355 int did_switch;
1356
1357 /* Switch to external phy */
1358 did_switch = switch_port_external(dev);
6aa20a22 1359
1da177e4
LT		 1360 /* Scan the possible phy addresses:
1361 *
1362 * PHY address 0 means that the phy is in isolate mode. Not yet
1363 * supported due to lack of test hardware. User space should
1364 * handle it through ethtool.
1365 */
1366 for (i = 1; i <= 31; i++) {
1367 move_int_phy(dev, i);
1368 tmp = miiport_read(dev, i, MII_BMSR);
1369 if (tmp != 0xffff && tmp != 0x0000) {
1370 /* found something! */
1371 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1372 + mdio_read(dev, MII_PHYSID2);
1373 if (netif_msg_probe(np)) {
1374 printk(KERN_INFO "natsemi %s: found external phy %08x at address %d.\n",
1375 pci_name(np->pci_dev), np->mii, i);
1376 }
1377 break;
1378 }
1379 }
1380 /* And switch back to internal phy: */
1381 if (did_switch)
1382 switch_port_internal(dev);
1383 return i;
1384}
1385
1386/* CFG bits [13:16] [18:23] */
1387#define CFG_RESET_SAVE 0xfde000
1388/* WCSR bits [0:4] [9:10] */
1389#define WCSR_RESET_SAVE 0x61f
1390/* RFCR bits [20] [22] [27:31] */
1391#define RFCR_RESET_SAVE 0xf8500000;
1392
1393static void natsemi_reset(struct net_device *dev)
1394{
1395 int i;
1396 u32 cfg;
1397 u32 wcsr;
1398 u32 rfcr;
1399 u16 pmatch[3];
1400 u16 sopass[3];
1401 struct netdev_private *np = netdev_priv(dev);
1402 void __iomem *ioaddr = ns_ioaddr(dev);
1403
1404 /*
1405 * Resetting the chip causes some registers to be lost.
1406 * Natsemi suggests NOT reloading the EEPROM while live, so instead
1407 * we save the state that would have been loaded from EEPROM
1408 * on a normal power-up (see the spec EEPROM map). This assumes
1409 * whoever calls this will follow up with init_registers() eventually.
1410 */
1411
1412 /* CFG */
1413 cfg = readl(ioaddr + ChipConfig) & CFG_RESET_SAVE;
1414 /* WCSR */
1415 wcsr = readl(ioaddr + WOLCmd) & WCSR_RESET_SAVE;
1416 /* RFCR */
1417 rfcr = readl(ioaddr + RxFilterAddr) & RFCR_RESET_SAVE;
1418 /* PMATCH */
1419 for (i = 0; i < 3; i++) {
1420 writel(i*2, ioaddr + RxFilterAddr);
1421 pmatch[i] = readw(ioaddr + RxFilterData);
1422 }
1423 /* SOPAS */
1424 for (i = 0; i < 3; i++) {
1425 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1426 sopass[i] = readw(ioaddr + RxFilterData);
1427 }
1428
1429 /* now whack the chip */
1430 writel(ChipReset, ioaddr + ChipCmd);
1431 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1432 if (!(readl(ioaddr + ChipCmd) & ChipReset))
1433 break;
1434 udelay(5);
1435 }
1436 if (i==NATSEMI_HW_TIMEOUT) {
1437 printk(KERN_WARNING "%s: reset did not complete in %d usec.\n",
1438 dev->name, i*5);
1439 } else if (netif_msg_hw(np)) {
1440 printk(KERN_DEBUG "%s: reset completed in %d usec.\n",
1441 dev->name, i*5);
1442 }
1443
1444 /* restore CFG */
1445 cfg |= readl(ioaddr + ChipConfig) & ~CFG_RESET_SAVE;
1446 /* turn on external phy if it was selected */
1447 if (dev->if_port == PORT_TP)
1448 cfg &= ~(CfgExtPhy | CfgPhyDis);
1449 else
1450 cfg |= (CfgExtPhy | CfgPhyDis);
1451 writel(cfg, ioaddr + ChipConfig);
1452 /* restore WCSR */
1453 wcsr |= readl(ioaddr + WOLCmd) & ~WCSR_RESET_SAVE;
1454 writel(wcsr, ioaddr + WOLCmd);
1455 /* read RFCR */
1456 rfcr |= readl(ioaddr + RxFilterAddr) & ~RFCR_RESET_SAVE;
1457 /* restore PMATCH */
1458 for (i = 0; i < 3; i++) {
1459 writel(i*2, ioaddr + RxFilterAddr);
1460 writew(pmatch[i], ioaddr + RxFilterData);
1461 }
1462 for (i = 0; i < 3; i++) {
1463 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1464 writew(sopass[i], ioaddr + RxFilterData);
1465 }
1466 /* restore RFCR */
1467 writel(rfcr, ioaddr + RxFilterAddr);
1468}
1469
e72fd96e
MB		 1470static void reset_rx(struct net_device *dev)
1471{
1472 int i;
1473 struct netdev_private *np = netdev_priv(dev);
1474 void __iomem *ioaddr = ns_ioaddr(dev);
1475
1476 np->intr_status &= ~RxResetDone;
1477
1478 writel(RxReset, ioaddr + ChipCmd);
1479
1480 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1481 np->intr_status |= readl(ioaddr + IntrStatus);
1482 if (np->intr_status & RxResetDone)
1483 break;
1484 udelay(15);
1485 }
1486 if (i==NATSEMI_HW_TIMEOUT) {
1487 printk(KERN_WARNING "%s: RX reset did not complete in %d usec.\n",
1488 dev->name, i*15);
1489 } else if (netif_msg_hw(np)) {
1490 printk(KERN_WARNING "%s: RX reset took %d usec.\n",
1491 dev->name, i*15);
1492 }
1493}
1494
1da177e4
LT		 1495static void natsemi_reload_eeprom(struct net_device *dev)
1496{
1497 struct netdev_private *np = netdev_priv(dev);
1498 void __iomem *ioaddr = ns_ioaddr(dev);
1499 int i;
1500
1501 writel(EepromReload, ioaddr + PCIBusCfg);
1502 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1503 udelay(50);
1504 if (!(readl(ioaddr + PCIBusCfg) & EepromReload))
1505 break;
1506 }
1507 if (i==NATSEMI_HW_TIMEOUT) {
1508 printk(KERN_WARNING "natsemi %s: EEPROM did not reload in %d usec.\n",
1509 pci_name(np->pci_dev), i*50);
1510 } else if (netif_msg_hw(np)) {
1511 printk(KERN_DEBUG "natsemi %s: EEPROM reloaded in %d usec.\n",
1512 pci_name(np->pci_dev), i*50);
1513 }
1514}
1515
1516static void natsemi_stop_rxtx(struct net_device *dev)
1517{
1518 void __iomem * ioaddr = ns_ioaddr(dev);
1519 struct netdev_private *np = netdev_priv(dev);
1520 int i;
1521
1522 writel(RxOff | TxOff, ioaddr + ChipCmd);
1523 for(i=0;i< NATSEMI_HW_TIMEOUT;i++) {
1524 if ((readl(ioaddr + ChipCmd) & (TxOn|RxOn)) == 0)
1525 break;
1526 udelay(5);
1527 }
1528 if (i==NATSEMI_HW_TIMEOUT) {
1529 printk(KERN_WARNING "%s: Tx/Rx process did not stop in %d usec.\n",
1530 dev->name, i*5);
1531 } else if (netif_msg_hw(np)) {
1532 printk(KERN_DEBUG "%s: Tx/Rx process stopped in %d usec.\n",
1533 dev->name, i*5);
1534 }
1535}
1536
1537static int netdev_open(struct net_device *dev)
1538{
1539 struct netdev_private *np = netdev_priv(dev);
1540 void __iomem * ioaddr = ns_ioaddr(dev);
1541 int i;
1542
1543 /* Reset the chip, just in case. */
1544 natsemi_reset(dev);
1545
1fb9df5d 1546 i = request_irq(dev->irq, &intr_handler, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 1547 if (i) return i;
1548
1549 if (netif_msg_ifup(np))
1550 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
1551 dev->name, dev->irq);
1552 i = alloc_ring(dev);
1553 if (i < 0) {
1554 free_irq(dev->irq, dev);
1555 return i;
1556 }
bea3348e
SH		 1557 napi_enable(&np->napi);
1558
1da177e4
LT		 1559 init_ring(dev);
1560 spin_lock_irq(&np->lock);
1561 init_registers(dev);
1562 /* now set the MAC address according to dev->dev_addr */
1563 for (i = 0; i < 3; i++) {
1564 u16 mac = (dev->dev_addr[2*i+1]<<8) + dev->dev_addr[2*i];
1565
1566 writel(i*2, ioaddr + RxFilterAddr);
1567 writew(mac, ioaddr + RxFilterData);
1568 }
1569 writel(np->cur_rx_mode, ioaddr + RxFilterAddr);
1570 spin_unlock_irq(&np->lock);
1571
1572 netif_start_queue(dev);
1573
1574 if (netif_msg_ifup(np))
1575 printk(KERN_DEBUG "%s: Done netdev_open(), status: %#08x.\n",
1576 dev->name, (int)readl(ioaddr + ChipCmd));
1577
1578 /* Set the timer to check for link beat. */
1579 init_timer(&np->timer);
0e5d5442 1580 np->timer.expires = round_jiffies(jiffies + NATSEMI_TIMER_FREQ);
1da177e4
LT		 1581 np->timer.data = (unsigned long)dev;
1582 np->timer.function = &netdev_timer; /* timer handler */
1583 add_timer(&np->timer);
1584
1585 return 0;
1586}
1587
1588static void do_cable_magic(struct net_device *dev)
1589{
1590 struct netdev_private *np = netdev_priv(dev);
1591 void __iomem *ioaddr = ns_ioaddr(dev);
1592
1593 if (dev->if_port != PORT_TP)
1594 return;
1595
1596 if (np->srr >= SRR_DP83816_A5)
1597 return;
1598
1599 /*
1600 * 100 MBit links with short cables can trip an issue with the chip.
1601 * The problem manifests as lots of CRC errors and/or flickering
1602 * activity LED while idle. This process is based on instructions
1603 * from engineers at National.
1604 */
1605 if (readl(ioaddr + ChipConfig) & CfgSpeed100) {
1606 u16 data;
1607
1608 writew(1, ioaddr + PGSEL);
1609 /*
1610 * coefficient visibility should already be enabled via
1611 * DSPCFG | 0x1000
1612 */
1613 data = readw(ioaddr + TSTDAT) & 0xff;
1614 /*
1615 * the value must be negative, and within certain values
1616 * (these values all come from National)
1617 */
1618 if (!(data & 0x80) || ((data >= 0xd8) && (data <= 0xff))) {
ddfce6bb 1619 np = netdev_priv(dev);
1da177e4
LT		 1620
1621 /* the bug has been triggered - fix the coefficient */
1622 writew(TSTDAT_FIXED, ioaddr + TSTDAT);
1623 /* lock the value */
1624 data = readw(ioaddr + DSPCFG);
1625 np->dspcfg = data | DSPCFG_LOCK;
1626 writew(np->dspcfg, ioaddr + DSPCFG);
1627 }
1628 writew(0, ioaddr + PGSEL);
1629 }
1630}
1631
1632static void undo_cable_magic(struct net_device *dev)
1633{
1634 u16 data;
1635 struct netdev_private *np = netdev_priv(dev);
1636 void __iomem * ioaddr = ns_ioaddr(dev);
1637
1638 if (dev->if_port != PORT_TP)
1639 return;
1640
1641 if (np->srr >= SRR_DP83816_A5)
1642 return;
1643
1644 writew(1, ioaddr + PGSEL);
1645 /* make sure the lock bit is clear */
1646 data = readw(ioaddr + DSPCFG);
1647 np->dspcfg = data & ~DSPCFG_LOCK;
1648 writew(np->dspcfg, ioaddr + DSPCFG);
1649 writew(0, ioaddr + PGSEL);
1650}
1651
1652static void check_link(struct net_device *dev)
1653{
1654 struct netdev_private *np = netdev_priv(dev);
1655 void __iomem * ioaddr = ns_ioaddr(dev);
68c90166 1656 int duplex = np->duplex;
1da177e4 1657 u16 bmsr;
6aa20a22 1658
68c90166
MB		 1659 /* If we are ignoring the PHY then don't try reading it. */
1660 if (np->ignore_phy)
1661 goto propagate_state;
1662
1da177e4
LT		 1663 /* The link status field is latched: it remains low after a temporary
1664 * link failure until it's read. We need the current link status,
1665 * thus read twice.
1666 */
1667 mdio_read(dev, MII_BMSR);
1668 bmsr = mdio_read(dev, MII_BMSR);
1669
1670 if (!(bmsr & BMSR_LSTATUS)) {
1671 if (netif_carrier_ok(dev)) {
1672 if (netif_msg_link(np))
1673 printk(KERN_NOTICE "%s: link down.\n",
68c90166 1674 dev->name);
1da177e4
LT		 1675 netif_carrier_off(dev);
1676 undo_cable_magic(dev);
1677 }
1678 return;
1679 }
1680 if (!netif_carrier_ok(dev)) {
1681 if (netif_msg_link(np))
1682 printk(KERN_NOTICE "%s: link up.\n", dev->name);
1683 netif_carrier_on(dev);
1684 do_cable_magic(dev);
1685 }
1686
1687 duplex = np->full_duplex;
1688 if (!duplex) {
1689 if (bmsr & BMSR_ANEGCOMPLETE) {
1690 int tmp = mii_nway_result(
1691 np->advertising & mdio_read(dev, MII_LPA));
1692 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
1693 duplex = 1;
1694 } else if (mdio_read(dev, MII_BMCR) & BMCR_FULLDPLX)
1695 duplex = 1;
1696 }
1697
68c90166 1698propagate_state:
1da177e4
LT		 1699 /* if duplex is set then bit 28 must be set, too */
1700 if (duplex ^ !!(np->rx_config & RxAcceptTx)) {
1701 if (netif_msg_link(np))
1702 printk(KERN_INFO
1703 "%s: Setting %s-duplex based on negotiated "
1704 "link capability.\n", dev->name,
1705 duplex ? "full" : "half");
1706 if (duplex) {
1707 np->rx_config |= RxAcceptTx;
1708 np->tx_config |= TxCarrierIgn | TxHeartIgn;
1709 } else {
1710 np->rx_config &= ~RxAcceptTx;
1711 np->tx_config &= ~(TxCarrierIgn | TxHeartIgn);
1712 }
1713 writel(np->tx_config, ioaddr + TxConfig);
1714 writel(np->rx_config, ioaddr + RxConfig);
1715 }
1716}
1717
1718static void init_registers(struct net_device *dev)
1719{
1720 struct netdev_private *np = netdev_priv(dev);
1721 void __iomem * ioaddr = ns_ioaddr(dev);
1722
1723 init_phy_fixup(dev);
1724
1725 /* clear any interrupts that are pending, such as wake events */
1726 readl(ioaddr + IntrStatus);
1727
1728 writel(np->ring_dma, ioaddr + RxRingPtr);
1729 writel(np->ring_dma + RX_RING_SIZE * sizeof(struct netdev_desc),
1730 ioaddr + TxRingPtr);
1731
1732 /* Initialize other registers.
1733 * Configure the PCI bus bursts and FIFO thresholds.
1734 * Configure for standard, in-spec Ethernet.
1735 * Start with half-duplex. check_link will update
1736 * to the correct settings.
1737 */
1738
1739 /* DRTH: 2: start tx if 64 bytes are in the fifo
1740 * FLTH: 0x10: refill with next packet if 512 bytes are free
1741 * MXDMA: 0: up to 256 byte bursts.
1742 * MXDMA must be <= FLTH
1743 * ECRETRY=1
1744 * ATP=1
1745 */
1746 np->tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 |
1747 TX_FLTH_VAL | TX_DRTH_VAL_START;
1748 writel(np->tx_config, ioaddr + TxConfig);
1749
1750 /* DRTH 0x10: start copying to memory if 128 bytes are in the fifo
1751 * MXDMA 0: up to 256 byte bursts
1752 */
1753 np->rx_config = RxMxdma_256 | RX_DRTH_VAL;
1754 /* if receive ring now has bigger buffers than normal, enable jumbo */
1755 if (np->rx_buf_sz > NATSEMI_LONGPKT)
1756 np->rx_config |= RxAcceptLong;
1757
1758 writel(np->rx_config, ioaddr + RxConfig);
1759
1760 /* Disable PME:
1761 * The PME bit is initialized from the EEPROM contents.
1762 * PCI cards probably have PME disabled, but motherboard
1763 * implementations may have PME set to enable WakeOnLan.
1764 * With PME set the chip will scan incoming packets but
1765 * nothing will be written to memory. */
1766 np->SavedClkRun = readl(ioaddr + ClkRun);
1767 writel(np->SavedClkRun & ~PMEEnable, ioaddr + ClkRun);
1768 if (np->SavedClkRun & PMEStatus && netif_msg_wol(np)) {
1769 printk(KERN_NOTICE "%s: Wake-up event %#08x\n",
1770 dev->name, readl(ioaddr + WOLCmd));
1771 }
1772
1773 check_link(dev);
1774 __set_rx_mode(dev);
1775
1776 /* Enable interrupts by setting the interrupt mask. */
1777 writel(DEFAULT_INTR, ioaddr + IntrMask);
14fdd90e 1778 natsemi_irq_enable(dev);
1da177e4
LT		 1779
1780 writel(RxOn | TxOn, ioaddr + ChipCmd);
1781 writel(StatsClear, ioaddr + StatsCtrl); /* Clear Stats */
1782}
1783
1784/*
1785 * netdev_timer:
1786 * Purpose:
1787 * 1) check for link changes. Usually they are handled by the MII interrupt
1788 * but it doesn't hurt to check twice.
1789 * 2) check for sudden death of the NIC:
1790 * It seems that a reference set for this chip went out with incorrect info,
1791 * and there exist boards that aren't quite right. An unexpected voltage
1792 * drop can cause the PHY to get itself in a weird state (basically reset).
1a147809
MB		 1793 * NOTE: this only seems to affect revC chips. The user can disable
1794 * this check via dspcfg_workaround sysfs option.
1da177e4
LT		 1795 * 3) check of death of the RX path due to OOM
1796 */
1797static void netdev_timer(unsigned long data)
1798{
1799 struct net_device *dev = (struct net_device *)data;
1800 struct netdev_private *np = netdev_priv(dev);
1801 void __iomem * ioaddr = ns_ioaddr(dev);
f2cade13 1802 int next_tick = NATSEMI_TIMER_FREQ;
1da177e4
LT		 1803
1804 if (netif_msg_timer(np)) {
1805 /* DO NOT read the IntrStatus register,
1806 * a read clears any pending interrupts.
1807 */
1808 printk(KERN_DEBUG "%s: Media selection timer tick.\n",
1809 dev->name);
1810 }
1811
1812 if (dev->if_port == PORT_TP) {
1813 u16 dspcfg;
1814
1815 spin_lock_irq(&np->lock);
1816 /* check for a nasty random phy-reset - use dspcfg as a flag */
1817 writew(1, ioaddr+PGSEL);
1818 dspcfg = readw(ioaddr+DSPCFG);
1819 writew(0, ioaddr+PGSEL);
1a147809 1820 if (np->dspcfg_workaround && dspcfg != np->dspcfg) {
1da177e4
LT		 1821 if (!netif_queue_stopped(dev)) {
1822 spin_unlock_irq(&np->lock);
d0ed4864 1823 if (netif_msg_drv(np))
1da177e4
LT		 1824 printk(KERN_NOTICE "%s: possible phy reset: "
1825 "re-initializing\n", dev->name);
1826 disable_irq(dev->irq);
1827 spin_lock_irq(&np->lock);
1828 natsemi_stop_rxtx(dev);
1829 dump_ring(dev);
1830 reinit_ring(dev);
1831 init_registers(dev);
1832 spin_unlock_irq(&np->lock);
1833 enable_irq(dev->irq);
1834 } else {
1835 /* hurry back */
1836 next_tick = HZ;
1837 spin_unlock_irq(&np->lock);
1838 }
1839 } else {
1840 /* init_registers() calls check_link() for the above case */
1841 check_link(dev);
1842 spin_unlock_irq(&np->lock);
1843 }
1844 } else {
1845 spin_lock_irq(&np->lock);
1846 check_link(dev);
1847 spin_unlock_irq(&np->lock);
1848 }
1849 if (np->oom) {
1850 disable_irq(dev->irq);
1851 np->oom = 0;
1852 refill_rx(dev);
1853 enable_irq(dev->irq);
1854 if (!np->oom) {
1855 writel(RxOn, ioaddr + ChipCmd);
1856 } else {
1857 next_tick = 1;
1858 }
1859 }
0e5d5442
MB		 1860
1861 if (next_tick > 1)
1862 mod_timer(&np->timer, round_jiffies(jiffies + next_tick));
1863 else
1864 mod_timer(&np->timer, jiffies + next_tick);
1da177e4
LT		 1865}
1866
1867static void dump_ring(struct net_device *dev)
1868{
1869 struct netdev_private *np = netdev_priv(dev);
1870
1871 if (netif_msg_pktdata(np)) {
1872 int i;
1873 printk(KERN_DEBUG " Tx ring at %p:\n", np->tx_ring);
1874 for (i = 0; i < TX_RING_SIZE; i++) {
1875 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1876 i, np->tx_ring[i].next_desc,
1877 np->tx_ring[i].cmd_status,
1878 np->tx_ring[i].addr);
1879 }
1880 printk(KERN_DEBUG " Rx ring %p:\n", np->rx_ring);
1881 for (i = 0; i < RX_RING_SIZE; i++) {
1882 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1883 i, np->rx_ring[i].next_desc,
1884 np->rx_ring[i].cmd_status,
1885 np->rx_ring[i].addr);
1886 }
1887 }
1888}
1889
1890static void tx_timeout(struct net_device *dev)
1891{
1892 struct netdev_private *np = netdev_priv(dev);
1893 void __iomem * ioaddr = ns_ioaddr(dev);
1894
1895 disable_irq(dev->irq);
1896 spin_lock_irq(&np->lock);
1897 if (!np->hands_off) {
1898 if (netif_msg_tx_err(np))
1899 printk(KERN_WARNING
1900 "%s: Transmit timed out, status %#08x,"
1901 " resetting...\n",
1902 dev->name, readl(ioaddr + IntrStatus));
1903 dump_ring(dev);
1904
1905 natsemi_reset(dev);
1906 reinit_ring(dev);
1907 init_registers(dev);
1908 } else {
1909 printk(KERN_WARNING
1910 "%s: tx_timeout while in hands_off state?\n",
1911 dev->name);
1912 }
1913 spin_unlock_irq(&np->lock);
1914 enable_irq(dev->irq);
1915
1916 dev->trans_start = jiffies;
1917 np->stats.tx_errors++;
1918 netif_wake_queue(dev);
1919}
1920
1921static int alloc_ring(struct net_device *dev)
1922{
1923 struct netdev_private *np = netdev_priv(dev);
1924 np->rx_ring = pci_alloc_consistent(np->pci_dev,
1925 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
1926 &np->ring_dma);
1927 if (!np->rx_ring)
1928 return -ENOMEM;
1929 np->tx_ring = &np->rx_ring[RX_RING_SIZE];
1930 return 0;
1931}
1932
1933static void refill_rx(struct net_device *dev)
1934{
1935 struct netdev_private *np = netdev_priv(dev);
1936
1937 /* Refill the Rx ring buffers. */
1938 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1939 struct sk_buff *skb;
1940 int entry = np->dirty_rx % RX_RING_SIZE;
1941 if (np->rx_skbuff[entry] == NULL) {
1942 unsigned int buflen = np->rx_buf_sz+NATSEMI_PADDING;
1943 skb = dev_alloc_skb(buflen);
1944 np->rx_skbuff[entry] = skb;
1945 if (skb == NULL)
1946 break; /* Better luck next round. */
1947 skb->dev = dev; /* Mark as being used by this device. */
1948 np->rx_dma[entry] = pci_map_single(np->pci_dev,
689be439 1949 skb->data, buflen, PCI_DMA_FROMDEVICE);
1da177e4
LT		 1950 np->rx_ring[entry].addr = cpu_to_le32(np->rx_dma[entry]);
1951 }
1952 np->rx_ring[entry].cmd_status = cpu_to_le32(np->rx_buf_sz);
1953 }
1954 if (np->cur_rx - np->dirty_rx == RX_RING_SIZE) {
1955 if (netif_msg_rx_err(np))
1956 printk(KERN_WARNING "%s: going OOM.\n", dev->name);
1957 np->oom = 1;
1958 }
1959}
1960
1961static void set_bufsize(struct net_device *dev)
1962{
1963 struct netdev_private *np = netdev_priv(dev);
1964 if (dev->mtu <= ETH_DATA_LEN)
1965 np->rx_buf_sz = ETH_DATA_LEN + NATSEMI_HEADERS;
1966 else
1967 np->rx_buf_sz = dev->mtu + NATSEMI_HEADERS;
1968}
1969
1970/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1971static void init_ring(struct net_device *dev)
1972{
1973 struct netdev_private *np = netdev_priv(dev);
1974 int i;
1975
1976 /* 1) TX ring */
1977 np->dirty_tx = np->cur_tx = 0;
1978 for (i = 0; i < TX_RING_SIZE; i++) {
1979 np->tx_skbuff[i] = NULL;
1980 np->tx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1981 +sizeof(struct netdev_desc)
1982 *((i+1)%TX_RING_SIZE+RX_RING_SIZE));
1983 np->tx_ring[i].cmd_status = 0;
1984 }
1985
1986 /* 2) RX ring */
1987 np->dirty_rx = 0;
1988 np->cur_rx = RX_RING_SIZE;
1989 np->oom = 0;
1990 set_bufsize(dev);
1991
1992 np->rx_head_desc = &np->rx_ring[0];
1993
1994 /* Please be carefull before changing this loop - at least gcc-2.95.1
1995 * miscompiles it otherwise.
1996 */
1997 /* Initialize all Rx descriptors. */
1998 for (i = 0; i < RX_RING_SIZE; i++) {
1999 np->rx_ring[i].next_desc = cpu_to_le32(np->ring_dma
2000 +sizeof(struct netdev_desc)
2001 *((i+1)%RX_RING_SIZE));
2002 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
2003 np->rx_skbuff[i] = NULL;
2004 }
2005 refill_rx(dev);
2006 dump_ring(dev);
2007}
2008
2009static void drain_tx(struct net_device *dev)
2010{
2011 struct netdev_private *np = netdev_priv(dev);
2012 int i;
2013
2014 for (i = 0; i < TX_RING_SIZE; i++) {
2015 if (np->tx_skbuff[i]) {
2016 pci_unmap_single(np->pci_dev,
2017 np->tx_dma[i], np->tx_skbuff[i]->len,
2018 PCI_DMA_TODEVICE);
2019 dev_kfree_skb(np->tx_skbuff[i]);
2020 np->stats.tx_dropped++;
2021 }
2022 np->tx_skbuff[i] = NULL;
2023 }
2024}
2025
2026static void drain_rx(struct net_device *dev)
2027{
2028 struct netdev_private *np = netdev_priv(dev);
2029 unsigned int buflen = np->rx_buf_sz;
2030 int i;
2031
2032 /* Free all the skbuffs in the Rx queue. */
2033 for (i = 0; i < RX_RING_SIZE; i++) {
2034 np->rx_ring[i].cmd_status = 0;
2035 np->rx_ring[i].addr = 0xBADF00D0; /* An invalid address. */
2036 if (np->rx_skbuff[i]) {
2037 pci_unmap_single(np->pci_dev,
2038 np->rx_dma[i], buflen,
2039 PCI_DMA_FROMDEVICE);
2040 dev_kfree_skb(np->rx_skbuff[i]);
2041 }
2042 np->rx_skbuff[i] = NULL;
2043 }
2044}
2045
2046static void drain_ring(struct net_device *dev)
2047{
2048 drain_rx(dev);
2049 drain_tx(dev);
2050}
2051
2052static void free_ring(struct net_device *dev)
2053{
2054 struct netdev_private *np = netdev_priv(dev);
2055 pci_free_consistent(np->pci_dev,
2056 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
2057 np->rx_ring, np->ring_dma);
2058}
2059
2060static void reinit_rx(struct net_device *dev)
2061{
2062 struct netdev_private *np = netdev_priv(dev);
2063 int i;
2064
2065 /* RX Ring */
2066 np->dirty_rx = 0;
2067 np->cur_rx = RX_RING_SIZE;
2068 np->rx_head_desc = &np->rx_ring[0];
2069 /* Initialize all Rx descriptors. */
2070 for (i = 0; i < RX_RING_SIZE; i++)
2071 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
2072
2073 refill_rx(dev);
2074}
2075
2076static void reinit_ring(struct net_device *dev)
2077{
2078 struct netdev_private *np = netdev_priv(dev);
2079 int i;
2080
2081 /* drain TX ring */
2082 drain_tx(dev);
2083 np->dirty_tx = np->cur_tx = 0;
2084 for (i=0;i<TX_RING_SIZE;i++)
2085 np->tx_ring[i].cmd_status = 0;
2086
2087 reinit_rx(dev);
2088}
2089
2090static int start_tx(struct sk_buff *skb, struct net_device *dev)
2091{
2092 struct netdev_private *np = netdev_priv(dev);
2093 void __iomem * ioaddr = ns_ioaddr(dev);
2094 unsigned entry;
6006f7f5 2095 unsigned long flags;
1da177e4
LT		 2096
2097 /* Note: Ordering is important here, set the field with the
2098 "ownership" bit last, and only then increment cur_tx. */
2099
2100 /* Calculate the next Tx descriptor entry. */
2101 entry = np->cur_tx % TX_RING_SIZE;
2102
2103 np->tx_skbuff[entry] = skb;
2104 np->tx_dma[entry] = pci_map_single(np->pci_dev,
2105 skb->data,skb->len, PCI_DMA_TODEVICE);
2106
2107 np->tx_ring[entry].addr = cpu_to_le32(np->tx_dma[entry]);
2108
6006f7f5 2109 spin_lock_irqsave(&np->lock, flags);
1da177e4
LT		 2110
2111 if (!np->hands_off) {
2112 np->tx_ring[entry].cmd_status = cpu_to_le32(DescOwn | skb->len);
2113 /* StrongARM: Explicitly cache flush np->tx_ring and
2114 * skb->data,skb->len. */
2115 wmb();
2116 np->cur_tx++;
2117 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1) {
2118 netdev_tx_done(dev);
2119 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1)
2120 netif_stop_queue(dev);
2121 }
2122 /* Wake the potentially-idle transmit channel. */
2123 writel(TxOn, ioaddr + ChipCmd);
2124 } else {
2125 dev_kfree_skb_irq(skb);
2126 np->stats.tx_dropped++;
2127 }
6006f7f5 2128 spin_unlock_irqrestore(&np->lock, flags);
1da177e4
LT		 2129
2130 dev->trans_start = jiffies;
2131
2132 if (netif_msg_tx_queued(np)) {
2133 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
2134 dev->name, np->cur_tx, entry);
2135 }
2136 return 0;
2137}
2138
2139static void netdev_tx_done(struct net_device *dev)
2140{
2141 struct netdev_private *np = netdev_priv(dev);
2142
2143 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
2144 int entry = np->dirty_tx % TX_RING_SIZE;
2145 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescOwn))
2146 break;
2147 if (netif_msg_tx_done(np))
2148 printk(KERN_DEBUG
2149 "%s: tx frame #%d finished, status %#08x.\n",
2150 dev->name, np->dirty_tx,
2151 le32_to_cpu(np->tx_ring[entry].cmd_status));
2152 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescPktOK)) {
2153 np->stats.tx_packets++;
2154 np->stats.tx_bytes += np->tx_skbuff[entry]->len;
2155 } else { /* Various Tx errors */
2156 int tx_status =
2157 le32_to_cpu(np->tx_ring[entry].cmd_status);
2158 if (tx_status & (DescTxAbort|DescTxExcColl))
2159 np->stats.tx_aborted_errors++;
2160 if (tx_status & DescTxFIFO)
2161 np->stats.tx_fifo_errors++;
2162 if (tx_status & DescTxCarrier)
2163 np->stats.tx_carrier_errors++;
2164 if (tx_status & DescTxOOWCol)
2165 np->stats.tx_window_errors++;
2166 np->stats.tx_errors++;
2167 }
2168 pci_unmap_single(np->pci_dev,np->tx_dma[entry],
2169 np->tx_skbuff[entry]->len,
2170 PCI_DMA_TODEVICE);
2171 /* Free the original skb. */
2172 dev_kfree_skb_irq(np->tx_skbuff[entry]);
2173 np->tx_skbuff[entry] = NULL;
2174 }
2175 if (netif_queue_stopped(dev)
2176 && np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
2177 /* The ring is no longer full, wake queue. */
2178 netif_wake_queue(dev);
2179 }
2180}
2181
b27a16b7
MB		 2182/* The interrupt handler doesn't actually handle interrupts itself, it
2183 * schedules a NAPI poll if there is anything to do. */
7d12e780 2184static irqreturn_t intr_handler(int irq, void *dev_instance)
1da177e4
LT		 2185{
2186 struct net_device *dev = dev_instance;
2187 struct netdev_private *np = netdev_priv(dev);
2188 void __iomem * ioaddr = ns_ioaddr(dev);
1da177e4 2189
069f8256 2190 /* Reading IntrStatus automatically acknowledges so don't do
2191 * that while interrupts are disabled, (for example, while a
2192 * poll is scheduled). */
2193 if (np->hands_off || !readl(ioaddr + IntrEnable))
1da177e4 2194 return IRQ_NONE;
6aa20a22 2195
b27a16b7 2196 np->intr_status = readl(ioaddr + IntrStatus);
1da177e4 2197
069f8256 2198 if (!np->intr_status)
2199 return IRQ_NONE;
2200
b27a16b7
MB		 2201 if (netif_msg_intr(np))
2202 printk(KERN_DEBUG
2203 "%s: Interrupt, status %#08x, mask %#08x.\n",
2204 dev->name, np->intr_status,
2205 readl(ioaddr + IntrMask));
1da177e4 2206
b27a16b7
MB		 2207 prefetch(&np->rx_skbuff[np->cur_rx % RX_RING_SIZE]);
2208
bea3348e 2209 if (netif_rx_schedule_prep(dev, &np->napi)) {
b27a16b7
MB		 2210 /* Disable interrupts and register for poll */
2211 natsemi_irq_disable(dev);
bea3348e 2212 __netif_rx_schedule(dev, &np->napi);
069f8256 2213 } else
2214 printk(KERN_WARNING
2215 "%s: Ignoring interrupt, status %#08x, mask %#08x.\n",
2216 dev->name, np->intr_status,
2217 readl(ioaddr + IntrMask));
2218
b27a16b7
MB		 2219 return IRQ_HANDLED;
2220}
2221
2222/* This is the NAPI poll routine. As well as the standard RX handling
2223 * it also handles all other interrupts that the chip might raise.
2224 */
bea3348e 2225static int natsemi_poll(struct napi_struct *napi, int budget)
b27a16b7 2226{
bea3348e
SH		 2227 struct netdev_private *np = container_of(napi, struct netdev_private, napi);
2228 struct net_device *dev = np->dev;
b27a16b7 2229 void __iomem * ioaddr = ns_ioaddr(dev);
b27a16b7
MB		 2230 int work_done = 0;
2231
2232 do {
069f8256 2233 if (netif_msg_intr(np))
2234 printk(KERN_DEBUG
2235 "%s: Poll, status %#08x, mask %#08x.\n",
2236 dev->name, np->intr_status,
2237 readl(ioaddr + IntrMask));
2238
d2a90036 2239 /* netdev_rx() may read IntrStatus again if the RX state
2240 * machine falls over so do it first. */
2241 if (np->intr_status &
2242 (IntrRxDone | IntrRxIntr | RxStatusFIFOOver |
2243 IntrRxErr | IntrRxOverrun)) {
bea3348e 2244 netdev_rx(dev, &work_done, budget);
d2a90036 2245 }
2246
b27a16b7
MB		 2247 if (np->intr_status &
2248 (IntrTxDone | IntrTxIntr | IntrTxIdle | IntrTxErr)) {
1da177e4
LT		 2249 spin_lock(&np->lock);
2250 netdev_tx_done(dev);
2251 spin_unlock(&np->lock);
2252 }
2253
2254 /* Abnormal error summary/uncommon events handlers. */
b27a16b7
MB		 2255 if (np->intr_status & IntrAbnormalSummary)
2256 netdev_error(dev, np->intr_status);
6aa20a22 2257
bea3348e
SH		 2258 if (work_done >= budget)
2259 return work_done;
b27a16b7
MB		 2260
2261 np->intr_status = readl(ioaddr + IntrStatus);
2262 } while (np->intr_status);
1da177e4 2263
bea3348e 2264 netif_rx_complete(dev, napi);
b27a16b7
MB		 2265
2266 /* Reenable interrupts providing nothing is trying to shut
2267 * the chip down. */
2268 spin_lock(&np->lock);
4ec24119 2269 if (!np->hands_off)
b27a16b7
MB		 2270 natsemi_irq_enable(dev);
2271 spin_unlock(&np->lock);
2272
bea3348e 2273 return work_done;
1da177e4
LT		 2274}
2275
2276/* This routine is logically part of the interrupt handler, but separated
2277 for clarity and better register allocation. */
b27a16b7 2278static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do)
1da177e4
LT		 2279{
2280 struct netdev_private *np = netdev_priv(dev);
2281 int entry = np->cur_rx % RX_RING_SIZE;
2282 int boguscnt = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
2283 s32 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2284 unsigned int buflen = np->rx_buf_sz;
2285 void __iomem * ioaddr = ns_ioaddr(dev);
2286
2287 /* If the driver owns the next entry it's a new packet. Send it up. */
2288 while (desc_status < 0) { /* e.g. & DescOwn */
2289 int pkt_len;
2290 if (netif_msg_rx_status(np))
2291 printk(KERN_DEBUG
2292 " netdev_rx() entry %d status was %#08x.\n",
2293 entry, desc_status);
2294 if (--boguscnt < 0)
2295 break;
b27a16b7
MB		 2296
2297 if (*work_done >= work_to_do)
2298 break;
2299
2300 (*work_done)++;
2301
1da177e4
LT		 2302 pkt_len = (desc_status & DescSizeMask) - 4;
2303 if ((desc_status&(DescMore|DescPktOK|DescRxLong)) != DescPktOK){
2304 if (desc_status & DescMore) {
6006f7f5
SS		 2305 unsigned long flags;
2306
1da177e4
LT		 2307 if (netif_msg_rx_err(np))
2308 printk(KERN_WARNING
2309 "%s: Oversized(?) Ethernet "
2310 "frame spanned multiple "
2311 "buffers, entry %#08x "
2312 "status %#08x.\n", dev->name,
2313 np->cur_rx, desc_status);
2314 np->stats.rx_length_errors++;
e72fd96e
MB		 2315
2316 /* The RX state machine has probably
2317 * locked up beneath us. Follow the
2318 * reset procedure documented in
2319 * AN-1287. */
2320
6006f7f5 2321 spin_lock_irqsave(&np->lock, flags);
e72fd96e
MB		 2322 reset_rx(dev);
2323 reinit_rx(dev);
2324 writel(np->ring_dma, ioaddr + RxRingPtr);
2325 check_link(dev);
6006f7f5 2326 spin_unlock_irqrestore(&np->lock, flags);
e72fd96e
MB		 2327
2328 /* We'll enable RX on exit from this
2329 * function. */
2330 break;
2331
1da177e4
LT		 2332 } else {
2333 /* There was an error. */
2334 np->stats.rx_errors++;
2335 if (desc_status & (DescRxAbort|DescRxOver))
2336 np->stats.rx_over_errors++;
2337 if (desc_status & (DescRxLong|DescRxRunt))
2338 np->stats.rx_length_errors++;
2339 if (desc_status & (DescRxInvalid|DescRxAlign))
2340 np->stats.rx_frame_errors++;
2341 if (desc_status & DescRxCRC)
2342 np->stats.rx_crc_errors++;
2343 }
2344 } else if (pkt_len > np->rx_buf_sz) {
2345 /* if this is the tail of a double buffer
2346 * packet, we've already counted the error
2347 * on the first part. Ignore the second half.
2348 */
2349 } else {
2350 struct sk_buff *skb;
2351 /* Omit CRC size. */
2352 /* Check if the packet is long enough to accept
2353 * without copying to a minimally-sized skbuff. */
2354 if (pkt_len < rx_copybreak
2355 && (skb = dev_alloc_skb(pkt_len + RX_OFFSET)) != NULL) {
1da177e4
LT		 2356 /* 16 byte align the IP header */
2357 skb_reserve(skb, RX_OFFSET);
2358 pci_dma_sync_single_for_cpu(np->pci_dev,
2359 np->rx_dma[entry],
2360 buflen,
2361 PCI_DMA_FROMDEVICE);
8c7b7faa
DM		 2362 skb_copy_to_linear_data(skb,
2363 np->rx_skbuff[entry]->data, pkt_len);
1da177e4
LT		 2364 skb_put(skb, pkt_len);
2365 pci_dma_sync_single_for_device(np->pci_dev,
2366 np->rx_dma[entry],
2367 buflen,
2368 PCI_DMA_FROMDEVICE);
2369 } else {
2370 pci_unmap_single(np->pci_dev, np->rx_dma[entry],
2371 buflen, PCI_DMA_FROMDEVICE);
2372 skb_put(skb = np->rx_skbuff[entry], pkt_len);
2373 np->rx_skbuff[entry] = NULL;
2374 }
2375 skb->protocol = eth_type_trans(skb, dev);
b27a16b7 2376 netif_receive_skb(skb);
1da177e4
LT		 2377 dev->last_rx = jiffies;
2378 np->stats.rx_packets++;
2379 np->stats.rx_bytes += pkt_len;
2380 }
2381 entry = (++np->cur_rx) % RX_RING_SIZE;
2382 np->rx_head_desc = &np->rx_ring[entry];
2383 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2384 }
2385 refill_rx(dev);
2386
2387 /* Restart Rx engine if stopped. */
2388 if (np->oom)
2389 mod_timer(&np->timer, jiffies + 1);
2390 else
2391 writel(RxOn, ioaddr + ChipCmd);
2392}
2393
2394static void netdev_error(struct net_device *dev, int intr_status)
2395{
2396 struct netdev_private *np = netdev_priv(dev);
2397 void __iomem * ioaddr = ns_ioaddr(dev);
2398
2399 spin_lock(&np->lock);
2400 if (intr_status & LinkChange) {
2401 u16 lpa = mdio_read(dev, MII_LPA);
2402 if (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE
2403 && netif_msg_link(np)) {
2404 printk(KERN_INFO
2405 "%s: Autonegotiation advertising"
2406 " %#04x partner %#04x.\n", dev->name,
2407 np->advertising, lpa);
2408 }
2409
2410 /* read MII int status to clear the flag */
2411 readw(ioaddr + MIntrStatus);
2412 check_link(dev);
2413 }
2414 if (intr_status & StatsMax) {
2415 __get_stats(dev);
2416 }
2417 if (intr_status & IntrTxUnderrun) {
2418 if ((np->tx_config & TxDrthMask) < TX_DRTH_VAL_LIMIT) {
2419 np->tx_config += TX_DRTH_VAL_INC;
2420 if (netif_msg_tx_err(np))
2421 printk(KERN_NOTICE
2422 "%s: increased tx threshold, txcfg %#08x.\n",
2423 dev->name, np->tx_config);
2424 } else {
2425 if (netif_msg_tx_err(np))
2426 printk(KERN_NOTICE
2427 "%s: tx underrun with maximum tx threshold, txcfg %#08x.\n",
2428 dev->name, np->tx_config);
2429 }
2430 writel(np->tx_config, ioaddr + TxConfig);
2431 }
2432 if (intr_status & WOLPkt && netif_msg_wol(np)) {
2433 int wol_status = readl(ioaddr + WOLCmd);
2434 printk(KERN_NOTICE "%s: Link wake-up event %#08x\n",
2435 dev->name, wol_status);
2436 }
2437 if (intr_status & RxStatusFIFOOver) {
2438 if (netif_msg_rx_err(np) && netif_msg_intr(np)) {
2439 printk(KERN_NOTICE "%s: Rx status FIFO overrun\n",
2440 dev->name);
2441 }
2442 np->stats.rx_fifo_errors++;
c76720cf 2443 np->stats.rx_errors++;
1da177e4
LT		 2444 }
2445 /* Hmmmmm, it's not clear how to recover from PCI faults. */
2446 if (intr_status & IntrPCIErr) {
2447 printk(KERN_NOTICE "%s: PCI error %#08x\n", dev->name,
2448 intr_status & IntrPCIErr);
2449 np->stats.tx_fifo_errors++;
c76720cf 2450 np->stats.tx_errors++;
1da177e4 2451 np->stats.rx_fifo_errors++;
c76720cf 2452 np->stats.rx_errors++;
1da177e4
LT		 2453 }
2454 spin_unlock(&np->lock);
2455}
2456
2457static void __get_stats(struct net_device *dev)
2458{
2459 void __iomem * ioaddr = ns_ioaddr(dev);
2460 struct netdev_private *np = netdev_priv(dev);
2461
2462 /* The chip only need report frame silently dropped. */
2463 np->stats.rx_crc_errors += readl(ioaddr + RxCRCErrs);
2464 np->stats.rx_missed_errors += readl(ioaddr + RxMissed);
2465}
2466
2467static struct net_device_stats *get_stats(struct net_device *dev)
2468{
2469 struct netdev_private *np = netdev_priv(dev);
2470
2471 /* The chip only need report frame silently dropped. */
2472 spin_lock_irq(&np->lock);
2473 if (netif_running(dev) && !np->hands_off)
2474 __get_stats(dev);
2475 spin_unlock_irq(&np->lock);
2476
2477 return &np->stats;
2478}
2479
2480#ifdef CONFIG_NET_POLL_CONTROLLER
2481static void natsemi_poll_controller(struct net_device *dev)
2482{
2483 disable_irq(dev->irq);
069f8256 2484 intr_handler(dev->irq, dev);
1da177e4
LT		 2485 enable_irq(dev->irq);
2486}
2487#endif
2488
2489#define HASH_TABLE 0x200
2490static void __set_rx_mode(struct net_device *dev)
2491{
2492 void __iomem * ioaddr = ns_ioaddr(dev);
2493 struct netdev_private *np = netdev_priv(dev);
2494 u8 mc_filter[64]; /* Multicast hash filter */
2495 u32 rx_mode;
2496
2497 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1da177e4
LT		 2498 rx_mode = RxFilterEnable | AcceptBroadcast
2499 | AcceptAllMulticast | AcceptAllPhys | AcceptMyPhys;
2500 } else if ((dev->mc_count > multicast_filter_limit)
2501 || (dev->flags & IFF_ALLMULTI)) {
2502 rx_mode = RxFilterEnable | AcceptBroadcast
2503 | AcceptAllMulticast | AcceptMyPhys;
2504 } else {
2505 struct dev_mc_list *mclist;
2506 int i;
2507 memset(mc_filter, 0, sizeof(mc_filter));
2508 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2509 i++, mclist = mclist->next) {
ddfce6bb
SH		 2510 int b = (ether_crc(ETH_ALEN, mclist->dmi_addr) >> 23) & 0x1ff;
2511 mc_filter[b/8] |= (1 << (b & 0x07));
1da177e4
LT		 2512 }
2513 rx_mode = RxFilterEnable | AcceptBroadcast
2514 | AcceptMulticast | AcceptMyPhys;
2515 for (i = 0; i < 64; i += 2) {
760f86d7
HX		 2516 writel(HASH_TABLE + i, ioaddr + RxFilterAddr);
2517 writel((mc_filter[i + 1] << 8) + mc_filter[i],
2518 ioaddr + RxFilterData);
1da177e4
LT		 2519 }
2520 }
2521 writel(rx_mode, ioaddr + RxFilterAddr);
2522 np->cur_rx_mode = rx_mode;
2523}
2524
2525static int natsemi_change_mtu(struct net_device *dev, int new_mtu)
2526{
2527 if (new_mtu < 64 || new_mtu > NATSEMI_RX_LIMIT-NATSEMI_HEADERS)
2528 return -EINVAL;
2529
2530 dev->mtu = new_mtu;
2531
2532 /* synchronized against open : rtnl_lock() held by caller */
2533 if (netif_running(dev)) {
2534 struct netdev_private *np = netdev_priv(dev);
2535 void __iomem * ioaddr = ns_ioaddr(dev);
2536
2537 disable_irq(dev->irq);
2538 spin_lock(&np->lock);
2539 /* stop engines */
2540 natsemi_stop_rxtx(dev);
2541 /* drain rx queue */
2542 drain_rx(dev);
2543 /* change buffers */
2544 set_bufsize(dev);
2545 reinit_rx(dev);
2546 writel(np->ring_dma, ioaddr + RxRingPtr);
2547 /* restart engines */
2548 writel(RxOn | TxOn, ioaddr + ChipCmd);
2549 spin_unlock(&np->lock);
2550 enable_irq(dev->irq);
2551 }
2552 return 0;
2553}
2554
2555static void set_rx_mode(struct net_device *dev)
2556{
2557 struct netdev_private *np = netdev_priv(dev);
2558 spin_lock_irq(&np->lock);
2559 if (!np->hands_off)
2560 __set_rx_mode(dev);
2561 spin_unlock_irq(&np->lock);
2562}
2563
2564static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2565{
2566 struct netdev_private *np = netdev_priv(dev);
2567 strncpy(info->driver, DRV_NAME, ETHTOOL_BUSINFO_LEN);
2568 strncpy(info->version, DRV_VERSION, ETHTOOL_BUSINFO_LEN);
2569 strncpy(info->bus_info, pci_name(np->pci_dev), ETHTOOL_BUSINFO_LEN);
2570}
2571
2572static int get_regs_len(struct net_device *dev)
2573{
2574 return NATSEMI_REGS_SIZE;
2575}
2576
2577static int get_eeprom_len(struct net_device *dev)
2578{
a8b4cf42
MB		 2579 struct netdev_private *np = netdev_priv(dev);
2580 return np->eeprom_size;
1da177e4
LT		 2581}
2582
2583static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2584{
2585 struct netdev_private *np = netdev_priv(dev);
2586 spin_lock_irq(&np->lock);
2587 netdev_get_ecmd(dev, ecmd);
2588 spin_unlock_irq(&np->lock);
2589 return 0;
2590}
2591
2592static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2593{
2594 struct netdev_private *np = netdev_priv(dev);
2595 int res;
2596 spin_lock_irq(&np->lock);
2597 res = netdev_set_ecmd(dev, ecmd);
2598 spin_unlock_irq(&np->lock);
2599 return res;
2600}
2601
2602static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2603{
2604 struct netdev_private *np = netdev_priv(dev);
2605 spin_lock_irq(&np->lock);
2606 netdev_get_wol(dev, &wol->supported, &wol->wolopts);
2607 netdev_get_sopass(dev, wol->sopass);
2608 spin_unlock_irq(&np->lock);
2609}
2610
2611static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2612{
2613 struct netdev_private *np = netdev_priv(dev);
2614 int res;
2615 spin_lock_irq(&np->lock);
2616 netdev_set_wol(dev, wol->wolopts);
2617 res = netdev_set_sopass(dev, wol->sopass);
2618 spin_unlock_irq(&np->lock);
2619 return res;
2620}
2621
2622static void get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
2623{
2624 struct netdev_private *np = netdev_priv(dev);
2625 regs->version = NATSEMI_REGS_VER;
2626 spin_lock_irq(&np->lock);
2627 netdev_get_regs(dev, buf);
2628 spin_unlock_irq(&np->lock);
2629}
2630
2631static u32 get_msglevel(struct net_device *dev)
2632{
2633 struct netdev_private *np = netdev_priv(dev);
2634 return np->msg_enable;
2635}
2636
2637static void set_msglevel(struct net_device *dev, u32 val)
2638{
2639 struct netdev_private *np = netdev_priv(dev);
2640 np->msg_enable = val;
2641}
2642
2643static int nway_reset(struct net_device *dev)
2644{
2645 int tmp;
2646 int r = -EINVAL;
2647 /* if autoneg is off, it's an error */
2648 tmp = mdio_read(dev, MII_BMCR);
2649 if (tmp & BMCR_ANENABLE) {
2650 tmp |= (BMCR_ANRESTART);
2651 mdio_write(dev, MII_BMCR, tmp);
2652 r = 0;
2653 }
2654 return r;
2655}
2656
2657static u32 get_link(struct net_device *dev)
2658{
2659 /* LSTATUS is latched low until a read - so read twice */
2660 mdio_read(dev, MII_BMSR);
2661 return (mdio_read(dev, MII_BMSR)&BMSR_LSTATUS) ? 1:0;
2662}
2663
2664static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
2665{
2666 struct netdev_private *np = netdev_priv(dev);
a8b4cf42 2667 u8 *eebuf;
1da177e4
LT		 2668 int res;
2669
a8b4cf42
MB		 2670 eebuf = kmalloc(np->eeprom_size, GFP_KERNEL);
2671 if (!eebuf)
2672 return -ENOMEM;
2673
1da177e4
LT		 2674 eeprom->magic = PCI_VENDOR_ID_NS | (PCI_DEVICE_ID_NS_83815<<16);
2675 spin_lock_irq(&np->lock);
2676 res = netdev_get_eeprom(dev, eebuf);
2677 spin_unlock_irq(&np->lock);
2678 if (!res)
2679 memcpy(data, eebuf+eeprom->offset, eeprom->len);
a8b4cf42 2680 kfree(eebuf);
1da177e4
LT		 2681 return res;
2682}
2683
7282d491 2684static const struct ethtool_ops ethtool_ops = {
1da177e4
LT		 2685 .get_drvinfo = get_drvinfo,
2686 .get_regs_len = get_regs_len,
2687 .get_eeprom_len = get_eeprom_len,
2688 .get_settings = get_settings,
2689 .set_settings = set_settings,
2690 .get_wol = get_wol,
2691 .set_wol = set_wol,
2692 .get_regs = get_regs,
2693 .get_msglevel = get_msglevel,
2694 .set_msglevel = set_msglevel,
2695 .nway_reset = nway_reset,
2696 .get_link = get_link,
2697 .get_eeprom = get_eeprom,
2698};
2699
2700static int netdev_set_wol(struct net_device *dev, u32 newval)
2701{
2702 struct netdev_private *np = netdev_priv(dev);
2703 void __iomem * ioaddr = ns_ioaddr(dev);
2704 u32 data = readl(ioaddr + WOLCmd) & ~WakeOptsSummary;
2705
2706 /* translate to bitmasks this chip understands */
2707 if (newval & WAKE_PHY)
2708 data |= WakePhy;
2709 if (newval & WAKE_UCAST)
2710 data |= WakeUnicast;
2711 if (newval & WAKE_MCAST)
2712 data |= WakeMulticast;
2713 if (newval & WAKE_BCAST)
2714 data |= WakeBroadcast;
2715 if (newval & WAKE_ARP)
2716 data |= WakeArp;
2717 if (newval & WAKE_MAGIC)
2718 data |= WakeMagic;
2719 if (np->srr >= SRR_DP83815_D) {
2720 if (newval & WAKE_MAGICSECURE) {
2721 data |= WakeMagicSecure;
2722 }
2723 }
2724
2725 writel(data, ioaddr + WOLCmd);
2726
2727 return 0;
2728}
2729
2730static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur)
2731{
2732 struct netdev_private *np = netdev_priv(dev);
2733 void __iomem * ioaddr = ns_ioaddr(dev);
2734 u32 regval = readl(ioaddr + WOLCmd);
2735
2736 *supported = (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST
2737 | WAKE_ARP | WAKE_MAGIC);
2738
2739 if (np->srr >= SRR_DP83815_D) {
2740 /* SOPASS works on revD and higher */
2741 *supported |= WAKE_MAGICSECURE;
2742 }
2743 *cur = 0;
2744
2745 /* translate from chip bitmasks */
2746 if (regval & WakePhy)
2747 *cur |= WAKE_PHY;
2748 if (regval & WakeUnicast)
2749 *cur |= WAKE_UCAST;
2750 if (regval & WakeMulticast)
2751 *cur |= WAKE_MCAST;
2752 if (regval & WakeBroadcast)
2753 *cur |= WAKE_BCAST;
2754 if (regval & WakeArp)
2755 *cur |= WAKE_ARP;
2756 if (regval & WakeMagic)
2757 *cur |= WAKE_MAGIC;
2758 if (regval & WakeMagicSecure) {
2759 /* this can be on in revC, but it's broken */
2760 *cur |= WAKE_MAGICSECURE;
2761 }
2762
2763 return 0;
2764}
2765
2766static int netdev_set_sopass(struct net_device *dev, u8 *newval)
2767{
2768 struct netdev_private *np = netdev_priv(dev);
2769 void __iomem * ioaddr = ns_ioaddr(dev);
2770 u16 *sval = (u16 *)newval;
2771 u32 addr;
2772
2773 if (np->srr < SRR_DP83815_D) {
2774 return 0;
2775 }
2776
2777 /* enable writing to these registers by disabling the RX filter */
2778 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2779 addr &= ~RxFilterEnable;
2780 writel(addr, ioaddr + RxFilterAddr);
2781
2782 /* write the three words to (undocumented) RFCR vals 0xa, 0xc, 0xe */
2783 writel(addr | 0xa, ioaddr + RxFilterAddr);
2784 writew(sval[0], ioaddr + RxFilterData);
2785
2786 writel(addr | 0xc, ioaddr + RxFilterAddr);
2787 writew(sval[1], ioaddr + RxFilterData);
2788
2789 writel(addr | 0xe, ioaddr + RxFilterAddr);
2790 writew(sval[2], ioaddr + RxFilterData);
2791
2792 /* re-enable the RX filter */
2793 writel(addr | RxFilterEnable, ioaddr + RxFilterAddr);
2794
2795 return 0;
2796}
2797
2798static int netdev_get_sopass(struct net_device *dev, u8 *data)
2799{
2800 struct netdev_private *np = netdev_priv(dev);
2801 void __iomem * ioaddr = ns_ioaddr(dev);
2802 u16 *sval = (u16 *)data;
2803 u32 addr;
2804
2805 if (np->srr < SRR_DP83815_D) {
2806 sval[0] = sval[1] = sval[2] = 0;
2807 return 0;
2808 }
2809
2810 /* read the three words from (undocumented) RFCR vals 0xa, 0xc, 0xe */
2811 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2812
2813 writel(addr | 0xa, ioaddr + RxFilterAddr);
2814 sval[0] = readw(ioaddr + RxFilterData);
2815
2816 writel(addr | 0xc, ioaddr + RxFilterAddr);
2817 sval[1] = readw(ioaddr + RxFilterData);
2818
2819 writel(addr | 0xe, ioaddr + RxFilterAddr);
2820 sval[2] = readw(ioaddr + RxFilterData);
2821
2822 writel(addr, ioaddr + RxFilterAddr);
2823
2824 return 0;
2825}
2826
2827static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2828{
2829 struct netdev_private *np = netdev_priv(dev);
2830 u32 tmp;
2831
2832 ecmd->port = dev->if_port;
2833 ecmd->speed = np->speed;
2834 ecmd->duplex = np->duplex;
2835 ecmd->autoneg = np->autoneg;
2836 ecmd->advertising = 0;
2837 if (np->advertising & ADVERTISE_10HALF)
2838 ecmd->advertising |= ADVERTISED_10baseT_Half;
2839 if (np->advertising & ADVERTISE_10FULL)
2840 ecmd->advertising |= ADVERTISED_10baseT_Full;
2841 if (np->advertising & ADVERTISE_100HALF)
2842 ecmd->advertising |= ADVERTISED_100baseT_Half;
2843 if (np->advertising & ADVERTISE_100FULL)
2844 ecmd->advertising |= ADVERTISED_100baseT_Full;
2845 ecmd->supported = (SUPPORTED_Autoneg |
2846 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2847 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2848 SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_FIBRE);
2849 ecmd->phy_address = np->phy_addr_external;
2850 /*
2851 * We intentionally report the phy address of the external
2852 * phy, even if the internal phy is used. This is necessary
2853 * to work around a deficiency of the ethtool interface:
2854 * It's only possible to query the settings of the active
6aa20a22 2855 * port. Therefore
1da177e4
LT		 2856 * # ethtool -s ethX port mii
2857 * actually sends an ioctl to switch to port mii with the
2858 * settings that are used for the current active port.
2859 * If we would report a different phy address in this
2860 * command, then
2861 * # ethtool -s ethX port tp;ethtool -s ethX port mii
2862 * would unintentionally change the phy address.
2863 *
2864 * Fortunately the phy address doesn't matter with the
2865 * internal phy...
2866 */
2867
2868 /* set information based on active port type */
2869 switch (ecmd->port) {
2870 default:
2871 case PORT_TP:
2872 ecmd->advertising |= ADVERTISED_TP;
2873 ecmd->transceiver = XCVR_INTERNAL;
2874 break;
2875 case PORT_MII:
2876 ecmd->advertising |= ADVERTISED_MII;
2877 ecmd->transceiver = XCVR_EXTERNAL;
2878 break;
2879 case PORT_FIBRE:
2880 ecmd->advertising |= ADVERTISED_FIBRE;
2881 ecmd->transceiver = XCVR_EXTERNAL;
2882 break;
2883 }
2884
2885 /* if autonegotiation is on, try to return the active speed/duplex */
2886 if (ecmd->autoneg == AUTONEG_ENABLE) {
2887 ecmd->advertising |= ADVERTISED_Autoneg;
2888 tmp = mii_nway_result(
2889 np->advertising & mdio_read(dev, MII_LPA));
2890 if (tmp == LPA_100FULL || tmp == LPA_100HALF)
2891 ecmd->speed = SPEED_100;
2892 else
2893 ecmd->speed = SPEED_10;
2894 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
2895 ecmd->duplex = DUPLEX_FULL;
2896 else
2897 ecmd->duplex = DUPLEX_HALF;
2898 }
2899
2900 /* ignore maxtxpkt, maxrxpkt for now */
2901
2902 return 0;
2903}
2904
2905static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2906{
2907 struct netdev_private *np = netdev_priv(dev);
2908
2909 if (ecmd->port != PORT_TP && ecmd->port != PORT_MII && ecmd->port != PORT_FIBRE)
2910 return -EINVAL;
2911 if (ecmd->transceiver != XCVR_INTERNAL && ecmd->transceiver != XCVR_EXTERNAL)
2912 return -EINVAL;
2913 if (ecmd->autoneg == AUTONEG_ENABLE) {
2914 if ((ecmd->advertising & (ADVERTISED_10baseT_Half |
2915 ADVERTISED_10baseT_Full |
2916 ADVERTISED_100baseT_Half |
2917 ADVERTISED_100baseT_Full)) == 0) {
2918 return -EINVAL;
2919 }
2920 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
2921 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
2922 return -EINVAL;
2923 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
2924 return -EINVAL;
2925 } else {
2926 return -EINVAL;
2927 }
2928
68c90166
MB		 2929 /*
2930 * If we're ignoring the PHY then autoneg and the internal
2931 * transciever are really not going to work so don't let the
2932 * user select them.
2933 */
2934 if (np->ignore_phy && (ecmd->autoneg == AUTONEG_ENABLE ||
2935 ecmd->port == PORT_TP))
2936 return -EINVAL;
2937
1da177e4
LT		 2938 /*
2939 * maxtxpkt, maxrxpkt: ignored for now.
2940 *
2941 * transceiver:
2942 * PORT_TP is always XCVR_INTERNAL, PORT_MII and PORT_FIBRE are always
2943 * XCVR_EXTERNAL. The implementation thus ignores ecmd->transceiver and
2944 * selects based on ecmd->port.
2945 *
2946 * Actually PORT_FIBRE is nearly identical to PORT_MII: it's for fibre
2947 * phys that are connected to the mii bus. It's used to apply fibre
2948 * specific updates.
2949 */
2950
2951 /* WHEW! now lets bang some bits */
2952
2953 /* save the parms */
2954 dev->if_port = ecmd->port;
2955 np->autoneg = ecmd->autoneg;
2956 np->phy_addr_external = ecmd->phy_address & PhyAddrMask;
2957 if (np->autoneg == AUTONEG_ENABLE) {
2958 /* advertise only what has been requested */
2959 np->advertising &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2960 if (ecmd->advertising & ADVERTISED_10baseT_Half)
2961 np->advertising |= ADVERTISE_10HALF;
2962 if (ecmd->advertising & ADVERTISED_10baseT_Full)
2963 np->advertising |= ADVERTISE_10FULL;
2964 if (ecmd->advertising & ADVERTISED_100baseT_Half)
2965 np->advertising |= ADVERTISE_100HALF;
2966 if (ecmd->advertising & ADVERTISED_100baseT_Full)
2967 np->advertising |= ADVERTISE_100FULL;
2968 } else {
2969 np->speed = ecmd->speed;
2970 np->duplex = ecmd->duplex;
2971 /* user overriding the initial full duplex parm? */
2972 if (np->duplex == DUPLEX_HALF)
2973 np->full_duplex = 0;
2974 }
2975
2976 /* get the right phy enabled */
2977 if (ecmd->port == PORT_TP)
2978 switch_port_internal(dev);
2979 else
2980 switch_port_external(dev);
2981
2982 /* set parms and see how this affected our link status */
2983 init_phy_fixup(dev);
2984 check_link(dev);
2985 return 0;
2986}
2987
2988static int netdev_get_regs(struct net_device *dev, u8 *buf)
2989{
2990 int i;
2991 int j;
2992 u32 rfcr;
2993 u32 *rbuf = (u32 *)buf;
2994 void __iomem * ioaddr = ns_ioaddr(dev);
2995
2996 /* read non-mii page 0 of registers */
2997 for (i = 0; i < NATSEMI_PG0_NREGS/2; i++) {
2998 rbuf[i] = readl(ioaddr + i*4);
2999 }
3000
3001 /* read current mii registers */
3002 for (i = NATSEMI_PG0_NREGS/2; i < NATSEMI_PG0_NREGS; i++)
3003 rbuf[i] = mdio_read(dev, i & 0x1f);
3004
3005 /* read only the 'magic' registers from page 1 */
3006 writew(1, ioaddr + PGSEL);
3007 rbuf[i++] = readw(ioaddr + PMDCSR);
3008 rbuf[i++] = readw(ioaddr + TSTDAT);
3009 rbuf[i++] = readw(ioaddr + DSPCFG);
3010 rbuf[i++] = readw(ioaddr + SDCFG);
3011 writew(0, ioaddr + PGSEL);
3012
3013 /* read RFCR indexed registers */
3014 rfcr = readl(ioaddr + RxFilterAddr);
3015 for (j = 0; j < NATSEMI_RFDR_NREGS; j++) {
3016 writel(j*2, ioaddr + RxFilterAddr);
3017 rbuf[i++] = readw(ioaddr + RxFilterData);
3018 }
3019 writel(rfcr, ioaddr + RxFilterAddr);
3020
3021 /* the interrupt status is clear-on-read - see if we missed any */
3022 if (rbuf[4] & rbuf[5]) {
3023 printk(KERN_WARNING
3024 "%s: shoot, we dropped an interrupt (%#08x)\n",
3025 dev->name, rbuf[4] & rbuf[5]);
3026 }
3027
3028 return 0;
3029}
3030
3031#define SWAP_BITS(x) ( (((x) & 0x0001) << 15) | (((x) & 0x0002) << 13) \
3032 | (((x) & 0x0004) << 11) | (((x) & 0x0008) << 9) \
3033 | (((x) & 0x0010) << 7) | (((x) & 0x0020) << 5) \
3034 | (((x) & 0x0040) << 3) | (((x) & 0x0080) << 1) \
3035 | (((x) & 0x0100) >> 1) | (((x) & 0x0200) >> 3) \
3036 | (((x) & 0x0400) >> 5) | (((x) & 0x0800) >> 7) \
3037 | (((x) & 0x1000) >> 9) | (((x) & 0x2000) >> 11) \
3038 | (((x) & 0x4000) >> 13) | (((x) & 0x8000) >> 15) )
3039
3040static int netdev_get_eeprom(struct net_device *dev, u8 *buf)
3041{
3042 int i;
3043 u16 *ebuf = (u16 *)buf;
3044 void __iomem * ioaddr = ns_ioaddr(dev);
a8b4cf42 3045 struct netdev_private *np = netdev_priv(dev);
1da177e4
LT		 3046
3047 /* eeprom_read reads 16 bits, and indexes by 16 bits */
a8b4cf42 3048 for (i = 0; i < np->eeprom_size/2; i++) {
1da177e4
LT		 3049 ebuf[i] = eeprom_read(ioaddr, i);
3050 /* The EEPROM itself stores data bit-swapped, but eeprom_read
3051 * reads it back "sanely". So we swap it back here in order to
3052 * present it to userland as it is stored. */
3053 ebuf[i] = SWAP_BITS(ebuf[i]);
3054 }
3055 return 0;
3056}
3057
3058static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3059{
3060 struct mii_ioctl_data *data = if_mii(rq);
3061 struct netdev_private *np = netdev_priv(dev);
3062
3063 switch(cmd) {
3064 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
3065 case SIOCDEVPRIVATE: /* for binary compat, remove in 2.5 */
3066 data->phy_id = np->phy_addr_external;
3067 /* Fall Through */
3068
3069 case SIOCGMIIREG: /* Read MII PHY register. */
3070 case SIOCDEVPRIVATE+1: /* for binary compat, remove in 2.5 */
3071 /* The phy_id is not enough to uniquely identify
3072 * the intended target. Therefore the command is sent to
3073 * the given mii on the current port.
3074 */
3075 if (dev->if_port == PORT_TP) {
3076 if ((data->phy_id & 0x1f) == np->phy_addr_external)
3077 data->val_out = mdio_read(dev,
3078 data->reg_num & 0x1f);
3079 else
3080 data->val_out = 0;
3081 } else {
3082 move_int_phy(dev, data->phy_id & 0x1f);
3083 data->val_out = miiport_read(dev, data->phy_id & 0x1f,
3084 data->reg_num & 0x1f);
3085 }
3086 return 0;
3087
3088 case SIOCSMIIREG: /* Write MII PHY register. */
3089 case SIOCDEVPRIVATE+2: /* for binary compat, remove in 2.5 */
3090 if (!capable(CAP_NET_ADMIN))
3091 return -EPERM;
3092 if (dev->if_port == PORT_TP) {
3093 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3094 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3095 np->advertising = data->val_in;
3096 mdio_write(dev, data->reg_num & 0x1f,
3097 data->val_in);
3098 }
3099 } else {
3100 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3101 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3102 np->advertising = data->val_in;
3103 }
3104 move_int_phy(dev, data->phy_id & 0x1f);
3105 miiport_write(dev, data->phy_id & 0x1f,
3106 data->reg_num & 0x1f,
3107 data->val_in);
3108 }
3109 return 0;
3110 default:
3111 return -EOPNOTSUPP;
3112 }
3113}
3114
3115static void enable_wol_mode(struct net_device *dev, int enable_intr)
3116{
3117 void __iomem * ioaddr = ns_ioaddr(dev);
3118 struct netdev_private *np = netdev_priv(dev);
3119
3120 if (netif_msg_wol(np))
3121 printk(KERN_INFO "%s: remaining active for wake-on-lan\n",
3122 dev->name);
3123
3124 /* For WOL we must restart the rx process in silent mode.
3125 * Write NULL to the RxRingPtr. Only possible if
3126 * rx process is stopped
3127 */
3128 writel(0, ioaddr + RxRingPtr);
3129
3130 /* read WoL status to clear */
3131 readl(ioaddr + WOLCmd);
3132
3133 /* PME on, clear status */
3134 writel(np->SavedClkRun | PMEEnable | PMEStatus, ioaddr + ClkRun);
3135
3136 /* and restart the rx process */
3137 writel(RxOn, ioaddr + ChipCmd);
3138
3139 if (enable_intr) {
3140 /* enable the WOL interrupt.
3141 * Could be used to send a netlink message.
3142 */
3143 writel(WOLPkt | LinkChange, ioaddr + IntrMask);
14fdd90e 3144 natsemi_irq_enable(dev);
1da177e4
LT		 3145 }
3146}
3147
3148static int netdev_close(struct net_device *dev)
3149{
3150 void __iomem * ioaddr = ns_ioaddr(dev);
3151 struct netdev_private *np = netdev_priv(dev);
3152
3153 if (netif_msg_ifdown(np))
3154 printk(KERN_DEBUG
3155 "%s: Shutting down ethercard, status was %#04x.\n",
3156 dev->name, (int)readl(ioaddr + ChipCmd));
3157 if (netif_msg_pktdata(np))
3158 printk(KERN_DEBUG
3159 "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
3160 dev->name, np->cur_tx, np->dirty_tx,
3161 np->cur_rx, np->dirty_rx);
3162
bea3348e
SH		 3163 napi_disable(&np->napi);
3164
1da177e4
LT		 3165 /*
3166 * FIXME: what if someone tries to close a device
3167 * that is suspended?
3168 * Should we reenable the nic to switch to
3169 * the final WOL settings?
3170 */
3171
3172 del_timer_sync(&np->timer);
3173 disable_irq(dev->irq);
3174 spin_lock_irq(&np->lock);
b27a16b7 3175 natsemi_irq_disable(dev);
1da177e4
LT		 3176 np->hands_off = 1;
3177 spin_unlock_irq(&np->lock);
3178 enable_irq(dev->irq);
3179
3180 free_irq(dev->irq, dev);
3181
3182 /* Interrupt disabled, interrupt handler released,
3183 * queue stopped, timer deleted, rtnl_lock held
3184 * All async codepaths that access the driver are disabled.
3185 */
3186 spin_lock_irq(&np->lock);
3187 np->hands_off = 0;
3188 readl(ioaddr + IntrMask);
3189 readw(ioaddr + MIntrStatus);
3190
3191 /* Freeze Stats */
3192 writel(StatsFreeze, ioaddr + StatsCtrl);
3193
3194 /* Stop the chip's Tx and Rx processes. */
3195 natsemi_stop_rxtx(dev);
3196
3197 __get_stats(dev);
3198 spin_unlock_irq(&np->lock);
3199
3200 /* clear the carrier last - an interrupt could reenable it otherwise */
3201 netif_carrier_off(dev);
3202 netif_stop_queue(dev);
3203
3204 dump_ring(dev);
3205 drain_ring(dev);
3206 free_ring(dev);
3207
3208 {
3209 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3210 if (wol) {
3211 /* restart the NIC in WOL mode.
3212 * The nic must be stopped for this.
3213 */
3214 enable_wol_mode(dev, 0);
3215 } else {
3216 /* Restore PME enable bit unmolested */
3217 writel(np->SavedClkRun, ioaddr + ClkRun);
3218 }
3219 }
3220 return 0;
3221}
3222
3223
3224static void __devexit natsemi_remove1 (struct pci_dev *pdev)
3225{
3226 struct net_device *dev = pci_get_drvdata(pdev);
3227 void __iomem * ioaddr = ns_ioaddr(dev);
3228
1a147809 3229 NATSEMI_REMOVE_FILE(pdev, dspcfg_workaround);
1da177e4
LT		 3230 unregister_netdev (dev);
3231 pci_release_regions (pdev);
3232 iounmap(ioaddr);
3233 free_netdev (dev);
3234 pci_set_drvdata(pdev, NULL);
3235}
3236
3237#ifdef CONFIG_PM
3238
3239/*
3240 * The ns83815 chip doesn't have explicit RxStop bits.
3241 * Kicking the Rx or Tx process for a new packet reenables the Rx process
3242 * of the nic, thus this function must be very careful:
3243 *
3244 * suspend/resume synchronization:
3245 * entry points:
3246 * netdev_open, netdev_close, netdev_ioctl, set_rx_mode, intr_handler,
3247 * start_tx, tx_timeout
3248 *
3249 * No function accesses the hardware without checking np->hands_off.
3250 * the check occurs under spin_lock_irq(&np->lock);
3251 * exceptions:
3252 * * netdev_ioctl: noncritical access.
3253 * * netdev_open: cannot happen due to the device_detach
3254 * * netdev_close: doesn't hurt.
3255 * * netdev_timer: timer stopped by natsemi_suspend.
3256 * * intr_handler: doesn't acquire the spinlock. suspend calls
3257 * disable_irq() to enforce synchronization.
b27a16b7
MB		 3258 * * natsemi_poll: checks before reenabling interrupts. suspend
3259 * sets hands_off, disables interrupts and then waits with
bea3348e 3260 * napi_disable().
1da177e4
LT		 3261 *
3262 * Interrupts must be disabled, otherwise hands_off can cause irq storms.
3263 */
3264
3265static int natsemi_suspend (struct pci_dev *pdev, pm_message_t state)
3266{
3267 struct net_device *dev = pci_get_drvdata (pdev);
3268 struct netdev_private *np = netdev_priv(dev);
3269 void __iomem * ioaddr = ns_ioaddr(dev);
3270
3271 rtnl_lock();
3272 if (netif_running (dev)) {
3273 del_timer_sync(&np->timer);
3274
3275 disable_irq(dev->irq);
3276 spin_lock_irq(&np->lock);
3277
14fdd90e 3278 natsemi_irq_disable(dev);
1da177e4
LT		 3279 np->hands_off = 1;
3280 natsemi_stop_rxtx(dev);
3281 netif_stop_queue(dev);
3282
3283 spin_unlock_irq(&np->lock);
3284 enable_irq(dev->irq);
3285
bea3348e 3286 napi_disable(&np->napi);
b27a16b7 3287
1da177e4
LT		 3288 /* Update the error counts. */
3289 __get_stats(dev);
3290
3291 /* pci_power_off(pdev, -1); */
3292 drain_ring(dev);
3293 {
3294 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3295 /* Restore PME enable bit */
3296 if (wol) {
3297 /* restart the NIC in WOL mode.
3298 * The nic must be stopped for this.
3299 * FIXME: use the WOL interrupt
3300 */
3301 enable_wol_mode(dev, 0);
3302 } else {
3303 /* Restore PME enable bit unmolested */
3304 writel(np->SavedClkRun, ioaddr + ClkRun);
3305 }
3306 }
3307 }
3308 netif_device_detach(dev);
3309 rtnl_unlock();
3310 return 0;
3311}
3312
3313
3314static int natsemi_resume (struct pci_dev *pdev)
3315{
3316 struct net_device *dev = pci_get_drvdata (pdev);
3317 struct netdev_private *np = netdev_priv(dev);
a8a935da 3318 int ret = 0;
1da177e4
LT		 3319
3320 rtnl_lock();
3321 if (netif_device_present(dev))
3322 goto out;
3323 if (netif_running(dev)) {
3324 BUG_ON(!np->hands_off);
a8a935da
MB		 3325 ret = pci_enable_device(pdev);
3326 if (ret < 0) {
3327 dev_err(&pdev->dev,
3328 "pci_enable_device() failed: %d\n", ret);
3329 goto out;
3330 }
1da177e4
LT		 3331 /* pci_power_on(pdev); */
3332
bea3348e
SH		 3333 napi_enable(&np->napi);
3334
1da177e4
LT		 3335 natsemi_reset(dev);
3336 init_ring(dev);
3337 disable_irq(dev->irq);
3338 spin_lock_irq(&np->lock);
3339 np->hands_off = 0;
3340 init_registers(dev);
3341 netif_device_attach(dev);
3342 spin_unlock_irq(&np->lock);
3343 enable_irq(dev->irq);
3344
0e5d5442 3345 mod_timer(&np->timer, round_jiffies(jiffies + 1*HZ));
1da177e4
LT		 3346 }
3347 netif_device_attach(dev);
3348out:
3349 rtnl_unlock();
a8a935da 3350 return ret;
1da177e4
LT		 3351}
3352
3353#endif /* CONFIG_PM */
3354
3355static struct pci_driver natsemi_driver = {
3356 .name = DRV_NAME,
3357 .id_table = natsemi_pci_tbl,
3358 .probe = natsemi_probe1,
3359 .remove = __devexit_p(natsemi_remove1),
3360#ifdef CONFIG_PM
3361 .suspend = natsemi_suspend,
3362 .resume = natsemi_resume,
3363#endif
3364};
3365
3366static int __init natsemi_init_mod (void)
3367{
3368/* when a module, this is printed whether or not devices are found in probe */
3369#ifdef MODULE
3370 printk(version);
3371#endif
3372
29917620 3373 return pci_register_driver(&natsemi_driver);
1da177e4
LT		 3374}
3375
3376static void __exit natsemi_exit_mod (void)
3377{
3378 pci_unregister_driver (&natsemi_driver);
3379}
3380
3381module_init(natsemi_init_mod);
3382module_exit(natsemi_exit_mod);
3383
Linux kernel - Deliverables
This page took 0.664813 seconds and 5 git commands to generate.