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NetXen: Fix softlockup seen during hardware access
[deliverable/linux.git] / drivers / net / natsemi.c
CommitLineData
1da177e4
LT		 1/* natsemi.c: A Linux PCI Ethernet driver for the NatSemi DP8381x series. */
2/*
3 Written/copyright 1999-2001 by Donald Becker.
4 Portions copyright (c) 2001,2002 Sun Microsystems (thockin@sun.com)
5 Portions copyright 2001,2002 Manfred Spraul (manfred@colorfullife.com)
b27a16b7 6 Portions copyright 2004 Harald Welte <laforge@gnumonks.org>
1da177e4
LT		 7
8 This software may be used and distributed according to the terms of
9 the GNU General Public License (GPL), incorporated herein by reference.
10 Drivers based on or derived from this code fall under the GPL and must
11 retain the authorship, copyright and license notice. This file is not
12 a complete program and may only be used when the entire operating
13 system is licensed under the GPL. License for under other terms may be
14 available. Contact the original author for details.
15
16 The original author may be reached as becker@scyld.com, or at
17 Scyld Computing Corporation
18 410 Severn Ave., Suite 210
19 Annapolis MD 21403
20
21 Support information and updates available at
22 http://www.scyld.com/network/netsemi.html
03a8c661 23 [link no longer provides useful info -jgarzik]
1da177e4
LT		 24
25
1da177e4
LT		 26 TODO:
27 * big endian support with CFG:BEM instead of cpu_to_le32
1da177e4
LT		 28*/
29
1da177e4
LT		 30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/string.h>
33#include <linux/timer.h>
34#include <linux/errno.h>
35#include <linux/ioport.h>
36#include <linux/slab.h>
37#include <linux/interrupt.h>
38#include <linux/pci.h>
39#include <linux/netdevice.h>
40#include <linux/etherdevice.h>
41#include <linux/skbuff.h>
42#include <linux/init.h>
43#include <linux/spinlock.h>
44#include <linux/ethtool.h>
45#include <linux/delay.h>
46#include <linux/rtnetlink.h>
47#include <linux/mii.h>
48#include <linux/crc32.h>
49#include <linux/bitops.h>
b27a16b7 50#include <linux/prefetch.h>
1da177e4
LT		 51#include <asm/processor.h> /* Processor type for cache alignment. */
52#include <asm/io.h>
53#include <asm/irq.h>
54#include <asm/uaccess.h>
55
56#define DRV_NAME "natsemi"
d5b20697
AG		 57#define DRV_VERSION "2.1"
58#define DRV_RELDATE "Sept 11, 2006"
1da177e4
LT		 59
60#define RX_OFFSET 2
61
62/* Updated to recommendations in pci-skeleton v2.03. */
63
64/* The user-configurable values.
65 These may be modified when a driver module is loaded.*/
66
67#define NATSEMI_DEF_MSG (NETIF_MSG_DRV | \
68 NETIF_MSG_LINK | \
69 NETIF_MSG_WOL | \
70 NETIF_MSG_RX_ERR | \
71 NETIF_MSG_TX_ERR)
72static int debug = -1;
73
1da177e4
LT		 74static int mtu;
75
76/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
77 This chip uses a 512 element hash table based on the Ethernet CRC. */
f71e1309 78static const int multicast_filter_limit = 100;
1da177e4
LT		 79
80/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
81 Setting to > 1518 effectively disables this feature. */
82static int rx_copybreak;
83
84/* Used to pass the media type, etc.
85 Both 'options[]' and 'full_duplex[]' should exist for driver
86 interoperability.
87 The media type is usually passed in 'options[]'.
88*/
89#define MAX_UNITS 8 /* More are supported, limit only on options */
90static int options[MAX_UNITS];
91static int full_duplex[MAX_UNITS];
92
93/* Operational parameters that are set at compile time. */
94
95/* Keep the ring sizes a power of two for compile efficiency.
96 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
97 Making the Tx ring too large decreases the effectiveness of channel
98 bonding and packet priority.
99 There are no ill effects from too-large receive rings. */
100#define TX_RING_SIZE 16
101#define TX_QUEUE_LEN 10 /* Limit ring entries actually used, min 4. */
102#define RX_RING_SIZE 32
103
104/* Operational parameters that usually are not changed. */
105/* Time in jiffies before concluding the transmitter is hung. */
106#define TX_TIMEOUT (2*HZ)
107
108#define NATSEMI_HW_TIMEOUT 400
109#define NATSEMI_TIMER_FREQ 3*HZ
110#define NATSEMI_PG0_NREGS 64
111#define NATSEMI_RFDR_NREGS 8
112#define NATSEMI_PG1_NREGS 4
113#define NATSEMI_NREGS (NATSEMI_PG0_NREGS + NATSEMI_RFDR_NREGS + \
114 NATSEMI_PG1_NREGS)
115#define NATSEMI_REGS_VER 1 /* v1 added RFDR registers */
116#define NATSEMI_REGS_SIZE (NATSEMI_NREGS * sizeof(u32))
1da177e4
LT		 117
118/* Buffer sizes:
119 * The nic writes 32-bit values, even if the upper bytes of
120 * a 32-bit value are beyond the end of the buffer.
121 */
122#define NATSEMI_HEADERS 22 /* 2*mac,type,vlan,crc */
123#define NATSEMI_PADDING 16 /* 2 bytes should be sufficient */
124#define NATSEMI_LONGPKT 1518 /* limit for normal packets */
125#define NATSEMI_RX_LIMIT 2046 /* maximum supported by hardware */
126
127/* These identify the driver base version and may not be removed. */
e19360f2 128static const char version[] __devinitdata =
1da177e4
LT		 129 KERN_INFO DRV_NAME " dp8381x driver, version "
130 DRV_VERSION ", " DRV_RELDATE "\n"
131 KERN_INFO " originally by Donald Becker <becker@scyld.com>\n"
132 KERN_INFO " http://www.scyld.com/network/natsemi.html\n"
133 KERN_INFO " 2.4.x kernel port by Jeff Garzik, Tjeerd Mulder\n";
134
135MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
136MODULE_DESCRIPTION("National Semiconductor DP8381x series PCI Ethernet driver");
137MODULE_LICENSE("GPL");
138
1da177e4
LT		 139module_param(mtu, int, 0);
140module_param(debug, int, 0);
141module_param(rx_copybreak, int, 0);
142module_param_array(options, int, NULL, 0);
143module_param_array(full_duplex, int, NULL, 0);
1da177e4
LT		 144MODULE_PARM_DESC(mtu, "DP8381x MTU (all boards)");
145MODULE_PARM_DESC(debug, "DP8381x default debug level");
6aa20a22 146MODULE_PARM_DESC(rx_copybreak,
1da177e4 147 "DP8381x copy breakpoint for copy-only-tiny-frames");
6aa20a22 148MODULE_PARM_DESC(options,
1da177e4
LT		 149 "DP8381x: Bits 0-3: media type, bit 17: full duplex");
150MODULE_PARM_DESC(full_duplex, "DP8381x full duplex setting(s) (1)");
151
152/*
153 Theory of Operation
154
155I. Board Compatibility
156
157This driver is designed for National Semiconductor DP83815 PCI Ethernet NIC.
158It also works with other chips in in the DP83810 series.
159
160II. Board-specific settings
161
162This driver requires the PCI interrupt line to be valid.
163It honors the EEPROM-set values.
164
165III. Driver operation
166
167IIIa. Ring buffers
168
169This driver uses two statically allocated fixed-size descriptor lists
170formed into rings by a branch from the final descriptor to the beginning of
171the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
172The NatSemi design uses a 'next descriptor' pointer that the driver forms
173into a list.
174
175IIIb/c. Transmit/Receive Structure
176
177This driver uses a zero-copy receive and transmit scheme.
178The driver allocates full frame size skbuffs for the Rx ring buffers at
179open() time and passes the skb->data field to the chip as receive data
180buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
181a fresh skbuff is allocated and the frame is copied to the new skbuff.
182When the incoming frame is larger, the skbuff is passed directly up the
183protocol stack. Buffers consumed this way are replaced by newly allocated
184skbuffs in a later phase of receives.
185
186The RX_COPYBREAK value is chosen to trade-off the memory wasted by
187using a full-sized skbuff for small frames vs. the copying costs of larger
188frames. New boards are typically used in generously configured machines
189and the underfilled buffers have negligible impact compared to the benefit of
190a single allocation size, so the default value of zero results in never
191copying packets. When copying is done, the cost is usually mitigated by using
192a combined copy/checksum routine. Copying also preloads the cache, which is
193most useful with small frames.
194
195A subtle aspect of the operation is that unaligned buffers are not permitted
196by the hardware. Thus the IP header at offset 14 in an ethernet frame isn't
197longword aligned for further processing. On copies frames are put into the
198skbuff at an offset of "+2", 16-byte aligning the IP header.
199
200IIId. Synchronization
201
202Most operations are synchronized on the np->lock irq spinlock, except the
203performance critical codepaths:
204
205The rx process only runs in the interrupt handler. Access from outside
206the interrupt handler is only permitted after disable_irq().
207
932ff279 208The rx process usually runs under the netif_tx_lock. If np->intr_tx_reap
1da177e4
LT		 209is set, then access is permitted under spin_lock_irq(&np->lock).
210
211Thus configuration functions that want to access everything must call
212 disable_irq(dev->irq);
932ff279 213 netif_tx_lock_bh(dev);
1da177e4
LT		 214 spin_lock_irq(&np->lock);
215
216IV. Notes
217
218NatSemi PCI network controllers are very uncommon.
219
220IVb. References
221
222http://www.scyld.com/expert/100mbps.html
223http://www.scyld.com/expert/NWay.html
224Datasheet is available from:
225http://www.national.com/pf/DP/DP83815.html
226
227IVc. Errata
228
229None characterised.
230*/
231
232
233
1da177e4
LT		 234/*
235 * Support for fibre connections on Am79C874:
236 * This phy needs a special setup when connected to a fibre cable.
237 * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/22235.pdf
238 */
239#define PHYID_AM79C874 0x0022561b
240
a2b524b2
JG		 241enum {
242 MII_MCTRL = 0x15, /* mode control register */
243 MII_FX_SEL = 0x0001, /* 100BASE-FX (fiber) */
244 MII_EN_SCRM = 0x0004, /* enable scrambler (tp) */
245};
1da177e4 246
6aab4447
MB		 247enum {
248 NATSEMI_FLAG_IGNORE_PHY = 0x1,
249};
6aa20a22 250
1da177e4 251/* array of board data directly indexed by pci_tbl[x].driver_data */
f71e1309 252static const struct {
1da177e4
LT		 253 const char *name;
254 unsigned long flags;
a2b524b2 255 unsigned int eeprom_size;
1da177e4 256} natsemi_pci_info[] __devinitdata = {
6aab4447 257 { "Aculab E1/T1 PMXc cPCI carrier card", NATSEMI_FLAG_IGNORE_PHY, 128 },
a2b524b2 258 { "NatSemi DP8381[56]", 0, 24 },
1da177e4
LT		 259};
260
a2b524b2 261static const struct pci_device_id natsemi_pci_tbl[] __devinitdata = {
6aab4447 262 { PCI_VENDOR_ID_NS, 0x0020, 0x12d9, 0x000c, 0, 0, 0 },
36c843d5 263 { PCI_VENDOR_ID_NS, 0x0020, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
a2b524b2 264 { } /* terminate list */
1da177e4
LT		 265};
266MODULE_DEVICE_TABLE(pci, natsemi_pci_tbl);
267
268/* Offsets to the device registers.
269 Unlike software-only systems, device drivers interact with complex hardware.
270 It's not useful to define symbolic names for every register bit in the
271 device.
272*/
273enum register_offsets {
274 ChipCmd = 0x00,
275 ChipConfig = 0x04,
276 EECtrl = 0x08,
277 PCIBusCfg = 0x0C,
278 IntrStatus = 0x10,
279 IntrMask = 0x14,
280 IntrEnable = 0x18,
281 IntrHoldoff = 0x1C, /* DP83816 only */
282 TxRingPtr = 0x20,
283 TxConfig = 0x24,
284 RxRingPtr = 0x30,
285 RxConfig = 0x34,
286 ClkRun = 0x3C,
287 WOLCmd = 0x40,
288 PauseCmd = 0x44,
289 RxFilterAddr = 0x48,
290 RxFilterData = 0x4C,
291 BootRomAddr = 0x50,
292 BootRomData = 0x54,
293 SiliconRev = 0x58,
294 StatsCtrl = 0x5C,
295 StatsData = 0x60,
296 RxPktErrs = 0x60,
297 RxMissed = 0x68,
298 RxCRCErrs = 0x64,
299 BasicControl = 0x80,
300 BasicStatus = 0x84,
301 AnegAdv = 0x90,
302 AnegPeer = 0x94,
303 PhyStatus = 0xC0,
304 MIntrCtrl = 0xC4,
305 MIntrStatus = 0xC8,
306 PhyCtrl = 0xE4,
307
308 /* These are from the spec, around page 78... on a separate table.
309 * The meaning of these registers depend on the value of PGSEL. */
310 PGSEL = 0xCC,
311 PMDCSR = 0xE4,
312 TSTDAT = 0xFC,
313 DSPCFG = 0xF4,
314 SDCFG = 0xF8
315};
316/* the values for the 'magic' registers above (PGSEL=1) */
317#define PMDCSR_VAL 0x189c /* enable preferred adaptation circuitry */
318#define TSTDAT_VAL 0x0
319#define DSPCFG_VAL 0x5040
320#define SDCFG_VAL 0x008c /* set voltage thresholds for Signal Detect */
321#define DSPCFG_LOCK 0x20 /* coefficient lock bit in DSPCFG */
322#define DSPCFG_COEF 0x1000 /* see coefficient (in TSTDAT) bit in DSPCFG */
323#define TSTDAT_FIXED 0xe8 /* magic number for bad coefficients */
324
325/* misc PCI space registers */
326enum pci_register_offsets {
327 PCIPM = 0x44,
328};
329
330enum ChipCmd_bits {
331 ChipReset = 0x100,
332 RxReset = 0x20,
333 TxReset = 0x10,
334 RxOff = 0x08,
335 RxOn = 0x04,
336 TxOff = 0x02,
337 TxOn = 0x01,
338};
339
340enum ChipConfig_bits {
341 CfgPhyDis = 0x200,
342 CfgPhyRst = 0x400,
343 CfgExtPhy = 0x1000,
344 CfgAnegEnable = 0x2000,
345 CfgAneg100 = 0x4000,
346 CfgAnegFull = 0x8000,
347 CfgAnegDone = 0x8000000,
348 CfgFullDuplex = 0x20000000,
349 CfgSpeed100 = 0x40000000,
350 CfgLink = 0x80000000,
351};
352
353enum EECtrl_bits {
354 EE_ShiftClk = 0x04,
355 EE_DataIn = 0x01,
356 EE_ChipSelect = 0x08,
357 EE_DataOut = 0x02,
358 MII_Data = 0x10,
359 MII_Write = 0x20,
360 MII_ShiftClk = 0x40,
361};
362
363enum PCIBusCfg_bits {
364 EepromReload = 0x4,
365};
366
367/* Bits in the interrupt status/mask registers. */
368enum IntrStatus_bits {
369 IntrRxDone = 0x0001,
370 IntrRxIntr = 0x0002,
371 IntrRxErr = 0x0004,
372 IntrRxEarly = 0x0008,
373 IntrRxIdle = 0x0010,
374 IntrRxOverrun = 0x0020,
375 IntrTxDone = 0x0040,
376 IntrTxIntr = 0x0080,
377 IntrTxErr = 0x0100,
378 IntrTxIdle = 0x0200,
379 IntrTxUnderrun = 0x0400,
380 StatsMax = 0x0800,
381 SWInt = 0x1000,
382 WOLPkt = 0x2000,
383 LinkChange = 0x4000,
384 IntrHighBits = 0x8000,
385 RxStatusFIFOOver = 0x10000,
386 IntrPCIErr = 0xf00000,
387 RxResetDone = 0x1000000,
388 TxResetDone = 0x2000000,
389 IntrAbnormalSummary = 0xCD20,
390};
391
392/*
393 * Default Interrupts:
394 * Rx OK, Rx Packet Error, Rx Overrun,
395 * Tx OK, Tx Packet Error, Tx Underrun,
396 * MIB Service, Phy Interrupt, High Bits,
397 * Rx Status FIFO overrun,
398 * Received Target Abort, Received Master Abort,
399 * Signalled System Error, Received Parity Error
400 */
401#define DEFAULT_INTR 0x00f1cd65
402
403enum TxConfig_bits {
404 TxDrthMask = 0x3f,
405 TxFlthMask = 0x3f00,
406 TxMxdmaMask = 0x700000,
407 TxMxdma_512 = 0x0,
408 TxMxdma_4 = 0x100000,
409 TxMxdma_8 = 0x200000,
410 TxMxdma_16 = 0x300000,
411 TxMxdma_32 = 0x400000,
412 TxMxdma_64 = 0x500000,
413 TxMxdma_128 = 0x600000,
414 TxMxdma_256 = 0x700000,
415 TxCollRetry = 0x800000,
416 TxAutoPad = 0x10000000,
417 TxMacLoop = 0x20000000,
418 TxHeartIgn = 0x40000000,
419 TxCarrierIgn = 0x80000000
420};
421
6aa20a22 422/*
1da177e4
LT		 423 * Tx Configuration:
424 * - 256 byte DMA burst length
425 * - fill threshold 512 bytes (i.e. restart DMA when 512 bytes are free)
426 * - 64 bytes initial drain threshold (i.e. begin actual transmission
427 * when 64 byte are in the fifo)
428 * - on tx underruns, increase drain threshold by 64.
429 * - at most use a drain threshold of 1472 bytes: The sum of the fill
430 * threshold and the drain threshold must be less than 2016 bytes.
431 *
432 */
433#define TX_FLTH_VAL ((512/32) << 8)
434#define TX_DRTH_VAL_START (64/32)
435#define TX_DRTH_VAL_INC 2
436#define TX_DRTH_VAL_LIMIT (1472/32)
437
438enum RxConfig_bits {
439 RxDrthMask = 0x3e,
440 RxMxdmaMask = 0x700000,
441 RxMxdma_512 = 0x0,
442 RxMxdma_4 = 0x100000,
443 RxMxdma_8 = 0x200000,
444 RxMxdma_16 = 0x300000,
445 RxMxdma_32 = 0x400000,
446 RxMxdma_64 = 0x500000,
447 RxMxdma_128 = 0x600000,
448 RxMxdma_256 = 0x700000,
449 RxAcceptLong = 0x8000000,
450 RxAcceptTx = 0x10000000,
451 RxAcceptRunt = 0x40000000,
452 RxAcceptErr = 0x80000000
453};
454#define RX_DRTH_VAL (128/8)
455
456enum ClkRun_bits {
457 PMEEnable = 0x100,
458 PMEStatus = 0x8000,
459};
460
461enum WolCmd_bits {
462 WakePhy = 0x1,
463 WakeUnicast = 0x2,
464 WakeMulticast = 0x4,
465 WakeBroadcast = 0x8,
466 WakeArp = 0x10,
467 WakePMatch0 = 0x20,
468 WakePMatch1 = 0x40,
469 WakePMatch2 = 0x80,
470 WakePMatch3 = 0x100,
471 WakeMagic = 0x200,
472 WakeMagicSecure = 0x400,
473 SecureHack = 0x100000,
474 WokePhy = 0x400000,
475 WokeUnicast = 0x800000,
476 WokeMulticast = 0x1000000,
477 WokeBroadcast = 0x2000000,
478 WokeArp = 0x4000000,
479 WokePMatch0 = 0x8000000,
480 WokePMatch1 = 0x10000000,
481 WokePMatch2 = 0x20000000,
482 WokePMatch3 = 0x40000000,
483 WokeMagic = 0x80000000,
484 WakeOptsSummary = 0x7ff
485};
486
487enum RxFilterAddr_bits {
488 RFCRAddressMask = 0x3ff,
489 AcceptMulticast = 0x00200000,
490 AcceptMyPhys = 0x08000000,
491 AcceptAllPhys = 0x10000000,
492 AcceptAllMulticast = 0x20000000,
493 AcceptBroadcast = 0x40000000,
494 RxFilterEnable = 0x80000000
495};
496
497enum StatsCtrl_bits {
498 StatsWarn = 0x1,
499 StatsFreeze = 0x2,
500 StatsClear = 0x4,
501 StatsStrobe = 0x8,
502};
503
504enum MIntrCtrl_bits {
505 MICRIntEn = 0x2,
506};
507
508enum PhyCtrl_bits {
509 PhyAddrMask = 0x1f,
510};
511
512#define PHY_ADDR_NONE 32
513#define PHY_ADDR_INTERNAL 1
514
515/* values we might find in the silicon revision register */
516#define SRR_DP83815_C 0x0302
517#define SRR_DP83815_D 0x0403
518#define SRR_DP83816_A4 0x0504
519#define SRR_DP83816_A5 0x0505
520
521/* The Rx and Tx buffer descriptors. */
522/* Note that using only 32 bit fields simplifies conversion to big-endian
523 architectures. */
524struct netdev_desc {
525 u32 next_desc;
526 s32 cmd_status;
527 u32 addr;
528 u32 software_use;
529};
530
531/* Bits in network_desc.status */
532enum desc_status_bits {
533 DescOwn=0x80000000, DescMore=0x40000000, DescIntr=0x20000000,
534 DescNoCRC=0x10000000, DescPktOK=0x08000000,
535 DescSizeMask=0xfff,
536
537 DescTxAbort=0x04000000, DescTxFIFO=0x02000000,
538 DescTxCarrier=0x01000000, DescTxDefer=0x00800000,
539 DescTxExcDefer=0x00400000, DescTxOOWCol=0x00200000,
540 DescTxExcColl=0x00100000, DescTxCollCount=0x000f0000,
541
542 DescRxAbort=0x04000000, DescRxOver=0x02000000,
543 DescRxDest=0x01800000, DescRxLong=0x00400000,
544 DescRxRunt=0x00200000, DescRxInvalid=0x00100000,
545 DescRxCRC=0x00080000, DescRxAlign=0x00040000,
546 DescRxLoop=0x00020000, DesRxColl=0x00010000,
547};
548
549struct netdev_private {
550 /* Descriptor rings first for alignment */
551 dma_addr_t ring_dma;
552 struct netdev_desc *rx_ring;
553 struct netdev_desc *tx_ring;
554 /* The addresses of receive-in-place skbuffs */
555 struct sk_buff *rx_skbuff[RX_RING_SIZE];
556 dma_addr_t rx_dma[RX_RING_SIZE];
557 /* address of a sent-in-place packet/buffer, for later free() */
558 struct sk_buff *tx_skbuff[TX_RING_SIZE];
559 dma_addr_t tx_dma[TX_RING_SIZE];
560 struct net_device_stats stats;
561 /* Media monitoring timer */
562 struct timer_list timer;
563 /* Frequently used values: keep some adjacent for cache effect */
564 struct pci_dev *pci_dev;
565 struct netdev_desc *rx_head_desc;
566 /* Producer/consumer ring indices */
567 unsigned int cur_rx, dirty_rx;
568 unsigned int cur_tx, dirty_tx;
569 /* Based on MTU+slack. */
570 unsigned int rx_buf_sz;
571 int oom;
b27a16b7
MB		 572 /* Interrupt status */
573 u32 intr_status;
1da177e4
LT		 574 /* Do not touch the nic registers */
575 int hands_off;
68c90166
MB		 576 /* Don't pay attention to the reported link state. */
577 int ignore_phy;
1da177e4
LT		 578 /* external phy that is used: only valid if dev->if_port != PORT_TP */
579 int mii;
580 int phy_addr_external;
581 unsigned int full_duplex;
582 /* Rx filter */
583 u32 cur_rx_mode;
584 u32 rx_filter[16];
585 /* FIFO and PCI burst thresholds */
586 u32 tx_config, rx_config;
587 /* original contents of ClkRun register */
588 u32 SavedClkRun;
589 /* silicon revision */
590 u32 srr;
591 /* expected DSPCFG value */
592 u16 dspcfg;
593 /* parms saved in ethtool format */
594 u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */
595 u8 duplex; /* Duplex, half or full */
596 u8 autoneg; /* Autonegotiation enabled */
597 /* MII transceiver section */
598 u16 advertising;
599 unsigned int iosize;
600 spinlock_t lock;
601 u32 msg_enable;
a8b4cf42
MB		 602 /* EEPROM data */
603 int eeprom_size;
1da177e4
LT		 604};
605
606static void move_int_phy(struct net_device *dev, int addr);
607static int eeprom_read(void __iomem *ioaddr, int location);
608static int mdio_read(struct net_device *dev, int reg);
609static void mdio_write(struct net_device *dev, int reg, u16 data);
610static void init_phy_fixup(struct net_device *dev);
611static int miiport_read(struct net_device *dev, int phy_id, int reg);
612static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data);
613static int find_mii(struct net_device *dev);
614static void natsemi_reset(struct net_device *dev);
615static void natsemi_reload_eeprom(struct net_device *dev);
616static void natsemi_stop_rxtx(struct net_device *dev);
617static int netdev_open(struct net_device *dev);
618static void do_cable_magic(struct net_device *dev);
619static void undo_cable_magic(struct net_device *dev);
620static void check_link(struct net_device *dev);
621static void netdev_timer(unsigned long data);
622static void dump_ring(struct net_device *dev);
623static void tx_timeout(struct net_device *dev);
624static int alloc_ring(struct net_device *dev);
625static void refill_rx(struct net_device *dev);
626static void init_ring(struct net_device *dev);
627static void drain_tx(struct net_device *dev);
628static void drain_ring(struct net_device *dev);
629static void free_ring(struct net_device *dev);
630static void reinit_ring(struct net_device *dev);
631static void init_registers(struct net_device *dev);
632static int start_tx(struct sk_buff *skb, struct net_device *dev);
7d12e780 633static irqreturn_t intr_handler(int irq, void *dev_instance);
1da177e4 634static void netdev_error(struct net_device *dev, int intr_status);
b27a16b7
MB		 635static int natsemi_poll(struct net_device *dev, int *budget);
636static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do);
1da177e4
LT		 637static void netdev_tx_done(struct net_device *dev);
638static int natsemi_change_mtu(struct net_device *dev, int new_mtu);
639#ifdef CONFIG_NET_POLL_CONTROLLER
640static void natsemi_poll_controller(struct net_device *dev);
641#endif
642static void __set_rx_mode(struct net_device *dev);
643static void set_rx_mode(struct net_device *dev);
644static void __get_stats(struct net_device *dev);
645static struct net_device_stats *get_stats(struct net_device *dev);
646static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
647static int netdev_set_wol(struct net_device *dev, u32 newval);
648static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur);
649static int netdev_set_sopass(struct net_device *dev, u8 *newval);
650static int netdev_get_sopass(struct net_device *dev, u8 *data);
651static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
652static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
653static void enable_wol_mode(struct net_device *dev, int enable_intr);
654static int netdev_close(struct net_device *dev);
655static int netdev_get_regs(struct net_device *dev, u8 *buf);
656static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
7282d491 657static const struct ethtool_ops ethtool_ops;
1da177e4
LT		 658
659static inline void __iomem *ns_ioaddr(struct net_device *dev)
660{
661 return (void __iomem *) dev->base_addr;
662}
663
b27a16b7
MB		 664static inline void natsemi_irq_enable(struct net_device *dev)
665{
666 writel(1, ns_ioaddr(dev) + IntrEnable);
667 readl(ns_ioaddr(dev) + IntrEnable);
668}
669
670static inline void natsemi_irq_disable(struct net_device *dev)
671{
672 writel(0, ns_ioaddr(dev) + IntrEnable);
673 readl(ns_ioaddr(dev) + IntrEnable);
674}
675
1da177e4
LT		 676static void move_int_phy(struct net_device *dev, int addr)
677{
678 struct netdev_private *np = netdev_priv(dev);
679 void __iomem *ioaddr = ns_ioaddr(dev);
680 int target = 31;
681
6aa20a22 682 /*
1da177e4
LT		 683 * The internal phy is visible on the external mii bus. Therefore we must
684 * move it away before we can send commands to an external phy.
685 * There are two addresses we must avoid:
686 * - the address on the external phy that is used for transmission.
687 * - the address that we want to access. User space can access phys
688 * on the mii bus with SIOCGMIIREG/SIOCSMIIREG, independant from the
689 * phy that is used for transmission.
690 */
691
692 if (target == addr)
693 target--;
694 if (target == np->phy_addr_external)
695 target--;
696 writew(target, ioaddr + PhyCtrl);
697 readw(ioaddr + PhyCtrl);
698 udelay(1);
699}
700
5a40f09b
JG		 701static void __devinit natsemi_init_media (struct net_device *dev)
702{
703 struct netdev_private *np = netdev_priv(dev);
704 u32 tmp;
705
68c90166
MB		 706 if (np->ignore_phy)
707 netif_carrier_on(dev);
708 else
709 netif_carrier_off(dev);
5a40f09b
JG		 710
711 /* get the initial settings from hardware */
712 tmp = mdio_read(dev, MII_BMCR);
713 np->speed = (tmp & BMCR_SPEED100)? SPEED_100 : SPEED_10;
714 np->duplex = (tmp & BMCR_FULLDPLX)? DUPLEX_FULL : DUPLEX_HALF;
715 np->autoneg = (tmp & BMCR_ANENABLE)? AUTONEG_ENABLE: AUTONEG_DISABLE;
716 np->advertising= mdio_read(dev, MII_ADVERTISE);
717
718 if ((np->advertising & ADVERTISE_ALL) != ADVERTISE_ALL
719 && netif_msg_probe(np)) {
720 printk(KERN_INFO "natsemi %s: Transceiver default autonegotiation %s "
721 "10%s %s duplex.\n",
722 pci_name(np->pci_dev),
723 (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE)?
724 "enabled, advertise" : "disabled, force",
725 (np->advertising &
726 (ADVERTISE_100FULL|ADVERTISE_100HALF))?
727 "0" : "",
728 (np->advertising &
729 (ADVERTISE_100FULL|ADVERTISE_10FULL))?
730 "full" : "half");
731 }
732 if (netif_msg_probe(np))
733 printk(KERN_INFO
734 "natsemi %s: Transceiver status %#04x advertising %#04x.\n",
735 pci_name(np->pci_dev), mdio_read(dev, MII_BMSR),
736 np->advertising);
737
738}
739
1da177e4
LT		 740static int __devinit natsemi_probe1 (struct pci_dev *pdev,
741 const struct pci_device_id *ent)
742{
743 struct net_device *dev;
744 struct netdev_private *np;
745 int i, option, irq, chip_idx = ent->driver_data;
746 static int find_cnt = -1;
747 unsigned long iostart, iosize;
748 void __iomem *ioaddr;
749 const int pcibar = 1; /* PCI base address register */
750 int prev_eedata;
751 u32 tmp;
752
753/* when built into the kernel, we only print version if device is found */
754#ifndef MODULE
755 static int printed_version;
756 if (!printed_version++)
757 printk(version);
758#endif
759
760 i = pci_enable_device(pdev);
761 if (i) return i;
762
763 /* natsemi has a non-standard PM control register
764 * in PCI config space. Some boards apparently need
765 * to be brought to D0 in this manner.
766 */
767 pci_read_config_dword(pdev, PCIPM, &tmp);
768 if (tmp & PCI_PM_CTRL_STATE_MASK) {
769 /* D0 state, disable PME assertion */
770 u32 newtmp = tmp & ~PCI_PM_CTRL_STATE_MASK;
771 pci_write_config_dword(pdev, PCIPM, newtmp);
772 }
773
774 find_cnt++;
775 iostart = pci_resource_start(pdev, pcibar);
776 iosize = pci_resource_len(pdev, pcibar);
777 irq = pdev->irq;
778
a2b524b2 779 pci_set_master(pdev);
1da177e4
LT		 780
781 dev = alloc_etherdev(sizeof (struct netdev_private));
782 if (!dev)
783 return -ENOMEM;
784 SET_MODULE_OWNER(dev);
785 SET_NETDEV_DEV(dev, &pdev->dev);
786
787 i = pci_request_regions(pdev, DRV_NAME);
788 if (i)
789 goto err_pci_request_regions;
790
791 ioaddr = ioremap(iostart, iosize);
792 if (!ioaddr) {
793 i = -ENOMEM;
794 goto err_ioremap;
795 }
796
797 /* Work around the dropped serial bit. */
798 prev_eedata = eeprom_read(ioaddr, 6);
799 for (i = 0; i < 3; i++) {
800 int eedata = eeprom_read(ioaddr, i + 7);
801 dev->dev_addr[i*2] = (eedata << 1) + (prev_eedata >> 15);
802 dev->dev_addr[i*2+1] = eedata >> 7;
803 prev_eedata = eedata;
804 }
805
806 dev->base_addr = (unsigned long __force) ioaddr;
807 dev->irq = irq;
808
809 np = netdev_priv(dev);
810
811 np->pci_dev = pdev;
812 pci_set_drvdata(pdev, dev);
813 np->iosize = iosize;
814 spin_lock_init(&np->lock);
815 np->msg_enable = (debug >= 0) ? (1<<debug)-1 : NATSEMI_DEF_MSG;
816 np->hands_off = 0;
b27a16b7 817 np->intr_status = 0;
a2b524b2 818 np->eeprom_size = natsemi_pci_info[chip_idx].eeprom_size;
6aab4447
MB		 819 if (natsemi_pci_info[chip_idx].flags & NATSEMI_FLAG_IGNORE_PHY)
820 np->ignore_phy = 1;
821 else
822 np->ignore_phy = 0;
1da177e4
LT		 823
824 /* Initial port:
68c90166 825 * - If configured to ignore the PHY set up for external.
1da177e4
LT		 826 * - If the nic was configured to use an external phy and if find_mii
827 * finds a phy: use external port, first phy that replies.
828 * - Otherwise: internal port.
829 * Note that the phy address for the internal phy doesn't matter:
830 * The address would be used to access a phy over the mii bus, but
831 * the internal phy is accessed through mapped registers.
832 */
68c90166 833 if (np->ignore_phy || readl(ioaddr + ChipConfig) & CfgExtPhy)
1da177e4
LT		 834 dev->if_port = PORT_MII;
835 else
836 dev->if_port = PORT_TP;
837 /* Reset the chip to erase previous misconfiguration. */
838 natsemi_reload_eeprom(dev);
839 natsemi_reset(dev);
840
841 if (dev->if_port != PORT_TP) {
842 np->phy_addr_external = find_mii(dev);
68c90166
MB		 843 /* If we're ignoring the PHY it doesn't matter if we can't
844 * find one. */
845 if (!np->ignore_phy && np->phy_addr_external == PHY_ADDR_NONE) {
1da177e4
LT		 846 dev->if_port = PORT_TP;
847 np->phy_addr_external = PHY_ADDR_INTERNAL;
848 }
849 } else {
850 np->phy_addr_external = PHY_ADDR_INTERNAL;
851 }
852
853 option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
854 if (dev->mem_start)
855 option = dev->mem_start;
856
857 /* The lower four bits are the media type. */
858 if (option) {
859 if (option & 0x200)
860 np->full_duplex = 1;
861 if (option & 15)
862 printk(KERN_INFO
863 "natsemi %s: ignoring user supplied media type %d",
864 pci_name(np->pci_dev), option & 15);
865 }
866 if (find_cnt < MAX_UNITS && full_duplex[find_cnt])
867 np->full_duplex = 1;
868
869 /* The chip-specific entries in the device structure. */
870 dev->open = &netdev_open;
871 dev->hard_start_xmit = &start_tx;
872 dev->stop = &netdev_close;
873 dev->get_stats = &get_stats;
874 dev->set_multicast_list = &set_rx_mode;
875 dev->change_mtu = &natsemi_change_mtu;
876 dev->do_ioctl = &netdev_ioctl;
877 dev->tx_timeout = &tx_timeout;
878 dev->watchdog_timeo = TX_TIMEOUT;
b27a16b7
MB		 879 dev->poll = natsemi_poll;
880 dev->weight = 64;
881
1da177e4
LT		 882#ifdef CONFIG_NET_POLL_CONTROLLER
883 dev->poll_controller = &natsemi_poll_controller;
884#endif
885 SET_ETHTOOL_OPS(dev, &ethtool_ops);
886
887 if (mtu)
888 dev->mtu = mtu;
889
5a40f09b 890 natsemi_init_media(dev);
1da177e4
LT		 891
892 /* save the silicon revision for later querying */
893 np->srr = readl(ioaddr + SiliconRev);
894 if (netif_msg_hw(np))
895 printk(KERN_INFO "natsemi %s: silicon revision %#04x.\n",
896 pci_name(np->pci_dev), np->srr);
897
898 i = register_netdev(dev);
899 if (i)
900 goto err_register_netdev;
901
902 if (netif_msg_drv(np)) {
903 printk(KERN_INFO "natsemi %s: %s at %#08lx (%s), ",
904 dev->name, natsemi_pci_info[chip_idx].name, iostart,
905 pci_name(np->pci_dev));
906 for (i = 0; i < ETH_ALEN-1; i++)
907 printk("%02x:", dev->dev_addr[i]);
908 printk("%02x, IRQ %d", dev->dev_addr[i], irq);
909 if (dev->if_port == PORT_TP)
910 printk(", port TP.\n");
68c90166
MB		 911 else if (np->ignore_phy)
912 printk(", port MII, ignoring PHY\n");
1da177e4
LT		 913 else
914 printk(", port MII, phy ad %d.\n", np->phy_addr_external);
915 }
916 return 0;
917
918 err_register_netdev:
919 iounmap(ioaddr);
920
921 err_ioremap:
922 pci_release_regions(pdev);
923 pci_set_drvdata(pdev, NULL);
924
925 err_pci_request_regions:
926 free_netdev(dev);
927 return i;
928}
929
930
931/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces.
932 The EEPROM code is for the common 93c06/46 EEPROMs with 6 bit addresses. */
933
934/* Delay between EEPROM clock transitions.
935 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
936 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
937 made udelay() unreliable.
938 The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is
939 depricated.
940*/
941#define eeprom_delay(ee_addr) readl(ee_addr)
942
943#define EE_Write0 (EE_ChipSelect)
944#define EE_Write1 (EE_ChipSelect | EE_DataIn)
945
946/* The EEPROM commands include the alway-set leading bit. */
947enum EEPROM_Cmds {
948 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
949};
950
951static int eeprom_read(void __iomem *addr, int location)
952{
953 int i;
954 int retval = 0;
955 void __iomem *ee_addr = addr + EECtrl;
956 int read_cmd = location | EE_ReadCmd;
957
958 writel(EE_Write0, ee_addr);
959
960 /* Shift the read command bits out. */
961 for (i = 10; i >= 0; i--) {
962 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
963 writel(dataval, ee_addr);
964 eeprom_delay(ee_addr);
965 writel(dataval | EE_ShiftClk, ee_addr);
966 eeprom_delay(ee_addr);
967 }
968 writel(EE_ChipSelect, ee_addr);
969 eeprom_delay(ee_addr);
970
971 for (i = 0; i < 16; i++) {
972 writel(EE_ChipSelect | EE_ShiftClk, ee_addr);
973 eeprom_delay(ee_addr);
974 retval |= (readl(ee_addr) & EE_DataOut) ? 1 << i : 0;
975 writel(EE_ChipSelect, ee_addr);
976 eeprom_delay(ee_addr);
977 }
978
979 /* Terminate the EEPROM access. */
980 writel(EE_Write0, ee_addr);
981 writel(0, ee_addr);
982 return retval;
983}
984
985/* MII transceiver control section.
986 * The 83815 series has an internal transceiver, and we present the
987 * internal management registers as if they were MII connected.
988 * External Phy registers are referenced through the MII interface.
989 */
990
991/* clock transitions >= 20ns (25MHz)
992 * One readl should be good to PCI @ 100MHz
993 */
994#define mii_delay(ioaddr) readl(ioaddr + EECtrl)
995
996static int mii_getbit (struct net_device *dev)
997{
998 int data;
999 void __iomem *ioaddr = ns_ioaddr(dev);
1000
1001 writel(MII_ShiftClk, ioaddr + EECtrl);
1002 data = readl(ioaddr + EECtrl);
1003 writel(0, ioaddr + EECtrl);
1004 mii_delay(ioaddr);
1005 return (data & MII_Data)? 1 : 0;
1006}
1007
1008static void mii_send_bits (struct net_device *dev, u32 data, int len)
1009{
1010 u32 i;
1011 void __iomem *ioaddr = ns_ioaddr(dev);
1012
1013 for (i = (1 << (len-1)); i; i >>= 1)
1014 {
1015 u32 mdio_val = MII_Write | ((data & i)? MII_Data : 0);
1016 writel(mdio_val, ioaddr + EECtrl);
1017 mii_delay(ioaddr);
1018 writel(mdio_val | MII_ShiftClk, ioaddr + EECtrl);
1019 mii_delay(ioaddr);
1020 }
1021 writel(0, ioaddr + EECtrl);
1022 mii_delay(ioaddr);
1023}
1024
1025static int miiport_read(struct net_device *dev, int phy_id, int reg)
1026{
1027 u32 cmd;
1028 int i;
1029 u32 retval = 0;
1030
1031 /* Ensure sync */
1032 mii_send_bits (dev, 0xffffffff, 32);
1033 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1034 /* ST,OP = 0110'b for read operation */
1035 cmd = (0x06 << 10) | (phy_id << 5) | reg;
1036 mii_send_bits (dev, cmd, 14);
1037 /* Turnaround */
1038 if (mii_getbit (dev))
1039 return 0;
1040 /* Read data */
1041 for (i = 0; i < 16; i++) {
1042 retval <<= 1;
1043 retval |= mii_getbit (dev);
1044 }
1045 /* End cycle */
1046 mii_getbit (dev);
1047 return retval;
1048}
1049
1050static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data)
1051{
1052 u32 cmd;
1053
1054 /* Ensure sync */
1055 mii_send_bits (dev, 0xffffffff, 32);
1056 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1057 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1058 cmd = (0x5002 << 16) | (phy_id << 23) | (reg << 18) | data;
1059 mii_send_bits (dev, cmd, 32);
1060 /* End cycle */
1061 mii_getbit (dev);
1062}
1063
1064static int mdio_read(struct net_device *dev, int reg)
1065{
1066 struct netdev_private *np = netdev_priv(dev);
1067 void __iomem *ioaddr = ns_ioaddr(dev);
1068
1069 /* The 83815 series has two ports:
1070 * - an internal transceiver
1071 * - an external mii bus
1072 */
1073 if (dev->if_port == PORT_TP)
1074 return readw(ioaddr+BasicControl+(reg<<2));
1075 else
1076 return miiport_read(dev, np->phy_addr_external, reg);
1077}
1078
1079static void mdio_write(struct net_device *dev, int reg, u16 data)
1080{
1081 struct netdev_private *np = netdev_priv(dev);
1082 void __iomem *ioaddr = ns_ioaddr(dev);
1083
1084 /* The 83815 series has an internal transceiver; handle separately */
1085 if (dev->if_port == PORT_TP)
1086 writew(data, ioaddr+BasicControl+(reg<<2));
1087 else
1088 miiport_write(dev, np->phy_addr_external, reg, data);
1089}
1090
1091static void init_phy_fixup(struct net_device *dev)
1092{
1093 struct netdev_private *np = netdev_priv(dev);
1094 void __iomem *ioaddr = ns_ioaddr(dev);
1095 int i;
1096 u32 cfg;
1097 u16 tmp;
1098
1099 /* restore stuff lost when power was out */
1100 tmp = mdio_read(dev, MII_BMCR);
1101 if (np->autoneg == AUTONEG_ENABLE) {
1102 /* renegotiate if something changed */
1103 if ((tmp & BMCR_ANENABLE) == 0
1104 || np->advertising != mdio_read(dev, MII_ADVERTISE))
1105 {
1106 /* turn on autonegotiation and force negotiation */
1107 tmp |= (BMCR_ANENABLE | BMCR_ANRESTART);
1108 mdio_write(dev, MII_ADVERTISE, np->advertising);
1109 }
1110 } else {
1111 /* turn off auto negotiation, set speed and duplexity */
1112 tmp &= ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX);
1113 if (np->speed == SPEED_100)
1114 tmp |= BMCR_SPEED100;
1115 if (np->duplex == DUPLEX_FULL)
1116 tmp |= BMCR_FULLDPLX;
6aa20a22 1117 /*
1da177e4
LT		 1118 * Note: there is no good way to inform the link partner
1119 * that our capabilities changed. The user has to unplug
1120 * and replug the network cable after some changes, e.g.
1121 * after switching from 10HD, autoneg off to 100 HD,
1122 * autoneg off.
1123 */
1124 }
1125 mdio_write(dev, MII_BMCR, tmp);
1126 readl(ioaddr + ChipConfig);
1127 udelay(1);
1128
1129 /* find out what phy this is */
1130 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1131 + mdio_read(dev, MII_PHYSID2);
1132
1133 /* handle external phys here */
1134 switch (np->mii) {
1135 case PHYID_AM79C874:
1136 /* phy specific configuration for fibre/tp operation */
1137 tmp = mdio_read(dev, MII_MCTRL);
1138 tmp &= ~(MII_FX_SEL | MII_EN_SCRM);
1139 if (dev->if_port == PORT_FIBRE)
1140 tmp |= MII_FX_SEL;
1141 else
1142 tmp |= MII_EN_SCRM;
1143 mdio_write(dev, MII_MCTRL, tmp);
1144 break;
1145 default:
1146 break;
1147 }
1148 cfg = readl(ioaddr + ChipConfig);
1149 if (cfg & CfgExtPhy)
1150 return;
1151
1152 /* On page 78 of the spec, they recommend some settings for "optimum
1153 performance" to be done in sequence. These settings optimize some
1154 of the 100Mbit autodetection circuitry. They say we only want to
1155 do this for rev C of the chip, but engineers at NSC (Bradley
1156 Kennedy) recommends always setting them. If you don't, you get
1157 errors on some autonegotiations that make the device unusable.
1158
1159 It seems that the DSP needs a few usec to reinitialize after
1160 the start of the phy. Just retry writing these values until they
1161 stick.
1162 */
1163 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1164
1165 int dspcfg;
1166 writew(1, ioaddr + PGSEL);
1167 writew(PMDCSR_VAL, ioaddr + PMDCSR);
1168 writew(TSTDAT_VAL, ioaddr + TSTDAT);
1169 np->dspcfg = (np->srr <= SRR_DP83815_C)?
1170 DSPCFG_VAL : (DSPCFG_COEF | readw(ioaddr + DSPCFG));
1171 writew(np->dspcfg, ioaddr + DSPCFG);
1172 writew(SDCFG_VAL, ioaddr + SDCFG);
1173 writew(0, ioaddr + PGSEL);
1174 readl(ioaddr + ChipConfig);
1175 udelay(10);
1176
1177 writew(1, ioaddr + PGSEL);
1178 dspcfg = readw(ioaddr + DSPCFG);
1179 writew(0, ioaddr + PGSEL);
1180 if (np->dspcfg == dspcfg)
1181 break;
1182 }
1183
1184 if (netif_msg_link(np)) {
1185 if (i==NATSEMI_HW_TIMEOUT) {
1186 printk(KERN_INFO
1187 "%s: DSPCFG mismatch after retrying for %d usec.\n",
1188 dev->name, i*10);
1189 } else {
1190 printk(KERN_INFO
1191 "%s: DSPCFG accepted after %d usec.\n",
1192 dev->name, i*10);
1193 }
1194 }
1195 /*
1196 * Enable PHY Specific event based interrupts. Link state change
1197 * and Auto-Negotiation Completion are among the affected.
1198 * Read the intr status to clear it (needed for wake events).
1199 */
1200 readw(ioaddr + MIntrStatus);
1201 writew(MICRIntEn, ioaddr + MIntrCtrl);
1202}
1203
1204static int switch_port_external(struct net_device *dev)
1205{
1206 struct netdev_private *np = netdev_priv(dev);
1207 void __iomem *ioaddr = ns_ioaddr(dev);
1208 u32 cfg;
1209
1210 cfg = readl(ioaddr + ChipConfig);
1211 if (cfg & CfgExtPhy)
1212 return 0;
1213
1214 if (netif_msg_link(np)) {
1215 printk(KERN_INFO "%s: switching to external transceiver.\n",
1216 dev->name);
1217 }
1218
1219 /* 1) switch back to external phy */
1220 writel(cfg | (CfgExtPhy | CfgPhyDis), ioaddr + ChipConfig);
1221 readl(ioaddr + ChipConfig);
1222 udelay(1);
1223
1224 /* 2) reset the external phy: */
1225 /* resetting the external PHY has been known to cause a hub supplying
1226 * power over Ethernet to kill the power. We don't want to kill
1227 * power to this computer, so we avoid resetting the phy.
1228 */
1229
1230 /* 3) reinit the phy fixup, it got lost during power down. */
1231 move_int_phy(dev, np->phy_addr_external);
1232 init_phy_fixup(dev);
1233
1234 return 1;
1235}
1236
1237static int switch_port_internal(struct net_device *dev)
1238{
1239 struct netdev_private *np = netdev_priv(dev);
1240 void __iomem *ioaddr = ns_ioaddr(dev);
1241 int i;
1242 u32 cfg;
1243 u16 bmcr;
1244
1245 cfg = readl(ioaddr + ChipConfig);
1246 if (!(cfg &CfgExtPhy))
1247 return 0;
1248
1249 if (netif_msg_link(np)) {
1250 printk(KERN_INFO "%s: switching to internal transceiver.\n",
1251 dev->name);
1252 }
1253 /* 1) switch back to internal phy: */
1254 cfg = cfg & ~(CfgExtPhy | CfgPhyDis);
1255 writel(cfg, ioaddr + ChipConfig);
1256 readl(ioaddr + ChipConfig);
1257 udelay(1);
6aa20a22 1258
1da177e4
LT		 1259 /* 2) reset the internal phy: */
1260 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1261 writel(bmcr | BMCR_RESET, ioaddr+BasicControl+(MII_BMCR<<2));
1262 readl(ioaddr + ChipConfig);
1263 udelay(10);
1264 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1265 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1266 if (!(bmcr & BMCR_RESET))
1267 break;
1268 udelay(10);
1269 }
1270 if (i==NATSEMI_HW_TIMEOUT && netif_msg_link(np)) {
1271 printk(KERN_INFO
1272 "%s: phy reset did not complete in %d usec.\n",
1273 dev->name, i*10);
1274 }
1275 /* 3) reinit the phy fixup, it got lost during power down. */
1276 init_phy_fixup(dev);
1277
1278 return 1;
1279}
1280
1281/* Scan for a PHY on the external mii bus.
1282 * There are two tricky points:
1283 * - Do not scan while the internal phy is enabled. The internal phy will
1284 * crash: e.g. reads from the DSPCFG register will return odd values and
1285 * the nasty random phy reset code will reset the nic every few seconds.
1286 * - The internal phy must be moved around, an external phy could
1287 * have the same address as the internal phy.
1288 */
1289static int find_mii(struct net_device *dev)
1290{
1291 struct netdev_private *np = netdev_priv(dev);
1292 int tmp;
1293 int i;
1294 int did_switch;
1295
1296 /* Switch to external phy */
1297 did_switch = switch_port_external(dev);
6aa20a22 1298
1da177e4
LT		 1299 /* Scan the possible phy addresses:
1300 *
1301 * PHY address 0 means that the phy is in isolate mode. Not yet
1302 * supported due to lack of test hardware. User space should
1303 * handle it through ethtool.
1304 */
1305 for (i = 1; i <= 31; i++) {
1306 move_int_phy(dev, i);
1307 tmp = miiport_read(dev, i, MII_BMSR);
1308 if (tmp != 0xffff && tmp != 0x0000) {
1309 /* found something! */
1310 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1311 + mdio_read(dev, MII_PHYSID2);
1312 if (netif_msg_probe(np)) {
1313 printk(KERN_INFO "natsemi %s: found external phy %08x at address %d.\n",
1314 pci_name(np->pci_dev), np->mii, i);
1315 }
1316 break;
1317 }
1318 }
1319 /* And switch back to internal phy: */
1320 if (did_switch)
1321 switch_port_internal(dev);
1322 return i;
1323}
1324
1325/* CFG bits [13:16] [18:23] */
1326#define CFG_RESET_SAVE 0xfde000
1327/* WCSR bits [0:4] [9:10] */
1328#define WCSR_RESET_SAVE 0x61f
1329/* RFCR bits [20] [22] [27:31] */
1330#define RFCR_RESET_SAVE 0xf8500000;
1331
1332static void natsemi_reset(struct net_device *dev)
1333{
1334 int i;
1335 u32 cfg;
1336 u32 wcsr;
1337 u32 rfcr;
1338 u16 pmatch[3];
1339 u16 sopass[3];
1340 struct netdev_private *np = netdev_priv(dev);
1341 void __iomem *ioaddr = ns_ioaddr(dev);
1342
1343 /*
1344 * Resetting the chip causes some registers to be lost.
1345 * Natsemi suggests NOT reloading the EEPROM while live, so instead
1346 * we save the state that would have been loaded from EEPROM
1347 * on a normal power-up (see the spec EEPROM map). This assumes
1348 * whoever calls this will follow up with init_registers() eventually.
1349 */
1350
1351 /* CFG */
1352 cfg = readl(ioaddr + ChipConfig) & CFG_RESET_SAVE;
1353 /* WCSR */
1354 wcsr = readl(ioaddr + WOLCmd) & WCSR_RESET_SAVE;
1355 /* RFCR */
1356 rfcr = readl(ioaddr + RxFilterAddr) & RFCR_RESET_SAVE;
1357 /* PMATCH */
1358 for (i = 0; i < 3; i++) {
1359 writel(i*2, ioaddr + RxFilterAddr);
1360 pmatch[i] = readw(ioaddr + RxFilterData);
1361 }
1362 /* SOPAS */
1363 for (i = 0; i < 3; i++) {
1364 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1365 sopass[i] = readw(ioaddr + RxFilterData);
1366 }
1367
1368 /* now whack the chip */
1369 writel(ChipReset, ioaddr + ChipCmd);
1370 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1371 if (!(readl(ioaddr + ChipCmd) & ChipReset))
1372 break;
1373 udelay(5);
1374 }
1375 if (i==NATSEMI_HW_TIMEOUT) {
1376 printk(KERN_WARNING "%s: reset did not complete in %d usec.\n",
1377 dev->name, i*5);
1378 } else if (netif_msg_hw(np)) {
1379 printk(KERN_DEBUG "%s: reset completed in %d usec.\n",
1380 dev->name, i*5);
1381 }
1382
1383 /* restore CFG */
1384 cfg |= readl(ioaddr + ChipConfig) & ~CFG_RESET_SAVE;
1385 /* turn on external phy if it was selected */
1386 if (dev->if_port == PORT_TP)
1387 cfg &= ~(CfgExtPhy | CfgPhyDis);
1388 else
1389 cfg |= (CfgExtPhy | CfgPhyDis);
1390 writel(cfg, ioaddr + ChipConfig);
1391 /* restore WCSR */
1392 wcsr |= readl(ioaddr + WOLCmd) & ~WCSR_RESET_SAVE;
1393 writel(wcsr, ioaddr + WOLCmd);
1394 /* read RFCR */
1395 rfcr |= readl(ioaddr + RxFilterAddr) & ~RFCR_RESET_SAVE;
1396 /* restore PMATCH */
1397 for (i = 0; i < 3; i++) {
1398 writel(i*2, ioaddr + RxFilterAddr);
1399 writew(pmatch[i], ioaddr + RxFilterData);
1400 }
1401 for (i = 0; i < 3; i++) {
1402 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1403 writew(sopass[i], ioaddr + RxFilterData);
1404 }
1405 /* restore RFCR */
1406 writel(rfcr, ioaddr + RxFilterAddr);
1407}
1408
e72fd96e
MB		 1409static void reset_rx(struct net_device *dev)
1410{
1411 int i;
1412 struct netdev_private *np = netdev_priv(dev);
1413 void __iomem *ioaddr = ns_ioaddr(dev);
1414
1415 np->intr_status &= ~RxResetDone;
1416
1417 writel(RxReset, ioaddr + ChipCmd);
1418
1419 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1420 np->intr_status |= readl(ioaddr + IntrStatus);
1421 if (np->intr_status & RxResetDone)
1422 break;
1423 udelay(15);
1424 }
1425 if (i==NATSEMI_HW_TIMEOUT) {
1426 printk(KERN_WARNING "%s: RX reset did not complete in %d usec.\n",
1427 dev->name, i*15);
1428 } else if (netif_msg_hw(np)) {
1429 printk(KERN_WARNING "%s: RX reset took %d usec.\n",
1430 dev->name, i*15);
1431 }
1432}
1433
1da177e4
LT		 1434static void natsemi_reload_eeprom(struct net_device *dev)
1435{
1436 struct netdev_private *np = netdev_priv(dev);
1437 void __iomem *ioaddr = ns_ioaddr(dev);
1438 int i;
1439
1440 writel(EepromReload, ioaddr + PCIBusCfg);
1441 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1442 udelay(50);
1443 if (!(readl(ioaddr + PCIBusCfg) & EepromReload))
1444 break;
1445 }
1446 if (i==NATSEMI_HW_TIMEOUT) {
1447 printk(KERN_WARNING "natsemi %s: EEPROM did not reload in %d usec.\n",
1448 pci_name(np->pci_dev), i*50);
1449 } else if (netif_msg_hw(np)) {
1450 printk(KERN_DEBUG "natsemi %s: EEPROM reloaded in %d usec.\n",
1451 pci_name(np->pci_dev), i*50);
1452 }
1453}
1454
1455static void natsemi_stop_rxtx(struct net_device *dev)
1456{
1457 void __iomem * ioaddr = ns_ioaddr(dev);
1458 struct netdev_private *np = netdev_priv(dev);
1459 int i;
1460
1461 writel(RxOff | TxOff, ioaddr + ChipCmd);
1462 for(i=0;i< NATSEMI_HW_TIMEOUT;i++) {
1463 if ((readl(ioaddr + ChipCmd) & (TxOn|RxOn)) == 0)
1464 break;
1465 udelay(5);
1466 }
1467 if (i==NATSEMI_HW_TIMEOUT) {
1468 printk(KERN_WARNING "%s: Tx/Rx process did not stop in %d usec.\n",
1469 dev->name, i*5);
1470 } else if (netif_msg_hw(np)) {
1471 printk(KERN_DEBUG "%s: Tx/Rx process stopped in %d usec.\n",
1472 dev->name, i*5);
1473 }
1474}
1475
1476static int netdev_open(struct net_device *dev)
1477{
1478 struct netdev_private *np = netdev_priv(dev);
1479 void __iomem * ioaddr = ns_ioaddr(dev);
1480 int i;
1481
1482 /* Reset the chip, just in case. */
1483 natsemi_reset(dev);
1484
1fb9df5d 1485 i = request_irq(dev->irq, &intr_handler, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 1486 if (i) return i;
1487
1488 if (netif_msg_ifup(np))
1489 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
1490 dev->name, dev->irq);
1491 i = alloc_ring(dev);
1492 if (i < 0) {
1493 free_irq(dev->irq, dev);
1494 return i;
1495 }
1496 init_ring(dev);
1497 spin_lock_irq(&np->lock);
1498 init_registers(dev);
1499 /* now set the MAC address according to dev->dev_addr */
1500 for (i = 0; i < 3; i++) {
1501 u16 mac = (dev->dev_addr[2*i+1]<<8) + dev->dev_addr[2*i];
1502
1503 writel(i*2, ioaddr + RxFilterAddr);
1504 writew(mac, ioaddr + RxFilterData);
1505 }
1506 writel(np->cur_rx_mode, ioaddr + RxFilterAddr);
1507 spin_unlock_irq(&np->lock);
1508
1509 netif_start_queue(dev);
1510
1511 if (netif_msg_ifup(np))
1512 printk(KERN_DEBUG "%s: Done netdev_open(), status: %#08x.\n",
1513 dev->name, (int)readl(ioaddr + ChipCmd));
1514
1515 /* Set the timer to check for link beat. */
1516 init_timer(&np->timer);
1517 np->timer.expires = jiffies + NATSEMI_TIMER_FREQ;
1518 np->timer.data = (unsigned long)dev;
1519 np->timer.function = &netdev_timer; /* timer handler */
1520 add_timer(&np->timer);
1521
1522 return 0;
1523}
1524
1525static void do_cable_magic(struct net_device *dev)
1526{
1527 struct netdev_private *np = netdev_priv(dev);
1528 void __iomem *ioaddr = ns_ioaddr(dev);
1529
1530 if (dev->if_port != PORT_TP)
1531 return;
1532
1533 if (np->srr >= SRR_DP83816_A5)
1534 return;
1535
1536 /*
1537 * 100 MBit links with short cables can trip an issue with the chip.
1538 * The problem manifests as lots of CRC errors and/or flickering
1539 * activity LED while idle. This process is based on instructions
1540 * from engineers at National.
1541 */
1542 if (readl(ioaddr + ChipConfig) & CfgSpeed100) {
1543 u16 data;
1544
1545 writew(1, ioaddr + PGSEL);
1546 /*
1547 * coefficient visibility should already be enabled via
1548 * DSPCFG | 0x1000
1549 */
1550 data = readw(ioaddr + TSTDAT) & 0xff;
1551 /*
1552 * the value must be negative, and within certain values
1553 * (these values all come from National)
1554 */
1555 if (!(data & 0x80) || ((data >= 0xd8) && (data <= 0xff))) {
1556 struct netdev_private *np = netdev_priv(dev);
1557
1558 /* the bug has been triggered - fix the coefficient */
1559 writew(TSTDAT_FIXED, ioaddr + TSTDAT);
1560 /* lock the value */
1561 data = readw(ioaddr + DSPCFG);
1562 np->dspcfg = data | DSPCFG_LOCK;
1563 writew(np->dspcfg, ioaddr + DSPCFG);
1564 }
1565 writew(0, ioaddr + PGSEL);
1566 }
1567}
1568
1569static void undo_cable_magic(struct net_device *dev)
1570{
1571 u16 data;
1572 struct netdev_private *np = netdev_priv(dev);
1573 void __iomem * ioaddr = ns_ioaddr(dev);
1574
1575 if (dev->if_port != PORT_TP)
1576 return;
1577
1578 if (np->srr >= SRR_DP83816_A5)
1579 return;
1580
1581 writew(1, ioaddr + PGSEL);
1582 /* make sure the lock bit is clear */
1583 data = readw(ioaddr + DSPCFG);
1584 np->dspcfg = data & ~DSPCFG_LOCK;
1585 writew(np->dspcfg, ioaddr + DSPCFG);
1586 writew(0, ioaddr + PGSEL);
1587}
1588
1589static void check_link(struct net_device *dev)
1590{
1591 struct netdev_private *np = netdev_priv(dev);
1592 void __iomem * ioaddr = ns_ioaddr(dev);
68c90166 1593 int duplex = np->duplex;
1da177e4 1594 u16 bmsr;
6aa20a22 1595
68c90166
MB		 1596 /* If we are ignoring the PHY then don't try reading it. */
1597 if (np->ignore_phy)
1598 goto propagate_state;
1599
1da177e4
LT		 1600 /* The link status field is latched: it remains low after a temporary
1601 * link failure until it's read. We need the current link status,
1602 * thus read twice.
1603 */
1604 mdio_read(dev, MII_BMSR);
1605 bmsr = mdio_read(dev, MII_BMSR);
1606
1607 if (!(bmsr & BMSR_LSTATUS)) {
1608 if (netif_carrier_ok(dev)) {
1609 if (netif_msg_link(np))
1610 printk(KERN_NOTICE "%s: link down.\n",
68c90166 1611 dev->name);
1da177e4
LT		 1612 netif_carrier_off(dev);
1613 undo_cable_magic(dev);
1614 }
1615 return;
1616 }
1617 if (!netif_carrier_ok(dev)) {
1618 if (netif_msg_link(np))
1619 printk(KERN_NOTICE "%s: link up.\n", dev->name);
1620 netif_carrier_on(dev);
1621 do_cable_magic(dev);
1622 }
1623
1624 duplex = np->full_duplex;
1625 if (!duplex) {
1626 if (bmsr & BMSR_ANEGCOMPLETE) {
1627 int tmp = mii_nway_result(
1628 np->advertising & mdio_read(dev, MII_LPA));
1629 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
1630 duplex = 1;
1631 } else if (mdio_read(dev, MII_BMCR) & BMCR_FULLDPLX)
1632 duplex = 1;
1633 }
1634
68c90166 1635propagate_state:
1da177e4
LT		 1636 /* if duplex is set then bit 28 must be set, too */
1637 if (duplex ^ !!(np->rx_config & RxAcceptTx)) {
1638 if (netif_msg_link(np))
1639 printk(KERN_INFO
1640 "%s: Setting %s-duplex based on negotiated "
1641 "link capability.\n", dev->name,
1642 duplex ? "full" : "half");
1643 if (duplex) {
1644 np->rx_config |= RxAcceptTx;
1645 np->tx_config |= TxCarrierIgn | TxHeartIgn;
1646 } else {
1647 np->rx_config &= ~RxAcceptTx;
1648 np->tx_config &= ~(TxCarrierIgn | TxHeartIgn);
1649 }
1650 writel(np->tx_config, ioaddr + TxConfig);
1651 writel(np->rx_config, ioaddr + RxConfig);
1652 }
1653}
1654
1655static void init_registers(struct net_device *dev)
1656{
1657 struct netdev_private *np = netdev_priv(dev);
1658 void __iomem * ioaddr = ns_ioaddr(dev);
1659
1660 init_phy_fixup(dev);
1661
1662 /* clear any interrupts that are pending, such as wake events */
1663 readl(ioaddr + IntrStatus);
1664
1665 writel(np->ring_dma, ioaddr + RxRingPtr);
1666 writel(np->ring_dma + RX_RING_SIZE * sizeof(struct netdev_desc),
1667 ioaddr + TxRingPtr);
1668
1669 /* Initialize other registers.
1670 * Configure the PCI bus bursts and FIFO thresholds.
1671 * Configure for standard, in-spec Ethernet.
1672 * Start with half-duplex. check_link will update
1673 * to the correct settings.
1674 */
1675
1676 /* DRTH: 2: start tx if 64 bytes are in the fifo
1677 * FLTH: 0x10: refill with next packet if 512 bytes are free
1678 * MXDMA: 0: up to 256 byte bursts.
1679 * MXDMA must be <= FLTH
1680 * ECRETRY=1
1681 * ATP=1
1682 */
1683 np->tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 |
1684 TX_FLTH_VAL | TX_DRTH_VAL_START;
1685 writel(np->tx_config, ioaddr + TxConfig);
1686
1687 /* DRTH 0x10: start copying to memory if 128 bytes are in the fifo
1688 * MXDMA 0: up to 256 byte bursts
1689 */
1690 np->rx_config = RxMxdma_256 | RX_DRTH_VAL;
1691 /* if receive ring now has bigger buffers than normal, enable jumbo */
1692 if (np->rx_buf_sz > NATSEMI_LONGPKT)
1693 np->rx_config |= RxAcceptLong;
1694
1695 writel(np->rx_config, ioaddr + RxConfig);
1696
1697 /* Disable PME:
1698 * The PME bit is initialized from the EEPROM contents.
1699 * PCI cards probably have PME disabled, but motherboard
1700 * implementations may have PME set to enable WakeOnLan.
1701 * With PME set the chip will scan incoming packets but
1702 * nothing will be written to memory. */
1703 np->SavedClkRun = readl(ioaddr + ClkRun);
1704 writel(np->SavedClkRun & ~PMEEnable, ioaddr + ClkRun);
1705 if (np->SavedClkRun & PMEStatus && netif_msg_wol(np)) {
1706 printk(KERN_NOTICE "%s: Wake-up event %#08x\n",
1707 dev->name, readl(ioaddr + WOLCmd));
1708 }
1709
1710 check_link(dev);
1711 __set_rx_mode(dev);
1712
1713 /* Enable interrupts by setting the interrupt mask. */
1714 writel(DEFAULT_INTR, ioaddr + IntrMask);
1715 writel(1, ioaddr + IntrEnable);
1716
1717 writel(RxOn | TxOn, ioaddr + ChipCmd);
1718 writel(StatsClear, ioaddr + StatsCtrl); /* Clear Stats */
1719}
1720
1721/*
1722 * netdev_timer:
1723 * Purpose:
1724 * 1) check for link changes. Usually they are handled by the MII interrupt
1725 * but it doesn't hurt to check twice.
1726 * 2) check for sudden death of the NIC:
1727 * It seems that a reference set for this chip went out with incorrect info,
1728 * and there exist boards that aren't quite right. An unexpected voltage
1729 * drop can cause the PHY to get itself in a weird state (basically reset).
1730 * NOTE: this only seems to affect revC chips.
1731 * 3) check of death of the RX path due to OOM
1732 */
1733static void netdev_timer(unsigned long data)
1734{
1735 struct net_device *dev = (struct net_device *)data;
1736 struct netdev_private *np = netdev_priv(dev);
1737 void __iomem * ioaddr = ns_ioaddr(dev);
1738 int next_tick = 5*HZ;
1739
1740 if (netif_msg_timer(np)) {
1741 /* DO NOT read the IntrStatus register,
1742 * a read clears any pending interrupts.
1743 */
1744 printk(KERN_DEBUG "%s: Media selection timer tick.\n",
1745 dev->name);
1746 }
1747
1748 if (dev->if_port == PORT_TP) {
1749 u16 dspcfg;
1750
1751 spin_lock_irq(&np->lock);
1752 /* check for a nasty random phy-reset - use dspcfg as a flag */
1753 writew(1, ioaddr+PGSEL);
1754 dspcfg = readw(ioaddr+DSPCFG);
1755 writew(0, ioaddr+PGSEL);
1756 if (dspcfg != np->dspcfg) {
1757 if (!netif_queue_stopped(dev)) {
1758 spin_unlock_irq(&np->lock);
1759 if (netif_msg_hw(np))
1760 printk(KERN_NOTICE "%s: possible phy reset: "
1761 "re-initializing\n", dev->name);
1762 disable_irq(dev->irq);
1763 spin_lock_irq(&np->lock);
1764 natsemi_stop_rxtx(dev);
1765 dump_ring(dev);
1766 reinit_ring(dev);
1767 init_registers(dev);
1768 spin_unlock_irq(&np->lock);
1769 enable_irq(dev->irq);
1770 } else {
1771 /* hurry back */
1772 next_tick = HZ;
1773 spin_unlock_irq(&np->lock);
1774 }
1775 } else {
1776 /* init_registers() calls check_link() for the above case */
1777 check_link(dev);
1778 spin_unlock_irq(&np->lock);
1779 }
1780 } else {
1781 spin_lock_irq(&np->lock);
1782 check_link(dev);
1783 spin_unlock_irq(&np->lock);
1784 }
1785 if (np->oom) {
1786 disable_irq(dev->irq);
1787 np->oom = 0;
1788 refill_rx(dev);
1789 enable_irq(dev->irq);
1790 if (!np->oom) {
1791 writel(RxOn, ioaddr + ChipCmd);
1792 } else {
1793 next_tick = 1;
1794 }
1795 }
1796 mod_timer(&np->timer, jiffies + next_tick);
1797}
1798
1799static void dump_ring(struct net_device *dev)
1800{
1801 struct netdev_private *np = netdev_priv(dev);
1802
1803 if (netif_msg_pktdata(np)) {
1804 int i;
1805 printk(KERN_DEBUG " Tx ring at %p:\n", np->tx_ring);
1806 for (i = 0; i < TX_RING_SIZE; i++) {
1807 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1808 i, np->tx_ring[i].next_desc,
1809 np->tx_ring[i].cmd_status,
1810 np->tx_ring[i].addr);
1811 }
1812 printk(KERN_DEBUG " Rx ring %p:\n", np->rx_ring);
1813 for (i = 0; i < RX_RING_SIZE; i++) {
1814 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1815 i, np->rx_ring[i].next_desc,
1816 np->rx_ring[i].cmd_status,
1817 np->rx_ring[i].addr);
1818 }
1819 }
1820}
1821
1822static void tx_timeout(struct net_device *dev)
1823{
1824 struct netdev_private *np = netdev_priv(dev);
1825 void __iomem * ioaddr = ns_ioaddr(dev);
1826
1827 disable_irq(dev->irq);
1828 spin_lock_irq(&np->lock);
1829 if (!np->hands_off) {
1830 if (netif_msg_tx_err(np))
1831 printk(KERN_WARNING
1832 "%s: Transmit timed out, status %#08x,"
1833 " resetting...\n",
1834 dev->name, readl(ioaddr + IntrStatus));
1835 dump_ring(dev);
1836
1837 natsemi_reset(dev);
1838 reinit_ring(dev);
1839 init_registers(dev);
1840 } else {
1841 printk(KERN_WARNING
1842 "%s: tx_timeout while in hands_off state?\n",
1843 dev->name);
1844 }
1845 spin_unlock_irq(&np->lock);
1846 enable_irq(dev->irq);
1847
1848 dev->trans_start = jiffies;
1849 np->stats.tx_errors++;
1850 netif_wake_queue(dev);
1851}
1852
1853static int alloc_ring(struct net_device *dev)
1854{
1855 struct netdev_private *np = netdev_priv(dev);
1856 np->rx_ring = pci_alloc_consistent(np->pci_dev,
1857 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
1858 &np->ring_dma);
1859 if (!np->rx_ring)
1860 return -ENOMEM;
1861 np->tx_ring = &np->rx_ring[RX_RING_SIZE];
1862 return 0;
1863}
1864
1865static void refill_rx(struct net_device *dev)
1866{
1867 struct netdev_private *np = netdev_priv(dev);
1868
1869 /* Refill the Rx ring buffers. */
1870 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1871 struct sk_buff *skb;
1872 int entry = np->dirty_rx % RX_RING_SIZE;
1873 if (np->rx_skbuff[entry] == NULL) {
1874 unsigned int buflen = np->rx_buf_sz+NATSEMI_PADDING;
1875 skb = dev_alloc_skb(buflen);
1876 np->rx_skbuff[entry] = skb;
1877 if (skb == NULL)
1878 break; /* Better luck next round. */
1879 skb->dev = dev; /* Mark as being used by this device. */
1880 np->rx_dma[entry] = pci_map_single(np->pci_dev,
689be439 1881 skb->data, buflen, PCI_DMA_FROMDEVICE);
1da177e4
LT		 1882 np->rx_ring[entry].addr = cpu_to_le32(np->rx_dma[entry]);
1883 }
1884 np->rx_ring[entry].cmd_status = cpu_to_le32(np->rx_buf_sz);
1885 }
1886 if (np->cur_rx - np->dirty_rx == RX_RING_SIZE) {
1887 if (netif_msg_rx_err(np))
1888 printk(KERN_WARNING "%s: going OOM.\n", dev->name);
1889 np->oom = 1;
1890 }
1891}
1892
1893static void set_bufsize(struct net_device *dev)
1894{
1895 struct netdev_private *np = netdev_priv(dev);
1896 if (dev->mtu <= ETH_DATA_LEN)
1897 np->rx_buf_sz = ETH_DATA_LEN + NATSEMI_HEADERS;
1898 else
1899 np->rx_buf_sz = dev->mtu + NATSEMI_HEADERS;
1900}
1901
1902/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1903static void init_ring(struct net_device *dev)
1904{
1905 struct netdev_private *np = netdev_priv(dev);
1906 int i;
1907
1908 /* 1) TX ring */
1909 np->dirty_tx = np->cur_tx = 0;
1910 for (i = 0; i < TX_RING_SIZE; i++) {
1911 np->tx_skbuff[i] = NULL;
1912 np->tx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1913 +sizeof(struct netdev_desc)
1914 *((i+1)%TX_RING_SIZE+RX_RING_SIZE));
1915 np->tx_ring[i].cmd_status = 0;
1916 }
1917
1918 /* 2) RX ring */
1919 np->dirty_rx = 0;
1920 np->cur_rx = RX_RING_SIZE;
1921 np->oom = 0;
1922 set_bufsize(dev);
1923
1924 np->rx_head_desc = &np->rx_ring[0];
1925
1926 /* Please be carefull before changing this loop - at least gcc-2.95.1
1927 * miscompiles it otherwise.
1928 */
1929 /* Initialize all Rx descriptors. */
1930 for (i = 0; i < RX_RING_SIZE; i++) {
1931 np->rx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1932 +sizeof(struct netdev_desc)
1933 *((i+1)%RX_RING_SIZE));
1934 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
1935 np->rx_skbuff[i] = NULL;
1936 }
1937 refill_rx(dev);
1938 dump_ring(dev);
1939}
1940
1941static void drain_tx(struct net_device *dev)
1942{
1943 struct netdev_private *np = netdev_priv(dev);
1944 int i;
1945
1946 for (i = 0; i < TX_RING_SIZE; i++) {
1947 if (np->tx_skbuff[i]) {
1948 pci_unmap_single(np->pci_dev,
1949 np->tx_dma[i], np->tx_skbuff[i]->len,
1950 PCI_DMA_TODEVICE);
1951 dev_kfree_skb(np->tx_skbuff[i]);
1952 np->stats.tx_dropped++;
1953 }
1954 np->tx_skbuff[i] = NULL;
1955 }
1956}
1957
1958static void drain_rx(struct net_device *dev)
1959{
1960 struct netdev_private *np = netdev_priv(dev);
1961 unsigned int buflen = np->rx_buf_sz;
1962 int i;
1963
1964 /* Free all the skbuffs in the Rx queue. */
1965 for (i = 0; i < RX_RING_SIZE; i++) {
1966 np->rx_ring[i].cmd_status = 0;
1967 np->rx_ring[i].addr = 0xBADF00D0; /* An invalid address. */
1968 if (np->rx_skbuff[i]) {
1969 pci_unmap_single(np->pci_dev,
1970 np->rx_dma[i], buflen,
1971 PCI_DMA_FROMDEVICE);
1972 dev_kfree_skb(np->rx_skbuff[i]);
1973 }
1974 np->rx_skbuff[i] = NULL;
1975 }
1976}
1977
1978static void drain_ring(struct net_device *dev)
1979{
1980 drain_rx(dev);
1981 drain_tx(dev);
1982}
1983
1984static void free_ring(struct net_device *dev)
1985{
1986 struct netdev_private *np = netdev_priv(dev);
1987 pci_free_consistent(np->pci_dev,
1988 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
1989 np->rx_ring, np->ring_dma);
1990}
1991
1992static void reinit_rx(struct net_device *dev)
1993{
1994 struct netdev_private *np = netdev_priv(dev);
1995 int i;
1996
1997 /* RX Ring */
1998 np->dirty_rx = 0;
1999 np->cur_rx = RX_RING_SIZE;
2000 np->rx_head_desc = &np->rx_ring[0];
2001 /* Initialize all Rx descriptors. */
2002 for (i = 0; i < RX_RING_SIZE; i++)
2003 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
2004
2005 refill_rx(dev);
2006}
2007
2008static void reinit_ring(struct net_device *dev)
2009{
2010 struct netdev_private *np = netdev_priv(dev);
2011 int i;
2012
2013 /* drain TX ring */
2014 drain_tx(dev);
2015 np->dirty_tx = np->cur_tx = 0;
2016 for (i=0;i<TX_RING_SIZE;i++)
2017 np->tx_ring[i].cmd_status = 0;
2018
2019 reinit_rx(dev);
2020}
2021
2022static int start_tx(struct sk_buff *skb, struct net_device *dev)
2023{
2024 struct netdev_private *np = netdev_priv(dev);
2025 void __iomem * ioaddr = ns_ioaddr(dev);
2026 unsigned entry;
6006f7f5 2027 unsigned long flags;
1da177e4
LT		 2028
2029 /* Note: Ordering is important here, set the field with the
2030 "ownership" bit last, and only then increment cur_tx. */
2031
2032 /* Calculate the next Tx descriptor entry. */
2033 entry = np->cur_tx % TX_RING_SIZE;
2034
2035 np->tx_skbuff[entry] = skb;
2036 np->tx_dma[entry] = pci_map_single(np->pci_dev,
2037 skb->data,skb->len, PCI_DMA_TODEVICE);
2038
2039 np->tx_ring[entry].addr = cpu_to_le32(np->tx_dma[entry]);
2040
6006f7f5 2041 spin_lock_irqsave(&np->lock, flags);
1da177e4
LT		 2042
2043 if (!np->hands_off) {
2044 np->tx_ring[entry].cmd_status = cpu_to_le32(DescOwn | skb->len);
2045 /* StrongARM: Explicitly cache flush np->tx_ring and
2046 * skb->data,skb->len. */
2047 wmb();
2048 np->cur_tx++;
2049 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1) {
2050 netdev_tx_done(dev);
2051 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1)
2052 netif_stop_queue(dev);
2053 }
2054 /* Wake the potentially-idle transmit channel. */
2055 writel(TxOn, ioaddr + ChipCmd);
2056 } else {
2057 dev_kfree_skb_irq(skb);
2058 np->stats.tx_dropped++;
2059 }
6006f7f5 2060 spin_unlock_irqrestore(&np->lock, flags);
1da177e4
LT		 2061
2062 dev->trans_start = jiffies;
2063
2064 if (netif_msg_tx_queued(np)) {
2065 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
2066 dev->name, np->cur_tx, entry);
2067 }
2068 return 0;
2069}
2070
2071static void netdev_tx_done(struct net_device *dev)
2072{
2073 struct netdev_private *np = netdev_priv(dev);
2074
2075 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
2076 int entry = np->dirty_tx % TX_RING_SIZE;
2077 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescOwn))
2078 break;
2079 if (netif_msg_tx_done(np))
2080 printk(KERN_DEBUG
2081 "%s: tx frame #%d finished, status %#08x.\n",
2082 dev->name, np->dirty_tx,
2083 le32_to_cpu(np->tx_ring[entry].cmd_status));
2084 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescPktOK)) {
2085 np->stats.tx_packets++;
2086 np->stats.tx_bytes += np->tx_skbuff[entry]->len;
2087 } else { /* Various Tx errors */
2088 int tx_status =
2089 le32_to_cpu(np->tx_ring[entry].cmd_status);
2090 if (tx_status & (DescTxAbort|DescTxExcColl))
2091 np->stats.tx_aborted_errors++;
2092 if (tx_status & DescTxFIFO)
2093 np->stats.tx_fifo_errors++;
2094 if (tx_status & DescTxCarrier)
2095 np->stats.tx_carrier_errors++;
2096 if (tx_status & DescTxOOWCol)
2097 np->stats.tx_window_errors++;
2098 np->stats.tx_errors++;
2099 }
2100 pci_unmap_single(np->pci_dev,np->tx_dma[entry],
2101 np->tx_skbuff[entry]->len,
2102 PCI_DMA_TODEVICE);
2103 /* Free the original skb. */
2104 dev_kfree_skb_irq(np->tx_skbuff[entry]);
2105 np->tx_skbuff[entry] = NULL;
2106 }
2107 if (netif_queue_stopped(dev)
2108 && np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
2109 /* The ring is no longer full, wake queue. */
2110 netif_wake_queue(dev);
2111 }
2112}
2113
b27a16b7
MB		 2114/* The interrupt handler doesn't actually handle interrupts itself, it
2115 * schedules a NAPI poll if there is anything to do. */
7d12e780 2116static irqreturn_t intr_handler(int irq, void *dev_instance)
1da177e4
LT		 2117{
2118 struct net_device *dev = dev_instance;
2119 struct netdev_private *np = netdev_priv(dev);
2120 void __iomem * ioaddr = ns_ioaddr(dev);
1da177e4
LT		 2121
2122 if (np->hands_off)
2123 return IRQ_NONE;
6aa20a22 2124
b27a16b7
MB		 2125 /* Reading automatically acknowledges. */
2126 np->intr_status = readl(ioaddr + IntrStatus);
1da177e4 2127
b27a16b7
MB		 2128 if (netif_msg_intr(np))
2129 printk(KERN_DEBUG
2130 "%s: Interrupt, status %#08x, mask %#08x.\n",
2131 dev->name, np->intr_status,
2132 readl(ioaddr + IntrMask));
1da177e4 2133
6aa20a22 2134 if (!np->intr_status)
b27a16b7 2135 return IRQ_NONE;
1da177e4 2136
b27a16b7
MB		 2137 prefetch(&np->rx_skbuff[np->cur_rx % RX_RING_SIZE]);
2138
2139 if (netif_rx_schedule_prep(dev)) {
2140 /* Disable interrupts and register for poll */
2141 natsemi_irq_disable(dev);
2142 __netif_rx_schedule(dev);
2143 }
2144 return IRQ_HANDLED;
2145}
2146
2147/* This is the NAPI poll routine. As well as the standard RX handling
2148 * it also handles all other interrupts that the chip might raise.
2149 */
2150static int natsemi_poll(struct net_device *dev, int *budget)
2151{
2152 struct netdev_private *np = netdev_priv(dev);
2153 void __iomem * ioaddr = ns_ioaddr(dev);
1da177e4 2154
b27a16b7
MB		 2155 int work_to_do = min(*budget, dev->quota);
2156 int work_done = 0;
2157
2158 do {
2159 if (np->intr_status &
2160 (IntrTxDone | IntrTxIntr | IntrTxIdle | IntrTxErr)) {
1da177e4
LT		 2161 spin_lock(&np->lock);
2162 netdev_tx_done(dev);
2163 spin_unlock(&np->lock);
2164 }
2165
2166 /* Abnormal error summary/uncommon events handlers. */
b27a16b7
MB		 2167 if (np->intr_status & IntrAbnormalSummary)
2168 netdev_error(dev, np->intr_status);
6aa20a22 2169
b27a16b7
MB		 2170 if (np->intr_status &
2171 (IntrRxDone | IntrRxIntr | RxStatusFIFOOver |
2172 IntrRxErr | IntrRxOverrun)) {
2173 netdev_rx(dev, &work_done, work_to_do);
1da177e4 2174 }
6aa20a22 2175
b27a16b7
MB		 2176 *budget -= work_done;
2177 dev->quota -= work_done;
1da177e4 2178
b27a16b7
MB		 2179 if (work_done >= work_to_do)
2180 return 1;
2181
2182 np->intr_status = readl(ioaddr + IntrStatus);
2183 } while (np->intr_status);
1da177e4 2184
b27a16b7
MB		 2185 netif_rx_complete(dev);
2186
2187 /* Reenable interrupts providing nothing is trying to shut
2188 * the chip down. */
2189 spin_lock(&np->lock);
2190 if (!np->hands_off && netif_running(dev))
2191 natsemi_irq_enable(dev);
2192 spin_unlock(&np->lock);
2193
2194 return 0;
1da177e4
LT		 2195}
2196
2197/* This routine is logically part of the interrupt handler, but separated
2198 for clarity and better register allocation. */
b27a16b7 2199static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do)
1da177e4
LT		 2200{
2201 struct netdev_private *np = netdev_priv(dev);
2202 int entry = np->cur_rx % RX_RING_SIZE;
2203 int boguscnt = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
2204 s32 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2205 unsigned int buflen = np->rx_buf_sz;
2206 void __iomem * ioaddr = ns_ioaddr(dev);
2207
2208 /* If the driver owns the next entry it's a new packet. Send it up. */
2209 while (desc_status < 0) { /* e.g. & DescOwn */
2210 int pkt_len;
2211 if (netif_msg_rx_status(np))
2212 printk(KERN_DEBUG
2213 " netdev_rx() entry %d status was %#08x.\n",
2214 entry, desc_status);
2215 if (--boguscnt < 0)
2216 break;
b27a16b7
MB		 2217
2218 if (*work_done >= work_to_do)
2219 break;
2220
2221 (*work_done)++;
2222
1da177e4
LT		 2223 pkt_len = (desc_status & DescSizeMask) - 4;
2224 if ((desc_status&(DescMore|DescPktOK|DescRxLong)) != DescPktOK){
2225 if (desc_status & DescMore) {
6006f7f5
SS		 2226 unsigned long flags;
2227
1da177e4
LT		 2228 if (netif_msg_rx_err(np))
2229 printk(KERN_WARNING
2230 "%s: Oversized(?) Ethernet "
2231 "frame spanned multiple "
2232 "buffers, entry %#08x "
2233 "status %#08x.\n", dev->name,
2234 np->cur_rx, desc_status);
2235 np->stats.rx_length_errors++;
e72fd96e
MB		 2236
2237 /* The RX state machine has probably
2238 * locked up beneath us. Follow the
2239 * reset procedure documented in
2240 * AN-1287. */
2241
6006f7f5 2242 spin_lock_irqsave(&np->lock, flags);
e72fd96e
MB		 2243 reset_rx(dev);
2244 reinit_rx(dev);
2245 writel(np->ring_dma, ioaddr + RxRingPtr);
2246 check_link(dev);
6006f7f5 2247 spin_unlock_irqrestore(&np->lock, flags);
e72fd96e
MB		 2248
2249 /* We'll enable RX on exit from this
2250 * function. */
2251 break;
2252
1da177e4
LT		 2253 } else {
2254 /* There was an error. */
2255 np->stats.rx_errors++;
2256 if (desc_status & (DescRxAbort|DescRxOver))
2257 np->stats.rx_over_errors++;
2258 if (desc_status & (DescRxLong|DescRxRunt))
2259 np->stats.rx_length_errors++;
2260 if (desc_status & (DescRxInvalid|DescRxAlign))
2261 np->stats.rx_frame_errors++;
2262 if (desc_status & DescRxCRC)
2263 np->stats.rx_crc_errors++;
2264 }
2265 } else if (pkt_len > np->rx_buf_sz) {
2266 /* if this is the tail of a double buffer
2267 * packet, we've already counted the error
2268 * on the first part. Ignore the second half.
2269 */
2270 } else {
2271 struct sk_buff *skb;
2272 /* Omit CRC size. */
2273 /* Check if the packet is long enough to accept
2274 * without copying to a minimally-sized skbuff. */
2275 if (pkt_len < rx_copybreak
2276 && (skb = dev_alloc_skb(pkt_len + RX_OFFSET)) != NULL) {
2277 skb->dev = dev;
2278 /* 16 byte align the IP header */
2279 skb_reserve(skb, RX_OFFSET);
2280 pci_dma_sync_single_for_cpu(np->pci_dev,
2281 np->rx_dma[entry],
2282 buflen,
2283 PCI_DMA_FROMDEVICE);
2284 eth_copy_and_sum(skb,
689be439 2285 np->rx_skbuff[entry]->data, pkt_len, 0);
1da177e4
LT		 2286 skb_put(skb, pkt_len);
2287 pci_dma_sync_single_for_device(np->pci_dev,
2288 np->rx_dma[entry],
2289 buflen,
2290 PCI_DMA_FROMDEVICE);
2291 } else {
2292 pci_unmap_single(np->pci_dev, np->rx_dma[entry],
2293 buflen, PCI_DMA_FROMDEVICE);
2294 skb_put(skb = np->rx_skbuff[entry], pkt_len);
2295 np->rx_skbuff[entry] = NULL;
2296 }
2297 skb->protocol = eth_type_trans(skb, dev);
b27a16b7 2298 netif_receive_skb(skb);
1da177e4
LT		 2299 dev->last_rx = jiffies;
2300 np->stats.rx_packets++;
2301 np->stats.rx_bytes += pkt_len;
2302 }
2303 entry = (++np->cur_rx) % RX_RING_SIZE;
2304 np->rx_head_desc = &np->rx_ring[entry];
2305 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2306 }
2307 refill_rx(dev);
2308
2309 /* Restart Rx engine if stopped. */
2310 if (np->oom)
2311 mod_timer(&np->timer, jiffies + 1);
2312 else
2313 writel(RxOn, ioaddr + ChipCmd);
2314}
2315
2316static void netdev_error(struct net_device *dev, int intr_status)
2317{
2318 struct netdev_private *np = netdev_priv(dev);
2319 void __iomem * ioaddr = ns_ioaddr(dev);
2320
2321 spin_lock(&np->lock);
2322 if (intr_status & LinkChange) {
2323 u16 lpa = mdio_read(dev, MII_LPA);
2324 if (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE
2325 && netif_msg_link(np)) {
2326 printk(KERN_INFO
2327 "%s: Autonegotiation advertising"
2328 " %#04x partner %#04x.\n", dev->name,
2329 np->advertising, lpa);
2330 }
2331
2332 /* read MII int status to clear the flag */
2333 readw(ioaddr + MIntrStatus);
2334 check_link(dev);
2335 }
2336 if (intr_status & StatsMax) {
2337 __get_stats(dev);
2338 }
2339 if (intr_status & IntrTxUnderrun) {
2340 if ((np->tx_config & TxDrthMask) < TX_DRTH_VAL_LIMIT) {
2341 np->tx_config += TX_DRTH_VAL_INC;
2342 if (netif_msg_tx_err(np))
2343 printk(KERN_NOTICE
2344 "%s: increased tx threshold, txcfg %#08x.\n",
2345 dev->name, np->tx_config);
2346 } else {
2347 if (netif_msg_tx_err(np))
2348 printk(KERN_NOTICE
2349 "%s: tx underrun with maximum tx threshold, txcfg %#08x.\n",
2350 dev->name, np->tx_config);
2351 }
2352 writel(np->tx_config, ioaddr + TxConfig);
2353 }
2354 if (intr_status & WOLPkt && netif_msg_wol(np)) {
2355 int wol_status = readl(ioaddr + WOLCmd);
2356 printk(KERN_NOTICE "%s: Link wake-up event %#08x\n",
2357 dev->name, wol_status);
2358 }
2359 if (intr_status & RxStatusFIFOOver) {
2360 if (netif_msg_rx_err(np) && netif_msg_intr(np)) {
2361 printk(KERN_NOTICE "%s: Rx status FIFO overrun\n",
2362 dev->name);
2363 }
2364 np->stats.rx_fifo_errors++;
2365 }
2366 /* Hmmmmm, it's not clear how to recover from PCI faults. */
2367 if (intr_status & IntrPCIErr) {
2368 printk(KERN_NOTICE "%s: PCI error %#08x\n", dev->name,
2369 intr_status & IntrPCIErr);
2370 np->stats.tx_fifo_errors++;
2371 np->stats.rx_fifo_errors++;
2372 }
2373 spin_unlock(&np->lock);
2374}
2375
2376static void __get_stats(struct net_device *dev)
2377{
2378 void __iomem * ioaddr = ns_ioaddr(dev);
2379 struct netdev_private *np = netdev_priv(dev);
2380
2381 /* The chip only need report frame silently dropped. */
2382 np->stats.rx_crc_errors += readl(ioaddr + RxCRCErrs);
2383 np->stats.rx_missed_errors += readl(ioaddr + RxMissed);
2384}
2385
2386static struct net_device_stats *get_stats(struct net_device *dev)
2387{
2388 struct netdev_private *np = netdev_priv(dev);
2389
2390 /* The chip only need report frame silently dropped. */
2391 spin_lock_irq(&np->lock);
2392 if (netif_running(dev) && !np->hands_off)
2393 __get_stats(dev);
2394 spin_unlock_irq(&np->lock);
2395
2396 return &np->stats;
2397}
2398
2399#ifdef CONFIG_NET_POLL_CONTROLLER
2400static void natsemi_poll_controller(struct net_device *dev)
2401{
6006f7f5
SS		 2402 struct netdev_private *np = netdev_priv(dev);
2403
1da177e4 2404 disable_irq(dev->irq);
6006f7f5
SS		 2405
2406 /*
2407 * A real interrupt might have already reached us at this point
2408 * but NAPI might still haven't called us back. As the interrupt
2409 * status register is cleared by reading, we should prevent an
2410 * interrupt loss in this case...
2411 */
2412 if (!np->intr_status)
2413 intr_handler(dev->irq, dev);
2414
1da177e4
LT		 2415 enable_irq(dev->irq);
2416}
2417#endif
2418
2419#define HASH_TABLE 0x200
2420static void __set_rx_mode(struct net_device *dev)
2421{
2422 void __iomem * ioaddr = ns_ioaddr(dev);
2423 struct netdev_private *np = netdev_priv(dev);
2424 u8 mc_filter[64]; /* Multicast hash filter */
2425 u32 rx_mode;
2426
2427 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1da177e4
LT		 2428 rx_mode = RxFilterEnable | AcceptBroadcast
2429 | AcceptAllMulticast | AcceptAllPhys | AcceptMyPhys;
2430 } else if ((dev->mc_count > multicast_filter_limit)
2431 || (dev->flags & IFF_ALLMULTI)) {
2432 rx_mode = RxFilterEnable | AcceptBroadcast
2433 | AcceptAllMulticast | AcceptMyPhys;
2434 } else {
2435 struct dev_mc_list *mclist;
2436 int i;
2437 memset(mc_filter, 0, sizeof(mc_filter));
2438 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2439 i++, mclist = mclist->next) {
2440 int i = (ether_crc(ETH_ALEN, mclist->dmi_addr) >> 23) & 0x1ff;
2441 mc_filter[i/8] |= (1 << (i & 0x07));
2442 }
2443 rx_mode = RxFilterEnable | AcceptBroadcast
2444 | AcceptMulticast | AcceptMyPhys;
2445 for (i = 0; i < 64; i += 2) {
760f86d7
HX		 2446 writel(HASH_TABLE + i, ioaddr + RxFilterAddr);
2447 writel((mc_filter[i + 1] << 8) + mc_filter[i],
2448 ioaddr + RxFilterData);
1da177e4
LT		 2449 }
2450 }
2451 writel(rx_mode, ioaddr + RxFilterAddr);
2452 np->cur_rx_mode = rx_mode;
2453}
2454
2455static int natsemi_change_mtu(struct net_device *dev, int new_mtu)
2456{
2457 if (new_mtu < 64 || new_mtu > NATSEMI_RX_LIMIT-NATSEMI_HEADERS)
2458 return -EINVAL;
2459
2460 dev->mtu = new_mtu;
2461
2462 /* synchronized against open : rtnl_lock() held by caller */
2463 if (netif_running(dev)) {
2464 struct netdev_private *np = netdev_priv(dev);
2465 void __iomem * ioaddr = ns_ioaddr(dev);
2466
2467 disable_irq(dev->irq);
2468 spin_lock(&np->lock);
2469 /* stop engines */
2470 natsemi_stop_rxtx(dev);
2471 /* drain rx queue */
2472 drain_rx(dev);
2473 /* change buffers */
2474 set_bufsize(dev);
2475 reinit_rx(dev);
2476 writel(np->ring_dma, ioaddr + RxRingPtr);
2477 /* restart engines */
2478 writel(RxOn | TxOn, ioaddr + ChipCmd);
2479 spin_unlock(&np->lock);
2480 enable_irq(dev->irq);
2481 }
2482 return 0;
2483}
2484
2485static void set_rx_mode(struct net_device *dev)
2486{
2487 struct netdev_private *np = netdev_priv(dev);
2488 spin_lock_irq(&np->lock);
2489 if (!np->hands_off)
2490 __set_rx_mode(dev);
2491 spin_unlock_irq(&np->lock);
2492}
2493
2494static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2495{
2496 struct netdev_private *np = netdev_priv(dev);
2497 strncpy(info->driver, DRV_NAME, ETHTOOL_BUSINFO_LEN);
2498 strncpy(info->version, DRV_VERSION, ETHTOOL_BUSINFO_LEN);
2499 strncpy(info->bus_info, pci_name(np->pci_dev), ETHTOOL_BUSINFO_LEN);
2500}
2501
2502static int get_regs_len(struct net_device *dev)
2503{
2504 return NATSEMI_REGS_SIZE;
2505}
2506
2507static int get_eeprom_len(struct net_device *dev)
2508{
a8b4cf42
MB		 2509 struct netdev_private *np = netdev_priv(dev);
2510 return np->eeprom_size;
1da177e4
LT		 2511}
2512
2513static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2514{
2515 struct netdev_private *np = netdev_priv(dev);
2516 spin_lock_irq(&np->lock);
2517 netdev_get_ecmd(dev, ecmd);
2518 spin_unlock_irq(&np->lock);
2519 return 0;
2520}
2521
2522static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2523{
2524 struct netdev_private *np = netdev_priv(dev);
2525 int res;
2526 spin_lock_irq(&np->lock);
2527 res = netdev_set_ecmd(dev, ecmd);
2528 spin_unlock_irq(&np->lock);
2529 return res;
2530}
2531
2532static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2533{
2534 struct netdev_private *np = netdev_priv(dev);
2535 spin_lock_irq(&np->lock);
2536 netdev_get_wol(dev, &wol->supported, &wol->wolopts);
2537 netdev_get_sopass(dev, wol->sopass);
2538 spin_unlock_irq(&np->lock);
2539}
2540
2541static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2542{
2543 struct netdev_private *np = netdev_priv(dev);
2544 int res;
2545 spin_lock_irq(&np->lock);
2546 netdev_set_wol(dev, wol->wolopts);
2547 res = netdev_set_sopass(dev, wol->sopass);
2548 spin_unlock_irq(&np->lock);
2549 return res;
2550}
2551
2552static void get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
2553{
2554 struct netdev_private *np = netdev_priv(dev);
2555 regs->version = NATSEMI_REGS_VER;
2556 spin_lock_irq(&np->lock);
2557 netdev_get_regs(dev, buf);
2558 spin_unlock_irq(&np->lock);
2559}
2560
2561static u32 get_msglevel(struct net_device *dev)
2562{
2563 struct netdev_private *np = netdev_priv(dev);
2564 return np->msg_enable;
2565}
2566
2567static void set_msglevel(struct net_device *dev, u32 val)
2568{
2569 struct netdev_private *np = netdev_priv(dev);
2570 np->msg_enable = val;
2571}
2572
2573static int nway_reset(struct net_device *dev)
2574{
2575 int tmp;
2576 int r = -EINVAL;
2577 /* if autoneg is off, it's an error */
2578 tmp = mdio_read(dev, MII_BMCR);
2579 if (tmp & BMCR_ANENABLE) {
2580 tmp |= (BMCR_ANRESTART);
2581 mdio_write(dev, MII_BMCR, tmp);
2582 r = 0;
2583 }
2584 return r;
2585}
2586
2587static u32 get_link(struct net_device *dev)
2588{
2589 /* LSTATUS is latched low until a read - so read twice */
2590 mdio_read(dev, MII_BMSR);
2591 return (mdio_read(dev, MII_BMSR)&BMSR_LSTATUS) ? 1:0;
2592}
2593
2594static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
2595{
2596 struct netdev_private *np = netdev_priv(dev);
a8b4cf42 2597 u8 *eebuf;
1da177e4
LT		 2598 int res;
2599
a8b4cf42
MB		 2600 eebuf = kmalloc(np->eeprom_size, GFP_KERNEL);
2601 if (!eebuf)
2602 return -ENOMEM;
2603
1da177e4
LT		 2604 eeprom->magic = PCI_VENDOR_ID_NS | (PCI_DEVICE_ID_NS_83815<<16);
2605 spin_lock_irq(&np->lock);
2606 res = netdev_get_eeprom(dev, eebuf);
2607 spin_unlock_irq(&np->lock);
2608 if (!res)
2609 memcpy(data, eebuf+eeprom->offset, eeprom->len);
a8b4cf42 2610 kfree(eebuf);
1da177e4
LT		 2611 return res;
2612}
2613
7282d491 2614static const struct ethtool_ops ethtool_ops = {
1da177e4
LT		 2615 .get_drvinfo = get_drvinfo,
2616 .get_regs_len = get_regs_len,
2617 .get_eeprom_len = get_eeprom_len,
2618 .get_settings = get_settings,
2619 .set_settings = set_settings,
2620 .get_wol = get_wol,
2621 .set_wol = set_wol,
2622 .get_regs = get_regs,
2623 .get_msglevel = get_msglevel,
2624 .set_msglevel = set_msglevel,
2625 .nway_reset = nway_reset,
2626 .get_link = get_link,
2627 .get_eeprom = get_eeprom,
2628};
2629
2630static int netdev_set_wol(struct net_device *dev, u32 newval)
2631{
2632 struct netdev_private *np = netdev_priv(dev);
2633 void __iomem * ioaddr = ns_ioaddr(dev);
2634 u32 data = readl(ioaddr + WOLCmd) & ~WakeOptsSummary;
2635
2636 /* translate to bitmasks this chip understands */
2637 if (newval & WAKE_PHY)
2638 data |= WakePhy;
2639 if (newval & WAKE_UCAST)
2640 data |= WakeUnicast;
2641 if (newval & WAKE_MCAST)
2642 data |= WakeMulticast;
2643 if (newval & WAKE_BCAST)
2644 data |= WakeBroadcast;
2645 if (newval & WAKE_ARP)
2646 data |= WakeArp;
2647 if (newval & WAKE_MAGIC)
2648 data |= WakeMagic;
2649 if (np->srr >= SRR_DP83815_D) {
2650 if (newval & WAKE_MAGICSECURE) {
2651 data |= WakeMagicSecure;
2652 }
2653 }
2654
2655 writel(data, ioaddr + WOLCmd);
2656
2657 return 0;
2658}
2659
2660static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur)
2661{
2662 struct netdev_private *np = netdev_priv(dev);
2663 void __iomem * ioaddr = ns_ioaddr(dev);
2664 u32 regval = readl(ioaddr + WOLCmd);
2665
2666 *supported = (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST
2667 | WAKE_ARP | WAKE_MAGIC);
2668
2669 if (np->srr >= SRR_DP83815_D) {
2670 /* SOPASS works on revD and higher */
2671 *supported |= WAKE_MAGICSECURE;
2672 }
2673 *cur = 0;
2674
2675 /* translate from chip bitmasks */
2676 if (regval & WakePhy)
2677 *cur |= WAKE_PHY;
2678 if (regval & WakeUnicast)
2679 *cur |= WAKE_UCAST;
2680 if (regval & WakeMulticast)
2681 *cur |= WAKE_MCAST;
2682 if (regval & WakeBroadcast)
2683 *cur |= WAKE_BCAST;
2684 if (regval & WakeArp)
2685 *cur |= WAKE_ARP;
2686 if (regval & WakeMagic)
2687 *cur |= WAKE_MAGIC;
2688 if (regval & WakeMagicSecure) {
2689 /* this can be on in revC, but it's broken */
2690 *cur |= WAKE_MAGICSECURE;
2691 }
2692
2693 return 0;
2694}
2695
2696static int netdev_set_sopass(struct net_device *dev, u8 *newval)
2697{
2698 struct netdev_private *np = netdev_priv(dev);
2699 void __iomem * ioaddr = ns_ioaddr(dev);
2700 u16 *sval = (u16 *)newval;
2701 u32 addr;
2702
2703 if (np->srr < SRR_DP83815_D) {
2704 return 0;
2705 }
2706
2707 /* enable writing to these registers by disabling the RX filter */
2708 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2709 addr &= ~RxFilterEnable;
2710 writel(addr, ioaddr + RxFilterAddr);
2711
2712 /* write the three words to (undocumented) RFCR vals 0xa, 0xc, 0xe */
2713 writel(addr | 0xa, ioaddr + RxFilterAddr);
2714 writew(sval[0], ioaddr + RxFilterData);
2715
2716 writel(addr | 0xc, ioaddr + RxFilterAddr);
2717 writew(sval[1], ioaddr + RxFilterData);
2718
2719 writel(addr | 0xe, ioaddr + RxFilterAddr);
2720 writew(sval[2], ioaddr + RxFilterData);
2721
2722 /* re-enable the RX filter */
2723 writel(addr | RxFilterEnable, ioaddr + RxFilterAddr);
2724
2725 return 0;
2726}
2727
2728static int netdev_get_sopass(struct net_device *dev, u8 *data)
2729{
2730 struct netdev_private *np = netdev_priv(dev);
2731 void __iomem * ioaddr = ns_ioaddr(dev);
2732 u16 *sval = (u16 *)data;
2733 u32 addr;
2734
2735 if (np->srr < SRR_DP83815_D) {
2736 sval[0] = sval[1] = sval[2] = 0;
2737 return 0;
2738 }
2739
2740 /* read the three words from (undocumented) RFCR vals 0xa, 0xc, 0xe */
2741 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2742
2743 writel(addr | 0xa, ioaddr + RxFilterAddr);
2744 sval[0] = readw(ioaddr + RxFilterData);
2745
2746 writel(addr | 0xc, ioaddr + RxFilterAddr);
2747 sval[1] = readw(ioaddr + RxFilterData);
2748
2749 writel(addr | 0xe, ioaddr + RxFilterAddr);
2750 sval[2] = readw(ioaddr + RxFilterData);
2751
2752 writel(addr, ioaddr + RxFilterAddr);
2753
2754 return 0;
2755}
2756
2757static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2758{
2759 struct netdev_private *np = netdev_priv(dev);
2760 u32 tmp;
2761
2762 ecmd->port = dev->if_port;
2763 ecmd->speed = np->speed;
2764 ecmd->duplex = np->duplex;
2765 ecmd->autoneg = np->autoneg;
2766 ecmd->advertising = 0;
2767 if (np->advertising & ADVERTISE_10HALF)
2768 ecmd->advertising |= ADVERTISED_10baseT_Half;
2769 if (np->advertising & ADVERTISE_10FULL)
2770 ecmd->advertising |= ADVERTISED_10baseT_Full;
2771 if (np->advertising & ADVERTISE_100HALF)
2772 ecmd->advertising |= ADVERTISED_100baseT_Half;
2773 if (np->advertising & ADVERTISE_100FULL)
2774 ecmd->advertising |= ADVERTISED_100baseT_Full;
2775 ecmd->supported = (SUPPORTED_Autoneg |
2776 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2777 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2778 SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_FIBRE);
2779 ecmd->phy_address = np->phy_addr_external;
2780 /*
2781 * We intentionally report the phy address of the external
2782 * phy, even if the internal phy is used. This is necessary
2783 * to work around a deficiency of the ethtool interface:
2784 * It's only possible to query the settings of the active
6aa20a22 2785 * port. Therefore
1da177e4
LT		 2786 * # ethtool -s ethX port mii
2787 * actually sends an ioctl to switch to port mii with the
2788 * settings that are used for the current active port.
2789 * If we would report a different phy address in this
2790 * command, then
2791 * # ethtool -s ethX port tp;ethtool -s ethX port mii
2792 * would unintentionally change the phy address.
2793 *
2794 * Fortunately the phy address doesn't matter with the
2795 * internal phy...
2796 */
2797
2798 /* set information based on active port type */
2799 switch (ecmd->port) {
2800 default:
2801 case PORT_TP:
2802 ecmd->advertising |= ADVERTISED_TP;
2803 ecmd->transceiver = XCVR_INTERNAL;
2804 break;
2805 case PORT_MII:
2806 ecmd->advertising |= ADVERTISED_MII;
2807 ecmd->transceiver = XCVR_EXTERNAL;
2808 break;
2809 case PORT_FIBRE:
2810 ecmd->advertising |= ADVERTISED_FIBRE;
2811 ecmd->transceiver = XCVR_EXTERNAL;
2812 break;
2813 }
2814
2815 /* if autonegotiation is on, try to return the active speed/duplex */
2816 if (ecmd->autoneg == AUTONEG_ENABLE) {
2817 ecmd->advertising |= ADVERTISED_Autoneg;
2818 tmp = mii_nway_result(
2819 np->advertising & mdio_read(dev, MII_LPA));
2820 if (tmp == LPA_100FULL || tmp == LPA_100HALF)
2821 ecmd->speed = SPEED_100;
2822 else
2823 ecmd->speed = SPEED_10;
2824 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
2825 ecmd->duplex = DUPLEX_FULL;
2826 else
2827 ecmd->duplex = DUPLEX_HALF;
2828 }
2829
2830 /* ignore maxtxpkt, maxrxpkt for now */
2831
2832 return 0;
2833}
2834
2835static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2836{
2837 struct netdev_private *np = netdev_priv(dev);
2838
2839 if (ecmd->port != PORT_TP && ecmd->port != PORT_MII && ecmd->port != PORT_FIBRE)
2840 return -EINVAL;
2841 if (ecmd->transceiver != XCVR_INTERNAL && ecmd->transceiver != XCVR_EXTERNAL)
2842 return -EINVAL;
2843 if (ecmd->autoneg == AUTONEG_ENABLE) {
2844 if ((ecmd->advertising & (ADVERTISED_10baseT_Half |
2845 ADVERTISED_10baseT_Full |
2846 ADVERTISED_100baseT_Half |
2847 ADVERTISED_100baseT_Full)) == 0) {
2848 return -EINVAL;
2849 }
2850 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
2851 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
2852 return -EINVAL;
2853 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
2854 return -EINVAL;
2855 } else {
2856 return -EINVAL;
2857 }
2858
68c90166
MB		 2859 /*
2860 * If we're ignoring the PHY then autoneg and the internal
2861 * transciever are really not going to work so don't let the
2862 * user select them.
2863 */
2864 if (np->ignore_phy && (ecmd->autoneg == AUTONEG_ENABLE ||
2865 ecmd->port == PORT_TP))
2866 return -EINVAL;
2867
1da177e4
LT		 2868 /*
2869 * maxtxpkt, maxrxpkt: ignored for now.
2870 *
2871 * transceiver:
2872 * PORT_TP is always XCVR_INTERNAL, PORT_MII and PORT_FIBRE are always
2873 * XCVR_EXTERNAL. The implementation thus ignores ecmd->transceiver and
2874 * selects based on ecmd->port.
2875 *
2876 * Actually PORT_FIBRE is nearly identical to PORT_MII: it's for fibre
2877 * phys that are connected to the mii bus. It's used to apply fibre
2878 * specific updates.
2879 */
2880
2881 /* WHEW! now lets bang some bits */
2882
2883 /* save the parms */
2884 dev->if_port = ecmd->port;
2885 np->autoneg = ecmd->autoneg;
2886 np->phy_addr_external = ecmd->phy_address & PhyAddrMask;
2887 if (np->autoneg == AUTONEG_ENABLE) {
2888 /* advertise only what has been requested */
2889 np->advertising &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2890 if (ecmd->advertising & ADVERTISED_10baseT_Half)
2891 np->advertising |= ADVERTISE_10HALF;
2892 if (ecmd->advertising & ADVERTISED_10baseT_Full)
2893 np->advertising |= ADVERTISE_10FULL;
2894 if (ecmd->advertising & ADVERTISED_100baseT_Half)
2895 np->advertising |= ADVERTISE_100HALF;
2896 if (ecmd->advertising & ADVERTISED_100baseT_Full)
2897 np->advertising |= ADVERTISE_100FULL;
2898 } else {
2899 np->speed = ecmd->speed;
2900 np->duplex = ecmd->duplex;
2901 /* user overriding the initial full duplex parm? */
2902 if (np->duplex == DUPLEX_HALF)
2903 np->full_duplex = 0;
2904 }
2905
2906 /* get the right phy enabled */
2907 if (ecmd->port == PORT_TP)
2908 switch_port_internal(dev);
2909 else
2910 switch_port_external(dev);
2911
2912 /* set parms and see how this affected our link status */
2913 init_phy_fixup(dev);
2914 check_link(dev);
2915 return 0;
2916}
2917
2918static int netdev_get_regs(struct net_device *dev, u8 *buf)
2919{
2920 int i;
2921 int j;
2922 u32 rfcr;
2923 u32 *rbuf = (u32 *)buf;
2924 void __iomem * ioaddr = ns_ioaddr(dev);
2925
2926 /* read non-mii page 0 of registers */
2927 for (i = 0; i < NATSEMI_PG0_NREGS/2; i++) {
2928 rbuf[i] = readl(ioaddr + i*4);
2929 }
2930
2931 /* read current mii registers */
2932 for (i = NATSEMI_PG0_NREGS/2; i < NATSEMI_PG0_NREGS; i++)
2933 rbuf[i] = mdio_read(dev, i & 0x1f);
2934
2935 /* read only the 'magic' registers from page 1 */
2936 writew(1, ioaddr + PGSEL);
2937 rbuf[i++] = readw(ioaddr + PMDCSR);
2938 rbuf[i++] = readw(ioaddr + TSTDAT);
2939 rbuf[i++] = readw(ioaddr + DSPCFG);
2940 rbuf[i++] = readw(ioaddr + SDCFG);
2941 writew(0, ioaddr + PGSEL);
2942
2943 /* read RFCR indexed registers */
2944 rfcr = readl(ioaddr + RxFilterAddr);
2945 for (j = 0; j < NATSEMI_RFDR_NREGS; j++) {
2946 writel(j*2, ioaddr + RxFilterAddr);
2947 rbuf[i++] = readw(ioaddr + RxFilterData);
2948 }
2949 writel(rfcr, ioaddr + RxFilterAddr);
2950
2951 /* the interrupt status is clear-on-read - see if we missed any */
2952 if (rbuf[4] & rbuf[5]) {
2953 printk(KERN_WARNING
2954 "%s: shoot, we dropped an interrupt (%#08x)\n",
2955 dev->name, rbuf[4] & rbuf[5]);
2956 }
2957
2958 return 0;
2959}
2960
2961#define SWAP_BITS(x) ( (((x) & 0x0001) << 15) | (((x) & 0x0002) << 13) \
2962 | (((x) & 0x0004) << 11) | (((x) & 0x0008) << 9) \
2963 | (((x) & 0x0010) << 7) | (((x) & 0x0020) << 5) \
2964 | (((x) & 0x0040) << 3) | (((x) & 0x0080) << 1) \
2965 | (((x) & 0x0100) >> 1) | (((x) & 0x0200) >> 3) \
2966 | (((x) & 0x0400) >> 5) | (((x) & 0x0800) >> 7) \
2967 | (((x) & 0x1000) >> 9) | (((x) & 0x2000) >> 11) \
2968 | (((x) & 0x4000) >> 13) | (((x) & 0x8000) >> 15) )
2969
2970static int netdev_get_eeprom(struct net_device *dev, u8 *buf)
2971{
2972 int i;
2973 u16 *ebuf = (u16 *)buf;
2974 void __iomem * ioaddr = ns_ioaddr(dev);
a8b4cf42 2975 struct netdev_private *np = netdev_priv(dev);
1da177e4
LT		 2976
2977 /* eeprom_read reads 16 bits, and indexes by 16 bits */
a8b4cf42 2978 for (i = 0; i < np->eeprom_size/2; i++) {
1da177e4
LT		 2979 ebuf[i] = eeprom_read(ioaddr, i);
2980 /* The EEPROM itself stores data bit-swapped, but eeprom_read
2981 * reads it back "sanely". So we swap it back here in order to
2982 * present it to userland as it is stored. */
2983 ebuf[i] = SWAP_BITS(ebuf[i]);
2984 }
2985 return 0;
2986}
2987
2988static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2989{
2990 struct mii_ioctl_data *data = if_mii(rq);
2991 struct netdev_private *np = netdev_priv(dev);
2992
2993 switch(cmd) {
2994 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
2995 case SIOCDEVPRIVATE: /* for binary compat, remove in 2.5 */
2996 data->phy_id = np->phy_addr_external;
2997 /* Fall Through */
2998
2999 case SIOCGMIIREG: /* Read MII PHY register. */
3000 case SIOCDEVPRIVATE+1: /* for binary compat, remove in 2.5 */
3001 /* The phy_id is not enough to uniquely identify
3002 * the intended target. Therefore the command is sent to
3003 * the given mii on the current port.
3004 */
3005 if (dev->if_port == PORT_TP) {
3006 if ((data->phy_id & 0x1f) == np->phy_addr_external)
3007 data->val_out = mdio_read(dev,
3008 data->reg_num & 0x1f);
3009 else
3010 data->val_out = 0;
3011 } else {
3012 move_int_phy(dev, data->phy_id & 0x1f);
3013 data->val_out = miiport_read(dev, data->phy_id & 0x1f,
3014 data->reg_num & 0x1f);
3015 }
3016 return 0;
3017
3018 case SIOCSMIIREG: /* Write MII PHY register. */
3019 case SIOCDEVPRIVATE+2: /* for binary compat, remove in 2.5 */
3020 if (!capable(CAP_NET_ADMIN))
3021 return -EPERM;
3022 if (dev->if_port == PORT_TP) {
3023 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3024 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3025 np->advertising = data->val_in;
3026 mdio_write(dev, data->reg_num & 0x1f,
3027 data->val_in);
3028 }
3029 } else {
3030 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3031 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3032 np->advertising = data->val_in;
3033 }
3034 move_int_phy(dev, data->phy_id & 0x1f);
3035 miiport_write(dev, data->phy_id & 0x1f,
3036 data->reg_num & 0x1f,
3037 data->val_in);
3038 }
3039 return 0;
3040 default:
3041 return -EOPNOTSUPP;
3042 }
3043}
3044
3045static void enable_wol_mode(struct net_device *dev, int enable_intr)
3046{
3047 void __iomem * ioaddr = ns_ioaddr(dev);
3048 struct netdev_private *np = netdev_priv(dev);
3049
3050 if (netif_msg_wol(np))
3051 printk(KERN_INFO "%s: remaining active for wake-on-lan\n",
3052 dev->name);
3053
3054 /* For WOL we must restart the rx process in silent mode.
3055 * Write NULL to the RxRingPtr. Only possible if
3056 * rx process is stopped
3057 */
3058 writel(0, ioaddr + RxRingPtr);
3059
3060 /* read WoL status to clear */
3061 readl(ioaddr + WOLCmd);
3062
3063 /* PME on, clear status */
3064 writel(np->SavedClkRun | PMEEnable | PMEStatus, ioaddr + ClkRun);
3065
3066 /* and restart the rx process */
3067 writel(RxOn, ioaddr + ChipCmd);
3068
3069 if (enable_intr) {
3070 /* enable the WOL interrupt.
3071 * Could be used to send a netlink message.
3072 */
3073 writel(WOLPkt | LinkChange, ioaddr + IntrMask);
3074 writel(1, ioaddr + IntrEnable);
3075 }
3076}
3077
3078static int netdev_close(struct net_device *dev)
3079{
3080 void __iomem * ioaddr = ns_ioaddr(dev);
3081 struct netdev_private *np = netdev_priv(dev);
3082
3083 if (netif_msg_ifdown(np))
3084 printk(KERN_DEBUG
3085 "%s: Shutting down ethercard, status was %#04x.\n",
3086 dev->name, (int)readl(ioaddr + ChipCmd));
3087 if (netif_msg_pktdata(np))
3088 printk(KERN_DEBUG
3089 "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
3090 dev->name, np->cur_tx, np->dirty_tx,
3091 np->cur_rx, np->dirty_rx);
3092
3093 /*
3094 * FIXME: what if someone tries to close a device
3095 * that is suspended?
3096 * Should we reenable the nic to switch to
3097 * the final WOL settings?
3098 */
3099
3100 del_timer_sync(&np->timer);
3101 disable_irq(dev->irq);
3102 spin_lock_irq(&np->lock);
b27a16b7 3103 natsemi_irq_disable(dev);
1da177e4
LT		 3104 np->hands_off = 1;
3105 spin_unlock_irq(&np->lock);
3106 enable_irq(dev->irq);
3107
3108 free_irq(dev->irq, dev);
3109
3110 /* Interrupt disabled, interrupt handler released,
3111 * queue stopped, timer deleted, rtnl_lock held
3112 * All async codepaths that access the driver are disabled.
3113 */
3114 spin_lock_irq(&np->lock);
3115 np->hands_off = 0;
3116 readl(ioaddr + IntrMask);
3117 readw(ioaddr + MIntrStatus);
3118
3119 /* Freeze Stats */
3120 writel(StatsFreeze, ioaddr + StatsCtrl);
3121
3122 /* Stop the chip's Tx and Rx processes. */
3123 natsemi_stop_rxtx(dev);
3124
3125 __get_stats(dev);
3126 spin_unlock_irq(&np->lock);
3127
3128 /* clear the carrier last - an interrupt could reenable it otherwise */
3129 netif_carrier_off(dev);
3130 netif_stop_queue(dev);
3131
3132 dump_ring(dev);
3133 drain_ring(dev);
3134 free_ring(dev);
3135
3136 {
3137 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3138 if (wol) {
3139 /* restart the NIC in WOL mode.
3140 * The nic must be stopped for this.
3141 */
3142 enable_wol_mode(dev, 0);
3143 } else {
3144 /* Restore PME enable bit unmolested */
3145 writel(np->SavedClkRun, ioaddr + ClkRun);
3146 }
3147 }
3148 return 0;
3149}
3150
3151
3152static void __devexit natsemi_remove1 (struct pci_dev *pdev)
3153{
3154 struct net_device *dev = pci_get_drvdata(pdev);
3155 void __iomem * ioaddr = ns_ioaddr(dev);
3156
3157 unregister_netdev (dev);
3158 pci_release_regions (pdev);
3159 iounmap(ioaddr);
3160 free_netdev (dev);
3161 pci_set_drvdata(pdev, NULL);
3162}
3163
3164#ifdef CONFIG_PM
3165
3166/*
3167 * The ns83815 chip doesn't have explicit RxStop bits.
3168 * Kicking the Rx or Tx process for a new packet reenables the Rx process
3169 * of the nic, thus this function must be very careful:
3170 *
3171 * suspend/resume synchronization:
3172 * entry points:
3173 * netdev_open, netdev_close, netdev_ioctl, set_rx_mode, intr_handler,
3174 * start_tx, tx_timeout
3175 *
3176 * No function accesses the hardware without checking np->hands_off.
3177 * the check occurs under spin_lock_irq(&np->lock);
3178 * exceptions:
3179 * * netdev_ioctl: noncritical access.
3180 * * netdev_open: cannot happen due to the device_detach
3181 * * netdev_close: doesn't hurt.
3182 * * netdev_timer: timer stopped by natsemi_suspend.
3183 * * intr_handler: doesn't acquire the spinlock. suspend calls
3184 * disable_irq() to enforce synchronization.
b27a16b7
MB		 3185 * * natsemi_poll: checks before reenabling interrupts. suspend
3186 * sets hands_off, disables interrupts and then waits with
3187 * netif_poll_disable().
1da177e4
LT		 3188 *
3189 * Interrupts must be disabled, otherwise hands_off can cause irq storms.
3190 */
3191
3192static int natsemi_suspend (struct pci_dev *pdev, pm_message_t state)
3193{
3194 struct net_device *dev = pci_get_drvdata (pdev);
3195 struct netdev_private *np = netdev_priv(dev);
3196 void __iomem * ioaddr = ns_ioaddr(dev);
3197
3198 rtnl_lock();
3199 if (netif_running (dev)) {
3200 del_timer_sync(&np->timer);
3201
3202 disable_irq(dev->irq);
3203 spin_lock_irq(&np->lock);
3204
3205 writel(0, ioaddr + IntrEnable);
3206 np->hands_off = 1;
3207 natsemi_stop_rxtx(dev);
3208 netif_stop_queue(dev);
3209
3210 spin_unlock_irq(&np->lock);
3211 enable_irq(dev->irq);
3212
b27a16b7
MB		 3213 netif_poll_disable(dev);
3214
1da177e4
LT		 3215 /* Update the error counts. */
3216 __get_stats(dev);
3217
3218 /* pci_power_off(pdev, -1); */
3219 drain_ring(dev);
3220 {
3221 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3222 /* Restore PME enable bit */
3223 if (wol) {
3224 /* restart the NIC in WOL mode.
3225 * The nic must be stopped for this.
3226 * FIXME: use the WOL interrupt
3227 */
3228 enable_wol_mode(dev, 0);
3229 } else {
3230 /* Restore PME enable bit unmolested */
3231 writel(np->SavedClkRun, ioaddr + ClkRun);
3232 }
3233 }
3234 }
3235 netif_device_detach(dev);
3236 rtnl_unlock();
3237 return 0;
3238}
3239
3240
3241static int natsemi_resume (struct pci_dev *pdev)
3242{
3243 struct net_device *dev = pci_get_drvdata (pdev);
3244 struct netdev_private *np = netdev_priv(dev);
3245
3246 rtnl_lock();
3247 if (netif_device_present(dev))
3248 goto out;
3249 if (netif_running(dev)) {
3250 BUG_ON(!np->hands_off);
3251 pci_enable_device(pdev);
3252 /* pci_power_on(pdev); */
3253
3254 natsemi_reset(dev);
3255 init_ring(dev);
3256 disable_irq(dev->irq);
3257 spin_lock_irq(&np->lock);
3258 np->hands_off = 0;
3259 init_registers(dev);
3260 netif_device_attach(dev);
3261 spin_unlock_irq(&np->lock);
3262 enable_irq(dev->irq);
3263
3264 mod_timer(&np->timer, jiffies + 1*HZ);
3265 }
3266 netif_device_attach(dev);
b27a16b7 3267 netif_poll_enable(dev);
1da177e4
LT		 3268out:
3269 rtnl_unlock();
3270 return 0;
3271}
3272
3273#endif /* CONFIG_PM */
3274
3275static struct pci_driver natsemi_driver = {
3276 .name = DRV_NAME,
3277 .id_table = natsemi_pci_tbl,
3278 .probe = natsemi_probe1,
3279 .remove = __devexit_p(natsemi_remove1),
3280#ifdef CONFIG_PM
3281 .suspend = natsemi_suspend,
3282 .resume = natsemi_resume,
3283#endif
3284};
3285
3286static int __init natsemi_init_mod (void)
3287{
3288/* when a module, this is printed whether or not devices are found in probe */
3289#ifdef MODULE
3290 printk(version);
3291#endif
3292
29917620 3293 return pci_register_driver(&natsemi_driver);
1da177e4
LT		 3294}
3295
3296static void __exit natsemi_exit_mod (void)
3297{
3298 pci_unregister_driver (&natsemi_driver);
3299}
3300
3301module_init(natsemi_init_mod);
3302module_exit(natsemi_exit_mod);
3303
Linux kernel - Deliverables
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