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natsemi: fix netdev error acounting
[deliverable/linux.git] / drivers / net / natsemi.c
CommitLineData
1da177e4
LT		 1/* natsemi.c: A Linux PCI Ethernet driver for the NatSemi DP8381x series. */
2/*
3 Written/copyright 1999-2001 by Donald Becker.
4 Portions copyright (c) 2001,2002 Sun Microsystems (thockin@sun.com)
5 Portions copyright 2001,2002 Manfred Spraul (manfred@colorfullife.com)
b27a16b7 6 Portions copyright 2004 Harald Welte <laforge@gnumonks.org>
1da177e4
LT		 7
8 This software may be used and distributed according to the terms of
9 the GNU General Public License (GPL), incorporated herein by reference.
10 Drivers based on or derived from this code fall under the GPL and must
11 retain the authorship, copyright and license notice. This file is not
12 a complete program and may only be used when the entire operating
13 system is licensed under the GPL. License for under other terms may be
14 available. Contact the original author for details.
15
16 The original author may be reached as becker@scyld.com, or at
17 Scyld Computing Corporation
18 410 Severn Ave., Suite 210
19 Annapolis MD 21403
20
21 Support information and updates available at
22 http://www.scyld.com/network/netsemi.html
03a8c661 23 [link no longer provides useful info -jgarzik]
1da177e4
LT		 24
25
1da177e4
LT		 26 TODO:
27 * big endian support with CFG:BEM instead of cpu_to_le32
1da177e4
LT		 28*/
29
1da177e4
LT		 30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/string.h>
33#include <linux/timer.h>
34#include <linux/errno.h>
35#include <linux/ioport.h>
36#include <linux/slab.h>
37#include <linux/interrupt.h>
38#include <linux/pci.h>
39#include <linux/netdevice.h>
40#include <linux/etherdevice.h>
41#include <linux/skbuff.h>
42#include <linux/init.h>
43#include <linux/spinlock.h>
44#include <linux/ethtool.h>
45#include <linux/delay.h>
46#include <linux/rtnetlink.h>
47#include <linux/mii.h>
48#include <linux/crc32.h>
49#include <linux/bitops.h>
b27a16b7 50#include <linux/prefetch.h>
1da177e4
LT		 51#include <asm/processor.h> /* Processor type for cache alignment. */
52#include <asm/io.h>
53#include <asm/irq.h>
54#include <asm/uaccess.h>
55
56#define DRV_NAME "natsemi"
d5b20697
AG		 57#define DRV_VERSION "2.1"
58#define DRV_RELDATE "Sept 11, 2006"
1da177e4
LT		 59
60#define RX_OFFSET 2
61
62/* Updated to recommendations in pci-skeleton v2.03. */
63
64/* The user-configurable values.
65 These may be modified when a driver module is loaded.*/
66
67#define NATSEMI_DEF_MSG (NETIF_MSG_DRV | \
68 NETIF_MSG_LINK | \
69 NETIF_MSG_WOL | \
70 NETIF_MSG_RX_ERR | \
71 NETIF_MSG_TX_ERR)
72static int debug = -1;
73
1da177e4
LT		 74static int mtu;
75
76/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
77 This chip uses a 512 element hash table based on the Ethernet CRC. */
f71e1309 78static const int multicast_filter_limit = 100;
1da177e4
LT		 79
80/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
81 Setting to > 1518 effectively disables this feature. */
82static int rx_copybreak;
83
1a147809
MB		 84static int dspcfg_workaround = 1;
85
1da177e4
LT		 86/* Used to pass the media type, etc.
87 Both 'options[]' and 'full_duplex[]' should exist for driver
88 interoperability.
89 The media type is usually passed in 'options[]'.
90*/
91#define MAX_UNITS 8 /* More are supported, limit only on options */
92static int options[MAX_UNITS];
93static int full_duplex[MAX_UNITS];
94
95/* Operational parameters that are set at compile time. */
96
97/* Keep the ring sizes a power of two for compile efficiency.
98 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
99 Making the Tx ring too large decreases the effectiveness of channel
100 bonding and packet priority.
101 There are no ill effects from too-large receive rings. */
102#define TX_RING_SIZE 16
103#define TX_QUEUE_LEN 10 /* Limit ring entries actually used, min 4. */
104#define RX_RING_SIZE 32
105
106/* Operational parameters that usually are not changed. */
107/* Time in jiffies before concluding the transmitter is hung. */
108#define TX_TIMEOUT (2*HZ)
109
110#define NATSEMI_HW_TIMEOUT 400
111#define NATSEMI_TIMER_FREQ 3*HZ
112#define NATSEMI_PG0_NREGS 64
113#define NATSEMI_RFDR_NREGS 8
114#define NATSEMI_PG1_NREGS 4
115#define NATSEMI_NREGS (NATSEMI_PG0_NREGS + NATSEMI_RFDR_NREGS + \
116 NATSEMI_PG1_NREGS)
117#define NATSEMI_REGS_VER 1 /* v1 added RFDR registers */
118#define NATSEMI_REGS_SIZE (NATSEMI_NREGS * sizeof(u32))
1da177e4
LT		 119
120/* Buffer sizes:
121 * The nic writes 32-bit values, even if the upper bytes of
122 * a 32-bit value are beyond the end of the buffer.
123 */
124#define NATSEMI_HEADERS 22 /* 2*mac,type,vlan,crc */
125#define NATSEMI_PADDING 16 /* 2 bytes should be sufficient */
126#define NATSEMI_LONGPKT 1518 /* limit for normal packets */
127#define NATSEMI_RX_LIMIT 2046 /* maximum supported by hardware */
128
129/* These identify the driver base version and may not be removed. */
e19360f2 130static const char version[] __devinitdata =
1da177e4
LT		 131 KERN_INFO DRV_NAME " dp8381x driver, version "
132 DRV_VERSION ", " DRV_RELDATE "\n"
133 KERN_INFO " originally by Donald Becker <becker@scyld.com>\n"
1da177e4
LT		 134 KERN_INFO " 2.4.x kernel port by Jeff Garzik, Tjeerd Mulder\n";
135
136MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
137MODULE_DESCRIPTION("National Semiconductor DP8381x series PCI Ethernet driver");
138MODULE_LICENSE("GPL");
139
1da177e4
LT		 140module_param(mtu, int, 0);
141module_param(debug, int, 0);
142module_param(rx_copybreak, int, 0);
1a147809 143module_param(dspcfg_workaround, int, 1);
1da177e4
LT		 144module_param_array(options, int, NULL, 0);
145module_param_array(full_duplex, int, NULL, 0);
1da177e4
LT		 146MODULE_PARM_DESC(mtu, "DP8381x MTU (all boards)");
147MODULE_PARM_DESC(debug, "DP8381x default debug level");
6aa20a22 148MODULE_PARM_DESC(rx_copybreak,
1da177e4 149 "DP8381x copy breakpoint for copy-only-tiny-frames");
1a147809 150MODULE_PARM_DESC(dspcfg_workaround, "DP8381x: control DspCfg workaround");
6aa20a22 151MODULE_PARM_DESC(options,
1da177e4
LT		 152 "DP8381x: Bits 0-3: media type, bit 17: full duplex");
153MODULE_PARM_DESC(full_duplex, "DP8381x full duplex setting(s) (1)");
154
155/*
156 Theory of Operation
157
158I. Board Compatibility
159
160This driver is designed for National Semiconductor DP83815 PCI Ethernet NIC.
161It also works with other chips in in the DP83810 series.
162
163II. Board-specific settings
164
165This driver requires the PCI interrupt line to be valid.
166It honors the EEPROM-set values.
167
168III. Driver operation
169
170IIIa. Ring buffers
171
172This driver uses two statically allocated fixed-size descriptor lists
173formed into rings by a branch from the final descriptor to the beginning of
174the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
175The NatSemi design uses a 'next descriptor' pointer that the driver forms
176into a list.
177
178IIIb/c. Transmit/Receive Structure
179
180This driver uses a zero-copy receive and transmit scheme.
181The driver allocates full frame size skbuffs for the Rx ring buffers at
182open() time and passes the skb->data field to the chip as receive data
183buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
184a fresh skbuff is allocated and the frame is copied to the new skbuff.
185When the incoming frame is larger, the skbuff is passed directly up the
186protocol stack. Buffers consumed this way are replaced by newly allocated
187skbuffs in a later phase of receives.
188
189The RX_COPYBREAK value is chosen to trade-off the memory wasted by
190using a full-sized skbuff for small frames vs. the copying costs of larger
191frames. New boards are typically used in generously configured machines
192and the underfilled buffers have negligible impact compared to the benefit of
193a single allocation size, so the default value of zero results in never
194copying packets. When copying is done, the cost is usually mitigated by using
195a combined copy/checksum routine. Copying also preloads the cache, which is
196most useful with small frames.
197
198A subtle aspect of the operation is that unaligned buffers are not permitted
199by the hardware. Thus the IP header at offset 14 in an ethernet frame isn't
200longword aligned for further processing. On copies frames are put into the
201skbuff at an offset of "+2", 16-byte aligning the IP header.
202
203IIId. Synchronization
204
205Most operations are synchronized on the np->lock irq spinlock, except the
206performance critical codepaths:
207
208The rx process only runs in the interrupt handler. Access from outside
209the interrupt handler is only permitted after disable_irq().
210
932ff279 211The rx process usually runs under the netif_tx_lock. If np->intr_tx_reap
1da177e4
LT		 212is set, then access is permitted under spin_lock_irq(&np->lock).
213
214Thus configuration functions that want to access everything must call
215 disable_irq(dev->irq);
932ff279 216 netif_tx_lock_bh(dev);
1da177e4
LT		 217 spin_lock_irq(&np->lock);
218
219IV. Notes
220
221NatSemi PCI network controllers are very uncommon.
222
223IVb. References
224
225http://www.scyld.com/expert/100mbps.html
226http://www.scyld.com/expert/NWay.html
227Datasheet is available from:
228http://www.national.com/pf/DP/DP83815.html
229
230IVc. Errata
231
232None characterised.
233*/
234
235
236
1da177e4
LT		 237/*
238 * Support for fibre connections on Am79C874:
239 * This phy needs a special setup when connected to a fibre cable.
240 * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/22235.pdf
241 */
242#define PHYID_AM79C874 0x0022561b
243
a2b524b2
JG		 244enum {
245 MII_MCTRL = 0x15, /* mode control register */
246 MII_FX_SEL = 0x0001, /* 100BASE-FX (fiber) */
247 MII_EN_SCRM = 0x0004, /* enable scrambler (tp) */
248};
1da177e4 249
6aab4447
MB		 250enum {
251 NATSEMI_FLAG_IGNORE_PHY = 0x1,
252};
6aa20a22 253
1da177e4 254/* array of board data directly indexed by pci_tbl[x].driver_data */
f71e1309 255static const struct {
1da177e4
LT		 256 const char *name;
257 unsigned long flags;
a2b524b2 258 unsigned int eeprom_size;
1da177e4 259} natsemi_pci_info[] __devinitdata = {
6aab4447 260 { "Aculab E1/T1 PMXc cPCI carrier card", NATSEMI_FLAG_IGNORE_PHY, 128 },
a2b524b2 261 { "NatSemi DP8381[56]", 0, 24 },
1da177e4
LT		 262};
263
a2b524b2 264static const struct pci_device_id natsemi_pci_tbl[] __devinitdata = {
6aab4447 265 { PCI_VENDOR_ID_NS, 0x0020, 0x12d9, 0x000c, 0, 0, 0 },
36c843d5 266 { PCI_VENDOR_ID_NS, 0x0020, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
a2b524b2 267 { } /* terminate list */
1da177e4
LT		 268};
269MODULE_DEVICE_TABLE(pci, natsemi_pci_tbl);
270
271/* Offsets to the device registers.
272 Unlike software-only systems, device drivers interact with complex hardware.
273 It's not useful to define symbolic names for every register bit in the
274 device.
275*/
276enum register_offsets {
277 ChipCmd = 0x00,
278 ChipConfig = 0x04,
279 EECtrl = 0x08,
280 PCIBusCfg = 0x0C,
281 IntrStatus = 0x10,
282 IntrMask = 0x14,
283 IntrEnable = 0x18,
284 IntrHoldoff = 0x1C, /* DP83816 only */
285 TxRingPtr = 0x20,
286 TxConfig = 0x24,
287 RxRingPtr = 0x30,
288 RxConfig = 0x34,
289 ClkRun = 0x3C,
290 WOLCmd = 0x40,
291 PauseCmd = 0x44,
292 RxFilterAddr = 0x48,
293 RxFilterData = 0x4C,
294 BootRomAddr = 0x50,
295 BootRomData = 0x54,
296 SiliconRev = 0x58,
297 StatsCtrl = 0x5C,
298 StatsData = 0x60,
299 RxPktErrs = 0x60,
300 RxMissed = 0x68,
301 RxCRCErrs = 0x64,
302 BasicControl = 0x80,
303 BasicStatus = 0x84,
304 AnegAdv = 0x90,
305 AnegPeer = 0x94,
306 PhyStatus = 0xC0,
307 MIntrCtrl = 0xC4,
308 MIntrStatus = 0xC8,
309 PhyCtrl = 0xE4,
310
311 /* These are from the spec, around page 78... on a separate table.
312 * The meaning of these registers depend on the value of PGSEL. */
313 PGSEL = 0xCC,
314 PMDCSR = 0xE4,
315 TSTDAT = 0xFC,
316 DSPCFG = 0xF4,
317 SDCFG = 0xF8
318};
319/* the values for the 'magic' registers above (PGSEL=1) */
320#define PMDCSR_VAL 0x189c /* enable preferred adaptation circuitry */
321#define TSTDAT_VAL 0x0
322#define DSPCFG_VAL 0x5040
323#define SDCFG_VAL 0x008c /* set voltage thresholds for Signal Detect */
324#define DSPCFG_LOCK 0x20 /* coefficient lock bit in DSPCFG */
325#define DSPCFG_COEF 0x1000 /* see coefficient (in TSTDAT) bit in DSPCFG */
326#define TSTDAT_FIXED 0xe8 /* magic number for bad coefficients */
327
328/* misc PCI space registers */
329enum pci_register_offsets {
330 PCIPM = 0x44,
331};
332
333enum ChipCmd_bits {
334 ChipReset = 0x100,
335 RxReset = 0x20,
336 TxReset = 0x10,
337 RxOff = 0x08,
338 RxOn = 0x04,
339 TxOff = 0x02,
340 TxOn = 0x01,
341};
342
343enum ChipConfig_bits {
344 CfgPhyDis = 0x200,
345 CfgPhyRst = 0x400,
346 CfgExtPhy = 0x1000,
347 CfgAnegEnable = 0x2000,
348 CfgAneg100 = 0x4000,
349 CfgAnegFull = 0x8000,
350 CfgAnegDone = 0x8000000,
351 CfgFullDuplex = 0x20000000,
352 CfgSpeed100 = 0x40000000,
353 CfgLink = 0x80000000,
354};
355
356enum EECtrl_bits {
357 EE_ShiftClk = 0x04,
358 EE_DataIn = 0x01,
359 EE_ChipSelect = 0x08,
360 EE_DataOut = 0x02,
361 MII_Data = 0x10,
362 MII_Write = 0x20,
363 MII_ShiftClk = 0x40,
364};
365
366enum PCIBusCfg_bits {
367 EepromReload = 0x4,
368};
369
370/* Bits in the interrupt status/mask registers. */
371enum IntrStatus_bits {
372 IntrRxDone = 0x0001,
373 IntrRxIntr = 0x0002,
374 IntrRxErr = 0x0004,
375 IntrRxEarly = 0x0008,
376 IntrRxIdle = 0x0010,
377 IntrRxOverrun = 0x0020,
378 IntrTxDone = 0x0040,
379 IntrTxIntr = 0x0080,
380 IntrTxErr = 0x0100,
381 IntrTxIdle = 0x0200,
382 IntrTxUnderrun = 0x0400,
383 StatsMax = 0x0800,
384 SWInt = 0x1000,
385 WOLPkt = 0x2000,
386 LinkChange = 0x4000,
387 IntrHighBits = 0x8000,
388 RxStatusFIFOOver = 0x10000,
389 IntrPCIErr = 0xf00000,
390 RxResetDone = 0x1000000,
391 TxResetDone = 0x2000000,
392 IntrAbnormalSummary = 0xCD20,
393};
394
395/*
396 * Default Interrupts:
397 * Rx OK, Rx Packet Error, Rx Overrun,
398 * Tx OK, Tx Packet Error, Tx Underrun,
399 * MIB Service, Phy Interrupt, High Bits,
400 * Rx Status FIFO overrun,
401 * Received Target Abort, Received Master Abort,
402 * Signalled System Error, Received Parity Error
403 */
404#define DEFAULT_INTR 0x00f1cd65
405
406enum TxConfig_bits {
407 TxDrthMask = 0x3f,
408 TxFlthMask = 0x3f00,
409 TxMxdmaMask = 0x700000,
410 TxMxdma_512 = 0x0,
411 TxMxdma_4 = 0x100000,
412 TxMxdma_8 = 0x200000,
413 TxMxdma_16 = 0x300000,
414 TxMxdma_32 = 0x400000,
415 TxMxdma_64 = 0x500000,
416 TxMxdma_128 = 0x600000,
417 TxMxdma_256 = 0x700000,
418 TxCollRetry = 0x800000,
419 TxAutoPad = 0x10000000,
420 TxMacLoop = 0x20000000,
421 TxHeartIgn = 0x40000000,
422 TxCarrierIgn = 0x80000000
423};
424
6aa20a22 425/*
1da177e4
LT		 426 * Tx Configuration:
427 * - 256 byte DMA burst length
428 * - fill threshold 512 bytes (i.e. restart DMA when 512 bytes are free)
429 * - 64 bytes initial drain threshold (i.e. begin actual transmission
430 * when 64 byte are in the fifo)
431 * - on tx underruns, increase drain threshold by 64.
432 * - at most use a drain threshold of 1472 bytes: The sum of the fill
433 * threshold and the drain threshold must be less than 2016 bytes.
434 *
435 */
436#define TX_FLTH_VAL ((512/32) << 8)
437#define TX_DRTH_VAL_START (64/32)
438#define TX_DRTH_VAL_INC 2
439#define TX_DRTH_VAL_LIMIT (1472/32)
440
441enum RxConfig_bits {
442 RxDrthMask = 0x3e,
443 RxMxdmaMask = 0x700000,
444 RxMxdma_512 = 0x0,
445 RxMxdma_4 = 0x100000,
446 RxMxdma_8 = 0x200000,
447 RxMxdma_16 = 0x300000,
448 RxMxdma_32 = 0x400000,
449 RxMxdma_64 = 0x500000,
450 RxMxdma_128 = 0x600000,
451 RxMxdma_256 = 0x700000,
452 RxAcceptLong = 0x8000000,
453 RxAcceptTx = 0x10000000,
454 RxAcceptRunt = 0x40000000,
455 RxAcceptErr = 0x80000000
456};
457#define RX_DRTH_VAL (128/8)
458
459enum ClkRun_bits {
460 PMEEnable = 0x100,
461 PMEStatus = 0x8000,
462};
463
464enum WolCmd_bits {
465 WakePhy = 0x1,
466 WakeUnicast = 0x2,
467 WakeMulticast = 0x4,
468 WakeBroadcast = 0x8,
469 WakeArp = 0x10,
470 WakePMatch0 = 0x20,
471 WakePMatch1 = 0x40,
472 WakePMatch2 = 0x80,
473 WakePMatch3 = 0x100,
474 WakeMagic = 0x200,
475 WakeMagicSecure = 0x400,
476 SecureHack = 0x100000,
477 WokePhy = 0x400000,
478 WokeUnicast = 0x800000,
479 WokeMulticast = 0x1000000,
480 WokeBroadcast = 0x2000000,
481 WokeArp = 0x4000000,
482 WokePMatch0 = 0x8000000,
483 WokePMatch1 = 0x10000000,
484 WokePMatch2 = 0x20000000,
485 WokePMatch3 = 0x40000000,
486 WokeMagic = 0x80000000,
487 WakeOptsSummary = 0x7ff
488};
489
490enum RxFilterAddr_bits {
491 RFCRAddressMask = 0x3ff,
492 AcceptMulticast = 0x00200000,
493 AcceptMyPhys = 0x08000000,
494 AcceptAllPhys = 0x10000000,
495 AcceptAllMulticast = 0x20000000,
496 AcceptBroadcast = 0x40000000,
497 RxFilterEnable = 0x80000000
498};
499
500enum StatsCtrl_bits {
501 StatsWarn = 0x1,
502 StatsFreeze = 0x2,
503 StatsClear = 0x4,
504 StatsStrobe = 0x8,
505};
506
507enum MIntrCtrl_bits {
508 MICRIntEn = 0x2,
509};
510
511enum PhyCtrl_bits {
512 PhyAddrMask = 0x1f,
513};
514
515#define PHY_ADDR_NONE 32
516#define PHY_ADDR_INTERNAL 1
517
518/* values we might find in the silicon revision register */
519#define SRR_DP83815_C 0x0302
520#define SRR_DP83815_D 0x0403
521#define SRR_DP83816_A4 0x0504
522#define SRR_DP83816_A5 0x0505
523
524/* The Rx and Tx buffer descriptors. */
525/* Note that using only 32 bit fields simplifies conversion to big-endian
526 architectures. */
527struct netdev_desc {
528 u32 next_desc;
529 s32 cmd_status;
530 u32 addr;
531 u32 software_use;
532};
533
534/* Bits in network_desc.status */
535enum desc_status_bits {
536 DescOwn=0x80000000, DescMore=0x40000000, DescIntr=0x20000000,
537 DescNoCRC=0x10000000, DescPktOK=0x08000000,
538 DescSizeMask=0xfff,
539
540 DescTxAbort=0x04000000, DescTxFIFO=0x02000000,
541 DescTxCarrier=0x01000000, DescTxDefer=0x00800000,
542 DescTxExcDefer=0x00400000, DescTxOOWCol=0x00200000,
543 DescTxExcColl=0x00100000, DescTxCollCount=0x000f0000,
544
545 DescRxAbort=0x04000000, DescRxOver=0x02000000,
546 DescRxDest=0x01800000, DescRxLong=0x00400000,
547 DescRxRunt=0x00200000, DescRxInvalid=0x00100000,
548 DescRxCRC=0x00080000, DescRxAlign=0x00040000,
549 DescRxLoop=0x00020000, DesRxColl=0x00010000,
550};
551
552struct netdev_private {
553 /* Descriptor rings first for alignment */
554 dma_addr_t ring_dma;
555 struct netdev_desc *rx_ring;
556 struct netdev_desc *tx_ring;
557 /* The addresses of receive-in-place skbuffs */
558 struct sk_buff *rx_skbuff[RX_RING_SIZE];
559 dma_addr_t rx_dma[RX_RING_SIZE];
560 /* address of a sent-in-place packet/buffer, for later free() */
561 struct sk_buff *tx_skbuff[TX_RING_SIZE];
562 dma_addr_t tx_dma[TX_RING_SIZE];
563 struct net_device_stats stats;
564 /* Media monitoring timer */
565 struct timer_list timer;
566 /* Frequently used values: keep some adjacent for cache effect */
567 struct pci_dev *pci_dev;
568 struct netdev_desc *rx_head_desc;
569 /* Producer/consumer ring indices */
570 unsigned int cur_rx, dirty_rx;
571 unsigned int cur_tx, dirty_tx;
572 /* Based on MTU+slack. */
573 unsigned int rx_buf_sz;
574 int oom;
b27a16b7
MB		 575 /* Interrupt status */
576 u32 intr_status;
1da177e4
LT		 577 /* Do not touch the nic registers */
578 int hands_off;
68c90166
MB		 579 /* Don't pay attention to the reported link state. */
580 int ignore_phy;
1da177e4
LT		 581 /* external phy that is used: only valid if dev->if_port != PORT_TP */
582 int mii;
583 int phy_addr_external;
584 unsigned int full_duplex;
585 /* Rx filter */
586 u32 cur_rx_mode;
587 u32 rx_filter[16];
588 /* FIFO and PCI burst thresholds */
589 u32 tx_config, rx_config;
590 /* original contents of ClkRun register */
591 u32 SavedClkRun;
592 /* silicon revision */
593 u32 srr;
594 /* expected DSPCFG value */
595 u16 dspcfg;
1a147809 596 int dspcfg_workaround;
1da177e4
LT		 597 /* parms saved in ethtool format */
598 u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */
599 u8 duplex; /* Duplex, half or full */
600 u8 autoneg; /* Autonegotiation enabled */
601 /* MII transceiver section */
602 u16 advertising;
603 unsigned int iosize;
604 spinlock_t lock;
605 u32 msg_enable;
a8b4cf42
MB		 606 /* EEPROM data */
607 int eeprom_size;
1da177e4
LT		 608};
609
610static void move_int_phy(struct net_device *dev, int addr);
611static int eeprom_read(void __iomem *ioaddr, int location);
612static int mdio_read(struct net_device *dev, int reg);
613static void mdio_write(struct net_device *dev, int reg, u16 data);
614static void init_phy_fixup(struct net_device *dev);
615static int miiport_read(struct net_device *dev, int phy_id, int reg);
616static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data);
617static int find_mii(struct net_device *dev);
618static void natsemi_reset(struct net_device *dev);
619static void natsemi_reload_eeprom(struct net_device *dev);
620static void natsemi_stop_rxtx(struct net_device *dev);
621static int netdev_open(struct net_device *dev);
622static void do_cable_magic(struct net_device *dev);
623static void undo_cable_magic(struct net_device *dev);
624static void check_link(struct net_device *dev);
625static void netdev_timer(unsigned long data);
626static void dump_ring(struct net_device *dev);
627static void tx_timeout(struct net_device *dev);
628static int alloc_ring(struct net_device *dev);
629static void refill_rx(struct net_device *dev);
630static void init_ring(struct net_device *dev);
631static void drain_tx(struct net_device *dev);
632static void drain_ring(struct net_device *dev);
633static void free_ring(struct net_device *dev);
634static void reinit_ring(struct net_device *dev);
635static void init_registers(struct net_device *dev);
636static int start_tx(struct sk_buff *skb, struct net_device *dev);
7d12e780 637static irqreturn_t intr_handler(int irq, void *dev_instance);
1da177e4 638static void netdev_error(struct net_device *dev, int intr_status);
b27a16b7
MB		 639static int natsemi_poll(struct net_device *dev, int *budget);
640static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do);
1da177e4
LT		 641static void netdev_tx_done(struct net_device *dev);
642static int natsemi_change_mtu(struct net_device *dev, int new_mtu);
643#ifdef CONFIG_NET_POLL_CONTROLLER
644static void natsemi_poll_controller(struct net_device *dev);
645#endif
646static void __set_rx_mode(struct net_device *dev);
647static void set_rx_mode(struct net_device *dev);
648static void __get_stats(struct net_device *dev);
649static struct net_device_stats *get_stats(struct net_device *dev);
650static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
651static int netdev_set_wol(struct net_device *dev, u32 newval);
652static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur);
653static int netdev_set_sopass(struct net_device *dev, u8 *newval);
654static int netdev_get_sopass(struct net_device *dev, u8 *data);
655static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
656static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
657static void enable_wol_mode(struct net_device *dev, int enable_intr);
658static int netdev_close(struct net_device *dev);
659static int netdev_get_regs(struct net_device *dev, u8 *buf);
660static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
7282d491 661static const struct ethtool_ops ethtool_ops;
1da177e4 662
1a147809
MB		 663#define NATSEMI_ATTR(_name) \
664static ssize_t natsemi_show_##_name(struct device *dev, \
665 struct device_attribute *attr, char *buf); \
666 static ssize_t natsemi_set_##_name(struct device *dev, \
667 struct device_attribute *attr, \
668 const char *buf, size_t count); \
669 static DEVICE_ATTR(_name, 0644, natsemi_show_##_name, natsemi_set_##_name)
670
671#define NATSEMI_CREATE_FILE(_dev, _name) \
672 device_create_file(&_dev->dev, &dev_attr_##_name)
673#define NATSEMI_REMOVE_FILE(_dev, _name) \
f6c42865 674 device_remove_file(&_dev->dev, &dev_attr_##_name)
1a147809
MB		 675
676NATSEMI_ATTR(dspcfg_workaround);
677
678static ssize_t natsemi_show_dspcfg_workaround(struct device *dev,
679 struct device_attribute *attr,
680 char *buf)
681{
682 struct netdev_private *np = netdev_priv(to_net_dev(dev));
683
684 return sprintf(buf, "%s\n", np->dspcfg_workaround ? "on" : "off");
685}
686
687static ssize_t natsemi_set_dspcfg_workaround(struct device *dev,
688 struct device_attribute *attr,
689 const char *buf, size_t count)
690{
691 struct netdev_private *np = netdev_priv(to_net_dev(dev));
692 int new_setting;
d41f2d17 693 unsigned long flags;
1a147809
MB		 694
695 /* Find out the new setting */
696 if (!strncmp("on", buf, count - 1) || !strncmp("1", buf, count - 1))
697 new_setting = 1;
698 else if (!strncmp("off", buf, count - 1)
699 || !strncmp("0", buf, count - 1))
700 new_setting = 0;
701 else
702 return count;
703
704 spin_lock_irqsave(&np->lock, flags);
705
706 np->dspcfg_workaround = new_setting;
707
708 spin_unlock_irqrestore(&np->lock, flags);
709
710 return count;
711}
712
1da177e4
LT		 713static inline void __iomem *ns_ioaddr(struct net_device *dev)
714{
715 return (void __iomem *) dev->base_addr;
716}
717
b27a16b7
MB		 718static inline void natsemi_irq_enable(struct net_device *dev)
719{
720 writel(1, ns_ioaddr(dev) + IntrEnable);
721 readl(ns_ioaddr(dev) + IntrEnable);
722}
723
724static inline void natsemi_irq_disable(struct net_device *dev)
725{
726 writel(0, ns_ioaddr(dev) + IntrEnable);
727 readl(ns_ioaddr(dev) + IntrEnable);
728}
729
1da177e4
LT		 730static void move_int_phy(struct net_device *dev, int addr)
731{
732 struct netdev_private *np = netdev_priv(dev);
733 void __iomem *ioaddr = ns_ioaddr(dev);
734 int target = 31;
735
6aa20a22 736 /*
1da177e4
LT		 737 * The internal phy is visible on the external mii bus. Therefore we must
738 * move it away before we can send commands to an external phy.
739 * There are two addresses we must avoid:
740 * - the address on the external phy that is used for transmission.
741 * - the address that we want to access. User space can access phys
742 * on the mii bus with SIOCGMIIREG/SIOCSMIIREG, independant from the
743 * phy that is used for transmission.
744 */
745
746 if (target == addr)
747 target--;
748 if (target == np->phy_addr_external)
749 target--;
750 writew(target, ioaddr + PhyCtrl);
751 readw(ioaddr + PhyCtrl);
752 udelay(1);
753}
754
5a40f09b
JG		 755static void __devinit natsemi_init_media (struct net_device *dev)
756{
757 struct netdev_private *np = netdev_priv(dev);
758 u32 tmp;
759
68c90166
MB		 760 if (np->ignore_phy)
761 netif_carrier_on(dev);
762 else
763 netif_carrier_off(dev);
5a40f09b
JG		 764
765 /* get the initial settings from hardware */
766 tmp = mdio_read(dev, MII_BMCR);
767 np->speed = (tmp & BMCR_SPEED100)? SPEED_100 : SPEED_10;
768 np->duplex = (tmp & BMCR_FULLDPLX)? DUPLEX_FULL : DUPLEX_HALF;
769 np->autoneg = (tmp & BMCR_ANENABLE)? AUTONEG_ENABLE: AUTONEG_DISABLE;
770 np->advertising= mdio_read(dev, MII_ADVERTISE);
771
772 if ((np->advertising & ADVERTISE_ALL) != ADVERTISE_ALL
773 && netif_msg_probe(np)) {
774 printk(KERN_INFO "natsemi %s: Transceiver default autonegotiation %s "
775 "10%s %s duplex.\n",
776 pci_name(np->pci_dev),
777 (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE)?
778 "enabled, advertise" : "disabled, force",
779 (np->advertising &
780 (ADVERTISE_100FULL|ADVERTISE_100HALF))?
781 "0" : "",
782 (np->advertising &
783 (ADVERTISE_100FULL|ADVERTISE_10FULL))?
784 "full" : "half");
785 }
786 if (netif_msg_probe(np))
787 printk(KERN_INFO
788 "natsemi %s: Transceiver status %#04x advertising %#04x.\n",
789 pci_name(np->pci_dev), mdio_read(dev, MII_BMSR),
790 np->advertising);
791
792}
793
1da177e4
LT		 794static int __devinit natsemi_probe1 (struct pci_dev *pdev,
795 const struct pci_device_id *ent)
796{
797 struct net_device *dev;
798 struct netdev_private *np;
799 int i, option, irq, chip_idx = ent->driver_data;
800 static int find_cnt = -1;
801 unsigned long iostart, iosize;
802 void __iomem *ioaddr;
803 const int pcibar = 1; /* PCI base address register */
804 int prev_eedata;
805 u32 tmp;
806
807/* when built into the kernel, we only print version if device is found */
808#ifndef MODULE
809 static int printed_version;
810 if (!printed_version++)
811 printk(version);
812#endif
813
814 i = pci_enable_device(pdev);
815 if (i) return i;
816
817 /* natsemi has a non-standard PM control register
818 * in PCI config space. Some boards apparently need
819 * to be brought to D0 in this manner.
820 */
821 pci_read_config_dword(pdev, PCIPM, &tmp);
822 if (tmp & PCI_PM_CTRL_STATE_MASK) {
823 /* D0 state, disable PME assertion */
824 u32 newtmp = tmp & ~PCI_PM_CTRL_STATE_MASK;
825 pci_write_config_dword(pdev, PCIPM, newtmp);
826 }
827
828 find_cnt++;
829 iostart = pci_resource_start(pdev, pcibar);
830 iosize = pci_resource_len(pdev, pcibar);
831 irq = pdev->irq;
832
a2b524b2 833 pci_set_master(pdev);
1da177e4
LT		 834
835 dev = alloc_etherdev(sizeof (struct netdev_private));
836 if (!dev)
837 return -ENOMEM;
838 SET_MODULE_OWNER(dev);
839 SET_NETDEV_DEV(dev, &pdev->dev);
840
841 i = pci_request_regions(pdev, DRV_NAME);
842 if (i)
843 goto err_pci_request_regions;
844
845 ioaddr = ioremap(iostart, iosize);
846 if (!ioaddr) {
847 i = -ENOMEM;
848 goto err_ioremap;
849 }
850
851 /* Work around the dropped serial bit. */
852 prev_eedata = eeprom_read(ioaddr, 6);
853 for (i = 0; i < 3; i++) {
854 int eedata = eeprom_read(ioaddr, i + 7);
855 dev->dev_addr[i*2] = (eedata << 1) + (prev_eedata >> 15);
856 dev->dev_addr[i*2+1] = eedata >> 7;
857 prev_eedata = eedata;
858 }
859
860 dev->base_addr = (unsigned long __force) ioaddr;
861 dev->irq = irq;
862
863 np = netdev_priv(dev);
864
865 np->pci_dev = pdev;
866 pci_set_drvdata(pdev, dev);
867 np->iosize = iosize;
868 spin_lock_init(&np->lock);
869 np->msg_enable = (debug >= 0) ? (1<<debug)-1 : NATSEMI_DEF_MSG;
870 np->hands_off = 0;
b27a16b7 871 np->intr_status = 0;
a2b524b2 872 np->eeprom_size = natsemi_pci_info[chip_idx].eeprom_size;
6aab4447
MB		 873 if (natsemi_pci_info[chip_idx].flags & NATSEMI_FLAG_IGNORE_PHY)
874 np->ignore_phy = 1;
875 else
876 np->ignore_phy = 0;
1a147809 877 np->dspcfg_workaround = dspcfg_workaround;
1da177e4
LT		 878
879 /* Initial port:
68c90166 880 * - If configured to ignore the PHY set up for external.
1da177e4
LT		 881 * - If the nic was configured to use an external phy and if find_mii
882 * finds a phy: use external port, first phy that replies.
883 * - Otherwise: internal port.
884 * Note that the phy address for the internal phy doesn't matter:
885 * The address would be used to access a phy over the mii bus, but
886 * the internal phy is accessed through mapped registers.
887 */
68c90166 888 if (np->ignore_phy || readl(ioaddr + ChipConfig) & CfgExtPhy)
1da177e4
LT		 889 dev->if_port = PORT_MII;
890 else
891 dev->if_port = PORT_TP;
892 /* Reset the chip to erase previous misconfiguration. */
893 natsemi_reload_eeprom(dev);
894 natsemi_reset(dev);
895
896 if (dev->if_port != PORT_TP) {
897 np->phy_addr_external = find_mii(dev);
68c90166
MB		 898 /* If we're ignoring the PHY it doesn't matter if we can't
899 * find one. */
900 if (!np->ignore_phy && np->phy_addr_external == PHY_ADDR_NONE) {
1da177e4
LT		 901 dev->if_port = PORT_TP;
902 np->phy_addr_external = PHY_ADDR_INTERNAL;
903 }
904 } else {
905 np->phy_addr_external = PHY_ADDR_INTERNAL;
906 }
907
908 option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
909 if (dev->mem_start)
910 option = dev->mem_start;
911
912 /* The lower four bits are the media type. */
913 if (option) {
914 if (option & 0x200)
915 np->full_duplex = 1;
916 if (option & 15)
917 printk(KERN_INFO
918 "natsemi %s: ignoring user supplied media type %d",
919 pci_name(np->pci_dev), option & 15);
920 }
921 if (find_cnt < MAX_UNITS && full_duplex[find_cnt])
922 np->full_duplex = 1;
923
924 /* The chip-specific entries in the device structure. */
925 dev->open = &netdev_open;
926 dev->hard_start_xmit = &start_tx;
927 dev->stop = &netdev_close;
928 dev->get_stats = &get_stats;
929 dev->set_multicast_list = &set_rx_mode;
930 dev->change_mtu = &natsemi_change_mtu;
931 dev->do_ioctl = &netdev_ioctl;
932 dev->tx_timeout = &tx_timeout;
933 dev->watchdog_timeo = TX_TIMEOUT;
b27a16b7
MB		 934 dev->poll = natsemi_poll;
935 dev->weight = 64;
936
1da177e4
LT		 937#ifdef CONFIG_NET_POLL_CONTROLLER
938 dev->poll_controller = &natsemi_poll_controller;
939#endif
940 SET_ETHTOOL_OPS(dev, &ethtool_ops);
941
942 if (mtu)
943 dev->mtu = mtu;
944
5a40f09b 945 natsemi_init_media(dev);
1da177e4
LT		 946
947 /* save the silicon revision for later querying */
948 np->srr = readl(ioaddr + SiliconRev);
949 if (netif_msg_hw(np))
950 printk(KERN_INFO "natsemi %s: silicon revision %#04x.\n",
951 pci_name(np->pci_dev), np->srr);
952
953 i = register_netdev(dev);
954 if (i)
955 goto err_register_netdev;
956
1a147809
MB		 957 if (NATSEMI_CREATE_FILE(pdev, dspcfg_workaround))
958 goto err_create_file;
959
1da177e4
LT		 960 if (netif_msg_drv(np)) {
961 printk(KERN_INFO "natsemi %s: %s at %#08lx (%s), ",
962 dev->name, natsemi_pci_info[chip_idx].name, iostart,
963 pci_name(np->pci_dev));
964 for (i = 0; i < ETH_ALEN-1; i++)
965 printk("%02x:", dev->dev_addr[i]);
966 printk("%02x, IRQ %d", dev->dev_addr[i], irq);
967 if (dev->if_port == PORT_TP)
968 printk(", port TP.\n");
68c90166
MB		 969 else if (np->ignore_phy)
970 printk(", port MII, ignoring PHY\n");
1da177e4
LT		 971 else
972 printk(", port MII, phy ad %d.\n", np->phy_addr_external);
973 }
974 return 0;
975
1a147809
MB		 976 err_create_file:
977 unregister_netdev(dev);
978
1da177e4
LT		 979 err_register_netdev:
980 iounmap(ioaddr);
981
982 err_ioremap:
983 pci_release_regions(pdev);
984 pci_set_drvdata(pdev, NULL);
985
986 err_pci_request_regions:
987 free_netdev(dev);
988 return i;
989}
990
991
992/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces.
993 The EEPROM code is for the common 93c06/46 EEPROMs with 6 bit addresses. */
994
995/* Delay between EEPROM clock transitions.
996 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
997 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
998 made udelay() unreliable.
999 The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is
1000 depricated.
1001*/
1002#define eeprom_delay(ee_addr) readl(ee_addr)
1003
1004#define EE_Write0 (EE_ChipSelect)
1005#define EE_Write1 (EE_ChipSelect | EE_DataIn)
1006
1007/* The EEPROM commands include the alway-set leading bit. */
1008enum EEPROM_Cmds {
1009 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
1010};
1011
1012static int eeprom_read(void __iomem *addr, int location)
1013{
1014 int i;
1015 int retval = 0;
1016 void __iomem *ee_addr = addr + EECtrl;
1017 int read_cmd = location | EE_ReadCmd;
1018
1019 writel(EE_Write0, ee_addr);
1020
1021 /* Shift the read command bits out. */
1022 for (i = 10; i >= 0; i--) {
1023 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
1024 writel(dataval, ee_addr);
1025 eeprom_delay(ee_addr);
1026 writel(dataval | EE_ShiftClk, ee_addr);
1027 eeprom_delay(ee_addr);
1028 }
1029 writel(EE_ChipSelect, ee_addr);
1030 eeprom_delay(ee_addr);
1031
1032 for (i = 0; i < 16; i++) {
1033 writel(EE_ChipSelect | EE_ShiftClk, ee_addr);
1034 eeprom_delay(ee_addr);
1035 retval |= (readl(ee_addr) & EE_DataOut) ? 1 << i : 0;
1036 writel(EE_ChipSelect, ee_addr);
1037 eeprom_delay(ee_addr);
1038 }
1039
1040 /* Terminate the EEPROM access. */
1041 writel(EE_Write0, ee_addr);
1042 writel(0, ee_addr);
1043 return retval;
1044}
1045
1046/* MII transceiver control section.
1047 * The 83815 series has an internal transceiver, and we present the
1048 * internal management registers as if they were MII connected.
1049 * External Phy registers are referenced through the MII interface.
1050 */
1051
1052/* clock transitions >= 20ns (25MHz)
1053 * One readl should be good to PCI @ 100MHz
1054 */
1055#define mii_delay(ioaddr) readl(ioaddr + EECtrl)
1056
1057static int mii_getbit (struct net_device *dev)
1058{
1059 int data;
1060 void __iomem *ioaddr = ns_ioaddr(dev);
1061
1062 writel(MII_ShiftClk, ioaddr + EECtrl);
1063 data = readl(ioaddr + EECtrl);
1064 writel(0, ioaddr + EECtrl);
1065 mii_delay(ioaddr);
1066 return (data & MII_Data)? 1 : 0;
1067}
1068
1069static void mii_send_bits (struct net_device *dev, u32 data, int len)
1070{
1071 u32 i;
1072 void __iomem *ioaddr = ns_ioaddr(dev);
1073
1074 for (i = (1 << (len-1)); i; i >>= 1)
1075 {
1076 u32 mdio_val = MII_Write | ((data & i)? MII_Data : 0);
1077 writel(mdio_val, ioaddr + EECtrl);
1078 mii_delay(ioaddr);
1079 writel(mdio_val | MII_ShiftClk, ioaddr + EECtrl);
1080 mii_delay(ioaddr);
1081 }
1082 writel(0, ioaddr + EECtrl);
1083 mii_delay(ioaddr);
1084}
1085
1086static int miiport_read(struct net_device *dev, int phy_id, int reg)
1087{
1088 u32 cmd;
1089 int i;
1090 u32 retval = 0;
1091
1092 /* Ensure sync */
1093 mii_send_bits (dev, 0xffffffff, 32);
1094 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1095 /* ST,OP = 0110'b for read operation */
1096 cmd = (0x06 << 10) | (phy_id << 5) | reg;
1097 mii_send_bits (dev, cmd, 14);
1098 /* Turnaround */
1099 if (mii_getbit (dev))
1100 return 0;
1101 /* Read data */
1102 for (i = 0; i < 16; i++) {
1103 retval <<= 1;
1104 retval |= mii_getbit (dev);
1105 }
1106 /* End cycle */
1107 mii_getbit (dev);
1108 return retval;
1109}
1110
1111static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data)
1112{
1113 u32 cmd;
1114
1115 /* Ensure sync */
1116 mii_send_bits (dev, 0xffffffff, 32);
1117 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1118 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1119 cmd = (0x5002 << 16) | (phy_id << 23) | (reg << 18) | data;
1120 mii_send_bits (dev, cmd, 32);
1121 /* End cycle */
1122 mii_getbit (dev);
1123}
1124
1125static int mdio_read(struct net_device *dev, int reg)
1126{
1127 struct netdev_private *np = netdev_priv(dev);
1128 void __iomem *ioaddr = ns_ioaddr(dev);
1129
1130 /* The 83815 series has two ports:
1131 * - an internal transceiver
1132 * - an external mii bus
1133 */
1134 if (dev->if_port == PORT_TP)
1135 return readw(ioaddr+BasicControl+(reg<<2));
1136 else
1137 return miiport_read(dev, np->phy_addr_external, reg);
1138}
1139
1140static void mdio_write(struct net_device *dev, int reg, u16 data)
1141{
1142 struct netdev_private *np = netdev_priv(dev);
1143 void __iomem *ioaddr = ns_ioaddr(dev);
1144
1145 /* The 83815 series has an internal transceiver; handle separately */
1146 if (dev->if_port == PORT_TP)
1147 writew(data, ioaddr+BasicControl+(reg<<2));
1148 else
1149 miiport_write(dev, np->phy_addr_external, reg, data);
1150}
1151
1152static void init_phy_fixup(struct net_device *dev)
1153{
1154 struct netdev_private *np = netdev_priv(dev);
1155 void __iomem *ioaddr = ns_ioaddr(dev);
1156 int i;
1157 u32 cfg;
1158 u16 tmp;
1159
1160 /* restore stuff lost when power was out */
1161 tmp = mdio_read(dev, MII_BMCR);
1162 if (np->autoneg == AUTONEG_ENABLE) {
1163 /* renegotiate if something changed */
1164 if ((tmp & BMCR_ANENABLE) == 0
1165 || np->advertising != mdio_read(dev, MII_ADVERTISE))
1166 {
1167 /* turn on autonegotiation and force negotiation */
1168 tmp |= (BMCR_ANENABLE | BMCR_ANRESTART);
1169 mdio_write(dev, MII_ADVERTISE, np->advertising);
1170 }
1171 } else {
1172 /* turn off auto negotiation, set speed and duplexity */
1173 tmp &= ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX);
1174 if (np->speed == SPEED_100)
1175 tmp |= BMCR_SPEED100;
1176 if (np->duplex == DUPLEX_FULL)
1177 tmp |= BMCR_FULLDPLX;
6aa20a22 1178 /*
1da177e4
LT		 1179 * Note: there is no good way to inform the link partner
1180 * that our capabilities changed. The user has to unplug
1181 * and replug the network cable after some changes, e.g.
1182 * after switching from 10HD, autoneg off to 100 HD,
1183 * autoneg off.
1184 */
1185 }
1186 mdio_write(dev, MII_BMCR, tmp);
1187 readl(ioaddr + ChipConfig);
1188 udelay(1);
1189
1190 /* find out what phy this is */
1191 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1192 + mdio_read(dev, MII_PHYSID2);
1193
1194 /* handle external phys here */
1195 switch (np->mii) {
1196 case PHYID_AM79C874:
1197 /* phy specific configuration for fibre/tp operation */
1198 tmp = mdio_read(dev, MII_MCTRL);
1199 tmp &= ~(MII_FX_SEL | MII_EN_SCRM);
1200 if (dev->if_port == PORT_FIBRE)
1201 tmp |= MII_FX_SEL;
1202 else
1203 tmp |= MII_EN_SCRM;
1204 mdio_write(dev, MII_MCTRL, tmp);
1205 break;
1206 default:
1207 break;
1208 }
1209 cfg = readl(ioaddr + ChipConfig);
1210 if (cfg & CfgExtPhy)
1211 return;
1212
1213 /* On page 78 of the spec, they recommend some settings for "optimum
1214 performance" to be done in sequence. These settings optimize some
1215 of the 100Mbit autodetection circuitry. They say we only want to
1216 do this for rev C of the chip, but engineers at NSC (Bradley
1217 Kennedy) recommends always setting them. If you don't, you get
1218 errors on some autonegotiations that make the device unusable.
1219
1220 It seems that the DSP needs a few usec to reinitialize after
1221 the start of the phy. Just retry writing these values until they
1222 stick.
1223 */
1224 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1225
1226 int dspcfg;
1227 writew(1, ioaddr + PGSEL);
1228 writew(PMDCSR_VAL, ioaddr + PMDCSR);
1229 writew(TSTDAT_VAL, ioaddr + TSTDAT);
1230 np->dspcfg = (np->srr <= SRR_DP83815_C)?
1231 DSPCFG_VAL : (DSPCFG_COEF | readw(ioaddr + DSPCFG));
1232 writew(np->dspcfg, ioaddr + DSPCFG);
1233 writew(SDCFG_VAL, ioaddr + SDCFG);
1234 writew(0, ioaddr + PGSEL);
1235 readl(ioaddr + ChipConfig);
1236 udelay(10);
1237
1238 writew(1, ioaddr + PGSEL);
1239 dspcfg = readw(ioaddr + DSPCFG);
1240 writew(0, ioaddr + PGSEL);
1241 if (np->dspcfg == dspcfg)
1242 break;
1243 }
1244
1245 if (netif_msg_link(np)) {
1246 if (i==NATSEMI_HW_TIMEOUT) {
1247 printk(KERN_INFO
1248 "%s: DSPCFG mismatch after retrying for %d usec.\n",
1249 dev->name, i*10);
1250 } else {
1251 printk(KERN_INFO
1252 "%s: DSPCFG accepted after %d usec.\n",
1253 dev->name, i*10);
1254 }
1255 }
1256 /*
1257 * Enable PHY Specific event based interrupts. Link state change
1258 * and Auto-Negotiation Completion are among the affected.
1259 * Read the intr status to clear it (needed for wake events).
1260 */
1261 readw(ioaddr + MIntrStatus);
1262 writew(MICRIntEn, ioaddr + MIntrCtrl);
1263}
1264
1265static int switch_port_external(struct net_device *dev)
1266{
1267 struct netdev_private *np = netdev_priv(dev);
1268 void __iomem *ioaddr = ns_ioaddr(dev);
1269 u32 cfg;
1270
1271 cfg = readl(ioaddr + ChipConfig);
1272 if (cfg & CfgExtPhy)
1273 return 0;
1274
1275 if (netif_msg_link(np)) {
1276 printk(KERN_INFO "%s: switching to external transceiver.\n",
1277 dev->name);
1278 }
1279
1280 /* 1) switch back to external phy */
1281 writel(cfg | (CfgExtPhy | CfgPhyDis), ioaddr + ChipConfig);
1282 readl(ioaddr + ChipConfig);
1283 udelay(1);
1284
1285 /* 2) reset the external phy: */
1286 /* resetting the external PHY has been known to cause a hub supplying
1287 * power over Ethernet to kill the power. We don't want to kill
1288 * power to this computer, so we avoid resetting the phy.
1289 */
1290
1291 /* 3) reinit the phy fixup, it got lost during power down. */
1292 move_int_phy(dev, np->phy_addr_external);
1293 init_phy_fixup(dev);
1294
1295 return 1;
1296}
1297
1298static int switch_port_internal(struct net_device *dev)
1299{
1300 struct netdev_private *np = netdev_priv(dev);
1301 void __iomem *ioaddr = ns_ioaddr(dev);
1302 int i;
1303 u32 cfg;
1304 u16 bmcr;
1305
1306 cfg = readl(ioaddr + ChipConfig);
1307 if (!(cfg &CfgExtPhy))
1308 return 0;
1309
1310 if (netif_msg_link(np)) {
1311 printk(KERN_INFO "%s: switching to internal transceiver.\n",
1312 dev->name);
1313 }
1314 /* 1) switch back to internal phy: */
1315 cfg = cfg & ~(CfgExtPhy | CfgPhyDis);
1316 writel(cfg, ioaddr + ChipConfig);
1317 readl(ioaddr + ChipConfig);
1318 udelay(1);
6aa20a22 1319
1da177e4
LT		 1320 /* 2) reset the internal phy: */
1321 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1322 writel(bmcr | BMCR_RESET, ioaddr+BasicControl+(MII_BMCR<<2));
1323 readl(ioaddr + ChipConfig);
1324 udelay(10);
1325 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1326 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1327 if (!(bmcr & BMCR_RESET))
1328 break;
1329 udelay(10);
1330 }
1331 if (i==NATSEMI_HW_TIMEOUT && netif_msg_link(np)) {
1332 printk(KERN_INFO
1333 "%s: phy reset did not complete in %d usec.\n",
1334 dev->name, i*10);
1335 }
1336 /* 3) reinit the phy fixup, it got lost during power down. */
1337 init_phy_fixup(dev);
1338
1339 return 1;
1340}
1341
1342/* Scan for a PHY on the external mii bus.
1343 * There are two tricky points:
1344 * - Do not scan while the internal phy is enabled. The internal phy will
1345 * crash: e.g. reads from the DSPCFG register will return odd values and
1346 * the nasty random phy reset code will reset the nic every few seconds.
1347 * - The internal phy must be moved around, an external phy could
1348 * have the same address as the internal phy.
1349 */
1350static int find_mii(struct net_device *dev)
1351{
1352 struct netdev_private *np = netdev_priv(dev);
1353 int tmp;
1354 int i;
1355 int did_switch;
1356
1357 /* Switch to external phy */
1358 did_switch = switch_port_external(dev);
6aa20a22 1359
1da177e4
LT		 1360 /* Scan the possible phy addresses:
1361 *
1362 * PHY address 0 means that the phy is in isolate mode. Not yet
1363 * supported due to lack of test hardware. User space should
1364 * handle it through ethtool.
1365 */
1366 for (i = 1; i <= 31; i++) {
1367 move_int_phy(dev, i);
1368 tmp = miiport_read(dev, i, MII_BMSR);
1369 if (tmp != 0xffff && tmp != 0x0000) {
1370 /* found something! */
1371 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1372 + mdio_read(dev, MII_PHYSID2);
1373 if (netif_msg_probe(np)) {
1374 printk(KERN_INFO "natsemi %s: found external phy %08x at address %d.\n",
1375 pci_name(np->pci_dev), np->mii, i);
1376 }
1377 break;
1378 }
1379 }
1380 /* And switch back to internal phy: */
1381 if (did_switch)
1382 switch_port_internal(dev);
1383 return i;
1384}
1385
1386/* CFG bits [13:16] [18:23] */
1387#define CFG_RESET_SAVE 0xfde000
1388/* WCSR bits [0:4] [9:10] */
1389#define WCSR_RESET_SAVE 0x61f
1390/* RFCR bits [20] [22] [27:31] */
1391#define RFCR_RESET_SAVE 0xf8500000;
1392
1393static void natsemi_reset(struct net_device *dev)
1394{
1395 int i;
1396 u32 cfg;
1397 u32 wcsr;
1398 u32 rfcr;
1399 u16 pmatch[3];
1400 u16 sopass[3];
1401 struct netdev_private *np = netdev_priv(dev);
1402 void __iomem *ioaddr = ns_ioaddr(dev);
1403
1404 /*
1405 * Resetting the chip causes some registers to be lost.
1406 * Natsemi suggests NOT reloading the EEPROM while live, so instead
1407 * we save the state that would have been loaded from EEPROM
1408 * on a normal power-up (see the spec EEPROM map). This assumes
1409 * whoever calls this will follow up with init_registers() eventually.
1410 */
1411
1412 /* CFG */
1413 cfg = readl(ioaddr + ChipConfig) & CFG_RESET_SAVE;
1414 /* WCSR */
1415 wcsr = readl(ioaddr + WOLCmd) & WCSR_RESET_SAVE;
1416 /* RFCR */
1417 rfcr = readl(ioaddr + RxFilterAddr) & RFCR_RESET_SAVE;
1418 /* PMATCH */
1419 for (i = 0; i < 3; i++) {
1420 writel(i*2, ioaddr + RxFilterAddr);
1421 pmatch[i] = readw(ioaddr + RxFilterData);
1422 }
1423 /* SOPAS */
1424 for (i = 0; i < 3; i++) {
1425 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1426 sopass[i] = readw(ioaddr + RxFilterData);
1427 }
1428
1429 /* now whack the chip */
1430 writel(ChipReset, ioaddr + ChipCmd);
1431 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1432 if (!(readl(ioaddr + ChipCmd) & ChipReset))
1433 break;
1434 udelay(5);
1435 }
1436 if (i==NATSEMI_HW_TIMEOUT) {
1437 printk(KERN_WARNING "%s: reset did not complete in %d usec.\n",
1438 dev->name, i*5);
1439 } else if (netif_msg_hw(np)) {
1440 printk(KERN_DEBUG "%s: reset completed in %d usec.\n",
1441 dev->name, i*5);
1442 }
1443
1444 /* restore CFG */
1445 cfg |= readl(ioaddr + ChipConfig) & ~CFG_RESET_SAVE;
1446 /* turn on external phy if it was selected */
1447 if (dev->if_port == PORT_TP)
1448 cfg &= ~(CfgExtPhy | CfgPhyDis);
1449 else
1450 cfg |= (CfgExtPhy | CfgPhyDis);
1451 writel(cfg, ioaddr + ChipConfig);
1452 /* restore WCSR */
1453 wcsr |= readl(ioaddr + WOLCmd) & ~WCSR_RESET_SAVE;
1454 writel(wcsr, ioaddr + WOLCmd);
1455 /* read RFCR */
1456 rfcr |= readl(ioaddr + RxFilterAddr) & ~RFCR_RESET_SAVE;
1457 /* restore PMATCH */
1458 for (i = 0; i < 3; i++) {
1459 writel(i*2, ioaddr + RxFilterAddr);
1460 writew(pmatch[i], ioaddr + RxFilterData);
1461 }
1462 for (i = 0; i < 3; i++) {
1463 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1464 writew(sopass[i], ioaddr + RxFilterData);
1465 }
1466 /* restore RFCR */
1467 writel(rfcr, ioaddr + RxFilterAddr);
1468}
1469
e72fd96e
MB		 1470static void reset_rx(struct net_device *dev)
1471{
1472 int i;
1473 struct netdev_private *np = netdev_priv(dev);
1474 void __iomem *ioaddr = ns_ioaddr(dev);
1475
1476 np->intr_status &= ~RxResetDone;
1477
1478 writel(RxReset, ioaddr + ChipCmd);
1479
1480 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1481 np->intr_status |= readl(ioaddr + IntrStatus);
1482 if (np->intr_status & RxResetDone)
1483 break;
1484 udelay(15);
1485 }
1486 if (i==NATSEMI_HW_TIMEOUT) {
1487 printk(KERN_WARNING "%s: RX reset did not complete in %d usec.\n",
1488 dev->name, i*15);
1489 } else if (netif_msg_hw(np)) {
1490 printk(KERN_WARNING "%s: RX reset took %d usec.\n",
1491 dev->name, i*15);
1492 }
1493}
1494
1da177e4
LT		 1495static void natsemi_reload_eeprom(struct net_device *dev)
1496{
1497 struct netdev_private *np = netdev_priv(dev);
1498 void __iomem *ioaddr = ns_ioaddr(dev);
1499 int i;
1500
1501 writel(EepromReload, ioaddr + PCIBusCfg);
1502 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1503 udelay(50);
1504 if (!(readl(ioaddr + PCIBusCfg) & EepromReload))
1505 break;
1506 }
1507 if (i==NATSEMI_HW_TIMEOUT) {
1508 printk(KERN_WARNING "natsemi %s: EEPROM did not reload in %d usec.\n",
1509 pci_name(np->pci_dev), i*50);
1510 } else if (netif_msg_hw(np)) {
1511 printk(KERN_DEBUG "natsemi %s: EEPROM reloaded in %d usec.\n",
1512 pci_name(np->pci_dev), i*50);
1513 }
1514}
1515
1516static void natsemi_stop_rxtx(struct net_device *dev)
1517{
1518 void __iomem * ioaddr = ns_ioaddr(dev);
1519 struct netdev_private *np = netdev_priv(dev);
1520 int i;
1521
1522 writel(RxOff | TxOff, ioaddr + ChipCmd);
1523 for(i=0;i< NATSEMI_HW_TIMEOUT;i++) {
1524 if ((readl(ioaddr + ChipCmd) & (TxOn|RxOn)) == 0)
1525 break;
1526 udelay(5);
1527 }
1528 if (i==NATSEMI_HW_TIMEOUT) {
1529 printk(KERN_WARNING "%s: Tx/Rx process did not stop in %d usec.\n",
1530 dev->name, i*5);
1531 } else if (netif_msg_hw(np)) {
1532 printk(KERN_DEBUG "%s: Tx/Rx process stopped in %d usec.\n",
1533 dev->name, i*5);
1534 }
1535}
1536
1537static int netdev_open(struct net_device *dev)
1538{
1539 struct netdev_private *np = netdev_priv(dev);
1540 void __iomem * ioaddr = ns_ioaddr(dev);
1541 int i;
1542
1543 /* Reset the chip, just in case. */
1544 natsemi_reset(dev);
1545
1fb9df5d 1546 i = request_irq(dev->irq, &intr_handler, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 1547 if (i) return i;
1548
1549 if (netif_msg_ifup(np))
1550 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
1551 dev->name, dev->irq);
1552 i = alloc_ring(dev);
1553 if (i < 0) {
1554 free_irq(dev->irq, dev);
1555 return i;
1556 }
1557 init_ring(dev);
1558 spin_lock_irq(&np->lock);
1559 init_registers(dev);
1560 /* now set the MAC address according to dev->dev_addr */
1561 for (i = 0; i < 3; i++) {
1562 u16 mac = (dev->dev_addr[2*i+1]<<8) + dev->dev_addr[2*i];
1563
1564 writel(i*2, ioaddr + RxFilterAddr);
1565 writew(mac, ioaddr + RxFilterData);
1566 }
1567 writel(np->cur_rx_mode, ioaddr + RxFilterAddr);
1568 spin_unlock_irq(&np->lock);
1569
1570 netif_start_queue(dev);
1571
1572 if (netif_msg_ifup(np))
1573 printk(KERN_DEBUG "%s: Done netdev_open(), status: %#08x.\n",
1574 dev->name, (int)readl(ioaddr + ChipCmd));
1575
1576 /* Set the timer to check for link beat. */
1577 init_timer(&np->timer);
1578 np->timer.expires = jiffies + NATSEMI_TIMER_FREQ;
1579 np->timer.data = (unsigned long)dev;
1580 np->timer.function = &netdev_timer; /* timer handler */
1581 add_timer(&np->timer);
1582
1583 return 0;
1584}
1585
1586static void do_cable_magic(struct net_device *dev)
1587{
1588 struct netdev_private *np = netdev_priv(dev);
1589 void __iomem *ioaddr = ns_ioaddr(dev);
1590
1591 if (dev->if_port != PORT_TP)
1592 return;
1593
1594 if (np->srr >= SRR_DP83816_A5)
1595 return;
1596
1597 /*
1598 * 100 MBit links with short cables can trip an issue with the chip.
1599 * The problem manifests as lots of CRC errors and/or flickering
1600 * activity LED while idle. This process is based on instructions
1601 * from engineers at National.
1602 */
1603 if (readl(ioaddr + ChipConfig) & CfgSpeed100) {
1604 u16 data;
1605
1606 writew(1, ioaddr + PGSEL);
1607 /*
1608 * coefficient visibility should already be enabled via
1609 * DSPCFG | 0x1000
1610 */
1611 data = readw(ioaddr + TSTDAT) & 0xff;
1612 /*
1613 * the value must be negative, and within certain values
1614 * (these values all come from National)
1615 */
1616 if (!(data & 0x80) || ((data >= 0xd8) && (data <= 0xff))) {
1617 struct netdev_private *np = netdev_priv(dev);
1618
1619 /* the bug has been triggered - fix the coefficient */
1620 writew(TSTDAT_FIXED, ioaddr + TSTDAT);
1621 /* lock the value */
1622 data = readw(ioaddr + DSPCFG);
1623 np->dspcfg = data | DSPCFG_LOCK;
1624 writew(np->dspcfg, ioaddr + DSPCFG);
1625 }
1626 writew(0, ioaddr + PGSEL);
1627 }
1628}
1629
1630static void undo_cable_magic(struct net_device *dev)
1631{
1632 u16 data;
1633 struct netdev_private *np = netdev_priv(dev);
1634 void __iomem * ioaddr = ns_ioaddr(dev);
1635
1636 if (dev->if_port != PORT_TP)
1637 return;
1638
1639 if (np->srr >= SRR_DP83816_A5)
1640 return;
1641
1642 writew(1, ioaddr + PGSEL);
1643 /* make sure the lock bit is clear */
1644 data = readw(ioaddr + DSPCFG);
1645 np->dspcfg = data & ~DSPCFG_LOCK;
1646 writew(np->dspcfg, ioaddr + DSPCFG);
1647 writew(0, ioaddr + PGSEL);
1648}
1649
1650static void check_link(struct net_device *dev)
1651{
1652 struct netdev_private *np = netdev_priv(dev);
1653 void __iomem * ioaddr = ns_ioaddr(dev);
68c90166 1654 int duplex = np->duplex;
1da177e4 1655 u16 bmsr;
6aa20a22 1656
68c90166
MB		 1657 /* If we are ignoring the PHY then don't try reading it. */
1658 if (np->ignore_phy)
1659 goto propagate_state;
1660
1da177e4
LT		 1661 /* The link status field is latched: it remains low after a temporary
1662 * link failure until it's read. We need the current link status,
1663 * thus read twice.
1664 */
1665 mdio_read(dev, MII_BMSR);
1666 bmsr = mdio_read(dev, MII_BMSR);
1667
1668 if (!(bmsr & BMSR_LSTATUS)) {
1669 if (netif_carrier_ok(dev)) {
1670 if (netif_msg_link(np))
1671 printk(KERN_NOTICE "%s: link down.\n",
68c90166 1672 dev->name);
1da177e4
LT		 1673 netif_carrier_off(dev);
1674 undo_cable_magic(dev);
1675 }
1676 return;
1677 }
1678 if (!netif_carrier_ok(dev)) {
1679 if (netif_msg_link(np))
1680 printk(KERN_NOTICE "%s: link up.\n", dev->name);
1681 netif_carrier_on(dev);
1682 do_cable_magic(dev);
1683 }
1684
1685 duplex = np->full_duplex;
1686 if (!duplex) {
1687 if (bmsr & BMSR_ANEGCOMPLETE) {
1688 int tmp = mii_nway_result(
1689 np->advertising & mdio_read(dev, MII_LPA));
1690 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
1691 duplex = 1;
1692 } else if (mdio_read(dev, MII_BMCR) & BMCR_FULLDPLX)
1693 duplex = 1;
1694 }
1695
68c90166 1696propagate_state:
1da177e4
LT		 1697 /* if duplex is set then bit 28 must be set, too */
1698 if (duplex ^ !!(np->rx_config & RxAcceptTx)) {
1699 if (netif_msg_link(np))
1700 printk(KERN_INFO
1701 "%s: Setting %s-duplex based on negotiated "
1702 "link capability.\n", dev->name,
1703 duplex ? "full" : "half");
1704 if (duplex) {
1705 np->rx_config |= RxAcceptTx;
1706 np->tx_config |= TxCarrierIgn | TxHeartIgn;
1707 } else {
1708 np->rx_config &= ~RxAcceptTx;
1709 np->tx_config &= ~(TxCarrierIgn | TxHeartIgn);
1710 }
1711 writel(np->tx_config, ioaddr + TxConfig);
1712 writel(np->rx_config, ioaddr + RxConfig);
1713 }
1714}
1715
1716static void init_registers(struct net_device *dev)
1717{
1718 struct netdev_private *np = netdev_priv(dev);
1719 void __iomem * ioaddr = ns_ioaddr(dev);
1720
1721 init_phy_fixup(dev);
1722
1723 /* clear any interrupts that are pending, such as wake events */
1724 readl(ioaddr + IntrStatus);
1725
1726 writel(np->ring_dma, ioaddr + RxRingPtr);
1727 writel(np->ring_dma + RX_RING_SIZE * sizeof(struct netdev_desc),
1728 ioaddr + TxRingPtr);
1729
1730 /* Initialize other registers.
1731 * Configure the PCI bus bursts and FIFO thresholds.
1732 * Configure for standard, in-spec Ethernet.
1733 * Start with half-duplex. check_link will update
1734 * to the correct settings.
1735 */
1736
1737 /* DRTH: 2: start tx if 64 bytes are in the fifo
1738 * FLTH: 0x10: refill with next packet if 512 bytes are free
1739 * MXDMA: 0: up to 256 byte bursts.
1740 * MXDMA must be <= FLTH
1741 * ECRETRY=1
1742 * ATP=1
1743 */
1744 np->tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 |
1745 TX_FLTH_VAL | TX_DRTH_VAL_START;
1746 writel(np->tx_config, ioaddr + TxConfig);
1747
1748 /* DRTH 0x10: start copying to memory if 128 bytes are in the fifo
1749 * MXDMA 0: up to 256 byte bursts
1750 */
1751 np->rx_config = RxMxdma_256 | RX_DRTH_VAL;
1752 /* if receive ring now has bigger buffers than normal, enable jumbo */
1753 if (np->rx_buf_sz > NATSEMI_LONGPKT)
1754 np->rx_config |= RxAcceptLong;
1755
1756 writel(np->rx_config, ioaddr + RxConfig);
1757
1758 /* Disable PME:
1759 * The PME bit is initialized from the EEPROM contents.
1760 * PCI cards probably have PME disabled, but motherboard
1761 * implementations may have PME set to enable WakeOnLan.
1762 * With PME set the chip will scan incoming packets but
1763 * nothing will be written to memory. */
1764 np->SavedClkRun = readl(ioaddr + ClkRun);
1765 writel(np->SavedClkRun & ~PMEEnable, ioaddr + ClkRun);
1766 if (np->SavedClkRun & PMEStatus && netif_msg_wol(np)) {
1767 printk(KERN_NOTICE "%s: Wake-up event %#08x\n",
1768 dev->name, readl(ioaddr + WOLCmd));
1769 }
1770
1771 check_link(dev);
1772 __set_rx_mode(dev);
1773
1774 /* Enable interrupts by setting the interrupt mask. */
1775 writel(DEFAULT_INTR, ioaddr + IntrMask);
14fdd90e 1776 natsemi_irq_enable(dev);
1da177e4
LT		 1777
1778 writel(RxOn | TxOn, ioaddr + ChipCmd);
1779 writel(StatsClear, ioaddr + StatsCtrl); /* Clear Stats */
1780}
1781
1782/*
1783 * netdev_timer:
1784 * Purpose:
1785 * 1) check for link changes. Usually they are handled by the MII interrupt
1786 * but it doesn't hurt to check twice.
1787 * 2) check for sudden death of the NIC:
1788 * It seems that a reference set for this chip went out with incorrect info,
1789 * and there exist boards that aren't quite right. An unexpected voltage
1790 * drop can cause the PHY to get itself in a weird state (basically reset).
1a147809
MB		 1791 * NOTE: this only seems to affect revC chips. The user can disable
1792 * this check via dspcfg_workaround sysfs option.
1da177e4
LT		 1793 * 3) check of death of the RX path due to OOM
1794 */
1795static void netdev_timer(unsigned long data)
1796{
1797 struct net_device *dev = (struct net_device *)data;
1798 struct netdev_private *np = netdev_priv(dev);
1799 void __iomem * ioaddr = ns_ioaddr(dev);
1800 int next_tick = 5*HZ;
1801
1802 if (netif_msg_timer(np)) {
1803 /* DO NOT read the IntrStatus register,
1804 * a read clears any pending interrupts.
1805 */
1806 printk(KERN_DEBUG "%s: Media selection timer tick.\n",
1807 dev->name);
1808 }
1809
1810 if (dev->if_port == PORT_TP) {
1811 u16 dspcfg;
1812
1813 spin_lock_irq(&np->lock);
1814 /* check for a nasty random phy-reset - use dspcfg as a flag */
1815 writew(1, ioaddr+PGSEL);
1816 dspcfg = readw(ioaddr+DSPCFG);
1817 writew(0, ioaddr+PGSEL);
1a147809 1818 if (np->dspcfg_workaround && dspcfg != np->dspcfg) {
1da177e4
LT		 1819 if (!netif_queue_stopped(dev)) {
1820 spin_unlock_irq(&np->lock);
d0ed4864 1821 if (netif_msg_drv(np))
1da177e4
LT		 1822 printk(KERN_NOTICE "%s: possible phy reset: "
1823 "re-initializing\n", dev->name);
1824 disable_irq(dev->irq);
1825 spin_lock_irq(&np->lock);
1826 natsemi_stop_rxtx(dev);
1827 dump_ring(dev);
1828 reinit_ring(dev);
1829 init_registers(dev);
1830 spin_unlock_irq(&np->lock);
1831 enable_irq(dev->irq);
1832 } else {
1833 /* hurry back */
1834 next_tick = HZ;
1835 spin_unlock_irq(&np->lock);
1836 }
1837 } else {
1838 /* init_registers() calls check_link() for the above case */
1839 check_link(dev);
1840 spin_unlock_irq(&np->lock);
1841 }
1842 } else {
1843 spin_lock_irq(&np->lock);
1844 check_link(dev);
1845 spin_unlock_irq(&np->lock);
1846 }
1847 if (np->oom) {
1848 disable_irq(dev->irq);
1849 np->oom = 0;
1850 refill_rx(dev);
1851 enable_irq(dev->irq);
1852 if (!np->oom) {
1853 writel(RxOn, ioaddr + ChipCmd);
1854 } else {
1855 next_tick = 1;
1856 }
1857 }
1858 mod_timer(&np->timer, jiffies + next_tick);
1859}
1860
1861static void dump_ring(struct net_device *dev)
1862{
1863 struct netdev_private *np = netdev_priv(dev);
1864
1865 if (netif_msg_pktdata(np)) {
1866 int i;
1867 printk(KERN_DEBUG " Tx ring at %p:\n", np->tx_ring);
1868 for (i = 0; i < TX_RING_SIZE; i++) {
1869 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1870 i, np->tx_ring[i].next_desc,
1871 np->tx_ring[i].cmd_status,
1872 np->tx_ring[i].addr);
1873 }
1874 printk(KERN_DEBUG " Rx ring %p:\n", np->rx_ring);
1875 for (i = 0; i < RX_RING_SIZE; i++) {
1876 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1877 i, np->rx_ring[i].next_desc,
1878 np->rx_ring[i].cmd_status,
1879 np->rx_ring[i].addr);
1880 }
1881 }
1882}
1883
1884static void tx_timeout(struct net_device *dev)
1885{
1886 struct netdev_private *np = netdev_priv(dev);
1887 void __iomem * ioaddr = ns_ioaddr(dev);
1888
1889 disable_irq(dev->irq);
1890 spin_lock_irq(&np->lock);
1891 if (!np->hands_off) {
1892 if (netif_msg_tx_err(np))
1893 printk(KERN_WARNING
1894 "%s: Transmit timed out, status %#08x,"
1895 " resetting...\n",
1896 dev->name, readl(ioaddr + IntrStatus));
1897 dump_ring(dev);
1898
1899 natsemi_reset(dev);
1900 reinit_ring(dev);
1901 init_registers(dev);
1902 } else {
1903 printk(KERN_WARNING
1904 "%s: tx_timeout while in hands_off state?\n",
1905 dev->name);
1906 }
1907 spin_unlock_irq(&np->lock);
1908 enable_irq(dev->irq);
1909
1910 dev->trans_start = jiffies;
1911 np->stats.tx_errors++;
1912 netif_wake_queue(dev);
1913}
1914
1915static int alloc_ring(struct net_device *dev)
1916{
1917 struct netdev_private *np = netdev_priv(dev);
1918 np->rx_ring = pci_alloc_consistent(np->pci_dev,
1919 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
1920 &np->ring_dma);
1921 if (!np->rx_ring)
1922 return -ENOMEM;
1923 np->tx_ring = &np->rx_ring[RX_RING_SIZE];
1924 return 0;
1925}
1926
1927static void refill_rx(struct net_device *dev)
1928{
1929 struct netdev_private *np = netdev_priv(dev);
1930
1931 /* Refill the Rx ring buffers. */
1932 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1933 struct sk_buff *skb;
1934 int entry = np->dirty_rx % RX_RING_SIZE;
1935 if (np->rx_skbuff[entry] == NULL) {
1936 unsigned int buflen = np->rx_buf_sz+NATSEMI_PADDING;
1937 skb = dev_alloc_skb(buflen);
1938 np->rx_skbuff[entry] = skb;
1939 if (skb == NULL)
1940 break; /* Better luck next round. */
1941 skb->dev = dev; /* Mark as being used by this device. */
1942 np->rx_dma[entry] = pci_map_single(np->pci_dev,
689be439 1943 skb->data, buflen, PCI_DMA_FROMDEVICE);
1da177e4
LT		 1944 np->rx_ring[entry].addr = cpu_to_le32(np->rx_dma[entry]);
1945 }
1946 np->rx_ring[entry].cmd_status = cpu_to_le32(np->rx_buf_sz);
1947 }
1948 if (np->cur_rx - np->dirty_rx == RX_RING_SIZE) {
1949 if (netif_msg_rx_err(np))
1950 printk(KERN_WARNING "%s: going OOM.\n", dev->name);
1951 np->oom = 1;
1952 }
1953}
1954
1955static void set_bufsize(struct net_device *dev)
1956{
1957 struct netdev_private *np = netdev_priv(dev);
1958 if (dev->mtu <= ETH_DATA_LEN)
1959 np->rx_buf_sz = ETH_DATA_LEN + NATSEMI_HEADERS;
1960 else
1961 np->rx_buf_sz = dev->mtu + NATSEMI_HEADERS;
1962}
1963
1964/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1965static void init_ring(struct net_device *dev)
1966{
1967 struct netdev_private *np = netdev_priv(dev);
1968 int i;
1969
1970 /* 1) TX ring */
1971 np->dirty_tx = np->cur_tx = 0;
1972 for (i = 0; i < TX_RING_SIZE; i++) {
1973 np->tx_skbuff[i] = NULL;
1974 np->tx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1975 +sizeof(struct netdev_desc)
1976 *((i+1)%TX_RING_SIZE+RX_RING_SIZE));
1977 np->tx_ring[i].cmd_status = 0;
1978 }
1979
1980 /* 2) RX ring */
1981 np->dirty_rx = 0;
1982 np->cur_rx = RX_RING_SIZE;
1983 np->oom = 0;
1984 set_bufsize(dev);
1985
1986 np->rx_head_desc = &np->rx_ring[0];
1987
1988 /* Please be carefull before changing this loop - at least gcc-2.95.1
1989 * miscompiles it otherwise.
1990 */
1991 /* Initialize all Rx descriptors. */
1992 for (i = 0; i < RX_RING_SIZE; i++) {
1993 np->rx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1994 +sizeof(struct netdev_desc)
1995 *((i+1)%RX_RING_SIZE));
1996 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
1997 np->rx_skbuff[i] = NULL;
1998 }
1999 refill_rx(dev);
2000 dump_ring(dev);
2001}
2002
2003static void drain_tx(struct net_device *dev)
2004{
2005 struct netdev_private *np = netdev_priv(dev);
2006 int i;
2007
2008 for (i = 0; i < TX_RING_SIZE; i++) {
2009 if (np->tx_skbuff[i]) {
2010 pci_unmap_single(np->pci_dev,
2011 np->tx_dma[i], np->tx_skbuff[i]->len,
2012 PCI_DMA_TODEVICE);
2013 dev_kfree_skb(np->tx_skbuff[i]);
2014 np->stats.tx_dropped++;
2015 }
2016 np->tx_skbuff[i] = NULL;
2017 }
2018}
2019
2020static void drain_rx(struct net_device *dev)
2021{
2022 struct netdev_private *np = netdev_priv(dev);
2023 unsigned int buflen = np->rx_buf_sz;
2024 int i;
2025
2026 /* Free all the skbuffs in the Rx queue. */
2027 for (i = 0; i < RX_RING_SIZE; i++) {
2028 np->rx_ring[i].cmd_status = 0;
2029 np->rx_ring[i].addr = 0xBADF00D0; /* An invalid address. */
2030 if (np->rx_skbuff[i]) {
2031 pci_unmap_single(np->pci_dev,
2032 np->rx_dma[i], buflen,
2033 PCI_DMA_FROMDEVICE);
2034 dev_kfree_skb(np->rx_skbuff[i]);
2035 }
2036 np->rx_skbuff[i] = NULL;
2037 }
2038}
2039
2040static void drain_ring(struct net_device *dev)
2041{
2042 drain_rx(dev);
2043 drain_tx(dev);
2044}
2045
2046static void free_ring(struct net_device *dev)
2047{
2048 struct netdev_private *np = netdev_priv(dev);
2049 pci_free_consistent(np->pci_dev,
2050 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
2051 np->rx_ring, np->ring_dma);
2052}
2053
2054static void reinit_rx(struct net_device *dev)
2055{
2056 struct netdev_private *np = netdev_priv(dev);
2057 int i;
2058
2059 /* RX Ring */
2060 np->dirty_rx = 0;
2061 np->cur_rx = RX_RING_SIZE;
2062 np->rx_head_desc = &np->rx_ring[0];
2063 /* Initialize all Rx descriptors. */
2064 for (i = 0; i < RX_RING_SIZE; i++)
2065 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
2066
2067 refill_rx(dev);
2068}
2069
2070static void reinit_ring(struct net_device *dev)
2071{
2072 struct netdev_private *np = netdev_priv(dev);
2073 int i;
2074
2075 /* drain TX ring */
2076 drain_tx(dev);
2077 np->dirty_tx = np->cur_tx = 0;
2078 for (i=0;i<TX_RING_SIZE;i++)
2079 np->tx_ring[i].cmd_status = 0;
2080
2081 reinit_rx(dev);
2082}
2083
2084static int start_tx(struct sk_buff *skb, struct net_device *dev)
2085{
2086 struct netdev_private *np = netdev_priv(dev);
2087 void __iomem * ioaddr = ns_ioaddr(dev);
2088 unsigned entry;
6006f7f5 2089 unsigned long flags;
1da177e4
LT		 2090
2091 /* Note: Ordering is important here, set the field with the
2092 "ownership" bit last, and only then increment cur_tx. */
2093
2094 /* Calculate the next Tx descriptor entry. */
2095 entry = np->cur_tx % TX_RING_SIZE;
2096
2097 np->tx_skbuff[entry] = skb;
2098 np->tx_dma[entry] = pci_map_single(np->pci_dev,
2099 skb->data,skb->len, PCI_DMA_TODEVICE);
2100
2101 np->tx_ring[entry].addr = cpu_to_le32(np->tx_dma[entry]);
2102
6006f7f5 2103 spin_lock_irqsave(&np->lock, flags);
1da177e4
LT		 2104
2105 if (!np->hands_off) {
2106 np->tx_ring[entry].cmd_status = cpu_to_le32(DescOwn | skb->len);
2107 /* StrongARM: Explicitly cache flush np->tx_ring and
2108 * skb->data,skb->len. */
2109 wmb();
2110 np->cur_tx++;
2111 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1) {
2112 netdev_tx_done(dev);
2113 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1)
2114 netif_stop_queue(dev);
2115 }
2116 /* Wake the potentially-idle transmit channel. */
2117 writel(TxOn, ioaddr + ChipCmd);
2118 } else {
2119 dev_kfree_skb_irq(skb);
2120 np->stats.tx_dropped++;
2121 }
6006f7f5 2122 spin_unlock_irqrestore(&np->lock, flags);
1da177e4
LT		 2123
2124 dev->trans_start = jiffies;
2125
2126 if (netif_msg_tx_queued(np)) {
2127 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
2128 dev->name, np->cur_tx, entry);
2129 }
2130 return 0;
2131}
2132
2133static void netdev_tx_done(struct net_device *dev)
2134{
2135 struct netdev_private *np = netdev_priv(dev);
2136
2137 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
2138 int entry = np->dirty_tx % TX_RING_SIZE;
2139 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescOwn))
2140 break;
2141 if (netif_msg_tx_done(np))
2142 printk(KERN_DEBUG
2143 "%s: tx frame #%d finished, status %#08x.\n",
2144 dev->name, np->dirty_tx,
2145 le32_to_cpu(np->tx_ring[entry].cmd_status));
2146 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescPktOK)) {
2147 np->stats.tx_packets++;
2148 np->stats.tx_bytes += np->tx_skbuff[entry]->len;
2149 } else { /* Various Tx errors */
2150 int tx_status =
2151 le32_to_cpu(np->tx_ring[entry].cmd_status);
2152 if (tx_status & (DescTxAbort|DescTxExcColl))
2153 np->stats.tx_aborted_errors++;
2154 if (tx_status & DescTxFIFO)
2155 np->stats.tx_fifo_errors++;
2156 if (tx_status & DescTxCarrier)
2157 np->stats.tx_carrier_errors++;
2158 if (tx_status & DescTxOOWCol)
2159 np->stats.tx_window_errors++;
2160 np->stats.tx_errors++;
2161 }
2162 pci_unmap_single(np->pci_dev,np->tx_dma[entry],
2163 np->tx_skbuff[entry]->len,
2164 PCI_DMA_TODEVICE);
2165 /* Free the original skb. */
2166 dev_kfree_skb_irq(np->tx_skbuff[entry]);
2167 np->tx_skbuff[entry] = NULL;
2168 }
2169 if (netif_queue_stopped(dev)
2170 && np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
2171 /* The ring is no longer full, wake queue. */
2172 netif_wake_queue(dev);
2173 }
2174}
2175
b27a16b7
MB		 2176/* The interrupt handler doesn't actually handle interrupts itself, it
2177 * schedules a NAPI poll if there is anything to do. */
7d12e780 2178static irqreturn_t intr_handler(int irq, void *dev_instance)
1da177e4
LT		 2179{
2180 struct net_device *dev = dev_instance;
2181 struct netdev_private *np = netdev_priv(dev);
2182 void __iomem * ioaddr = ns_ioaddr(dev);
1da177e4 2183
069f8256 2184 /* Reading IntrStatus automatically acknowledges so don't do
2185 * that while interrupts are disabled, (for example, while a
2186 * poll is scheduled). */
2187 if (np->hands_off || !readl(ioaddr + IntrEnable))
1da177e4 2188 return IRQ_NONE;
6aa20a22 2189
b27a16b7 2190 np->intr_status = readl(ioaddr + IntrStatus);
1da177e4 2191
069f8256 2192 if (!np->intr_status)
2193 return IRQ_NONE;
2194
b27a16b7
MB		 2195 if (netif_msg_intr(np))
2196 printk(KERN_DEBUG
2197 "%s: Interrupt, status %#08x, mask %#08x.\n",
2198 dev->name, np->intr_status,
2199 readl(ioaddr + IntrMask));
1da177e4 2200
b27a16b7
MB		 2201 prefetch(&np->rx_skbuff[np->cur_rx % RX_RING_SIZE]);
2202
2203 if (netif_rx_schedule_prep(dev)) {
2204 /* Disable interrupts and register for poll */
2205 natsemi_irq_disable(dev);
2206 __netif_rx_schedule(dev);
069f8256 2207 } else
2208 printk(KERN_WARNING
2209 "%s: Ignoring interrupt, status %#08x, mask %#08x.\n",
2210 dev->name, np->intr_status,
2211 readl(ioaddr + IntrMask));
2212
b27a16b7
MB		 2213 return IRQ_HANDLED;
2214}
2215
2216/* This is the NAPI poll routine. As well as the standard RX handling
2217 * it also handles all other interrupts that the chip might raise.
2218 */
2219static int natsemi_poll(struct net_device *dev, int *budget)
2220{
2221 struct netdev_private *np = netdev_priv(dev);
2222 void __iomem * ioaddr = ns_ioaddr(dev);
1da177e4 2223
b27a16b7
MB		 2224 int work_to_do = min(*budget, dev->quota);
2225 int work_done = 0;
2226
2227 do {
069f8256 2228 if (netif_msg_intr(np))
2229 printk(KERN_DEBUG
2230 "%s: Poll, status %#08x, mask %#08x.\n",
2231 dev->name, np->intr_status,
2232 readl(ioaddr + IntrMask));
2233
d2a90036 2234 /* netdev_rx() may read IntrStatus again if the RX state
2235 * machine falls over so do it first. */
2236 if (np->intr_status &
2237 (IntrRxDone | IntrRxIntr | RxStatusFIFOOver |
2238 IntrRxErr | IntrRxOverrun)) {
2239 netdev_rx(dev, &work_done, work_to_do);
2240 }
2241
b27a16b7
MB		 2242 if (np->intr_status &
2243 (IntrTxDone | IntrTxIntr | IntrTxIdle | IntrTxErr)) {
1da177e4
LT		 2244 spin_lock(&np->lock);
2245 netdev_tx_done(dev);
2246 spin_unlock(&np->lock);
2247 }
2248
2249 /* Abnormal error summary/uncommon events handlers. */
b27a16b7
MB		 2250 if (np->intr_status & IntrAbnormalSummary)
2251 netdev_error(dev, np->intr_status);
6aa20a22 2252
b27a16b7
MB		 2253 *budget -= work_done;
2254 dev->quota -= work_done;
1da177e4 2255
b27a16b7
MB		 2256 if (work_done >= work_to_do)
2257 return 1;
2258
2259 np->intr_status = readl(ioaddr + IntrStatus);
2260 } while (np->intr_status);
1da177e4 2261
b27a16b7
MB		 2262 netif_rx_complete(dev);
2263
2264 /* Reenable interrupts providing nothing is trying to shut
2265 * the chip down. */
2266 spin_lock(&np->lock);
2267 if (!np->hands_off && netif_running(dev))
2268 natsemi_irq_enable(dev);
2269 spin_unlock(&np->lock);
2270
2271 return 0;
1da177e4
LT		 2272}
2273
2274/* This routine is logically part of the interrupt handler, but separated
2275 for clarity and better register allocation. */
b27a16b7 2276static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do)
1da177e4
LT		 2277{
2278 struct netdev_private *np = netdev_priv(dev);
2279 int entry = np->cur_rx % RX_RING_SIZE;
2280 int boguscnt = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
2281 s32 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2282 unsigned int buflen = np->rx_buf_sz;
2283 void __iomem * ioaddr = ns_ioaddr(dev);
2284
2285 /* If the driver owns the next entry it's a new packet. Send it up. */
2286 while (desc_status < 0) { /* e.g. & DescOwn */
2287 int pkt_len;
2288 if (netif_msg_rx_status(np))
2289 printk(KERN_DEBUG
2290 " netdev_rx() entry %d status was %#08x.\n",
2291 entry, desc_status);
2292 if (--boguscnt < 0)
2293 break;
b27a16b7
MB		 2294
2295 if (*work_done >= work_to_do)
2296 break;
2297
2298 (*work_done)++;
2299
1da177e4
LT		 2300 pkt_len = (desc_status & DescSizeMask) - 4;
2301 if ((desc_status&(DescMore|DescPktOK|DescRxLong)) != DescPktOK){
2302 if (desc_status & DescMore) {
6006f7f5
SS		 2303 unsigned long flags;
2304
1da177e4
LT		 2305 if (netif_msg_rx_err(np))
2306 printk(KERN_WARNING
2307 "%s: Oversized(?) Ethernet "
2308 "frame spanned multiple "
2309 "buffers, entry %#08x "
2310 "status %#08x.\n", dev->name,
2311 np->cur_rx, desc_status);
2312 np->stats.rx_length_errors++;
e72fd96e
MB		 2313
2314 /* The RX state machine has probably
2315 * locked up beneath us. Follow the
2316 * reset procedure documented in
2317 * AN-1287. */
2318
6006f7f5 2319 spin_lock_irqsave(&np->lock, flags);
e72fd96e
MB		 2320 reset_rx(dev);
2321 reinit_rx(dev);
2322 writel(np->ring_dma, ioaddr + RxRingPtr);
2323 check_link(dev);
6006f7f5 2324 spin_unlock_irqrestore(&np->lock, flags);
e72fd96e
MB		 2325
2326 /* We'll enable RX on exit from this
2327 * function. */
2328 break;
2329
1da177e4
LT		 2330 } else {
2331 /* There was an error. */
2332 np->stats.rx_errors++;
2333 if (desc_status & (DescRxAbort|DescRxOver))
2334 np->stats.rx_over_errors++;
2335 if (desc_status & (DescRxLong|DescRxRunt))
2336 np->stats.rx_length_errors++;
2337 if (desc_status & (DescRxInvalid|DescRxAlign))
2338 np->stats.rx_frame_errors++;
2339 if (desc_status & DescRxCRC)
2340 np->stats.rx_crc_errors++;
2341 }
2342 } else if (pkt_len > np->rx_buf_sz) {
2343 /* if this is the tail of a double buffer
2344 * packet, we've already counted the error
2345 * on the first part. Ignore the second half.
2346 */
2347 } else {
2348 struct sk_buff *skb;
2349 /* Omit CRC size. */
2350 /* Check if the packet is long enough to accept
2351 * without copying to a minimally-sized skbuff. */
2352 if (pkt_len < rx_copybreak
2353 && (skb = dev_alloc_skb(pkt_len + RX_OFFSET)) != NULL) {
1da177e4
LT		 2354 /* 16 byte align the IP header */
2355 skb_reserve(skb, RX_OFFSET);
2356 pci_dma_sync_single_for_cpu(np->pci_dev,
2357 np->rx_dma[entry],
2358 buflen,
2359 PCI_DMA_FROMDEVICE);
8c7b7faa
DM		 2360 skb_copy_to_linear_data(skb,
2361 np->rx_skbuff[entry]->data, pkt_len);
1da177e4
LT		 2362 skb_put(skb, pkt_len);
2363 pci_dma_sync_single_for_device(np->pci_dev,
2364 np->rx_dma[entry],
2365 buflen,
2366 PCI_DMA_FROMDEVICE);
2367 } else {
2368 pci_unmap_single(np->pci_dev, np->rx_dma[entry],
2369 buflen, PCI_DMA_FROMDEVICE);
2370 skb_put(skb = np->rx_skbuff[entry], pkt_len);
2371 np->rx_skbuff[entry] = NULL;
2372 }
2373 skb->protocol = eth_type_trans(skb, dev);
b27a16b7 2374 netif_receive_skb(skb);
1da177e4
LT		 2375 dev->last_rx = jiffies;
2376 np->stats.rx_packets++;
2377 np->stats.rx_bytes += pkt_len;
2378 }
2379 entry = (++np->cur_rx) % RX_RING_SIZE;
2380 np->rx_head_desc = &np->rx_ring[entry];
2381 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2382 }
2383 refill_rx(dev);
2384
2385 /* Restart Rx engine if stopped. */
2386 if (np->oom)
2387 mod_timer(&np->timer, jiffies + 1);
2388 else
2389 writel(RxOn, ioaddr + ChipCmd);
2390}
2391
2392static void netdev_error(struct net_device *dev, int intr_status)
2393{
2394 struct netdev_private *np = netdev_priv(dev);
2395 void __iomem * ioaddr = ns_ioaddr(dev);
2396
2397 spin_lock(&np->lock);
2398 if (intr_status & LinkChange) {
2399 u16 lpa = mdio_read(dev, MII_LPA);
2400 if (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE
2401 && netif_msg_link(np)) {
2402 printk(KERN_INFO
2403 "%s: Autonegotiation advertising"
2404 " %#04x partner %#04x.\n", dev->name,
2405 np->advertising, lpa);
2406 }
2407
2408 /* read MII int status to clear the flag */
2409 readw(ioaddr + MIntrStatus);
2410 check_link(dev);
2411 }
2412 if (intr_status & StatsMax) {
2413 __get_stats(dev);
2414 }
2415 if (intr_status & IntrTxUnderrun) {
2416 if ((np->tx_config & TxDrthMask) < TX_DRTH_VAL_LIMIT) {
2417 np->tx_config += TX_DRTH_VAL_INC;
2418 if (netif_msg_tx_err(np))
2419 printk(KERN_NOTICE
2420 "%s: increased tx threshold, txcfg %#08x.\n",
2421 dev->name, np->tx_config);
2422 } else {
2423 if (netif_msg_tx_err(np))
2424 printk(KERN_NOTICE
2425 "%s: tx underrun with maximum tx threshold, txcfg %#08x.\n",
2426 dev->name, np->tx_config);
2427 }
2428 writel(np->tx_config, ioaddr + TxConfig);
2429 }
2430 if (intr_status & WOLPkt && netif_msg_wol(np)) {
2431 int wol_status = readl(ioaddr + WOLCmd);
2432 printk(KERN_NOTICE "%s: Link wake-up event %#08x\n",
2433 dev->name, wol_status);
2434 }
2435 if (intr_status & RxStatusFIFOOver) {
2436 if (netif_msg_rx_err(np) && netif_msg_intr(np)) {
2437 printk(KERN_NOTICE "%s: Rx status FIFO overrun\n",
2438 dev->name);
2439 }
2440 np->stats.rx_fifo_errors++;
c76720cf 2441 np->stats.rx_errors++;
1da177e4
LT		 2442 }
2443 /* Hmmmmm, it's not clear how to recover from PCI faults. */
2444 if (intr_status & IntrPCIErr) {
2445 printk(KERN_NOTICE "%s: PCI error %#08x\n", dev->name,
2446 intr_status & IntrPCIErr);
2447 np->stats.tx_fifo_errors++;
c76720cf 2448 np->stats.tx_errors++;
1da177e4 2449 np->stats.rx_fifo_errors++;
c76720cf 2450 np->stats.rx_errors++;
1da177e4
LT		 2451 }
2452 spin_unlock(&np->lock);
2453}
2454
2455static void __get_stats(struct net_device *dev)
2456{
2457 void __iomem * ioaddr = ns_ioaddr(dev);
2458 struct netdev_private *np = netdev_priv(dev);
2459
2460 /* The chip only need report frame silently dropped. */
2461 np->stats.rx_crc_errors += readl(ioaddr + RxCRCErrs);
2462 np->stats.rx_missed_errors += readl(ioaddr + RxMissed);
2463}
2464
2465static struct net_device_stats *get_stats(struct net_device *dev)
2466{
2467 struct netdev_private *np = netdev_priv(dev);
2468
2469 /* The chip only need report frame silently dropped. */
2470 spin_lock_irq(&np->lock);
2471 if (netif_running(dev) && !np->hands_off)
2472 __get_stats(dev);
2473 spin_unlock_irq(&np->lock);
2474
2475 return &np->stats;
2476}
2477
2478#ifdef CONFIG_NET_POLL_CONTROLLER
2479static void natsemi_poll_controller(struct net_device *dev)
2480{
2481 disable_irq(dev->irq);
069f8256 2482 intr_handler(dev->irq, dev);
1da177e4
LT		 2483 enable_irq(dev->irq);
2484}
2485#endif
2486
2487#define HASH_TABLE 0x200
2488static void __set_rx_mode(struct net_device *dev)
2489{
2490 void __iomem * ioaddr = ns_ioaddr(dev);
2491 struct netdev_private *np = netdev_priv(dev);
2492 u8 mc_filter[64]; /* Multicast hash filter */
2493 u32 rx_mode;
2494
2495 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1da177e4
LT		 2496 rx_mode = RxFilterEnable | AcceptBroadcast
2497 | AcceptAllMulticast | AcceptAllPhys | AcceptMyPhys;
2498 } else if ((dev->mc_count > multicast_filter_limit)
2499 || (dev->flags & IFF_ALLMULTI)) {
2500 rx_mode = RxFilterEnable | AcceptBroadcast
2501 | AcceptAllMulticast | AcceptMyPhys;
2502 } else {
2503 struct dev_mc_list *mclist;
2504 int i;
2505 memset(mc_filter, 0, sizeof(mc_filter));
2506 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2507 i++, mclist = mclist->next) {
2508 int i = (ether_crc(ETH_ALEN, mclist->dmi_addr) >> 23) & 0x1ff;
2509 mc_filter[i/8] |= (1 << (i & 0x07));
2510 }
2511 rx_mode = RxFilterEnable | AcceptBroadcast
2512 | AcceptMulticast | AcceptMyPhys;
2513 for (i = 0; i < 64; i += 2) {
760f86d7
HX		 2514 writel(HASH_TABLE + i, ioaddr + RxFilterAddr);
2515 writel((mc_filter[i + 1] << 8) + mc_filter[i],
2516 ioaddr + RxFilterData);
1da177e4
LT		 2517 }
2518 }
2519 writel(rx_mode, ioaddr + RxFilterAddr);
2520 np->cur_rx_mode = rx_mode;
2521}
2522
2523static int natsemi_change_mtu(struct net_device *dev, int new_mtu)
2524{
2525 if (new_mtu < 64 || new_mtu > NATSEMI_RX_LIMIT-NATSEMI_HEADERS)
2526 return -EINVAL;
2527
2528 dev->mtu = new_mtu;
2529
2530 /* synchronized against open : rtnl_lock() held by caller */
2531 if (netif_running(dev)) {
2532 struct netdev_private *np = netdev_priv(dev);
2533 void __iomem * ioaddr = ns_ioaddr(dev);
2534
2535 disable_irq(dev->irq);
2536 spin_lock(&np->lock);
2537 /* stop engines */
2538 natsemi_stop_rxtx(dev);
2539 /* drain rx queue */
2540 drain_rx(dev);
2541 /* change buffers */
2542 set_bufsize(dev);
2543 reinit_rx(dev);
2544 writel(np->ring_dma, ioaddr + RxRingPtr);
2545 /* restart engines */
2546 writel(RxOn | TxOn, ioaddr + ChipCmd);
2547 spin_unlock(&np->lock);
2548 enable_irq(dev->irq);
2549 }
2550 return 0;
2551}
2552
2553static void set_rx_mode(struct net_device *dev)
2554{
2555 struct netdev_private *np = netdev_priv(dev);
2556 spin_lock_irq(&np->lock);
2557 if (!np->hands_off)
2558 __set_rx_mode(dev);
2559 spin_unlock_irq(&np->lock);
2560}
2561
2562static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2563{
2564 struct netdev_private *np = netdev_priv(dev);
2565 strncpy(info->driver, DRV_NAME, ETHTOOL_BUSINFO_LEN);
2566 strncpy(info->version, DRV_VERSION, ETHTOOL_BUSINFO_LEN);
2567 strncpy(info->bus_info, pci_name(np->pci_dev), ETHTOOL_BUSINFO_LEN);
2568}
2569
2570static int get_regs_len(struct net_device *dev)
2571{
2572 return NATSEMI_REGS_SIZE;
2573}
2574
2575static int get_eeprom_len(struct net_device *dev)
2576{
a8b4cf42
MB		 2577 struct netdev_private *np = netdev_priv(dev);
2578 return np->eeprom_size;
1da177e4
LT		 2579}
2580
2581static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2582{
2583 struct netdev_private *np = netdev_priv(dev);
2584 spin_lock_irq(&np->lock);
2585 netdev_get_ecmd(dev, ecmd);
2586 spin_unlock_irq(&np->lock);
2587 return 0;
2588}
2589
2590static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2591{
2592 struct netdev_private *np = netdev_priv(dev);
2593 int res;
2594 spin_lock_irq(&np->lock);
2595 res = netdev_set_ecmd(dev, ecmd);
2596 spin_unlock_irq(&np->lock);
2597 return res;
2598}
2599
2600static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2601{
2602 struct netdev_private *np = netdev_priv(dev);
2603 spin_lock_irq(&np->lock);
2604 netdev_get_wol(dev, &wol->supported, &wol->wolopts);
2605 netdev_get_sopass(dev, wol->sopass);
2606 spin_unlock_irq(&np->lock);
2607}
2608
2609static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2610{
2611 struct netdev_private *np = netdev_priv(dev);
2612 int res;
2613 spin_lock_irq(&np->lock);
2614 netdev_set_wol(dev, wol->wolopts);
2615 res = netdev_set_sopass(dev, wol->sopass);
2616 spin_unlock_irq(&np->lock);
2617 return res;
2618}
2619
2620static void get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
2621{
2622 struct netdev_private *np = netdev_priv(dev);
2623 regs->version = NATSEMI_REGS_VER;
2624 spin_lock_irq(&np->lock);
2625 netdev_get_regs(dev, buf);
2626 spin_unlock_irq(&np->lock);
2627}
2628
2629static u32 get_msglevel(struct net_device *dev)
2630{
2631 struct netdev_private *np = netdev_priv(dev);
2632 return np->msg_enable;
2633}
2634
2635static void set_msglevel(struct net_device *dev, u32 val)
2636{
2637 struct netdev_private *np = netdev_priv(dev);
2638 np->msg_enable = val;
2639}
2640
2641static int nway_reset(struct net_device *dev)
2642{
2643 int tmp;
2644 int r = -EINVAL;
2645 /* if autoneg is off, it's an error */
2646 tmp = mdio_read(dev, MII_BMCR);
2647 if (tmp & BMCR_ANENABLE) {
2648 tmp |= (BMCR_ANRESTART);
2649 mdio_write(dev, MII_BMCR, tmp);
2650 r = 0;
2651 }
2652 return r;
2653}
2654
2655static u32 get_link(struct net_device *dev)
2656{
2657 /* LSTATUS is latched low until a read - so read twice */
2658 mdio_read(dev, MII_BMSR);
2659 return (mdio_read(dev, MII_BMSR)&BMSR_LSTATUS) ? 1:0;
2660}
2661
2662static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
2663{
2664 struct netdev_private *np = netdev_priv(dev);
a8b4cf42 2665 u8 *eebuf;
1da177e4
LT		 2666 int res;
2667
a8b4cf42
MB		 2668 eebuf = kmalloc(np->eeprom_size, GFP_KERNEL);
2669 if (!eebuf)
2670 return -ENOMEM;
2671
1da177e4
LT		 2672 eeprom->magic = PCI_VENDOR_ID_NS | (PCI_DEVICE_ID_NS_83815<<16);
2673 spin_lock_irq(&np->lock);
2674 res = netdev_get_eeprom(dev, eebuf);
2675 spin_unlock_irq(&np->lock);
2676 if (!res)
2677 memcpy(data, eebuf+eeprom->offset, eeprom->len);
a8b4cf42 2678 kfree(eebuf);
1da177e4
LT		 2679 return res;
2680}
2681
7282d491 2682static const struct ethtool_ops ethtool_ops = {
1da177e4
LT		 2683 .get_drvinfo = get_drvinfo,
2684 .get_regs_len = get_regs_len,
2685 .get_eeprom_len = get_eeprom_len,
2686 .get_settings = get_settings,
2687 .set_settings = set_settings,
2688 .get_wol = get_wol,
2689 .set_wol = set_wol,
2690 .get_regs = get_regs,
2691 .get_msglevel = get_msglevel,
2692 .set_msglevel = set_msglevel,
2693 .nway_reset = nway_reset,
2694 .get_link = get_link,
2695 .get_eeprom = get_eeprom,
2696};
2697
2698static int netdev_set_wol(struct net_device *dev, u32 newval)
2699{
2700 struct netdev_private *np = netdev_priv(dev);
2701 void __iomem * ioaddr = ns_ioaddr(dev);
2702 u32 data = readl(ioaddr + WOLCmd) & ~WakeOptsSummary;
2703
2704 /* translate to bitmasks this chip understands */
2705 if (newval & WAKE_PHY)
2706 data |= WakePhy;
2707 if (newval & WAKE_UCAST)
2708 data |= WakeUnicast;
2709 if (newval & WAKE_MCAST)
2710 data |= WakeMulticast;
2711 if (newval & WAKE_BCAST)
2712 data |= WakeBroadcast;
2713 if (newval & WAKE_ARP)
2714 data |= WakeArp;
2715 if (newval & WAKE_MAGIC)
2716 data |= WakeMagic;
2717 if (np->srr >= SRR_DP83815_D) {
2718 if (newval & WAKE_MAGICSECURE) {
2719 data |= WakeMagicSecure;
2720 }
2721 }
2722
2723 writel(data, ioaddr + WOLCmd);
2724
2725 return 0;
2726}
2727
2728static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur)
2729{
2730 struct netdev_private *np = netdev_priv(dev);
2731 void __iomem * ioaddr = ns_ioaddr(dev);
2732 u32 regval = readl(ioaddr + WOLCmd);
2733
2734 *supported = (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST
2735 | WAKE_ARP | WAKE_MAGIC);
2736
2737 if (np->srr >= SRR_DP83815_D) {
2738 /* SOPASS works on revD and higher */
2739 *supported |= WAKE_MAGICSECURE;
2740 }
2741 *cur = 0;
2742
2743 /* translate from chip bitmasks */
2744 if (regval & WakePhy)
2745 *cur |= WAKE_PHY;
2746 if (regval & WakeUnicast)
2747 *cur |= WAKE_UCAST;
2748 if (regval & WakeMulticast)
2749 *cur |= WAKE_MCAST;
2750 if (regval & WakeBroadcast)
2751 *cur |= WAKE_BCAST;
2752 if (regval & WakeArp)
2753 *cur |= WAKE_ARP;
2754 if (regval & WakeMagic)
2755 *cur |= WAKE_MAGIC;
2756 if (regval & WakeMagicSecure) {
2757 /* this can be on in revC, but it's broken */
2758 *cur |= WAKE_MAGICSECURE;
2759 }
2760
2761 return 0;
2762}
2763
2764static int netdev_set_sopass(struct net_device *dev, u8 *newval)
2765{
2766 struct netdev_private *np = netdev_priv(dev);
2767 void __iomem * ioaddr = ns_ioaddr(dev);
2768 u16 *sval = (u16 *)newval;
2769 u32 addr;
2770
2771 if (np->srr < SRR_DP83815_D) {
2772 return 0;
2773 }
2774
2775 /* enable writing to these registers by disabling the RX filter */
2776 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2777 addr &= ~RxFilterEnable;
2778 writel(addr, ioaddr + RxFilterAddr);
2779
2780 /* write the three words to (undocumented) RFCR vals 0xa, 0xc, 0xe */
2781 writel(addr | 0xa, ioaddr + RxFilterAddr);
2782 writew(sval[0], ioaddr + RxFilterData);
2783
2784 writel(addr | 0xc, ioaddr + RxFilterAddr);
2785 writew(sval[1], ioaddr + RxFilterData);
2786
2787 writel(addr | 0xe, ioaddr + RxFilterAddr);
2788 writew(sval[2], ioaddr + RxFilterData);
2789
2790 /* re-enable the RX filter */
2791 writel(addr | RxFilterEnable, ioaddr + RxFilterAddr);
2792
2793 return 0;
2794}
2795
2796static int netdev_get_sopass(struct net_device *dev, u8 *data)
2797{
2798 struct netdev_private *np = netdev_priv(dev);
2799 void __iomem * ioaddr = ns_ioaddr(dev);
2800 u16 *sval = (u16 *)data;
2801 u32 addr;
2802
2803 if (np->srr < SRR_DP83815_D) {
2804 sval[0] = sval[1] = sval[2] = 0;
2805 return 0;
2806 }
2807
2808 /* read the three words from (undocumented) RFCR vals 0xa, 0xc, 0xe */
2809 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2810
2811 writel(addr | 0xa, ioaddr + RxFilterAddr);
2812 sval[0] = readw(ioaddr + RxFilterData);
2813
2814 writel(addr | 0xc, ioaddr + RxFilterAddr);
2815 sval[1] = readw(ioaddr + RxFilterData);
2816
2817 writel(addr | 0xe, ioaddr + RxFilterAddr);
2818 sval[2] = readw(ioaddr + RxFilterData);
2819
2820 writel(addr, ioaddr + RxFilterAddr);
2821
2822 return 0;
2823}
2824
2825static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2826{
2827 struct netdev_private *np = netdev_priv(dev);
2828 u32 tmp;
2829
2830 ecmd->port = dev->if_port;
2831 ecmd->speed = np->speed;
2832 ecmd->duplex = np->duplex;
2833 ecmd->autoneg = np->autoneg;
2834 ecmd->advertising = 0;
2835 if (np->advertising & ADVERTISE_10HALF)
2836 ecmd->advertising |= ADVERTISED_10baseT_Half;
2837 if (np->advertising & ADVERTISE_10FULL)
2838 ecmd->advertising |= ADVERTISED_10baseT_Full;
2839 if (np->advertising & ADVERTISE_100HALF)
2840 ecmd->advertising |= ADVERTISED_100baseT_Half;
2841 if (np->advertising & ADVERTISE_100FULL)
2842 ecmd->advertising |= ADVERTISED_100baseT_Full;
2843 ecmd->supported = (SUPPORTED_Autoneg |
2844 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2845 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2846 SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_FIBRE);
2847 ecmd->phy_address = np->phy_addr_external;
2848 /*
2849 * We intentionally report the phy address of the external
2850 * phy, even if the internal phy is used. This is necessary
2851 * to work around a deficiency of the ethtool interface:
2852 * It's only possible to query the settings of the active
6aa20a22 2853 * port. Therefore
1da177e4
LT		 2854 * # ethtool -s ethX port mii
2855 * actually sends an ioctl to switch to port mii with the
2856 * settings that are used for the current active port.
2857 * If we would report a different phy address in this
2858 * command, then
2859 * # ethtool -s ethX port tp;ethtool -s ethX port mii
2860 * would unintentionally change the phy address.
2861 *
2862 * Fortunately the phy address doesn't matter with the
2863 * internal phy...
2864 */
2865
2866 /* set information based on active port type */
2867 switch (ecmd->port) {
2868 default:
2869 case PORT_TP:
2870 ecmd->advertising |= ADVERTISED_TP;
2871 ecmd->transceiver = XCVR_INTERNAL;
2872 break;
2873 case PORT_MII:
2874 ecmd->advertising |= ADVERTISED_MII;
2875 ecmd->transceiver = XCVR_EXTERNAL;
2876 break;
2877 case PORT_FIBRE:
2878 ecmd->advertising |= ADVERTISED_FIBRE;
2879 ecmd->transceiver = XCVR_EXTERNAL;
2880 break;
2881 }
2882
2883 /* if autonegotiation is on, try to return the active speed/duplex */
2884 if (ecmd->autoneg == AUTONEG_ENABLE) {
2885 ecmd->advertising |= ADVERTISED_Autoneg;
2886 tmp = mii_nway_result(
2887 np->advertising & mdio_read(dev, MII_LPA));
2888 if (tmp == LPA_100FULL || tmp == LPA_100HALF)
2889 ecmd->speed = SPEED_100;
2890 else
2891 ecmd->speed = SPEED_10;
2892 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
2893 ecmd->duplex = DUPLEX_FULL;
2894 else
2895 ecmd->duplex = DUPLEX_HALF;
2896 }
2897
2898 /* ignore maxtxpkt, maxrxpkt for now */
2899
2900 return 0;
2901}
2902
2903static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2904{
2905 struct netdev_private *np = netdev_priv(dev);
2906
2907 if (ecmd->port != PORT_TP && ecmd->port != PORT_MII && ecmd->port != PORT_FIBRE)
2908 return -EINVAL;
2909 if (ecmd->transceiver != XCVR_INTERNAL && ecmd->transceiver != XCVR_EXTERNAL)
2910 return -EINVAL;
2911 if (ecmd->autoneg == AUTONEG_ENABLE) {
2912 if ((ecmd->advertising & (ADVERTISED_10baseT_Half |
2913 ADVERTISED_10baseT_Full |
2914 ADVERTISED_100baseT_Half |
2915 ADVERTISED_100baseT_Full)) == 0) {
2916 return -EINVAL;
2917 }
2918 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
2919 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
2920 return -EINVAL;
2921 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
2922 return -EINVAL;
2923 } else {
2924 return -EINVAL;
2925 }
2926
68c90166
MB		 2927 /*
2928 * If we're ignoring the PHY then autoneg and the internal
2929 * transciever are really not going to work so don't let the
2930 * user select them.
2931 */
2932 if (np->ignore_phy && (ecmd->autoneg == AUTONEG_ENABLE ||
2933 ecmd->port == PORT_TP))
2934 return -EINVAL;
2935
1da177e4
LT		 2936 /*
2937 * maxtxpkt, maxrxpkt: ignored for now.
2938 *
2939 * transceiver:
2940 * PORT_TP is always XCVR_INTERNAL, PORT_MII and PORT_FIBRE are always
2941 * XCVR_EXTERNAL. The implementation thus ignores ecmd->transceiver and
2942 * selects based on ecmd->port.
2943 *
2944 * Actually PORT_FIBRE is nearly identical to PORT_MII: it's for fibre
2945 * phys that are connected to the mii bus. It's used to apply fibre
2946 * specific updates.
2947 */
2948
2949 /* WHEW! now lets bang some bits */
2950
2951 /* save the parms */
2952 dev->if_port = ecmd->port;
2953 np->autoneg = ecmd->autoneg;
2954 np->phy_addr_external = ecmd->phy_address & PhyAddrMask;
2955 if (np->autoneg == AUTONEG_ENABLE) {
2956 /* advertise only what has been requested */
2957 np->advertising &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2958 if (ecmd->advertising & ADVERTISED_10baseT_Half)
2959 np->advertising |= ADVERTISE_10HALF;
2960 if (ecmd->advertising & ADVERTISED_10baseT_Full)
2961 np->advertising |= ADVERTISE_10FULL;
2962 if (ecmd->advertising & ADVERTISED_100baseT_Half)
2963 np->advertising |= ADVERTISE_100HALF;
2964 if (ecmd->advertising & ADVERTISED_100baseT_Full)
2965 np->advertising |= ADVERTISE_100FULL;
2966 } else {
2967 np->speed = ecmd->speed;
2968 np->duplex = ecmd->duplex;
2969 /* user overriding the initial full duplex parm? */
2970 if (np->duplex == DUPLEX_HALF)
2971 np->full_duplex = 0;
2972 }
2973
2974 /* get the right phy enabled */
2975 if (ecmd->port == PORT_TP)
2976 switch_port_internal(dev);
2977 else
2978 switch_port_external(dev);
2979
2980 /* set parms and see how this affected our link status */
2981 init_phy_fixup(dev);
2982 check_link(dev);
2983 return 0;
2984}
2985
2986static int netdev_get_regs(struct net_device *dev, u8 *buf)
2987{
2988 int i;
2989 int j;
2990 u32 rfcr;
2991 u32 *rbuf = (u32 *)buf;
2992 void __iomem * ioaddr = ns_ioaddr(dev);
2993
2994 /* read non-mii page 0 of registers */
2995 for (i = 0; i < NATSEMI_PG0_NREGS/2; i++) {
2996 rbuf[i] = readl(ioaddr + i*4);
2997 }
2998
2999 /* read current mii registers */
3000 for (i = NATSEMI_PG0_NREGS/2; i < NATSEMI_PG0_NREGS; i++)
3001 rbuf[i] = mdio_read(dev, i & 0x1f);
3002
3003 /* read only the 'magic' registers from page 1 */
3004 writew(1, ioaddr + PGSEL);
3005 rbuf[i++] = readw(ioaddr + PMDCSR);
3006 rbuf[i++] = readw(ioaddr + TSTDAT);
3007 rbuf[i++] = readw(ioaddr + DSPCFG);
3008 rbuf[i++] = readw(ioaddr + SDCFG);
3009 writew(0, ioaddr + PGSEL);
3010
3011 /* read RFCR indexed registers */
3012 rfcr = readl(ioaddr + RxFilterAddr);
3013 for (j = 0; j < NATSEMI_RFDR_NREGS; j++) {
3014 writel(j*2, ioaddr + RxFilterAddr);
3015 rbuf[i++] = readw(ioaddr + RxFilterData);
3016 }
3017 writel(rfcr, ioaddr + RxFilterAddr);
3018
3019 /* the interrupt status is clear-on-read - see if we missed any */
3020 if (rbuf[4] & rbuf[5]) {
3021 printk(KERN_WARNING
3022 "%s: shoot, we dropped an interrupt (%#08x)\n",
3023 dev->name, rbuf[4] & rbuf[5]);
3024 }
3025
3026 return 0;
3027}
3028
3029#define SWAP_BITS(x) ( (((x) & 0x0001) << 15) | (((x) & 0x0002) << 13) \
3030 | (((x) & 0x0004) << 11) | (((x) & 0x0008) << 9) \
3031 | (((x) & 0x0010) << 7) | (((x) & 0x0020) << 5) \
3032 | (((x) & 0x0040) << 3) | (((x) & 0x0080) << 1) \
3033 | (((x) & 0x0100) >> 1) | (((x) & 0x0200) >> 3) \
3034 | (((x) & 0x0400) >> 5) | (((x) & 0x0800) >> 7) \
3035 | (((x) & 0x1000) >> 9) | (((x) & 0x2000) >> 11) \
3036 | (((x) & 0x4000) >> 13) | (((x) & 0x8000) >> 15) )
3037
3038static int netdev_get_eeprom(struct net_device *dev, u8 *buf)
3039{
3040 int i;
3041 u16 *ebuf = (u16 *)buf;
3042 void __iomem * ioaddr = ns_ioaddr(dev);
a8b4cf42 3043 struct netdev_private *np = netdev_priv(dev);
1da177e4
LT		 3044
3045 /* eeprom_read reads 16 bits, and indexes by 16 bits */
a8b4cf42 3046 for (i = 0; i < np->eeprom_size/2; i++) {
1da177e4
LT		 3047 ebuf[i] = eeprom_read(ioaddr, i);
3048 /* The EEPROM itself stores data bit-swapped, but eeprom_read
3049 * reads it back "sanely". So we swap it back here in order to
3050 * present it to userland as it is stored. */
3051 ebuf[i] = SWAP_BITS(ebuf[i]);
3052 }
3053 return 0;
3054}
3055
3056static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3057{
3058 struct mii_ioctl_data *data = if_mii(rq);
3059 struct netdev_private *np = netdev_priv(dev);
3060
3061 switch(cmd) {
3062 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
3063 case SIOCDEVPRIVATE: /* for binary compat, remove in 2.5 */
3064 data->phy_id = np->phy_addr_external;
3065 /* Fall Through */
3066
3067 case SIOCGMIIREG: /* Read MII PHY register. */
3068 case SIOCDEVPRIVATE+1: /* for binary compat, remove in 2.5 */
3069 /* The phy_id is not enough to uniquely identify
3070 * the intended target. Therefore the command is sent to
3071 * the given mii on the current port.
3072 */
3073 if (dev->if_port == PORT_TP) {
3074 if ((data->phy_id & 0x1f) == np->phy_addr_external)
3075 data->val_out = mdio_read(dev,
3076 data->reg_num & 0x1f);
3077 else
3078 data->val_out = 0;
3079 } else {
3080 move_int_phy(dev, data->phy_id & 0x1f);
3081 data->val_out = miiport_read(dev, data->phy_id & 0x1f,
3082 data->reg_num & 0x1f);
3083 }
3084 return 0;
3085
3086 case SIOCSMIIREG: /* Write MII PHY register. */
3087 case SIOCDEVPRIVATE+2: /* for binary compat, remove in 2.5 */
3088 if (!capable(CAP_NET_ADMIN))
3089 return -EPERM;
3090 if (dev->if_port == PORT_TP) {
3091 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3092 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3093 np->advertising = data->val_in;
3094 mdio_write(dev, data->reg_num & 0x1f,
3095 data->val_in);
3096 }
3097 } else {
3098 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3099 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3100 np->advertising = data->val_in;
3101 }
3102 move_int_phy(dev, data->phy_id & 0x1f);
3103 miiport_write(dev, data->phy_id & 0x1f,
3104 data->reg_num & 0x1f,
3105 data->val_in);
3106 }
3107 return 0;
3108 default:
3109 return -EOPNOTSUPP;
3110 }
3111}
3112
3113static void enable_wol_mode(struct net_device *dev, int enable_intr)
3114{
3115 void __iomem * ioaddr = ns_ioaddr(dev);
3116 struct netdev_private *np = netdev_priv(dev);
3117
3118 if (netif_msg_wol(np))
3119 printk(KERN_INFO "%s: remaining active for wake-on-lan\n",
3120 dev->name);
3121
3122 /* For WOL we must restart the rx process in silent mode.
3123 * Write NULL to the RxRingPtr. Only possible if
3124 * rx process is stopped
3125 */
3126 writel(0, ioaddr + RxRingPtr);
3127
3128 /* read WoL status to clear */
3129 readl(ioaddr + WOLCmd);
3130
3131 /* PME on, clear status */
3132 writel(np->SavedClkRun | PMEEnable | PMEStatus, ioaddr + ClkRun);
3133
3134 /* and restart the rx process */
3135 writel(RxOn, ioaddr + ChipCmd);
3136
3137 if (enable_intr) {
3138 /* enable the WOL interrupt.
3139 * Could be used to send a netlink message.
3140 */
3141 writel(WOLPkt | LinkChange, ioaddr + IntrMask);
14fdd90e 3142 natsemi_irq_enable(dev);
1da177e4
LT		 3143 }
3144}
3145
3146static int netdev_close(struct net_device *dev)
3147{
3148 void __iomem * ioaddr = ns_ioaddr(dev);
3149 struct netdev_private *np = netdev_priv(dev);
3150
3151 if (netif_msg_ifdown(np))
3152 printk(KERN_DEBUG
3153 "%s: Shutting down ethercard, status was %#04x.\n",
3154 dev->name, (int)readl(ioaddr + ChipCmd));
3155 if (netif_msg_pktdata(np))
3156 printk(KERN_DEBUG
3157 "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
3158 dev->name, np->cur_tx, np->dirty_tx,
3159 np->cur_rx, np->dirty_rx);
3160
3161 /*
3162 * FIXME: what if someone tries to close a device
3163 * that is suspended?
3164 * Should we reenable the nic to switch to
3165 * the final WOL settings?
3166 */
3167
3168 del_timer_sync(&np->timer);
3169 disable_irq(dev->irq);
3170 spin_lock_irq(&np->lock);
b27a16b7 3171 natsemi_irq_disable(dev);
1da177e4
LT		 3172 np->hands_off = 1;
3173 spin_unlock_irq(&np->lock);
3174 enable_irq(dev->irq);
3175
3176 free_irq(dev->irq, dev);
3177
3178 /* Interrupt disabled, interrupt handler released,
3179 * queue stopped, timer deleted, rtnl_lock held
3180 * All async codepaths that access the driver are disabled.
3181 */
3182 spin_lock_irq(&np->lock);
3183 np->hands_off = 0;
3184 readl(ioaddr + IntrMask);
3185 readw(ioaddr + MIntrStatus);
3186
3187 /* Freeze Stats */
3188 writel(StatsFreeze, ioaddr + StatsCtrl);
3189
3190 /* Stop the chip's Tx and Rx processes. */
3191 natsemi_stop_rxtx(dev);
3192
3193 __get_stats(dev);
3194 spin_unlock_irq(&np->lock);
3195
3196 /* clear the carrier last - an interrupt could reenable it otherwise */
3197 netif_carrier_off(dev);
3198 netif_stop_queue(dev);
3199
3200 dump_ring(dev);
3201 drain_ring(dev);
3202 free_ring(dev);
3203
3204 {
3205 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3206 if (wol) {
3207 /* restart the NIC in WOL mode.
3208 * The nic must be stopped for this.
3209 */
3210 enable_wol_mode(dev, 0);
3211 } else {
3212 /* Restore PME enable bit unmolested */
3213 writel(np->SavedClkRun, ioaddr + ClkRun);
3214 }
3215 }
3216 return 0;
3217}
3218
3219
3220static void __devexit natsemi_remove1 (struct pci_dev *pdev)
3221{
3222 struct net_device *dev = pci_get_drvdata(pdev);
3223 void __iomem * ioaddr = ns_ioaddr(dev);
3224
1a147809 3225 NATSEMI_REMOVE_FILE(pdev, dspcfg_workaround);
1da177e4
LT		 3226 unregister_netdev (dev);
3227 pci_release_regions (pdev);
3228 iounmap(ioaddr);
3229 free_netdev (dev);
3230 pci_set_drvdata(pdev, NULL);
3231}
3232
3233#ifdef CONFIG_PM
3234
3235/*
3236 * The ns83815 chip doesn't have explicit RxStop bits.
3237 * Kicking the Rx or Tx process for a new packet reenables the Rx process
3238 * of the nic, thus this function must be very careful:
3239 *
3240 * suspend/resume synchronization:
3241 * entry points:
3242 * netdev_open, netdev_close, netdev_ioctl, set_rx_mode, intr_handler,
3243 * start_tx, tx_timeout
3244 *
3245 * No function accesses the hardware without checking np->hands_off.
3246 * the check occurs under spin_lock_irq(&np->lock);
3247 * exceptions:
3248 * * netdev_ioctl: noncritical access.
3249 * * netdev_open: cannot happen due to the device_detach
3250 * * netdev_close: doesn't hurt.
3251 * * netdev_timer: timer stopped by natsemi_suspend.
3252 * * intr_handler: doesn't acquire the spinlock. suspend calls
3253 * disable_irq() to enforce synchronization.
b27a16b7
MB		 3254 * * natsemi_poll: checks before reenabling interrupts. suspend
3255 * sets hands_off, disables interrupts and then waits with
3256 * netif_poll_disable().
1da177e4
LT		 3257 *
3258 * Interrupts must be disabled, otherwise hands_off can cause irq storms.
3259 */
3260
3261static int natsemi_suspend (struct pci_dev *pdev, pm_message_t state)
3262{
3263 struct net_device *dev = pci_get_drvdata (pdev);
3264 struct netdev_private *np = netdev_priv(dev);
3265 void __iomem * ioaddr = ns_ioaddr(dev);
3266
3267 rtnl_lock();
3268 if (netif_running (dev)) {
3269 del_timer_sync(&np->timer);
3270
3271 disable_irq(dev->irq);
3272 spin_lock_irq(&np->lock);
3273
14fdd90e 3274 natsemi_irq_disable(dev);
1da177e4
LT		 3275 np->hands_off = 1;
3276 natsemi_stop_rxtx(dev);
3277 netif_stop_queue(dev);
3278
3279 spin_unlock_irq(&np->lock);
3280 enable_irq(dev->irq);
3281
b27a16b7
MB		 3282 netif_poll_disable(dev);
3283
1da177e4
LT		 3284 /* Update the error counts. */
3285 __get_stats(dev);
3286
3287 /* pci_power_off(pdev, -1); */
3288 drain_ring(dev);
3289 {
3290 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3291 /* Restore PME enable bit */
3292 if (wol) {
3293 /* restart the NIC in WOL mode.
3294 * The nic must be stopped for this.
3295 * FIXME: use the WOL interrupt
3296 */
3297 enable_wol_mode(dev, 0);
3298 } else {
3299 /* Restore PME enable bit unmolested */
3300 writel(np->SavedClkRun, ioaddr + ClkRun);
3301 }
3302 }
3303 }
3304 netif_device_detach(dev);
3305 rtnl_unlock();
3306 return 0;
3307}
3308
3309
3310static int natsemi_resume (struct pci_dev *pdev)
3311{
3312 struct net_device *dev = pci_get_drvdata (pdev);
3313 struct netdev_private *np = netdev_priv(dev);
3314
3315 rtnl_lock();
3316 if (netif_device_present(dev))
3317 goto out;
3318 if (netif_running(dev)) {
3319 BUG_ON(!np->hands_off);
3320 pci_enable_device(pdev);
3321 /* pci_power_on(pdev); */
3322
3323 natsemi_reset(dev);
3324 init_ring(dev);
3325 disable_irq(dev->irq);
3326 spin_lock_irq(&np->lock);
3327 np->hands_off = 0;
3328 init_registers(dev);
3329 netif_device_attach(dev);
3330 spin_unlock_irq(&np->lock);
3331 enable_irq(dev->irq);
3332
3333 mod_timer(&np->timer, jiffies + 1*HZ);
3334 }
3335 netif_device_attach(dev);
b27a16b7 3336 netif_poll_enable(dev);
1da177e4
LT		 3337out:
3338 rtnl_unlock();
3339 return 0;
3340}
3341
3342#endif /* CONFIG_PM */
3343
3344static struct pci_driver natsemi_driver = {
3345 .name = DRV_NAME,
3346 .id_table = natsemi_pci_tbl,
3347 .probe = natsemi_probe1,
3348 .remove = __devexit_p(natsemi_remove1),
3349#ifdef CONFIG_PM
3350 .suspend = natsemi_suspend,
3351 .resume = natsemi_resume,
3352#endif
3353};
3354
3355static int __init natsemi_init_mod (void)
3356{
3357/* when a module, this is printed whether or not devices are found in probe */
3358#ifdef MODULE
3359 printk(version);
3360#endif
3361
29917620 3362 return pci_register_driver(&natsemi_driver);
1da177e4
LT		 3363}
3364
3365static void __exit natsemi_exit_mod (void)
3366{
3367 pci_unregister_driver (&natsemi_driver);
3368}
3369
3370module_init(natsemi_init_mod);
3371module_exit(natsemi_exit_mod);
3372
Linux kernel - Deliverables
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