Commit | Line | Data |
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3d396eb1 AK |
1 | /* |
2 | * Copyright (C) 2003 - 2006 NetXen, Inc. | |
3 | * All rights reserved. | |
80922fbc | 4 | * |
3d396eb1 AK |
5 | * This program is free software; you can redistribute it and/or |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
80922fbc | 9 | * |
3d396eb1 AK |
10 | * This program is distributed in the hope that it will be useful, but |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
80922fbc | 14 | * |
3d396eb1 AK |
15 | * You should have received a copy of the GNU General Public License |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, | |
18 | * MA 02111-1307, USA. | |
80922fbc | 19 | * |
3d396eb1 AK |
20 | * The full GNU General Public License is included in this distribution |
21 | * in the file called LICENSE. | |
80922fbc | 22 | * |
3d396eb1 AK |
23 | * Contact Information: |
24 | * info@netxen.com | |
25 | * NetXen, | |
26 | * 3965 Freedom Circle, Fourth floor, | |
27 | * Santa Clara, CA 95054 | |
28 | */ | |
29 | ||
30 | #ifndef _NETXEN_NIC_H_ | |
31 | #define _NETXEN_NIC_H_ | |
32 | ||
3d396eb1 AK |
33 | #include <linux/module.h> |
34 | #include <linux/kernel.h> | |
35 | #include <linux/types.h> | |
36 | #include <linux/compiler.h> | |
37 | #include <linux/slab.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/init.h> | |
40 | #include <linux/ioport.h> | |
41 | #include <linux/pci.h> | |
42 | #include <linux/netdevice.h> | |
43 | #include <linux/etherdevice.h> | |
44 | #include <linux/ip.h> | |
45 | #include <linux/in.h> | |
46 | #include <linux/tcp.h> | |
47 | #include <linux/skbuff.h> | |
48 | #include <linux/version.h> | |
49 | ||
50 | #include <linux/ethtool.h> | |
51 | #include <linux/mii.h> | |
52 | #include <linux/interrupt.h> | |
53 | #include <linux/timer.h> | |
54 | ||
55 | #include <linux/mm.h> | |
56 | #include <linux/mman.h> | |
57 | ||
58 | #include <asm/system.h> | |
59 | #include <asm/io.h> | |
60 | #include <asm/byteorder.h> | |
61 | #include <asm/uaccess.h> | |
62 | #include <asm/pgtable.h> | |
63 | ||
64 | #include "netxen_nic_hw.h" | |
65 | ||
ed25ffa1 | 66 | #define _NETXEN_NIC_LINUX_MAJOR 3 |
6d1495f2 | 67 | #define _NETXEN_NIC_LINUX_MINOR 4 |
001a731e | 68 | #define _NETXEN_NIC_LINUX_SUBVERSION 18 |
69 | #define NETXEN_NIC_LINUX_VERSIONID "3.4.18" | |
27d2ab54 | 70 | |
0d04761d MT |
71 | #define NETXEN_NUM_FLASH_SECTORS (64) |
72 | #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024) | |
73 | #define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \ | |
74 | * NETXEN_FLASH_SECTOR_SIZE) | |
3d396eb1 | 75 | |
0c25cfe1 LCMT |
76 | #define PHAN_VENDOR_ID 0x4040 |
77 | ||
3d396eb1 AK |
78 | #define RCV_DESC_RINGSIZE \ |
79 | (sizeof(struct rcv_desc) * adapter->max_rx_desc_count) | |
80 | #define STATUS_DESC_RINGSIZE \ | |
81 | (sizeof(struct status_desc)* adapter->max_rx_desc_count) | |
ed25ffa1 AK |
82 | #define LRO_DESC_RINGSIZE \ |
83 | (sizeof(rcvDesc_t) * adapter->max_lro_rx_desc_count) | |
3d396eb1 AK |
84 | #define TX_RINGSIZE \ |
85 | (sizeof(struct netxen_cmd_buffer) * adapter->max_tx_desc_count) | |
86 | #define RCV_BUFFSIZE \ | |
87 | (sizeof(struct netxen_rx_buffer) * rcv_desc->max_rx_desc_count) | |
0c25cfe1 | 88 | #define find_diff_among(a,b,range) ((a)<=(b)?((b)-(a)):((b)+(range)-(a))) |
3d396eb1 | 89 | |
ed25ffa1 AK |
90 | #define NETXEN_NETDEV_STATUS 0x1 |
91 | #define NETXEN_RCV_PRODUCER_OFFSET 0 | |
92 | #define NETXEN_RCV_PEG_DB_ID 2 | |
93 | #define NETXEN_HOST_DUMMY_DMA_SIZE 1024 | |
27d2ab54 | 94 | #define FLASH_SUCCESS 0 |
3d396eb1 AK |
95 | |
96 | #define ADDR_IN_WINDOW1(off) \ | |
97 | ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0 | |
ed25ffa1 AK |
98 | /* |
99 | * In netxen_nic_down(), we must wait for any pending callback requests into | |
100 | * netxen_watchdog_task() to complete; eg otherwise the watchdog_timer could be | |
101 | * reenabled right after it is deleted in netxen_nic_down(). FLUSH_SCHEDULED_WORK() | |
102 | * does this synchronization. | |
103 | * | |
104 | * Normally, schedule_work()/flush_scheduled_work() could have worked, but | |
105 | * netxen_nic_close() is invoked with kernel rtnl lock held. netif_carrier_off() | |
106 | * call in netxen_nic_close() triggers a schedule_work(&linkwatch_work), and a | |
107 | * subsequent call to flush_scheduled_work() in netxen_nic_down() would cause | |
108 | * linkwatch_event() to be executed which also attempts to acquire the rtnl | |
109 | * lock thus causing a deadlock. | |
110 | */ | |
111 | ||
112 | #define SCHEDULE_WORK(tp) queue_work(netxen_workq, tp) | |
113 | #define FLUSH_SCHEDULED_WORK() flush_workqueue(netxen_workq) | |
114 | extern struct workqueue_struct *netxen_workq; | |
3d396eb1 | 115 | |
4790654c JG |
116 | /* |
117 | * normalize a 64MB crb address to 32MB PCI window | |
3d396eb1 AK |
118 | * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1 |
119 | */ | |
80922fbc AK |
120 | #define NETXEN_CRB_NORMAL(reg) \ |
121 | ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST) | |
cb8011ad | 122 | |
3d396eb1 | 123 | #define NETXEN_CRB_NORMALIZE(adapter, reg) \ |
cb8011ad AK |
124 | pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg)) |
125 | ||
ed25ffa1 AK |
126 | #define DB_NORMALIZE(adapter, off) \ |
127 | (adapter->ahw.db_base + (off)) | |
128 | ||
129 | #define NX_P2_C0 0x24 | |
130 | #define NX_P2_C1 0x25 | |
131 | ||
cb8011ad | 132 | #define FIRST_PAGE_GROUP_START 0 |
ed25ffa1 | 133 | #define FIRST_PAGE_GROUP_END 0x100000 |
cb8011ad | 134 | |
78403a92 MT |
135 | #define SECOND_PAGE_GROUP_START 0x6000000 |
136 | #define SECOND_PAGE_GROUP_END 0x68BC000 | |
cb8011ad AK |
137 | |
138 | #define THIRD_PAGE_GROUP_START 0x70E4000 | |
139 | #define THIRD_PAGE_GROUP_END 0x8000000 | |
140 | ||
141 | #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START | |
142 | #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START | |
143 | #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START | |
3d396eb1 | 144 | |
ed25ffa1 | 145 | #define MAX_RX_BUFFER_LENGTH 1760 |
bd56c6b1 | 146 | #define MAX_RX_JUMBO_BUFFER_LENGTH 8062 |
ed25ffa1 AK |
147 | #define MAX_RX_LRO_BUFFER_LENGTH ((48*1024)-512) |
148 | #define RX_DMA_MAP_LEN (MAX_RX_BUFFER_LENGTH - 2) | |
3d396eb1 | 149 | #define RX_JUMBO_DMA_MAP_LEN \ |
ed25ffa1 AK |
150 | (MAX_RX_JUMBO_BUFFER_LENGTH - 2) |
151 | #define RX_LRO_DMA_MAP_LEN (MAX_RX_LRO_BUFFER_LENGTH - 2) | |
3d396eb1 AK |
152 | #define NETXEN_ROM_ROUNDUP 0x80000000ULL |
153 | ||
154 | /* | |
155 | * Maximum number of ring contexts | |
156 | */ | |
157 | #define MAX_RING_CTX 1 | |
158 | ||
159 | /* Opcodes to be used with the commands */ | |
160 | enum { | |
161 | TX_ETHER_PKT = 0x01, | |
162 | /* The following opcodes are for IP checksum */ | |
163 | TX_TCP_PKT, | |
164 | TX_UDP_PKT, | |
165 | TX_IP_PKT, | |
166 | TX_TCP_LSO, | |
167 | TX_IPSEC, | |
168 | TX_IPSEC_CMD | |
169 | }; | |
170 | ||
171 | /* The following opcodes are for internal consumption. */ | |
172 | #define NETXEN_CONTROL_OP 0x10 | |
173 | #define PEGNET_REQUEST 0x11 | |
174 | ||
175 | #define MAX_NUM_CARDS 4 | |
176 | ||
177 | #define MAX_BUFFERS_PER_CMD 32 | |
178 | ||
179 | /* | |
180 | * Following are the states of the Phantom. Phantom will set them and | |
181 | * Host will read to check if the fields are correct. | |
182 | */ | |
183 | #define PHAN_INITIALIZE_START 0xff00 | |
184 | #define PHAN_INITIALIZE_FAILED 0xffff | |
185 | #define PHAN_INITIALIZE_COMPLETE 0xff01 | |
186 | ||
187 | /* Host writes the following to notify that it has done the init-handshake */ | |
188 | #define PHAN_INITIALIZE_ACK 0xf00f | |
189 | ||
ed25ffa1 | 190 | #define NUM_RCV_DESC_RINGS 3 /* No of Rcv Descriptor contexts */ |
3d396eb1 AK |
191 | |
192 | /* descriptor types */ | |
193 | #define RCV_DESC_NORMAL 0x01 | |
194 | #define RCV_DESC_JUMBO 0x02 | |
ed25ffa1 | 195 | #define RCV_DESC_LRO 0x04 |
3d396eb1 AK |
196 | #define RCV_DESC_NORMAL_CTXID 0 |
197 | #define RCV_DESC_JUMBO_CTXID 1 | |
ed25ffa1 | 198 | #define RCV_DESC_LRO_CTXID 2 |
3d396eb1 AK |
199 | |
200 | #define RCV_DESC_TYPE(ID) \ | |
ed25ffa1 AK |
201 | ((ID == RCV_DESC_JUMBO_CTXID) \ |
202 | ? RCV_DESC_JUMBO \ | |
203 | : ((ID == RCV_DESC_LRO_CTXID) \ | |
204 | ? RCV_DESC_LRO : \ | |
205 | (RCV_DESC_NORMAL))) | |
3d396eb1 AK |
206 | |
207 | #define MAX_CMD_DESCRIPTORS 1024 | |
bd56c6b1 | 208 | #define MAX_RCV_DESCRIPTORS 16384 |
6c80b18d | 209 | #define MAX_CMD_DESCRIPTORS_HOST (MAX_CMD_DESCRIPTORS / 4) |
13ba9c77 | 210 | #define MAX_RCV_DESCRIPTORS_1G (MAX_RCV_DESCRIPTORS / 4) |
bd56c6b1 AK |
211 | #define MAX_JUMBO_RCV_DESCRIPTORS 1024 |
212 | #define MAX_LRO_RCV_DESCRIPTORS 64 | |
3d396eb1 AK |
213 | #define MAX_RCVSTATUS_DESCRIPTORS MAX_RCV_DESCRIPTORS |
214 | #define MAX_JUMBO_RCV_DESC MAX_JUMBO_RCV_DESCRIPTORS | |
215 | #define MAX_RCV_DESC MAX_RCV_DESCRIPTORS | |
216 | #define MAX_RCVSTATUS_DESC MAX_RCV_DESCRIPTORS | |
3d396eb1 | 217 | #define MAX_EPG_DESCRIPTORS (MAX_CMD_DESCRIPTORS * 8) |
ed25ffa1 AK |
218 | #define NUM_RCV_DESC (MAX_RCV_DESC + MAX_JUMBO_RCV_DESCRIPTORS + \ |
219 | MAX_LRO_RCV_DESCRIPTORS) | |
3d396eb1 AK |
220 | #define MIN_TX_COUNT 4096 |
221 | #define MIN_RX_COUNT 4096 | |
ed25ffa1 AK |
222 | #define NETXEN_CTX_SIGNATURE 0xdee0 |
223 | #define NETXEN_RCV_PRODUCER(ringid) (ringid) | |
3d396eb1 AK |
224 | #define MAX_FRAME_SIZE 0x10000 /* 64K MAX size for LSO */ |
225 | ||
226 | #define PHAN_PEG_RCV_INITIALIZED 0xff01 | |
227 | #define PHAN_PEG_RCV_START_INITIALIZE 0xff00 | |
228 | ||
229 | #define get_next_index(index, length) \ | |
230 | (((index) + 1) & ((length) - 1)) | |
231 | ||
232 | #define get_index_range(index,length,count) \ | |
233 | (((index) + (count)) & ((length) - 1)) | |
234 | ||
ed25ffa1 | 235 | #define MPORT_SINGLE_FUNCTION_MODE 0x1111 |
3176ff3e | 236 | #define MPORT_MULTI_FUNCTION_MODE 0x2222 |
ed25ffa1 | 237 | |
3176ff3e | 238 | #include "netxen_nic_phan_reg.h" |
ed25ffa1 | 239 | extern unsigned long long netxen_dma_mask; |
b58ecad8 | 240 | extern unsigned long last_schedule_time; |
ed25ffa1 AK |
241 | |
242 | /* | |
243 | * NetXen host-peg signal message structure | |
244 | * | |
245 | * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx | |
246 | * Bit 2 : priv_id => must be 1 | |
247 | * Bit 3-17 : count => for doorbell | |
248 | * Bit 18-27 : ctx_id => Context id | |
249 | * Bit 28-31 : opcode | |
250 | */ | |
251 | ||
252 | typedef u32 netxen_ctx_msg; | |
253 | ||
ed25ffa1 | 254 | #define netxen_set_msg_peg_id(config_word, val) \ |
a608ab9c | 255 | ((config_word) &= ~3, (config_word) |= val & 3) |
ed25ffa1 | 256 | #define netxen_set_msg_privid(config_word) \ |
a608ab9c | 257 | ((config_word) |= 1 << 2) |
ed25ffa1 | 258 | #define netxen_set_msg_count(config_word, val) \ |
a608ab9c | 259 | ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3) |
ed25ffa1 | 260 | #define netxen_set_msg_ctxid(config_word, val) \ |
a608ab9c | 261 | ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18) |
ed25ffa1 | 262 | #define netxen_set_msg_opcode(config_word, val) \ |
82581174 | 263 | ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28) |
ed25ffa1 AK |
264 | |
265 | struct netxen_rcv_context { | |
a608ab9c AV |
266 | __le64 rcv_ring_addr; |
267 | __le32 rcv_ring_size; | |
268 | __le32 rsrvd; | |
ed25ffa1 AK |
269 | }; |
270 | ||
271 | struct netxen_ring_ctx { | |
272 | ||
273 | /* one command ring */ | |
a608ab9c AV |
274 | __le64 cmd_consumer_offset; |
275 | __le64 cmd_ring_addr; | |
276 | __le32 cmd_ring_size; | |
277 | __le32 rsrvd; | |
ed25ffa1 AK |
278 | |
279 | /* three receive rings */ | |
280 | struct netxen_rcv_context rcv_ctx[3]; | |
281 | ||
282 | /* one status ring */ | |
a608ab9c AV |
283 | __le64 sts_ring_addr; |
284 | __le32 sts_ring_size; | |
ed25ffa1 | 285 | |
a608ab9c | 286 | __le32 ctx_id; |
ed25ffa1 AK |
287 | } __attribute__ ((aligned(64))); |
288 | ||
3d396eb1 AK |
289 | /* |
290 | * Following data structures describe the descriptors that will be used. | |
291 | * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when | |
292 | * we are doing LSO (above the 1500 size packet) only. | |
293 | */ | |
294 | ||
295 | /* | |
296 | * The size of reference handle been changed to 16 bits to pass the MSS fields | |
297 | * for the LSO packet | |
298 | */ | |
299 | ||
300 | #define FLAGS_CHECKSUM_ENABLED 0x01 | |
301 | #define FLAGS_LSO_ENABLED 0x02 | |
302 | #define FLAGS_IPSEC_SA_ADD 0x04 | |
303 | #define FLAGS_IPSEC_SA_DELETE 0x08 | |
304 | #define FLAGS_VLAN_TAGGED 0x10 | |
305 | ||
ed25ffa1 AK |
306 | #define netxen_set_cmd_desc_port(cmd_desc, var) \ |
307 | ((cmd_desc)->port_ctxid |= ((var) & 0x0F)) | |
6c80b18d MT |
308 | #define netxen_set_cmd_desc_ctxid(cmd_desc, var) \ |
309 | ((cmd_desc)->port_ctxid |= ((var) & 0xF0)) | |
3d396eb1 | 310 | |
ed25ffa1 | 311 | #define netxen_set_cmd_desc_flags(cmd_desc, val) \ |
5dc16268 DP |
312 | (cmd_desc)->flags_opcode = ((cmd_desc)->flags_opcode & \ |
313 | ~cpu_to_le16(0x7f)) | cpu_to_le16((val) & 0x7f) | |
ed25ffa1 | 314 | #define netxen_set_cmd_desc_opcode(cmd_desc, val) \ |
5dc16268 DP |
315 | (cmd_desc)->flags_opcode = ((cmd_desc)->flags_opcode & \ |
316 | ~cpu_to_le16((u16)0x3f << 7)) | cpu_to_le16(((val) & 0x3f) << 7) | |
ed25ffa1 AK |
317 | |
318 | #define netxen_set_cmd_desc_num_of_buff(cmd_desc, val) \ | |
5dc16268 DP |
319 | (cmd_desc)->num_of_buffers_total_length = \ |
320 | ((cmd_desc)->num_of_buffers_total_length & \ | |
321 | ~cpu_to_le32(0xff)) | cpu_to_le32((val) & 0xff) | |
ed25ffa1 | 322 | #define netxen_set_cmd_desc_totallength(cmd_desc, val) \ |
5dc16268 DP |
323 | (cmd_desc)->num_of_buffers_total_length = \ |
324 | ((cmd_desc)->num_of_buffers_total_length & \ | |
325 | ~cpu_to_le32((u32)0xffffff << 8)) | \ | |
326 | cpu_to_le32(((val) & 0xffffff) << 8) | |
ed25ffa1 AK |
327 | |
328 | #define netxen_get_cmd_desc_opcode(cmd_desc) \ | |
5dc16268 | 329 | ((le16_to_cpu((cmd_desc)->flags_opcode) >> 7) & 0x003f) |
ed25ffa1 | 330 | #define netxen_get_cmd_desc_totallength(cmd_desc) \ |
5dc16268 | 331 | ((le32_to_cpu((cmd_desc)->num_of_buffers_total_length) >> 8) & 0xffffff) |
3d396eb1 AK |
332 | |
333 | struct cmd_desc_type0 { | |
ed25ffa1 AK |
334 | u8 tcp_hdr_offset; /* For LSO only */ |
335 | u8 ip_hdr_offset; /* For LSO only */ | |
336 | /* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */ | |
a608ab9c | 337 | __le16 flags_opcode; |
ed25ffa1 AK |
338 | /* Bit pattern: 0-7 total number of segments, |
339 | 8-31 Total size of the packet */ | |
a608ab9c | 340 | __le32 num_of_buffers_total_length; |
3d396eb1 AK |
341 | union { |
342 | struct { | |
a608ab9c AV |
343 | __le32 addr_low_part2; |
344 | __le32 addr_high_part2; | |
3d396eb1 | 345 | }; |
a608ab9c | 346 | __le64 addr_buffer2; |
3d396eb1 AK |
347 | }; |
348 | ||
a608ab9c AV |
349 | __le16 reference_handle; /* changed to u16 to add mss */ |
350 | __le16 mss; /* passed by NDIS_PACKET for LSO */ | |
3d396eb1 AK |
351 | /* Bit pattern 0-3 port, 0-3 ctx id */ |
352 | u8 port_ctxid; | |
353 | u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */ | |
a608ab9c | 354 | __le16 conn_id; /* IPSec offoad only */ |
3d396eb1 AK |
355 | |
356 | union { | |
357 | struct { | |
a608ab9c AV |
358 | __le32 addr_low_part3; |
359 | __le32 addr_high_part3; | |
3d396eb1 | 360 | }; |
a608ab9c | 361 | __le64 addr_buffer3; |
3d396eb1 | 362 | }; |
3d396eb1 AK |
363 | union { |
364 | struct { | |
a608ab9c AV |
365 | __le32 addr_low_part1; |
366 | __le32 addr_high_part1; | |
3d396eb1 | 367 | }; |
a608ab9c | 368 | __le64 addr_buffer1; |
3d396eb1 AK |
369 | }; |
370 | ||
a608ab9c AV |
371 | __le16 buffer1_length; |
372 | __le16 buffer2_length; | |
373 | __le16 buffer3_length; | |
374 | __le16 buffer4_length; | |
3d396eb1 AK |
375 | |
376 | union { | |
377 | struct { | |
a608ab9c AV |
378 | __le32 addr_low_part4; |
379 | __le32 addr_high_part4; | |
3d396eb1 | 380 | }; |
a608ab9c | 381 | __le64 addr_buffer4; |
3d396eb1 AK |
382 | }; |
383 | ||
a608ab9c | 384 | __le64 unused; |
ed25ffa1 | 385 | |
3d396eb1 AK |
386 | } __attribute__ ((aligned(64))); |
387 | ||
388 | /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */ | |
389 | struct rcv_desc { | |
a608ab9c AV |
390 | __le16 reference_handle; |
391 | __le16 reserved; | |
392 | __le32 buffer_length; /* allocated buffer length (usually 2K) */ | |
393 | __le64 addr_buffer; | |
3d396eb1 AK |
394 | }; |
395 | ||
396 | /* opcode field in status_desc */ | |
397 | #define RCV_NIC_PKT (0xA) | |
398 | #define STATUS_NIC_PKT ((RCV_NIC_PKT) << 12) | |
399 | ||
400 | /* for status field in status_desc */ | |
401 | #define STATUS_NEED_CKSUM (1) | |
402 | #define STATUS_CKSUM_OK (2) | |
403 | ||
404 | /* owner bits of status_desc */ | |
405 | #define STATUS_OWNER_HOST (0x1) | |
406 | #define STATUS_OWNER_PHANTOM (0x2) | |
407 | ||
408 | #define NETXEN_PROT_IP (1) | |
409 | #define NETXEN_PROT_UNKNOWN (0) | |
410 | ||
411 | /* Note: sizeof(status_desc) should always be a mutliple of 2 */ | |
ed25ffa1 AK |
412 | |
413 | #define netxen_get_sts_desc_lro_cnt(status_desc) \ | |
414 | ((status_desc)->lro & 0x7F) | |
415 | #define netxen_get_sts_desc_lro_last_frag(status_desc) \ | |
416 | (((status_desc)->lro & 0x80) >> 7) | |
417 | ||
5dc16268 DP |
418 | #define netxen_get_sts_port(sts_data) \ |
419 | ((sts_data) & 0x0F) | |
420 | #define netxen_get_sts_status(sts_data) \ | |
421 | (((sts_data) >> 4) & 0x0F) | |
422 | #define netxen_get_sts_type(sts_data) \ | |
423 | (((sts_data) >> 8) & 0x0F) | |
424 | #define netxen_get_sts_totallength(sts_data) \ | |
425 | (((sts_data) >> 12) & 0xFFFF) | |
426 | #define netxen_get_sts_refhandle(sts_data) \ | |
427 | (((sts_data) >> 28) & 0xFFFF) | |
428 | #define netxen_get_sts_prot(sts_data) \ | |
429 | (((sts_data) >> 44) & 0x0F) | |
430 | #define netxen_get_sts_opcode(sts_data) \ | |
431 | (((sts_data) >> 58) & 0x03F) | |
432 | ||
ed25ffa1 | 433 | #define netxen_get_sts_owner(status_desc) \ |
a608ab9c | 434 | ((le64_to_cpu((status_desc)->status_desc_data) >> 56) & 0x03) |
5dc16268 DP |
435 | #define netxen_set_sts_owner(status_desc, val) { \ |
436 | (status_desc)->status_desc_data = \ | |
437 | ((status_desc)->status_desc_data & \ | |
438 | ~cpu_to_le64(0x3ULL << 56)) | \ | |
439 | cpu_to_le64((u64)((val) & 0x3) << 56); \ | |
440 | } | |
3d396eb1 AK |
441 | |
442 | struct status_desc { | |
ed25ffa1 AK |
443 | /* Bit pattern: 0-3 port, 4-7 status, 8-11 type, 12-27 total_length |
444 | 28-43 reference_handle, 44-47 protocol, 48-52 unused | |
445 | 53-55 desc_cnt, 56-57 owner, 58-63 opcode | |
446 | */ | |
a608ab9c AV |
447 | __le64 status_desc_data; |
448 | __le32 hash_value; | |
ed25ffa1 AK |
449 | u8 hash_type; |
450 | u8 msg_type; | |
451 | u8 unused; | |
452 | /* Bit pattern: 0-6 lro_count indicates frag sequence, | |
453 | 7 last_frag indicates last frag */ | |
454 | u8 lro; | |
6c80b18d | 455 | } __attribute__ ((aligned(16))); |
3d396eb1 AK |
456 | |
457 | enum { | |
458 | NETXEN_RCV_PEG_0 = 0, | |
459 | NETXEN_RCV_PEG_1 | |
460 | }; | |
461 | /* The version of the main data structure */ | |
462 | #define NETXEN_BDINFO_VERSION 1 | |
463 | ||
464 | /* Magic number to let user know flash is programmed */ | |
465 | #define NETXEN_BDINFO_MAGIC 0x12345678 | |
466 | ||
467 | /* Max number of Gig ports on a Phantom board */ | |
468 | #define NETXEN_MAX_PORTS 4 | |
469 | ||
470 | typedef enum { | |
471 | NETXEN_BRDTYPE_P1_BD = 0x0000, | |
472 | NETXEN_BRDTYPE_P1_SB = 0x0001, | |
473 | NETXEN_BRDTYPE_P1_SMAX = 0x0002, | |
474 | NETXEN_BRDTYPE_P1_SOCK = 0x0003, | |
475 | ||
476 | NETXEN_BRDTYPE_P2_SOCK_31 = 0x0008, | |
477 | NETXEN_BRDTYPE_P2_SOCK_35 = 0x0009, | |
478 | NETXEN_BRDTYPE_P2_SB35_4G = 0x000a, | |
479 | NETXEN_BRDTYPE_P2_SB31_10G = 0x000b, | |
480 | NETXEN_BRDTYPE_P2_SB31_2G = 0x000c, | |
481 | ||
482 | NETXEN_BRDTYPE_P2_SB31_10G_IMEZ = 0x000d, | |
483 | NETXEN_BRDTYPE_P2_SB31_10G_HMEZ = 0x000e, | |
484 | NETXEN_BRDTYPE_P2_SB31_10G_CX4 = 0x000f | |
485 | } netxen_brdtype_t; | |
486 | ||
487 | typedef enum { | |
488 | NETXEN_BRDMFG_INVENTEC = 1 | |
489 | } netxen_brdmfg; | |
490 | ||
491 | typedef enum { | |
492 | MEM_ORG_128Mbx4 = 0x0, /* DDR1 only */ | |
493 | MEM_ORG_128Mbx8 = 0x1, /* DDR1 only */ | |
494 | MEM_ORG_128Mbx16 = 0x2, /* DDR1 only */ | |
495 | MEM_ORG_256Mbx4 = 0x3, | |
496 | MEM_ORG_256Mbx8 = 0x4, | |
497 | MEM_ORG_256Mbx16 = 0x5, | |
498 | MEM_ORG_512Mbx4 = 0x6, | |
499 | MEM_ORG_512Mbx8 = 0x7, | |
500 | MEM_ORG_512Mbx16 = 0x8, | |
501 | MEM_ORG_1Gbx4 = 0x9, | |
502 | MEM_ORG_1Gbx8 = 0xa, | |
503 | MEM_ORG_1Gbx16 = 0xb, | |
504 | MEM_ORG_2Gbx4 = 0xc, | |
505 | MEM_ORG_2Gbx8 = 0xd, | |
506 | MEM_ORG_2Gbx16 = 0xe, | |
507 | MEM_ORG_128Mbx32 = 0x10002, /* GDDR only */ | |
508 | MEM_ORG_256Mbx32 = 0x10005 /* GDDR only */ | |
509 | } netxen_mn_mem_org_t; | |
510 | ||
511 | typedef enum { | |
512 | MEM_ORG_512Kx36 = 0x0, | |
513 | MEM_ORG_1Mx36 = 0x1, | |
514 | MEM_ORG_2Mx36 = 0x2 | |
515 | } netxen_sn_mem_org_t; | |
516 | ||
517 | typedef enum { | |
518 | MEM_DEPTH_4MB = 0x1, | |
519 | MEM_DEPTH_8MB = 0x2, | |
520 | MEM_DEPTH_16MB = 0x3, | |
521 | MEM_DEPTH_32MB = 0x4, | |
522 | MEM_DEPTH_64MB = 0x5, | |
523 | MEM_DEPTH_128MB = 0x6, | |
524 | MEM_DEPTH_256MB = 0x7, | |
525 | MEM_DEPTH_512MB = 0x8, | |
526 | MEM_DEPTH_1GB = 0x9, | |
527 | MEM_DEPTH_2GB = 0xa, | |
528 | MEM_DEPTH_4GB = 0xb, | |
529 | MEM_DEPTH_8GB = 0xc, | |
530 | MEM_DEPTH_16GB = 0xd, | |
531 | MEM_DEPTH_32GB = 0xe | |
532 | } netxen_mem_depth_t; | |
533 | ||
534 | struct netxen_board_info { | |
535 | u32 header_version; | |
536 | ||
537 | u32 board_mfg; | |
538 | u32 board_type; | |
539 | u32 board_num; | |
540 | u32 chip_id; | |
541 | u32 chip_minor; | |
542 | u32 chip_major; | |
543 | u32 chip_pkg; | |
544 | u32 chip_lot; | |
545 | ||
546 | u32 port_mask; /* available niu ports */ | |
547 | u32 peg_mask; /* available pegs */ | |
548 | u32 icache_ok; /* can we run with icache? */ | |
549 | u32 dcache_ok; /* can we run with dcache? */ | |
550 | u32 casper_ok; | |
551 | ||
552 | u32 mac_addr_lo_0; | |
553 | u32 mac_addr_lo_1; | |
554 | u32 mac_addr_lo_2; | |
555 | u32 mac_addr_lo_3; | |
556 | ||
557 | /* MN-related config */ | |
558 | u32 mn_sync_mode; /* enable/ sync shift cclk/ sync shift mclk */ | |
559 | u32 mn_sync_shift_cclk; | |
560 | u32 mn_sync_shift_mclk; | |
561 | u32 mn_wb_en; | |
562 | u32 mn_crystal_freq; /* in MHz */ | |
563 | u32 mn_speed; /* in MHz */ | |
564 | u32 mn_org; | |
565 | u32 mn_depth; | |
566 | u32 mn_ranks_0; /* ranks per slot */ | |
567 | u32 mn_ranks_1; /* ranks per slot */ | |
568 | u32 mn_rd_latency_0; | |
569 | u32 mn_rd_latency_1; | |
570 | u32 mn_rd_latency_2; | |
571 | u32 mn_rd_latency_3; | |
572 | u32 mn_rd_latency_4; | |
573 | u32 mn_rd_latency_5; | |
574 | u32 mn_rd_latency_6; | |
575 | u32 mn_rd_latency_7; | |
576 | u32 mn_rd_latency_8; | |
577 | u32 mn_dll_val[18]; | |
578 | u32 mn_mode_reg; /* MIU DDR Mode Register */ | |
579 | u32 mn_ext_mode_reg; /* MIU DDR Extended Mode Register */ | |
580 | u32 mn_timing_0; /* MIU Memory Control Timing Rgister */ | |
581 | u32 mn_timing_1; /* MIU Extended Memory Ctrl Timing Register */ | |
582 | u32 mn_timing_2; /* MIU Extended Memory Ctrl Timing2 Register */ | |
583 | ||
584 | /* SN-related config */ | |
585 | u32 sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */ | |
586 | u32 sn_pt_mode; /* pass through mode */ | |
587 | u32 sn_ecc_en; | |
588 | u32 sn_wb_en; | |
589 | u32 sn_crystal_freq; | |
590 | u32 sn_speed; | |
591 | u32 sn_org; | |
592 | u32 sn_depth; | |
593 | u32 sn_dll_tap; | |
594 | u32 sn_rd_latency; | |
595 | ||
596 | u32 mac_addr_hi_0; | |
597 | u32 mac_addr_hi_1; | |
598 | u32 mac_addr_hi_2; | |
599 | u32 mac_addr_hi_3; | |
600 | ||
601 | u32 magic; /* indicates flash has been initialized */ | |
602 | ||
603 | u32 mn_rdimm; | |
604 | u32 mn_dll_override; | |
605 | ||
606 | }; | |
607 | ||
608 | #define FLASH_NUM_PORTS (4) | |
609 | ||
610 | struct netxen_flash_mac_addr { | |
611 | u32 flash_addr[32]; | |
612 | }; | |
613 | ||
614 | struct netxen_user_old_info { | |
615 | u8 flash_md5[16]; | |
616 | u8 crbinit_md5[16]; | |
617 | u8 brdcfg_md5[16]; | |
618 | /* bootloader */ | |
619 | u32 bootld_version; | |
620 | u32 bootld_size; | |
621 | u8 bootld_md5[16]; | |
622 | /* image */ | |
623 | u32 image_version; | |
624 | u32 image_size; | |
625 | u8 image_md5[16]; | |
626 | /* primary image status */ | |
627 | u32 primary_status; | |
628 | u32 secondary_present; | |
629 | ||
630 | /* MAC address , 4 ports */ | |
631 | struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS]; | |
632 | }; | |
633 | #define FLASH_NUM_MAC_PER_PORT 32 | |
634 | struct netxen_user_info { | |
635 | u8 flash_md5[16 * 64]; | |
636 | /* bootloader */ | |
637 | u32 bootld_version; | |
638 | u32 bootld_size; | |
639 | /* image */ | |
640 | u32 image_version; | |
641 | u32 image_size; | |
642 | /* primary image status */ | |
643 | u32 primary_status; | |
644 | u32 secondary_present; | |
645 | ||
646 | /* MAC address , 4 ports, 32 address per port */ | |
647 | u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT]; | |
648 | u32 sub_sys_id; | |
649 | u8 serial_num[32]; | |
650 | ||
651 | /* Any user defined data */ | |
652 | }; | |
653 | ||
654 | /* | |
655 | * Flash Layout - new format. | |
656 | */ | |
657 | struct netxen_new_user_info { | |
658 | u8 flash_md5[16 * 64]; | |
659 | /* bootloader */ | |
660 | u32 bootld_version; | |
661 | u32 bootld_size; | |
662 | /* image */ | |
663 | u32 image_version; | |
664 | u32 image_size; | |
665 | /* primary image status */ | |
666 | u32 primary_status; | |
667 | u32 secondary_present; | |
668 | ||
669 | /* MAC address , 4 ports, 32 address per port */ | |
670 | u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT]; | |
671 | u32 sub_sys_id; | |
672 | u8 serial_num[32]; | |
673 | ||
674 | /* Any user defined data */ | |
675 | }; | |
676 | ||
677 | #define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6 | |
678 | #define SECONDARY_IMAGE_ABSENT 0xffffffff | |
679 | #define PRIMARY_IMAGE_GOOD 0x5a5a5a5a | |
680 | #define PRIMARY_IMAGE_BAD 0xffffffff | |
681 | ||
682 | /* Flash memory map */ | |
683 | typedef enum { | |
0d04761d MT |
684 | NETXEN_CRBINIT_START = 0, /* Crbinit section */ |
685 | NETXEN_BRDCFG_START = 0x4000, /* board config */ | |
686 | NETXEN_INITCODE_START = 0x6000, /* pegtune code */ | |
687 | NETXEN_BOOTLD_START = 0x10000, /* bootld */ | |
688 | NETXEN_IMAGE_START = 0x43000, /* compressed image */ | |
689 | NETXEN_SECONDARY_START = 0x200000, /* backup images */ | |
690 | NETXEN_PXE_START = 0x3E0000, /* user defined region */ | |
691 | NETXEN_USER_START = 0x3E8000, /* User defined region for new boards */ | |
692 | NETXEN_FIXED_START = 0x3F0000 /* backup of crbinit */ | |
3d396eb1 AK |
693 | } netxen_flash_map_t; |
694 | ||
0d04761d MT |
695 | #define NETXEN_USER_START_OLD NETXEN_PXE_START /* for backward compatibility */ |
696 | ||
697 | #define NETXEN_FLASH_START (NETXEN_CRBINIT_START) | |
698 | #define NETXEN_INIT_SECTOR (0) | |
699 | #define NETXEN_PRIMARY_START (NETXEN_BOOTLD_START) | |
700 | #define NETXEN_FLASH_CRBINIT_SIZE (0x4000) | |
701 | #define NETXEN_FLASH_BRDCFG_SIZE (sizeof(struct netxen_board_info)) | |
702 | #define NETXEN_FLASH_USER_SIZE (sizeof(struct netxen_user_info)/sizeof(u32)) | |
703 | #define NETXEN_FLASH_SECONDARY_SIZE (NETXEN_USER_START-NETXEN_SECONDARY_START) | |
704 | #define NETXEN_NUM_PRIMARY_SECTORS (0x20) | |
705 | #define NETXEN_NUM_CONFIG_SECTORS (1) | |
ed25ffa1 AK |
706 | #define PFX "NetXen: " |
707 | extern char netxen_nic_driver_name[]; | |
3d396eb1 AK |
708 | |
709 | /* Note: Make sure to not call this before adapter->port is valid */ | |
710 | #if !defined(NETXEN_DEBUG) | |
711 | #define DPRINTK(klevel, fmt, args...) do { \ | |
712 | } while (0) | |
713 | #else | |
714 | #define DPRINTK(klevel, fmt, args...) do { \ | |
715 | printk(KERN_##klevel PFX "%s: %s: " fmt, __FUNCTION__,\ | |
3176ff3e MT |
716 | (adapter != NULL && adapter->netdev != NULL) ? \ |
717 | adapter->netdev->name : NULL, \ | |
3d396eb1 AK |
718 | ## args); } while(0) |
719 | #endif | |
720 | ||
721 | /* Number of status descriptors to handle per interrupt */ | |
722 | #define MAX_STATUS_HANDLE (128) | |
723 | ||
724 | /* | |
725 | * netxen_skb_frag{} is to contain mapping info for each SG list. This | |
726 | * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}. | |
727 | */ | |
728 | struct netxen_skb_frag { | |
729 | u64 dma; | |
730 | u32 length; | |
731 | }; | |
732 | ||
6c80b18d MT |
733 | #define _netxen_set_bits(config_word, start, bits, val) {\ |
734 | unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));\ | |
735 | unsigned long long __tvalue = (val); \ | |
736 | (config_word) &= ~__tmask; \ | |
737 | (config_word) |= (((__tvalue) << (start)) & __tmask); \ | |
738 | } | |
4790654c | 739 | |
6c80b18d MT |
740 | #define _netxen_clear_bits(config_word, start, bits) {\ |
741 | unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start)); \ | |
742 | (config_word) &= ~__tmask; \ | |
4790654c | 743 | } |
6c80b18d | 744 | |
3d396eb1 AK |
745 | /* Following defines are for the state of the buffers */ |
746 | #define NETXEN_BUFFER_FREE 0 | |
747 | #define NETXEN_BUFFER_BUSY 1 | |
748 | ||
749 | /* | |
750 | * There will be one netxen_buffer per skb packet. These will be | |
751 | * used to save the dma info for pci_unmap_page() | |
752 | */ | |
753 | struct netxen_cmd_buffer { | |
754 | struct sk_buff *skb; | |
755 | struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1]; | |
756 | u32 total_length; | |
757 | u32 mss; | |
758 | u16 port; | |
759 | u8 cmd; | |
760 | u8 frag_count; | |
761 | unsigned long time_stamp; | |
762 | u32 state; | |
3d396eb1 AK |
763 | }; |
764 | ||
765 | /* In rx_buffer, we do not need multiple fragments as is a single buffer */ | |
766 | struct netxen_rx_buffer { | |
767 | struct sk_buff *skb; | |
768 | u64 dma; | |
769 | u16 ref_handle; | |
770 | u16 state; | |
ed25ffa1 AK |
771 | u32 lro_expected_frags; |
772 | u32 lro_current_frags; | |
773 | u32 lro_length; | |
3d396eb1 AK |
774 | }; |
775 | ||
776 | /* Board types */ | |
777 | #define NETXEN_NIC_GBE 0x01 | |
778 | #define NETXEN_NIC_XGBE 0x02 | |
779 | ||
780 | /* | |
781 | * One hardware_context{} per adapter | |
782 | * contains interrupt info as well shared hardware info. | |
783 | */ | |
784 | struct netxen_hardware_context { | |
785 | struct pci_dev *pdev; | |
cb8011ad AK |
786 | void __iomem *pci_base0; |
787 | void __iomem *pci_base1; | |
788 | void __iomem *pci_base2; | |
6c80b18d MT |
789 | unsigned long first_page_group_end; |
790 | unsigned long first_page_group_start; | |
ed25ffa1 AK |
791 | void __iomem *db_base; |
792 | unsigned long db_len; | |
cb8011ad | 793 | |
3d396eb1 AK |
794 | u8 revision_id; |
795 | u16 board_type; | |
796 | u16 max_ports; | |
797 | struct netxen_board_info boardcfg; | |
798 | u32 xg_linkup; | |
cb8011ad | 799 | u32 qg_linksup; |
3d396eb1 AK |
800 | /* Address of cmd ring in Phantom */ |
801 | struct cmd_desc_type0 *cmd_desc_head; | |
cb8011ad | 802 | struct pci_dev *cmd_desc_pdev; |
3d396eb1 AK |
803 | dma_addr_t cmd_desc_phys_addr; |
804 | struct netxen_adapter *adapter; | |
13ba9c77 | 805 | int pci_func; |
3d396eb1 AK |
806 | }; |
807 | ||
ed25ffa1 AK |
808 | #define RCV_RING_LRO RCV_DESC_LRO |
809 | ||
3d396eb1 AK |
810 | #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ |
811 | #define ETHERNET_FCS_SIZE 4 | |
812 | ||
813 | struct netxen_adapter_stats { | |
3176ff3e MT |
814 | u64 rcvdbadskb; |
815 | u64 xmitcalled; | |
816 | u64 xmitedframes; | |
817 | u64 xmitfinished; | |
818 | u64 badskblen; | |
819 | u64 nocmddescriptor; | |
820 | u64 polled; | |
821 | u64 uphappy; | |
822 | u64 updropped; | |
823 | u64 uplcong; | |
824 | u64 uphcong; | |
825 | u64 upmcong; | |
826 | u64 updunno; | |
827 | u64 skbfreed; | |
828 | u64 txdropped; | |
829 | u64 txnullskb; | |
830 | u64 csummed; | |
831 | u64 no_rcv; | |
832 | u64 rxbytes; | |
833 | u64 txbytes; | |
834 | u64 ints; | |
3d396eb1 AK |
835 | }; |
836 | ||
837 | /* | |
838 | * Rcv Descriptor Context. One such per Rcv Descriptor. There may | |
839 | * be one Rcv Descriptor for normal packets, one for jumbo and may be others. | |
840 | */ | |
841 | struct netxen_rcv_desc_ctx { | |
842 | u32 flags; | |
843 | u32 producer; | |
844 | u32 rcv_pending; /* Num of bufs posted in phantom */ | |
3d396eb1 | 845 | dma_addr_t phys_addr; |
cb8011ad | 846 | struct pci_dev *phys_pdev; |
3d396eb1 AK |
847 | struct rcv_desc *desc_head; /* address of rx ring in Phantom */ |
848 | u32 max_rx_desc_count; | |
849 | u32 dma_size; | |
850 | u32 skb_size; | |
851 | struct netxen_rx_buffer *rx_buf_arr; /* rx buffers for receive */ | |
852 | int begin_alloc; | |
853 | }; | |
854 | ||
855 | /* | |
856 | * Receive context. There is one such structure per instance of the | |
857 | * receive processing. Any state information that is relevant to | |
858 | * the receive, and is must be in this structure. The global data may be | |
859 | * present elsewhere. | |
860 | */ | |
861 | struct netxen_recv_context { | |
862 | struct netxen_rcv_desc_ctx rcv_desc[NUM_RCV_DESC_RINGS]; | |
863 | u32 status_rx_producer; | |
864 | u32 status_rx_consumer; | |
865 | dma_addr_t rcv_status_desc_phys_addr; | |
cb8011ad | 866 | struct pci_dev *rcv_status_desc_pdev; |
3d396eb1 AK |
867 | struct status_desc *rcv_status_desc_head; |
868 | }; | |
869 | ||
870 | #define NETXEN_NIC_MSI_ENABLED 0x02 | |
ed25ffa1 AK |
871 | #define NETXEN_DMA_MASK 0xfffffffe |
872 | #define NETXEN_DB_MAPSIZE_BYTES 0x1000 | |
873 | ||
874 | struct netxen_dummy_dma { | |
875 | void *addr; | |
876 | dma_addr_t phys_addr; | |
877 | }; | |
3d396eb1 | 878 | |
3d396eb1 AK |
879 | struct netxen_adapter { |
880 | struct netxen_hardware_context ahw; | |
4790654c | 881 | |
3176ff3e MT |
882 | struct netxen_adapter *master; |
883 | struct net_device *netdev; | |
884 | struct pci_dev *pdev; | |
bea3348e | 885 | struct napi_struct napi; |
6c80b18d | 886 | struct net_device_stats net_stats; |
3176ff3e MT |
887 | unsigned char mac_addr[ETH_ALEN]; |
888 | int mtu; | |
889 | int portnum; | |
890 | ||
3d396eb1 AK |
891 | spinlock_t tx_lock; |
892 | spinlock_t lock; | |
893 | struct work_struct watchdog_task; | |
3d396eb1 | 894 | struct timer_list watchdog_timer; |
3176ff3e | 895 | struct work_struct tx_timeout_task; |
3d396eb1 AK |
896 | |
897 | u32 curr_window; | |
898 | ||
899 | u32 cmd_producer; | |
f305f789 | 900 | __le32 *cmd_consumer; |
3d396eb1 AK |
901 | |
902 | u32 last_cmd_consumer; | |
903 | u32 max_tx_desc_count; | |
904 | u32 max_rx_desc_count; | |
905 | u32 max_jumbo_rx_desc_count; | |
ed25ffa1 | 906 | u32 max_lro_rx_desc_count; |
3d396eb1 AK |
907 | /* Num of instances active on cmd buffer ring */ |
908 | u32 proc_cmd_buf_counter; | |
909 | ||
910 | u32 num_threads, total_threads; /*Use to keep track of xmit threads */ | |
911 | ||
912 | u32 flags; | |
913 | u32 irq; | |
914 | int driver_mismatch; | |
cb8011ad | 915 | u32 temp; |
3d396eb1 AK |
916 | |
917 | struct netxen_adapter_stats stats; | |
4790654c | 918 | |
3176ff3e MT |
919 | u16 portno; |
920 | u16 link_speed; | |
921 | u16 link_duplex; | |
922 | u16 state; | |
923 | u16 link_autoneg; | |
200eef20 | 924 | int rx_csum; |
3176ff3e MT |
925 | int status; |
926 | spinlock_t stats_lock; | |
3d396eb1 AK |
927 | |
928 | struct netxen_cmd_buffer *cmd_buf_arr; /* Command buffers for xmit */ | |
929 | ||
930 | /* | |
931 | * Receive instances. These can be either one per port, | |
932 | * or one per peg, etc. | |
933 | */ | |
934 | struct netxen_recv_context recv_ctx[MAX_RCV_CTX]; | |
935 | ||
936 | int is_up; | |
ed25ffa1 AK |
937 | struct netxen_dummy_dma dummy_dma; |
938 | ||
939 | /* Context interface shared between card and host */ | |
940 | struct netxen_ring_ctx *ctx_desc; | |
941 | struct pci_dev *ctx_desc_pdev; | |
942 | dma_addr_t ctx_desc_phys_addr; | |
2d1a3bbd | 943 | int intr_scheme; |
443be796 | 944 | int msi_mode; |
13ba9c77 MT |
945 | int (*enable_phy_interrupts) (struct netxen_adapter *); |
946 | int (*disable_phy_interrupts) (struct netxen_adapter *); | |
80922fbc | 947 | void (*handle_phy_intr) (struct netxen_adapter *); |
3176ff3e MT |
948 | int (*macaddr_set) (struct netxen_adapter *, netxen_ethernet_macaddr_t); |
949 | int (*set_mtu) (struct netxen_adapter *, int); | |
950 | int (*set_promisc) (struct netxen_adapter *, netxen_niu_prom_mode_t); | |
951 | int (*unset_promisc) (struct netxen_adapter *, netxen_niu_prom_mode_t); | |
13ba9c77 MT |
952 | int (*phy_read) (struct netxen_adapter *, long reg, u32 *); |
953 | int (*phy_write) (struct netxen_adapter *, long reg, u32 val); | |
80922fbc AK |
954 | int (*init_port) (struct netxen_adapter *, int); |
955 | void (*init_niu) (struct netxen_adapter *); | |
3176ff3e | 956 | int (*stop_port) (struct netxen_adapter *); |
3d396eb1 AK |
957 | }; /* netxen_adapter structure */ |
958 | ||
96acb6eb DP |
959 | /* |
960 | * NetXen dma watchdog control structure | |
961 | * | |
962 | * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive | |
963 | * Bit 1 : disable_request => 1 req disable dma watchdog | |
964 | * Bit 2 : enable_request => 1 req enable dma watchdog | |
965 | * Bit 3-31 : unused | |
966 | */ | |
967 | ||
968 | #define netxen_set_dma_watchdog_disable_req(config_word) \ | |
969 | _netxen_set_bits(config_word, 1, 1, 1) | |
970 | #define netxen_set_dma_watchdog_enable_req(config_word) \ | |
971 | _netxen_set_bits(config_word, 2, 1, 1) | |
972 | #define netxen_get_dma_watchdog_enabled(config_word) \ | |
973 | ((config_word) & 0x1) | |
974 | #define netxen_get_dma_watchdog_disabled(config_word) \ | |
975 | (((config_word) >> 1) & 0x1) | |
976 | ||
3d396eb1 AK |
977 | /* Max number of xmit producer threads that can run simultaneously */ |
978 | #define MAX_XMIT_PRODUCERS 16 | |
979 | ||
cb8011ad AK |
980 | #define PCI_OFFSET_FIRST_RANGE(adapter, off) \ |
981 | ((adapter)->ahw.pci_base0 + (off)) | |
982 | #define PCI_OFFSET_SECOND_RANGE(adapter, off) \ | |
983 | ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START) | |
984 | #define PCI_OFFSET_THIRD_RANGE(adapter, off) \ | |
985 | ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START) | |
986 | ||
987 | static inline void __iomem *pci_base_offset(struct netxen_adapter *adapter, | |
988 | unsigned long off) | |
989 | { | |
990 | if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) { | |
991 | return (adapter->ahw.pci_base0 + off); | |
992 | } else if ((off < SECOND_PAGE_GROUP_END) && | |
993 | (off >= SECOND_PAGE_GROUP_START)) { | |
994 | return (adapter->ahw.pci_base1 + off - SECOND_PAGE_GROUP_START); | |
995 | } else if ((off < THIRD_PAGE_GROUP_END) && | |
996 | (off >= THIRD_PAGE_GROUP_START)) { | |
997 | return (adapter->ahw.pci_base2 + off - THIRD_PAGE_GROUP_START); | |
998 | } | |
999 | return NULL; | |
1000 | } | |
1001 | ||
1002 | static inline void __iomem *pci_base(struct netxen_adapter *adapter, | |
1003 | unsigned long off) | |
1004 | { | |
1005 | if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) { | |
1006 | return adapter->ahw.pci_base0; | |
1007 | } else if ((off < SECOND_PAGE_GROUP_END) && | |
1008 | (off >= SECOND_PAGE_GROUP_START)) { | |
1009 | return adapter->ahw.pci_base1; | |
1010 | } else if ((off < THIRD_PAGE_GROUP_END) && | |
1011 | (off >= THIRD_PAGE_GROUP_START)) { | |
1012 | return adapter->ahw.pci_base2; | |
1013 | } | |
1014 | return NULL; | |
1015 | } | |
1016 | ||
13ba9c77 MT |
1017 | int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter); |
1018 | int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter); | |
1019 | int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter); | |
1020 | int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter); | |
3d396eb1 AK |
1021 | void netxen_nic_xgbe_handle_phy_intr(struct netxen_adapter *adapter); |
1022 | void netxen_nic_gbe_handle_phy_intr(struct netxen_adapter *adapter); | |
13ba9c77 | 1023 | int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg, |
a608ab9c | 1024 | __u32 * readval); |
13ba9c77 | 1025 | int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, |
a608ab9c | 1026 | long reg, __u32 val); |
3d396eb1 AK |
1027 | |
1028 | /* Functions available from netxen_nic_hw.c */ | |
3176ff3e MT |
1029 | int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu); |
1030 | int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu); | |
3d396eb1 AK |
1031 | void netxen_nic_init_niu_gb(struct netxen_adapter *adapter); |
1032 | void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw); | |
1033 | void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val); | |
1034 | int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off); | |
1035 | void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value); | |
1036 | void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value); | |
1037 | ||
1038 | int netxen_nic_get_board_info(struct netxen_adapter *adapter); | |
1039 | int netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data, | |
1040 | int len); | |
1041 | int netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data, | |
1042 | int len); | |
1043 | void netxen_crb_writelit_adapter(struct netxen_adapter *adapter, | |
1044 | unsigned long off, int data); | |
1045 | ||
1046 | /* Functions from netxen_nic_init.c */ | |
ed25ffa1 AK |
1047 | void netxen_free_adapter_offload(struct netxen_adapter *adapter); |
1048 | int netxen_initialize_adapter_offload(struct netxen_adapter *adapter); | |
96acb6eb DP |
1049 | int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val); |
1050 | int netxen_load_firmware(struct netxen_adapter *adapter); | |
3d396eb1 AK |
1051 | int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose); |
1052 | int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp); | |
4790654c | 1053 | int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr, |
27d2ab54 | 1054 | u8 *bytes, size_t size); |
4790654c | 1055 | int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr, |
27d2ab54 AK |
1056 | u8 *bytes, size_t size); |
1057 | int netxen_flash_unlock(struct netxen_adapter *adapter); | |
1058 | int netxen_backup_crbinit(struct netxen_adapter *adapter); | |
1059 | int netxen_flash_erase_secondary(struct netxen_adapter *adapter); | |
1060 | int netxen_flash_erase_primary(struct netxen_adapter *adapter); | |
e45d9ab4 | 1061 | void netxen_halt_pegs(struct netxen_adapter *adapter); |
27d2ab54 | 1062 | |
cb8011ad | 1063 | int netxen_rom_se(struct netxen_adapter *adapter, int addr); |
3d396eb1 AK |
1064 | |
1065 | /* Functions from netxen_nic_isr.c */ | |
c27e6721 | 1066 | int netxen_nic_link_ok(struct netxen_adapter *adapter); |
3d396eb1 AK |
1067 | void netxen_initialize_adapter_sw(struct netxen_adapter *adapter); |
1068 | void netxen_initialize_adapter_hw(struct netxen_adapter *adapter); | |
cb8011ad AK |
1069 | void *netxen_alloc(struct pci_dev *pdev, size_t sz, dma_addr_t * ptr, |
1070 | struct pci_dev **used_dev); | |
3d396eb1 AK |
1071 | void netxen_initialize_adapter_ops(struct netxen_adapter *adapter); |
1072 | int netxen_init_firmware(struct netxen_adapter *adapter); | |
1073 | void netxen_free_hw_resources(struct netxen_adapter *adapter); | |
1074 | void netxen_tso_check(struct netxen_adapter *adapter, | |
1075 | struct cmd_desc_type0 *desc, struct sk_buff *skb); | |
1076 | int netxen_nic_hw_resources(struct netxen_adapter *adapter); | |
1077 | void netxen_nic_clear_stats(struct netxen_adapter *adapter); | |
6d5aefb8 | 1078 | void netxen_watchdog_task(struct work_struct *work); |
3d396eb1 AK |
1079 | void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, |
1080 | u32 ringid); | |
05aaa02d | 1081 | int netxen_process_cmd_ring(struct netxen_adapter *adapter); |
3d396eb1 AK |
1082 | u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctx, int max); |
1083 | void netxen_nic_set_multi(struct net_device *netdev); | |
1084 | int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu); | |
1085 | int netxen_nic_set_mac(struct net_device *netdev, void *p); | |
1086 | struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev); | |
1087 | ||
cb8011ad AK |
1088 | |
1089 | /* | |
1090 | * NetXen Board information | |
1091 | */ | |
1092 | ||
1093 | #define NETXEN_MAX_SHORT_NAME 16 | |
71bd7877 | 1094 | struct netxen_brdinfo { |
cb8011ad AK |
1095 | netxen_brdtype_t brdtype; /* type of board */ |
1096 | long ports; /* max no of physical ports */ | |
1097 | char short_name[NETXEN_MAX_SHORT_NAME]; | |
71bd7877 | 1098 | }; |
cb8011ad | 1099 | |
71bd7877 | 1100 | static const struct netxen_brdinfo netxen_boards[] = { |
cb8011ad AK |
1101 | {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"}, |
1102 | {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"}, | |
1103 | {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"}, | |
1104 | {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"}, | |
1105 | {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"}, | |
1106 | {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"}, | |
1107 | }; | |
1108 | ||
ff8ac609 | 1109 | #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards) |
cb8011ad AK |
1110 | |
1111 | static inline void get_brd_port_by_type(u32 type, int *ports) | |
1112 | { | |
1113 | int i, found = 0; | |
1114 | for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) { | |
1115 | if (netxen_boards[i].brdtype == type) { | |
1116 | *ports = netxen_boards[i].ports; | |
1117 | found = 1; | |
1118 | break; | |
1119 | } | |
1120 | } | |
1121 | if (!found) | |
1122 | *ports = 0; | |
1123 | } | |
1124 | ||
1125 | static inline void get_brd_name_by_type(u32 type, char *name) | |
1126 | { | |
1127 | int i, found = 0; | |
1128 | for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) { | |
1129 | if (netxen_boards[i].brdtype == type) { | |
1130 | strcpy(name, netxen_boards[i].short_name); | |
1131 | found = 1; | |
1132 | break; | |
1133 | } | |
1134 | ||
3d396eb1 | 1135 | } |
cb8011ad AK |
1136 | if (!found) |
1137 | name = "Unknown"; | |
3d396eb1 AK |
1138 | } |
1139 | ||
96acb6eb DP |
1140 | static inline int |
1141 | dma_watchdog_shutdown_request(struct netxen_adapter *adapter) | |
1142 | { | |
1143 | u32 ctrl; | |
1144 | ||
1145 | /* check if already inactive */ | |
1146 | if (netxen_nic_hw_read_wx(adapter, | |
1147 | NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4)) | |
1148 | printk(KERN_ERR "failed to read dma watchdog status\n"); | |
1149 | ||
1150 | if (netxen_get_dma_watchdog_enabled(ctrl) == 0) | |
1151 | return 1; | |
1152 | ||
1153 | /* Send the disable request */ | |
1154 | netxen_set_dma_watchdog_disable_req(ctrl); | |
1155 | netxen_crb_writelit_adapter(adapter, | |
1156 | NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl); | |
1157 | ||
1158 | return 0; | |
1159 | } | |
1160 | ||
1161 | static inline int | |
1162 | dma_watchdog_shutdown_poll_result(struct netxen_adapter *adapter) | |
1163 | { | |
1164 | u32 ctrl; | |
1165 | ||
1166 | if (netxen_nic_hw_read_wx(adapter, | |
1167 | NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4)) | |
1168 | printk(KERN_ERR "failed to read dma watchdog status\n"); | |
1169 | ||
ceded32f | 1170 | return (netxen_get_dma_watchdog_enabled(ctrl) == 0); |
96acb6eb DP |
1171 | } |
1172 | ||
1173 | static inline int | |
1174 | dma_watchdog_wakeup(struct netxen_adapter *adapter) | |
1175 | { | |
1176 | u32 ctrl; | |
1177 | ||
1178 | if (netxen_nic_hw_read_wx(adapter, | |
1179 | NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4)) | |
1180 | printk(KERN_ERR "failed to read dma watchdog status\n"); | |
1181 | ||
1182 | if (netxen_get_dma_watchdog_enabled(ctrl)) | |
1183 | return 1; | |
1184 | ||
1185 | /* send the wakeup request */ | |
1186 | netxen_set_dma_watchdog_enable_req(ctrl); | |
1187 | ||
1188 | netxen_crb_writelit_adapter(adapter, | |
1189 | NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl); | |
1190 | ||
1191 | return 0; | |
1192 | } | |
1193 | ||
1194 | ||
3d396eb1 | 1195 | int netxen_is_flash_supported(struct netxen_adapter *adapter); |
f305f789 | 1196 | int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 mac[]); |
3d396eb1 AK |
1197 | extern void netxen_change_ringparam(struct netxen_adapter *adapter); |
1198 | extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, | |
1199 | int *valp); | |
1200 | ||
1201 | extern struct ethtool_ops netxen_nic_ethtool_ops; | |
1202 | ||
6c80b18d | 1203 | extern int physical_port[]; /* physical port # from virtual port.*/ |
3d396eb1 | 1204 | #endif /* __NETXEN_NIC_H_ */ |