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3d396eb1 AK |
1 | /* |
2 | * Copyright (C) 2003 - 2006 NetXen, Inc. | |
3 | * All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, | |
18 | * MA 02111-1307, USA. | |
19 | * | |
20 | * The full GNU General Public License is included in this distribution | |
21 | * in the file called LICENSE. | |
22 | * | |
23 | * Contact Information: | |
24 | * info@netxen.com | |
25 | * NetXen, | |
26 | * 3965 Freedom Circle, Fourth floor, | |
27 | * Santa Clara, CA 95054 | |
28 | */ | |
29 | ||
30 | #ifndef _NETXEN_NIC_H_ | |
31 | #define _NETXEN_NIC_H_ | |
32 | ||
3d396eb1 AK |
33 | #include <linux/module.h> |
34 | #include <linux/kernel.h> | |
35 | #include <linux/types.h> | |
36 | #include <linux/compiler.h> | |
37 | #include <linux/slab.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/init.h> | |
40 | #include <linux/ioport.h> | |
41 | #include <linux/pci.h> | |
42 | #include <linux/netdevice.h> | |
43 | #include <linux/etherdevice.h> | |
44 | #include <linux/ip.h> | |
45 | #include <linux/in.h> | |
46 | #include <linux/tcp.h> | |
47 | #include <linux/skbuff.h> | |
48 | #include <linux/version.h> | |
49 | ||
50 | #include <linux/ethtool.h> | |
51 | #include <linux/mii.h> | |
52 | #include <linux/interrupt.h> | |
53 | #include <linux/timer.h> | |
54 | ||
55 | #include <linux/mm.h> | |
56 | #include <linux/mman.h> | |
57 | ||
58 | #include <asm/system.h> | |
59 | #include <asm/io.h> | |
60 | #include <asm/byteorder.h> | |
61 | #include <asm/uaccess.h> | |
62 | #include <asm/pgtable.h> | |
63 | ||
64 | #include "netxen_nic_hw.h" | |
65 | ||
cb8011ad | 66 | #define NETXEN_NIC_BUILD_NO "5" |
3d396eb1 AK |
67 | #define _NETXEN_NIC_LINUX_MAJOR 2 |
68 | #define _NETXEN_NIC_LINUX_MINOR 3 | |
cb8011ad AK |
69 | #define _NETXEN_NIC_LINUX_SUBVERSION 59 |
70 | #define NETXEN_NIC_LINUX_VERSIONID "2.3.59" "-" NETXEN_NIC_BUILD_NO | |
71 | #define NETXEN_NIC_FW_VERSIONID "2.3.59" | |
3d396eb1 AK |
72 | |
73 | #define RCV_DESC_RINGSIZE \ | |
74 | (sizeof(struct rcv_desc) * adapter->max_rx_desc_count) | |
75 | #define STATUS_DESC_RINGSIZE \ | |
76 | (sizeof(struct status_desc)* adapter->max_rx_desc_count) | |
77 | #define TX_RINGSIZE \ | |
78 | (sizeof(struct netxen_cmd_buffer) * adapter->max_tx_desc_count) | |
79 | #define RCV_BUFFSIZE \ | |
80 | (sizeof(struct netxen_rx_buffer) * rcv_desc->max_rx_desc_count) | |
81 | #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a))) | |
82 | ||
83 | #define NETXEN_NETDEV_STATUS 0x1 | |
84 | ||
85 | #define ADDR_IN_WINDOW1(off) \ | |
86 | ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0 | |
87 | ||
88 | /* | |
89 | * normalize a 64MB crb address to 32MB PCI window | |
90 | * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1 | |
91 | */ | |
cb8011ad AK |
92 | #define NETXEN_CRB_NORMAL(reg) \ |
93 | (reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST | |
94 | ||
3d396eb1 | 95 | #define NETXEN_CRB_NORMALIZE(adapter, reg) \ |
cb8011ad AK |
96 | pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg)) |
97 | ||
98 | #define FIRST_PAGE_GROUP_START 0 | |
99 | #define FIRST_PAGE_GROUP_END 0x400000 | |
100 | ||
101 | #define SECOND_PAGE_GROUP_START 0x4000000 | |
102 | #define SECOND_PAGE_GROUP_END 0x66BC000 | |
103 | ||
104 | #define THIRD_PAGE_GROUP_START 0x70E4000 | |
105 | #define THIRD_PAGE_GROUP_END 0x8000000 | |
106 | ||
107 | #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START | |
108 | #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START | |
109 | #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START | |
3d396eb1 AK |
110 | |
111 | #define MAX_RX_BUFFER_LENGTH 2000 | |
112 | #define MAX_RX_JUMBO_BUFFER_LENGTH 9046 | |
113 | #define RX_DMA_MAP_LEN (MAX_RX_BUFFER_LENGTH - NET_IP_ALIGN) | |
114 | #define RX_JUMBO_DMA_MAP_LEN \ | |
115 | (MAX_RX_JUMBO_BUFFER_LENGTH - NET_IP_ALIGN) | |
116 | #define NETXEN_ROM_ROUNDUP 0x80000000ULL | |
117 | ||
118 | /* | |
119 | * Maximum number of ring contexts | |
120 | */ | |
121 | #define MAX_RING_CTX 1 | |
122 | ||
123 | /* Opcodes to be used with the commands */ | |
124 | enum { | |
125 | TX_ETHER_PKT = 0x01, | |
126 | /* The following opcodes are for IP checksum */ | |
127 | TX_TCP_PKT, | |
128 | TX_UDP_PKT, | |
129 | TX_IP_PKT, | |
130 | TX_TCP_LSO, | |
131 | TX_IPSEC, | |
132 | TX_IPSEC_CMD | |
133 | }; | |
134 | ||
135 | /* The following opcodes are for internal consumption. */ | |
136 | #define NETXEN_CONTROL_OP 0x10 | |
137 | #define PEGNET_REQUEST 0x11 | |
138 | ||
139 | #define MAX_NUM_CARDS 4 | |
140 | ||
141 | #define MAX_BUFFERS_PER_CMD 32 | |
142 | ||
143 | /* | |
144 | * Following are the states of the Phantom. Phantom will set them and | |
145 | * Host will read to check if the fields are correct. | |
146 | */ | |
147 | #define PHAN_INITIALIZE_START 0xff00 | |
148 | #define PHAN_INITIALIZE_FAILED 0xffff | |
149 | #define PHAN_INITIALIZE_COMPLETE 0xff01 | |
150 | ||
151 | /* Host writes the following to notify that it has done the init-handshake */ | |
152 | #define PHAN_INITIALIZE_ACK 0xf00f | |
153 | ||
154 | #define NUM_RCV_DESC_RINGS 2 /* No of Rcv Descriptor contexts */ | |
155 | ||
156 | /* descriptor types */ | |
157 | #define RCV_DESC_NORMAL 0x01 | |
158 | #define RCV_DESC_JUMBO 0x02 | |
159 | #define RCV_DESC_NORMAL_CTXID 0 | |
160 | #define RCV_DESC_JUMBO_CTXID 1 | |
161 | ||
162 | #define RCV_DESC_TYPE(ID) \ | |
163 | ((ID == RCV_DESC_JUMBO_CTXID) ? RCV_DESC_JUMBO : RCV_DESC_NORMAL) | |
164 | ||
165 | #define MAX_CMD_DESCRIPTORS 1024 | |
166 | #define MAX_RCV_DESCRIPTORS 32768 | |
167 | #define MAX_JUMBO_RCV_DESCRIPTORS 1024 | |
168 | #define MAX_RCVSTATUS_DESCRIPTORS MAX_RCV_DESCRIPTORS | |
169 | #define MAX_JUMBO_RCV_DESC MAX_JUMBO_RCV_DESCRIPTORS | |
170 | #define MAX_RCV_DESC MAX_RCV_DESCRIPTORS | |
171 | #define MAX_RCVSTATUS_DESC MAX_RCV_DESCRIPTORS | |
172 | #define NUM_RCV_DESC (MAX_RCV_DESC + MAX_JUMBO_RCV_DESCRIPTORS) | |
173 | #define MAX_EPG_DESCRIPTORS (MAX_CMD_DESCRIPTORS * 8) | |
174 | ||
175 | #define MIN_TX_COUNT 4096 | |
176 | #define MIN_RX_COUNT 4096 | |
177 | ||
178 | #define MAX_FRAME_SIZE 0x10000 /* 64K MAX size for LSO */ | |
179 | ||
180 | #define PHAN_PEG_RCV_INITIALIZED 0xff01 | |
181 | #define PHAN_PEG_RCV_START_INITIALIZE 0xff00 | |
182 | ||
183 | #define get_next_index(index, length) \ | |
184 | (((index) + 1) & ((length) - 1)) | |
185 | ||
186 | #define get_index_range(index,length,count) \ | |
187 | (((index) + (count)) & ((length) - 1)) | |
188 | ||
189 | /* | |
190 | * Following data structures describe the descriptors that will be used. | |
191 | * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when | |
192 | * we are doing LSO (above the 1500 size packet) only. | |
193 | */ | |
194 | ||
195 | /* | |
196 | * The size of reference handle been changed to 16 bits to pass the MSS fields | |
197 | * for the LSO packet | |
198 | */ | |
199 | ||
200 | #define FLAGS_CHECKSUM_ENABLED 0x01 | |
201 | #define FLAGS_LSO_ENABLED 0x02 | |
202 | #define FLAGS_IPSEC_SA_ADD 0x04 | |
203 | #define FLAGS_IPSEC_SA_DELETE 0x08 | |
204 | #define FLAGS_VLAN_TAGGED 0x10 | |
205 | ||
206 | #define CMD_DESC_TOTAL_LENGTH(cmd_desc) \ | |
207 | ((cmd_desc)->length_tcp_hdr & 0x00FFFFFF) | |
208 | #define CMD_DESC_TCP_HDR_OFFSET(cmd_desc) \ | |
209 | (((cmd_desc)->length_tcp_hdr >> 24) & 0x0FF) | |
210 | #define CMD_DESC_PORT(cmd_desc) ((cmd_desc)->port_ctxid & 0x0F) | |
211 | #define CMD_DESC_CTX_ID(cmd_desc) (((cmd_desc)->port_ctxid >> 4) & 0x0F) | |
212 | ||
213 | #define CMD_DESC_TOTAL_LENGTH_WRT(cmd_desc, var) \ | |
214 | ((cmd_desc)->length_tcp_hdr |= ((var) & 0x00FFFFFF)) | |
215 | #define CMD_DESC_TCP_HDR_OFFSET_WRT(cmd_desc, var) \ | |
216 | ((cmd_desc)->length_tcp_hdr |= (((var) << 24) & 0xFF000000)) | |
217 | #define CMD_DESC_PORT_WRT(cmd_desc, var) \ | |
218 | ((cmd_desc)->port_ctxid |= ((var) & 0x0F)) | |
219 | ||
220 | struct cmd_desc_type0 { | |
221 | u64 netxen_next; /* for fragments handled by Phantom */ | |
222 | union { | |
223 | struct { | |
224 | u32 addr_low_part2; | |
225 | u32 addr_high_part2; | |
226 | }; | |
227 | u64 addr_buffer2; | |
228 | }; | |
229 | ||
230 | /* Bit pattern: 0-23 total length, 24-32 tcp header offset */ | |
231 | u32 length_tcp_hdr; | |
232 | u8 ip_hdr_offset; /* For LSO only */ | |
233 | u8 num_of_buffers; /* total number of segments */ | |
234 | u8 flags; /* as defined above */ | |
235 | u8 opcode; | |
236 | ||
237 | u16 reference_handle; /* changed to u16 to add mss */ | |
238 | u16 mss; /* passed by NDIS_PACKET for LSO */ | |
239 | /* Bit pattern 0-3 port, 0-3 ctx id */ | |
240 | u8 port_ctxid; | |
241 | u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */ | |
242 | u16 conn_id; /* IPSec offoad only */ | |
243 | ||
244 | union { | |
245 | struct { | |
246 | u32 addr_low_part3; | |
247 | u32 addr_high_part3; | |
248 | }; | |
249 | u64 addr_buffer3; | |
250 | }; | |
251 | ||
252 | union { | |
253 | struct { | |
254 | u32 addr_low_part1; | |
255 | u32 addr_high_part1; | |
256 | }; | |
257 | u64 addr_buffer1; | |
258 | }; | |
259 | ||
260 | u16 buffer1_length; | |
261 | u16 buffer2_length; | |
262 | u16 buffer3_length; | |
263 | u16 buffer4_length; | |
264 | ||
265 | union { | |
266 | struct { | |
267 | u32 addr_low_part4; | |
268 | u32 addr_high_part4; | |
269 | }; | |
270 | u64 addr_buffer4; | |
271 | }; | |
272 | ||
273 | } __attribute__ ((aligned(64))); | |
274 | ||
275 | /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */ | |
276 | struct rcv_desc { | |
277 | u16 reference_handle; | |
278 | u16 reserved; | |
279 | u32 buffer_length; /* allocated buffer length (usually 2K) */ | |
280 | u64 addr_buffer; | |
281 | }; | |
282 | ||
283 | /* opcode field in status_desc */ | |
284 | #define RCV_NIC_PKT (0xA) | |
285 | #define STATUS_NIC_PKT ((RCV_NIC_PKT) << 12) | |
286 | ||
287 | /* for status field in status_desc */ | |
288 | #define STATUS_NEED_CKSUM (1) | |
289 | #define STATUS_CKSUM_OK (2) | |
290 | ||
291 | /* owner bits of status_desc */ | |
292 | #define STATUS_OWNER_HOST (0x1) | |
293 | #define STATUS_OWNER_PHANTOM (0x2) | |
294 | ||
295 | #define NETXEN_PROT_IP (1) | |
296 | #define NETXEN_PROT_UNKNOWN (0) | |
297 | ||
298 | /* Note: sizeof(status_desc) should always be a mutliple of 2 */ | |
299 | #define STATUS_DESC_PORT(status_desc) \ | |
300 | ((status_desc)->port_status_type_op & 0x0F) | |
301 | #define STATUS_DESC_STATUS(status_desc) \ | |
302 | (((status_desc)->port_status_type_op >> 4) & 0x0F) | |
303 | #define STATUS_DESC_TYPE(status_desc) \ | |
304 | (((status_desc)->port_status_type_op >> 8) & 0x0F) | |
305 | #define STATUS_DESC_OPCODE(status_desc) \ | |
306 | (((status_desc)->port_status_type_op >> 12) & 0x0F) | |
307 | ||
308 | struct status_desc { | |
309 | /* Bit pattern: 0-3 port, 4-7 status, 8-11 type, 12-15 opcode */ | |
310 | u16 port_status_type_op; | |
311 | u16 total_length; /* NIC mode */ | |
312 | u16 reference_handle; /* handle for the associated packet */ | |
313 | /* Bit pattern: 0-1 owner, 2-5 protocol */ | |
314 | u16 owner; /* Owner of the descriptor */ | |
315 | } __attribute__ ((aligned(8))); | |
316 | ||
317 | enum { | |
318 | NETXEN_RCV_PEG_0 = 0, | |
319 | NETXEN_RCV_PEG_1 | |
320 | }; | |
321 | /* The version of the main data structure */ | |
322 | #define NETXEN_BDINFO_VERSION 1 | |
323 | ||
324 | /* Magic number to let user know flash is programmed */ | |
325 | #define NETXEN_BDINFO_MAGIC 0x12345678 | |
326 | ||
327 | /* Max number of Gig ports on a Phantom board */ | |
328 | #define NETXEN_MAX_PORTS 4 | |
329 | ||
330 | typedef enum { | |
331 | NETXEN_BRDTYPE_P1_BD = 0x0000, | |
332 | NETXEN_BRDTYPE_P1_SB = 0x0001, | |
333 | NETXEN_BRDTYPE_P1_SMAX = 0x0002, | |
334 | NETXEN_BRDTYPE_P1_SOCK = 0x0003, | |
335 | ||
336 | NETXEN_BRDTYPE_P2_SOCK_31 = 0x0008, | |
337 | NETXEN_BRDTYPE_P2_SOCK_35 = 0x0009, | |
338 | NETXEN_BRDTYPE_P2_SB35_4G = 0x000a, | |
339 | NETXEN_BRDTYPE_P2_SB31_10G = 0x000b, | |
340 | NETXEN_BRDTYPE_P2_SB31_2G = 0x000c, | |
341 | ||
342 | NETXEN_BRDTYPE_P2_SB31_10G_IMEZ = 0x000d, | |
343 | NETXEN_BRDTYPE_P2_SB31_10G_HMEZ = 0x000e, | |
344 | NETXEN_BRDTYPE_P2_SB31_10G_CX4 = 0x000f | |
345 | } netxen_brdtype_t; | |
346 | ||
347 | typedef enum { | |
348 | NETXEN_BRDMFG_INVENTEC = 1 | |
349 | } netxen_brdmfg; | |
350 | ||
351 | typedef enum { | |
352 | MEM_ORG_128Mbx4 = 0x0, /* DDR1 only */ | |
353 | MEM_ORG_128Mbx8 = 0x1, /* DDR1 only */ | |
354 | MEM_ORG_128Mbx16 = 0x2, /* DDR1 only */ | |
355 | MEM_ORG_256Mbx4 = 0x3, | |
356 | MEM_ORG_256Mbx8 = 0x4, | |
357 | MEM_ORG_256Mbx16 = 0x5, | |
358 | MEM_ORG_512Mbx4 = 0x6, | |
359 | MEM_ORG_512Mbx8 = 0x7, | |
360 | MEM_ORG_512Mbx16 = 0x8, | |
361 | MEM_ORG_1Gbx4 = 0x9, | |
362 | MEM_ORG_1Gbx8 = 0xa, | |
363 | MEM_ORG_1Gbx16 = 0xb, | |
364 | MEM_ORG_2Gbx4 = 0xc, | |
365 | MEM_ORG_2Gbx8 = 0xd, | |
366 | MEM_ORG_2Gbx16 = 0xe, | |
367 | MEM_ORG_128Mbx32 = 0x10002, /* GDDR only */ | |
368 | MEM_ORG_256Mbx32 = 0x10005 /* GDDR only */ | |
369 | } netxen_mn_mem_org_t; | |
370 | ||
371 | typedef enum { | |
372 | MEM_ORG_512Kx36 = 0x0, | |
373 | MEM_ORG_1Mx36 = 0x1, | |
374 | MEM_ORG_2Mx36 = 0x2 | |
375 | } netxen_sn_mem_org_t; | |
376 | ||
377 | typedef enum { | |
378 | MEM_DEPTH_4MB = 0x1, | |
379 | MEM_DEPTH_8MB = 0x2, | |
380 | MEM_DEPTH_16MB = 0x3, | |
381 | MEM_DEPTH_32MB = 0x4, | |
382 | MEM_DEPTH_64MB = 0x5, | |
383 | MEM_DEPTH_128MB = 0x6, | |
384 | MEM_DEPTH_256MB = 0x7, | |
385 | MEM_DEPTH_512MB = 0x8, | |
386 | MEM_DEPTH_1GB = 0x9, | |
387 | MEM_DEPTH_2GB = 0xa, | |
388 | MEM_DEPTH_4GB = 0xb, | |
389 | MEM_DEPTH_8GB = 0xc, | |
390 | MEM_DEPTH_16GB = 0xd, | |
391 | MEM_DEPTH_32GB = 0xe | |
392 | } netxen_mem_depth_t; | |
393 | ||
394 | struct netxen_board_info { | |
395 | u32 header_version; | |
396 | ||
397 | u32 board_mfg; | |
398 | u32 board_type; | |
399 | u32 board_num; | |
400 | u32 chip_id; | |
401 | u32 chip_minor; | |
402 | u32 chip_major; | |
403 | u32 chip_pkg; | |
404 | u32 chip_lot; | |
405 | ||
406 | u32 port_mask; /* available niu ports */ | |
407 | u32 peg_mask; /* available pegs */ | |
408 | u32 icache_ok; /* can we run with icache? */ | |
409 | u32 dcache_ok; /* can we run with dcache? */ | |
410 | u32 casper_ok; | |
411 | ||
412 | u32 mac_addr_lo_0; | |
413 | u32 mac_addr_lo_1; | |
414 | u32 mac_addr_lo_2; | |
415 | u32 mac_addr_lo_3; | |
416 | ||
417 | /* MN-related config */ | |
418 | u32 mn_sync_mode; /* enable/ sync shift cclk/ sync shift mclk */ | |
419 | u32 mn_sync_shift_cclk; | |
420 | u32 mn_sync_shift_mclk; | |
421 | u32 mn_wb_en; | |
422 | u32 mn_crystal_freq; /* in MHz */ | |
423 | u32 mn_speed; /* in MHz */ | |
424 | u32 mn_org; | |
425 | u32 mn_depth; | |
426 | u32 mn_ranks_0; /* ranks per slot */ | |
427 | u32 mn_ranks_1; /* ranks per slot */ | |
428 | u32 mn_rd_latency_0; | |
429 | u32 mn_rd_latency_1; | |
430 | u32 mn_rd_latency_2; | |
431 | u32 mn_rd_latency_3; | |
432 | u32 mn_rd_latency_4; | |
433 | u32 mn_rd_latency_5; | |
434 | u32 mn_rd_latency_6; | |
435 | u32 mn_rd_latency_7; | |
436 | u32 mn_rd_latency_8; | |
437 | u32 mn_dll_val[18]; | |
438 | u32 mn_mode_reg; /* MIU DDR Mode Register */ | |
439 | u32 mn_ext_mode_reg; /* MIU DDR Extended Mode Register */ | |
440 | u32 mn_timing_0; /* MIU Memory Control Timing Rgister */ | |
441 | u32 mn_timing_1; /* MIU Extended Memory Ctrl Timing Register */ | |
442 | u32 mn_timing_2; /* MIU Extended Memory Ctrl Timing2 Register */ | |
443 | ||
444 | /* SN-related config */ | |
445 | u32 sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */ | |
446 | u32 sn_pt_mode; /* pass through mode */ | |
447 | u32 sn_ecc_en; | |
448 | u32 sn_wb_en; | |
449 | u32 sn_crystal_freq; | |
450 | u32 sn_speed; | |
451 | u32 sn_org; | |
452 | u32 sn_depth; | |
453 | u32 sn_dll_tap; | |
454 | u32 sn_rd_latency; | |
455 | ||
456 | u32 mac_addr_hi_0; | |
457 | u32 mac_addr_hi_1; | |
458 | u32 mac_addr_hi_2; | |
459 | u32 mac_addr_hi_3; | |
460 | ||
461 | u32 magic; /* indicates flash has been initialized */ | |
462 | ||
463 | u32 mn_rdimm; | |
464 | u32 mn_dll_override; | |
465 | ||
466 | }; | |
467 | ||
468 | #define FLASH_NUM_PORTS (4) | |
469 | ||
470 | struct netxen_flash_mac_addr { | |
471 | u32 flash_addr[32]; | |
472 | }; | |
473 | ||
474 | struct netxen_user_old_info { | |
475 | u8 flash_md5[16]; | |
476 | u8 crbinit_md5[16]; | |
477 | u8 brdcfg_md5[16]; | |
478 | /* bootloader */ | |
479 | u32 bootld_version; | |
480 | u32 bootld_size; | |
481 | u8 bootld_md5[16]; | |
482 | /* image */ | |
483 | u32 image_version; | |
484 | u32 image_size; | |
485 | u8 image_md5[16]; | |
486 | /* primary image status */ | |
487 | u32 primary_status; | |
488 | u32 secondary_present; | |
489 | ||
490 | /* MAC address , 4 ports */ | |
491 | struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS]; | |
492 | }; | |
493 | #define FLASH_NUM_MAC_PER_PORT 32 | |
494 | struct netxen_user_info { | |
495 | u8 flash_md5[16 * 64]; | |
496 | /* bootloader */ | |
497 | u32 bootld_version; | |
498 | u32 bootld_size; | |
499 | /* image */ | |
500 | u32 image_version; | |
501 | u32 image_size; | |
502 | /* primary image status */ | |
503 | u32 primary_status; | |
504 | u32 secondary_present; | |
505 | ||
506 | /* MAC address , 4 ports, 32 address per port */ | |
507 | u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT]; | |
508 | u32 sub_sys_id; | |
509 | u8 serial_num[32]; | |
510 | ||
511 | /* Any user defined data */ | |
512 | }; | |
513 | ||
514 | /* | |
515 | * Flash Layout - new format. | |
516 | */ | |
517 | struct netxen_new_user_info { | |
518 | u8 flash_md5[16 * 64]; | |
519 | /* bootloader */ | |
520 | u32 bootld_version; | |
521 | u32 bootld_size; | |
522 | /* image */ | |
523 | u32 image_version; | |
524 | u32 image_size; | |
525 | /* primary image status */ | |
526 | u32 primary_status; | |
527 | u32 secondary_present; | |
528 | ||
529 | /* MAC address , 4 ports, 32 address per port */ | |
530 | u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT]; | |
531 | u32 sub_sys_id; | |
532 | u8 serial_num[32]; | |
533 | ||
534 | /* Any user defined data */ | |
535 | }; | |
536 | ||
537 | #define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6 | |
538 | #define SECONDARY_IMAGE_ABSENT 0xffffffff | |
539 | #define PRIMARY_IMAGE_GOOD 0x5a5a5a5a | |
540 | #define PRIMARY_IMAGE_BAD 0xffffffff | |
541 | ||
542 | /* Flash memory map */ | |
543 | typedef enum { | |
544 | CRBINIT_START = 0, /* Crbinit section */ | |
545 | BRDCFG_START = 0x4000, /* board config */ | |
546 | INITCODE_START = 0x6000, /* pegtune code */ | |
547 | BOOTLD_START = 0x10000, /* bootld */ | |
548 | IMAGE_START = 0x43000, /* compressed image */ | |
549 | SECONDARY_START = 0x200000, /* backup images */ | |
550 | PXE_START = 0x3E0000, /* user defined region */ | |
551 | USER_START = 0x3E8000, /* User defined region for new boards */ | |
552 | FIXED_START = 0x3F0000 /* backup of crbinit */ | |
553 | } netxen_flash_map_t; | |
554 | ||
555 | #define USER_START_OLD PXE_START /* for backward compatibility */ | |
556 | ||
557 | #define FLASH_START (CRBINIT_START) | |
558 | #define INIT_SECTOR (0) | |
559 | #define PRIMARY_START (BOOTLD_START) | |
560 | #define FLASH_CRBINIT_SIZE (0x4000) | |
561 | #define FLASH_BRDCFG_SIZE (sizeof(struct netxen_board_info)) | |
562 | #define FLASH_USER_SIZE (sizeof(netxen_user_info)/sizeof(u32)) | |
563 | #define FLASH_SECONDARY_SIZE (USER_START-SECONDARY_START) | |
564 | #define NUM_PRIMARY_SECTORS (0x20) | |
565 | #define NUM_CONFIG_SECTORS (1) | |
566 | #define PFX "netxen: " | |
567 | ||
568 | /* Note: Make sure to not call this before adapter->port is valid */ | |
569 | #if !defined(NETXEN_DEBUG) | |
570 | #define DPRINTK(klevel, fmt, args...) do { \ | |
571 | } while (0) | |
572 | #else | |
573 | #define DPRINTK(klevel, fmt, args...) do { \ | |
574 | printk(KERN_##klevel PFX "%s: %s: " fmt, __FUNCTION__,\ | |
575 | (adapter != NULL && adapter->port != NULL && \ | |
576 | adapter->port[0] != NULL && \ | |
577 | adapter->port[0]->netdev != NULL) ? \ | |
578 | adapter->port[0]->netdev->name : NULL, \ | |
579 | ## args); } while(0) | |
580 | #endif | |
581 | ||
582 | /* Number of status descriptors to handle per interrupt */ | |
583 | #define MAX_STATUS_HANDLE (128) | |
584 | ||
585 | /* | |
586 | * netxen_skb_frag{} is to contain mapping info for each SG list. This | |
587 | * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}. | |
588 | */ | |
589 | struct netxen_skb_frag { | |
590 | u64 dma; | |
591 | u32 length; | |
592 | }; | |
593 | ||
594 | /* Following defines are for the state of the buffers */ | |
595 | #define NETXEN_BUFFER_FREE 0 | |
596 | #define NETXEN_BUFFER_BUSY 1 | |
597 | ||
598 | /* | |
599 | * There will be one netxen_buffer per skb packet. These will be | |
600 | * used to save the dma info for pci_unmap_page() | |
601 | */ | |
602 | struct netxen_cmd_buffer { | |
603 | struct sk_buff *skb; | |
604 | struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1]; | |
605 | u32 total_length; | |
606 | u32 mss; | |
607 | u16 port; | |
608 | u8 cmd; | |
609 | u8 frag_count; | |
610 | unsigned long time_stamp; | |
611 | u32 state; | |
612 | u32 no_of_descriptors; | |
613 | }; | |
614 | ||
615 | /* In rx_buffer, we do not need multiple fragments as is a single buffer */ | |
616 | struct netxen_rx_buffer { | |
617 | struct sk_buff *skb; | |
618 | u64 dma; | |
619 | u16 ref_handle; | |
620 | u16 state; | |
621 | }; | |
622 | ||
623 | /* Board types */ | |
624 | #define NETXEN_NIC_GBE 0x01 | |
625 | #define NETXEN_NIC_XGBE 0x02 | |
626 | ||
627 | /* | |
628 | * One hardware_context{} per adapter | |
629 | * contains interrupt info as well shared hardware info. | |
630 | */ | |
631 | struct netxen_hardware_context { | |
632 | struct pci_dev *pdev; | |
cb8011ad AK |
633 | void __iomem *pci_base0; |
634 | void __iomem *pci_base1; | |
635 | void __iomem *pci_base2; | |
636 | ||
3d396eb1 AK |
637 | u8 revision_id; |
638 | u16 board_type; | |
639 | u16 max_ports; | |
640 | struct netxen_board_info boardcfg; | |
641 | u32 xg_linkup; | |
cb8011ad | 642 | u32 qg_linksup; |
3d396eb1 AK |
643 | /* Address of cmd ring in Phantom */ |
644 | struct cmd_desc_type0 *cmd_desc_head; | |
cb8011ad AK |
645 | char *pauseaddr; |
646 | struct pci_dev *cmd_desc_pdev; | |
3d396eb1 | 647 | dma_addr_t cmd_desc_phys_addr; |
cb8011ad AK |
648 | dma_addr_t pause_physaddr; |
649 | struct pci_dev *pause_pdev; | |
3d396eb1 AK |
650 | struct netxen_adapter *adapter; |
651 | }; | |
652 | ||
653 | #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ | |
654 | #define ETHERNET_FCS_SIZE 4 | |
655 | ||
656 | struct netxen_adapter_stats { | |
657 | u64 ints; | |
658 | u64 hostints; | |
659 | u64 otherints; | |
660 | u64 process_rcv; | |
661 | u64 process_xmit; | |
662 | u64 noxmitdone; | |
663 | u64 xmitcsummed; | |
664 | u64 post_called; | |
665 | u64 posted; | |
666 | u64 lastposted; | |
667 | u64 goodskbposts; | |
668 | }; | |
669 | ||
670 | /* | |
671 | * Rcv Descriptor Context. One such per Rcv Descriptor. There may | |
672 | * be one Rcv Descriptor for normal packets, one for jumbo and may be others. | |
673 | */ | |
674 | struct netxen_rcv_desc_ctx { | |
675 | u32 flags; | |
676 | u32 producer; | |
677 | u32 rcv_pending; /* Num of bufs posted in phantom */ | |
678 | u32 rcv_free; /* Num of bufs in free list */ | |
679 | dma_addr_t phys_addr; | |
cb8011ad | 680 | struct pci_dev *phys_pdev; |
3d396eb1 AK |
681 | struct rcv_desc *desc_head; /* address of rx ring in Phantom */ |
682 | u32 max_rx_desc_count; | |
683 | u32 dma_size; | |
684 | u32 skb_size; | |
685 | struct netxen_rx_buffer *rx_buf_arr; /* rx buffers for receive */ | |
686 | int begin_alloc; | |
687 | }; | |
688 | ||
689 | /* | |
690 | * Receive context. There is one such structure per instance of the | |
691 | * receive processing. Any state information that is relevant to | |
692 | * the receive, and is must be in this structure. The global data may be | |
693 | * present elsewhere. | |
694 | */ | |
695 | struct netxen_recv_context { | |
696 | struct netxen_rcv_desc_ctx rcv_desc[NUM_RCV_DESC_RINGS]; | |
697 | u32 status_rx_producer; | |
698 | u32 status_rx_consumer; | |
699 | dma_addr_t rcv_status_desc_phys_addr; | |
cb8011ad | 700 | struct pci_dev *rcv_status_desc_pdev; |
3d396eb1 AK |
701 | struct status_desc *rcv_status_desc_head; |
702 | }; | |
703 | ||
704 | #define NETXEN_NIC_MSI_ENABLED 0x02 | |
705 | ||
706 | struct netxen_drvops; | |
707 | ||
708 | struct netxen_adapter { | |
709 | struct netxen_hardware_context ahw; | |
710 | int port_count; /* Number of configured ports */ | |
711 | int active_ports; /* Number of open ports */ | |
712 | struct netxen_port *port[NETXEN_MAX_PORTS]; /* ptr to each port */ | |
713 | spinlock_t tx_lock; | |
714 | spinlock_t lock; | |
715 | struct work_struct watchdog_task; | |
716 | struct work_struct tx_timeout_task; | |
717 | struct timer_list watchdog_timer; | |
718 | ||
719 | u32 curr_window; | |
720 | ||
721 | u32 cmd_producer; | |
722 | u32 cmd_consumer; | |
723 | ||
724 | u32 last_cmd_consumer; | |
725 | u32 max_tx_desc_count; | |
726 | u32 max_rx_desc_count; | |
727 | u32 max_jumbo_rx_desc_count; | |
728 | /* Num of instances active on cmd buffer ring */ | |
729 | u32 proc_cmd_buf_counter; | |
730 | ||
731 | u32 num_threads, total_threads; /*Use to keep track of xmit threads */ | |
732 | ||
733 | u32 flags; | |
734 | u32 irq; | |
735 | int driver_mismatch; | |
cb8011ad | 736 | u32 temp; |
3d396eb1 AK |
737 | |
738 | struct netxen_adapter_stats stats; | |
739 | ||
740 | struct netxen_cmd_buffer *cmd_buf_arr; /* Command buffers for xmit */ | |
741 | ||
742 | /* | |
743 | * Receive instances. These can be either one per port, | |
744 | * or one per peg, etc. | |
745 | */ | |
746 | struct netxen_recv_context recv_ctx[MAX_RCV_CTX]; | |
747 | ||
748 | int is_up; | |
749 | int work_done; | |
750 | struct netxen_drvops *ops; | |
751 | }; /* netxen_adapter structure */ | |
752 | ||
753 | /* Max number of xmit producer threads that can run simultaneously */ | |
754 | #define MAX_XMIT_PRODUCERS 16 | |
755 | ||
756 | struct netxen_port_stats { | |
757 | u64 rcvdbadskb; | |
758 | u64 xmitcalled; | |
759 | u64 xmitedframes; | |
760 | u64 xmitfinished; | |
761 | u64 badskblen; | |
762 | u64 nocmddescriptor; | |
763 | u64 polled; | |
764 | u64 uphappy; | |
765 | u64 updropped; | |
766 | u64 uplcong; | |
767 | u64 uphcong; | |
768 | u64 upmcong; | |
769 | u64 updunno; | |
770 | u64 skbfreed; | |
771 | u64 txdropped; | |
772 | u64 txnullskb; | |
773 | u64 csummed; | |
774 | u64 no_rcv; | |
775 | u64 rxbytes; | |
776 | u64 txbytes; | |
777 | }; | |
778 | ||
779 | struct netxen_port { | |
780 | struct netxen_adapter *adapter; | |
781 | ||
782 | u16 portnum; /* GBE port number */ | |
783 | u16 link_speed; | |
784 | u16 link_duplex; | |
785 | u16 link_autoneg; | |
786 | ||
787 | int flags; | |
788 | ||
789 | struct net_device *netdev; | |
790 | struct pci_dev *pdev; | |
791 | struct net_device_stats net_stats; | |
792 | struct netxen_port_stats stats; | |
793 | }; | |
794 | ||
cb8011ad AK |
795 | #define PCI_OFFSET_FIRST_RANGE(adapter, off) \ |
796 | ((adapter)->ahw.pci_base0 + (off)) | |
797 | #define PCI_OFFSET_SECOND_RANGE(adapter, off) \ | |
798 | ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START) | |
799 | #define PCI_OFFSET_THIRD_RANGE(adapter, off) \ | |
800 | ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START) | |
801 | ||
802 | static inline void __iomem *pci_base_offset(struct netxen_adapter *adapter, | |
803 | unsigned long off) | |
804 | { | |
805 | if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) { | |
806 | return (adapter->ahw.pci_base0 + off); | |
807 | } else if ((off < SECOND_PAGE_GROUP_END) && | |
808 | (off >= SECOND_PAGE_GROUP_START)) { | |
809 | return (adapter->ahw.pci_base1 + off - SECOND_PAGE_GROUP_START); | |
810 | } else if ((off < THIRD_PAGE_GROUP_END) && | |
811 | (off >= THIRD_PAGE_GROUP_START)) { | |
812 | return (adapter->ahw.pci_base2 + off - THIRD_PAGE_GROUP_START); | |
813 | } | |
814 | return NULL; | |
815 | } | |
816 | ||
817 | static inline void __iomem *pci_base(struct netxen_adapter *adapter, | |
818 | unsigned long off) | |
819 | { | |
820 | if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) { | |
821 | return adapter->ahw.pci_base0; | |
822 | } else if ((off < SECOND_PAGE_GROUP_END) && | |
823 | (off >= SECOND_PAGE_GROUP_START)) { | |
824 | return adapter->ahw.pci_base1; | |
825 | } else if ((off < THIRD_PAGE_GROUP_END) && | |
826 | (off >= THIRD_PAGE_GROUP_START)) { | |
827 | return adapter->ahw.pci_base2; | |
828 | } | |
829 | return NULL; | |
830 | } | |
831 | ||
3d396eb1 AK |
832 | struct netxen_drvops { |
833 | int (*enable_phy_interrupts) (struct netxen_adapter *, int); | |
834 | int (*disable_phy_interrupts) (struct netxen_adapter *, int); | |
835 | void (*handle_phy_intr) (struct netxen_adapter *); | |
836 | int (*macaddr_set) (struct netxen_port *, netxen_ethernet_macaddr_t); | |
837 | int (*set_mtu) (struct netxen_port *, int); | |
838 | int (*set_promisc) (struct netxen_adapter *, int, | |
839 | netxen_niu_prom_mode_t); | |
840 | int (*unset_promisc) (struct netxen_adapter *, int, | |
841 | netxen_niu_prom_mode_t); | |
842 | int (*phy_read) (struct netxen_adapter *, long phy, long reg, u32 *); | |
843 | int (*phy_write) (struct netxen_adapter *, long phy, long reg, u32 val); | |
844 | int (*init_port) (struct netxen_adapter *, int); | |
845 | void (*init_niu) (struct netxen_adapter *); | |
846 | int (*stop_port) (struct netxen_adapter *, int); | |
847 | }; | |
848 | ||
849 | extern char netxen_nic_driver_name[]; | |
850 | ||
851 | int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter, | |
852 | int port); | |
853 | int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter, | |
854 | int port); | |
855 | int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter, | |
856 | int port); | |
857 | int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter, | |
858 | int port); | |
859 | int netxen_niu_xgbe_clear_phy_interrupts(struct netxen_adapter *adapter, | |
860 | int port); | |
861 | int netxen_niu_gbe_clear_phy_interrupts(struct netxen_adapter *adapter, | |
862 | int port); | |
863 | void netxen_nic_xgbe_handle_phy_intr(struct netxen_adapter *adapter); | |
864 | void netxen_nic_gbe_handle_phy_intr(struct netxen_adapter *adapter); | |
865 | void netxen_niu_gbe_set_mii_mode(struct netxen_adapter *adapter, int port, | |
866 | long enable); | |
867 | void netxen_niu_gbe_set_gmii_mode(struct netxen_adapter *adapter, int port, | |
868 | long enable); | |
869 | int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long phy, long reg, | |
870 | __le32 * readval); | |
871 | int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, long phy, | |
872 | long reg, __le32 val); | |
873 | ||
874 | /* Functions available from netxen_nic_hw.c */ | |
3d396eb1 AK |
875 | int netxen_nic_set_mtu_xgb(struct netxen_port *port, int new_mtu); |
876 | int netxen_nic_set_mtu_gb(struct netxen_port *port, int new_mtu); | |
877 | void netxen_nic_init_niu_gb(struct netxen_adapter *adapter); | |
878 | void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw); | |
879 | void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val); | |
880 | int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off); | |
881 | void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value); | |
882 | void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value); | |
883 | ||
884 | int netxen_nic_get_board_info(struct netxen_adapter *adapter); | |
885 | int netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data, | |
886 | int len); | |
887 | int netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data, | |
888 | int len); | |
889 | void netxen_crb_writelit_adapter(struct netxen_adapter *adapter, | |
890 | unsigned long off, int data); | |
891 | ||
892 | /* Functions from netxen_nic_init.c */ | |
cb8011ad | 893 | void netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val); |
3d396eb1 AK |
894 | void netxen_load_firmware(struct netxen_adapter *adapter); |
895 | int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose); | |
896 | int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp); | |
cb8011ad AK |
897 | int netxen_rom_fast_write(struct netxen_adapter *adapter, int addr, int data); |
898 | int netxen_rom_se(struct netxen_adapter *adapter, int addr); | |
899 | int netxen_do_rom_se(struct netxen_adapter *adapter, int addr); | |
3d396eb1 AK |
900 | |
901 | /* Functions from netxen_nic_isr.c */ | |
902 | void netxen_nic_isr_other(struct netxen_adapter *adapter); | |
903 | void netxen_indicate_link_status(struct netxen_adapter *adapter, u32 port, | |
904 | u32 link); | |
905 | void netxen_handle_port_int(struct netxen_adapter *adapter, u32 port, | |
906 | u32 enable); | |
907 | void netxen_nic_stop_all_ports(struct netxen_adapter *adapter); | |
908 | void netxen_initialize_adapter_sw(struct netxen_adapter *adapter); | |
909 | void netxen_initialize_adapter_hw(struct netxen_adapter *adapter); | |
cb8011ad AK |
910 | void *netxen_alloc(struct pci_dev *pdev, size_t sz, dma_addr_t * ptr, |
911 | struct pci_dev **used_dev); | |
3d396eb1 AK |
912 | void netxen_initialize_adapter_ops(struct netxen_adapter *adapter); |
913 | int netxen_init_firmware(struct netxen_adapter *adapter); | |
914 | void netxen_free_hw_resources(struct netxen_adapter *adapter); | |
915 | void netxen_tso_check(struct netxen_adapter *adapter, | |
916 | struct cmd_desc_type0 *desc, struct sk_buff *skb); | |
917 | int netxen_nic_hw_resources(struct netxen_adapter *adapter); | |
918 | void netxen_nic_clear_stats(struct netxen_adapter *adapter); | |
919 | int | |
920 | netxen_nic_do_ioctl(struct netxen_adapter *adapter, void *u_data, | |
921 | struct netxen_port *port); | |
922 | int netxen_nic_rx_has_work(struct netxen_adapter *adapter); | |
923 | int netxen_nic_tx_has_work(struct netxen_adapter *adapter); | |
924 | void netxen_watchdog_task(unsigned long v); | |
925 | void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, | |
926 | u32 ringid); | |
927 | void netxen_process_cmd_ring(unsigned long data); | |
928 | u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctx, int max); | |
929 | void netxen_nic_set_multi(struct net_device *netdev); | |
930 | int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu); | |
931 | int netxen_nic_set_mac(struct net_device *netdev, void *p); | |
932 | struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev); | |
933 | ||
934 | static inline void netxen_nic_disable_int(struct netxen_adapter *adapter) | |
935 | { | |
936 | /* | |
937 | * ISR_INT_MASK: Can be read from window 0 or 1. | |
938 | */ | |
71bd7877 | 939 | writel(0x7ff, PCI_OFFSET_SECOND_RANGE(adapter, ISR_INT_MASK)); |
cb8011ad | 940 | |
3d396eb1 AK |
941 | } |
942 | ||
943 | static inline void netxen_nic_enable_int(struct netxen_adapter *adapter) | |
944 | { | |
945 | u32 mask; | |
946 | ||
947 | switch (adapter->ahw.board_type) { | |
948 | case NETXEN_NIC_GBE: | |
949 | mask = 0x77b; | |
950 | break; | |
951 | case NETXEN_NIC_XGBE: | |
952 | mask = 0x77f; | |
953 | break; | |
954 | default: | |
955 | mask = 0x7ff; | |
956 | break; | |
957 | } | |
958 | ||
71bd7877 | 959 | writel(mask, PCI_OFFSET_SECOND_RANGE(adapter, ISR_INT_MASK)); |
3d396eb1 AK |
960 | |
961 | if (!(adapter->flags & NETXEN_NIC_MSI_ENABLED)) { | |
962 | mask = 0xbff; | |
71bd7877 AK |
963 | writel(mask, PCI_OFFSET_SECOND_RANGE(adapter, |
964 | ISR_INT_TARGET_MASK)); | |
cb8011ad AK |
965 | } |
966 | } | |
967 | ||
968 | /* | |
969 | * NetXen Board information | |
970 | */ | |
971 | ||
972 | #define NETXEN_MAX_SHORT_NAME 16 | |
71bd7877 | 973 | struct netxen_brdinfo { |
cb8011ad AK |
974 | netxen_brdtype_t brdtype; /* type of board */ |
975 | long ports; /* max no of physical ports */ | |
976 | char short_name[NETXEN_MAX_SHORT_NAME]; | |
71bd7877 | 977 | }; |
cb8011ad | 978 | |
71bd7877 | 979 | static const struct netxen_brdinfo netxen_boards[] = { |
cb8011ad AK |
980 | {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"}, |
981 | {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"}, | |
982 | {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"}, | |
983 | {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"}, | |
984 | {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"}, | |
985 | {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"}, | |
986 | }; | |
987 | ||
71bd7877 | 988 | #define NUM_SUPPORTED_BOARDS (sizeof(netxen_boards)/sizeof(struct netxen_brdinfo)) |
cb8011ad AK |
989 | |
990 | static inline void get_brd_port_by_type(u32 type, int *ports) | |
991 | { | |
992 | int i, found = 0; | |
993 | for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) { | |
994 | if (netxen_boards[i].brdtype == type) { | |
995 | *ports = netxen_boards[i].ports; | |
996 | found = 1; | |
997 | break; | |
998 | } | |
999 | } | |
1000 | if (!found) | |
1001 | *ports = 0; | |
1002 | } | |
1003 | ||
1004 | static inline void get_brd_name_by_type(u32 type, char *name) | |
1005 | { | |
1006 | int i, found = 0; | |
1007 | for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) { | |
1008 | if (netxen_boards[i].brdtype == type) { | |
1009 | strcpy(name, netxen_boards[i].short_name); | |
1010 | found = 1; | |
1011 | break; | |
1012 | } | |
1013 | ||
3d396eb1 | 1014 | } |
cb8011ad AK |
1015 | if (!found) |
1016 | name = "Unknown"; | |
3d396eb1 AK |
1017 | } |
1018 | ||
1019 | int netxen_is_flash_supported(struct netxen_adapter *adapter); | |
1020 | int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 mac[]); | |
1021 | ||
1022 | extern void netxen_change_ringparam(struct netxen_adapter *adapter); | |
1023 | extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, | |
1024 | int *valp); | |
1025 | ||
1026 | extern struct ethtool_ops netxen_nic_ethtool_ops; | |
1027 | ||
1028 | #endif /* __NETXEN_NIC_H_ */ |