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d9e651bc DP |
1 | /* |
2 | * Copyright (C) 2003 - 2008 NetXen, Inc. | |
3 | * All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, | |
18 | * MA 02111-1307, USA. | |
19 | * | |
20 | * The full GNU General Public License is included in this distribution | |
21 | * in the file called LICENSE. | |
22 | * | |
23 | * Contact Information: | |
24 | * info@netxen.com | |
25 | * NetXen, | |
26 | * 3965 Freedom Circle, Fourth floor, | |
27 | * Santa Clara, CA 95054 | |
28 | * | |
29 | */ | |
30 | ||
31 | #include "netxen_nic_hw.h" | |
32 | #include "netxen_nic.h" | |
33 | #include "netxen_nic_phan_reg.h" | |
34 | ||
35 | #define NXHAL_VERSION 1 | |
36 | ||
37 | static int | |
38 | netxen_api_lock(struct netxen_adapter *adapter) | |
39 | { | |
40 | u32 done = 0, timeout = 0; | |
41 | ||
42 | for (;;) { | |
43 | /* Acquire PCIE HW semaphore5 */ | |
44 | netxen_nic_read_w0(adapter, | |
45 | NETXEN_PCIE_REG(PCIE_SEM5_LOCK), &done); | |
46 | ||
47 | if (done == 1) | |
48 | break; | |
49 | ||
50 | if (++timeout >= NX_OS_CRB_RETRY_COUNT) { | |
51 | printk(KERN_ERR "%s: lock timeout.\n", __func__); | |
52 | return -1; | |
53 | } | |
54 | ||
55 | msleep(1); | |
56 | } | |
57 | ||
58 | #if 0 | |
59 | netxen_nic_write_w1(adapter, | |
60 | NETXEN_API_LOCK_ID, NX_OS_API_LOCK_DRIVER); | |
61 | #endif | |
62 | return 0; | |
63 | } | |
64 | ||
65 | static int | |
66 | netxen_api_unlock(struct netxen_adapter *adapter) | |
67 | { | |
68 | u32 val; | |
69 | ||
70 | /* Release PCIE HW semaphore5 */ | |
71 | netxen_nic_read_w0(adapter, | |
72 | NETXEN_PCIE_REG(PCIE_SEM5_UNLOCK), &val); | |
73 | return 0; | |
74 | } | |
75 | ||
76 | static u32 | |
77 | netxen_poll_rsp(struct netxen_adapter *adapter) | |
78 | { | |
2edbb454 | 79 | u32 rsp = NX_CDRP_RSP_OK; |
d9e651bc DP |
80 | int timeout = 0; |
81 | ||
82 | do { | |
83 | /* give atleast 1ms for firmware to respond */ | |
84 | msleep(1); | |
85 | ||
86 | if (++timeout > NX_OS_CRB_RETRY_COUNT) | |
87 | return NX_CDRP_RSP_TIMEOUT; | |
88 | ||
2edbb454 | 89 | netxen_nic_read_w1(adapter, NX_CDRP_CRB_OFFSET, &rsp); |
d9e651bc DP |
90 | } while (!NX_CDRP_IS_RSP(rsp)); |
91 | ||
92 | return rsp; | |
93 | } | |
94 | ||
95 | static u32 | |
96 | netxen_issue_cmd(struct netxen_adapter *adapter, | |
97 | u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd) | |
98 | { | |
99 | u32 rsp; | |
100 | u32 signature = 0; | |
101 | u32 rcode = NX_RCODE_SUCCESS; | |
102 | ||
103 | signature = NX_CDRP_SIGNATURE_MAKE(pci_fn, version); | |
104 | ||
105 | /* Acquire semaphore before accessing CRB */ | |
106 | if (netxen_api_lock(adapter)) | |
107 | return NX_RCODE_TIMEOUT; | |
108 | ||
2edbb454 | 109 | netxen_nic_write_w1(adapter, NX_SIGN_CRB_OFFSET, signature); |
d9e651bc | 110 | |
2edbb454 | 111 | netxen_nic_write_w1(adapter, NX_ARG1_CRB_OFFSET, arg1); |
d9e651bc | 112 | |
2edbb454 | 113 | netxen_nic_write_w1(adapter, NX_ARG2_CRB_OFFSET, arg2); |
d9e651bc | 114 | |
2edbb454 | 115 | netxen_nic_write_w1(adapter, NX_ARG3_CRB_OFFSET, arg3); |
d9e651bc DP |
116 | |
117 | netxen_nic_write_w1(adapter, NX_CDRP_CRB_OFFSET, | |
2edbb454 | 118 | NX_CDRP_FORM_CMD(cmd)); |
d9e651bc DP |
119 | |
120 | rsp = netxen_poll_rsp(adapter); | |
121 | ||
122 | if (rsp == NX_CDRP_RSP_TIMEOUT) { | |
123 | printk(KERN_ERR "%s: card response timeout.\n", | |
124 | netxen_nic_driver_name); | |
125 | ||
126 | rcode = NX_RCODE_TIMEOUT; | |
127 | } else if (rsp == NX_CDRP_RSP_FAIL) { | |
128 | netxen_nic_read_w1(adapter, NX_ARG1_CRB_OFFSET, &rcode); | |
d9e651bc DP |
129 | |
130 | printk(KERN_ERR "%s: failed card response code:0x%x\n", | |
131 | netxen_nic_driver_name, rcode); | |
132 | } | |
133 | ||
134 | /* Release semaphore */ | |
135 | netxen_api_unlock(adapter); | |
136 | ||
137 | return rcode; | |
138 | } | |
139 | ||
9ad27643 DP |
140 | int |
141 | nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu) | |
d9e651bc DP |
142 | { |
143 | u32 rcode = NX_RCODE_SUCCESS; | |
144 | struct netxen_recv_context *recv_ctx = &adapter->recv_ctx[0]; | |
145 | ||
146 | if (recv_ctx->state == NX_HOST_CTX_STATE_ACTIVE) | |
147 | rcode = netxen_issue_cmd(adapter, | |
148 | adapter->ahw.pci_func, | |
149 | NXHAL_VERSION, | |
150 | recv_ctx->context_id, | |
151 | mtu, | |
152 | 0, | |
153 | NX_CDRP_CMD_SET_MTU); | |
154 | ||
9ad27643 DP |
155 | if (rcode != NX_RCODE_SUCCESS) |
156 | return -EIO; | |
157 | ||
158 | return 0; | |
d9e651bc DP |
159 | } |
160 | ||
161 | static int | |
162 | nx_fw_cmd_create_rx_ctx(struct netxen_adapter *adapter) | |
163 | { | |
164 | void *addr; | |
165 | nx_hostrq_rx_ctx_t *prq; | |
166 | nx_cardrsp_rx_ctx_t *prsp; | |
167 | nx_hostrq_rds_ring_t *prq_rds; | |
168 | nx_hostrq_sds_ring_t *prq_sds; | |
169 | nx_cardrsp_rds_ring_t *prsp_rds; | |
170 | nx_cardrsp_sds_ring_t *prsp_sds; | |
171 | struct nx_host_rds_ring *rds_ring; | |
172 | ||
173 | dma_addr_t hostrq_phys_addr, cardrsp_phys_addr; | |
174 | u64 phys_addr; | |
175 | ||
176 | int i, nrds_rings, nsds_rings; | |
177 | size_t rq_size, rsp_size; | |
2edbb454 | 178 | u32 cap, reg, val; |
d9e651bc DP |
179 | |
180 | int err; | |
181 | ||
182 | struct netxen_recv_context *recv_ctx = &adapter->recv_ctx[0]; | |
183 | ||
184 | /* only one sds ring for now */ | |
185 | nrds_rings = adapter->max_rds_rings; | |
186 | nsds_rings = 1; | |
187 | ||
188 | rq_size = | |
189 | SIZEOF_HOSTRQ_RX(nx_hostrq_rx_ctx_t, nrds_rings, nsds_rings); | |
190 | rsp_size = | |
191 | SIZEOF_CARDRSP_RX(nx_cardrsp_rx_ctx_t, nrds_rings, nsds_rings); | |
192 | ||
193 | addr = pci_alloc_consistent(adapter->pdev, | |
194 | rq_size, &hostrq_phys_addr); | |
195 | if (addr == NULL) | |
196 | return -ENOMEM; | |
197 | prq = (nx_hostrq_rx_ctx_t *)addr; | |
198 | ||
199 | addr = pci_alloc_consistent(adapter->pdev, | |
200 | rsp_size, &cardrsp_phys_addr); | |
201 | if (addr == NULL) { | |
202 | err = -ENOMEM; | |
203 | goto out_free_rq; | |
204 | } | |
205 | prsp = (nx_cardrsp_rx_ctx_t *)addr; | |
206 | ||
207 | prq->host_rsp_dma_addr = cpu_to_le64(cardrsp_phys_addr); | |
208 | ||
209 | cap = (NX_CAP0_LEGACY_CONTEXT | NX_CAP0_LEGACY_MN); | |
210 | cap |= (NX_CAP0_JUMBO_CONTIGUOUS | NX_CAP0_LRO_CONTIGUOUS); | |
211 | ||
212 | prq->capabilities[0] = cpu_to_le32(cap); | |
213 | prq->host_int_crb_mode = | |
214 | cpu_to_le32(NX_HOST_INT_CRB_MODE_SHARED); | |
215 | prq->host_rds_crb_mode = | |
216 | cpu_to_le32(NX_HOST_RDS_CRB_MODE_UNIQUE); | |
217 | ||
218 | prq->num_rds_rings = cpu_to_le16(nrds_rings); | |
219 | prq->num_sds_rings = cpu_to_le16(nsds_rings); | |
2edbb454 DP |
220 | prq->rds_ring_offset = cpu_to_le32(0); |
221 | ||
222 | val = le32_to_cpu(prq->rds_ring_offset) + | |
d9e651bc | 223 | (sizeof(nx_hostrq_rds_ring_t) * nrds_rings); |
2edbb454 | 224 | prq->sds_ring_offset = cpu_to_le32(val); |
d9e651bc | 225 | |
2edbb454 DP |
226 | prq_rds = (nx_hostrq_rds_ring_t *)(prq->data + |
227 | le32_to_cpu(prq->rds_ring_offset)); | |
d9e651bc DP |
228 | |
229 | for (i = 0; i < nrds_rings; i++) { | |
230 | ||
231 | rds_ring = &recv_ctx->rds_rings[i]; | |
232 | ||
233 | prq_rds[i].host_phys_addr = cpu_to_le64(rds_ring->phys_addr); | |
234 | prq_rds[i].ring_size = cpu_to_le32(rds_ring->max_rx_desc_count); | |
235 | prq_rds[i].ring_kind = cpu_to_le32(i); | |
236 | prq_rds[i].buff_size = cpu_to_le64(rds_ring->dma_size); | |
237 | } | |
238 | ||
2edbb454 DP |
239 | prq_sds = (nx_hostrq_sds_ring_t *)(prq->data + |
240 | le32_to_cpu(prq->sds_ring_offset)); | |
d9e651bc DP |
241 | |
242 | prq_sds[0].host_phys_addr = | |
243 | cpu_to_le64(recv_ctx->rcv_status_desc_phys_addr); | |
244 | prq_sds[0].ring_size = cpu_to_le32(adapter->max_rx_desc_count); | |
245 | /* only one msix vector for now */ | |
2edbb454 | 246 | prq_sds[0].msi_index = cpu_to_le16(0); |
d9e651bc DP |
247 | |
248 | phys_addr = hostrq_phys_addr; | |
249 | err = netxen_issue_cmd(adapter, | |
250 | adapter->ahw.pci_func, | |
251 | NXHAL_VERSION, | |
252 | (u32)(phys_addr >> 32), | |
253 | (u32)(phys_addr & 0xffffffff), | |
254 | rq_size, | |
255 | NX_CDRP_CMD_CREATE_RX_CTX); | |
256 | if (err) { | |
257 | printk(KERN_WARNING | |
258 | "Failed to create rx ctx in firmware%d\n", err); | |
259 | goto out_free_rsp; | |
260 | } | |
261 | ||
262 | ||
263 | prsp_rds = ((nx_cardrsp_rds_ring_t *) | |
2edbb454 | 264 | &prsp->data[le32_to_cpu(prsp->rds_ring_offset)]); |
d9e651bc | 265 | |
2edbb454 | 266 | for (i = 0; i < le16_to_cpu(prsp->num_rds_rings); i++) { |
d9e651bc DP |
267 | rds_ring = &recv_ctx->rds_rings[i]; |
268 | ||
269 | reg = le32_to_cpu(prsp_rds[i].host_producer_crb); | |
270 | rds_ring->crb_rcv_producer = NETXEN_NIC_REG(reg - 0x200); | |
271 | } | |
272 | ||
273 | prsp_sds = ((nx_cardrsp_sds_ring_t *) | |
2edbb454 | 274 | &prsp->data[le32_to_cpu(prsp->sds_ring_offset)]); |
d9e651bc DP |
275 | reg = le32_to_cpu(prsp_sds[0].host_consumer_crb); |
276 | recv_ctx->crb_sts_consumer = NETXEN_NIC_REG(reg - 0x200); | |
277 | ||
278 | reg = le32_to_cpu(prsp_sds[0].interrupt_crb); | |
279 | adapter->crb_intr_mask = NETXEN_NIC_REG(reg - 0x200); | |
280 | ||
281 | recv_ctx->state = le32_to_cpu(prsp->host_ctx_state); | |
282 | recv_ctx->context_id = le16_to_cpu(prsp->context_id); | |
2edbb454 | 283 | recv_ctx->virt_port = prsp->virt_port; |
d9e651bc DP |
284 | |
285 | out_free_rsp: | |
286 | pci_free_consistent(adapter->pdev, rsp_size, prsp, cardrsp_phys_addr); | |
287 | out_free_rq: | |
288 | pci_free_consistent(adapter->pdev, rq_size, prq, hostrq_phys_addr); | |
289 | return err; | |
290 | } | |
291 | ||
292 | static void | |
293 | nx_fw_cmd_destroy_rx_ctx(struct netxen_adapter *adapter) | |
294 | { | |
295 | struct netxen_recv_context *recv_ctx = &adapter->recv_ctx[0]; | |
296 | ||
297 | if (netxen_issue_cmd(adapter, | |
298 | adapter->ahw.pci_func, | |
299 | NXHAL_VERSION, | |
300 | recv_ctx->context_id, | |
301 | NX_DESTROY_CTX_RESET, | |
302 | 0, | |
303 | NX_CDRP_CMD_DESTROY_RX_CTX)) { | |
304 | ||
305 | printk(KERN_WARNING | |
306 | "%s: Failed to destroy rx ctx in firmware\n", | |
307 | netxen_nic_driver_name); | |
308 | } | |
309 | } | |
310 | ||
311 | static int | |
312 | nx_fw_cmd_create_tx_ctx(struct netxen_adapter *adapter) | |
313 | { | |
314 | nx_hostrq_tx_ctx_t *prq; | |
315 | nx_hostrq_cds_ring_t *prq_cds; | |
316 | nx_cardrsp_tx_ctx_t *prsp; | |
317 | void *rq_addr, *rsp_addr; | |
318 | size_t rq_size, rsp_size; | |
319 | u32 temp; | |
320 | int err = 0; | |
321 | u64 offset, phys_addr; | |
322 | dma_addr_t rq_phys_addr, rsp_phys_addr; | |
323 | ||
324 | rq_size = SIZEOF_HOSTRQ_TX(nx_hostrq_tx_ctx_t); | |
325 | rq_addr = pci_alloc_consistent(adapter->pdev, | |
326 | rq_size, &rq_phys_addr); | |
327 | if (!rq_addr) | |
328 | return -ENOMEM; | |
329 | ||
330 | rsp_size = SIZEOF_CARDRSP_TX(nx_cardrsp_tx_ctx_t); | |
331 | rsp_addr = pci_alloc_consistent(adapter->pdev, | |
332 | rsp_size, &rsp_phys_addr); | |
333 | if (!rsp_addr) { | |
334 | err = -ENOMEM; | |
335 | goto out_free_rq; | |
336 | } | |
337 | ||
338 | memset(rq_addr, 0, rq_size); | |
339 | prq = (nx_hostrq_tx_ctx_t *)rq_addr; | |
340 | ||
341 | memset(rsp_addr, 0, rsp_size); | |
342 | prsp = (nx_cardrsp_tx_ctx_t *)rsp_addr; | |
343 | ||
344 | prq->host_rsp_dma_addr = cpu_to_le64(rsp_phys_addr); | |
345 | ||
346 | temp = (NX_CAP0_LEGACY_CONTEXT | NX_CAP0_LEGACY_MN | NX_CAP0_LSO); | |
347 | prq->capabilities[0] = cpu_to_le32(temp); | |
348 | ||
349 | prq->host_int_crb_mode = | |
350 | cpu_to_le32(NX_HOST_INT_CRB_MODE_SHARED); | |
351 | ||
352 | prq->interrupt_ctl = 0; | |
353 | prq->msi_index = 0; | |
354 | ||
355 | prq->dummy_dma_addr = cpu_to_le64(adapter->dummy_dma.phys_addr); | |
356 | ||
357 | offset = adapter->ctx_desc_phys_addr+sizeof(struct netxen_ring_ctx); | |
358 | prq->cmd_cons_dma_addr = cpu_to_le64(offset); | |
359 | ||
360 | prq_cds = &prq->cds_ring; | |
361 | ||
362 | prq_cds->host_phys_addr = | |
363 | cpu_to_le64(adapter->ahw.cmd_desc_phys_addr); | |
364 | ||
365 | prq_cds->ring_size = cpu_to_le32(adapter->max_tx_desc_count); | |
366 | ||
367 | phys_addr = rq_phys_addr; | |
368 | err = netxen_issue_cmd(adapter, | |
369 | adapter->ahw.pci_func, | |
370 | NXHAL_VERSION, | |
371 | (u32)(phys_addr >> 32), | |
372 | ((u32)phys_addr & 0xffffffff), | |
373 | rq_size, | |
374 | NX_CDRP_CMD_CREATE_TX_CTX); | |
375 | ||
376 | if (err == NX_RCODE_SUCCESS) { | |
377 | temp = le32_to_cpu(prsp->cds_ring.host_producer_crb); | |
378 | adapter->crb_addr_cmd_producer = | |
379 | NETXEN_NIC_REG(temp - 0x200); | |
380 | #if 0 | |
381 | adapter->tx_state = | |
382 | le32_to_cpu(prsp->host_ctx_state); | |
383 | #endif | |
384 | adapter->tx_context_id = | |
385 | le16_to_cpu(prsp->context_id); | |
386 | } else { | |
387 | printk(KERN_WARNING | |
388 | "Failed to create tx ctx in firmware%d\n", err); | |
389 | err = -EIO; | |
390 | } | |
391 | ||
392 | pci_free_consistent(adapter->pdev, rsp_size, rsp_addr, rsp_phys_addr); | |
393 | ||
394 | out_free_rq: | |
395 | pci_free_consistent(adapter->pdev, rq_size, rq_addr, rq_phys_addr); | |
396 | ||
397 | return err; | |
398 | } | |
399 | ||
400 | static void | |
401 | nx_fw_cmd_destroy_tx_ctx(struct netxen_adapter *adapter) | |
402 | { | |
403 | if (netxen_issue_cmd(adapter, | |
404 | adapter->ahw.pci_func, | |
405 | NXHAL_VERSION, | |
406 | adapter->tx_context_id, | |
407 | NX_DESTROY_CTX_RESET, | |
408 | 0, | |
409 | NX_CDRP_CMD_DESTROY_TX_CTX)) { | |
410 | ||
411 | printk(KERN_WARNING | |
412 | "%s: Failed to destroy tx ctx in firmware\n", | |
413 | netxen_nic_driver_name); | |
414 | } | |
415 | } | |
416 | ||
417 | static u64 ctx_addr_sig_regs[][3] = { | |
418 | {NETXEN_NIC_REG(0x188), NETXEN_NIC_REG(0x18c), NETXEN_NIC_REG(0x1c0)}, | |
419 | {NETXEN_NIC_REG(0x190), NETXEN_NIC_REG(0x194), NETXEN_NIC_REG(0x1c4)}, | |
420 | {NETXEN_NIC_REG(0x198), NETXEN_NIC_REG(0x19c), NETXEN_NIC_REG(0x1c8)}, | |
421 | {NETXEN_NIC_REG(0x1a0), NETXEN_NIC_REG(0x1a4), NETXEN_NIC_REG(0x1cc)} | |
422 | }; | |
423 | ||
424 | #define CRB_CTX_ADDR_REG_LO(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][0]) | |
425 | #define CRB_CTX_ADDR_REG_HI(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][2]) | |
426 | #define CRB_CTX_SIGNATURE_REG(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][1]) | |
427 | ||
428 | #define lower32(x) ((u32)((x) & 0xffffffff)) | |
429 | #define upper32(x) ((u32)(((u64)(x) >> 32) & 0xffffffff)) | |
430 | ||
431 | static struct netxen_recv_crb recv_crb_registers[] = { | |
432 | /* Instance 0 */ | |
433 | { | |
434 | /* crb_rcv_producer: */ | |
435 | { | |
436 | NETXEN_NIC_REG(0x100), | |
437 | /* Jumbo frames */ | |
438 | NETXEN_NIC_REG(0x110), | |
439 | /* LRO */ | |
440 | NETXEN_NIC_REG(0x120) | |
441 | }, | |
442 | /* crb_sts_consumer: */ | |
443 | NETXEN_NIC_REG(0x138), | |
444 | }, | |
445 | /* Instance 1 */ | |
446 | { | |
447 | /* crb_rcv_producer: */ | |
448 | { | |
449 | NETXEN_NIC_REG(0x144), | |
450 | /* Jumbo frames */ | |
451 | NETXEN_NIC_REG(0x154), | |
452 | /* LRO */ | |
453 | NETXEN_NIC_REG(0x164) | |
454 | }, | |
455 | /* crb_sts_consumer: */ | |
456 | NETXEN_NIC_REG(0x17c), | |
457 | }, | |
458 | /* Instance 2 */ | |
459 | { | |
460 | /* crb_rcv_producer: */ | |
461 | { | |
462 | NETXEN_NIC_REG(0x1d8), | |
463 | /* Jumbo frames */ | |
464 | NETXEN_NIC_REG(0x1f8), | |
465 | /* LRO */ | |
466 | NETXEN_NIC_REG(0x208) | |
467 | }, | |
468 | /* crb_sts_consumer: */ | |
469 | NETXEN_NIC_REG(0x220), | |
470 | }, | |
471 | /* Instance 3 */ | |
472 | { | |
473 | /* crb_rcv_producer: */ | |
474 | { | |
475 | NETXEN_NIC_REG(0x22c), | |
476 | /* Jumbo frames */ | |
477 | NETXEN_NIC_REG(0x23c), | |
478 | /* LRO */ | |
479 | NETXEN_NIC_REG(0x24c) | |
480 | }, | |
481 | /* crb_sts_consumer: */ | |
482 | NETXEN_NIC_REG(0x264), | |
483 | }, | |
484 | }; | |
485 | ||
486 | static int | |
487 | netxen_init_old_ctx(struct netxen_adapter *adapter) | |
488 | { | |
489 | struct netxen_recv_context *recv_ctx; | |
490 | struct nx_host_rds_ring *rds_ring; | |
491 | int ctx, ring; | |
492 | int func_id = adapter->portnum; | |
493 | ||
494 | adapter->ctx_desc->cmd_ring_addr = | |
495 | cpu_to_le64(adapter->ahw.cmd_desc_phys_addr); | |
496 | adapter->ctx_desc->cmd_ring_size = | |
497 | cpu_to_le32(adapter->max_tx_desc_count); | |
498 | ||
499 | for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) { | |
500 | recv_ctx = &adapter->recv_ctx[ctx]; | |
501 | ||
502 | for (ring = 0; ring < adapter->max_rds_rings; ring++) { | |
503 | rds_ring = &recv_ctx->rds_rings[ring]; | |
504 | ||
505 | adapter->ctx_desc->rcv_ctx[ring].rcv_ring_addr = | |
506 | cpu_to_le64(rds_ring->phys_addr); | |
507 | adapter->ctx_desc->rcv_ctx[ring].rcv_ring_size = | |
508 | cpu_to_le32(rds_ring->max_rx_desc_count); | |
509 | } | |
510 | adapter->ctx_desc->sts_ring_addr = | |
511 | cpu_to_le64(recv_ctx->rcv_status_desc_phys_addr); | |
512 | adapter->ctx_desc->sts_ring_size = | |
513 | cpu_to_le32(adapter->max_rx_desc_count); | |
514 | } | |
515 | ||
516 | adapter->pci_write_normalize(adapter, CRB_CTX_ADDR_REG_LO(func_id), | |
517 | lower32(adapter->ctx_desc_phys_addr)); | |
518 | adapter->pci_write_normalize(adapter, CRB_CTX_ADDR_REG_HI(func_id), | |
519 | upper32(adapter->ctx_desc_phys_addr)); | |
520 | adapter->pci_write_normalize(adapter, CRB_CTX_SIGNATURE_REG(func_id), | |
521 | NETXEN_CTX_SIGNATURE | func_id); | |
522 | return 0; | |
523 | } | |
524 | ||
525 | static uint32_t sw_int_mask[4] = { | |
526 | CRB_SW_INT_MASK_0, CRB_SW_INT_MASK_1, | |
527 | CRB_SW_INT_MASK_2, CRB_SW_INT_MASK_3 | |
528 | }; | |
529 | ||
530 | int netxen_alloc_hw_resources(struct netxen_adapter *adapter) | |
531 | { | |
532 | struct netxen_hardware_context *hw = &adapter->ahw; | |
533 | u32 state = 0; | |
534 | void *addr; | |
535 | int err = 0; | |
536 | int ctx, ring; | |
537 | struct netxen_recv_context *recv_ctx; | |
538 | struct nx_host_rds_ring *rds_ring; | |
539 | ||
540 | err = netxen_receive_peg_ready(adapter); | |
541 | if (err) { | |
542 | printk(KERN_ERR "Rcv Peg initialization not complete:%x.\n", | |
543 | state); | |
544 | return err; | |
545 | } | |
546 | ||
547 | addr = pci_alloc_consistent(adapter->pdev, | |
548 | sizeof(struct netxen_ring_ctx) + sizeof(uint32_t), | |
549 | &adapter->ctx_desc_phys_addr); | |
550 | ||
551 | if (addr == NULL) { | |
552 | DPRINTK(ERR, "failed to allocate hw context\n"); | |
553 | return -ENOMEM; | |
554 | } | |
555 | memset(addr, 0, sizeof(struct netxen_ring_ctx)); | |
556 | adapter->ctx_desc = (struct netxen_ring_ctx *)addr; | |
557 | adapter->ctx_desc->ctx_id = cpu_to_le32(adapter->portnum); | |
558 | adapter->ctx_desc->cmd_consumer_offset = | |
559 | cpu_to_le64(adapter->ctx_desc_phys_addr + | |
560 | sizeof(struct netxen_ring_ctx)); | |
561 | adapter->cmd_consumer = | |
562 | (__le32 *)(((char *)addr) + sizeof(struct netxen_ring_ctx)); | |
563 | ||
564 | /* cmd desc ring */ | |
565 | addr = pci_alloc_consistent(adapter->pdev, | |
566 | sizeof(struct cmd_desc_type0) * | |
567 | adapter->max_tx_desc_count, | |
568 | &hw->cmd_desc_phys_addr); | |
569 | ||
570 | if (addr == NULL) { | |
571 | printk(KERN_ERR "%s failed to allocate tx desc ring\n", | |
572 | netxen_nic_driver_name); | |
573 | return -ENOMEM; | |
574 | } | |
575 | ||
576 | hw->cmd_desc_head = (struct cmd_desc_type0 *)addr; | |
577 | ||
578 | for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) { | |
579 | recv_ctx = &adapter->recv_ctx[ctx]; | |
580 | ||
581 | for (ring = 0; ring < adapter->max_rds_rings; ring++) { | |
582 | /* rx desc ring */ | |
583 | rds_ring = &recv_ctx->rds_rings[ring]; | |
584 | addr = pci_alloc_consistent(adapter->pdev, | |
585 | RCV_DESC_RINGSIZE, | |
586 | &rds_ring->phys_addr); | |
587 | if (addr == NULL) { | |
588 | printk(KERN_ERR "%s failed to allocate rx " | |
589 | "desc ring[%d]\n", | |
590 | netxen_nic_driver_name, ring); | |
591 | err = -ENOMEM; | |
592 | goto err_out_free; | |
593 | } | |
594 | rds_ring->desc_head = (struct rcv_desc *)addr; | |
595 | ||
596 | if (adapter->fw_major < 4) | |
597 | rds_ring->crb_rcv_producer = | |
598 | recv_crb_registers[adapter->portnum]. | |
599 | crb_rcv_producer[ring]; | |
600 | } | |
601 | ||
602 | /* status desc ring */ | |
603 | addr = pci_alloc_consistent(adapter->pdev, | |
604 | STATUS_DESC_RINGSIZE, | |
605 | &recv_ctx->rcv_status_desc_phys_addr); | |
606 | if (addr == NULL) { | |
607 | printk(KERN_ERR "%s failed to allocate sts desc ring\n", | |
608 | netxen_nic_driver_name); | |
609 | err = -ENOMEM; | |
610 | goto err_out_free; | |
611 | } | |
612 | recv_ctx->rcv_status_desc_head = (struct status_desc *)addr; | |
613 | ||
614 | if (adapter->fw_major < 4) | |
615 | recv_ctx->crb_sts_consumer = | |
616 | recv_crb_registers[adapter->portnum]. | |
617 | crb_sts_consumer; | |
618 | } | |
619 | ||
620 | if (adapter->fw_major >= 4) { | |
621 | adapter->intr_scheme = INTR_SCHEME_PERPORT; | |
622 | adapter->msi_mode = MSI_MODE_MULTIFUNC; | |
623 | ||
624 | err = nx_fw_cmd_create_rx_ctx(adapter); | |
625 | if (err) | |
626 | goto err_out_free; | |
627 | err = nx_fw_cmd_create_tx_ctx(adapter); | |
628 | if (err) | |
629 | goto err_out_free; | |
630 | } else { | |
631 | ||
632 | adapter->intr_scheme = adapter->pci_read_normalize(adapter, | |
633 | CRB_NIC_CAPABILITIES_FW); | |
634 | adapter->msi_mode = adapter->pci_read_normalize(adapter, | |
635 | CRB_NIC_MSI_MODE_FW); | |
636 | adapter->crb_intr_mask = sw_int_mask[adapter->portnum]; | |
637 | ||
638 | err = netxen_init_old_ctx(adapter); | |
639 | if (err) { | |
640 | netxen_free_hw_resources(adapter); | |
641 | return err; | |
642 | } | |
643 | ||
644 | } | |
645 | ||
646 | return 0; | |
647 | ||
648 | err_out_free: | |
649 | netxen_free_hw_resources(adapter); | |
650 | return err; | |
651 | } | |
652 | ||
653 | void netxen_free_hw_resources(struct netxen_adapter *adapter) | |
654 | { | |
655 | struct netxen_recv_context *recv_ctx; | |
656 | struct nx_host_rds_ring *rds_ring; | |
657 | int ctx, ring; | |
658 | ||
659 | if (adapter->fw_major >= 4) { | |
660 | nx_fw_cmd_destroy_tx_ctx(adapter); | |
661 | nx_fw_cmd_destroy_rx_ctx(adapter); | |
662 | } | |
663 | ||
664 | if (adapter->ctx_desc != NULL) { | |
665 | pci_free_consistent(adapter->pdev, | |
666 | sizeof(struct netxen_ring_ctx) + | |
667 | sizeof(uint32_t), | |
668 | adapter->ctx_desc, | |
669 | adapter->ctx_desc_phys_addr); | |
670 | adapter->ctx_desc = NULL; | |
671 | } | |
672 | ||
673 | if (adapter->ahw.cmd_desc_head != NULL) { | |
674 | pci_free_consistent(adapter->pdev, | |
675 | sizeof(struct cmd_desc_type0) * | |
676 | adapter->max_tx_desc_count, | |
677 | adapter->ahw.cmd_desc_head, | |
678 | adapter->ahw.cmd_desc_phys_addr); | |
679 | adapter->ahw.cmd_desc_head = NULL; | |
680 | } | |
681 | ||
682 | for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) { | |
683 | recv_ctx = &adapter->recv_ctx[ctx]; | |
684 | for (ring = 0; ring < adapter->max_rds_rings; ring++) { | |
685 | rds_ring = &recv_ctx->rds_rings[ring]; | |
686 | ||
687 | if (rds_ring->desc_head != NULL) { | |
688 | pci_free_consistent(adapter->pdev, | |
689 | RCV_DESC_RINGSIZE, | |
690 | rds_ring->desc_head, | |
691 | rds_ring->phys_addr); | |
692 | rds_ring->desc_head = NULL; | |
693 | } | |
694 | } | |
695 | ||
696 | if (recv_ctx->rcv_status_desc_head != NULL) { | |
697 | pci_free_consistent(adapter->pdev, | |
698 | STATUS_DESC_RINGSIZE, | |
699 | recv_ctx->rcv_status_desc_head, | |
700 | recv_ctx->rcv_status_desc_phys_addr); | |
701 | recv_ctx->rcv_status_desc_head = NULL; | |
702 | } | |
703 | } | |
704 | } | |
705 |