Commit | Line | Data |
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d9e651bc | 1 | /* |
5d242f1c | 2 | * Copyright (C) 2003 - 2009 NetXen, Inc. |
d9e651bc DP |
3 | * All rights reserved. |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, | |
18 | * MA 02111-1307, USA. | |
19 | * | |
20 | * The full GNU General Public License is included in this distribution | |
21 | * in the file called LICENSE. | |
22 | * | |
23 | * Contact Information: | |
24 | * info@netxen.com | |
5d242f1c DP |
25 | * NetXen Inc, |
26 | * 18922 Forge Drive | |
27 | * Cupertino, CA 95014-0701 | |
d9e651bc DP |
28 | * |
29 | */ | |
30 | ||
31 | #include "netxen_nic_hw.h" | |
32 | #include "netxen_nic.h" | |
33 | #include "netxen_nic_phan_reg.h" | |
34 | ||
35 | #define NXHAL_VERSION 1 | |
36 | ||
37 | static int | |
38 | netxen_api_lock(struct netxen_adapter *adapter) | |
39 | { | |
40 | u32 done = 0, timeout = 0; | |
41 | ||
42 | for (;;) { | |
43 | /* Acquire PCIE HW semaphore5 */ | |
f98a9f69 | 44 | done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM5_LOCK)); |
d9e651bc DP |
45 | |
46 | if (done == 1) | |
47 | break; | |
48 | ||
49 | if (++timeout >= NX_OS_CRB_RETRY_COUNT) { | |
50 | printk(KERN_ERR "%s: lock timeout.\n", __func__); | |
51 | return -1; | |
52 | } | |
53 | ||
54 | msleep(1); | |
55 | } | |
56 | ||
57 | #if 0 | |
f98a9f69 | 58 | NXWR32(adapter, |
d9e651bc DP |
59 | NETXEN_API_LOCK_ID, NX_OS_API_LOCK_DRIVER); |
60 | #endif | |
61 | return 0; | |
62 | } | |
63 | ||
64 | static int | |
65 | netxen_api_unlock(struct netxen_adapter *adapter) | |
66 | { | |
d9e651bc | 67 | /* Release PCIE HW semaphore5 */ |
f98a9f69 | 68 | NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM5_UNLOCK)); |
d9e651bc DP |
69 | return 0; |
70 | } | |
71 | ||
72 | static u32 | |
73 | netxen_poll_rsp(struct netxen_adapter *adapter) | |
74 | { | |
2edbb454 | 75 | u32 rsp = NX_CDRP_RSP_OK; |
d9e651bc DP |
76 | int timeout = 0; |
77 | ||
78 | do { | |
79 | /* give atleast 1ms for firmware to respond */ | |
80 | msleep(1); | |
81 | ||
82 | if (++timeout > NX_OS_CRB_RETRY_COUNT) | |
83 | return NX_CDRP_RSP_TIMEOUT; | |
84 | ||
f98a9f69 | 85 | rsp = NXRD32(adapter, NX_CDRP_CRB_OFFSET); |
d9e651bc DP |
86 | } while (!NX_CDRP_IS_RSP(rsp)); |
87 | ||
88 | return rsp; | |
89 | } | |
90 | ||
91 | static u32 | |
92 | netxen_issue_cmd(struct netxen_adapter *adapter, | |
93 | u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd) | |
94 | { | |
95 | u32 rsp; | |
96 | u32 signature = 0; | |
97 | u32 rcode = NX_RCODE_SUCCESS; | |
98 | ||
99 | signature = NX_CDRP_SIGNATURE_MAKE(pci_fn, version); | |
100 | ||
101 | /* Acquire semaphore before accessing CRB */ | |
102 | if (netxen_api_lock(adapter)) | |
103 | return NX_RCODE_TIMEOUT; | |
104 | ||
f98a9f69 | 105 | NXWR32(adapter, NX_SIGN_CRB_OFFSET, signature); |
d9e651bc | 106 | |
f98a9f69 | 107 | NXWR32(adapter, NX_ARG1_CRB_OFFSET, arg1); |
d9e651bc | 108 | |
f98a9f69 | 109 | NXWR32(adapter, NX_ARG2_CRB_OFFSET, arg2); |
d9e651bc | 110 | |
f98a9f69 | 111 | NXWR32(adapter, NX_ARG3_CRB_OFFSET, arg3); |
d9e651bc | 112 | |
f98a9f69 | 113 | NXWR32(adapter, NX_CDRP_CRB_OFFSET, NX_CDRP_FORM_CMD(cmd)); |
d9e651bc DP |
114 | |
115 | rsp = netxen_poll_rsp(adapter); | |
116 | ||
117 | if (rsp == NX_CDRP_RSP_TIMEOUT) { | |
118 | printk(KERN_ERR "%s: card response timeout.\n", | |
119 | netxen_nic_driver_name); | |
120 | ||
121 | rcode = NX_RCODE_TIMEOUT; | |
122 | } else if (rsp == NX_CDRP_RSP_FAIL) { | |
f98a9f69 | 123 | rcode = NXRD32(adapter, NX_ARG1_CRB_OFFSET); |
d9e651bc DP |
124 | |
125 | printk(KERN_ERR "%s: failed card response code:0x%x\n", | |
126 | netxen_nic_driver_name, rcode); | |
127 | } | |
128 | ||
129 | /* Release semaphore */ | |
130 | netxen_api_unlock(adapter); | |
131 | ||
132 | return rcode; | |
133 | } | |
134 | ||
9ad27643 DP |
135 | int |
136 | nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu) | |
d9e651bc DP |
137 | { |
138 | u32 rcode = NX_RCODE_SUCCESS; | |
becf46a0 | 139 | struct netxen_recv_context *recv_ctx = &adapter->recv_ctx; |
d9e651bc DP |
140 | |
141 | if (recv_ctx->state == NX_HOST_CTX_STATE_ACTIVE) | |
142 | rcode = netxen_issue_cmd(adapter, | |
143 | adapter->ahw.pci_func, | |
144 | NXHAL_VERSION, | |
145 | recv_ctx->context_id, | |
146 | mtu, | |
147 | 0, | |
148 | NX_CDRP_CMD_SET_MTU); | |
149 | ||
9ad27643 DP |
150 | if (rcode != NX_RCODE_SUCCESS) |
151 | return -EIO; | |
152 | ||
153 | return 0; | |
d9e651bc DP |
154 | } |
155 | ||
156 | static int | |
157 | nx_fw_cmd_create_rx_ctx(struct netxen_adapter *adapter) | |
158 | { | |
159 | void *addr; | |
160 | nx_hostrq_rx_ctx_t *prq; | |
161 | nx_cardrsp_rx_ctx_t *prsp; | |
162 | nx_hostrq_rds_ring_t *prq_rds; | |
163 | nx_hostrq_sds_ring_t *prq_sds; | |
164 | nx_cardrsp_rds_ring_t *prsp_rds; | |
165 | nx_cardrsp_sds_ring_t *prsp_sds; | |
166 | struct nx_host_rds_ring *rds_ring; | |
d8b100c5 | 167 | struct nx_host_sds_ring *sds_ring; |
d9e651bc DP |
168 | |
169 | dma_addr_t hostrq_phys_addr, cardrsp_phys_addr; | |
170 | u64 phys_addr; | |
171 | ||
172 | int i, nrds_rings, nsds_rings; | |
173 | size_t rq_size, rsp_size; | |
2edbb454 | 174 | u32 cap, reg, val; |
d9e651bc DP |
175 | |
176 | int err; | |
177 | ||
becf46a0 | 178 | struct netxen_recv_context *recv_ctx = &adapter->recv_ctx; |
d9e651bc | 179 | |
d9e651bc | 180 | nrds_rings = adapter->max_rds_rings; |
d8b100c5 | 181 | nsds_rings = adapter->max_sds_rings; |
d9e651bc DP |
182 | |
183 | rq_size = | |
184 | SIZEOF_HOSTRQ_RX(nx_hostrq_rx_ctx_t, nrds_rings, nsds_rings); | |
185 | rsp_size = | |
186 | SIZEOF_CARDRSP_RX(nx_cardrsp_rx_ctx_t, nrds_rings, nsds_rings); | |
187 | ||
188 | addr = pci_alloc_consistent(adapter->pdev, | |
189 | rq_size, &hostrq_phys_addr); | |
190 | if (addr == NULL) | |
191 | return -ENOMEM; | |
192 | prq = (nx_hostrq_rx_ctx_t *)addr; | |
193 | ||
194 | addr = pci_alloc_consistent(adapter->pdev, | |
195 | rsp_size, &cardrsp_phys_addr); | |
196 | if (addr == NULL) { | |
197 | err = -ENOMEM; | |
198 | goto out_free_rq; | |
199 | } | |
200 | prsp = (nx_cardrsp_rx_ctx_t *)addr; | |
201 | ||
202 | prq->host_rsp_dma_addr = cpu_to_le64(cardrsp_phys_addr); | |
203 | ||
204 | cap = (NX_CAP0_LEGACY_CONTEXT | NX_CAP0_LEGACY_MN); | |
205 | cap |= (NX_CAP0_JUMBO_CONTIGUOUS | NX_CAP0_LRO_CONTIGUOUS); | |
206 | ||
207 | prq->capabilities[0] = cpu_to_le32(cap); | |
208 | prq->host_int_crb_mode = | |
209 | cpu_to_le32(NX_HOST_INT_CRB_MODE_SHARED); | |
210 | prq->host_rds_crb_mode = | |
211 | cpu_to_le32(NX_HOST_RDS_CRB_MODE_UNIQUE); | |
212 | ||
213 | prq->num_rds_rings = cpu_to_le16(nrds_rings); | |
214 | prq->num_sds_rings = cpu_to_le16(nsds_rings); | |
2edbb454 DP |
215 | prq->rds_ring_offset = cpu_to_le32(0); |
216 | ||
217 | val = le32_to_cpu(prq->rds_ring_offset) + | |
d9e651bc | 218 | (sizeof(nx_hostrq_rds_ring_t) * nrds_rings); |
2edbb454 | 219 | prq->sds_ring_offset = cpu_to_le32(val); |
d9e651bc | 220 | |
2edbb454 DP |
221 | prq_rds = (nx_hostrq_rds_ring_t *)(prq->data + |
222 | le32_to_cpu(prq->rds_ring_offset)); | |
d9e651bc DP |
223 | |
224 | for (i = 0; i < nrds_rings; i++) { | |
225 | ||
226 | rds_ring = &recv_ctx->rds_rings[i]; | |
227 | ||
228 | prq_rds[i].host_phys_addr = cpu_to_le64(rds_ring->phys_addr); | |
438627c7 | 229 | prq_rds[i].ring_size = cpu_to_le32(rds_ring->num_desc); |
d9e651bc DP |
230 | prq_rds[i].ring_kind = cpu_to_le32(i); |
231 | prq_rds[i].buff_size = cpu_to_le64(rds_ring->dma_size); | |
232 | } | |
233 | ||
2edbb454 DP |
234 | prq_sds = (nx_hostrq_sds_ring_t *)(prq->data + |
235 | le32_to_cpu(prq->sds_ring_offset)); | |
d9e651bc | 236 | |
d8b100c5 DP |
237 | for (i = 0; i < nsds_rings; i++) { |
238 | ||
239 | sds_ring = &recv_ctx->sds_rings[i]; | |
240 | ||
241 | prq_sds[i].host_phys_addr = cpu_to_le64(sds_ring->phys_addr); | |
242 | prq_sds[i].ring_size = cpu_to_le32(sds_ring->num_desc); | |
243 | prq_sds[i].msi_index = cpu_to_le16(i); | |
244 | } | |
d9e651bc DP |
245 | |
246 | phys_addr = hostrq_phys_addr; | |
247 | err = netxen_issue_cmd(adapter, | |
248 | adapter->ahw.pci_func, | |
249 | NXHAL_VERSION, | |
250 | (u32)(phys_addr >> 32), | |
251 | (u32)(phys_addr & 0xffffffff), | |
252 | rq_size, | |
253 | NX_CDRP_CMD_CREATE_RX_CTX); | |
254 | if (err) { | |
255 | printk(KERN_WARNING | |
256 | "Failed to create rx ctx in firmware%d\n", err); | |
257 | goto out_free_rsp; | |
258 | } | |
259 | ||
260 | ||
261 | prsp_rds = ((nx_cardrsp_rds_ring_t *) | |
2edbb454 | 262 | &prsp->data[le32_to_cpu(prsp->rds_ring_offset)]); |
d9e651bc | 263 | |
2edbb454 | 264 | for (i = 0; i < le16_to_cpu(prsp->num_rds_rings); i++) { |
d9e651bc DP |
265 | rds_ring = &recv_ctx->rds_rings[i]; |
266 | ||
267 | reg = le32_to_cpu(prsp_rds[i].host_producer_crb); | |
268 | rds_ring->crb_rcv_producer = NETXEN_NIC_REG(reg - 0x200); | |
269 | } | |
270 | ||
271 | prsp_sds = ((nx_cardrsp_sds_ring_t *) | |
2edbb454 | 272 | &prsp->data[le32_to_cpu(prsp->sds_ring_offset)]); |
d9e651bc | 273 | |
d8b100c5 DP |
274 | for (i = 0; i < le16_to_cpu(prsp->num_sds_rings); i++) { |
275 | sds_ring = &recv_ctx->sds_rings[i]; | |
276 | ||
277 | reg = le32_to_cpu(prsp_sds[i].host_consumer_crb); | |
278 | sds_ring->crb_sts_consumer = NETXEN_NIC_REG(reg - 0x200); | |
279 | ||
280 | reg = le32_to_cpu(prsp_sds[i].interrupt_crb); | |
281 | sds_ring->crb_intr_mask = NETXEN_NIC_REG(reg - 0x200); | |
282 | } | |
d9e651bc DP |
283 | |
284 | recv_ctx->state = le32_to_cpu(prsp->host_ctx_state); | |
285 | recv_ctx->context_id = le16_to_cpu(prsp->context_id); | |
2edbb454 | 286 | recv_ctx->virt_port = prsp->virt_port; |
d9e651bc DP |
287 | |
288 | out_free_rsp: | |
289 | pci_free_consistent(adapter->pdev, rsp_size, prsp, cardrsp_phys_addr); | |
290 | out_free_rq: | |
291 | pci_free_consistent(adapter->pdev, rq_size, prq, hostrq_phys_addr); | |
292 | return err; | |
293 | } | |
294 | ||
295 | static void | |
296 | nx_fw_cmd_destroy_rx_ctx(struct netxen_adapter *adapter) | |
297 | { | |
becf46a0 | 298 | struct netxen_recv_context *recv_ctx = &adapter->recv_ctx; |
d9e651bc DP |
299 | |
300 | if (netxen_issue_cmd(adapter, | |
301 | adapter->ahw.pci_func, | |
302 | NXHAL_VERSION, | |
303 | recv_ctx->context_id, | |
304 | NX_DESTROY_CTX_RESET, | |
305 | 0, | |
306 | NX_CDRP_CMD_DESTROY_RX_CTX)) { | |
307 | ||
308 | printk(KERN_WARNING | |
309 | "%s: Failed to destroy rx ctx in firmware\n", | |
310 | netxen_nic_driver_name); | |
311 | } | |
312 | } | |
313 | ||
314 | static int | |
315 | nx_fw_cmd_create_tx_ctx(struct netxen_adapter *adapter) | |
316 | { | |
317 | nx_hostrq_tx_ctx_t *prq; | |
318 | nx_hostrq_cds_ring_t *prq_cds; | |
319 | nx_cardrsp_tx_ctx_t *prsp; | |
320 | void *rq_addr, *rsp_addr; | |
321 | size_t rq_size, rsp_size; | |
322 | u32 temp; | |
323 | int err = 0; | |
324 | u64 offset, phys_addr; | |
325 | dma_addr_t rq_phys_addr, rsp_phys_addr; | |
4ea528a1 DP |
326 | struct nx_host_tx_ring *tx_ring = adapter->tx_ring; |
327 | struct netxen_recv_context *recv_ctx = &adapter->recv_ctx; | |
d9e651bc DP |
328 | |
329 | rq_size = SIZEOF_HOSTRQ_TX(nx_hostrq_tx_ctx_t); | |
330 | rq_addr = pci_alloc_consistent(adapter->pdev, | |
331 | rq_size, &rq_phys_addr); | |
332 | if (!rq_addr) | |
333 | return -ENOMEM; | |
334 | ||
335 | rsp_size = SIZEOF_CARDRSP_TX(nx_cardrsp_tx_ctx_t); | |
336 | rsp_addr = pci_alloc_consistent(adapter->pdev, | |
337 | rsp_size, &rsp_phys_addr); | |
338 | if (!rsp_addr) { | |
339 | err = -ENOMEM; | |
340 | goto out_free_rq; | |
341 | } | |
342 | ||
343 | memset(rq_addr, 0, rq_size); | |
344 | prq = (nx_hostrq_tx_ctx_t *)rq_addr; | |
345 | ||
346 | memset(rsp_addr, 0, rsp_size); | |
347 | prsp = (nx_cardrsp_tx_ctx_t *)rsp_addr; | |
348 | ||
349 | prq->host_rsp_dma_addr = cpu_to_le64(rsp_phys_addr); | |
350 | ||
351 | temp = (NX_CAP0_LEGACY_CONTEXT | NX_CAP0_LEGACY_MN | NX_CAP0_LSO); | |
352 | prq->capabilities[0] = cpu_to_le32(temp); | |
353 | ||
354 | prq->host_int_crb_mode = | |
355 | cpu_to_le32(NX_HOST_INT_CRB_MODE_SHARED); | |
356 | ||
357 | prq->interrupt_ctl = 0; | |
358 | prq->msi_index = 0; | |
359 | ||
360 | prq->dummy_dma_addr = cpu_to_le64(adapter->dummy_dma.phys_addr); | |
361 | ||
4ea528a1 | 362 | offset = recv_ctx->phys_addr + sizeof(struct netxen_ring_ctx); |
d9e651bc DP |
363 | prq->cmd_cons_dma_addr = cpu_to_le64(offset); |
364 | ||
365 | prq_cds = &prq->cds_ring; | |
366 | ||
d877f1e3 DP |
367 | prq_cds->host_phys_addr = cpu_to_le64(tx_ring->phys_addr); |
368 | prq_cds->ring_size = cpu_to_le32(tx_ring->num_desc); | |
d9e651bc DP |
369 | |
370 | phys_addr = rq_phys_addr; | |
371 | err = netxen_issue_cmd(adapter, | |
372 | adapter->ahw.pci_func, | |
373 | NXHAL_VERSION, | |
374 | (u32)(phys_addr >> 32), | |
375 | ((u32)phys_addr & 0xffffffff), | |
376 | rq_size, | |
377 | NX_CDRP_CMD_CREATE_TX_CTX); | |
378 | ||
379 | if (err == NX_RCODE_SUCCESS) { | |
380 | temp = le32_to_cpu(prsp->cds_ring.host_producer_crb); | |
d877f1e3 | 381 | tx_ring->crb_cmd_producer = NETXEN_NIC_REG(temp - 0x200); |
d9e651bc DP |
382 | #if 0 |
383 | adapter->tx_state = | |
384 | le32_to_cpu(prsp->host_ctx_state); | |
385 | #endif | |
386 | adapter->tx_context_id = | |
387 | le16_to_cpu(prsp->context_id); | |
388 | } else { | |
389 | printk(KERN_WARNING | |
390 | "Failed to create tx ctx in firmware%d\n", err); | |
391 | err = -EIO; | |
392 | } | |
393 | ||
394 | pci_free_consistent(adapter->pdev, rsp_size, rsp_addr, rsp_phys_addr); | |
395 | ||
396 | out_free_rq: | |
397 | pci_free_consistent(adapter->pdev, rq_size, rq_addr, rq_phys_addr); | |
398 | ||
399 | return err; | |
400 | } | |
401 | ||
402 | static void | |
403 | nx_fw_cmd_destroy_tx_ctx(struct netxen_adapter *adapter) | |
404 | { | |
405 | if (netxen_issue_cmd(adapter, | |
406 | adapter->ahw.pci_func, | |
407 | NXHAL_VERSION, | |
408 | adapter->tx_context_id, | |
409 | NX_DESTROY_CTX_RESET, | |
410 | 0, | |
411 | NX_CDRP_CMD_DESTROY_TX_CTX)) { | |
412 | ||
413 | printk(KERN_WARNING | |
414 | "%s: Failed to destroy tx ctx in firmware\n", | |
415 | netxen_nic_driver_name); | |
416 | } | |
417 | } | |
418 | ||
419 | static u64 ctx_addr_sig_regs[][3] = { | |
420 | {NETXEN_NIC_REG(0x188), NETXEN_NIC_REG(0x18c), NETXEN_NIC_REG(0x1c0)}, | |
421 | {NETXEN_NIC_REG(0x190), NETXEN_NIC_REG(0x194), NETXEN_NIC_REG(0x1c4)}, | |
422 | {NETXEN_NIC_REG(0x198), NETXEN_NIC_REG(0x19c), NETXEN_NIC_REG(0x1c8)}, | |
423 | {NETXEN_NIC_REG(0x1a0), NETXEN_NIC_REG(0x1a4), NETXEN_NIC_REG(0x1cc)} | |
424 | }; | |
425 | ||
426 | #define CRB_CTX_ADDR_REG_LO(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][0]) | |
427 | #define CRB_CTX_ADDR_REG_HI(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][2]) | |
428 | #define CRB_CTX_SIGNATURE_REG(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][1]) | |
429 | ||
430 | #define lower32(x) ((u32)((x) & 0xffffffff)) | |
431 | #define upper32(x) ((u32)(((u64)(x) >> 32) & 0xffffffff)) | |
432 | ||
433 | static struct netxen_recv_crb recv_crb_registers[] = { | |
434 | /* Instance 0 */ | |
435 | { | |
436 | /* crb_rcv_producer: */ | |
437 | { | |
438 | NETXEN_NIC_REG(0x100), | |
439 | /* Jumbo frames */ | |
440 | NETXEN_NIC_REG(0x110), | |
441 | /* LRO */ | |
442 | NETXEN_NIC_REG(0x120) | |
443 | }, | |
444 | /* crb_sts_consumer: */ | |
f6d21f44 DP |
445 | { |
446 | NETXEN_NIC_REG(0x138), | |
447 | NETXEN_NIC_REG_2(0x000), | |
448 | NETXEN_NIC_REG_2(0x004), | |
449 | NETXEN_NIC_REG_2(0x008), | |
450 | }, | |
451 | /* sw_int_mask */ | |
452 | { | |
453 | CRB_SW_INT_MASK_0, | |
454 | NETXEN_NIC_REG_2(0x044), | |
455 | NETXEN_NIC_REG_2(0x048), | |
456 | NETXEN_NIC_REG_2(0x04c), | |
457 | }, | |
d9e651bc DP |
458 | }, |
459 | /* Instance 1 */ | |
460 | { | |
461 | /* crb_rcv_producer: */ | |
462 | { | |
463 | NETXEN_NIC_REG(0x144), | |
464 | /* Jumbo frames */ | |
465 | NETXEN_NIC_REG(0x154), | |
466 | /* LRO */ | |
467 | NETXEN_NIC_REG(0x164) | |
468 | }, | |
469 | /* crb_sts_consumer: */ | |
f6d21f44 DP |
470 | { |
471 | NETXEN_NIC_REG(0x17c), | |
472 | NETXEN_NIC_REG_2(0x020), | |
473 | NETXEN_NIC_REG_2(0x024), | |
474 | NETXEN_NIC_REG_2(0x028), | |
475 | }, | |
476 | /* sw_int_mask */ | |
477 | { | |
478 | CRB_SW_INT_MASK_1, | |
479 | NETXEN_NIC_REG_2(0x064), | |
480 | NETXEN_NIC_REG_2(0x068), | |
481 | NETXEN_NIC_REG_2(0x06c), | |
482 | }, | |
d9e651bc DP |
483 | }, |
484 | /* Instance 2 */ | |
485 | { | |
486 | /* crb_rcv_producer: */ | |
487 | { | |
488 | NETXEN_NIC_REG(0x1d8), | |
489 | /* Jumbo frames */ | |
490 | NETXEN_NIC_REG(0x1f8), | |
491 | /* LRO */ | |
492 | NETXEN_NIC_REG(0x208) | |
493 | }, | |
494 | /* crb_sts_consumer: */ | |
f6d21f44 DP |
495 | { |
496 | NETXEN_NIC_REG(0x220), | |
497 | NETXEN_NIC_REG_2(0x03c), | |
498 | NETXEN_NIC_REG_2(0x03c), | |
499 | NETXEN_NIC_REG_2(0x03c), | |
500 | }, | |
501 | /* sw_int_mask */ | |
502 | { | |
503 | CRB_SW_INT_MASK_2, | |
504 | NETXEN_NIC_REG_2(0x03c), | |
505 | NETXEN_NIC_REG_2(0x03c), | |
506 | NETXEN_NIC_REG_2(0x03c), | |
507 | }, | |
d9e651bc DP |
508 | }, |
509 | /* Instance 3 */ | |
510 | { | |
511 | /* crb_rcv_producer: */ | |
512 | { | |
513 | NETXEN_NIC_REG(0x22c), | |
514 | /* Jumbo frames */ | |
515 | NETXEN_NIC_REG(0x23c), | |
516 | /* LRO */ | |
517 | NETXEN_NIC_REG(0x24c) | |
518 | }, | |
519 | /* crb_sts_consumer: */ | |
f6d21f44 DP |
520 | { |
521 | NETXEN_NIC_REG(0x264), | |
522 | NETXEN_NIC_REG_2(0x03c), | |
523 | NETXEN_NIC_REG_2(0x03c), | |
524 | NETXEN_NIC_REG_2(0x03c), | |
525 | }, | |
526 | /* sw_int_mask */ | |
527 | { | |
528 | CRB_SW_INT_MASK_3, | |
529 | NETXEN_NIC_REG_2(0x03c), | |
530 | NETXEN_NIC_REG_2(0x03c), | |
531 | NETXEN_NIC_REG_2(0x03c), | |
532 | }, | |
d9e651bc DP |
533 | }, |
534 | }; | |
535 | ||
536 | static int | |
537 | netxen_init_old_ctx(struct netxen_adapter *adapter) | |
538 | { | |
539 | struct netxen_recv_context *recv_ctx; | |
540 | struct nx_host_rds_ring *rds_ring; | |
d8b100c5 | 541 | struct nx_host_sds_ring *sds_ring; |
d877f1e3 | 542 | struct nx_host_tx_ring *tx_ring; |
becf46a0 | 543 | int ring; |
f6d21f44 | 544 | int port = adapter->portnum; |
4ea528a1 | 545 | struct netxen_ring_ctx *hwctx; |
f6d21f44 | 546 | u32 signature; |
d9e651bc | 547 | |
4ea528a1 DP |
548 | tx_ring = adapter->tx_ring; |
549 | recv_ctx = &adapter->recv_ctx; | |
550 | hwctx = recv_ctx->hwctx; | |
551 | ||
f6d21f44 DP |
552 | hwctx->cmd_ring_addr = cpu_to_le64(tx_ring->phys_addr); |
553 | hwctx->cmd_ring_size = cpu_to_le32(tx_ring->num_desc); | |
d9e651bc | 554 | |
d9e651bc | 555 | |
becf46a0 DP |
556 | for (ring = 0; ring < adapter->max_rds_rings; ring++) { |
557 | rds_ring = &recv_ctx->rds_rings[ring]; | |
d9e651bc | 558 | |
f6d21f44 | 559 | hwctx->rcv_rings[ring].addr = |
becf46a0 | 560 | cpu_to_le64(rds_ring->phys_addr); |
f6d21f44 | 561 | hwctx->rcv_rings[ring].size = |
438627c7 | 562 | cpu_to_le32(rds_ring->num_desc); |
d9e651bc DP |
563 | } |
564 | ||
f6d21f44 DP |
565 | for (ring = 0; ring < adapter->max_sds_rings; ring++) { |
566 | sds_ring = &recv_ctx->sds_rings[ring]; | |
567 | ||
568 | if (ring == 0) { | |
569 | hwctx->sts_ring_addr = cpu_to_le64(sds_ring->phys_addr); | |
570 | hwctx->sts_ring_size = cpu_to_le32(sds_ring->num_desc); | |
571 | } | |
572 | hwctx->sts_rings[ring].addr = cpu_to_le64(sds_ring->phys_addr); | |
573 | hwctx->sts_rings[ring].size = cpu_to_le32(sds_ring->num_desc); | |
574 | hwctx->sts_rings[ring].msi_index = cpu_to_le16(ring); | |
575 | } | |
576 | hwctx->sts_ring_count = cpu_to_le32(adapter->max_sds_rings); | |
577 | ||
578 | signature = (adapter->max_sds_rings > 1) ? | |
579 | NETXEN_CTX_SIGNATURE_V2 : NETXEN_CTX_SIGNATURE; | |
580 | ||
581 | NXWR32(adapter, CRB_CTX_ADDR_REG_LO(port), | |
4ea528a1 | 582 | lower32(recv_ctx->phys_addr)); |
f6d21f44 | 583 | NXWR32(adapter, CRB_CTX_ADDR_REG_HI(port), |
4ea528a1 | 584 | upper32(recv_ctx->phys_addr)); |
f6d21f44 DP |
585 | NXWR32(adapter, CRB_CTX_SIGNATURE_REG(port), |
586 | signature | port); | |
d9e651bc DP |
587 | return 0; |
588 | } | |
589 | ||
d9e651bc DP |
590 | int netxen_alloc_hw_resources(struct netxen_adapter *adapter) |
591 | { | |
d9e651bc DP |
592 | void *addr; |
593 | int err = 0; | |
becf46a0 | 594 | int ring; |
d9e651bc DP |
595 | struct netxen_recv_context *recv_ctx; |
596 | struct nx_host_rds_ring *rds_ring; | |
d8b100c5 | 597 | struct nx_host_sds_ring *sds_ring; |
4ea528a1 | 598 | struct nx_host_tx_ring *tx_ring; |
d8b100c5 DP |
599 | |
600 | struct pci_dev *pdev = adapter->pdev; | |
601 | struct net_device *netdev = adapter->netdev; | |
f6d21f44 | 602 | int port = adapter->portnum; |
d9e651bc | 603 | |
4ea528a1 DP |
604 | recv_ctx = &adapter->recv_ctx; |
605 | tx_ring = adapter->tx_ring; | |
606 | ||
d8b100c5 | 607 | addr = pci_alloc_consistent(pdev, |
d9e651bc | 608 | sizeof(struct netxen_ring_ctx) + sizeof(uint32_t), |
4ea528a1 | 609 | &recv_ctx->phys_addr); |
d9e651bc | 610 | if (addr == NULL) { |
d8b100c5 | 611 | dev_err(&pdev->dev, "failed to allocate hw context\n"); |
d9e651bc DP |
612 | return -ENOMEM; |
613 | } | |
4ea528a1 | 614 | |
d9e651bc | 615 | memset(addr, 0, sizeof(struct netxen_ring_ctx)); |
4ea528a1 DP |
616 | recv_ctx->hwctx = (struct netxen_ring_ctx *)addr; |
617 | recv_ctx->hwctx->ctx_id = cpu_to_le32(port); | |
618 | recv_ctx->hwctx->cmd_consumer_offset = | |
619 | cpu_to_le64(recv_ctx->phys_addr + | |
d9e651bc | 620 | sizeof(struct netxen_ring_ctx)); |
d877f1e3 | 621 | tx_ring->hw_consumer = |
d9e651bc DP |
622 | (__le32 *)(((char *)addr) + sizeof(struct netxen_ring_ctx)); |
623 | ||
624 | /* cmd desc ring */ | |
d877f1e3 DP |
625 | addr = pci_alloc_consistent(pdev, TX_DESC_RINGSIZE(tx_ring), |
626 | &tx_ring->phys_addr); | |
d9e651bc DP |
627 | |
628 | if (addr == NULL) { | |
d8b100c5 DP |
629 | dev_err(&pdev->dev, "%s: failed to allocate tx desc ring\n", |
630 | netdev->name); | |
d9e651bc DP |
631 | return -ENOMEM; |
632 | } | |
633 | ||
d877f1e3 | 634 | tx_ring->desc_head = (struct cmd_desc_type0 *)addr; |
d9e651bc | 635 | |
becf46a0 | 636 | for (ring = 0; ring < adapter->max_rds_rings; ring++) { |
becf46a0 | 637 | rds_ring = &recv_ctx->rds_rings[ring]; |
d9e651bc | 638 | addr = pci_alloc_consistent(adapter->pdev, |
d8b100c5 | 639 | RCV_DESC_RINGSIZE(rds_ring), |
becf46a0 | 640 | &rds_ring->phys_addr); |
d9e651bc | 641 | if (addr == NULL) { |
d8b100c5 DP |
642 | dev_err(&pdev->dev, |
643 | "%s: failed to allocate rds ring [%d]\n", | |
644 | netdev->name, ring); | |
d9e651bc DP |
645 | err = -ENOMEM; |
646 | goto err_out_free; | |
647 | } | |
becf46a0 | 648 | rds_ring->desc_head = (struct rcv_desc *)addr; |
d9e651bc DP |
649 | |
650 | if (adapter->fw_major < 4) | |
becf46a0 | 651 | rds_ring->crb_rcv_producer = |
f6d21f44 | 652 | recv_crb_registers[port].crb_rcv_producer[ring]; |
d9e651bc DP |
653 | } |
654 | ||
d8b100c5 DP |
655 | for (ring = 0; ring < adapter->max_sds_rings; ring++) { |
656 | sds_ring = &recv_ctx->sds_rings[ring]; | |
657 | ||
658 | addr = pci_alloc_consistent(adapter->pdev, | |
659 | STATUS_DESC_RINGSIZE(sds_ring), | |
660 | &sds_ring->phys_addr); | |
661 | if (addr == NULL) { | |
662 | dev_err(&pdev->dev, | |
663 | "%s: failed to allocate sds ring [%d]\n", | |
664 | netdev->name, ring); | |
665 | err = -ENOMEM; | |
666 | goto err_out_free; | |
667 | } | |
668 | sds_ring->desc_head = (struct status_desc *)addr; | |
f6d21f44 DP |
669 | |
670 | sds_ring->crb_sts_consumer = | |
671 | recv_crb_registers[port].crb_sts_consumer[ring]; | |
672 | ||
673 | sds_ring->crb_intr_mask = | |
674 | recv_crb_registers[port].sw_int_mask[ring]; | |
becf46a0 | 675 | } |
becf46a0 | 676 | |
becf46a0 | 677 | |
d9e651bc | 678 | if (adapter->fw_major >= 4) { |
d9e651bc DP |
679 | err = nx_fw_cmd_create_rx_ctx(adapter); |
680 | if (err) | |
681 | goto err_out_free; | |
682 | err = nx_fw_cmd_create_tx_ctx(adapter); | |
683 | if (err) | |
684 | goto err_out_free; | |
685 | } else { | |
d9e651bc DP |
686 | err = netxen_init_old_ctx(adapter); |
687 | if (err) { | |
688 | netxen_free_hw_resources(adapter); | |
689 | return err; | |
690 | } | |
d9e651bc DP |
691 | } |
692 | ||
693 | return 0; | |
694 | ||
695 | err_out_free: | |
696 | netxen_free_hw_resources(adapter); | |
697 | return err; | |
698 | } | |
699 | ||
700 | void netxen_free_hw_resources(struct netxen_adapter *adapter) | |
701 | { | |
702 | struct netxen_recv_context *recv_ctx; | |
703 | struct nx_host_rds_ring *rds_ring; | |
d8b100c5 | 704 | struct nx_host_sds_ring *sds_ring; |
d877f1e3 | 705 | struct nx_host_tx_ring *tx_ring; |
becf46a0 | 706 | int ring; |
d9e651bc | 707 | |
f6d21f44 DP |
708 | int port = adapter->portnum; |
709 | ||
d9e651bc DP |
710 | if (adapter->fw_major >= 4) { |
711 | nx_fw_cmd_destroy_tx_ctx(adapter); | |
712 | nx_fw_cmd_destroy_rx_ctx(adapter); | |
f6d21f44 DP |
713 | } else { |
714 | netxen_api_lock(adapter); | |
715 | NXWR32(adapter, CRB_CTX_SIGNATURE_REG(port), | |
716 | NETXEN_CTX_RESET | port); | |
717 | netxen_api_unlock(adapter); | |
d9e651bc DP |
718 | } |
719 | ||
4ea528a1 DP |
720 | recv_ctx = &adapter->recv_ctx; |
721 | ||
722 | if (recv_ctx->hwctx != NULL) { | |
d9e651bc DP |
723 | pci_free_consistent(adapter->pdev, |
724 | sizeof(struct netxen_ring_ctx) + | |
725 | sizeof(uint32_t), | |
4ea528a1 DP |
726 | recv_ctx->hwctx, |
727 | recv_ctx->phys_addr); | |
728 | recv_ctx->hwctx = NULL; | |
d9e651bc DP |
729 | } |
730 | ||
4ea528a1 | 731 | tx_ring = adapter->tx_ring; |
d877f1e3 | 732 | if (tx_ring->desc_head != NULL) { |
d9e651bc | 733 | pci_free_consistent(adapter->pdev, |
d877f1e3 DP |
734 | TX_DESC_RINGSIZE(tx_ring), |
735 | tx_ring->desc_head, tx_ring->phys_addr); | |
736 | tx_ring->desc_head = NULL; | |
d9e651bc DP |
737 | } |
738 | ||
becf46a0 DP |
739 | for (ring = 0; ring < adapter->max_rds_rings; ring++) { |
740 | rds_ring = &recv_ctx->rds_rings[ring]; | |
d9e651bc | 741 | |
becf46a0 | 742 | if (rds_ring->desc_head != NULL) { |
d9e651bc | 743 | pci_free_consistent(adapter->pdev, |
d8b100c5 | 744 | RCV_DESC_RINGSIZE(rds_ring), |
becf46a0 DP |
745 | rds_ring->desc_head, |
746 | rds_ring->phys_addr); | |
747 | rds_ring->desc_head = NULL; | |
d9e651bc DP |
748 | } |
749 | } | |
becf46a0 | 750 | |
d8b100c5 DP |
751 | for (ring = 0; ring < adapter->max_sds_rings; ring++) { |
752 | sds_ring = &recv_ctx->sds_rings[ring]; | |
753 | ||
754 | if (sds_ring->desc_head != NULL) { | |
755 | pci_free_consistent(adapter->pdev, | |
756 | STATUS_DESC_RINGSIZE(sds_ring), | |
757 | sds_ring->desc_head, | |
758 | sds_ring->phys_addr); | |
759 | sds_ring->desc_head = NULL; | |
760 | } | |
becf46a0 | 761 | } |
d9e651bc DP |
762 | } |
763 |