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netdev: convert bulk of drivers to netdev_tx_t
[deliverable/linux.git] / drivers / net / netxen / netxen_nic_hw.c
CommitLineData
3d396eb1 1/*
5d242f1c 2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3d396eb1 3 * All rights reserved.
80922fbc 4 *
3d396eb1
AK		 5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
cb8011ad 9 *
3d396eb1
AK		 10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
cb8011ad 14 *
3d396eb1
AK		 15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
80922fbc 19 *
3d396eb1
AK		 20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
80922fbc 22 *
3d396eb1
AK		 23 * Contact Information:
24 * info@netxen.com
5d242f1c
DP		 25 * NetXen Inc,
26 * 18922 Forge Drive
27 * Cupertino, CA 95014-0701
3d396eb1
AK		 28 *
29 */
30
31#include "netxen_nic.h"
32#include "netxen_nic_hw.h"
3d396eb1 33
c9bdd4b5
ACM		 34#include <net/ip.h>
35
3ce06a32
DP		 36#define MASK(n) ((1ULL<<(n))-1)
37#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
38#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
39#define MS_WIN(addr) (addr & 0x0ffc0000)
40
41#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
42
43#define CRB_BLK(off) ((off >> 20) & 0x3f)
44#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
45#define CRB_WINDOW_2M (0x130060)
46#define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
47#define CRB_INDIRECT_2M (0x1e0000UL)
48
e98e3350
DP		 49#ifndef readq
50static inline u64 readq(void __iomem *addr)
51{
52 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
53}
54#endif
55
56#ifndef writeq
57static inline void writeq(u64 val, void __iomem *addr)
58{
59 writel(((u32) (val)), (addr));
60 writel(((u32) (val >> 32)), (addr + 4));
61}
62#endif
63
1fbe6323
DP		 64#define ADDR_IN_RANGE(addr, low, high) \
65 (((addr) < (high)) && ((addr) >= (low)))
66
67#define PCI_OFFSET_FIRST_RANGE(adapter, off) \
68 ((adapter)->ahw.pci_base0 + (off))
69#define PCI_OFFSET_SECOND_RANGE(adapter, off) \
70 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
71#define PCI_OFFSET_THIRD_RANGE(adapter, off) \
72 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
73
74static void __iomem *pci_base_offset(struct netxen_adapter *adapter,
75 unsigned long off)
76{
77 if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END))
78 return PCI_OFFSET_FIRST_RANGE(adapter, off);
79
80 if (ADDR_IN_RANGE(off, SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_END))
81 return PCI_OFFSET_SECOND_RANGE(adapter, off);
82
83 if (ADDR_IN_RANGE(off, THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_END))
84 return PCI_OFFSET_THIRD_RANGE(adapter, off);
85
86 return NULL;
87}
88
ea7eaa39
DP		 89static crb_128M_2M_block_map_t
90crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
3ce06a32
DP		 91 {{{0, 0, 0, 0} } }, /* 0: PCI */
92 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
93 {1, 0x0110000, 0x0120000, 0x130000},
94 {1, 0x0120000, 0x0122000, 0x124000},
95 {1, 0x0130000, 0x0132000, 0x126000},
96 {1, 0x0140000, 0x0142000, 0x128000},
97 {1, 0x0150000, 0x0152000, 0x12a000},
98 {1, 0x0160000, 0x0170000, 0x110000},
99 {1, 0x0170000, 0x0172000, 0x12e000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {1, 0x01e0000, 0x01e0800, 0x122000},
107 {0, 0x0000000, 0x0000000, 0x000000} } },
108 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
109 {{{0, 0, 0, 0} } }, /* 3: */
110 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
111 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
112 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
113 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
114 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {1, 0x08f0000, 0x08f2000, 0x172000} } },
130 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {1, 0x09f0000, 0x09f2000, 0x176000} } },
146 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
162 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
178 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
179 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
180 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
181 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
182 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
183 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
184 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
185 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
186 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
187 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
188 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
189 {{{0, 0, 0, 0} } }, /* 23: */
190 {{{0, 0, 0, 0} } }, /* 24: */
191 {{{0, 0, 0, 0} } }, /* 25: */
192 {{{0, 0, 0, 0} } }, /* 26: */
193 {{{0, 0, 0, 0} } }, /* 27: */
194 {{{0, 0, 0, 0} } }, /* 28: */
195 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
196 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
197 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
198 {{{0} } }, /* 32: PCI */
199 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
200 {1, 0x2110000, 0x2120000, 0x130000},
201 {1, 0x2120000, 0x2122000, 0x124000},
202 {1, 0x2130000, 0x2132000, 0x126000},
203 {1, 0x2140000, 0x2142000, 0x128000},
204 {1, 0x2150000, 0x2152000, 0x12a000},
205 {1, 0x2160000, 0x2170000, 0x110000},
206 {1, 0x2170000, 0x2172000, 0x12e000},
207 {0, 0x0000000, 0x0000000, 0x000000},
208 {0, 0x0000000, 0x0000000, 0x000000},
209 {0, 0x0000000, 0x0000000, 0x000000},
210 {0, 0x0000000, 0x0000000, 0x000000},
211 {0, 0x0000000, 0x0000000, 0x000000},
212 {0, 0x0000000, 0x0000000, 0x000000},
213 {0, 0x0000000, 0x0000000, 0x000000},
214 {0, 0x0000000, 0x0000000, 0x000000} } },
215 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
216 {{{0} } }, /* 35: */
217 {{{0} } }, /* 36: */
218 {{{0} } }, /* 37: */
219 {{{0} } }, /* 38: */
220 {{{0} } }, /* 39: */
221 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
222 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
223 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
224 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
225 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
226 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
227 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
228 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
229 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
230 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
231 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
232 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
233 {{{0} } }, /* 52: */
234 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
235 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
236 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
237 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
238 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
239 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
240 {{{0} } }, /* 59: I2C0 */
241 {{{0} } }, /* 60: I2C1 */
242 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
243 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
244 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
245};
246
247/*
248 * top 12 bits of crb internal address (hub, agent)
249 */
250static unsigned crb_hub_agt[64] =
251{
252 0,
253 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
254 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
255 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
256 0,
257 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
258 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
259 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
260 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
261 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
262 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
263 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
264 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
265 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
266 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
267 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
268 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
269 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
270 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
271 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
272 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
273 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
274 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
275 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
276 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
277 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
278 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
279 0,
280 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
281 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
282 0,
283 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
284 0,
285 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
286 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
287 0,
288 0,
289 0,
290 0,
291 0,
292 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
293 0,
294 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
295 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
296 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
297 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
298 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
299 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
300 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
301 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
302 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
303 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
304 0,
305 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
306 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
307 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
308 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
309 0,
310 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
311 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
312 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
313 0,
314 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
315 0,
316};
317
3d396eb1
AK		 318/* PCI Windowing for DDR regions. */
319
3ce06a32 320#define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
3d396eb1 321
c9517e58
DP		 322#define NETXEN_PCIE_SEM_TIMEOUT 10000
323
324int
325netxen_pcie_sem_lock(struct netxen_adapter *adapter, int sem, u32 id_reg)
326{
327 int done = 0, timeout = 0;
328
329 while (!done) {
330 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_LOCK(sem)));
331 if (done == 1)
332 break;
333 if (++timeout >= NETXEN_PCIE_SEM_TIMEOUT)
334 return -1;
335 msleep(1);
336 }
337
338 if (id_reg)
339 NXWR32(adapter, id_reg, adapter->portnum);
340
341 return 0;
342}
343
344void
345netxen_pcie_sem_unlock(struct netxen_adapter *adapter, int sem)
346{
347 int val;
348 val = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
349}
350
3ad4467c
DP		 351int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port)
352{
353 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
354 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447);
355 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5);
356 }
357
358 return 0;
359}
360
361/* Disable an XG interface */
362int netxen_niu_disable_xg_port(struct netxen_adapter *adapter)
363{
364 __u32 mac_cfg;
365 u32 port = adapter->physical_port;
366
367 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
368 return 0;
369
370 if (port > NETXEN_NIU_MAX_XG_PORTS)
371 return -EINVAL;
372
373 mac_cfg = 0;
374 if (NXWR32(adapter,
375 NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg))
376 return -EIO;
377 return 0;
378}
379
623621b0
DP		 380#define NETXEN_UNICAST_ADDR(port, index) \
381 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
382#define NETXEN_MCAST_ADDR(port, index) \
383 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
384#define MAC_HI(addr) \
385 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
386#define MAC_LO(addr) \
387 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
388
3ad4467c
DP		 389int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
390{
391 __u32 reg;
392 u32 port = adapter->physical_port;
393
394 if (port > NETXEN_NIU_MAX_XG_PORTS)
395 return -EINVAL;
396
397 reg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port));
398 if (mode == NETXEN_NIU_PROMISC_MODE)
399 reg = (reg | 0x2000UL);
400 else
401 reg = (reg & ~0x2000UL);
402
403 if (mode == NETXEN_NIU_ALLMULTI_MODE)
404 reg = (reg | 0x1000UL);
405 else
406 reg = (reg & ~0x1000UL);
407
408 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
409
410 return 0;
411}
412
413int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
414{
415 u32 mac_hi, mac_lo;
416 u32 reg_hi, reg_lo;
417
418 u8 phy = adapter->physical_port;
419
420 if (phy >= NETXEN_NIU_MAX_XG_PORTS)
421 return -EINVAL;
422
423 mac_lo = ((u32)addr[0] << 16) | ((u32)addr[1] << 24);
424 mac_hi = addr[2] | ((u32)addr[3] << 8) |
425 ((u32)addr[4] << 16) | ((u32)addr[5] << 24);
426
427 reg_lo = NETXEN_NIU_XGE_STATION_ADDR_0_1 + (0x10000 * phy);
428 reg_hi = NETXEN_NIU_XGE_STATION_ADDR_0_HI + (0x10000 * phy);
429
430 /* write twice to flush */
431 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
432 return -EIO;
433 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
434 return -EIO;
435
436 return 0;
437}
438
623621b0
DP		 439static int
440netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
441{
442 u32 val = 0;
443 u16 port = adapter->physical_port;
444 u8 *addr = adapter->netdev->dev_addr;
445
446 if (adapter->mc_enabled)
447 return 0;
448
f98a9f69 449 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
623621b0 450 val |= (1UL << (28+port));
f98a9f69 451 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
623621b0
DP		 452
453 /* add broadcast addr to filter */
454 val = 0xffffff;
f98a9f69
DP		 455 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
456 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
623621b0
DP		 457
458 /* add station addr to filter */
459 val = MAC_HI(addr);
f98a9f69 460 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
623621b0 461 val = MAC_LO(addr);
f98a9f69 462 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val);
623621b0
DP		 463
464 adapter->mc_enabled = 1;
465 return 0;
466}
467
468static int
469netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
470{
471 u32 val = 0;
472 u16 port = adapter->physical_port;
473 u8 *addr = adapter->netdev->dev_addr;
474
475 if (!adapter->mc_enabled)
476 return 0;
477
f98a9f69 478 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
623621b0 479 val &= ~(1UL << (28+port));
f98a9f69 480 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
623621b0
DP		 481
482 val = MAC_HI(addr);
f98a9f69 483 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
623621b0 484 val = MAC_LO(addr);
f98a9f69 485 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
623621b0 486
f98a9f69
DP		 487 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
488 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
623621b0
DP		 489
490 adapter->mc_enabled = 0;
491 return 0;
492}
493
494static int
495netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
496 int index, u8 *addr)
497{
498 u32 hi = 0, lo = 0;
499 u16 port = adapter->physical_port;
500
501 lo = MAC_LO(addr);
502 hi = MAC_HI(addr);
503
f98a9f69
DP		 504 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi);
505 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo);
623621b0
DP		 506
507 return 0;
508}
509
c9fc891f 510void netxen_p2_nic_set_multi(struct net_device *netdev)
3d396eb1 511{
3176ff3e 512 struct netxen_adapter *adapter = netdev_priv(netdev);
3d396eb1 513 struct dev_mc_list *mc_ptr;
623621b0
DP		 514 u8 null_addr[6];
515 int index = 0;
516
517 memset(null_addr, 0, 6);
3d396eb1 518
3d396eb1 519 if (netdev->flags & IFF_PROMISC) {
623621b0
DP		 520
521 adapter->set_promisc(adapter,
522 NETXEN_NIU_PROMISC_MODE);
523
524 /* Full promiscuous mode */
525 netxen_nic_disable_mcast_filter(adapter);
526
527 return;
528 }
529
530 if (netdev->mc_count == 0) {
531 adapter->set_promisc(adapter,
532 NETXEN_NIU_NON_PROMISC_MODE);
533 netxen_nic_disable_mcast_filter(adapter);
534 return;
535 }
536
537 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
538 if (netdev->flags & IFF_ALLMULTI ||
539 netdev->mc_count > adapter->max_mc_count) {
540 netxen_nic_disable_mcast_filter(adapter);
541 return;
3d396eb1 542 }
623621b0
DP		 543
544 netxen_nic_enable_mcast_filter(adapter);
545
546 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++)
547 netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr);
548
549 if (index != netdev->mc_count)
550 printk(KERN_WARNING "%s: %s multicast address count mismatch\n",
551 netxen_nic_driver_name, netdev->name);
552
553 /* Clear out remaining addresses */
554 for (; index < adapter->max_mc_count; index++)
555 netxen_nic_set_mcast_addr(adapter, index, null_addr);
3d396eb1
AK		 556}
557
c9fc891f
DP		 558static int
559netxen_send_cmd_descs(struct netxen_adapter *adapter,
d877f1e3 560 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
c9fc891f 561{
d877f1e3 562 u32 i, producer, consumer;
c9fc891f
DP		 563 struct netxen_cmd_buffer *pbuf;
564 struct cmd_desc_type0 *cmd_desc;
d877f1e3 565 struct nx_host_tx_ring *tx_ring;
c9fc891f
DP		 566
567 i = 0;
568
4ea528a1 569 tx_ring = adapter->tx_ring;
b2af9cb0 570 __netif_tx_lock_bh(tx_ring->txq);
03e678ee 571
d877f1e3
DP		 572 producer = tx_ring->producer;
573 consumer = tx_ring->sw_consumer;
574
b2af9cb0
DP		 575 if (nr_desc >= netxen_tx_avail(tx_ring)) {
576 netif_tx_stop_queue(tx_ring->txq);
577 __netif_tx_unlock_bh(tx_ring->txq);
d877f1e3
DP		 578 return -EBUSY;
579 }
580
c9fc891f
DP		 581 do {
582 cmd_desc = &cmd_desc_arr[i];
583
d877f1e3 584 pbuf = &tx_ring->cmd_buf_arr[producer];
c9fc891f 585 pbuf->skb = NULL;
c9fc891f 586 pbuf->frag_count = 0;
c9fc891f 587
d877f1e3 588 memcpy(&tx_ring->desc_head[producer],
c9fc891f
DP		 589 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
590
d877f1e3 591 producer = get_next_index(producer, tx_ring->num_desc);
c9fc891f
DP		 592 i++;
593
d877f1e3 594 } while (i != nr_desc);
c9fc891f 595
d877f1e3 596 tx_ring->producer = producer;
c9fc891f 597
cb2107be 598 netxen_nic_update_cmd_producer(adapter, tx_ring);
c9fc891f 599
b2af9cb0 600 __netif_tx_unlock_bh(tx_ring->txq);
03e678ee 601
c9fc891f
DP		 602 return 0;
603}
604
5cf4d323
DP		 605static int
606nx_p3_sre_macaddr_change(struct netxen_adapter *adapter, u8 *addr, unsigned op)
c9fc891f 607{
c9fc891f 608 nx_nic_req_t req;
2edbb454
DP		 609 nx_mac_req_t *mac_req;
610 u64 word;
c9fc891f
DP		 611
612 memset(&req, 0, sizeof(nx_nic_req_t));
2edbb454
DP		 613 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
614
615 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16);
616 req.req_hdr = cpu_to_le64(word);
617
618 mac_req = (nx_mac_req_t *)&req.words[0];
619 mac_req->op = op;
620 memcpy(mac_req->mac_addr, addr, 6);
c9fc891f 621
5cf4d323
DP		 622 return netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
623}
624
625static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
626 u8 *addr, struct list_head *del_list)
627{
628 struct list_head *head;
629 nx_mac_list_t *cur;
630
631 /* look up if already exists */
632 list_for_each(head, del_list) {
633 cur = list_entry(head, nx_mac_list_t, list);
634
635 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
636 list_move_tail(head, &adapter->mac_list);
637 return 0;
638 }
c9fc891f
DP		 639 }
640
5cf4d323
DP		 641 cur = kzalloc(sizeof(nx_mac_list_t), GFP_ATOMIC);
642 if (cur == NULL) {
643 printk(KERN_ERR "%s: failed to add mac address filter\n",
644 adapter->netdev->name);
645 return -ENOMEM;
646 }
647 memcpy(cur->mac_addr, addr, ETH_ALEN);
648 list_add_tail(&cur->list, &adapter->mac_list);
649 return nx_p3_sre_macaddr_change(adapter,
650 cur->mac_addr, NETXEN_MAC_ADD);
c9fc891f
DP		 651}
652
653void netxen_p3_nic_set_multi(struct net_device *netdev)
654{
655 struct netxen_adapter *adapter = netdev_priv(netdev);
c9fc891f
DP		 656 struct dev_mc_list *mc_ptr;
657 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
9ad27643 658 u32 mode = VPORT_MISS_MODE_DROP;
5cf4d323
DP		 659 LIST_HEAD(del_list);
660 struct list_head *head;
661 nx_mac_list_t *cur;
c9fc891f 662
5cf4d323 663 list_splice_tail_init(&adapter->mac_list, &del_list);
c9fc891f 664
5cf4d323
DP		 665 nx_p3_nic_add_mac(adapter, netdev->dev_addr, &del_list);
666 nx_p3_nic_add_mac(adapter, bcast_addr, &del_list);
9ad27643
DP		 667
668 if (netdev->flags & IFF_PROMISC) {
669 mode = VPORT_MISS_MODE_ACCEPT_ALL;
670 goto send_fw_cmd;
671 }
672
673 if ((netdev->flags & IFF_ALLMULTI) ||
674 (netdev->mc_count > adapter->max_mc_count)) {
675 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
676 goto send_fw_cmd;
677 }
678
c9fc891f 679 if (netdev->mc_count > 0) {
c9fc891f
DP		 680 for (mc_ptr = netdev->mc_list; mc_ptr;
681 mc_ptr = mc_ptr->next) {
5cf4d323 682 nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr, &del_list);
c9fc891f
DP		 683 }
684 }
9ad27643
DP		 685
686send_fw_cmd:
687 adapter->set_promisc(adapter, mode);
5cf4d323
DP		 688 head = &del_list;
689 while (!list_empty(head)) {
690 cur = list_entry(head->next, nx_mac_list_t, list);
691
692 nx_p3_sre_macaddr_change(adapter,
693 cur->mac_addr, NETXEN_MAC_DEL);
694 list_del(&cur->list);
c9fc891f 695 kfree(cur);
c9fc891f
DP		 696 }
697}
698
9ad27643
DP		 699int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
700{
701 nx_nic_req_t req;
2edbb454 702 u64 word;
9ad27643
DP		 703
704 memset(&req, 0, sizeof(nx_nic_req_t));
705
2edbb454
DP		 706 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
707
708 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
709 ((u64)adapter->portnum << 16);
710 req.req_hdr = cpu_to_le64(word);
711
9ad27643
DP		 712 req.words[0] = cpu_to_le64(mode);
713
714 return netxen_send_cmd_descs(adapter,
715 (struct cmd_desc_type0 *)&req, 1);
716}
717
06e9d9f9
DP		 718void netxen_p3_free_mac_list(struct netxen_adapter *adapter)
719{
5cf4d323
DP		 720 nx_mac_list_t *cur;
721 struct list_head *head = &adapter->mac_list;
722
723 while (!list_empty(head)) {
724 cur = list_entry(head->next, nx_mac_list_t, list);
725 nx_p3_sre_macaddr_change(adapter,
726 cur->mac_addr, NETXEN_MAC_DEL);
727 list_del(&cur->list);
06e9d9f9 728 kfree(cur);
06e9d9f9
DP		 729 }
730}
731
3d0a3cc9
DP		 732int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
733{
734 /* assuming caller has already copied new addr to netdev */
735 netxen_p3_nic_set_multi(adapter->netdev);
736 return 0;
737}
738
cd1f8160
DP		 739#define NETXEN_CONFIG_INTR_COALESCE 3
740
741/*
742 * Send the interrupt coalescing parameter set by ethtool to the card.
743 */
744int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
745{
746 nx_nic_req_t req;
2edbb454 747 u64 word;
cd1f8160
DP		 748 int rv;
749
750 memset(&req, 0, sizeof(nx_nic_req_t));
751
1bb482f8 752 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
2edbb454
DP		 753
754 word = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
755 req.req_hdr = cpu_to_le64(word);
cd1f8160
DP		 756
757 memcpy(&req.words[0], &adapter->coal, sizeof(adapter->coal));
758
759 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
760 if (rv != 0) {
761 printk(KERN_ERR "ERROR. Could not send "
762 "interrupt coalescing parameters\n");
763 }
764
765 return rv;
766}
767
1bb482f8
NK		 768int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable)
769{
770 nx_nic_req_t req;
771 u64 word;
772 int rv = 0;
773
774 if ((adapter->flags & NETXEN_NIC_LRO_ENABLED) == enable)
775 return 0;
776
777 memset(&req, 0, sizeof(nx_nic_req_t));
778
779 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
780
781 word = NX_NIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
782 req.req_hdr = cpu_to_le64(word);
783
784 req.words[0] = cpu_to_le64(enable);
785
786 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
787 if (rv != 0) {
788 printk(KERN_ERR "ERROR. Could not send "
789 "configure hw lro request\n");
790 }
791
792 adapter->flags ^= NETXEN_NIC_LRO_ENABLED;
793
794 return rv;
795}
796
fa3ce355
NK		 797int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable)
798{
799 nx_nic_req_t req;
800 u64 word;
801 int rv = 0;
802
803 if (!!(adapter->flags & NETXEN_NIC_BRIDGE_ENABLED) == enable)
804 return rv;
805
806 memset(&req, 0, sizeof(nx_nic_req_t));
807
808 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
809
810 word = NX_NIC_H2C_OPCODE_CONFIG_BRIDGING |
811 ((u64)adapter->portnum << 16);
812 req.req_hdr = cpu_to_le64(word);
813
814 req.words[0] = cpu_to_le64(enable);
815
816 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
817 if (rv != 0) {
818 printk(KERN_ERR "ERROR. Could not send "
819 "configure bridge mode request\n");
820 }
821
822 adapter->flags ^= NETXEN_NIC_BRIDGE_ENABLED;
823
824 return rv;
825}
826
827
d8b100c5
DP		 828#define RSS_HASHTYPE_IP_TCP 0x3
829
830int netxen_config_rss(struct netxen_adapter *adapter, int enable)
831{
832 nx_nic_req_t req;
833 u64 word;
834 int i, rv;
835
836 u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
837 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
838 0x255b0ec26d5a56daULL };
839
840
841 memset(&req, 0, sizeof(nx_nic_req_t));
842 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
843
844 word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
845 req.req_hdr = cpu_to_le64(word);
846
847 /*
848 * RSS request:
849 * bits 3-0: hash_method
850 * 5-4: hash_type_ipv4
851 * 7-6: hash_type_ipv6
852 * 8: enable
853 * 9: use indirection table
854 * 47-10: reserved
855 * 63-48: indirection table mask
856 */
857 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
858 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
859 ((u64)(enable & 0x1) << 8) |
860 ((0x7ULL) << 48);
861 req.words[0] = cpu_to_le64(word);
862 for (i = 0; i < 5; i++)
863 req.words[i+1] = cpu_to_le64(key[i]);
864
865
866 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
867 if (rv != 0) {
868 printk(KERN_ERR "%s: could not configure RSS\n",
869 adapter->netdev->name);
870 }
871
872 return rv;
873}
874
6598b169
DP		 875int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd)
876{
877 nx_nic_req_t req;
878 u64 word;
879 int rv;
880
881 memset(&req, 0, sizeof(nx_nic_req_t));
882 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
883
884 word = NX_NIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
885 req.req_hdr = cpu_to_le64(word);
886
887 req.words[0] = cpu_to_le64(cmd);
888 req.words[1] = cpu_to_le64(ip);
889
890 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
891 if (rv != 0) {
892 printk(KERN_ERR "%s: could not notify %s IP 0x%x reuqest\n",
893 adapter->netdev->name,
894 (cmd == NX_IP_UP) ? "Add" : "Remove", ip);
895 }
896 return rv;
897}
898
3bf26ce3
DP		 899int netxen_linkevent_request(struct netxen_adapter *adapter, int enable)
900{
901 nx_nic_req_t req;
902 u64 word;
903 int rv;
904
905 memset(&req, 0, sizeof(nx_nic_req_t));
906 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
907
908 word = NX_NIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
909 req.req_hdr = cpu_to_le64(word);
22527864 910 req.words[0] = cpu_to_le64(enable | (enable << 8));
3bf26ce3
DP		 911
912 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
913 if (rv != 0) {
914 printk(KERN_ERR "%s: could not configure link notification\n",
915 adapter->netdev->name);
916 }
917
918 return rv;
919}
920
1bb482f8
NK		 921int netxen_send_lro_cleanup(struct netxen_adapter *adapter)
922{
923 nx_nic_req_t req;
924 u64 word;
925 int rv;
926
927 memset(&req, 0, sizeof(nx_nic_req_t));
928 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
929
930 word = NX_NIC_H2C_OPCODE_LRO_REQUEST |
931 ((u64)adapter->portnum << 16) |
932 ((u64)NX_NIC_LRO_REQUEST_CLEANUP << 56) ;
933
934 req.req_hdr = cpu_to_le64(word);
935
936 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
937 if (rv != 0) {
938 printk(KERN_ERR "%s: could not cleanup lro flows\n",
939 adapter->netdev->name);
940 }
941 return rv;
942}
943
3d396eb1
AK		 944/*
945 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
946 * @returns 0 on success, negative on failure
947 */
c9fc891f
DP		 948
949#define MTU_FUDGE_FACTOR 100
950
3d396eb1
AK		 951int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
952{
3176ff3e 953 struct netxen_adapter *adapter = netdev_priv(netdev);
c9fc891f 954 int max_mtu;
9ad27643 955 int rc = 0;
3d396eb1 956
c9fc891f
DP		 957 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
958 max_mtu = P3_MAX_MTU;
959 else
960 max_mtu = P2_MAX_MTU;
961
962 if (mtu > max_mtu) {
963 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
964 netdev->name, max_mtu);
3d396eb1
AK		 965 return -EINVAL;
966 }
967
80922fbc 968 if (adapter->set_mtu)
9ad27643 969 rc = adapter->set_mtu(adapter, mtu);
3d396eb1 970
9ad27643
DP		 971 if (!rc)
972 netdev->mtu = mtu;
c9fc891f 973
9ad27643 974 return rc;
3d396eb1
AK		 975}
976
3d396eb1 977static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
f305f789 978 int size, __le32 * buf)
3d396eb1 979{
1e2d0059 980 int i, v, addr;
f305f789 981 __le32 *ptr32;
3d396eb1
AK		 982
983 addr = base;
984 ptr32 = buf;
985 for (i = 0; i < size / sizeof(u32); i++) {
f305f789 986 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
3d396eb1 987 return -1;
f305f789 988 *ptr32 = cpu_to_le32(v);
3d396eb1
AK		 989 ptr32++;
990 addr += sizeof(u32);
991 }
992 if ((char *)buf + size > (char *)ptr32) {
f305f789
AV		 993 __le32 local;
994 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
3d396eb1 995 return -1;
f305f789 996 local = cpu_to_le32(v);
3d396eb1
AK		 997 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
998 }
999
1000 return 0;
1001}
1002
9dc28efe 1003int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
3d396eb1 1004{
9dc28efe
DP		 1005 __le32 *pmac = (__le32 *) mac;
1006 u32 offset;
3d396eb1 1007
06db58c0 1008 offset = NX_FW_MAC_ADDR_OFFSET + (adapter->portnum * sizeof(u64));
9dc28efe
DP		 1009
1010 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
3d396eb1 1011 return -1;
9dc28efe 1012
f305f789 1013 if (*mac == cpu_to_le64(~0ULL)) {
9dc28efe 1014
06db58c0
DP		 1015 offset = NX_OLD_MAC_ADDR_OFFSET +
1016 (adapter->portnum * sizeof(u64));
9dc28efe 1017
3d396eb1 1018 if (netxen_get_flash_block(adapter,
9dc28efe 1019 offset, sizeof(u64), pmac) == -1)
3d396eb1 1020 return -1;
9dc28efe 1021
f305f789 1022 if (*mac == cpu_to_le64(~0ULL))
3d396eb1
AK		 1023 return -1;
1024 }
1025 return 0;
1026}
1027
9dc28efe
DP		 1028int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
1029{
1030 uint32_t crbaddr, mac_hi, mac_lo;
1031 int pci_func = adapter->ahw.pci_func;
1032
1033 crbaddr = CRB_MAC_BLOCK_START +
1034 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
1035
f98a9f69
DP		 1036 mac_lo = NXRD32(adapter, crbaddr);
1037 mac_hi = NXRD32(adapter, crbaddr+4);
9dc28efe 1038
9dc28efe 1039 if (pci_func & 1)
2edbb454 1040 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
9dc28efe 1041 else
2edbb454 1042 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
9dc28efe
DP		 1043
1044 return 0;
1045}
1046
3d396eb1
AK		 1047/*
1048 * Changes the CRB window to the specified window.
1049 */
3ce06a32
DP		 1050void
1051netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw)
3d396eb1
AK		 1052{
1053 void __iomem *offset;
1054 u32 tmp;
1055 int count = 0;
e4c93c81 1056 uint8_t func = adapter->ahw.pci_func;
3d396eb1
AK		 1057
1058 if (adapter->curr_window == wndw)
1059 return;
3d396eb1
AK		 1060 /*
1061 * Move the CRB window.
1062 * We need to write to the "direct access" region of PCI
1063 * to avoid a race condition where the window register has
1064 * not been successfully written across CRB before the target
1065 * register address is received by PCI. The direct region bypasses
1066 * the CRB bus.
1067 */
e4c93c81
DP		 1068 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1069 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
3d396eb1
AK		 1070
1071 if (wndw & 0x1)
1072 wndw = NETXEN_WINDOW_ONE;
1073
1074 writel(wndw, offset);
1075
1076 /* MUST make sure window is set before we forge on... */
1077 while ((tmp = readl(offset)) != wndw) {
1078 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
1079 "registered properly: 0x%08x.\n",
3ce06a32 1080 netxen_nic_driver_name, __func__, tmp);
3d396eb1
AK		 1081 mdelay(1);
1082 if (count >= 10)
1083 break;
1084 count++;
1085 }
1086
6c80b18d
MT		 1087 if (wndw == NETXEN_WINDOW_ONE)
1088 adapter->curr_window = 1;
1089 else
1090 adapter->curr_window = 0;
3d396eb1
AK		 1091}
1092
3ce06a32
DP		 1093/*
1094 * Return -1 if off is not valid,
1095 * 1 if window access is needed. 'off' is set to offset from
1096 * CRB space in 128M pci map
1097 * 0 if no window access is needed. 'off' is set to 2M addr
1098 * In: 'off' is offset from base in 128M pci map
1099 */
1100static int
23b6cc42 1101netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter, ulong *off)
3ce06a32 1102{
3ce06a32
DP		 1103 crb_128M_2M_sub_block_map_t *m;
1104
1105
1106 if (*off >= NETXEN_CRB_MAX)
1107 return -1;
1108
23b6cc42 1109 if (*off >= NETXEN_PCI_CAMQM && (*off < NETXEN_PCI_CAMQM_2M_END)) {
3ce06a32
DP		 1110 *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE +
1111 (ulong)adapter->ahw.pci_base0;
1112 return 0;
1113 }
1114
1115 if (*off < NETXEN_PCI_CRBSPACE)
1116 return -1;
1117
1118 *off -= NETXEN_PCI_CRBSPACE;
3ce06a32
DP		 1119
1120 /*
1121 * Try direct map
1122 */
1123 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
1124
23b6cc42 1125 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
3ce06a32
DP		 1126 *off = *off + m->start_2M - m->start_128M +
1127 (ulong)adapter->ahw.pci_base0;
1128 return 0;
1129 }
1130
1131 /*
1132 * Not in direct map, use crb window
1133 */
1134 return 1;
1135}
1136
1137/*
1138 * In: 'off' is offset from CRB space in 128M pci map
1139 * Out: 'off' is 2M pci map addr
1140 * side effect: lock crb window
1141 */
1142static void
1143netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off)
1144{
1145 u32 win_read;
1146
1147 adapter->crb_win = CRB_HI(*off);
d8313ce0 1148 writel(adapter->crb_win, (adapter->ahw.pci_base0 + CRB_WINDOW_2M));
3ce06a32
DP		 1149 /*
1150 * Read back value to make sure write has gone through before trying
1151 * to use it.
1152 */
d8313ce0 1153 win_read = readl(adapter->ahw.pci_base0 + CRB_WINDOW_2M);
3ce06a32
DP		 1154 if (win_read != adapter->crb_win) {
1155 printk(KERN_ERR "%s: Written crbwin (0x%x) != "
1156 "Read crbwin (0x%x), off=0x%lx\n",
1157 __func__, adapter->crb_win, win_read, *off);
1158 }
1159 *off = (*off & MASK(16)) + CRB_INDIRECT_2M +
1160 (ulong)adapter->ahw.pci_base0;
1161}
1162
3d396eb1 1163int
1fbe6323 1164netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, ulong off, u32 data)
3d396eb1
AK		 1165{
1166 void __iomem *addr;
1167
1168 if (ADDR_IN_WINDOW1(off)) {
1169 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1170 } else { /* Window 0 */
cb8011ad 1171 addr = pci_base_offset(adapter, off);
3ce06a32 1172 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
3d396eb1
AK		 1173 }
1174
cb8011ad 1175 if (!addr) {
3ce06a32 1176 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
cb8011ad
AK		 1177 return 1;
1178 }
1179
1fbe6323 1180 writel(data, addr);
3d396eb1 1181
3d396eb1 1182 if (!ADDR_IN_WINDOW1(off))
3ce06a32 1183 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
3d396eb1
AK		 1184
1185 return 0;
1186}
1187
1fbe6323
DP		 1188u32
1189netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off)
3d396eb1
AK		 1190{
1191 void __iomem *addr;
1fbe6323 1192 u32 data;
d8313ce0 1193
3d396eb1
AK		 1194 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1195 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1196 } else { /* Window 0 */
cb8011ad 1197 addr = pci_base_offset(adapter, off);
3ce06a32 1198 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
3d396eb1
AK		 1199 }
1200
cb8011ad 1201 if (!addr) {
3ce06a32 1202 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
cb8011ad
AK		 1203 return 1;
1204 }
d8313ce0 1205
1fbe6323 1206 data = readl(addr);
3d396eb1
AK		 1207
1208 if (!ADDR_IN_WINDOW1(off))
3ce06a32 1209 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
3d396eb1 1210
1fbe6323 1211 return data;
3d396eb1
AK		 1212}
1213
3ce06a32 1214int
1fbe6323 1215netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, ulong off, u32 data)
3ce06a32
DP		 1216{
1217 unsigned long flags = 0;
1218 int rv;
3d396eb1 1219
23b6cc42 1220 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off);
3d396eb1 1221
3ce06a32
DP		 1222 if (rv == -1) {
1223 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1224 __func__, off);
1225 dump_stack();
1226 return -1;
1227 }
1228
1229 if (rv == 1) {
1230 write_lock_irqsave(&adapter->adapter_lock, flags);
1231 crb_win_lock(adapter);
1232 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1fbe6323 1233 writel(data, (void __iomem *)off);
3ce06a32
DP		 1234 crb_win_unlock(adapter);
1235 write_unlock_irqrestore(&adapter->adapter_lock, flags);
d8313ce0 1236 } else
1fbe6323 1237 writel(data, (void __iomem *)off);
d8313ce0 1238
3ce06a32
DP		 1239
1240 return 0;
3d396eb1
AK		 1241}
1242
1fbe6323
DP		 1243u32
1244netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off)
3ce06a32
DP		 1245{
1246 unsigned long flags = 0;
1247 int rv;
1fbe6323 1248 u32 data;
3d396eb1 1249
23b6cc42 1250 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off);
3ce06a32
DP		 1251
1252 if (rv == -1) {
1253 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1254 __func__, off);
1255 dump_stack();
1256 return -1;
1257 }
1258
1259 if (rv == 1) {
1260 write_lock_irqsave(&adapter->adapter_lock, flags);
1261 crb_win_lock(adapter);
1262 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1fbe6323 1263 data = readl((void __iomem *)off);
3ce06a32
DP		 1264 crb_win_unlock(adapter);
1265 write_unlock_irqrestore(&adapter->adapter_lock, flags);
d8313ce0 1266 } else
1fbe6323 1267 data = readl((void __iomem *)off);
3ce06a32 1268
1fbe6323 1269 return data;
3ce06a32
DP		 1270}
1271
3ce06a32
DP		 1272/*
1273 * check memory access boundary.
1274 * used by test agent. support ddr access only for now
1275 */
1276static unsigned long
1277netxen_nic_pci_mem_bound_check(struct netxen_adapter *adapter,
1278 unsigned long long addr, int size)
1279{
1280 if (!ADDR_IN_RANGE(addr,
1281 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1282 !ADDR_IN_RANGE(addr+size-1,
1283 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1284 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
1285 return 0;
1286 }
3d396eb1 1287
3ce06a32 1288 return 1;
3d396eb1
AK		 1289}
1290
4790654c 1291static int netxen_pci_set_window_warning_count;
3d396eb1 1292
3ce06a32
DP		 1293unsigned long
1294netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1295 unsigned long long addr)
3d396eb1 1296{
e4c93c81 1297 void __iomem *offset;
3d396eb1 1298 int window;
3ce06a32 1299 unsigned long long qdr_max;
e4c93c81 1300 uint8_t func = adapter->ahw.pci_func;
3d396eb1 1301
3ce06a32
DP		 1302 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1303 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1304 } else {
1305 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1306 }
1307
3d396eb1
AK		 1308 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1309 /* DDR network side */
1310 addr -= NETXEN_ADDR_DDR_NET;
1311 window = (addr >> 25) & 0x3ff;
3ce06a32
DP		 1312 if (adapter->ahw.ddr_mn_window != window) {
1313 adapter->ahw.ddr_mn_window = window;
e4c93c81
DP		 1314 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1315 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func)));
1316 writel(window, offset);
3d396eb1 1317 /* MUST make sure window is set before we forge on... */
e4c93c81 1318 readl(offset);
3d396eb1 1319 }
cb8011ad 1320 addr -= (window * NETXEN_WINDOW_ONE);
3d396eb1
AK		 1321 addr += NETXEN_PCI_DDR_NET;
1322 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1323 addr -= NETXEN_ADDR_OCM0;
1324 addr += NETXEN_PCI_OCM0;
1325 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1326 addr -= NETXEN_ADDR_OCM1;
1327 addr += NETXEN_PCI_OCM1;
3ce06a32 1328 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
3d396eb1
AK		 1329 /* QDR network side */
1330 addr -= NETXEN_ADDR_QDR_NET;
1331 window = (addr >> 22) & 0x3f;
3ce06a32
DP		 1332 if (adapter->ahw.qdr_sn_window != window) {
1333 adapter->ahw.qdr_sn_window = window;
e4c93c81
DP		 1334 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1335 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func)));
1336 writel((window << 22), offset);
3d396eb1 1337 /* MUST make sure window is set before we forge on... */
e4c93c81 1338 readl(offset);
3d396eb1
AK		 1339 }
1340 addr -= (window * 0x400000);
1341 addr += NETXEN_PCI_QDR_NET;
1342 } else {
1343 /*
1344 * peg gdb frequently accesses memory that doesn't exist,
1345 * this limits the chit chat so debugging isn't slowed down.
1346 */
1347 if ((netxen_pci_set_window_warning_count++ < 8)
1348 || (netxen_pci_set_window_warning_count % 64 == 0))
1349 printk("%s: Warning:netxen_nic_pci_set_window()"
1350 " Unknown address range!\n",
1351 netxen_nic_driver_name);
3ce06a32
DP		 1352 addr = -1UL;
1353 }
1354 return addr;
1355}
1356
1357/*
1358 * Note : only 32-bit writes!
1359 */
1360int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1361 u64 off, u32 data)
1362{
1363 writel(data, (void __iomem *)(PCI_OFFSET_SECOND_RANGE(adapter, off)));
1364 return 0;
1365}
1366
1367u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off)
1368{
1369 return readl((void __iomem *)(pci_base_offset(adapter, off)));
1370}
1371
3ce06a32
DP		 1372unsigned long
1373netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1374 unsigned long long addr)
1375{
1376 int window;
1377 u32 win_read;
3d396eb1 1378
3ce06a32
DP		 1379 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1380 /* DDR network side */
1381 window = MN_WIN(addr);
1382 adapter->ahw.ddr_mn_window = window;
f98a9f69 1383 NXWR32(adapter, adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1fbe6323 1384 window);
f98a9f69 1385 win_read = NXRD32(adapter,
1fbe6323 1386 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE);
3ce06a32
DP		 1387 if ((win_read << 17) != window) {
1388 printk(KERN_INFO "Written MNwin (0x%x) != "
1389 "Read MNwin (0x%x)\n", window, win_read);
1390 }
1391 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_DDR_NET;
1392 } else if (ADDR_IN_RANGE(addr,
1393 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1394 if ((addr & 0x00ff800) == 0xff800) {
1395 printk("%s: QM access not handled.\n", __func__);
1396 addr = -1UL;
1397 }
1398
1399 window = OCM_WIN(addr);
1400 adapter->ahw.ddr_mn_window = window;
f98a9f69 1401 NXWR32(adapter, adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1fbe6323 1402 window);
f98a9f69 1403 win_read = NXRD32(adapter,
1fbe6323 1404 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE);
3ce06a32
DP		 1405 if ((win_read >> 7) != window) {
1406 printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
1407 "Read OCMwin (0x%x)\n",
1408 __func__, window, win_read);
1409 }
1410 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_OCM0_2M;
1411
1412 } else if (ADDR_IN_RANGE(addr,
1413 NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P3)) {
1414 /* QDR network side */
1415 window = MS_WIN(addr);
1416 adapter->ahw.qdr_sn_window = window;
f98a9f69 1417 NXWR32(adapter, adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1fbe6323 1418 window);
f98a9f69 1419 win_read = NXRD32(adapter,
1fbe6323 1420 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE);
3ce06a32
DP		 1421 if (win_read != window) {
1422 printk(KERN_INFO "%s: Written MSwin (0x%x) != "
1423 "Read MSwin (0x%x)\n",
1424 __func__, window, win_read);
1425 }
1426 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_QDR_NET;
1427
1428 } else {
1429 /*
1430 * peg gdb frequently accesses memory that doesn't exist,
1431 * this limits the chit chat so debugging isn't slowed down.
1432 */
1433 if ((netxen_pci_set_window_warning_count++ < 8)
1434 || (netxen_pci_set_window_warning_count%64 == 0)) {
1435 printk("%s: Warning:%s Unknown address range!\n",
1436 __func__, netxen_nic_driver_name);
1437}
1438 addr = -1UL;
3d396eb1
AK		 1439 }
1440 return addr;
1441}
1442
3ce06a32
DP		 1443static int netxen_nic_pci_is_same_window(struct netxen_adapter *adapter,
1444 unsigned long long addr)
1445{
1446 int window;
1447 unsigned long long qdr_max;
1448
1449 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1450 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1451 else
1452 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1453
1454 if (ADDR_IN_RANGE(addr,
1455 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1456 /* DDR network side */
1457 BUG(); /* MN access can not come here */
1458 } else if (ADDR_IN_RANGE(addr,
1459 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1460 return 1;
1461 } else if (ADDR_IN_RANGE(addr,
1462 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1463 return 1;
1464 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1465 /* QDR network side */
1466 window = ((addr - NETXEN_ADDR_QDR_NET) >> 22) & 0x3f;
1467 if (adapter->ahw.qdr_sn_window == window)
1468 return 1;
1469 }
1470
1471 return 0;
1472}
1473
1474static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter,
1475 u64 off, void *data, int size)
1476{
1477 unsigned long flags;
d8313ce0 1478 void __iomem *addr, *mem_ptr = NULL;
3ce06a32
DP		 1479 int ret = 0;
1480 u64 start;
3ce06a32
DP		 1481 unsigned long mem_base;
1482 unsigned long mem_page;
1483
1484 write_lock_irqsave(&adapter->adapter_lock, flags);
1485
1486 /*
1487 * If attempting to access unknown address or straddle hw windows,
1488 * do not access.
1489 */
1490 start = adapter->pci_set_window(adapter, off);
1491 if ((start == -1UL) ||
1492 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1493 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1494 printk(KERN_ERR "%s out of bound pci memory access. "
11a859e5
AM		 1495 "offset is 0x%llx\n", netxen_nic_driver_name,
1496 (unsigned long long)off);
3ce06a32
DP		 1497 return -1;
1498 }
1499
d8313ce0 1500 addr = pci_base_offset(adapter, start);
3ce06a32
DP		 1501 if (!addr) {
1502 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1503 mem_base = pci_resource_start(adapter->pdev, 0);
1504 mem_page = start & PAGE_MASK;
1505 /* Map two pages whenever user tries to access addresses in two
1506 consecutive pages.
1507 */
1508 if (mem_page != ((start + size - 1) & PAGE_MASK))
1509 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
1510 else
1511 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
f8057b7f 1512 if (mem_ptr == NULL) {
3ce06a32
DP		 1513 *(uint8_t *)data = 0;
1514 return -1;
1515 }
1516 addr = mem_ptr;
1517 addr += start & (PAGE_SIZE - 1);
1518 write_lock_irqsave(&adapter->adapter_lock, flags);
1519 }
1520
1521 switch (size) {
1522 case 1:
1523 *(uint8_t *)data = readb(addr);
1524 break;
1525 case 2:
1526 *(uint16_t *)data = readw(addr);
1527 break;
1528 case 4:
1529 *(uint32_t *)data = readl(addr);
1530 break;
1531 case 8:
1532 *(uint64_t *)data = readq(addr);
1533 break;
1534 default:
1535 ret = -1;
1536 break;
1537 }
1538 write_unlock_irqrestore(&adapter->adapter_lock, flags);
3ce06a32
DP		 1539
1540 if (mem_ptr)
1541 iounmap(mem_ptr);
1542 return ret;
1543}
1544
1545static int
1546netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off,
1547 void *data, int size)
1548{
1549 unsigned long flags;
d8313ce0 1550 void __iomem *addr, *mem_ptr = NULL;
3ce06a32
DP		 1551 int ret = 0;
1552 u64 start;
3ce06a32
DP		 1553 unsigned long mem_base;
1554 unsigned long mem_page;
1555
1556 write_lock_irqsave(&adapter->adapter_lock, flags);
1557
1558 /*
1559 * If attempting to access unknown address or straddle hw windows,
1560 * do not access.
1561 */
1562 start = adapter->pci_set_window(adapter, off);
1563 if ((start == -1UL) ||
1564 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1565 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1566 printk(KERN_ERR "%s out of bound pci memory access. "
11a859e5
AM		 1567 "offset is 0x%llx\n", netxen_nic_driver_name,
1568 (unsigned long long)off);
3ce06a32
DP		 1569 return -1;
1570 }
1571
d8313ce0 1572 addr = pci_base_offset(adapter, start);
3ce06a32
DP		 1573 if (!addr) {
1574 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1575 mem_base = pci_resource_start(adapter->pdev, 0);
1576 mem_page = start & PAGE_MASK;
1577 /* Map two pages whenever user tries to access addresses in two
1578 * consecutive pages.
1579 */
1580 if (mem_page != ((start + size - 1) & PAGE_MASK))
1581 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
1582 else
1583 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
f8057b7f 1584 if (mem_ptr == NULL)
3ce06a32
DP		 1585 return -1;
1586 addr = mem_ptr;
1587 addr += start & (PAGE_SIZE - 1);
1588 write_lock_irqsave(&adapter->adapter_lock, flags);
1589 }
1590
1591 switch (size) {
1592 case 1:
1593 writeb(*(uint8_t *)data, addr);
1594 break;
1595 case 2:
1596 writew(*(uint16_t *)data, addr);
1597 break;
1598 case 4:
1599 writel(*(uint32_t *)data, addr);
1600 break;
1601 case 8:
1602 writeq(*(uint64_t *)data, addr);
1603 break;
1604 default:
1605 ret = -1;
1606 break;
1607 }
1608 write_unlock_irqrestore(&adapter->adapter_lock, flags);
3ce06a32
DP		 1609 if (mem_ptr)
1610 iounmap(mem_ptr);
1611 return ret;
1612}
1613
1614#define MAX_CTL_CHECK 1000
1615
1616int
1617netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1618 u64 off, void *data, int size)
1619{
d8313ce0 1620 unsigned long flags;
3ce06a32
DP		 1621 int i, j, ret = 0, loop, sz[2], off0;
1622 uint32_t temp;
1623 uint64_t off8, tmpw, word[2] = {0, 0};
d8313ce0 1624 void __iomem *mem_crb;
3ce06a32
DP		 1625
1626 /*
1627 * If not MN, go check for MS or invalid.
1628 */
1629 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1630 return netxen_nic_pci_mem_write_direct(adapter,
1631 off, data, size);
1632
1633 off8 = off & 0xfffffff8;
1634 off0 = off & 0x7;
1635 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1636 sz[1] = size - sz[0];
1637 loop = ((off0 + size - 1) >> 3) + 1;
d8313ce0 1638 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
3ce06a32
DP		 1639
1640 if ((size != 8) || (off0 != 0)) {
1641 for (i = 0; i < loop; i++) {
1642 if (adapter->pci_mem_read(adapter,
1643 off8 + (i << 3), &word[i], 8))
1644 return -1;
1645 }
1646 }
1647
1648 switch (size) {
1649 case 1:
1650 tmpw = *((uint8_t *)data);
1651 break;
1652 case 2:
1653 tmpw = *((uint16_t *)data);
1654 break;
1655 case 4:
1656 tmpw = *((uint32_t *)data);
1657 break;
1658 case 8:
1659 default:
1660 tmpw = *((uint64_t *)data);
1661 break;
1662 }
1663 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1664 word[0] |= tmpw << (off0 * 8);
1665
1666 if (loop == 2) {
1667 word[1] &= ~(~0ULL << (sz[1] * 8));
1668 word[1] |= tmpw >> (sz[0] * 8);
1669 }
1670
1671 write_lock_irqsave(&adapter->adapter_lock, flags);
1672 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1673
1674 for (i = 0; i < loop; i++) {
1675 writel((uint32_t)(off8 + (i << 3)),
d8313ce0 1676 (mem_crb+MIU_TEST_AGT_ADDR_LO));
3ce06a32 1677 writel(0,
d8313ce0 1678 (mem_crb+MIU_TEST_AGT_ADDR_HI));
3ce06a32 1679 writel(word[i] & 0xffffffff,
d8313ce0 1680 (mem_crb+MIU_TEST_AGT_WRDATA_LO));
3ce06a32 1681 writel((word[i] >> 32) & 0xffffffff,
d8313ce0 1682 (mem_crb+MIU_TEST_AGT_WRDATA_HI));
3ce06a32 1683 writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
d8313ce0 1684 (mem_crb+MIU_TEST_AGT_CTRL));
3ce06a32 1685 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
d8313ce0 1686 (mem_crb+MIU_TEST_AGT_CTRL));
3ce06a32
DP		 1687
1688 for (j = 0; j < MAX_CTL_CHECK; j++) {
1689 temp = readl(
d8313ce0 1690 (mem_crb+MIU_TEST_AGT_CTRL));
3ce06a32
DP		 1691 if ((temp & MIU_TA_CTL_BUSY) == 0)
1692 break;
1693 }
1694
1695 if (j >= MAX_CTL_CHECK) {
39754f44
DP		 1696 if (printk_ratelimit())
1697 dev_err(&adapter->pdev->dev,
1698 "failed to write through agent\n");
3ce06a32
DP		 1699 ret = -1;
1700 break;
1701 }
1702 }
1703
1704 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1705 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1706 return ret;
1707}
1708
1709int
1710netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1711 u64 off, void *data, int size)
1712{
d8313ce0 1713 unsigned long flags;
3ce06a32
DP		 1714 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1715 uint32_t temp;
1716 uint64_t off8, val, word[2] = {0, 0};
d8313ce0 1717 void __iomem *mem_crb;
3ce06a32
DP		 1718
1719
1720 /*
1721 * If not MN, go check for MS or invalid.
1722 */
1723 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1724 return netxen_nic_pci_mem_read_direct(adapter, off, data, size);
1725
1726 off8 = off & 0xfffffff8;
1727 off0[0] = off & 0x7;
1728 off0[1] = 0;
1729 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1730 sz[1] = size - sz[0];
1731 loop = ((off0[0] + size - 1) >> 3) + 1;
d8313ce0 1732 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
3ce06a32
DP		 1733
1734 write_lock_irqsave(&adapter->adapter_lock, flags);
1735 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1736
1737 for (i = 0; i < loop; i++) {
1738 writel((uint32_t)(off8 + (i << 3)),
d8313ce0 1739 (mem_crb+MIU_TEST_AGT_ADDR_LO));
3ce06a32 1740 writel(0,
d8313ce0 1741 (mem_crb+MIU_TEST_AGT_ADDR_HI));
3ce06a32 1742 writel(MIU_TA_CTL_ENABLE,
d8313ce0 1743 (mem_crb+MIU_TEST_AGT_CTRL));
3ce06a32 1744 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE,
d8313ce0 1745 (mem_crb+MIU_TEST_AGT_CTRL));
3ce06a32
DP		 1746
1747 for (j = 0; j < MAX_CTL_CHECK; j++) {
1748 temp = readl(
d8313ce0 1749 (mem_crb+MIU_TEST_AGT_CTRL));
3ce06a32
DP		 1750 if ((temp & MIU_TA_CTL_BUSY) == 0)
1751 break;
1752 }
1753
1754 if (j >= MAX_CTL_CHECK) {
39754f44
DP		 1755 if (printk_ratelimit())
1756 dev_err(&adapter->pdev->dev,
1757 "failed to read through agent\n");
3ce06a32
DP		 1758 break;
1759 }
1760
1761 start = off0[i] >> 2;
1762 end = (off0[i] + sz[i] - 1) >> 2;
1763 for (k = start; k <= end; k++) {
1764 word[i] |= ((uint64_t) readl(
d8313ce0 1765 (mem_crb +
3ce06a32
DP		 1766 MIU_TEST_AGT_RDDATA(k))) << (32*k));
1767 }
1768 }
1769
1770 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1771 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1772
1773 if (j >= MAX_CTL_CHECK)
1774 return -1;
1775
1776 if (sz[0] == 8) {
1777 val = word[0];
1778 } else {
1779 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1780 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1781 }
1782
1783 switch (size) {
1784 case 1:
1785 *(uint8_t *)data = val;
1786 break;
1787 case 2:
1788 *(uint16_t *)data = val;
1789 break;
1790 case 4:
1791 *(uint32_t *)data = val;
1792 break;
1793 case 8:
1794 *(uint64_t *)data = val;
1795 break;
1796 }
3ce06a32
DP		 1797 return 0;
1798}
1799
1800int
1801netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1802 u64 off, void *data, int size)
1803{
1804 int i, j, ret = 0, loop, sz[2], off0;
1805 uint32_t temp;
1806 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1807
1808 /*
1809 * If not MN, go check for MS or invalid.
1810 */
1811 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1812 mem_crb = NETXEN_CRB_QDR_NET;
1813 else {
1814 mem_crb = NETXEN_CRB_DDR_NET;
1815 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1816 return netxen_nic_pci_mem_write_direct(adapter,
1817 off, data, size);
1818 }
1819
1820 off8 = off & 0xfffffff8;
1821 off0 = off & 0x7;
1822 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1823 sz[1] = size - sz[0];
1824 loop = ((off0 + size - 1) >> 3) + 1;
1825
1826 if ((size != 8) || (off0 != 0)) {
1827 for (i = 0; i < loop; i++) {
1828 if (adapter->pci_mem_read(adapter, off8 + (i << 3),
1829 &word[i], 8))
1830 return -1;
1831 }
1832 }
1833
1834 switch (size) {
1835 case 1:
1836 tmpw = *((uint8_t *)data);
1837 break;
1838 case 2:
1839 tmpw = *((uint16_t *)data);
1840 break;
1841 case 4:
1842 tmpw = *((uint32_t *)data);
1843 break;
1844 case 8:
1845 default:
1846 tmpw = *((uint64_t *)data);
1847 break;
1848 }
1849
1850 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1851 word[0] |= tmpw << (off0 * 8);
1852
1853 if (loop == 2) {
1854 word[1] &= ~(~0ULL << (sz[1] * 8));
1855 word[1] |= tmpw >> (sz[0] * 8);
1856 }
1857
1858 /*
1859 * don't lock here - write_wx gets the lock if each time
1860 * write_lock_irqsave(&adapter->adapter_lock, flags);
1861 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1862 */
1863
1864 for (i = 0; i < loop; i++) {
1865 temp = off8 + (i << 3);
f98a9f69 1866 NXWR32(adapter, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
3ce06a32 1867 temp = 0;
f98a9f69 1868 NXWR32(adapter, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
3ce06a32 1869 temp = word[i] & 0xffffffff;
f98a9f69 1870 NXWR32(adapter, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
3ce06a32 1871 temp = (word[i] >> 32) & 0xffffffff;
f98a9f69 1872 NXWR32(adapter, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
3ce06a32 1873 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
f98a9f69 1874 NXWR32(adapter, mem_crb+MIU_TEST_AGT_CTRL, temp);
3ce06a32 1875 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
f98a9f69 1876 NXWR32(adapter, mem_crb+MIU_TEST_AGT_CTRL, temp);
3ce06a32
DP		 1877
1878 for (j = 0; j < MAX_CTL_CHECK; j++) {
f98a9f69 1879 temp = NXRD32(adapter, mem_crb + MIU_TEST_AGT_CTRL);
3ce06a32
DP		 1880 if ((temp & MIU_TA_CTL_BUSY) == 0)
1881 break;
1882 }
1883
1884 if (j >= MAX_CTL_CHECK) {
39754f44
DP		 1885 if (printk_ratelimit())
1886 dev_err(&adapter->pdev->dev,
1887 "failed to write through agent\n");
3ce06a32
DP		 1888 ret = -1;
1889 break;
1890 }
1891 }
1892
1893 /*
1894 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1895 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1896 */
1897 return ret;
1898}
1899
1900int
1901netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1902 u64 off, void *data, int size)
1903{
1904 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1905 uint32_t temp;
1906 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1907
1908 /*
1909 * If not MN, go check for MS or invalid.
1910 */
1911
1912 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1913 mem_crb = NETXEN_CRB_QDR_NET;
1914 else {
1915 mem_crb = NETXEN_CRB_DDR_NET;
1916 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1917 return netxen_nic_pci_mem_read_direct(adapter,
1918 off, data, size);
1919 }
1920
1921 off8 = off & 0xfffffff8;
1922 off0[0] = off & 0x7;
1923 off0[1] = 0;
1924 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1925 sz[1] = size - sz[0];
1926 loop = ((off0[0] + size - 1) >> 3) + 1;
1927
1928 /*
1929 * don't lock here - write_wx gets the lock if each time
1930 * write_lock_irqsave(&adapter->adapter_lock, flags);
1931 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1932 */
1933
1934 for (i = 0; i < loop; i++) {
1935 temp = off8 + (i << 3);
f98a9f69 1936 NXWR32(adapter, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
3ce06a32 1937 temp = 0;
f98a9f69 1938 NXWR32(adapter, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
3ce06a32 1939 temp = MIU_TA_CTL_ENABLE;
f98a9f69 1940 NXWR32(adapter, mem_crb + MIU_TEST_AGT_CTRL, temp);
3ce06a32 1941 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
f98a9f69 1942 NXWR32(adapter, mem_crb + MIU_TEST_AGT_CTRL, temp);
3ce06a32
DP		 1943
1944 for (j = 0; j < MAX_CTL_CHECK; j++) {
f98a9f69 1945 temp = NXRD32(adapter, mem_crb + MIU_TEST_AGT_CTRL);
3ce06a32
DP		 1946 if ((temp & MIU_TA_CTL_BUSY) == 0)
1947 break;
1948 }
1949
1950 if (j >= MAX_CTL_CHECK) {
39754f44
DP		 1951 if (printk_ratelimit())
1952 dev_err(&adapter->pdev->dev,
1953 "failed to read through agent\n");
3ce06a32
DP		 1954 break;
1955 }
1956
1957 start = off0[i] >> 2;
1958 end = (off0[i] + sz[i] - 1) >> 2;
1959 for (k = start; k <= end; k++) {
f98a9f69 1960 temp = NXRD32(adapter,
1fbe6323 1961 mem_crb + MIU_TEST_AGT_RDDATA(k));
3ce06a32
DP		 1962 word[i] |= ((uint64_t)temp << (32 * k));
1963 }
1964 }
1965
1966 /*
1967 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1968 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1969 */
1970
1971 if (j >= MAX_CTL_CHECK)
1972 return -1;
1973
1974 if (sz[0] == 8) {
1975 val = word[0];
1976 } else {
1977 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1978 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1979 }
1980
1981 switch (size) {
1982 case 1:
1983 *(uint8_t *)data = val;
1984 break;
1985 case 2:
1986 *(uint16_t *)data = val;
1987 break;
1988 case 4:
1989 *(uint32_t *)data = val;
1990 break;
1991 case 8:
1992 *(uint64_t *)data = val;
1993 break;
1994 }
3ce06a32
DP		 1995 return 0;
1996}
1997
1998/*
1999 * Note : only 32-bit writes!
2000 */
2001int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
2002 u64 off, u32 data)
2003{
f98a9f69 2004 NXWR32(adapter, off, data);
3ce06a32
DP		 2005
2006 return 0;
2007}
2008
2009u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off)
2010{
f98a9f69 2011 return NXRD32(adapter, off);
3ce06a32
DP		 2012}
2013
3d396eb1
AK		 2014int netxen_nic_get_board_info(struct netxen_adapter *adapter)
2015{
1e2d0059
DP		 2016 int offset, board_type, magic, header_version;
2017 struct pci_dev *pdev = adapter->pdev;
3d396eb1 2018
06db58c0 2019 offset = NX_FW_MAGIC_OFFSET;
1e2d0059
DP		 2020 if (netxen_rom_fast_read(adapter, offset, &magic))
2021 return -EIO;
3d396eb1 2022
06db58c0 2023 offset = NX_HDR_VERSION_OFFSET;
1e2d0059
DP		 2024 if (netxen_rom_fast_read(adapter, offset, &header_version))
2025 return -EIO;
2026
2027 if (magic != NETXEN_BDINFO_MAGIC ||
2028 header_version != NETXEN_BDINFO_VERSION) {
2029 dev_err(&pdev->dev,
2030 "invalid board config, magic=%08x, version=%08x\n",
2031 magic, header_version);
2032 return -EIO;
3d396eb1
AK		 2033 }
2034
06db58c0 2035 offset = NX_BRDTYPE_OFFSET;
1e2d0059
DP		 2036 if (netxen_rom_fast_read(adapter, offset, &board_type))
2037 return -EIO;
2038
2039 adapter->ahw.board_type = board_type;
2040
2041 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
f98a9f69 2042 u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I);
c7860a2a 2043 if ((gpio & 0x8000) == 0)
1e2d0059 2044 board_type = NETXEN_BRDTYPE_P3_10G_TP;
c7860a2a
DP		 2045 }
2046
e98e3350 2047 switch (board_type) {
3d396eb1 2048 case NETXEN_BRDTYPE_P2_SB35_4G:
1e2d0059 2049 adapter->ahw.port_type = NETXEN_NIC_GBE;
3d396eb1
AK		 2050 break;
2051 case NETXEN_BRDTYPE_P2_SB31_10G:
2052 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
2053 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
2054 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
e4c93c81
DP		 2055 case NETXEN_BRDTYPE_P3_HMEZ:
2056 case NETXEN_BRDTYPE_P3_XG_LOM:
2057 case NETXEN_BRDTYPE_P3_10G_CX4:
2058 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
2059 case NETXEN_BRDTYPE_P3_IMEZ:
2060 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
a70f9393
DP		 2061 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
2062 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
e4c93c81
DP		 2063 case NETXEN_BRDTYPE_P3_10G_XFP:
2064 case NETXEN_BRDTYPE_P3_10000_BASE_T:
1e2d0059 2065 adapter->ahw.port_type = NETXEN_NIC_XGBE;
3d396eb1
AK		 2066 break;
2067 case NETXEN_BRDTYPE_P1_BD:
2068 case NETXEN_BRDTYPE_P1_SB:
2069 case NETXEN_BRDTYPE_P1_SMAX:
2070 case NETXEN_BRDTYPE_P1_SOCK:
e4c93c81
DP		 2071 case NETXEN_BRDTYPE_P3_REF_QG:
2072 case NETXEN_BRDTYPE_P3_4_GB:
2073 case NETXEN_BRDTYPE_P3_4_GB_MM:
1e2d0059 2074 adapter->ahw.port_type = NETXEN_NIC_GBE;
3d396eb1 2075 break;
c7860a2a 2076 case NETXEN_BRDTYPE_P3_10G_TP:
1e2d0059 2077 adapter->ahw.port_type = (adapter->portnum < 2) ?
c7860a2a
DP		 2078 NETXEN_NIC_XGBE : NETXEN_NIC_GBE;
2079 break;
3d396eb1 2080 default:
1e2d0059
DP		 2081 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
2082 adapter->ahw.port_type = NETXEN_NIC_XGBE;
3d396eb1
AK		 2083 break;
2084 }
2085
1e2d0059 2086 return 0;
3d396eb1
AK		 2087}
2088
2089/* NIU access sections */
2090
3176ff3e 2091int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
3d396eb1 2092{
9ad27643 2093 new_mtu += MTU_FUDGE_FACTOR;
f98a9f69 2094 NXWR32(adapter, NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
3276fbad 2095 new_mtu);
3d396eb1
AK		 2096 return 0;
2097}
2098
3176ff3e 2099int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
3d396eb1 2100{
9ad27643 2101 new_mtu += MTU_FUDGE_FACTOR;
3276fbad 2102 if (adapter->physical_port == 0)
f98a9f69 2103 NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
4790654c 2104 else
f98a9f69 2105 NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu);
3d396eb1
AK		 2106 return 0;
2107}
2108
3176ff3e 2109void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
3d396eb1 2110{
a608ab9c
AV		 2111 __u32 status;
2112 __u32 autoneg;
24a7a455 2113 __u32 port_mode;
3d396eb1 2114
c7860a2a
DP		 2115 if (!netif_carrier_ok(adapter->netdev)) {
2116 adapter->link_speed = 0;
2117 adapter->link_duplex = -1;
2118 adapter->link_autoneg = AUTONEG_ENABLE;
2119 return;
2120 }
24a7a455 2121
1e2d0059 2122 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
f98a9f69 2123 port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR);
24a7a455
DP		 2124 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
2125 adapter->link_speed = SPEED_1000;
2126 adapter->link_duplex = DUPLEX_FULL;
2127 adapter->link_autoneg = AUTONEG_DISABLE;
2128 return;
2129 }
2130
80922fbc 2131 if (adapter->phy_read
24a7a455 2132 && adapter->phy_read(adapter,
3d396eb1
AK		 2133 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
2134 &status) == 0) {
2135 if (netxen_get_phy_link(status)) {
2136 switch (netxen_get_phy_speed(status)) {
2137 case 0:
3176ff3e 2138 adapter->link_speed = SPEED_10;
3d396eb1
AK		 2139 break;
2140 case 1:
3176ff3e 2141 adapter->link_speed = SPEED_100;
3d396eb1
AK		 2142 break;
2143 case 2:
3176ff3e 2144 adapter->link_speed = SPEED_1000;
3d396eb1
AK		 2145 break;
2146 default:
c7860a2a 2147 adapter->link_speed = 0;
3d396eb1
AK		 2148 break;
2149 }
2150 switch (netxen_get_phy_duplex(status)) {
2151 case 0:
3176ff3e 2152 adapter->link_duplex = DUPLEX_HALF;
3d396eb1
AK		 2153 break;
2154 case 1:
3176ff3e 2155 adapter->link_duplex = DUPLEX_FULL;
3d396eb1
AK		 2156 break;
2157 default:
3176ff3e 2158 adapter->link_duplex = -1;
3d396eb1
AK		 2159 break;
2160 }
80922fbc 2161 if (adapter->phy_read
24a7a455 2162 && adapter->phy_read(adapter,
3d396eb1 2163 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
ed25ffa1 2164 &autoneg) != 0)
3176ff3e 2165 adapter->link_autoneg = autoneg;
3d396eb1
AK		 2166 } else
2167 goto link_down;
2168 } else {
2169 link_down:
c7860a2a 2170 adapter->link_speed = 0;
3176ff3e 2171 adapter->link_duplex = -1;
3d396eb1
AK		 2172 }
2173 }
2174}
2175
1e2d0059 2176void netxen_nic_get_firmware_info(struct netxen_adapter *adapter)
3d396eb1 2177{
1e2d0059 2178 u32 fw_major, fw_minor, fw_build;
cb8011ad 2179 char brd_name[NETXEN_MAX_SHORT_NAME];
8d74849b 2180 char serial_num[32];
06db58c0 2181 int i, offset, val;
d8313ce0 2182 int *ptr32;
1e2d0059 2183 struct pci_dev *pdev = adapter->pdev;
dcd56fdb
DP		 2184
2185 adapter->driver_mismatch = 0;
2186
d8313ce0 2187 ptr32 = (int *)&serial_num;
06db58c0 2188 offset = NX_FW_SERIAL_NUM_OFFSET;
dcd56fdb 2189 for (i = 0; i < 8; i++) {
06db58c0 2190 if (netxen_rom_fast_read(adapter, offset, &val) == -1) {
fbb52f22 2191 dev_err(&pdev->dev, "error reading board info\n");
dcd56fdb
DP		 2192 adapter->driver_mismatch = 1;
2193 return;
cb8011ad 2194 }
fbb52f22 2195 ptr32[i] = cpu_to_le32(val);
06db58c0 2196 offset += sizeof(u32);
dcd56fdb
DP		 2197 }
2198
f98a9f69
DP		 2199 fw_major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
2200 fw_minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
2201 fw_build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
8d74849b 2202
1e2d0059 2203 adapter->fw_version = NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build);
2956640d 2204
dcd56fdb 2205 if (adapter->portnum == 0) {
1e2d0059 2206 get_brd_name_by_type(adapter->ahw.board_type, brd_name);
cb8011ad 2207
11d89d63
DP		 2208 printk(KERN_INFO "NetXen %s Board S/N %s Chip rev 0x%x\n",
2209 brd_name, serial_num, adapter->ahw.revision_id);
3d396eb1 2210 }
dcd56fdb 2211
1e2d0059 2212 if (adapter->fw_version < NETXEN_VERSION_CODE(3, 4, 216)) {
3d396eb1 2213 adapter->driver_mismatch = 1;
1e2d0059 2214 dev_warn(&pdev->dev, "firmware version %d.%d.%d unsupported\n",
58735567 2215 fw_major, fw_minor, fw_build);
dcd56fdb
DP		 2216 return;
2217 }
1e2d0059
DP		 2218
2219 dev_info(&pdev->dev, "firmware version %d.%d.%d\n",
2220 fw_major, fw_minor, fw_build);
2221
2222 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
d1733460
DP		 2223 i = NXRD32(adapter, NETXEN_SRE_MISC);
2224 adapter->ahw.cut_through = (i & 0x8000) ? 1 : 0;
1e2d0059
DP		 2225 dev_info(&pdev->dev, "firmware running in %s mode\n",
2226 adapter->ahw.cut_through ? "cut-through" : "legacy");
2227 }
68b3cae0
DP		 2228
2229 if (adapter->fw_version >= NETXEN_VERSION_CODE(4, 0, 222))
2230 adapter->capabilities = NXRD32(adapter, CRB_FW_CAPABILITIES_1);
1bb482f8
NK		 2231
2232 adapter->flags &= ~NETXEN_NIC_LRO_ENABLED;
3d396eb1
AK		 2233}
2234
0b72e659
DP		 2235int
2236netxen_nic_wol_supported(struct netxen_adapter *adapter)
2237{
2238 u32 wol_cfg;
2239
2240 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
2241 return 0;
2242
f98a9f69 2243 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
0b72e659 2244 if (wol_cfg & (1UL << adapter->portnum)) {
f98a9f69 2245 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
0b72e659
DP		 2246 if (wol_cfg & (1 << adapter->portnum))
2247 return 1;
2248 }
2249
2250 return 0;
2251}
Linux kernel - Deliverables
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