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netxen: avoid undue board config check
[deliverable/linux.git] / drivers / net / netxen / netxen_nic_hw.c
CommitLineData
3d396eb1 1/*
5d242f1c 2 * Copyright (C) 2003 - 2009 NetXen, Inc.
13af7a6e 3 * Copyright (C) 2009 - QLogic Corporation.
3d396eb1 4 * All rights reserved.
80922fbc 5 *
3d396eb1
AK		 6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
cb8011ad 10 *
3d396eb1
AK		 11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
cb8011ad 15 *
3d396eb1
AK		 16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
80922fbc 20 *
3d396eb1
AK		 21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.
80922fbc 23 *
3d396eb1
AK		 24 */
25
26#include "netxen_nic.h"
27#include "netxen_nic_hw.h"
3d396eb1 28
c9bdd4b5
ACM		 29#include <net/ip.h>
30
3ce06a32
DP		 31#define MASK(n) ((1ULL<<(n))-1)
32#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
33#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
34#define MS_WIN(addr) (addr & 0x0ffc0000)
35
36#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
37
38#define CRB_BLK(off) ((off >> 20) & 0x3f)
39#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
40#define CRB_WINDOW_2M (0x130060)
41#define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
42#define CRB_INDIRECT_2M (0x1e0000UL)
43
e98e3350
DP		 44#ifndef readq
45static inline u64 readq(void __iomem *addr)
46{
47 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
48}
49#endif
50
51#ifndef writeq
52static inline void writeq(u64 val, void __iomem *addr)
53{
54 writel(((u32) (val)), (addr));
55 writel(((u32) (val >> 32)), (addr + 4));
56}
57#endif
58
1fbe6323
DP		 59#define ADDR_IN_RANGE(addr, low, high) \
60 (((addr) < (high)) && ((addr) >= (low)))
61
62#define PCI_OFFSET_FIRST_RANGE(adapter, off) \
63 ((adapter)->ahw.pci_base0 + (off))
64#define PCI_OFFSET_SECOND_RANGE(adapter, off) \
65 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
66#define PCI_OFFSET_THIRD_RANGE(adapter, off) \
67 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
68
69static void __iomem *pci_base_offset(struct netxen_adapter *adapter,
70 unsigned long off)
71{
72 if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END))
73 return PCI_OFFSET_FIRST_RANGE(adapter, off);
74
75 if (ADDR_IN_RANGE(off, SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_END))
76 return PCI_OFFSET_SECOND_RANGE(adapter, off);
77
78 if (ADDR_IN_RANGE(off, THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_END))
79 return PCI_OFFSET_THIRD_RANGE(adapter, off);
80
81 return NULL;
82}
83
ea7eaa39
DP		 84static crb_128M_2M_block_map_t
85crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
3ce06a32
DP		 86 {{{0, 0, 0, 0} } }, /* 0: PCI */
87 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
88 {1, 0x0110000, 0x0120000, 0x130000},
89 {1, 0x0120000, 0x0122000, 0x124000},
90 {1, 0x0130000, 0x0132000, 0x126000},
91 {1, 0x0140000, 0x0142000, 0x128000},
92 {1, 0x0150000, 0x0152000, 0x12a000},
93 {1, 0x0160000, 0x0170000, 0x110000},
94 {1, 0x0170000, 0x0172000, 0x12e000},
95 {0, 0x0000000, 0x0000000, 0x000000},
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {1, 0x01e0000, 0x01e0800, 0x122000},
102 {0, 0x0000000, 0x0000000, 0x000000} } },
103 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
104 {{{0, 0, 0, 0} } }, /* 3: */
105 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
106 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
107 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
108 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
109 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
110 {0, 0x0000000, 0x0000000, 0x000000},
111 {0, 0x0000000, 0x0000000, 0x000000},
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {1, 0x08f0000, 0x08f2000, 0x172000} } },
125 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {1, 0x09f0000, 0x09f2000, 0x176000} } },
141 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
157 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
173 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
174 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
175 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
176 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
177 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
178 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
179 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
180 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
181 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
182 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
183 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
184 {{{0, 0, 0, 0} } }, /* 23: */
185 {{{0, 0, 0, 0} } }, /* 24: */
186 {{{0, 0, 0, 0} } }, /* 25: */
187 {{{0, 0, 0, 0} } }, /* 26: */
188 {{{0, 0, 0, 0} } }, /* 27: */
189 {{{0, 0, 0, 0} } }, /* 28: */
190 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
191 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
192 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
193 {{{0} } }, /* 32: PCI */
194 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
195 {1, 0x2110000, 0x2120000, 0x130000},
196 {1, 0x2120000, 0x2122000, 0x124000},
197 {1, 0x2130000, 0x2132000, 0x126000},
198 {1, 0x2140000, 0x2142000, 0x128000},
199 {1, 0x2150000, 0x2152000, 0x12a000},
200 {1, 0x2160000, 0x2170000, 0x110000},
201 {1, 0x2170000, 0x2172000, 0x12e000},
202 {0, 0x0000000, 0x0000000, 0x000000},
203 {0, 0x0000000, 0x0000000, 0x000000},
204 {0, 0x0000000, 0x0000000, 0x000000},
205 {0, 0x0000000, 0x0000000, 0x000000},
206 {0, 0x0000000, 0x0000000, 0x000000},
207 {0, 0x0000000, 0x0000000, 0x000000},
208 {0, 0x0000000, 0x0000000, 0x000000},
209 {0, 0x0000000, 0x0000000, 0x000000} } },
210 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
211 {{{0} } }, /* 35: */
212 {{{0} } }, /* 36: */
213 {{{0} } }, /* 37: */
214 {{{0} } }, /* 38: */
215 {{{0} } }, /* 39: */
216 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
217 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
218 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
219 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
220 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
221 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
222 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
223 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
224 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
225 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
226 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
227 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
228 {{{0} } }, /* 52: */
229 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
230 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
231 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
232 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
233 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
234 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
235 {{{0} } }, /* 59: I2C0 */
236 {{{0} } }, /* 60: I2C1 */
237 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
238 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
239 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
240};
241
242/*
243 * top 12 bits of crb internal address (hub, agent)
244 */
245static unsigned crb_hub_agt[64] =
246{
247 0,
248 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
249 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
250 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
251 0,
252 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
253 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
254 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
255 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
256 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
257 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
258 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
259 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
260 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
261 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
262 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
263 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
264 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
265 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
266 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
267 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
268 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
269 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
270 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
271 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
272 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
273 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
274 0,
275 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
276 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
277 0,
278 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
279 0,
280 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
281 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
282 0,
283 0,
284 0,
285 0,
286 0,
287 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
288 0,
289 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
290 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
291 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
292 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
293 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
294 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
295 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
296 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
297 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
298 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
299 0,
300 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
301 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
302 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
303 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
304 0,
305 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
306 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
307 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
308 0,
309 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
310 0,
311};
312
3d396eb1
AK		 313/* PCI Windowing for DDR regions. */
314
3ce06a32 315#define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
3d396eb1 316
c9517e58
DP		 317#define NETXEN_PCIE_SEM_TIMEOUT 10000
318
319int
320netxen_pcie_sem_lock(struct netxen_adapter *adapter, int sem, u32 id_reg)
321{
322 int done = 0, timeout = 0;
323
324 while (!done) {
325 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_LOCK(sem)));
326 if (done == 1)
327 break;
328 if (++timeout >= NETXEN_PCIE_SEM_TIMEOUT)
329 return -1;
330 msleep(1);
331 }
332
333 if (id_reg)
334 NXWR32(adapter, id_reg, adapter->portnum);
335
336 return 0;
337}
338
339void
340netxen_pcie_sem_unlock(struct netxen_adapter *adapter, int sem)
341{
342 int val;
343 val = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
344}
345
3ad4467c
DP		 346int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port)
347{
348 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
349 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447);
350 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5);
351 }
352
353 return 0;
354}
355
356/* Disable an XG interface */
357int netxen_niu_disable_xg_port(struct netxen_adapter *adapter)
358{
359 __u32 mac_cfg;
360 u32 port = adapter->physical_port;
361
362 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
363 return 0;
364
365 if (port > NETXEN_NIU_MAX_XG_PORTS)
366 return -EINVAL;
367
368 mac_cfg = 0;
369 if (NXWR32(adapter,
370 NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg))
371 return -EIO;
372 return 0;
373}
374
623621b0
DP		 375#define NETXEN_UNICAST_ADDR(port, index) \
376 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
377#define NETXEN_MCAST_ADDR(port, index) \
378 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
379#define MAC_HI(addr) \
380 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
381#define MAC_LO(addr) \
382 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
383
3ad4467c
DP		 384int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
385{
386 __u32 reg;
387 u32 port = adapter->physical_port;
388
389 if (port > NETXEN_NIU_MAX_XG_PORTS)
390 return -EINVAL;
391
392 reg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port));
393 if (mode == NETXEN_NIU_PROMISC_MODE)
394 reg = (reg | 0x2000UL);
395 else
396 reg = (reg & ~0x2000UL);
397
398 if (mode == NETXEN_NIU_ALLMULTI_MODE)
399 reg = (reg | 0x1000UL);
400 else
401 reg = (reg & ~0x1000UL);
402
403 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
404
405 return 0;
406}
407
408int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
409{
410 u32 mac_hi, mac_lo;
411 u32 reg_hi, reg_lo;
412
413 u8 phy = adapter->physical_port;
414
415 if (phy >= NETXEN_NIU_MAX_XG_PORTS)
416 return -EINVAL;
417
418 mac_lo = ((u32)addr[0] << 16) | ((u32)addr[1] << 24);
419 mac_hi = addr[2] | ((u32)addr[3] << 8) |
420 ((u32)addr[4] << 16) | ((u32)addr[5] << 24);
421
422 reg_lo = NETXEN_NIU_XGE_STATION_ADDR_0_1 + (0x10000 * phy);
423 reg_hi = NETXEN_NIU_XGE_STATION_ADDR_0_HI + (0x10000 * phy);
424
425 /* write twice to flush */
426 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
427 return -EIO;
428 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
429 return -EIO;
430
431 return 0;
432}
433
623621b0
DP		 434static int
435netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
436{
437 u32 val = 0;
438 u16 port = adapter->physical_port;
439 u8 *addr = adapter->netdev->dev_addr;
440
441 if (adapter->mc_enabled)
442 return 0;
443
f98a9f69 444 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
623621b0 445 val |= (1UL << (28+port));
f98a9f69 446 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
623621b0
DP		 447
448 /* add broadcast addr to filter */
449 val = 0xffffff;
f98a9f69
DP		 450 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
451 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
623621b0
DP		 452
453 /* add station addr to filter */
454 val = MAC_HI(addr);
f98a9f69 455 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
623621b0 456 val = MAC_LO(addr);
f98a9f69 457 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val);
623621b0
DP		 458
459 adapter->mc_enabled = 1;
460 return 0;
461}
462
463static int
464netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
465{
466 u32 val = 0;
467 u16 port = adapter->physical_port;
468 u8 *addr = adapter->netdev->dev_addr;
469
470 if (!adapter->mc_enabled)
471 return 0;
472
f98a9f69 473 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
623621b0 474 val &= ~(1UL << (28+port));
f98a9f69 475 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
623621b0
DP		 476
477 val = MAC_HI(addr);
f98a9f69 478 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
623621b0 479 val = MAC_LO(addr);
f98a9f69 480 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
623621b0 481
f98a9f69
DP		 482 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
483 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
623621b0
DP		 484
485 adapter->mc_enabled = 0;
486 return 0;
487}
488
489static int
490netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
491 int index, u8 *addr)
492{
493 u32 hi = 0, lo = 0;
494 u16 port = adapter->physical_port;
495
496 lo = MAC_LO(addr);
497 hi = MAC_HI(addr);
498
f98a9f69
DP		 499 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi);
500 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo);
623621b0
DP		 501
502 return 0;
503}
504
c9fc891f 505void netxen_p2_nic_set_multi(struct net_device *netdev)
3d396eb1 506{
3176ff3e 507 struct netxen_adapter *adapter = netdev_priv(netdev);
3d396eb1 508 struct dev_mc_list *mc_ptr;
623621b0
DP		 509 u8 null_addr[6];
510 int index = 0;
511
512 memset(null_addr, 0, 6);
3d396eb1 513
3d396eb1 514 if (netdev->flags & IFF_PROMISC) {
623621b0
DP		 515
516 adapter->set_promisc(adapter,
517 NETXEN_NIU_PROMISC_MODE);
518
519 /* Full promiscuous mode */
520 netxen_nic_disable_mcast_filter(adapter);
521
522 return;
523 }
524
525 if (netdev->mc_count == 0) {
526 adapter->set_promisc(adapter,
527 NETXEN_NIU_NON_PROMISC_MODE);
528 netxen_nic_disable_mcast_filter(adapter);
529 return;
530 }
531
532 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
533 if (netdev->flags & IFF_ALLMULTI ||
534 netdev->mc_count > adapter->max_mc_count) {
535 netxen_nic_disable_mcast_filter(adapter);
536 return;
3d396eb1 537 }
623621b0
DP		 538
539 netxen_nic_enable_mcast_filter(adapter);
540
541 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++)
542 netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr);
543
544 if (index != netdev->mc_count)
545 printk(KERN_WARNING "%s: %s multicast address count mismatch\n",
546 netxen_nic_driver_name, netdev->name);
547
548 /* Clear out remaining addresses */
549 for (; index < adapter->max_mc_count; index++)
550 netxen_nic_set_mcast_addr(adapter, index, null_addr);
3d396eb1
AK		 551}
552
c9fc891f
DP		 553static int
554netxen_send_cmd_descs(struct netxen_adapter *adapter,
d877f1e3 555 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
c9fc891f 556{
d877f1e3 557 u32 i, producer, consumer;
c9fc891f
DP		 558 struct netxen_cmd_buffer *pbuf;
559 struct cmd_desc_type0 *cmd_desc;
d877f1e3 560 struct nx_host_tx_ring *tx_ring;
c9fc891f
DP		 561
562 i = 0;
563
db4cfd8a
DP		 564 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
565 return -EIO;
566
4ea528a1 567 tx_ring = adapter->tx_ring;
b2af9cb0 568 __netif_tx_lock_bh(tx_ring->txq);
03e678ee 569
d877f1e3
DP		 570 producer = tx_ring->producer;
571 consumer = tx_ring->sw_consumer;
572
b2af9cb0
DP		 573 if (nr_desc >= netxen_tx_avail(tx_ring)) {
574 netif_tx_stop_queue(tx_ring->txq);
575 __netif_tx_unlock_bh(tx_ring->txq);
d877f1e3
DP		 576 return -EBUSY;
577 }
578
c9fc891f
DP		 579 do {
580 cmd_desc = &cmd_desc_arr[i];
581
d877f1e3 582 pbuf = &tx_ring->cmd_buf_arr[producer];
c9fc891f 583 pbuf->skb = NULL;
c9fc891f 584 pbuf->frag_count = 0;
c9fc891f 585
d877f1e3 586 memcpy(&tx_ring->desc_head[producer],
c9fc891f
DP		 587 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
588
d877f1e3 589 producer = get_next_index(producer, tx_ring->num_desc);
c9fc891f
DP		 590 i++;
591
d877f1e3 592 } while (i != nr_desc);
c9fc891f 593
d877f1e3 594 tx_ring->producer = producer;
c9fc891f 595
cb2107be 596 netxen_nic_update_cmd_producer(adapter, tx_ring);
c9fc891f 597
b2af9cb0 598 __netif_tx_unlock_bh(tx_ring->txq);
03e678ee 599
c9fc891f
DP		 600 return 0;
601}
602
5cf4d323
DP		 603static int
604nx_p3_sre_macaddr_change(struct netxen_adapter *adapter, u8 *addr, unsigned op)
c9fc891f 605{
c9fc891f 606 nx_nic_req_t req;
2edbb454
DP		 607 nx_mac_req_t *mac_req;
608 u64 word;
c9fc891f
DP		 609
610 memset(&req, 0, sizeof(nx_nic_req_t));
2edbb454
DP		 611 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
612
613 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16);
614 req.req_hdr = cpu_to_le64(word);
615
616 mac_req = (nx_mac_req_t *)&req.words[0];
617 mac_req->op = op;
618 memcpy(mac_req->mac_addr, addr, 6);
c9fc891f 619
5cf4d323
DP		 620 return netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
621}
622
623static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
624 u8 *addr, struct list_head *del_list)
625{
626 struct list_head *head;
627 nx_mac_list_t *cur;
628
629 /* look up if already exists */
630 list_for_each(head, del_list) {
631 cur = list_entry(head, nx_mac_list_t, list);
632
633 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
634 list_move_tail(head, &adapter->mac_list);
635 return 0;
636 }
c9fc891f
DP		 637 }
638
5cf4d323
DP		 639 cur = kzalloc(sizeof(nx_mac_list_t), GFP_ATOMIC);
640 if (cur == NULL) {
641 printk(KERN_ERR "%s: failed to add mac address filter\n",
642 adapter->netdev->name);
643 return -ENOMEM;
644 }
645 memcpy(cur->mac_addr, addr, ETH_ALEN);
646 list_add_tail(&cur->list, &adapter->mac_list);
647 return nx_p3_sre_macaddr_change(adapter,
648 cur->mac_addr, NETXEN_MAC_ADD);
c9fc891f
DP		 649}
650
651void netxen_p3_nic_set_multi(struct net_device *netdev)
652{
653 struct netxen_adapter *adapter = netdev_priv(netdev);
c9fc891f
DP		 654 struct dev_mc_list *mc_ptr;
655 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
9ad27643 656 u32 mode = VPORT_MISS_MODE_DROP;
5cf4d323
DP		 657 LIST_HEAD(del_list);
658 struct list_head *head;
659 nx_mac_list_t *cur;
c9fc891f 660
5cf4d323 661 list_splice_tail_init(&adapter->mac_list, &del_list);
c9fc891f 662
5cf4d323
DP		 663 nx_p3_nic_add_mac(adapter, netdev->dev_addr, &del_list);
664 nx_p3_nic_add_mac(adapter, bcast_addr, &del_list);
9ad27643
DP		 665
666 if (netdev->flags & IFF_PROMISC) {
667 mode = VPORT_MISS_MODE_ACCEPT_ALL;
668 goto send_fw_cmd;
669 }
670
671 if ((netdev->flags & IFF_ALLMULTI) ||
672 (netdev->mc_count > adapter->max_mc_count)) {
673 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
674 goto send_fw_cmd;
675 }
676
c9fc891f 677 if (netdev->mc_count > 0) {
c9fc891f
DP		 678 for (mc_ptr = netdev->mc_list; mc_ptr;
679 mc_ptr = mc_ptr->next) {
5cf4d323 680 nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr, &del_list);
c9fc891f
DP		 681 }
682 }
9ad27643
DP		 683
684send_fw_cmd:
685 adapter->set_promisc(adapter, mode);
5cf4d323
DP		 686 head = &del_list;
687 while (!list_empty(head)) {
688 cur = list_entry(head->next, nx_mac_list_t, list);
689
690 nx_p3_sre_macaddr_change(adapter,
691 cur->mac_addr, NETXEN_MAC_DEL);
692 list_del(&cur->list);
c9fc891f 693 kfree(cur);
c9fc891f
DP		 694 }
695}
696
9ad27643
DP		 697int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
698{
699 nx_nic_req_t req;
2edbb454 700 u64 word;
9ad27643
DP		 701
702 memset(&req, 0, sizeof(nx_nic_req_t));
703
2edbb454
DP		 704 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
705
706 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
707 ((u64)adapter->portnum << 16);
708 req.req_hdr = cpu_to_le64(word);
709
9ad27643
DP		 710 req.words[0] = cpu_to_le64(mode);
711
712 return netxen_send_cmd_descs(adapter,
713 (struct cmd_desc_type0 *)&req, 1);
714}
715
06e9d9f9
DP		 716void netxen_p3_free_mac_list(struct netxen_adapter *adapter)
717{
5cf4d323
DP		 718 nx_mac_list_t *cur;
719 struct list_head *head = &adapter->mac_list;
720
721 while (!list_empty(head)) {
722 cur = list_entry(head->next, nx_mac_list_t, list);
723 nx_p3_sre_macaddr_change(adapter,
724 cur->mac_addr, NETXEN_MAC_DEL);
725 list_del(&cur->list);
06e9d9f9 726 kfree(cur);
06e9d9f9
DP		 727 }
728}
729
3d0a3cc9
DP		 730int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
731{
732 /* assuming caller has already copied new addr to netdev */
733 netxen_p3_nic_set_multi(adapter->netdev);
734 return 0;
735}
736
cd1f8160
DP		 737#define NETXEN_CONFIG_INTR_COALESCE 3
738
739/*
740 * Send the interrupt coalescing parameter set by ethtool to the card.
741 */
742int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
743{
744 nx_nic_req_t req;
2edbb454 745 u64 word;
cd1f8160
DP		 746 int rv;
747
748 memset(&req, 0, sizeof(nx_nic_req_t));
749
1bb482f8 750 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
2edbb454
DP		 751
752 word = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
753 req.req_hdr = cpu_to_le64(word);
cd1f8160
DP		 754
755 memcpy(&req.words[0], &adapter->coal, sizeof(adapter->coal));
756
757 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
758 if (rv != 0) {
759 printk(KERN_ERR "ERROR. Could not send "
760 "interrupt coalescing parameters\n");
761 }
762
763 return rv;
764}
765
1bb482f8
NK		 766int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable)
767{
768 nx_nic_req_t req;
769 u64 word;
770 int rv = 0;
771
772 if ((adapter->flags & NETXEN_NIC_LRO_ENABLED) == enable)
773 return 0;
774
775 memset(&req, 0, sizeof(nx_nic_req_t));
776
777 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
778
779 word = NX_NIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
780 req.req_hdr = cpu_to_le64(word);
781
782 req.words[0] = cpu_to_le64(enable);
783
784 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
785 if (rv != 0) {
786 printk(KERN_ERR "ERROR. Could not send "
787 "configure hw lro request\n");
788 }
789
790 adapter->flags ^= NETXEN_NIC_LRO_ENABLED;
791
792 return rv;
793}
794
fa3ce355
NK		 795int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable)
796{
797 nx_nic_req_t req;
798 u64 word;
799 int rv = 0;
800
801 if (!!(adapter->flags & NETXEN_NIC_BRIDGE_ENABLED) == enable)
802 return rv;
803
804 memset(&req, 0, sizeof(nx_nic_req_t));
805
806 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
807
808 word = NX_NIC_H2C_OPCODE_CONFIG_BRIDGING |
809 ((u64)adapter->portnum << 16);
810 req.req_hdr = cpu_to_le64(word);
811
812 req.words[0] = cpu_to_le64(enable);
813
814 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
815 if (rv != 0) {
816 printk(KERN_ERR "ERROR. Could not send "
817 "configure bridge mode request\n");
818 }
819
820 adapter->flags ^= NETXEN_NIC_BRIDGE_ENABLED;
821
822 return rv;
823}
824
825
d8b100c5
DP		 826#define RSS_HASHTYPE_IP_TCP 0x3
827
828int netxen_config_rss(struct netxen_adapter *adapter, int enable)
829{
830 nx_nic_req_t req;
831 u64 word;
832 int i, rv;
833
834 u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
835 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
836 0x255b0ec26d5a56daULL };
837
838
839 memset(&req, 0, sizeof(nx_nic_req_t));
840 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
841
842 word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
843 req.req_hdr = cpu_to_le64(word);
844
845 /*
846 * RSS request:
847 * bits 3-0: hash_method
848 * 5-4: hash_type_ipv4
849 * 7-6: hash_type_ipv6
850 * 8: enable
851 * 9: use indirection table
852 * 47-10: reserved
853 * 63-48: indirection table mask
854 */
855 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
856 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
857 ((u64)(enable & 0x1) << 8) |
858 ((0x7ULL) << 48);
859 req.words[0] = cpu_to_le64(word);
860 for (i = 0; i < 5; i++)
861 req.words[i+1] = cpu_to_le64(key[i]);
862
863
864 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
865 if (rv != 0) {
866 printk(KERN_ERR "%s: could not configure RSS\n",
867 adapter->netdev->name);
868 }
869
870 return rv;
871}
872
6598b169
DP		 873int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd)
874{
875 nx_nic_req_t req;
876 u64 word;
877 int rv;
878
879 memset(&req, 0, sizeof(nx_nic_req_t));
880 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
881
882 word = NX_NIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
883 req.req_hdr = cpu_to_le64(word);
884
885 req.words[0] = cpu_to_le64(cmd);
886 req.words[1] = cpu_to_le64(ip);
887
888 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
889 if (rv != 0) {
890 printk(KERN_ERR "%s: could not notify %s IP 0x%x reuqest\n",
891 adapter->netdev->name,
892 (cmd == NX_IP_UP) ? "Add" : "Remove", ip);
893 }
894 return rv;
895}
896
3bf26ce3
DP		 897int netxen_linkevent_request(struct netxen_adapter *adapter, int enable)
898{
899 nx_nic_req_t req;
900 u64 word;
901 int rv;
902
903 memset(&req, 0, sizeof(nx_nic_req_t));
904 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
905
906 word = NX_NIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
907 req.req_hdr = cpu_to_le64(word);
22527864 908 req.words[0] = cpu_to_le64(enable | (enable << 8));
3bf26ce3
DP		 909
910 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
911 if (rv != 0) {
912 printk(KERN_ERR "%s: could not configure link notification\n",
913 adapter->netdev->name);
914 }
915
916 return rv;
917}
918
1bb482f8
NK		 919int netxen_send_lro_cleanup(struct netxen_adapter *adapter)
920{
921 nx_nic_req_t req;
922 u64 word;
923 int rv;
924
925 memset(&req, 0, sizeof(nx_nic_req_t));
926 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
927
928 word = NX_NIC_H2C_OPCODE_LRO_REQUEST |
929 ((u64)adapter->portnum << 16) |
930 ((u64)NX_NIC_LRO_REQUEST_CLEANUP << 56) ;
931
932 req.req_hdr = cpu_to_le64(word);
933
934 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
935 if (rv != 0) {
936 printk(KERN_ERR "%s: could not cleanup lro flows\n",
937 adapter->netdev->name);
938 }
939 return rv;
940}
941
3d396eb1
AK		 942/*
943 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
944 * @returns 0 on success, negative on failure
945 */
c9fc891f
DP		 946
947#define MTU_FUDGE_FACTOR 100
948
3d396eb1
AK		 949int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
950{
3176ff3e 951 struct netxen_adapter *adapter = netdev_priv(netdev);
c9fc891f 952 int max_mtu;
9ad27643 953 int rc = 0;
3d396eb1 954
c9fc891f
DP		 955 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
956 max_mtu = P3_MAX_MTU;
957 else
958 max_mtu = P2_MAX_MTU;
959
960 if (mtu > max_mtu) {
961 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
962 netdev->name, max_mtu);
3d396eb1
AK		 963 return -EINVAL;
964 }
965
80922fbc 966 if (adapter->set_mtu)
9ad27643 967 rc = adapter->set_mtu(adapter, mtu);
3d396eb1 968
9ad27643
DP		 969 if (!rc)
970 netdev->mtu = mtu;
c9fc891f 971
9ad27643 972 return rc;
3d396eb1
AK		 973}
974
3d396eb1 975static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
f305f789 976 int size, __le32 * buf)
3d396eb1 977{
1e2d0059 978 int i, v, addr;
f305f789 979 __le32 *ptr32;
3d396eb1
AK		 980
981 addr = base;
982 ptr32 = buf;
983 for (i = 0; i < size / sizeof(u32); i++) {
f305f789 984 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
3d396eb1 985 return -1;
f305f789 986 *ptr32 = cpu_to_le32(v);
3d396eb1
AK		 987 ptr32++;
988 addr += sizeof(u32);
989 }
990 if ((char *)buf + size > (char *)ptr32) {
f305f789
AV		 991 __le32 local;
992 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
3d396eb1 993 return -1;
f305f789 994 local = cpu_to_le32(v);
3d396eb1
AK		 995 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
996 }
997
998 return 0;
999}
1000
9dc28efe 1001int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
3d396eb1 1002{
9dc28efe
DP		 1003 __le32 *pmac = (__le32 *) mac;
1004 u32 offset;
3d396eb1 1005
06db58c0 1006 offset = NX_FW_MAC_ADDR_OFFSET + (adapter->portnum * sizeof(u64));
9dc28efe
DP		 1007
1008 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
3d396eb1 1009 return -1;
9dc28efe 1010
f305f789 1011 if (*mac == cpu_to_le64(~0ULL)) {
9dc28efe 1012
06db58c0
DP		 1013 offset = NX_OLD_MAC_ADDR_OFFSET +
1014 (adapter->portnum * sizeof(u64));
9dc28efe 1015
3d396eb1 1016 if (netxen_get_flash_block(adapter,
9dc28efe 1017 offset, sizeof(u64), pmac) == -1)
3d396eb1 1018 return -1;
9dc28efe 1019
f305f789 1020 if (*mac == cpu_to_le64(~0ULL))
3d396eb1
AK		 1021 return -1;
1022 }
1023 return 0;
1024}
1025
9dc28efe
DP		 1026int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
1027{
1028 uint32_t crbaddr, mac_hi, mac_lo;
1029 int pci_func = adapter->ahw.pci_func;
1030
1031 crbaddr = CRB_MAC_BLOCK_START +
1032 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
1033
f98a9f69
DP		 1034 mac_lo = NXRD32(adapter, crbaddr);
1035 mac_hi = NXRD32(adapter, crbaddr+4);
9dc28efe 1036
9dc28efe 1037 if (pci_func & 1)
2edbb454 1038 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
9dc28efe 1039 else
2edbb454 1040 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
9dc28efe
DP		 1041
1042 return 0;
1043}
1044
3d396eb1
AK		 1045/*
1046 * Changes the CRB window to the specified window.
1047 */
195c5f98 1048static void
3ce06a32 1049netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw)
3d396eb1
AK		 1050{
1051 void __iomem *offset;
1052 u32 tmp;
1053 int count = 0;
e4c93c81 1054 uint8_t func = adapter->ahw.pci_func;
3d396eb1
AK		 1055
1056 if (adapter->curr_window == wndw)
1057 return;
3d396eb1
AK		 1058 /*
1059 * Move the CRB window.
1060 * We need to write to the "direct access" region of PCI
1061 * to avoid a race condition where the window register has
1062 * not been successfully written across CRB before the target
1063 * register address is received by PCI. The direct region bypasses
1064 * the CRB bus.
1065 */
e4c93c81
DP		 1066 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1067 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
3d396eb1
AK		 1068
1069 if (wndw & 0x1)
1070 wndw = NETXEN_WINDOW_ONE;
1071
1072 writel(wndw, offset);
1073
1074 /* MUST make sure window is set before we forge on... */
1075 while ((tmp = readl(offset)) != wndw) {
1076 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
1077 "registered properly: 0x%08x.\n",
3ce06a32 1078 netxen_nic_driver_name, __func__, tmp);
3d396eb1
AK		 1079 mdelay(1);
1080 if (count >= 10)
1081 break;
1082 count++;
1083 }
1084
6c80b18d
MT		 1085 if (wndw == NETXEN_WINDOW_ONE)
1086 adapter->curr_window = 1;
1087 else
1088 adapter->curr_window = 0;
3d396eb1
AK		 1089}
1090
3ce06a32
DP		 1091/*
1092 * Return -1 if off is not valid,
1093 * 1 if window access is needed. 'off' is set to offset from
1094 * CRB space in 128M pci map
1095 * 0 if no window access is needed. 'off' is set to 2M addr
1096 * In: 'off' is offset from base in 128M pci map
1097 */
1098static int
23b6cc42 1099netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter, ulong *off)
3ce06a32 1100{
3ce06a32
DP		 1101 crb_128M_2M_sub_block_map_t *m;
1102
1103
1104 if (*off >= NETXEN_CRB_MAX)
1105 return -1;
1106
23b6cc42 1107 if (*off >= NETXEN_PCI_CAMQM && (*off < NETXEN_PCI_CAMQM_2M_END)) {
3ce06a32
DP		 1108 *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE +
1109 (ulong)adapter->ahw.pci_base0;
1110 return 0;
1111 }
1112
1113 if (*off < NETXEN_PCI_CRBSPACE)
1114 return -1;
1115
1116 *off -= NETXEN_PCI_CRBSPACE;
3ce06a32
DP		 1117
1118 /*
1119 * Try direct map
1120 */
1121 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
1122
23b6cc42 1123 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
3ce06a32
DP		 1124 *off = *off + m->start_2M - m->start_128M +
1125 (ulong)adapter->ahw.pci_base0;
1126 return 0;
1127 }
1128
1129 /*
1130 * Not in direct map, use crb window
1131 */
1132 return 1;
1133}
1134
1135/*
1136 * In: 'off' is offset from CRB space in 128M pci map
1137 * Out: 'off' is 2M pci map addr
1138 * side effect: lock crb window
1139 */
1140static void
1141netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off)
1142{
1143 u32 win_read;
1144
1145 adapter->crb_win = CRB_HI(*off);
d8313ce0 1146 writel(adapter->crb_win, (adapter->ahw.pci_base0 + CRB_WINDOW_2M));
3ce06a32
DP		 1147 /*
1148 * Read back value to make sure write has gone through before trying
1149 * to use it.
1150 */
d8313ce0 1151 win_read = readl(adapter->ahw.pci_base0 + CRB_WINDOW_2M);
3ce06a32
DP		 1152 if (win_read != adapter->crb_win) {
1153 printk(KERN_ERR "%s: Written crbwin (0x%x) != "
1154 "Read crbwin (0x%x), off=0x%lx\n",
1155 __func__, adapter->crb_win, win_read, *off);
1156 }
1157 *off = (*off & MASK(16)) + CRB_INDIRECT_2M +
1158 (ulong)adapter->ahw.pci_base0;
1159}
1160
195c5f98 1161static int
1fbe6323 1162netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, ulong off, u32 data)
3d396eb1 1163{
195c5f98 1164 unsigned long flags;
3d396eb1
AK		 1165 void __iomem *addr;
1166
195c5f98 1167 if (ADDR_IN_WINDOW1(off))
3d396eb1 1168 addr = NETXEN_CRB_NORMALIZE(adapter, off);
195c5f98
AKS		 1169 else
1170 addr = pci_base_offset(adapter, off);
1171
1172 BUG_ON(!addr);
1173
1174 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1175 read_lock(&adapter->adapter_lock);
1176 writel(data, addr);
1177 read_unlock(&adapter->adapter_lock);
3d396eb1 1178 } else { /* Window 0 */
195c5f98 1179 write_lock_irqsave(&adapter->adapter_lock, flags);
cb8011ad 1180 addr = pci_base_offset(adapter, off);
3ce06a32 1181 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
195c5f98 1182 writel(data, addr);
3ce06a32 1183 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
195c5f98 1184 write_unlock_irqrestore(&adapter->adapter_lock, flags);
cb8011ad
AK		 1185 }
1186
3d396eb1
AK		 1187 return 0;
1188}
1189
195c5f98 1190static u32
1fbe6323 1191netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off)
3d396eb1 1192{
195c5f98 1193 unsigned long flags;
3d396eb1 1194 void __iomem *addr;
1fbe6323 1195 u32 data;
d8313ce0 1196
195c5f98 1197 if (ADDR_IN_WINDOW1(off))
3d396eb1 1198 addr = NETXEN_CRB_NORMALIZE(adapter, off);
195c5f98 1199 else
cb8011ad 1200 addr = pci_base_offset(adapter, off);
d8313ce0 1201
195c5f98 1202 BUG_ON(!addr);
3d396eb1 1203
195c5f98
AKS		 1204 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1205 read_lock(&adapter->adapter_lock);
1206 data = readl(addr);
1207 read_unlock(&adapter->adapter_lock);
1208 } else { /* Window 0 */
1209 write_lock_irqsave(&adapter->adapter_lock, flags);
1210 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1211 data = readl(addr);
3ce06a32 1212 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
195c5f98
AKS		 1213 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1214 }
3d396eb1 1215
1fbe6323 1216 return data;
3d396eb1
AK		 1217}
1218
195c5f98 1219static int
1fbe6323 1220netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, ulong off, u32 data)
3ce06a32 1221{
195c5f98 1222 unsigned long flags;
3ce06a32 1223 int rv;
3d396eb1 1224
23b6cc42 1225 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off);
3d396eb1 1226
3ce06a32
DP		 1227 if (rv == -1) {
1228 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1229 __func__, off);
1230 dump_stack();
1231 return -1;
1232 }
1233
1234 if (rv == 1) {
1235 write_lock_irqsave(&adapter->adapter_lock, flags);
1236 crb_win_lock(adapter);
1237 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1fbe6323 1238 writel(data, (void __iomem *)off);
3ce06a32
DP		 1239 crb_win_unlock(adapter);
1240 write_unlock_irqrestore(&adapter->adapter_lock, flags);
d8313ce0 1241 } else
1fbe6323 1242 writel(data, (void __iomem *)off);
d8313ce0 1243
3ce06a32
DP		 1244
1245 return 0;
3d396eb1
AK		 1246}
1247
195c5f98 1248static u32
1fbe6323 1249netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off)
3ce06a32 1250{
195c5f98 1251 unsigned long flags;
3ce06a32 1252 int rv;
1fbe6323 1253 u32 data;
3d396eb1 1254
23b6cc42 1255 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off);
3ce06a32
DP		 1256
1257 if (rv == -1) {
1258 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1259 __func__, off);
1260 dump_stack();
1261 return -1;
1262 }
1263
1264 if (rv == 1) {
1265 write_lock_irqsave(&adapter->adapter_lock, flags);
1266 crb_win_lock(adapter);
1267 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1fbe6323 1268 data = readl((void __iomem *)off);
3ce06a32
DP		 1269 crb_win_unlock(adapter);
1270 write_unlock_irqrestore(&adapter->adapter_lock, flags);
d8313ce0 1271 } else
1fbe6323 1272 data = readl((void __iomem *)off);
3ce06a32 1273
1fbe6323 1274 return data;
3ce06a32
DP		 1275}
1276
4790654c 1277static int netxen_pci_set_window_warning_count;
3d396eb1 1278
195c5f98 1279static unsigned long
3ce06a32
DP		 1280netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1281 unsigned long long addr)
3d396eb1 1282{
e4c93c81 1283 void __iomem *offset;
3d396eb1 1284 int window;
3ce06a32 1285 unsigned long long qdr_max;
e4c93c81 1286 uint8_t func = adapter->ahw.pci_func;
3d396eb1 1287
3ce06a32
DP		 1288 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1289 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1290 } else {
1291 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1292 }
1293
3d396eb1
AK		 1294 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1295 /* DDR network side */
1296 addr -= NETXEN_ADDR_DDR_NET;
1297 window = (addr >> 25) & 0x3ff;
3ce06a32
DP		 1298 if (adapter->ahw.ddr_mn_window != window) {
1299 adapter->ahw.ddr_mn_window = window;
e4c93c81
DP		 1300 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1301 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func)));
1302 writel(window, offset);
3d396eb1 1303 /* MUST make sure window is set before we forge on... */
e4c93c81 1304 readl(offset);
3d396eb1 1305 }
cb8011ad 1306 addr -= (window * NETXEN_WINDOW_ONE);
3d396eb1
AK		 1307 addr += NETXEN_PCI_DDR_NET;
1308 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1309 addr -= NETXEN_ADDR_OCM0;
1310 addr += NETXEN_PCI_OCM0;
1311 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1312 addr -= NETXEN_ADDR_OCM1;
1313 addr += NETXEN_PCI_OCM1;
3ce06a32 1314 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
3d396eb1
AK		 1315 /* QDR network side */
1316 addr -= NETXEN_ADDR_QDR_NET;
1317 window = (addr >> 22) & 0x3f;
3ce06a32
DP		 1318 if (adapter->ahw.qdr_sn_window != window) {
1319 adapter->ahw.qdr_sn_window = window;
e4c93c81
DP		 1320 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1321 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func)));
1322 writel((window << 22), offset);
3d396eb1 1323 /* MUST make sure window is set before we forge on... */
e4c93c81 1324 readl(offset);
3d396eb1
AK		 1325 }
1326 addr -= (window * 0x400000);
1327 addr += NETXEN_PCI_QDR_NET;
1328 } else {
1329 /*
1330 * peg gdb frequently accesses memory that doesn't exist,
1331 * this limits the chit chat so debugging isn't slowed down.
1332 */
1333 if ((netxen_pci_set_window_warning_count++ < 8)
1334 || (netxen_pci_set_window_warning_count % 64 == 0))
1335 printk("%s: Warning:netxen_nic_pci_set_window()"
1336 " Unknown address range!\n",
1337 netxen_nic_driver_name);
3ce06a32
DP		 1338 addr = -1UL;
1339 }
1340 return addr;
1341}
1342
195c5f98
AKS		 1343/* window 1 registers only */
1344static void netxen_nic_io_write_128M(struct netxen_adapter *adapter,
1345 void __iomem *addr, u32 data)
3ce06a32 1346{
195c5f98
AKS		 1347 read_lock(&adapter->adapter_lock);
1348 writel(data, addr);
1349 read_unlock(&adapter->adapter_lock);
1350}
1351
1352static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter,
1353 void __iomem *addr)
1354{
1355 u32 val;
1356
1357 read_lock(&adapter->adapter_lock);
1358 val = readl(addr);
1359 read_unlock(&adapter->adapter_lock);
1360
1361 return val;
3ce06a32
DP		 1362}
1363
195c5f98
AKS		 1364static void netxen_nic_io_write_2M(struct netxen_adapter *adapter,
1365 void __iomem *addr, u32 data)
3ce06a32 1366{
195c5f98
AKS		 1367 writel(data, addr);
1368}
1369
1370static u32 netxen_nic_io_read_2M(struct netxen_adapter *adapter,
1371 void __iomem *addr)
1372{
1373 return readl(addr);
1374}
1375
1376void __iomem *
1377netxen_get_ioaddr(struct netxen_adapter *adapter, u32 offset)
1378{
1379 ulong off = offset;
1380
1381 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1382 if (offset < NETXEN_CRB_PCIX_HOST2 &&
1383 offset > NETXEN_CRB_PCIX_HOST)
1384 return PCI_OFFSET_SECOND_RANGE(adapter, offset);
1385 return NETXEN_CRB_NORMALIZE(adapter, offset);
1386 }
1387
1388 BUG_ON(netxen_nic_pci_get_crb_addr_2M(adapter, &off));
1389 return (void __iomem *)off;
3ce06a32
DP		 1390}
1391
195c5f98 1392static unsigned long
3ce06a32
DP		 1393netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1394 unsigned long long addr)
1395{
1396 int window;
1397 u32 win_read;
3d396eb1 1398
3ce06a32
DP		 1399 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1400 /* DDR network side */
1401 window = MN_WIN(addr);
1402 adapter->ahw.ddr_mn_window = window;
ea6828b8
DP		 1403 NXWR32(adapter, adapter->ahw.mn_win_crb, window);
1404 win_read = NXRD32(adapter, adapter->ahw.mn_win_crb);
3ce06a32
DP		 1405 if ((win_read << 17) != window) {
1406 printk(KERN_INFO "Written MNwin (0x%x) != "
1407 "Read MNwin (0x%x)\n", window, win_read);
1408 }
1409 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_DDR_NET;
1410 } else if (ADDR_IN_RANGE(addr,
1411 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1412 if ((addr & 0x00ff800) == 0xff800) {
1413 printk("%s: QM access not handled.\n", __func__);
1414 addr = -1UL;
1415 }
1416
1417 window = OCM_WIN(addr);
1418 adapter->ahw.ddr_mn_window = window;
ea6828b8
DP		 1419 NXWR32(adapter, adapter->ahw.mn_win_crb, window);
1420 win_read = NXRD32(adapter, adapter->ahw.mn_win_crb);
3ce06a32
DP		 1421 if ((win_read >> 7) != window) {
1422 printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
1423 "Read OCMwin (0x%x)\n",
1424 __func__, window, win_read);
1425 }
1426 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_OCM0_2M;
1427
1428 } else if (ADDR_IN_RANGE(addr,
1429 NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P3)) {
1430 /* QDR network side */
1431 window = MS_WIN(addr);
1432 adapter->ahw.qdr_sn_window = window;
ea6828b8
DP		 1433 NXWR32(adapter, adapter->ahw.ms_win_crb, window);
1434 win_read = NXRD32(adapter, adapter->ahw.ms_win_crb);
3ce06a32
DP		 1435 if (win_read != window) {
1436 printk(KERN_INFO "%s: Written MSwin (0x%x) != "
1437 "Read MSwin (0x%x)\n",
1438 __func__, window, win_read);
1439 }
1440 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_QDR_NET;
1441
1442 } else {
1443 /*
1444 * peg gdb frequently accesses memory that doesn't exist,
1445 * this limits the chit chat so debugging isn't slowed down.
1446 */
1447 if ((netxen_pci_set_window_warning_count++ < 8)
1448 || (netxen_pci_set_window_warning_count%64 == 0)) {
1449 printk("%s: Warning:%s Unknown address range!\n",
1450 __func__, netxen_nic_driver_name);
1451}
1452 addr = -1UL;
3d396eb1
AK		 1453 }
1454 return addr;
1455}
1456
3ce06a32
DP		 1457#define MAX_CTL_CHECK 1000
1458
195c5f98 1459static int
3ce06a32
DP		 1460netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1461 u64 off, void *data, int size)
1462{
d8313ce0 1463 unsigned long flags;
3ce06a32
DP		 1464 int i, j, ret = 0, loop, sz[2], off0;
1465 uint32_t temp;
1466 uint64_t off8, tmpw, word[2] = {0, 0};
d8313ce0 1467 void __iomem *mem_crb;
3ce06a32 1468
ea6828b8
DP		 1469 if (size != 8)
1470 return -EIO;
1471
1472 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1473 NETXEN_ADDR_QDR_NET_MAX_P2)) {
1474 mem_crb = pci_base_offset(adapter, NETXEN_CRB_QDR_NET);
1475 goto correct;
1476 }
3ce06a32 1477
ea6828b8
DP		 1478 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1479 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1480 goto correct;
1481 }
1482
1483 return -EIO;
1484
1485correct:
3ce06a32
DP		 1486 off8 = off & 0xfffffff8;
1487 off0 = off & 0x7;
1488 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1489 sz[1] = size - sz[0];
1490 loop = ((off0 + size - 1) >> 3) + 1;
3ce06a32
DP		 1491
1492 if ((size != 8) || (off0 != 0)) {
1493 for (i = 0; i < loop; i++) {
1494 if (adapter->pci_mem_read(adapter,
1495 off8 + (i << 3), &word[i], 8))
1496 return -1;
1497 }
1498 }
1499
1500 switch (size) {
1501 case 1:
1502 tmpw = *((uint8_t *)data);
1503 break;
1504 case 2:
1505 tmpw = *((uint16_t *)data);
1506 break;
1507 case 4:
1508 tmpw = *((uint32_t *)data);
1509 break;
1510 case 8:
1511 default:
1512 tmpw = *((uint64_t *)data);
1513 break;
1514 }
1515 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1516 word[0] |= tmpw << (off0 * 8);
1517
1518 if (loop == 2) {
1519 word[1] &= ~(~0ULL << (sz[1] * 8));
1520 word[1] |= tmpw >> (sz[0] * 8);
1521 }
1522
1523 write_lock_irqsave(&adapter->adapter_lock, flags);
1524 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1525
1526 for (i = 0; i < loop; i++) {
1527 writel((uint32_t)(off8 + (i << 3)),
d8313ce0 1528 (mem_crb+MIU_TEST_AGT_ADDR_LO));
3ce06a32 1529 writel(0,
d8313ce0 1530 (mem_crb+MIU_TEST_AGT_ADDR_HI));
3ce06a32 1531 writel(word[i] & 0xffffffff,
d8313ce0 1532 (mem_crb+MIU_TEST_AGT_WRDATA_LO));
3ce06a32 1533 writel((word[i] >> 32) & 0xffffffff,
d8313ce0 1534 (mem_crb+MIU_TEST_AGT_WRDATA_HI));
3ce06a32 1535 writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
d8313ce0 1536 (mem_crb+MIU_TEST_AGT_CTRL));
3ce06a32 1537 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
d8313ce0 1538 (mem_crb+MIU_TEST_AGT_CTRL));
3ce06a32
DP		 1539
1540 for (j = 0; j < MAX_CTL_CHECK; j++) {
1541 temp = readl(
d8313ce0 1542 (mem_crb+MIU_TEST_AGT_CTRL));
3ce06a32
DP		 1543 if ((temp & MIU_TA_CTL_BUSY) == 0)
1544 break;
1545 }
1546
1547 if (j >= MAX_CTL_CHECK) {
39754f44
DP		 1548 if (printk_ratelimit())
1549 dev_err(&adapter->pdev->dev,
1550 "failed to write through agent\n");
3ce06a32
DP		 1551 ret = -1;
1552 break;
1553 }
1554 }
1555
1556 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1557 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1558 return ret;
1559}
1560
195c5f98 1561static int
3ce06a32
DP		 1562netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1563 u64 off, void *data, int size)
1564{
d8313ce0 1565 unsigned long flags;
3ce06a32
DP		 1566 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1567 uint32_t temp;
1568 uint64_t off8, val, word[2] = {0, 0};
d8313ce0 1569 void __iomem *mem_crb;
3ce06a32 1570
ea6828b8
DP		 1571 if (size != 8)
1572 return -EIO;
1573
1574 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1575 NETXEN_ADDR_QDR_NET_MAX_P2)) {
1576 mem_crb = pci_base_offset(adapter, NETXEN_CRB_QDR_NET);
1577 goto correct;
1578 }
3ce06a32 1579
ea6828b8
DP		 1580 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1581 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1582 goto correct;
1583 }
1584
1585 return -EIO;
3ce06a32 1586
ea6828b8 1587correct:
3ce06a32
DP		 1588 off8 = off & 0xfffffff8;
1589 off0[0] = off & 0x7;
1590 off0[1] = 0;
1591 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1592 sz[1] = size - sz[0];
1593 loop = ((off0[0] + size - 1) >> 3) + 1;
3ce06a32
DP		 1594
1595 write_lock_irqsave(&adapter->adapter_lock, flags);
1596 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1597
1598 for (i = 0; i < loop; i++) {
1599 writel((uint32_t)(off8 + (i << 3)),
d8313ce0 1600 (mem_crb+MIU_TEST_AGT_ADDR_LO));
3ce06a32 1601 writel(0,
d8313ce0 1602 (mem_crb+MIU_TEST_AGT_ADDR_HI));
3ce06a32 1603 writel(MIU_TA_CTL_ENABLE,
d8313ce0 1604 (mem_crb+MIU_TEST_AGT_CTRL));
3ce06a32 1605 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE,
d8313ce0 1606 (mem_crb+MIU_TEST_AGT_CTRL));
3ce06a32
DP		 1607
1608 for (j = 0; j < MAX_CTL_CHECK; j++) {
1609 temp = readl(
d8313ce0 1610 (mem_crb+MIU_TEST_AGT_CTRL));
3ce06a32
DP		 1611 if ((temp & MIU_TA_CTL_BUSY) == 0)
1612 break;
1613 }
1614
1615 if (j >= MAX_CTL_CHECK) {
39754f44
DP		 1616 if (printk_ratelimit())
1617 dev_err(&adapter->pdev->dev,
1618 "failed to read through agent\n");
3ce06a32
DP		 1619 break;
1620 }
1621
1622 start = off0[i] >> 2;
1623 end = (off0[i] + sz[i] - 1) >> 2;
1624 for (k = start; k <= end; k++) {
1625 word[i] |= ((uint64_t) readl(
d8313ce0 1626 (mem_crb +
3ce06a32
DP		 1627 MIU_TEST_AGT_RDDATA(k))) << (32*k));
1628 }
1629 }
1630
1631 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1632 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1633
1634 if (j >= MAX_CTL_CHECK)
1635 return -1;
1636
1637 if (sz[0] == 8) {
1638 val = word[0];
1639 } else {
1640 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1641 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1642 }
1643
1644 switch (size) {
1645 case 1:
1646 *(uint8_t *)data = val;
1647 break;
1648 case 2:
1649 *(uint16_t *)data = val;
1650 break;
1651 case 4:
1652 *(uint32_t *)data = val;
1653 break;
1654 case 8:
1655 *(uint64_t *)data = val;
1656 break;
1657 }
3ce06a32
DP		 1658 return 0;
1659}
1660
195c5f98 1661static int
3ce06a32
DP		 1662netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1663 u64 off, void *data, int size)
1664{
1665 int i, j, ret = 0, loop, sz[2], off0;
1666 uint32_t temp;
ea6828b8
DP		 1667 uint64_t off8, tmpw, word[2] = {0, 0};
1668 void __iomem *mem_crb;
3ce06a32 1669
ea6828b8
DP		 1670 if (size != 8)
1671 return -EIO;
1672
1673 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1674 NETXEN_ADDR_QDR_NET_MAX_P3)) {
1675 mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_QDR_NET);
1676 goto correct;
1677 }
1678
1679 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1680 mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_DDR_NET);
1681 goto correct;
3ce06a32
DP		 1682 }
1683
ea6828b8
DP		 1684 return -EIO;
1685
1686correct:
3ce06a32
DP		 1687 off8 = off & 0xfffffff8;
1688 off0 = off & 0x7;
1689 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1690 sz[1] = size - sz[0];
1691 loop = ((off0 + size - 1) >> 3) + 1;
1692
1693 if ((size != 8) || (off0 != 0)) {
1694 for (i = 0; i < loop; i++) {
195c5f98
AKS		 1695 if (adapter->pci_mem_read(adapter,
1696 off8 + (i << 3), &word[i], 8))
3ce06a32
DP		 1697 return -1;
1698 }
1699 }
1700
1701 switch (size) {
1702 case 1:
1703 tmpw = *((uint8_t *)data);
1704 break;
1705 case 2:
1706 tmpw = *((uint16_t *)data);
1707 break;
1708 case 4:
1709 tmpw = *((uint32_t *)data);
1710 break;
1711 case 8:
1712 default:
1713 tmpw = *((uint64_t *)data);
1714 break;
1715 }
1716
1717 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1718 word[0] |= tmpw << (off0 * 8);
1719
1720 if (loop == 2) {
1721 word[1] &= ~(~0ULL << (sz[1] * 8));
1722 word[1] |= tmpw >> (sz[0] * 8);
1723 }
1724
1725 /*
1726 * don't lock here - write_wx gets the lock if each time
1727 * write_lock_irqsave(&adapter->adapter_lock, flags);
1728 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1729 */
1730
1731 for (i = 0; i < loop; i++) {
ea6828b8
DP		 1732 writel(off8 + (i << 3), mem_crb+MIU_TEST_AGT_ADDR_LO);
1733 writel(0, mem_crb+MIU_TEST_AGT_ADDR_HI);
1734 writel(word[i] & 0xffffffff, mem_crb+MIU_TEST_AGT_WRDATA_LO);
1735 writel((word[i] >> 32) & 0xffffffff,
1736 mem_crb+MIU_TEST_AGT_WRDATA_HI);
1737 writel((MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE),
1738 mem_crb+MIU_TEST_AGT_CTRL);
1739 writel(MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE,
1740 mem_crb+MIU_TEST_AGT_CTRL);
3ce06a32
DP		 1741
1742 for (j = 0; j < MAX_CTL_CHECK; j++) {
ea6828b8 1743 temp = readl(mem_crb + MIU_TEST_AGT_CTRL);
3ce06a32
DP		 1744 if ((temp & MIU_TA_CTL_BUSY) == 0)
1745 break;
1746 }
1747
1748 if (j >= MAX_CTL_CHECK) {
39754f44
DP		 1749 if (printk_ratelimit())
1750 dev_err(&adapter->pdev->dev,
1751 "failed to write through agent\n");
3ce06a32
DP		 1752 ret = -1;
1753 break;
1754 }
1755 }
1756
1757 /*
1758 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1759 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1760 */
1761 return ret;
1762}
1763
195c5f98 1764static int
3ce06a32
DP		 1765netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1766 u64 off, void *data, int size)
1767{
1768 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1769 uint32_t temp;
ea6828b8
DP		 1770 uint64_t off8, val, word[2] = {0, 0};
1771 void __iomem *mem_crb;
3ce06a32 1772
ea6828b8
DP		 1773 if (size != 8)
1774 return -EIO;
3ce06a32 1775
ea6828b8
DP		 1776 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1777 NETXEN_ADDR_QDR_NET_MAX_P3)) {
1778 mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_QDR_NET);
1779 goto correct;
3ce06a32
DP		 1780 }
1781
ea6828b8
DP		 1782 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1783 mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_DDR_NET);
1784 goto correct;
1785 }
1786
1787 return -EIO;
1788
1789correct:
3ce06a32
DP		 1790 off8 = off & 0xfffffff8;
1791 off0[0] = off & 0x7;
1792 off0[1] = 0;
1793 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1794 sz[1] = size - sz[0];
1795 loop = ((off0[0] + size - 1) >> 3) + 1;
1796
1797 /*
1798 * don't lock here - write_wx gets the lock if each time
1799 * write_lock_irqsave(&adapter->adapter_lock, flags);
1800 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1801 */
1802
1803 for (i = 0; i < loop; i++) {
ea6828b8
DP		 1804 writel(off8 + (i << 3), mem_crb + MIU_TEST_AGT_ADDR_LO);
1805 writel(0, mem_crb + MIU_TEST_AGT_ADDR_HI);
1806 writel(MIU_TA_CTL_ENABLE, mem_crb + MIU_TEST_AGT_CTRL);
1807 writel(MIU_TA_CTL_START | MIU_TA_CTL_ENABLE,
1808 mem_crb + MIU_TEST_AGT_CTRL);
3ce06a32
DP		 1809
1810 for (j = 0; j < MAX_CTL_CHECK; j++) {
ea6828b8 1811 temp = readl(mem_crb + MIU_TEST_AGT_CTRL);
3ce06a32
DP		 1812 if ((temp & MIU_TA_CTL_BUSY) == 0)
1813 break;
1814 }
1815
1816 if (j >= MAX_CTL_CHECK) {
39754f44
DP		 1817 if (printk_ratelimit())
1818 dev_err(&adapter->pdev->dev,
1819 "failed to read through agent\n");
3ce06a32
DP		 1820 break;
1821 }
1822
1823 start = off0[i] >> 2;
1824 end = (off0[i] + sz[i] - 1) >> 2;
1825 for (k = start; k <= end; k++) {
ea6828b8 1826 temp = readl(mem_crb + MIU_TEST_AGT_RDDATA(k));
3ce06a32
DP		 1827 word[i] |= ((uint64_t)temp << (32 * k));
1828 }
1829 }
1830
1831 /*
1832 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1833 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1834 */
1835
1836 if (j >= MAX_CTL_CHECK)
1837 return -1;
1838
1839 if (sz[0] == 8) {
1840 val = word[0];
1841 } else {
1842 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1843 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1844 }
1845
1846 switch (size) {
1847 case 1:
1848 *(uint8_t *)data = val;
1849 break;
1850 case 2:
1851 *(uint16_t *)data = val;
1852 break;
1853 case 4:
1854 *(uint32_t *)data = val;
1855 break;
1856 case 8:
1857 *(uint64_t *)data = val;
1858 break;
1859 }
3ce06a32
DP		 1860 return 0;
1861}
1862
195c5f98
AKS		 1863void
1864netxen_setup_hwops(struct netxen_adapter *adapter)
3ce06a32 1865{
195c5f98
AKS		 1866 adapter->init_port = netxen_niu_xg_init_port;
1867 adapter->stop_port = netxen_niu_disable_xg_port;
3ce06a32 1868
195c5f98
AKS		 1869 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1870 adapter->crb_read = netxen_nic_hw_read_wx_128M,
1871 adapter->crb_write = netxen_nic_hw_write_wx_128M,
1872 adapter->pci_set_window = netxen_nic_pci_set_window_128M,
1873 adapter->pci_mem_read = netxen_nic_pci_mem_read_128M,
1874 adapter->pci_mem_write = netxen_nic_pci_mem_write_128M,
1875 adapter->io_read = netxen_nic_io_read_128M,
1876 adapter->io_write = netxen_nic_io_write_128M,
1877
1878 adapter->macaddr_set = netxen_p2_nic_set_mac_addr;
1879 adapter->set_multi = netxen_p2_nic_set_multi;
1880 adapter->set_mtu = netxen_nic_set_mtu_xgb;
1881 adapter->set_promisc = netxen_p2_nic_set_promisc;
3ce06a32 1882
195c5f98
AKS		 1883 } else {
1884 adapter->crb_read = netxen_nic_hw_read_wx_2M,
1885 adapter->crb_write = netxen_nic_hw_write_wx_2M,
1886 adapter->pci_set_window = netxen_nic_pci_set_window_2M,
1887 adapter->pci_mem_read = netxen_nic_pci_mem_read_2M,
1888 adapter->pci_mem_write = netxen_nic_pci_mem_write_2M,
1889 adapter->io_read = netxen_nic_io_read_2M,
1890 adapter->io_write = netxen_nic_io_write_2M,
1891
1892 adapter->set_mtu = nx_fw_cmd_set_mtu;
1893 adapter->set_promisc = netxen_p3_nic_set_promisc;
1894 adapter->macaddr_set = netxen_p3_nic_set_mac_addr;
1895 adapter->set_multi = netxen_p3_nic_set_multi;
1896
1897 adapter->phy_read = nx_fw_cmd_query_phy;
1898 adapter->phy_write = nx_fw_cmd_set_phy;
1899 }
3ce06a32
DP		 1900}
1901
3d396eb1
AK		 1902int netxen_nic_get_board_info(struct netxen_adapter *adapter)
1903{
0dc6d9cb 1904 int offset, board_type, magic;
1e2d0059 1905 struct pci_dev *pdev = adapter->pdev;
3d396eb1 1906
06db58c0 1907 offset = NX_FW_MAGIC_OFFSET;
1e2d0059
DP		 1908 if (netxen_rom_fast_read(adapter, offset, &magic))
1909 return -EIO;
3d396eb1 1910
0dc6d9cb
DP		 1911 if (magic != NETXEN_BDINFO_MAGIC) {
1912 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1913 magic);
1e2d0059 1914 return -EIO;
3d396eb1
AK		 1915 }
1916
06db58c0 1917 offset = NX_BRDTYPE_OFFSET;
1e2d0059
DP		 1918 if (netxen_rom_fast_read(adapter, offset, &board_type))
1919 return -EIO;
1920
1921 adapter->ahw.board_type = board_type;
1922
1923 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
f98a9f69 1924 u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I);
c7860a2a 1925 if ((gpio & 0x8000) == 0)
1e2d0059 1926 board_type = NETXEN_BRDTYPE_P3_10G_TP;
c7860a2a
DP		 1927 }
1928
e98e3350 1929 switch (board_type) {
3d396eb1 1930 case NETXEN_BRDTYPE_P2_SB35_4G:
1e2d0059 1931 adapter->ahw.port_type = NETXEN_NIC_GBE;
3d396eb1
AK		 1932 break;
1933 case NETXEN_BRDTYPE_P2_SB31_10G:
1934 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
1935 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
1936 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
e4c93c81
DP		 1937 case NETXEN_BRDTYPE_P3_HMEZ:
1938 case NETXEN_BRDTYPE_P3_XG_LOM:
1939 case NETXEN_BRDTYPE_P3_10G_CX4:
1940 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
1941 case NETXEN_BRDTYPE_P3_IMEZ:
1942 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
a70f9393
DP		 1943 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
1944 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
e4c93c81
DP		 1945 case NETXEN_BRDTYPE_P3_10G_XFP:
1946 case NETXEN_BRDTYPE_P3_10000_BASE_T:
1e2d0059 1947 adapter->ahw.port_type = NETXEN_NIC_XGBE;
3d396eb1
AK		 1948 break;
1949 case NETXEN_BRDTYPE_P1_BD:
1950 case NETXEN_BRDTYPE_P1_SB:
1951 case NETXEN_BRDTYPE_P1_SMAX:
1952 case NETXEN_BRDTYPE_P1_SOCK:
e4c93c81
DP		 1953 case NETXEN_BRDTYPE_P3_REF_QG:
1954 case NETXEN_BRDTYPE_P3_4_GB:
1955 case NETXEN_BRDTYPE_P3_4_GB_MM:
1e2d0059 1956 adapter->ahw.port_type = NETXEN_NIC_GBE;
3d396eb1 1957 break;
c7860a2a 1958 case NETXEN_BRDTYPE_P3_10G_TP:
1e2d0059 1959 adapter->ahw.port_type = (adapter->portnum < 2) ?
c7860a2a
DP		 1960 NETXEN_NIC_XGBE : NETXEN_NIC_GBE;
1961 break;
3d396eb1 1962 default:
1e2d0059
DP		 1963 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1964 adapter->ahw.port_type = NETXEN_NIC_XGBE;
3d396eb1
AK		 1965 break;
1966 }
1967
1e2d0059 1968 return 0;
3d396eb1
AK		 1969}
1970
1971/* NIU access sections */
1972
3176ff3e 1973int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
3d396eb1 1974{
9ad27643 1975 new_mtu += MTU_FUDGE_FACTOR;
f98a9f69 1976 NXWR32(adapter, NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
3276fbad 1977 new_mtu);
3d396eb1
AK		 1978 return 0;
1979}
1980
3176ff3e 1981int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
3d396eb1 1982{
9ad27643 1983 new_mtu += MTU_FUDGE_FACTOR;
3276fbad 1984 if (adapter->physical_port == 0)
f98a9f69 1985 NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
4790654c 1986 else
f98a9f69 1987 NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu);
3d396eb1
AK		 1988 return 0;
1989}
1990
3176ff3e 1991void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
3d396eb1 1992{
a608ab9c
AV		 1993 __u32 status;
1994 __u32 autoneg;
24a7a455 1995 __u32 port_mode;
3d396eb1 1996
c7860a2a
DP		 1997 if (!netif_carrier_ok(adapter->netdev)) {
1998 adapter->link_speed = 0;
1999 adapter->link_duplex = -1;
2000 adapter->link_autoneg = AUTONEG_ENABLE;
2001 return;
2002 }
24a7a455 2003
1e2d0059 2004 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
f98a9f69 2005 port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR);
24a7a455
DP		 2006 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
2007 adapter->link_speed = SPEED_1000;
2008 adapter->link_duplex = DUPLEX_FULL;
2009 adapter->link_autoneg = AUTONEG_DISABLE;
2010 return;
2011 }
2012
80922fbc 2013 if (adapter->phy_read
24a7a455 2014 && adapter->phy_read(adapter,
3d396eb1
AK		 2015 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
2016 &status) == 0) {
2017 if (netxen_get_phy_link(status)) {
2018 switch (netxen_get_phy_speed(status)) {
2019 case 0:
3176ff3e 2020 adapter->link_speed = SPEED_10;
3d396eb1
AK		 2021 break;
2022 case 1:
3176ff3e 2023 adapter->link_speed = SPEED_100;
3d396eb1
AK		 2024 break;
2025 case 2:
3176ff3e 2026 adapter->link_speed = SPEED_1000;
3d396eb1
AK		 2027 break;
2028 default:
c7860a2a 2029 adapter->link_speed = 0;
3d396eb1
AK		 2030 break;
2031 }
2032 switch (netxen_get_phy_duplex(status)) {
2033 case 0:
3176ff3e 2034 adapter->link_duplex = DUPLEX_HALF;
3d396eb1
AK		 2035 break;
2036 case 1:
3176ff3e 2037 adapter->link_duplex = DUPLEX_FULL;
3d396eb1
AK		 2038 break;
2039 default:
3176ff3e 2040 adapter->link_duplex = -1;
3d396eb1
AK		 2041 break;
2042 }
80922fbc 2043 if (adapter->phy_read
24a7a455 2044 && adapter->phy_read(adapter,
3d396eb1 2045 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
ed25ffa1 2046 &autoneg) != 0)
3176ff3e 2047 adapter->link_autoneg = autoneg;
3d396eb1
AK		 2048 } else
2049 goto link_down;
2050 } else {
2051 link_down:
c7860a2a 2052 adapter->link_speed = 0;
3176ff3e 2053 adapter->link_duplex = -1;
3d396eb1
AK		 2054 }
2055 }
2056}
2057
0b72e659
DP		 2058int
2059netxen_nic_wol_supported(struct netxen_adapter *adapter)
2060{
2061 u32 wol_cfg;
2062
2063 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
2064 return 0;
2065
f98a9f69 2066 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
0b72e659 2067 if (wol_cfg & (1UL << adapter->portnum)) {
f98a9f69 2068 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
0b72e659
DP		 2069 if (wol_cfg & (1 << adapter->portnum))
2070 return 1;
2071 }
2072
2073 return 0;
2074}
Linux kernel - Deliverables
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