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netxen: fix endianness in firmware commands
[deliverable/linux.git] / drivers / net / netxen / netxen_nic_hw.c
CommitLineData
3d396eb1
AK		 1/*
2 * Copyright (C) 2003 - 2006 NetXen, Inc.
3 * All rights reserved.
80922fbc 4 *
3d396eb1
AK		 5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
cb8011ad 9 *
3d396eb1
AK		 10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
cb8011ad 14 *
3d396eb1
AK		 15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
80922fbc 19 *
3d396eb1
AK		 20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
80922fbc 22 *
3d396eb1
AK		 23 * Contact Information:
24 * info@netxen.com
25 * NetXen,
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
28 *
29 *
30 * Source file for NIC routines to access the Phantom hardware
31 *
32 */
33
34#include "netxen_nic.h"
35#include "netxen_nic_hw.h"
36#include "netxen_nic_phan_reg.h"
37
3176ff3e 38
c9bdd4b5
ACM		 39#include <net/ip.h>
40
3ce06a32
DP		 41#define MASK(n) ((1ULL<<(n))-1)
42#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
43#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
44#define MS_WIN(addr) (addr & 0x0ffc0000)
45
46#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
47
48#define CRB_BLK(off) ((off >> 20) & 0x3f)
49#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
50#define CRB_WINDOW_2M (0x130060)
51#define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
52#define CRB_INDIRECT_2M (0x1e0000UL)
53
54#define CRB_WIN_LOCK_TIMEOUT 100000000
55static crb_128M_2M_block_map_t crb_128M_2M_map[64] = {
56 {{{0, 0, 0, 0} } }, /* 0: PCI */
57 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
58 {1, 0x0110000, 0x0120000, 0x130000},
59 {1, 0x0120000, 0x0122000, 0x124000},
60 {1, 0x0130000, 0x0132000, 0x126000},
61 {1, 0x0140000, 0x0142000, 0x128000},
62 {1, 0x0150000, 0x0152000, 0x12a000},
63 {1, 0x0160000, 0x0170000, 0x110000},
64 {1, 0x0170000, 0x0172000, 0x12e000},
65 {0, 0x0000000, 0x0000000, 0x000000},
66 {0, 0x0000000, 0x0000000, 0x000000},
67 {0, 0x0000000, 0x0000000, 0x000000},
68 {0, 0x0000000, 0x0000000, 0x000000},
69 {0, 0x0000000, 0x0000000, 0x000000},
70 {0, 0x0000000, 0x0000000, 0x000000},
71 {1, 0x01e0000, 0x01e0800, 0x122000},
72 {0, 0x0000000, 0x0000000, 0x000000} } },
73 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
74 {{{0, 0, 0, 0} } }, /* 3: */
75 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
76 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
77 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
78 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
79 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
80 {0, 0x0000000, 0x0000000, 0x000000},
81 {0, 0x0000000, 0x0000000, 0x000000},
82 {0, 0x0000000, 0x0000000, 0x000000},
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {0, 0x0000000, 0x0000000, 0x000000},
89 {0, 0x0000000, 0x0000000, 0x000000},
90 {0, 0x0000000, 0x0000000, 0x000000},
91 {0, 0x0000000, 0x0000000, 0x000000},
92 {0, 0x0000000, 0x0000000, 0x000000},
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {1, 0x08f0000, 0x08f2000, 0x172000} } },
95 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {0, 0x0000000, 0x0000000, 0x000000},
108 {0, 0x0000000, 0x0000000, 0x000000},
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {1, 0x09f0000, 0x09f2000, 0x176000} } },
111 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
127 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
143 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
144 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
145 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
146 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
147 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
148 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
149 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
150 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
151 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
152 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
153 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
154 {{{0, 0, 0, 0} } }, /* 23: */
155 {{{0, 0, 0, 0} } }, /* 24: */
156 {{{0, 0, 0, 0} } }, /* 25: */
157 {{{0, 0, 0, 0} } }, /* 26: */
158 {{{0, 0, 0, 0} } }, /* 27: */
159 {{{0, 0, 0, 0} } }, /* 28: */
160 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
161 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
162 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
163 {{{0} } }, /* 32: PCI */
164 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
165 {1, 0x2110000, 0x2120000, 0x130000},
166 {1, 0x2120000, 0x2122000, 0x124000},
167 {1, 0x2130000, 0x2132000, 0x126000},
168 {1, 0x2140000, 0x2142000, 0x128000},
169 {1, 0x2150000, 0x2152000, 0x12a000},
170 {1, 0x2160000, 0x2170000, 0x110000},
171 {1, 0x2170000, 0x2172000, 0x12e000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000} } },
180 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
181 {{{0} } }, /* 35: */
182 {{{0} } }, /* 36: */
183 {{{0} } }, /* 37: */
184 {{{0} } }, /* 38: */
185 {{{0} } }, /* 39: */
186 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
187 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
188 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
189 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
190 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
191 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
192 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
193 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
194 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
195 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
196 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
197 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
198 {{{0} } }, /* 52: */
199 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
200 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
201 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
202 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
203 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
204 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
205 {{{0} } }, /* 59: I2C0 */
206 {{{0} } }, /* 60: I2C1 */
207 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
208 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
209 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
210};
211
212/*
213 * top 12 bits of crb internal address (hub, agent)
214 */
215static unsigned crb_hub_agt[64] =
216{
217 0,
218 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
219 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
220 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
221 0,
222 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
223 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
224 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
225 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
226 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
227 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
228 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
229 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
230 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
231 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
232 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
233 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
234 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
235 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
236 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
237 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
238 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
239 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
240 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
241 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
242 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
243 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
244 0,
245 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
246 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
247 0,
248 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
249 0,
250 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
251 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
252 0,
253 0,
254 0,
255 0,
256 0,
257 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
258 0,
259 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
260 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
261 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
262 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
263 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
264 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
265 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
266 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
267 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
268 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
269 0,
270 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
271 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
272 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
273 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
274 0,
275 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
276 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
277 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
278 0,
279 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
280 0,
281};
282
3d396eb1
AK		 283/* PCI Windowing for DDR regions. */
284
285#define ADDR_IN_RANGE(addr, low, high) \
286 (((addr) <= (high)) && ((addr) >= (low)))
287
3ce06a32 288#define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
3d396eb1 289
cb8011ad
AK		 290#define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL
291#define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL
292#define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL
293#define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL
294
295#define NETXEN_NIC_WINDOW_MARGIN 0x100000
296
3d396eb1
AK		 297int netxen_nic_set_mac(struct net_device *netdev, void *p)
298{
3176ff3e 299 struct netxen_adapter *adapter = netdev_priv(netdev);
3d396eb1
AK		 300 struct sockaddr *addr = p;
301
302 if (netif_running(netdev))
303 return -EBUSY;
304
305 if (!is_valid_ether_addr(addr->sa_data))
306 return -EADDRNOTAVAIL;
307
3d396eb1
AK		 308 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
309
c9fc891f
DP		 310 /* For P3, MAC addr is not set in NIU */
311 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
312 if (adapter->macaddr_set)
313 adapter->macaddr_set(adapter, addr->sa_data);
3d396eb1
AK		 314
315 return 0;
316}
317
623621b0
DP		 318#define NETXEN_UNICAST_ADDR(port, index) \
319 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
320#define NETXEN_MCAST_ADDR(port, index) \
321 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
322#define MAC_HI(addr) \
323 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
324#define MAC_LO(addr) \
325 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
326
327static int
328netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
329{
330 u32 val = 0;
331 u16 port = adapter->physical_port;
332 u8 *addr = adapter->netdev->dev_addr;
333
334 if (adapter->mc_enabled)
335 return 0;
336
3ce06a32 337 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
623621b0 338 val |= (1UL << (28+port));
3ce06a32 339 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
623621b0
DP		 340
341 /* add broadcast addr to filter */
342 val = 0xffffff;
343 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
344 netxen_crb_writelit_adapter(adapter,
345 NETXEN_UNICAST_ADDR(port, 0)+4, val);
346
347 /* add station addr to filter */
348 val = MAC_HI(addr);
349 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
350 val = MAC_LO(addr);
351 netxen_crb_writelit_adapter(adapter,
352 NETXEN_UNICAST_ADDR(port, 1)+4, val);
353
354 adapter->mc_enabled = 1;
355 return 0;
356}
357
358static int
359netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
360{
361 u32 val = 0;
362 u16 port = adapter->physical_port;
363 u8 *addr = adapter->netdev->dev_addr;
364
365 if (!adapter->mc_enabled)
366 return 0;
367
3ce06a32 368 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
623621b0 369 val &= ~(1UL << (28+port));
3ce06a32 370 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
623621b0
DP		 371
372 val = MAC_HI(addr);
373 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
374 val = MAC_LO(addr);
375 netxen_crb_writelit_adapter(adapter,
376 NETXEN_UNICAST_ADDR(port, 0)+4, val);
377
378 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
379 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
380
381 adapter->mc_enabled = 0;
382 return 0;
383}
384
385static int
386netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
387 int index, u8 *addr)
388{
389 u32 hi = 0, lo = 0;
390 u16 port = adapter->physical_port;
391
392 lo = MAC_LO(addr);
393 hi = MAC_HI(addr);
394
395 netxen_crb_writelit_adapter(adapter,
396 NETXEN_MCAST_ADDR(port, index), hi);
397 netxen_crb_writelit_adapter(adapter,
398 NETXEN_MCAST_ADDR(port, index)+4, lo);
399
400 return 0;
401}
402
c9fc891f 403void netxen_p2_nic_set_multi(struct net_device *netdev)
3d396eb1 404{
3176ff3e 405 struct netxen_adapter *adapter = netdev_priv(netdev);
3d396eb1 406 struct dev_mc_list *mc_ptr;
623621b0
DP		 407 u8 null_addr[6];
408 int index = 0;
409
410 memset(null_addr, 0, 6);
3d396eb1 411
3d396eb1 412 if (netdev->flags & IFF_PROMISC) {
623621b0
DP		 413
414 adapter->set_promisc(adapter,
415 NETXEN_NIU_PROMISC_MODE);
416
417 /* Full promiscuous mode */
418 netxen_nic_disable_mcast_filter(adapter);
419
420 return;
421 }
422
423 if (netdev->mc_count == 0) {
424 adapter->set_promisc(adapter,
425 NETXEN_NIU_NON_PROMISC_MODE);
426 netxen_nic_disable_mcast_filter(adapter);
427 return;
428 }
429
430 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
431 if (netdev->flags & IFF_ALLMULTI ||
432 netdev->mc_count > adapter->max_mc_count) {
433 netxen_nic_disable_mcast_filter(adapter);
434 return;
3d396eb1 435 }
623621b0
DP		 436
437 netxen_nic_enable_mcast_filter(adapter);
438
439 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++)
440 netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr);
441
442 if (index != netdev->mc_count)
443 printk(KERN_WARNING "%s: %s multicast address count mismatch\n",
444 netxen_nic_driver_name, netdev->name);
445
446 /* Clear out remaining addresses */
447 for (; index < adapter->max_mc_count; index++)
448 netxen_nic_set_mcast_addr(adapter, index, null_addr);
3d396eb1
AK		 449}
450
c9fc891f
DP		 451static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
452 u8 *addr, nx_mac_list_t **add_list, nx_mac_list_t **del_list)
453{
454 nx_mac_list_t *cur, *prev;
455
456 /* if in del_list, move it to adapter->mac_list */
457 for (cur = *del_list, prev = NULL; cur;) {
458 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
459 if (prev == NULL)
460 *del_list = cur->next;
461 else
462 prev->next = cur->next;
463 cur->next = adapter->mac_list;
464 adapter->mac_list = cur;
465 return 0;
466 }
467 prev = cur;
468 cur = cur->next;
469 }
470
471 /* make sure to add each mac address only once */
472 for (cur = adapter->mac_list; cur; cur = cur->next) {
473 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
474 return 0;
475 }
476 /* not in del_list, create new entry and add to add_list */
477 cur = kmalloc(sizeof(*cur), in_atomic()? GFP_ATOMIC : GFP_KERNEL);
478 if (cur == NULL) {
479 printk(KERN_ERR "%s: cannot allocate memory. MAC filtering may"
480 "not work properly from now.\n", __func__);
481 return -1;
482 }
483
484 memcpy(cur->mac_addr, addr, ETH_ALEN);
485 cur->next = *add_list;
486 *add_list = cur;
487 return 0;
488}
489
490static int
491netxen_send_cmd_descs(struct netxen_adapter *adapter,
492 struct cmd_desc_type0 *cmd_desc_arr, int nr_elements)
493{
494 uint32_t i, producer;
495 struct netxen_cmd_buffer *pbuf;
496 struct cmd_desc_type0 *cmd_desc;
497
498 if (nr_elements > MAX_PENDING_DESC_BLOCK_SIZE || nr_elements == 0) {
499 printk(KERN_WARNING "%s: Too many command descriptors in a "
500 "request\n", __func__);
501 return -EINVAL;
502 }
503
504 i = 0;
505
506 producer = adapter->cmd_producer;
507 do {
508 cmd_desc = &cmd_desc_arr[i];
509
510 pbuf = &adapter->cmd_buf_arr[producer];
511 pbuf->mss = 0;
512 pbuf->total_length = 0;
513 pbuf->skb = NULL;
514 pbuf->cmd = 0;
515 pbuf->frag_count = 0;
516 pbuf->port = 0;
517
518 /* adapter->ahw.cmd_desc_head[producer] = *cmd_desc; */
519 memcpy(&adapter->ahw.cmd_desc_head[producer],
520 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
521
522 producer = get_next_index(producer,
523 adapter->max_tx_desc_count);
524 i++;
525
526 } while (i != nr_elements);
527
528 adapter->cmd_producer = producer;
529
530 /* write producer index to start the xmit */
531
532 netxen_nic_update_cmd_producer(adapter, adapter->cmd_producer);
533
534 return 0;
535}
536
c9fc891f
DP		 537static int nx_p3_sre_macaddr_change(struct net_device *dev,
538 u8 *addr, unsigned op)
539{
4cf1653a 540 struct netxen_adapter *adapter = netdev_priv(dev);
c9fc891f 541 nx_nic_req_t req;
2edbb454
DP		 542 nx_mac_req_t *mac_req;
543 u64 word;
c9fc891f
DP		 544 int rv;
545
546 memset(&req, 0, sizeof(nx_nic_req_t));
2edbb454
DP		 547 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
548
549 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16);
550 req.req_hdr = cpu_to_le64(word);
551
552 mac_req = (nx_mac_req_t *)&req.words[0];
553 mac_req->op = op;
554 memcpy(mac_req->mac_addr, addr, 6);
c9fc891f
DP		 555
556 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
557 if (rv != 0) {
558 printk(KERN_ERR "ERROR. Could not send mac update\n");
559 return rv;
560 }
561
562 return 0;
563}
564
565void netxen_p3_nic_set_multi(struct net_device *netdev)
566{
567 struct netxen_adapter *adapter = netdev_priv(netdev);
568 nx_mac_list_t *cur, *next, *del_list, *add_list = NULL;
569 struct dev_mc_list *mc_ptr;
570 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
9ad27643 571 u32 mode = VPORT_MISS_MODE_DROP;
c9fc891f
DP		 572
573 del_list = adapter->mac_list;
574 adapter->mac_list = NULL;
575
576 nx_p3_nic_add_mac(adapter, netdev->dev_addr, &add_list, &del_list);
9ad27643
DP		 577 nx_p3_nic_add_mac(adapter, bcast_addr, &add_list, &del_list);
578
579 if (netdev->flags & IFF_PROMISC) {
580 mode = VPORT_MISS_MODE_ACCEPT_ALL;
581 goto send_fw_cmd;
582 }
583
584 if ((netdev->flags & IFF_ALLMULTI) ||
585 (netdev->mc_count > adapter->max_mc_count)) {
586 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
587 goto send_fw_cmd;
588 }
589
c9fc891f 590 if (netdev->mc_count > 0) {
c9fc891f
DP		 591 for (mc_ptr = netdev->mc_list; mc_ptr;
592 mc_ptr = mc_ptr->next) {
593 nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr,
594 &add_list, &del_list);
595 }
596 }
9ad27643
DP		 597
598send_fw_cmd:
599 adapter->set_promisc(adapter, mode);
c9fc891f
DP		 600 for (cur = del_list; cur;) {
601 nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_DEL);
602 next = cur->next;
603 kfree(cur);
604 cur = next;
605 }
606 for (cur = add_list; cur;) {
607 nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_ADD);
608 next = cur->next;
609 cur->next = adapter->mac_list;
610 adapter->mac_list = cur;
611 cur = next;
612 }
613}
614
9ad27643
DP		 615int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
616{
617 nx_nic_req_t req;
2edbb454 618 u64 word;
9ad27643
DP		 619
620 memset(&req, 0, sizeof(nx_nic_req_t));
621
2edbb454
DP		 622 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
623
624 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
625 ((u64)adapter->portnum << 16);
626 req.req_hdr = cpu_to_le64(word);
627
9ad27643
DP		 628 req.words[0] = cpu_to_le64(mode);
629
630 return netxen_send_cmd_descs(adapter,
631 (struct cmd_desc_type0 *)&req, 1);
632}
633
cd1f8160
DP		 634#define NETXEN_CONFIG_INTR_COALESCE 3
635
636/*
637 * Send the interrupt coalescing parameter set by ethtool to the card.
638 */
639int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
640{
641 nx_nic_req_t req;
2edbb454 642 u64 word;
cd1f8160
DP		 643 int rv;
644
645 memset(&req, 0, sizeof(nx_nic_req_t));
646
2edbb454
DP		 647 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
648
649 word = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
650 req.req_hdr = cpu_to_le64(word);
cd1f8160
DP		 651
652 memcpy(&req.words[0], &adapter->coal, sizeof(adapter->coal));
653
654 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
655 if (rv != 0) {
656 printk(KERN_ERR "ERROR. Could not send "
657 "interrupt coalescing parameters\n");
658 }
659
660 return rv;
661}
662
3d396eb1
AK		 663/*
664 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
665 * @returns 0 on success, negative on failure
666 */
c9fc891f
DP		 667
668#define MTU_FUDGE_FACTOR 100
669
3d396eb1
AK		 670int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
671{
3176ff3e 672 struct netxen_adapter *adapter = netdev_priv(netdev);
c9fc891f 673 int max_mtu;
9ad27643 674 int rc = 0;
3d396eb1 675
c9fc891f
DP		 676 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
677 max_mtu = P3_MAX_MTU;
678 else
679 max_mtu = P2_MAX_MTU;
680
681 if (mtu > max_mtu) {
682 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
683 netdev->name, max_mtu);
3d396eb1
AK		 684 return -EINVAL;
685 }
686
80922fbc 687 if (adapter->set_mtu)
9ad27643 688 rc = adapter->set_mtu(adapter, mtu);
3d396eb1 689
9ad27643
DP		 690 if (!rc)
691 netdev->mtu = mtu;
c9fc891f 692
9ad27643 693 return rc;
3d396eb1
AK		 694}
695
3d396eb1
AK		 696int netxen_is_flash_supported(struct netxen_adapter *adapter)
697{
698 const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 };
699 int addr, val01, val02, i, j;
700
701 /* if the flash size less than 4Mb, make huge war cry and die */
702 for (j = 1; j < 4; j++) {
cb8011ad 703 addr = j * NETXEN_NIC_WINDOW_MARGIN;
ff8ac609 704 for (i = 0; i < ARRAY_SIZE(locs); i++) {
3d396eb1
AK		 705 if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0
706 && netxen_rom_fast_read(adapter, (addr + locs[i]),
707 &val02) == 0) {
708 if (val01 == val02)
709 return -1;
710 } else
711 return -1;
712 }
713 }
714
715 return 0;
716}
717
718static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
f305f789 719 int size, __le32 * buf)
3d396eb1
AK		 720{
721 int i, addr;
f305f789
AV		 722 __le32 *ptr32;
723 u32 v;
3d396eb1
AK		 724
725 addr = base;
726 ptr32 = buf;
727 for (i = 0; i < size / sizeof(u32); i++) {
f305f789 728 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
3d396eb1 729 return -1;
f305f789 730 *ptr32 = cpu_to_le32(v);
3d396eb1
AK		 731 ptr32++;
732 addr += sizeof(u32);
733 }
734 if ((char *)buf + size > (char *)ptr32) {
f305f789
AV		 735 __le32 local;
736 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
3d396eb1 737 return -1;
f305f789 738 local = cpu_to_le32(v);
3d396eb1
AK		 739 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
740 }
741
742 return 0;
743}
744
9dc28efe 745int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
3d396eb1 746{
9dc28efe
DP		 747 __le32 *pmac = (__le32 *) mac;
748 u32 offset;
3d396eb1 749
9dc28efe
DP		 750 offset = NETXEN_USER_START +
751 offsetof(struct netxen_new_user_info, mac_addr) +
752 adapter->portnum * sizeof(u64);
753
754 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
3d396eb1 755 return -1;
9dc28efe 756
f305f789 757 if (*mac == cpu_to_le64(~0ULL)) {
9dc28efe
DP		 758
759 offset = NETXEN_USER_START_OLD +
760 offsetof(struct netxen_user_old_info, mac_addr) +
761 adapter->portnum * sizeof(u64);
762
3d396eb1 763 if (netxen_get_flash_block(adapter,
9dc28efe 764 offset, sizeof(u64), pmac) == -1)
3d396eb1 765 return -1;
9dc28efe 766
f305f789 767 if (*mac == cpu_to_le64(~0ULL))
3d396eb1
AK		 768 return -1;
769 }
770 return 0;
771}
772
9dc28efe
DP		 773int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
774{
775 uint32_t crbaddr, mac_hi, mac_lo;
776 int pci_func = adapter->ahw.pci_func;
777
778 crbaddr = CRB_MAC_BLOCK_START +
779 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
780
781 adapter->hw_read_wx(adapter, crbaddr, &mac_lo, 4);
782 adapter->hw_read_wx(adapter, crbaddr+4, &mac_hi, 4);
783
9dc28efe 784 if (pci_func & 1)
2edbb454 785 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
9dc28efe 786 else
2edbb454 787 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
9dc28efe
DP		 788
789 return 0;
790}
791
3ce06a32
DP		 792#define CRB_WIN_LOCK_TIMEOUT 100000000
793
794static int crb_win_lock(struct netxen_adapter *adapter)
795{
796 int done = 0, timeout = 0;
797
798 while (!done) {
799 /* acquire semaphore3 from PCI HW block */
800 adapter->hw_read_wx(adapter,
801 NETXEN_PCIE_REG(PCIE_SEM7_LOCK), &done, 4);
802 if (done == 1)
803 break;
804 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
805 return -1;
806 timeout++;
807 udelay(1);
808 }
809 netxen_crb_writelit_adapter(adapter,
810 NETXEN_CRB_WIN_LOCK_ID, adapter->portnum);
811 return 0;
812}
813
814static void crb_win_unlock(struct netxen_adapter *adapter)
815{
816 int val;
817
818 adapter->hw_read_wx(adapter,
819 NETXEN_PCIE_REG(PCIE_SEM7_UNLOCK), &val, 4);
820}
821
3d396eb1
AK		 822/*
823 * Changes the CRB window to the specified window.
824 */
3ce06a32
DP		 825void
826netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw)
3d396eb1
AK		 827{
828 void __iomem *offset;
829 u32 tmp;
830 int count = 0;
e4c93c81 831 uint8_t func = adapter->ahw.pci_func;
3d396eb1
AK		 832
833 if (adapter->curr_window == wndw)
834 return;
3d396eb1
AK		 835 /*
836 * Move the CRB window.
837 * We need to write to the "direct access" region of PCI
838 * to avoid a race condition where the window register has
839 * not been successfully written across CRB before the target
840 * register address is received by PCI. The direct region bypasses
841 * the CRB bus.
842 */
e4c93c81
DP		 843 offset = PCI_OFFSET_SECOND_RANGE(adapter,
844 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
3d396eb1
AK		 845
846 if (wndw & 0x1)
847 wndw = NETXEN_WINDOW_ONE;
848
849 writel(wndw, offset);
850
851 /* MUST make sure window is set before we forge on... */
852 while ((tmp = readl(offset)) != wndw) {
853 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
854 "registered properly: 0x%08x.\n",
3ce06a32 855 netxen_nic_driver_name, __func__, tmp);
3d396eb1
AK		 856 mdelay(1);
857 if (count >= 10)
858 break;
859 count++;
860 }
861
6c80b18d
MT		 862 if (wndw == NETXEN_WINDOW_ONE)
863 adapter->curr_window = 1;
864 else
865 adapter->curr_window = 0;
3d396eb1
AK		 866}
867
3ce06a32
DP		 868/*
869 * Return -1 if off is not valid,
870 * 1 if window access is needed. 'off' is set to offset from
871 * CRB space in 128M pci map
872 * 0 if no window access is needed. 'off' is set to 2M addr
873 * In: 'off' is offset from base in 128M pci map
874 */
875static int
876netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter,
877 ulong *off, int len)
878{
879 unsigned long end = *off + len;
880 crb_128M_2M_sub_block_map_t *m;
881
882
883 if (*off >= NETXEN_CRB_MAX)
884 return -1;
885
886 if (*off >= NETXEN_PCI_CAMQM && (end <= NETXEN_PCI_CAMQM_2M_END)) {
887 *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE +
888 (ulong)adapter->ahw.pci_base0;
889 return 0;
890 }
891
892 if (*off < NETXEN_PCI_CRBSPACE)
893 return -1;
894
895 *off -= NETXEN_PCI_CRBSPACE;
896 end = *off + len;
897
898 /*
899 * Try direct map
900 */
901 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
902
903 if (m->valid && (m->start_128M <= *off) && (m->end_128M >= end)) {
904 *off = *off + m->start_2M - m->start_128M +
905 (ulong)adapter->ahw.pci_base0;
906 return 0;
907 }
908
909 /*
910 * Not in direct map, use crb window
911 */
912 return 1;
913}
914
915/*
916 * In: 'off' is offset from CRB space in 128M pci map
917 * Out: 'off' is 2M pci map addr
918 * side effect: lock crb window
919 */
920static void
921netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off)
922{
923 u32 win_read;
924
925 adapter->crb_win = CRB_HI(*off);
926 writel(adapter->crb_win, (void *)(CRB_WINDOW_2M +
927 adapter->ahw.pci_base0));
928 /*
929 * Read back value to make sure write has gone through before trying
930 * to use it.
931 */
932 win_read = readl((void *)(CRB_WINDOW_2M + adapter->ahw.pci_base0));
933 if (win_read != adapter->crb_win) {
934 printk(KERN_ERR "%s: Written crbwin (0x%x) != "
935 "Read crbwin (0x%x), off=0x%lx\n",
936 __func__, adapter->crb_win, win_read, *off);
937 }
938 *off = (*off & MASK(16)) + CRB_INDIRECT_2M +
939 (ulong)adapter->ahw.pci_base0;
940}
941
96acb6eb 942int netxen_load_firmware(struct netxen_adapter *adapter)
3d396eb1
AK		 943{
944 int i;
e0e20a1a 945 u32 data, size = 0;
2956640d
DP		 946 u32 flashaddr = NETXEN_BOOTLD_START, memaddr = NETXEN_BOOTLD_START;
947
948 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START)/4;
3d396eb1 949
2956640d
DP		 950 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
951 adapter->pci_write_normalize(adapter,
3ce06a32 952 NETXEN_ROMUSB_GLB_CAS_RST, 1);
3d396eb1
AK		 953
954 for (i = 0; i < size; i++) {
96acb6eb
DP		 955 if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0)
956 return -EIO;
957
3ce06a32 958 adapter->pci_mem_write(adapter, memaddr, &data, 4);
3d396eb1
AK		 959 flashaddr += 4;
960 memaddr += 4;
3ce06a32 961 cond_resched();
3d396eb1 962 }
2956640d
DP		 963 msleep(1);
964
965 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
966 adapter->pci_write_normalize(adapter,
967 NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
968 else {
969 adapter->pci_write_normalize(adapter,
3ce06a32 970 NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
2956640d 971 adapter->pci_write_normalize(adapter,
3ce06a32 972 NETXEN_ROMUSB_GLB_CAS_RST, 0);
2956640d 973 }
3d396eb1 974
96acb6eb 975 return 0;
3d396eb1
AK		 976}
977
978int
3ce06a32
DP		 979netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
980 ulong off, void *data, int len)
3d396eb1
AK		 981{
982 void __iomem *addr;
983
984 if (ADDR_IN_WINDOW1(off)) {
985 addr = NETXEN_CRB_NORMALIZE(adapter, off);
986 } else { /* Window 0 */
cb8011ad 987 addr = pci_base_offset(adapter, off);
3ce06a32 988 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
3d396eb1
AK		 989 }
990
991 DPRINTK(INFO, "writing to base %lx offset %llx addr %p"
992 " data %llx len %d\n",
cb8011ad 993 pci_base(adapter, off), off, addr,
3d396eb1 994 *(unsigned long long *)data, len);
cb8011ad 995 if (!addr) {
3ce06a32 996 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
cb8011ad
AK		 997 return 1;
998 }
999
3d396eb1
AK		 1000 switch (len) {
1001 case 1:
1002 writeb(*(u8 *) data, addr);
1003 break;
1004 case 2:
1005 writew(*(u16 *) data, addr);
1006 break;
1007 case 4:
1008 writel(*(u32 *) data, addr);
1009 break;
1010 case 8:
1011 writeq(*(u64 *) data, addr);
1012 break;
1013 default:
1014 DPRINTK(INFO,
1015 "writing data %lx to offset %llx, num words=%d\n",
1016 *(unsigned long *)data, off, (len >> 3));
1017
1018 netxen_nic_hw_block_write64((u64 __iomem *) data, addr,
1019 (len >> 3));
1020 break;
1021 }
1022 if (!ADDR_IN_WINDOW1(off))
3ce06a32 1023 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
3d396eb1
AK		 1024
1025 return 0;
1026}
1027
1028int
3ce06a32
DP		 1029netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
1030 ulong off, void *data, int len)
3d396eb1
AK		 1031{
1032 void __iomem *addr;
1033
1034 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1035 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1036 } else { /* Window 0 */
cb8011ad 1037 addr = pci_base_offset(adapter, off);
3ce06a32 1038 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
3d396eb1
AK		 1039 }
1040
1041 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
cb8011ad
AK		 1042 pci_base(adapter, off), off, addr);
1043 if (!addr) {
3ce06a32 1044 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
cb8011ad
AK		 1045 return 1;
1046 }
3d396eb1
AK		 1047 switch (len) {
1048 case 1:
1049 *(u8 *) data = readb(addr);
1050 break;
1051 case 2:
1052 *(u16 *) data = readw(addr);
1053 break;
1054 case 4:
1055 *(u32 *) data = readl(addr);
1056 break;
1057 case 8:
1058 *(u64 *) data = readq(addr);
1059 break;
1060 default:
1061 netxen_nic_hw_block_read64((u64 __iomem *) data, addr,
1062 (len >> 3));
1063 break;
1064 }
1065 DPRINTK(INFO, "read %lx\n", *(unsigned long *)data);
1066
1067 if (!ADDR_IN_WINDOW1(off))
3ce06a32 1068 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
3d396eb1
AK		 1069
1070 return 0;
1071}
1072
3ce06a32
DP		 1073int
1074netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1075 ulong off, void *data, int len)
1076{
1077 unsigned long flags = 0;
1078 int rv;
3d396eb1 1079
3ce06a32 1080 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
3d396eb1 1081
3ce06a32
DP		 1082 if (rv == -1) {
1083 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1084 __func__, off);
1085 dump_stack();
1086 return -1;
1087 }
1088
1089 if (rv == 1) {
1090 write_lock_irqsave(&adapter->adapter_lock, flags);
1091 crb_win_lock(adapter);
1092 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1093 }
1094
1095 DPRINTK(1, INFO, "write data %lx to offset %llx, len=%d\n",
1096 *(unsigned long *)data, off, len);
1097
1098 switch (len) {
1099 case 1:
1100 writeb(*(uint8_t *)data, (void *)off);
1101 break;
1102 case 2:
1103 writew(*(uint16_t *)data, (void *)off);
1104 break;
1105 case 4:
1106 writel(*(uint32_t *)data, (void *)off);
1107 break;
1108 case 8:
1109 writeq(*(uint64_t *)data, (void *)off);
1110 break;
1111 default:
1112 DPRINTK(1, INFO,
1113 "writing data %lx to offset %llx, num words=%d\n",
1114 *(unsigned long *)data, off, (len>>3));
1115 break;
1116 }
1117 if (rv == 1) {
1118 crb_win_unlock(adapter);
1119 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1120 }
1121
1122 return 0;
3d396eb1
AK		 1123}
1124
3ce06a32
DP		 1125int
1126netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
1127 ulong off, void *data, int len)
1128{
1129 unsigned long flags = 0;
1130 int rv;
3d396eb1 1131
3ce06a32
DP		 1132 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
1133
1134 if (rv == -1) {
1135 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1136 __func__, off);
1137 dump_stack();
1138 return -1;
1139 }
1140
1141 if (rv == 1) {
1142 write_lock_irqsave(&adapter->adapter_lock, flags);
1143 crb_win_lock(adapter);
1144 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1145 }
1146
1147 DPRINTK(1, INFO, "read from offset %lx, len=%d\n", off, len);
1148
1149 switch (len) {
1150 case 1:
1151 *(uint8_t *)data = readb((void *)off);
1152 break;
1153 case 2:
1154 *(uint16_t *)data = readw((void *)off);
1155 break;
1156 case 4:
1157 *(uint32_t *)data = readl((void *)off);
1158 break;
1159 case 8:
1160 *(uint64_t *)data = readq((void *)off);
1161 break;
1162 default:
1163 break;
1164 }
1165
1166 DPRINTK(1, INFO, "read %lx\n", *(unsigned long *)data);
3d396eb1 1167
3ce06a32
DP		 1168 if (rv == 1) {
1169 crb_win_unlock(adapter);
1170 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1171 }
1172
1173 return 0;
1174}
1175
1176void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
1177{
1178 adapter->hw_write_wx(adapter, off, &val, 4);
1179}
1180
1181int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
1182{
1183 int val;
1184 adapter->hw_read_wx(adapter, off, &val, 4);
3d396eb1
AK		 1185 return val;
1186}
1187
1188/* Change the window to 0, write and change back to window 1. */
1189void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
1190{
3ce06a32 1191 adapter->hw_write_wx(adapter, index, &value, 4);
3d396eb1
AK		 1192}
1193
1194/* Change the window to 0, read and change back to window 1. */
3ce06a32 1195void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value)
3d396eb1 1196{
3ce06a32
DP		 1197 adapter->hw_read_wx(adapter, index, value, 4);
1198}
3d396eb1 1199
3ce06a32
DP		 1200void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value)
1201{
1202 adapter->hw_write_wx(adapter, index, &value, 4);
1203}
1204
1205void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value)
1206{
1207 adapter->hw_read_wx(adapter, index, value, 4);
1208}
1209
1210/*
1211 * check memory access boundary.
1212 * used by test agent. support ddr access only for now
1213 */
1214static unsigned long
1215netxen_nic_pci_mem_bound_check(struct netxen_adapter *adapter,
1216 unsigned long long addr, int size)
1217{
1218 if (!ADDR_IN_RANGE(addr,
1219 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1220 !ADDR_IN_RANGE(addr+size-1,
1221 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1222 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
1223 return 0;
1224 }
3d396eb1 1225
3ce06a32 1226 return 1;
3d396eb1
AK		 1227}
1228
4790654c 1229static int netxen_pci_set_window_warning_count;
3d396eb1 1230
3ce06a32
DP		 1231unsigned long
1232netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1233 unsigned long long addr)
3d396eb1 1234{
e4c93c81 1235 void __iomem *offset;
3d396eb1 1236 int window;
3ce06a32 1237 unsigned long long qdr_max;
e4c93c81 1238 uint8_t func = adapter->ahw.pci_func;
3d396eb1 1239
3ce06a32
DP		 1240 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1241 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1242 } else {
1243 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1244 }
1245
3d396eb1
AK		 1246 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1247 /* DDR network side */
1248 addr -= NETXEN_ADDR_DDR_NET;
1249 window = (addr >> 25) & 0x3ff;
3ce06a32
DP		 1250 if (adapter->ahw.ddr_mn_window != window) {
1251 adapter->ahw.ddr_mn_window = window;
e4c93c81
DP		 1252 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1253 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func)));
1254 writel(window, offset);
3d396eb1 1255 /* MUST make sure window is set before we forge on... */
e4c93c81 1256 readl(offset);
3d396eb1 1257 }
cb8011ad 1258 addr -= (window * NETXEN_WINDOW_ONE);
3d396eb1
AK		 1259 addr += NETXEN_PCI_DDR_NET;
1260 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1261 addr -= NETXEN_ADDR_OCM0;
1262 addr += NETXEN_PCI_OCM0;
1263 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1264 addr -= NETXEN_ADDR_OCM1;
1265 addr += NETXEN_PCI_OCM1;
3ce06a32 1266 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
3d396eb1
AK		 1267 /* QDR network side */
1268 addr -= NETXEN_ADDR_QDR_NET;
1269 window = (addr >> 22) & 0x3f;
3ce06a32
DP		 1270 if (adapter->ahw.qdr_sn_window != window) {
1271 adapter->ahw.qdr_sn_window = window;
e4c93c81
DP		 1272 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1273 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func)));
1274 writel((window << 22), offset);
3d396eb1 1275 /* MUST make sure window is set before we forge on... */
e4c93c81 1276 readl(offset);
3d396eb1
AK		 1277 }
1278 addr -= (window * 0x400000);
1279 addr += NETXEN_PCI_QDR_NET;
1280 } else {
1281 /*
1282 * peg gdb frequently accesses memory that doesn't exist,
1283 * this limits the chit chat so debugging isn't slowed down.
1284 */
1285 if ((netxen_pci_set_window_warning_count++ < 8)
1286 || (netxen_pci_set_window_warning_count % 64 == 0))
1287 printk("%s: Warning:netxen_nic_pci_set_window()"
1288 " Unknown address range!\n",
1289 netxen_nic_driver_name);
3ce06a32
DP		 1290 addr = -1UL;
1291 }
1292 return addr;
1293}
1294
1295/*
1296 * Note : only 32-bit writes!
1297 */
1298int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1299 u64 off, u32 data)
1300{
1301 writel(data, (void __iomem *)(PCI_OFFSET_SECOND_RANGE(adapter, off)));
1302 return 0;
1303}
1304
1305u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off)
1306{
1307 return readl((void __iomem *)(pci_base_offset(adapter, off)));
1308}
1309
1310void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1311 u64 off, u32 data)
1312{
1313 writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
1314}
1315
1316u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off)
1317{
1318 return readl(NETXEN_CRB_NORMALIZE(adapter, off));
1319}
1320
1321unsigned long
1322netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1323 unsigned long long addr)
1324{
1325 int window;
1326 u32 win_read;
3d396eb1 1327
3ce06a32
DP		 1328 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1329 /* DDR network side */
1330 window = MN_WIN(addr);
1331 adapter->ahw.ddr_mn_window = window;
1332 adapter->hw_write_wx(adapter,
1333 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1334 &window, 4);
1335 adapter->hw_read_wx(adapter,
1336 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1337 &win_read, 4);
1338 if ((win_read << 17) != window) {
1339 printk(KERN_INFO "Written MNwin (0x%x) != "
1340 "Read MNwin (0x%x)\n", window, win_read);
1341 }
1342 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_DDR_NET;
1343 } else if (ADDR_IN_RANGE(addr,
1344 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1345 if ((addr & 0x00ff800) == 0xff800) {
1346 printk("%s: QM access not handled.\n", __func__);
1347 addr = -1UL;
1348 }
1349
1350 window = OCM_WIN(addr);
1351 adapter->ahw.ddr_mn_window = window;
1352 adapter->hw_write_wx(adapter,
1353 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1354 &window, 4);
1355 adapter->hw_read_wx(adapter,
1356 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1357 &win_read, 4);
1358 if ((win_read >> 7) != window) {
1359 printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
1360 "Read OCMwin (0x%x)\n",
1361 __func__, window, win_read);
1362 }
1363 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_OCM0_2M;
1364
1365 } else if (ADDR_IN_RANGE(addr,
1366 NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P3)) {
1367 /* QDR network side */
1368 window = MS_WIN(addr);
1369 adapter->ahw.qdr_sn_window = window;
1370 adapter->hw_write_wx(adapter,
1371 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1372 &window, 4);
1373 adapter->hw_read_wx(adapter,
1374 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1375 &win_read, 4);
1376 if (win_read != window) {
1377 printk(KERN_INFO "%s: Written MSwin (0x%x) != "
1378 "Read MSwin (0x%x)\n",
1379 __func__, window, win_read);
1380 }
1381 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_QDR_NET;
1382
1383 } else {
1384 /*
1385 * peg gdb frequently accesses memory that doesn't exist,
1386 * this limits the chit chat so debugging isn't slowed down.
1387 */
1388 if ((netxen_pci_set_window_warning_count++ < 8)
1389 || (netxen_pci_set_window_warning_count%64 == 0)) {
1390 printk("%s: Warning:%s Unknown address range!\n",
1391 __func__, netxen_nic_driver_name);
1392}
1393 addr = -1UL;
3d396eb1
AK		 1394 }
1395 return addr;
1396}
1397
3ce06a32
DP		 1398static int netxen_nic_pci_is_same_window(struct netxen_adapter *adapter,
1399 unsigned long long addr)
1400{
1401 int window;
1402 unsigned long long qdr_max;
1403
1404 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1405 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1406 else
1407 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1408
1409 if (ADDR_IN_RANGE(addr,
1410 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1411 /* DDR network side */
1412 BUG(); /* MN access can not come here */
1413 } else if (ADDR_IN_RANGE(addr,
1414 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1415 return 1;
1416 } else if (ADDR_IN_RANGE(addr,
1417 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1418 return 1;
1419 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1420 /* QDR network side */
1421 window = ((addr - NETXEN_ADDR_QDR_NET) >> 22) & 0x3f;
1422 if (adapter->ahw.qdr_sn_window == window)
1423 return 1;
1424 }
1425
1426 return 0;
1427}
1428
1429static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter,
1430 u64 off, void *data, int size)
1431{
1432 unsigned long flags;
1433 void *addr;
1434 int ret = 0;
1435 u64 start;
1436 uint8_t *mem_ptr = NULL;
1437 unsigned long mem_base;
1438 unsigned long mem_page;
1439
1440 write_lock_irqsave(&adapter->adapter_lock, flags);
1441
1442 /*
1443 * If attempting to access unknown address or straddle hw windows,
1444 * do not access.
1445 */
1446 start = adapter->pci_set_window(adapter, off);
1447 if ((start == -1UL) ||
1448 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1449 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1450 printk(KERN_ERR "%s out of bound pci memory access. "
11a859e5
AM		 1451 "offset is 0x%llx\n", netxen_nic_driver_name,
1452 (unsigned long long)off);
3ce06a32
DP		 1453 return -1;
1454 }
1455
1456 addr = (void *)(pci_base_offset(adapter, start));
1457 if (!addr) {
1458 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1459 mem_base = pci_resource_start(adapter->pdev, 0);
1460 mem_page = start & PAGE_MASK;
1461 /* Map two pages whenever user tries to access addresses in two
1462 consecutive pages.
1463 */
1464 if (mem_page != ((start + size - 1) & PAGE_MASK))
1465 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
1466 else
1467 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
f8057b7f 1468 if (mem_ptr == NULL) {
3ce06a32
DP		 1469 *(uint8_t *)data = 0;
1470 return -1;
1471 }
1472 addr = mem_ptr;
1473 addr += start & (PAGE_SIZE - 1);
1474 write_lock_irqsave(&adapter->adapter_lock, flags);
1475 }
1476
1477 switch (size) {
1478 case 1:
1479 *(uint8_t *)data = readb(addr);
1480 break;
1481 case 2:
1482 *(uint16_t *)data = readw(addr);
1483 break;
1484 case 4:
1485 *(uint32_t *)data = readl(addr);
1486 break;
1487 case 8:
1488 *(uint64_t *)data = readq(addr);
1489 break;
1490 default:
1491 ret = -1;
1492 break;
1493 }
1494 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1495 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1496
1497 if (mem_ptr)
1498 iounmap(mem_ptr);
1499 return ret;
1500}
1501
1502static int
1503netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off,
1504 void *data, int size)
1505{
1506 unsigned long flags;
1507 void *addr;
1508 int ret = 0;
1509 u64 start;
1510 uint8_t *mem_ptr = NULL;
1511 unsigned long mem_base;
1512 unsigned long mem_page;
1513
1514 write_lock_irqsave(&adapter->adapter_lock, flags);
1515
1516 /*
1517 * If attempting to access unknown address or straddle hw windows,
1518 * do not access.
1519 */
1520 start = adapter->pci_set_window(adapter, off);
1521 if ((start == -1UL) ||
1522 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1523 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1524 printk(KERN_ERR "%s out of bound pci memory access. "
11a859e5
AM		 1525 "offset is 0x%llx\n", netxen_nic_driver_name,
1526 (unsigned long long)off);
3ce06a32
DP		 1527 return -1;
1528 }
1529
1530 addr = (void *)(pci_base_offset(adapter, start));
1531 if (!addr) {
1532 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1533 mem_base = pci_resource_start(adapter->pdev, 0);
1534 mem_page = start & PAGE_MASK;
1535 /* Map two pages whenever user tries to access addresses in two
1536 * consecutive pages.
1537 */
1538 if (mem_page != ((start + size - 1) & PAGE_MASK))
1539 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
1540 else
1541 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
f8057b7f 1542 if (mem_ptr == NULL)
3ce06a32
DP		 1543 return -1;
1544 addr = mem_ptr;
1545 addr += start & (PAGE_SIZE - 1);
1546 write_lock_irqsave(&adapter->adapter_lock, flags);
1547 }
1548
1549 switch (size) {
1550 case 1:
1551 writeb(*(uint8_t *)data, addr);
1552 break;
1553 case 2:
1554 writew(*(uint16_t *)data, addr);
1555 break;
1556 case 4:
1557 writel(*(uint32_t *)data, addr);
1558 break;
1559 case 8:
1560 writeq(*(uint64_t *)data, addr);
1561 break;
1562 default:
1563 ret = -1;
1564 break;
1565 }
1566 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1567 DPRINTK(1, INFO, "writing data %llx to offset %llx\n",
1568 *(unsigned long long *)data, start);
1569 if (mem_ptr)
1570 iounmap(mem_ptr);
1571 return ret;
1572}
1573
1574#define MAX_CTL_CHECK 1000
1575
1576int
1577netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1578 u64 off, void *data, int size)
1579{
1580 unsigned long flags, mem_crb;
1581 int i, j, ret = 0, loop, sz[2], off0;
1582 uint32_t temp;
1583 uint64_t off8, tmpw, word[2] = {0, 0};
1584
1585 /*
1586 * If not MN, go check for MS or invalid.
1587 */
1588 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1589 return netxen_nic_pci_mem_write_direct(adapter,
1590 off, data, size);
1591
1592 off8 = off & 0xfffffff8;
1593 off0 = off & 0x7;
1594 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1595 sz[1] = size - sz[0];
1596 loop = ((off0 + size - 1) >> 3) + 1;
1597 mem_crb = (unsigned long)pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1598
1599 if ((size != 8) || (off0 != 0)) {
1600 for (i = 0; i < loop; i++) {
1601 if (adapter->pci_mem_read(adapter,
1602 off8 + (i << 3), &word[i], 8))
1603 return -1;
1604 }
1605 }
1606
1607 switch (size) {
1608 case 1:
1609 tmpw = *((uint8_t *)data);
1610 break;
1611 case 2:
1612 tmpw = *((uint16_t *)data);
1613 break;
1614 case 4:
1615 tmpw = *((uint32_t *)data);
1616 break;
1617 case 8:
1618 default:
1619 tmpw = *((uint64_t *)data);
1620 break;
1621 }
1622 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1623 word[0] |= tmpw << (off0 * 8);
1624
1625 if (loop == 2) {
1626 word[1] &= ~(~0ULL << (sz[1] * 8));
1627 word[1] |= tmpw >> (sz[0] * 8);
1628 }
1629
1630 write_lock_irqsave(&adapter->adapter_lock, flags);
1631 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1632
1633 for (i = 0; i < loop; i++) {
1634 writel((uint32_t)(off8 + (i << 3)),
1635 (void *)(mem_crb+MIU_TEST_AGT_ADDR_LO));
1636 writel(0,
1637 (void *)(mem_crb+MIU_TEST_AGT_ADDR_HI));
1638 writel(word[i] & 0xffffffff,
1639 (void *)(mem_crb+MIU_TEST_AGT_WRDATA_LO));
1640 writel((word[i] >> 32) & 0xffffffff,
1641 (void *)(mem_crb+MIU_TEST_AGT_WRDATA_HI));
1642 writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1643 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1644 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1645 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1646
1647 for (j = 0; j < MAX_CTL_CHECK; j++) {
1648 temp = readl(
1649 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1650 if ((temp & MIU_TA_CTL_BUSY) == 0)
1651 break;
1652 }
1653
1654 if (j >= MAX_CTL_CHECK) {
1655 printk("%s: %s Fail to write through agent\n",
1656 __func__, netxen_nic_driver_name);
1657 ret = -1;
1658 break;
1659 }
1660 }
1661
1662 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1663 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1664 return ret;
1665}
1666
1667int
1668netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1669 u64 off, void *data, int size)
1670{
1671 unsigned long flags, mem_crb;
1672 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1673 uint32_t temp;
1674 uint64_t off8, val, word[2] = {0, 0};
1675
1676
1677 /*
1678 * If not MN, go check for MS or invalid.
1679 */
1680 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1681 return netxen_nic_pci_mem_read_direct(adapter, off, data, size);
1682
1683 off8 = off & 0xfffffff8;
1684 off0[0] = off & 0x7;
1685 off0[1] = 0;
1686 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1687 sz[1] = size - sz[0];
1688 loop = ((off0[0] + size - 1) >> 3) + 1;
1689 mem_crb = (unsigned long)pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1690
1691 write_lock_irqsave(&adapter->adapter_lock, flags);
1692 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1693
1694 for (i = 0; i < loop; i++) {
1695 writel((uint32_t)(off8 + (i << 3)),
1696 (void *)(mem_crb+MIU_TEST_AGT_ADDR_LO));
1697 writel(0,
1698 (void *)(mem_crb+MIU_TEST_AGT_ADDR_HI));
1699 writel(MIU_TA_CTL_ENABLE,
1700 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1701 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE,
1702 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1703
1704 for (j = 0; j < MAX_CTL_CHECK; j++) {
1705 temp = readl(
1706 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1707 if ((temp & MIU_TA_CTL_BUSY) == 0)
1708 break;
1709 }
1710
1711 if (j >= MAX_CTL_CHECK) {
1712 printk(KERN_ERR "%s: %s Fail to read through agent\n",
1713 __func__, netxen_nic_driver_name);
1714 break;
1715 }
1716
1717 start = off0[i] >> 2;
1718 end = (off0[i] + sz[i] - 1) >> 2;
1719 for (k = start; k <= end; k++) {
1720 word[i] |= ((uint64_t) readl(
1721 (void *)(mem_crb +
1722 MIU_TEST_AGT_RDDATA(k))) << (32*k));
1723 }
1724 }
1725
1726 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1727 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1728
1729 if (j >= MAX_CTL_CHECK)
1730 return -1;
1731
1732 if (sz[0] == 8) {
1733 val = word[0];
1734 } else {
1735 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1736 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1737 }
1738
1739 switch (size) {
1740 case 1:
1741 *(uint8_t *)data = val;
1742 break;
1743 case 2:
1744 *(uint16_t *)data = val;
1745 break;
1746 case 4:
1747 *(uint32_t *)data = val;
1748 break;
1749 case 8:
1750 *(uint64_t *)data = val;
1751 break;
1752 }
1753 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1754 return 0;
1755}
1756
1757int
1758netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1759 u64 off, void *data, int size)
1760{
1761 int i, j, ret = 0, loop, sz[2], off0;
1762 uint32_t temp;
1763 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1764
1765 /*
1766 * If not MN, go check for MS or invalid.
1767 */
1768 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1769 mem_crb = NETXEN_CRB_QDR_NET;
1770 else {
1771 mem_crb = NETXEN_CRB_DDR_NET;
1772 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1773 return netxen_nic_pci_mem_write_direct(adapter,
1774 off, data, size);
1775 }
1776
1777 off8 = off & 0xfffffff8;
1778 off0 = off & 0x7;
1779 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1780 sz[1] = size - sz[0];
1781 loop = ((off0 + size - 1) >> 3) + 1;
1782
1783 if ((size != 8) || (off0 != 0)) {
1784 for (i = 0; i < loop; i++) {
1785 if (adapter->pci_mem_read(adapter, off8 + (i << 3),
1786 &word[i], 8))
1787 return -1;
1788 }
1789 }
1790
1791 switch (size) {
1792 case 1:
1793 tmpw = *((uint8_t *)data);
1794 break;
1795 case 2:
1796 tmpw = *((uint16_t *)data);
1797 break;
1798 case 4:
1799 tmpw = *((uint32_t *)data);
1800 break;
1801 case 8:
1802 default:
1803 tmpw = *((uint64_t *)data);
1804 break;
1805 }
1806
1807 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1808 word[0] |= tmpw << (off0 * 8);
1809
1810 if (loop == 2) {
1811 word[1] &= ~(~0ULL << (sz[1] * 8));
1812 word[1] |= tmpw >> (sz[0] * 8);
1813 }
1814
1815 /*
1816 * don't lock here - write_wx gets the lock if each time
1817 * write_lock_irqsave(&adapter->adapter_lock, flags);
1818 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1819 */
1820
1821 for (i = 0; i < loop; i++) {
1822 temp = off8 + (i << 3);
1823 adapter->hw_write_wx(adapter,
1824 mem_crb+MIU_TEST_AGT_ADDR_LO, &temp, 4);
1825 temp = 0;
1826 adapter->hw_write_wx(adapter,
1827 mem_crb+MIU_TEST_AGT_ADDR_HI, &temp, 4);
1828 temp = word[i] & 0xffffffff;
1829 adapter->hw_write_wx(adapter,
1830 mem_crb+MIU_TEST_AGT_WRDATA_LO, &temp, 4);
1831 temp = (word[i] >> 32) & 0xffffffff;
1832 adapter->hw_write_wx(adapter,
1833 mem_crb+MIU_TEST_AGT_WRDATA_HI, &temp, 4);
1834 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1835 adapter->hw_write_wx(adapter,
1836 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1837 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1838 adapter->hw_write_wx(adapter,
1839 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1840
1841 for (j = 0; j < MAX_CTL_CHECK; j++) {
1842 adapter->hw_read_wx(adapter,
1843 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1844 if ((temp & MIU_TA_CTL_BUSY) == 0)
1845 break;
1846 }
1847
1848 if (j >= MAX_CTL_CHECK) {
1849 printk(KERN_ERR "%s: Fail to write through agent\n",
1850 netxen_nic_driver_name);
1851 ret = -1;
1852 break;
1853 }
1854 }
1855
1856 /*
1857 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1858 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1859 */
1860 return ret;
1861}
1862
1863int
1864netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1865 u64 off, void *data, int size)
1866{
1867 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1868 uint32_t temp;
1869 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1870
1871 /*
1872 * If not MN, go check for MS or invalid.
1873 */
1874
1875 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1876 mem_crb = NETXEN_CRB_QDR_NET;
1877 else {
1878 mem_crb = NETXEN_CRB_DDR_NET;
1879 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1880 return netxen_nic_pci_mem_read_direct(adapter,
1881 off, data, size);
1882 }
1883
1884 off8 = off & 0xfffffff8;
1885 off0[0] = off & 0x7;
1886 off0[1] = 0;
1887 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1888 sz[1] = size - sz[0];
1889 loop = ((off0[0] + size - 1) >> 3) + 1;
1890
1891 /*
1892 * don't lock here - write_wx gets the lock if each time
1893 * write_lock_irqsave(&adapter->adapter_lock, flags);
1894 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1895 */
1896
1897 for (i = 0; i < loop; i++) {
1898 temp = off8 + (i << 3);
1899 adapter->hw_write_wx(adapter,
1900 mem_crb + MIU_TEST_AGT_ADDR_LO, &temp, 4);
1901 temp = 0;
1902 adapter->hw_write_wx(adapter,
1903 mem_crb + MIU_TEST_AGT_ADDR_HI, &temp, 4);
1904 temp = MIU_TA_CTL_ENABLE;
1905 adapter->hw_write_wx(adapter,
1906 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1907 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1908 adapter->hw_write_wx(adapter,
1909 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1910
1911 for (j = 0; j < MAX_CTL_CHECK; j++) {
1912 adapter->hw_read_wx(adapter,
1913 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1914 if ((temp & MIU_TA_CTL_BUSY) == 0)
1915 break;
1916 }
1917
1918 if (j >= MAX_CTL_CHECK) {
1919 printk(KERN_ERR "%s: Fail to read through agent\n",
1920 netxen_nic_driver_name);
1921 break;
1922 }
1923
1924 start = off0[i] >> 2;
1925 end = (off0[i] + sz[i] - 1) >> 2;
1926 for (k = start; k <= end; k++) {
1927 adapter->hw_read_wx(adapter,
1928 mem_crb + MIU_TEST_AGT_RDDATA(k), &temp, 4);
1929 word[i] |= ((uint64_t)temp << (32 * k));
1930 }
1931 }
1932
1933 /*
1934 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1935 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1936 */
1937
1938 if (j >= MAX_CTL_CHECK)
1939 return -1;
1940
1941 if (sz[0] == 8) {
1942 val = word[0];
1943 } else {
1944 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1945 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1946 }
1947
1948 switch (size) {
1949 case 1:
1950 *(uint8_t *)data = val;
1951 break;
1952 case 2:
1953 *(uint16_t *)data = val;
1954 break;
1955 case 4:
1956 *(uint32_t *)data = val;
1957 break;
1958 case 8:
1959 *(uint64_t *)data = val;
1960 break;
1961 }
1962 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1963 return 0;
1964}
1965
1966/*
1967 * Note : only 32-bit writes!
1968 */
1969int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1970 u64 off, u32 data)
1971{
1972 adapter->hw_write_wx(adapter, off, &data, 4);
1973
1974 return 0;
1975}
1976
1977u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off)
1978{
1979 u32 temp;
1980 adapter->hw_read_wx(adapter, off, &temp, 4);
1981 return temp;
1982}
1983
1984void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
1985 u64 off, u32 data)
1986{
1987 adapter->hw_write_wx(adapter, off, &data, 4);
1988}
1989
1990u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off)
1991{
1992 u32 temp;
1993 adapter->hw_read_wx(adapter, off, &temp, 4);
1994 return temp;
1995}
1996
993fb90c 1997#if 0
13ba9c77
MT		 1998int
1999netxen_nic_erase_pxe(struct netxen_adapter *adapter)
2000{
0d04761d 2001 if (netxen_rom_fast_write(adapter, NETXEN_PXE_START, 0) == -1) {
4790654c 2002 printk(KERN_ERR "%s: erase pxe failed\n",
13ba9c77
MT		 2003 netxen_nic_driver_name);
2004 return -1;
2005 }
2006 return 0;
2007}
993fb90c 2008#endif /* 0 */
13ba9c77 2009
3d396eb1
AK		 2010int netxen_nic_get_board_info(struct netxen_adapter *adapter)
2011{
2012 int rv = 0;
0d04761d 2013 int addr = NETXEN_BRDCFG_START;
3d396eb1
AK		 2014 struct netxen_board_info *boardinfo;
2015 int index;
2016 u32 *ptr32;
2017
2018 boardinfo = &adapter->ahw.boardcfg;
2019 ptr32 = (u32 *) boardinfo;
2020
2021 for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32);
2022 index++) {
2023 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
2024 return -EIO;
2025 }
2026 ptr32++;
2027 addr += sizeof(u32);
2028 }
2029 if (boardinfo->magic != NETXEN_BDINFO_MAGIC) {
2030 printk("%s: ERROR reading %s board config."
2031 " Read %x, expected %x\n", netxen_nic_driver_name,
2032 netxen_nic_driver_name,
2033 boardinfo->magic, NETXEN_BDINFO_MAGIC);
2034 rv = -1;
2035 }
2036 if (boardinfo->header_version != NETXEN_BDINFO_VERSION) {
2037 printk("%s: Unknown board config version."
2038 " Read %x, expected %x\n", netxen_nic_driver_name,
2039 boardinfo->header_version, NETXEN_BDINFO_VERSION);
2040 rv = -1;
2041 }
2042
2043 DPRINTK(INFO, "Discovered board type:0x%x ", boardinfo->board_type);
2044 switch ((netxen_brdtype_t) boardinfo->board_type) {
2045 case NETXEN_BRDTYPE_P2_SB35_4G:
2046 adapter->ahw.board_type = NETXEN_NIC_GBE;
2047 break;
2048 case NETXEN_BRDTYPE_P2_SB31_10G:
2049 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
2050 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
2051 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
e4c93c81
DP		 2052 case NETXEN_BRDTYPE_P3_HMEZ:
2053 case NETXEN_BRDTYPE_P3_XG_LOM:
2054 case NETXEN_BRDTYPE_P3_10G_CX4:
2055 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
2056 case NETXEN_BRDTYPE_P3_IMEZ:
2057 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
a70f9393
DP		 2058 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
2059 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
e4c93c81
DP		 2060 case NETXEN_BRDTYPE_P3_10G_XFP:
2061 case NETXEN_BRDTYPE_P3_10000_BASE_T:
2062
3d396eb1
AK		 2063 adapter->ahw.board_type = NETXEN_NIC_XGBE;
2064 break;
2065 case NETXEN_BRDTYPE_P1_BD:
2066 case NETXEN_BRDTYPE_P1_SB:
2067 case NETXEN_BRDTYPE_P1_SMAX:
2068 case NETXEN_BRDTYPE_P1_SOCK:
e4c93c81
DP		 2069 case NETXEN_BRDTYPE_P3_REF_QG:
2070 case NETXEN_BRDTYPE_P3_4_GB:
2071 case NETXEN_BRDTYPE_P3_4_GB_MM:
2072
3d396eb1
AK		 2073 adapter->ahw.board_type = NETXEN_NIC_GBE;
2074 break;
2075 default:
2076 printk("%s: Unknown(%x)\n", netxen_nic_driver_name,
2077 boardinfo->board_type);
a70f9393 2078 rv = -ENODEV;
3d396eb1
AK		 2079 break;
2080 }
2081
2082 return rv;
2083}
2084
2085/* NIU access sections */
2086
3176ff3e 2087int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
3d396eb1 2088{
9ad27643 2089 new_mtu += MTU_FUDGE_FACTOR;
3d396eb1 2090 netxen_nic_write_w0(adapter,
3276fbad
DP		 2091 NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
2092 new_mtu);
3d396eb1
AK		 2093 return 0;
2094}
2095
3176ff3e 2096int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
3d396eb1 2097{
9ad27643 2098 new_mtu += MTU_FUDGE_FACTOR;
3276fbad 2099 if (adapter->physical_port == 0)
4790654c 2100 netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE,
595e3fb8 2101 new_mtu);
4790654c 2102 else
595e3fb8
MT		 2103 netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE,
2104 new_mtu);
3d396eb1
AK		 2105 return 0;
2106}
2107
3d396eb1 2108void
3ce06a32
DP		 2109netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
2110 unsigned long off, int data)
3d396eb1 2111{
3ce06a32 2112 adapter->hw_write_wx(adapter, off, &data, 4);
3d396eb1
AK		 2113}
2114
3176ff3e 2115void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
3d396eb1 2116{
a608ab9c
AV		 2117 __u32 status;
2118 __u32 autoneg;
2119 __u32 mode;
24a7a455 2120 __u32 port_mode;
3d396eb1
AK		 2121
2122 netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode);
2123 if (netxen_get_niu_enable_ge(mode)) { /* Gb 10/100/1000 Mbps mode */
24a7a455
DP		 2124
2125 adapter->hw_read_wx(adapter,
2126 NETXEN_PORT_MODE_ADDR, &port_mode, 4);
2127 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
2128 adapter->link_speed = SPEED_1000;
2129 adapter->link_duplex = DUPLEX_FULL;
2130 adapter->link_autoneg = AUTONEG_DISABLE;
2131 return;
2132 }
2133
80922fbc 2134 if (adapter->phy_read
24a7a455 2135 && adapter->phy_read(adapter,
3d396eb1
AK		 2136 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
2137 &status) == 0) {
2138 if (netxen_get_phy_link(status)) {
2139 switch (netxen_get_phy_speed(status)) {
2140 case 0:
3176ff3e 2141 adapter->link_speed = SPEED_10;
3d396eb1
AK		 2142 break;
2143 case 1:
3176ff3e 2144 adapter->link_speed = SPEED_100;
3d396eb1
AK		 2145 break;
2146 case 2:
3176ff3e 2147 adapter->link_speed = SPEED_1000;
3d396eb1
AK		 2148 break;
2149 default:
3176ff3e 2150 adapter->link_speed = -1;
3d396eb1
AK		 2151 break;
2152 }
2153 switch (netxen_get_phy_duplex(status)) {
2154 case 0:
3176ff3e 2155 adapter->link_duplex = DUPLEX_HALF;
3d396eb1
AK		 2156 break;
2157 case 1:
3176ff3e 2158 adapter->link_duplex = DUPLEX_FULL;
3d396eb1
AK		 2159 break;
2160 default:
3176ff3e 2161 adapter->link_duplex = -1;
3d396eb1
AK		 2162 break;
2163 }
80922fbc 2164 if (adapter->phy_read
24a7a455 2165 && adapter->phy_read(adapter,
3d396eb1 2166 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
ed25ffa1 2167 &autoneg) != 0)
3176ff3e 2168 adapter->link_autoneg = autoneg;
3d396eb1
AK		 2169 } else
2170 goto link_down;
2171 } else {
2172 link_down:
3176ff3e
MT		 2173 adapter->link_speed = -1;
2174 adapter->link_duplex = -1;
3d396eb1
AK		 2175 }
2176 }
2177}
2178
2179void netxen_nic_flash_print(struct netxen_adapter *adapter)
2180{
3d396eb1
AK		 2181 u32 fw_major = 0;
2182 u32 fw_minor = 0;
2183 u32 fw_build = 0;
cb8011ad 2184 char brd_name[NETXEN_MAX_SHORT_NAME];
8d74849b
HH		 2185 char serial_num[32];
2186 int i, addr;
6d1495f2 2187 __le32 *ptr32;
3d396eb1
AK		 2188
2189 struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
dcd56fdb
DP		 2190
2191 adapter->driver_mismatch = 0;
2192
2193 ptr32 = (u32 *)&serial_num;
2194 addr = NETXEN_USER_START +
2195 offsetof(struct netxen_new_user_info, serial_num);
2196 for (i = 0; i < 8; i++) {
2197 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
2198 printk("%s: ERROR reading %s board userarea.\n",
2199 netxen_nic_driver_name,
2200 netxen_nic_driver_name);
2201 adapter->driver_mismatch = 1;
2202 return;
cb8011ad 2203 }
dcd56fdb
DP		 2204 ptr32++;
2205 addr += sizeof(u32);
2206 }
2207
3ce06a32
DP		 2208 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MAJOR, &fw_major, 4);
2209 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MINOR, &fw_minor, 4);
2210 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_SUB, &fw_build, 4);
8d74849b 2211
2956640d
DP		 2212 adapter->fw_major = fw_major;
2213
dcd56fdb 2214 if (adapter->portnum == 0) {
cb8011ad
AK		 2215 get_brd_name_by_type(board_info->board_type, brd_name);
2216
11d89d63
DP		 2217 printk(KERN_INFO "NetXen %s Board S/N %s Chip rev 0x%x\n",
2218 brd_name, serial_num, adapter->ahw.revision_id);
2219 printk(KERN_INFO "NetXen Firmware version %d.%d.%d\n",
2220 fw_major, fw_minor, fw_build);
3d396eb1 2221 }
dcd56fdb 2222
58735567
DP		 2223 if (NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build) <
2224 NETXEN_VERSION_CODE(3, 4, 216)) {
3d396eb1 2225 adapter->driver_mismatch = 1;
58735567
DP		 2226 printk(KERN_ERR "%s: firmware version %d.%d.%d unsupported\n",
2227 netxen_nic_driver_name,
2228 fw_major, fw_minor, fw_build);
dcd56fdb
DP		 2229 return;
2230 }
3d396eb1
AK		 2231}
2232
Linux kernel - Deliverables
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