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netdevice: safe convert to netdev_priv() #part-2
[deliverable/linux.git] / drivers / net / netxen / netxen_nic_hw.c
CommitLineData
3d396eb1
AK		 1/*
2 * Copyright (C) 2003 - 2006 NetXen, Inc.
3 * All rights reserved.
80922fbc 4 *
3d396eb1
AK		 5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
cb8011ad 9 *
3d396eb1
AK		 10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
cb8011ad 14 *
3d396eb1
AK		 15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
80922fbc 19 *
3d396eb1
AK		 20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
80922fbc 22 *
3d396eb1
AK		 23 * Contact Information:
24 * info@netxen.com
25 * NetXen,
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
28 *
29 *
30 * Source file for NIC routines to access the Phantom hardware
31 *
32 */
33
34#include "netxen_nic.h"
35#include "netxen_nic_hw.h"
36#include "netxen_nic_phan_reg.h"
37
3176ff3e 38
c9bdd4b5
ACM		 39#include <net/ip.h>
40
3ce06a32
DP		 41#define MASK(n) ((1ULL<<(n))-1)
42#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
43#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
44#define MS_WIN(addr) (addr & 0x0ffc0000)
45
46#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
47
48#define CRB_BLK(off) ((off >> 20) & 0x3f)
49#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
50#define CRB_WINDOW_2M (0x130060)
51#define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
52#define CRB_INDIRECT_2M (0x1e0000UL)
53
54#define CRB_WIN_LOCK_TIMEOUT 100000000
55static crb_128M_2M_block_map_t crb_128M_2M_map[64] = {
56 {{{0, 0, 0, 0} } }, /* 0: PCI */
57 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
58 {1, 0x0110000, 0x0120000, 0x130000},
59 {1, 0x0120000, 0x0122000, 0x124000},
60 {1, 0x0130000, 0x0132000, 0x126000},
61 {1, 0x0140000, 0x0142000, 0x128000},
62 {1, 0x0150000, 0x0152000, 0x12a000},
63 {1, 0x0160000, 0x0170000, 0x110000},
64 {1, 0x0170000, 0x0172000, 0x12e000},
65 {0, 0x0000000, 0x0000000, 0x000000},
66 {0, 0x0000000, 0x0000000, 0x000000},
67 {0, 0x0000000, 0x0000000, 0x000000},
68 {0, 0x0000000, 0x0000000, 0x000000},
69 {0, 0x0000000, 0x0000000, 0x000000},
70 {0, 0x0000000, 0x0000000, 0x000000},
71 {1, 0x01e0000, 0x01e0800, 0x122000},
72 {0, 0x0000000, 0x0000000, 0x000000} } },
73 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
74 {{{0, 0, 0, 0} } }, /* 3: */
75 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
76 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
77 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
78 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
79 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
80 {0, 0x0000000, 0x0000000, 0x000000},
81 {0, 0x0000000, 0x0000000, 0x000000},
82 {0, 0x0000000, 0x0000000, 0x000000},
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {0, 0x0000000, 0x0000000, 0x000000},
89 {0, 0x0000000, 0x0000000, 0x000000},
90 {0, 0x0000000, 0x0000000, 0x000000},
91 {0, 0x0000000, 0x0000000, 0x000000},
92 {0, 0x0000000, 0x0000000, 0x000000},
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {1, 0x08f0000, 0x08f2000, 0x172000} } },
95 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {0, 0x0000000, 0x0000000, 0x000000},
108 {0, 0x0000000, 0x0000000, 0x000000},
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {1, 0x09f0000, 0x09f2000, 0x176000} } },
111 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
127 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
143 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
144 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
145 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
146 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
147 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
148 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
149 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
150 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
151 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
152 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
153 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
154 {{{0, 0, 0, 0} } }, /* 23: */
155 {{{0, 0, 0, 0} } }, /* 24: */
156 {{{0, 0, 0, 0} } }, /* 25: */
157 {{{0, 0, 0, 0} } }, /* 26: */
158 {{{0, 0, 0, 0} } }, /* 27: */
159 {{{0, 0, 0, 0} } }, /* 28: */
160 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
161 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
162 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
163 {{{0} } }, /* 32: PCI */
164 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
165 {1, 0x2110000, 0x2120000, 0x130000},
166 {1, 0x2120000, 0x2122000, 0x124000},
167 {1, 0x2130000, 0x2132000, 0x126000},
168 {1, 0x2140000, 0x2142000, 0x128000},
169 {1, 0x2150000, 0x2152000, 0x12a000},
170 {1, 0x2160000, 0x2170000, 0x110000},
171 {1, 0x2170000, 0x2172000, 0x12e000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000} } },
180 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
181 {{{0} } }, /* 35: */
182 {{{0} } }, /* 36: */
183 {{{0} } }, /* 37: */
184 {{{0} } }, /* 38: */
185 {{{0} } }, /* 39: */
186 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
187 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
188 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
189 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
190 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
191 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
192 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
193 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
194 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
195 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
196 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
197 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
198 {{{0} } }, /* 52: */
199 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
200 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
201 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
202 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
203 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
204 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
205 {{{0} } }, /* 59: I2C0 */
206 {{{0} } }, /* 60: I2C1 */
207 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
208 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
209 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
210};
211
212/*
213 * top 12 bits of crb internal address (hub, agent)
214 */
215static unsigned crb_hub_agt[64] =
216{
217 0,
218 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
219 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
220 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
221 0,
222 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
223 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
224 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
225 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
226 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
227 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
228 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
229 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
230 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
231 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
232 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
233 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
234 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
235 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
236 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
237 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
238 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
239 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
240 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
241 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
242 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
243 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
244 0,
245 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
246 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
247 0,
248 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
249 0,
250 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
251 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
252 0,
253 0,
254 0,
255 0,
256 0,
257 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
258 0,
259 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
260 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
261 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
262 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
263 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
264 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
265 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
266 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
267 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
268 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
269 0,
270 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
271 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
272 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
273 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
274 0,
275 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
276 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
277 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
278 0,
279 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
280 0,
281};
282
3d396eb1
AK		 283/* PCI Windowing for DDR regions. */
284
285#define ADDR_IN_RANGE(addr, low, high) \
286 (((addr) <= (high)) && ((addr) >= (low)))
287
3ce06a32 288#define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
3d396eb1 289
cb8011ad
AK		 290#define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL
291#define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL
292#define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL
293#define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL
294
295#define NETXEN_NIC_WINDOW_MARGIN 0x100000
296
3d396eb1
AK		 297int netxen_nic_set_mac(struct net_device *netdev, void *p)
298{
3176ff3e 299 struct netxen_adapter *adapter = netdev_priv(netdev);
3d396eb1
AK		 300 struct sockaddr *addr = p;
301
302 if (netif_running(netdev))
303 return -EBUSY;
304
305 if (!is_valid_ether_addr(addr->sa_data))
306 return -EADDRNOTAVAIL;
307
3d396eb1
AK		 308 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
309
c9fc891f
DP		 310 /* For P3, MAC addr is not set in NIU */
311 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
312 if (adapter->macaddr_set)
313 adapter->macaddr_set(adapter, addr->sa_data);
3d396eb1
AK		 314
315 return 0;
316}
317
623621b0
DP		 318#define NETXEN_UNICAST_ADDR(port, index) \
319 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
320#define NETXEN_MCAST_ADDR(port, index) \
321 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
322#define MAC_HI(addr) \
323 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
324#define MAC_LO(addr) \
325 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
326
327static int
328netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
329{
330 u32 val = 0;
331 u16 port = adapter->physical_port;
332 u8 *addr = adapter->netdev->dev_addr;
333
334 if (adapter->mc_enabled)
335 return 0;
336
3ce06a32 337 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
623621b0 338 val |= (1UL << (28+port));
3ce06a32 339 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
623621b0
DP		 340
341 /* add broadcast addr to filter */
342 val = 0xffffff;
343 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
344 netxen_crb_writelit_adapter(adapter,
345 NETXEN_UNICAST_ADDR(port, 0)+4, val);
346
347 /* add station addr to filter */
348 val = MAC_HI(addr);
349 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
350 val = MAC_LO(addr);
351 netxen_crb_writelit_adapter(adapter,
352 NETXEN_UNICAST_ADDR(port, 1)+4, val);
353
354 adapter->mc_enabled = 1;
355 return 0;
356}
357
358static int
359netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
360{
361 u32 val = 0;
362 u16 port = adapter->physical_port;
363 u8 *addr = adapter->netdev->dev_addr;
364
365 if (!adapter->mc_enabled)
366 return 0;
367
3ce06a32 368 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
623621b0 369 val &= ~(1UL << (28+port));
3ce06a32 370 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
623621b0
DP		 371
372 val = MAC_HI(addr);
373 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
374 val = MAC_LO(addr);
375 netxen_crb_writelit_adapter(adapter,
376 NETXEN_UNICAST_ADDR(port, 0)+4, val);
377
378 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
379 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
380
381 adapter->mc_enabled = 0;
382 return 0;
383}
384
385static int
386netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
387 int index, u8 *addr)
388{
389 u32 hi = 0, lo = 0;
390 u16 port = adapter->physical_port;
391
392 lo = MAC_LO(addr);
393 hi = MAC_HI(addr);
394
395 netxen_crb_writelit_adapter(adapter,
396 NETXEN_MCAST_ADDR(port, index), hi);
397 netxen_crb_writelit_adapter(adapter,
398 NETXEN_MCAST_ADDR(port, index)+4, lo);
399
400 return 0;
401}
402
c9fc891f 403void netxen_p2_nic_set_multi(struct net_device *netdev)
3d396eb1 404{
3176ff3e 405 struct netxen_adapter *adapter = netdev_priv(netdev);
3d396eb1 406 struct dev_mc_list *mc_ptr;
623621b0
DP		 407 u8 null_addr[6];
408 int index = 0;
409
410 memset(null_addr, 0, 6);
3d396eb1 411
3d396eb1 412 if (netdev->flags & IFF_PROMISC) {
623621b0
DP		 413
414 adapter->set_promisc(adapter,
415 NETXEN_NIU_PROMISC_MODE);
416
417 /* Full promiscuous mode */
418 netxen_nic_disable_mcast_filter(adapter);
419
420 return;
421 }
422
423 if (netdev->mc_count == 0) {
424 adapter->set_promisc(adapter,
425 NETXEN_NIU_NON_PROMISC_MODE);
426 netxen_nic_disable_mcast_filter(adapter);
427 return;
428 }
429
430 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
431 if (netdev->flags & IFF_ALLMULTI ||
432 netdev->mc_count > adapter->max_mc_count) {
433 netxen_nic_disable_mcast_filter(adapter);
434 return;
3d396eb1 435 }
623621b0
DP		 436
437 netxen_nic_enable_mcast_filter(adapter);
438
439 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++)
440 netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr);
441
442 if (index != netdev->mc_count)
443 printk(KERN_WARNING "%s: %s multicast address count mismatch\n",
444 netxen_nic_driver_name, netdev->name);
445
446 /* Clear out remaining addresses */
447 for (; index < adapter->max_mc_count; index++)
448 netxen_nic_set_mcast_addr(adapter, index, null_addr);
3d396eb1
AK		 449}
450
c9fc891f
DP		 451static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
452 u8 *addr, nx_mac_list_t **add_list, nx_mac_list_t **del_list)
453{
454 nx_mac_list_t *cur, *prev;
455
456 /* if in del_list, move it to adapter->mac_list */
457 for (cur = *del_list, prev = NULL; cur;) {
458 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
459 if (prev == NULL)
460 *del_list = cur->next;
461 else
462 prev->next = cur->next;
463 cur->next = adapter->mac_list;
464 adapter->mac_list = cur;
465 return 0;
466 }
467 prev = cur;
468 cur = cur->next;
469 }
470
471 /* make sure to add each mac address only once */
472 for (cur = adapter->mac_list; cur; cur = cur->next) {
473 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
474 return 0;
475 }
476 /* not in del_list, create new entry and add to add_list */
477 cur = kmalloc(sizeof(*cur), in_atomic()? GFP_ATOMIC : GFP_KERNEL);
478 if (cur == NULL) {
479 printk(KERN_ERR "%s: cannot allocate memory. MAC filtering may"
480 "not work properly from now.\n", __func__);
481 return -1;
482 }
483
484 memcpy(cur->mac_addr, addr, ETH_ALEN);
485 cur->next = *add_list;
486 *add_list = cur;
487 return 0;
488}
489
490static int
491netxen_send_cmd_descs(struct netxen_adapter *adapter,
492 struct cmd_desc_type0 *cmd_desc_arr, int nr_elements)
493{
494 uint32_t i, producer;
495 struct netxen_cmd_buffer *pbuf;
496 struct cmd_desc_type0 *cmd_desc;
497
498 if (nr_elements > MAX_PENDING_DESC_BLOCK_SIZE || nr_elements == 0) {
499 printk(KERN_WARNING "%s: Too many command descriptors in a "
500 "request\n", __func__);
501 return -EINVAL;
502 }
503
504 i = 0;
505
506 producer = adapter->cmd_producer;
507 do {
508 cmd_desc = &cmd_desc_arr[i];
509
510 pbuf = &adapter->cmd_buf_arr[producer];
511 pbuf->mss = 0;
512 pbuf->total_length = 0;
513 pbuf->skb = NULL;
514 pbuf->cmd = 0;
515 pbuf->frag_count = 0;
516 pbuf->port = 0;
517
518 /* adapter->ahw.cmd_desc_head[producer] = *cmd_desc; */
519 memcpy(&adapter->ahw.cmd_desc_head[producer],
520 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
521
522 producer = get_next_index(producer,
523 adapter->max_tx_desc_count);
524 i++;
525
526 } while (i != nr_elements);
527
528 adapter->cmd_producer = producer;
529
530 /* write producer index to start the xmit */
531
532 netxen_nic_update_cmd_producer(adapter, adapter->cmd_producer);
533
534 return 0;
535}
536
c9fc891f
DP		 537static int nx_p3_sre_macaddr_change(struct net_device *dev,
538 u8 *addr, unsigned op)
539{
4cf1653a 540 struct netxen_adapter *adapter = netdev_priv(dev);
c9fc891f
DP		 541 nx_nic_req_t req;
542 nx_mac_req_t mac_req;
543 int rv;
544
545 memset(&req, 0, sizeof(nx_nic_req_t));
9ad27643
DP		 546 req.qhdr |= (NX_NIC_REQUEST << 23);
547 req.req_hdr |= NX_MAC_EVENT;
c9fc891f
DP		 548 req.req_hdr |= ((u64)adapter->portnum << 16);
549 mac_req.op = op;
550 memcpy(&mac_req.mac_addr, addr, 6);
551 req.words[0] = cpu_to_le64(*(u64 *)&mac_req);
552
553 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
554 if (rv != 0) {
555 printk(KERN_ERR "ERROR. Could not send mac update\n");
556 return rv;
557 }
558
559 return 0;
560}
561
562void netxen_p3_nic_set_multi(struct net_device *netdev)
563{
564 struct netxen_adapter *adapter = netdev_priv(netdev);
565 nx_mac_list_t *cur, *next, *del_list, *add_list = NULL;
566 struct dev_mc_list *mc_ptr;
567 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
9ad27643 568 u32 mode = VPORT_MISS_MODE_DROP;
c9fc891f
DP		 569
570 del_list = adapter->mac_list;
571 adapter->mac_list = NULL;
572
573 nx_p3_nic_add_mac(adapter, netdev->dev_addr, &add_list, &del_list);
9ad27643
DP		 574 nx_p3_nic_add_mac(adapter, bcast_addr, &add_list, &del_list);
575
576 if (netdev->flags & IFF_PROMISC) {
577 mode = VPORT_MISS_MODE_ACCEPT_ALL;
578 goto send_fw_cmd;
579 }
580
581 if ((netdev->flags & IFF_ALLMULTI) ||
582 (netdev->mc_count > adapter->max_mc_count)) {
583 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
584 goto send_fw_cmd;
585 }
586
c9fc891f 587 if (netdev->mc_count > 0) {
c9fc891f
DP		 588 for (mc_ptr = netdev->mc_list; mc_ptr;
589 mc_ptr = mc_ptr->next) {
590 nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr,
591 &add_list, &del_list);
592 }
593 }
9ad27643
DP		 594
595send_fw_cmd:
596 adapter->set_promisc(adapter, mode);
c9fc891f
DP		 597 for (cur = del_list; cur;) {
598 nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_DEL);
599 next = cur->next;
600 kfree(cur);
601 cur = next;
602 }
603 for (cur = add_list; cur;) {
604 nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_ADD);
605 next = cur->next;
606 cur->next = adapter->mac_list;
607 adapter->mac_list = cur;
608 cur = next;
609 }
610}
611
9ad27643
DP		 612int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
613{
614 nx_nic_req_t req;
615
616 memset(&req, 0, sizeof(nx_nic_req_t));
617
618 req.qhdr |= (NX_HOST_REQUEST << 23);
619 req.req_hdr |= NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE;
620 req.req_hdr |= ((u64)adapter->portnum << 16);
621 req.words[0] = cpu_to_le64(mode);
622
623 return netxen_send_cmd_descs(adapter,
624 (struct cmd_desc_type0 *)&req, 1);
625}
626
cd1f8160
DP		 627#define NETXEN_CONFIG_INTR_COALESCE 3
628
629/*
630 * Send the interrupt coalescing parameter set by ethtool to the card.
631 */
632int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
633{
634 nx_nic_req_t req;
635 int rv;
636
637 memset(&req, 0, sizeof(nx_nic_req_t));
638
9ad27643 639 req.qhdr |= (NX_NIC_REQUEST << 23);
cd1f8160
DP		 640 req.req_hdr |= NETXEN_CONFIG_INTR_COALESCE;
641 req.req_hdr |= ((u64)adapter->portnum << 16);
642
643 memcpy(&req.words[0], &adapter->coal, sizeof(adapter->coal));
644
645 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
646 if (rv != 0) {
647 printk(KERN_ERR "ERROR. Could not send "
648 "interrupt coalescing parameters\n");
649 }
650
651 return rv;
652}
653
3d396eb1
AK		 654/*
655 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
656 * @returns 0 on success, negative on failure
657 */
c9fc891f
DP		 658
659#define MTU_FUDGE_FACTOR 100
660
3d396eb1
AK		 661int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
662{
3176ff3e 663 struct netxen_adapter *adapter = netdev_priv(netdev);
c9fc891f 664 int max_mtu;
9ad27643 665 int rc = 0;
3d396eb1 666
c9fc891f
DP		 667 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
668 max_mtu = P3_MAX_MTU;
669 else
670 max_mtu = P2_MAX_MTU;
671
672 if (mtu > max_mtu) {
673 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
674 netdev->name, max_mtu);
3d396eb1
AK		 675 return -EINVAL;
676 }
677
80922fbc 678 if (adapter->set_mtu)
9ad27643 679 rc = adapter->set_mtu(adapter, mtu);
3d396eb1 680
9ad27643
DP		 681 if (!rc)
682 netdev->mtu = mtu;
c9fc891f 683
9ad27643 684 return rc;
3d396eb1
AK		 685}
686
3d396eb1
AK		 687int netxen_is_flash_supported(struct netxen_adapter *adapter)
688{
689 const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 };
690 int addr, val01, val02, i, j;
691
692 /* if the flash size less than 4Mb, make huge war cry and die */
693 for (j = 1; j < 4; j++) {
cb8011ad 694 addr = j * NETXEN_NIC_WINDOW_MARGIN;
ff8ac609 695 for (i = 0; i < ARRAY_SIZE(locs); i++) {
3d396eb1
AK		 696 if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0
697 && netxen_rom_fast_read(adapter, (addr + locs[i]),
698 &val02) == 0) {
699 if (val01 == val02)
700 return -1;
701 } else
702 return -1;
703 }
704 }
705
706 return 0;
707}
708
709static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
f305f789 710 int size, __le32 * buf)
3d396eb1
AK		 711{
712 int i, addr;
f305f789
AV		 713 __le32 *ptr32;
714 u32 v;
3d396eb1
AK		 715
716 addr = base;
717 ptr32 = buf;
718 for (i = 0; i < size / sizeof(u32); i++) {
f305f789 719 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
3d396eb1 720 return -1;
f305f789 721 *ptr32 = cpu_to_le32(v);
3d396eb1
AK		 722 ptr32++;
723 addr += sizeof(u32);
724 }
725 if ((char *)buf + size > (char *)ptr32) {
f305f789
AV		 726 __le32 local;
727 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
3d396eb1 728 return -1;
f305f789 729 local = cpu_to_le32(v);
3d396eb1
AK		 730 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
731 }
732
733 return 0;
734}
735
9dc28efe 736int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
3d396eb1 737{
9dc28efe
DP		 738 __le32 *pmac = (__le32 *) mac;
739 u32 offset;
3d396eb1 740
9dc28efe
DP		 741 offset = NETXEN_USER_START +
742 offsetof(struct netxen_new_user_info, mac_addr) +
743 adapter->portnum * sizeof(u64);
744
745 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
3d396eb1 746 return -1;
9dc28efe 747
f305f789 748 if (*mac == cpu_to_le64(~0ULL)) {
9dc28efe
DP		 749
750 offset = NETXEN_USER_START_OLD +
751 offsetof(struct netxen_user_old_info, mac_addr) +
752 adapter->portnum * sizeof(u64);
753
3d396eb1 754 if (netxen_get_flash_block(adapter,
9dc28efe 755 offset, sizeof(u64), pmac) == -1)
3d396eb1 756 return -1;
9dc28efe 757
f305f789 758 if (*mac == cpu_to_le64(~0ULL))
3d396eb1
AK		 759 return -1;
760 }
761 return 0;
762}
763
9dc28efe
DP		 764int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
765{
766 uint32_t crbaddr, mac_hi, mac_lo;
767 int pci_func = adapter->ahw.pci_func;
768
769 crbaddr = CRB_MAC_BLOCK_START +
770 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
771
772 adapter->hw_read_wx(adapter, crbaddr, &mac_lo, 4);
773 adapter->hw_read_wx(adapter, crbaddr+4, &mac_hi, 4);
774
775 mac_hi = cpu_to_le32(mac_hi);
776 mac_lo = cpu_to_le32(mac_lo);
777
778 if (pci_func & 1)
779 *mac = ((mac_lo >> 16) | ((u64)mac_hi << 16));
780 else
781 *mac = ((mac_lo) | ((u64)mac_hi << 32));
782
783 return 0;
784}
785
3ce06a32
DP		 786#define CRB_WIN_LOCK_TIMEOUT 100000000
787
788static int crb_win_lock(struct netxen_adapter *adapter)
789{
790 int done = 0, timeout = 0;
791
792 while (!done) {
793 /* acquire semaphore3 from PCI HW block */
794 adapter->hw_read_wx(adapter,
795 NETXEN_PCIE_REG(PCIE_SEM7_LOCK), &done, 4);
796 if (done == 1)
797 break;
798 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
799 return -1;
800 timeout++;
801 udelay(1);
802 }
803 netxen_crb_writelit_adapter(adapter,
804 NETXEN_CRB_WIN_LOCK_ID, adapter->portnum);
805 return 0;
806}
807
808static void crb_win_unlock(struct netxen_adapter *adapter)
809{
810 int val;
811
812 adapter->hw_read_wx(adapter,
813 NETXEN_PCIE_REG(PCIE_SEM7_UNLOCK), &val, 4);
814}
815
3d396eb1
AK		 816/*
817 * Changes the CRB window to the specified window.
818 */
3ce06a32
DP		 819void
820netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw)
3d396eb1
AK		 821{
822 void __iomem *offset;
823 u32 tmp;
824 int count = 0;
e4c93c81 825 uint8_t func = adapter->ahw.pci_func;
3d396eb1
AK		 826
827 if (adapter->curr_window == wndw)
828 return;
3d396eb1
AK		 829 /*
830 * Move the CRB window.
831 * We need to write to the "direct access" region of PCI
832 * to avoid a race condition where the window register has
833 * not been successfully written across CRB before the target
834 * register address is received by PCI. The direct region bypasses
835 * the CRB bus.
836 */
e4c93c81
DP		 837 offset = PCI_OFFSET_SECOND_RANGE(adapter,
838 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
3d396eb1
AK		 839
840 if (wndw & 0x1)
841 wndw = NETXEN_WINDOW_ONE;
842
843 writel(wndw, offset);
844
845 /* MUST make sure window is set before we forge on... */
846 while ((tmp = readl(offset)) != wndw) {
847 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
848 "registered properly: 0x%08x.\n",
3ce06a32 849 netxen_nic_driver_name, __func__, tmp);
3d396eb1
AK		 850 mdelay(1);
851 if (count >= 10)
852 break;
853 count++;
854 }
855
6c80b18d
MT		 856 if (wndw == NETXEN_WINDOW_ONE)
857 adapter->curr_window = 1;
858 else
859 adapter->curr_window = 0;
3d396eb1
AK		 860}
861
3ce06a32
DP		 862/*
863 * Return -1 if off is not valid,
864 * 1 if window access is needed. 'off' is set to offset from
865 * CRB space in 128M pci map
866 * 0 if no window access is needed. 'off' is set to 2M addr
867 * In: 'off' is offset from base in 128M pci map
868 */
869static int
870netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter,
871 ulong *off, int len)
872{
873 unsigned long end = *off + len;
874 crb_128M_2M_sub_block_map_t *m;
875
876
877 if (*off >= NETXEN_CRB_MAX)
878 return -1;
879
880 if (*off >= NETXEN_PCI_CAMQM && (end <= NETXEN_PCI_CAMQM_2M_END)) {
881 *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE +
882 (ulong)adapter->ahw.pci_base0;
883 return 0;
884 }
885
886 if (*off < NETXEN_PCI_CRBSPACE)
887 return -1;
888
889 *off -= NETXEN_PCI_CRBSPACE;
890 end = *off + len;
891
892 /*
893 * Try direct map
894 */
895 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
896
897 if (m->valid && (m->start_128M <= *off) && (m->end_128M >= end)) {
898 *off = *off + m->start_2M - m->start_128M +
899 (ulong)adapter->ahw.pci_base0;
900 return 0;
901 }
902
903 /*
904 * Not in direct map, use crb window
905 */
906 return 1;
907}
908
909/*
910 * In: 'off' is offset from CRB space in 128M pci map
911 * Out: 'off' is 2M pci map addr
912 * side effect: lock crb window
913 */
914static void
915netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off)
916{
917 u32 win_read;
918
919 adapter->crb_win = CRB_HI(*off);
920 writel(adapter->crb_win, (void *)(CRB_WINDOW_2M +
921 adapter->ahw.pci_base0));
922 /*
923 * Read back value to make sure write has gone through before trying
924 * to use it.
925 */
926 win_read = readl((void *)(CRB_WINDOW_2M + adapter->ahw.pci_base0));
927 if (win_read != adapter->crb_win) {
928 printk(KERN_ERR "%s: Written crbwin (0x%x) != "
929 "Read crbwin (0x%x), off=0x%lx\n",
930 __func__, adapter->crb_win, win_read, *off);
931 }
932 *off = (*off & MASK(16)) + CRB_INDIRECT_2M +
933 (ulong)adapter->ahw.pci_base0;
934}
935
96acb6eb 936int netxen_load_firmware(struct netxen_adapter *adapter)
3d396eb1
AK		 937{
938 int i;
e0e20a1a 939 u32 data, size = 0;
2956640d
DP		 940 u32 flashaddr = NETXEN_BOOTLD_START, memaddr = NETXEN_BOOTLD_START;
941
942 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START)/4;
3d396eb1 943
2956640d
DP		 944 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
945 adapter->pci_write_normalize(adapter,
3ce06a32 946 NETXEN_ROMUSB_GLB_CAS_RST, 1);
3d396eb1
AK		 947
948 for (i = 0; i < size; i++) {
96acb6eb
DP		 949 if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0)
950 return -EIO;
951
3ce06a32 952 adapter->pci_mem_write(adapter, memaddr, &data, 4);
3d396eb1
AK		 953 flashaddr += 4;
954 memaddr += 4;
3ce06a32 955 cond_resched();
3d396eb1 956 }
2956640d
DP		 957 msleep(1);
958
959 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
960 adapter->pci_write_normalize(adapter,
961 NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
962 else {
963 adapter->pci_write_normalize(adapter,
3ce06a32 964 NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
2956640d 965 adapter->pci_write_normalize(adapter,
3ce06a32 966 NETXEN_ROMUSB_GLB_CAS_RST, 0);
2956640d 967 }
3d396eb1 968
96acb6eb 969 return 0;
3d396eb1
AK		 970}
971
972int
3ce06a32
DP		 973netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
974 ulong off, void *data, int len)
3d396eb1
AK		 975{
976 void __iomem *addr;
977
978 if (ADDR_IN_WINDOW1(off)) {
979 addr = NETXEN_CRB_NORMALIZE(adapter, off);
980 } else { /* Window 0 */
cb8011ad 981 addr = pci_base_offset(adapter, off);
3ce06a32 982 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
3d396eb1
AK		 983 }
984
985 DPRINTK(INFO, "writing to base %lx offset %llx addr %p"
986 " data %llx len %d\n",
cb8011ad 987 pci_base(adapter, off), off, addr,
3d396eb1 988 *(unsigned long long *)data, len);
cb8011ad 989 if (!addr) {
3ce06a32 990 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
cb8011ad
AK		 991 return 1;
992 }
993
3d396eb1
AK		 994 switch (len) {
995 case 1:
996 writeb(*(u8 *) data, addr);
997 break;
998 case 2:
999 writew(*(u16 *) data, addr);
1000 break;
1001 case 4:
1002 writel(*(u32 *) data, addr);
1003 break;
1004 case 8:
1005 writeq(*(u64 *) data, addr);
1006 break;
1007 default:
1008 DPRINTK(INFO,
1009 "writing data %lx to offset %llx, num words=%d\n",
1010 *(unsigned long *)data, off, (len >> 3));
1011
1012 netxen_nic_hw_block_write64((u64 __iomem *) data, addr,
1013 (len >> 3));
1014 break;
1015 }
1016 if (!ADDR_IN_WINDOW1(off))
3ce06a32 1017 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
3d396eb1
AK		 1018
1019 return 0;
1020}
1021
1022int
3ce06a32
DP		 1023netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
1024 ulong off, void *data, int len)
3d396eb1
AK		 1025{
1026 void __iomem *addr;
1027
1028 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1029 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1030 } else { /* Window 0 */
cb8011ad 1031 addr = pci_base_offset(adapter, off);
3ce06a32 1032 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
3d396eb1
AK		 1033 }
1034
1035 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
cb8011ad
AK		 1036 pci_base(adapter, off), off, addr);
1037 if (!addr) {
3ce06a32 1038 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
cb8011ad
AK		 1039 return 1;
1040 }
3d396eb1
AK		 1041 switch (len) {
1042 case 1:
1043 *(u8 *) data = readb(addr);
1044 break;
1045 case 2:
1046 *(u16 *) data = readw(addr);
1047 break;
1048 case 4:
1049 *(u32 *) data = readl(addr);
1050 break;
1051 case 8:
1052 *(u64 *) data = readq(addr);
1053 break;
1054 default:
1055 netxen_nic_hw_block_read64((u64 __iomem *) data, addr,
1056 (len >> 3));
1057 break;
1058 }
1059 DPRINTK(INFO, "read %lx\n", *(unsigned long *)data);
1060
1061 if (!ADDR_IN_WINDOW1(off))
3ce06a32 1062 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
3d396eb1
AK		 1063
1064 return 0;
1065}
1066
3ce06a32
DP		 1067int
1068netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1069 ulong off, void *data, int len)
1070{
1071 unsigned long flags = 0;
1072 int rv;
3d396eb1 1073
3ce06a32 1074 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
3d396eb1 1075
3ce06a32
DP		 1076 if (rv == -1) {
1077 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1078 __func__, off);
1079 dump_stack();
1080 return -1;
1081 }
1082
1083 if (rv == 1) {
1084 write_lock_irqsave(&adapter->adapter_lock, flags);
1085 crb_win_lock(adapter);
1086 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1087 }
1088
1089 DPRINTK(1, INFO, "write data %lx to offset %llx, len=%d\n",
1090 *(unsigned long *)data, off, len);
1091
1092 switch (len) {
1093 case 1:
1094 writeb(*(uint8_t *)data, (void *)off);
1095 break;
1096 case 2:
1097 writew(*(uint16_t *)data, (void *)off);
1098 break;
1099 case 4:
1100 writel(*(uint32_t *)data, (void *)off);
1101 break;
1102 case 8:
1103 writeq(*(uint64_t *)data, (void *)off);
1104 break;
1105 default:
1106 DPRINTK(1, INFO,
1107 "writing data %lx to offset %llx, num words=%d\n",
1108 *(unsigned long *)data, off, (len>>3));
1109 break;
1110 }
1111 if (rv == 1) {
1112 crb_win_unlock(adapter);
1113 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1114 }
1115
1116 return 0;
3d396eb1
AK		 1117}
1118
3ce06a32
DP		 1119int
1120netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
1121 ulong off, void *data, int len)
1122{
1123 unsigned long flags = 0;
1124 int rv;
3d396eb1 1125
3ce06a32
DP		 1126 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
1127
1128 if (rv == -1) {
1129 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1130 __func__, off);
1131 dump_stack();
1132 return -1;
1133 }
1134
1135 if (rv == 1) {
1136 write_lock_irqsave(&adapter->adapter_lock, flags);
1137 crb_win_lock(adapter);
1138 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1139 }
1140
1141 DPRINTK(1, INFO, "read from offset %lx, len=%d\n", off, len);
1142
1143 switch (len) {
1144 case 1:
1145 *(uint8_t *)data = readb((void *)off);
1146 break;
1147 case 2:
1148 *(uint16_t *)data = readw((void *)off);
1149 break;
1150 case 4:
1151 *(uint32_t *)data = readl((void *)off);
1152 break;
1153 case 8:
1154 *(uint64_t *)data = readq((void *)off);
1155 break;
1156 default:
1157 break;
1158 }
1159
1160 DPRINTK(1, INFO, "read %lx\n", *(unsigned long *)data);
3d396eb1 1161
3ce06a32
DP		 1162 if (rv == 1) {
1163 crb_win_unlock(adapter);
1164 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1165 }
1166
1167 return 0;
1168}
1169
1170void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
1171{
1172 adapter->hw_write_wx(adapter, off, &val, 4);
1173}
1174
1175int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
1176{
1177 int val;
1178 adapter->hw_read_wx(adapter, off, &val, 4);
3d396eb1
AK		 1179 return val;
1180}
1181
1182/* Change the window to 0, write and change back to window 1. */
1183void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
1184{
3ce06a32 1185 adapter->hw_write_wx(adapter, index, &value, 4);
3d396eb1
AK		 1186}
1187
1188/* Change the window to 0, read and change back to window 1. */
3ce06a32 1189void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value)
3d396eb1 1190{
3ce06a32
DP		 1191 adapter->hw_read_wx(adapter, index, value, 4);
1192}
3d396eb1 1193
3ce06a32
DP		 1194void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value)
1195{
1196 adapter->hw_write_wx(adapter, index, &value, 4);
1197}
1198
1199void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value)
1200{
1201 adapter->hw_read_wx(adapter, index, value, 4);
1202}
1203
1204/*
1205 * check memory access boundary.
1206 * used by test agent. support ddr access only for now
1207 */
1208static unsigned long
1209netxen_nic_pci_mem_bound_check(struct netxen_adapter *adapter,
1210 unsigned long long addr, int size)
1211{
1212 if (!ADDR_IN_RANGE(addr,
1213 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1214 !ADDR_IN_RANGE(addr+size-1,
1215 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1216 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
1217 return 0;
1218 }
3d396eb1 1219
3ce06a32 1220 return 1;
3d396eb1
AK		 1221}
1222
4790654c 1223static int netxen_pci_set_window_warning_count;
3d396eb1 1224
3ce06a32
DP		 1225unsigned long
1226netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1227 unsigned long long addr)
3d396eb1 1228{
e4c93c81 1229 void __iomem *offset;
3d396eb1 1230 int window;
3ce06a32 1231 unsigned long long qdr_max;
e4c93c81 1232 uint8_t func = adapter->ahw.pci_func;
3d396eb1 1233
3ce06a32
DP		 1234 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1235 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1236 } else {
1237 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1238 }
1239
3d396eb1
AK		 1240 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1241 /* DDR network side */
1242 addr -= NETXEN_ADDR_DDR_NET;
1243 window = (addr >> 25) & 0x3ff;
3ce06a32
DP		 1244 if (adapter->ahw.ddr_mn_window != window) {
1245 adapter->ahw.ddr_mn_window = window;
e4c93c81
DP		 1246 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1247 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func)));
1248 writel(window, offset);
3d396eb1 1249 /* MUST make sure window is set before we forge on... */
e4c93c81 1250 readl(offset);
3d396eb1 1251 }
cb8011ad 1252 addr -= (window * NETXEN_WINDOW_ONE);
3d396eb1
AK		 1253 addr += NETXEN_PCI_DDR_NET;
1254 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1255 addr -= NETXEN_ADDR_OCM0;
1256 addr += NETXEN_PCI_OCM0;
1257 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1258 addr -= NETXEN_ADDR_OCM1;
1259 addr += NETXEN_PCI_OCM1;
3ce06a32 1260 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
3d396eb1
AK		 1261 /* QDR network side */
1262 addr -= NETXEN_ADDR_QDR_NET;
1263 window = (addr >> 22) & 0x3f;
3ce06a32
DP		 1264 if (adapter->ahw.qdr_sn_window != window) {
1265 adapter->ahw.qdr_sn_window = window;
e4c93c81
DP		 1266 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1267 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func)));
1268 writel((window << 22), offset);
3d396eb1 1269 /* MUST make sure window is set before we forge on... */
e4c93c81 1270 readl(offset);
3d396eb1
AK		 1271 }
1272 addr -= (window * 0x400000);
1273 addr += NETXEN_PCI_QDR_NET;
1274 } else {
1275 /*
1276 * peg gdb frequently accesses memory that doesn't exist,
1277 * this limits the chit chat so debugging isn't slowed down.
1278 */
1279 if ((netxen_pci_set_window_warning_count++ < 8)
1280 || (netxen_pci_set_window_warning_count % 64 == 0))
1281 printk("%s: Warning:netxen_nic_pci_set_window()"
1282 " Unknown address range!\n",
1283 netxen_nic_driver_name);
3ce06a32
DP		 1284 addr = -1UL;
1285 }
1286 return addr;
1287}
1288
1289/*
1290 * Note : only 32-bit writes!
1291 */
1292int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1293 u64 off, u32 data)
1294{
1295 writel(data, (void __iomem *)(PCI_OFFSET_SECOND_RANGE(adapter, off)));
1296 return 0;
1297}
1298
1299u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off)
1300{
1301 return readl((void __iomem *)(pci_base_offset(adapter, off)));
1302}
1303
1304void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1305 u64 off, u32 data)
1306{
1307 writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
1308}
1309
1310u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off)
1311{
1312 return readl(NETXEN_CRB_NORMALIZE(adapter, off));
1313}
1314
1315unsigned long
1316netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1317 unsigned long long addr)
1318{
1319 int window;
1320 u32 win_read;
3d396eb1 1321
3ce06a32
DP		 1322 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1323 /* DDR network side */
1324 window = MN_WIN(addr);
1325 adapter->ahw.ddr_mn_window = window;
1326 adapter->hw_write_wx(adapter,
1327 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1328 &window, 4);
1329 adapter->hw_read_wx(adapter,
1330 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1331 &win_read, 4);
1332 if ((win_read << 17) != window) {
1333 printk(KERN_INFO "Written MNwin (0x%x) != "
1334 "Read MNwin (0x%x)\n", window, win_read);
1335 }
1336 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_DDR_NET;
1337 } else if (ADDR_IN_RANGE(addr,
1338 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1339 if ((addr & 0x00ff800) == 0xff800) {
1340 printk("%s: QM access not handled.\n", __func__);
1341 addr = -1UL;
1342 }
1343
1344 window = OCM_WIN(addr);
1345 adapter->ahw.ddr_mn_window = window;
1346 adapter->hw_write_wx(adapter,
1347 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1348 &window, 4);
1349 adapter->hw_read_wx(adapter,
1350 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1351 &win_read, 4);
1352 if ((win_read >> 7) != window) {
1353 printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
1354 "Read OCMwin (0x%x)\n",
1355 __func__, window, win_read);
1356 }
1357 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_OCM0_2M;
1358
1359 } else if (ADDR_IN_RANGE(addr,
1360 NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P3)) {
1361 /* QDR network side */
1362 window = MS_WIN(addr);
1363 adapter->ahw.qdr_sn_window = window;
1364 adapter->hw_write_wx(adapter,
1365 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1366 &window, 4);
1367 adapter->hw_read_wx(adapter,
1368 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1369 &win_read, 4);
1370 if (win_read != window) {
1371 printk(KERN_INFO "%s: Written MSwin (0x%x) != "
1372 "Read MSwin (0x%x)\n",
1373 __func__, window, win_read);
1374 }
1375 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_QDR_NET;
1376
1377 } else {
1378 /*
1379 * peg gdb frequently accesses memory that doesn't exist,
1380 * this limits the chit chat so debugging isn't slowed down.
1381 */
1382 if ((netxen_pci_set_window_warning_count++ < 8)
1383 || (netxen_pci_set_window_warning_count%64 == 0)) {
1384 printk("%s: Warning:%s Unknown address range!\n",
1385 __func__, netxen_nic_driver_name);
1386}
1387 addr = -1UL;
3d396eb1
AK		 1388 }
1389 return addr;
1390}
1391
3ce06a32
DP		 1392static int netxen_nic_pci_is_same_window(struct netxen_adapter *adapter,
1393 unsigned long long addr)
1394{
1395 int window;
1396 unsigned long long qdr_max;
1397
1398 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1399 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1400 else
1401 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1402
1403 if (ADDR_IN_RANGE(addr,
1404 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1405 /* DDR network side */
1406 BUG(); /* MN access can not come here */
1407 } else if (ADDR_IN_RANGE(addr,
1408 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1409 return 1;
1410 } else if (ADDR_IN_RANGE(addr,
1411 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1412 return 1;
1413 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1414 /* QDR network side */
1415 window = ((addr - NETXEN_ADDR_QDR_NET) >> 22) & 0x3f;
1416 if (adapter->ahw.qdr_sn_window == window)
1417 return 1;
1418 }
1419
1420 return 0;
1421}
1422
1423static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter,
1424 u64 off, void *data, int size)
1425{
1426 unsigned long flags;
1427 void *addr;
1428 int ret = 0;
1429 u64 start;
1430 uint8_t *mem_ptr = NULL;
1431 unsigned long mem_base;
1432 unsigned long mem_page;
1433
1434 write_lock_irqsave(&adapter->adapter_lock, flags);
1435
1436 /*
1437 * If attempting to access unknown address or straddle hw windows,
1438 * do not access.
1439 */
1440 start = adapter->pci_set_window(adapter, off);
1441 if ((start == -1UL) ||
1442 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1443 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1444 printk(KERN_ERR "%s out of bound pci memory access. "
11a859e5
AM		 1445 "offset is 0x%llx\n", netxen_nic_driver_name,
1446 (unsigned long long)off);
3ce06a32
DP		 1447 return -1;
1448 }
1449
1450 addr = (void *)(pci_base_offset(adapter, start));
1451 if (!addr) {
1452 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1453 mem_base = pci_resource_start(adapter->pdev, 0);
1454 mem_page = start & PAGE_MASK;
1455 /* Map two pages whenever user tries to access addresses in two
1456 consecutive pages.
1457 */
1458 if (mem_page != ((start + size - 1) & PAGE_MASK))
1459 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
1460 else
1461 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1462 if (mem_ptr == 0UL) {
1463 *(uint8_t *)data = 0;
1464 return -1;
1465 }
1466 addr = mem_ptr;
1467 addr += start & (PAGE_SIZE - 1);
1468 write_lock_irqsave(&adapter->adapter_lock, flags);
1469 }
1470
1471 switch (size) {
1472 case 1:
1473 *(uint8_t *)data = readb(addr);
1474 break;
1475 case 2:
1476 *(uint16_t *)data = readw(addr);
1477 break;
1478 case 4:
1479 *(uint32_t *)data = readl(addr);
1480 break;
1481 case 8:
1482 *(uint64_t *)data = readq(addr);
1483 break;
1484 default:
1485 ret = -1;
1486 break;
1487 }
1488 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1489 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1490
1491 if (mem_ptr)
1492 iounmap(mem_ptr);
1493 return ret;
1494}
1495
1496static int
1497netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off,
1498 void *data, int size)
1499{
1500 unsigned long flags;
1501 void *addr;
1502 int ret = 0;
1503 u64 start;
1504 uint8_t *mem_ptr = NULL;
1505 unsigned long mem_base;
1506 unsigned long mem_page;
1507
1508 write_lock_irqsave(&adapter->adapter_lock, flags);
1509
1510 /*
1511 * If attempting to access unknown address or straddle hw windows,
1512 * do not access.
1513 */
1514 start = adapter->pci_set_window(adapter, off);
1515 if ((start == -1UL) ||
1516 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1517 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1518 printk(KERN_ERR "%s out of bound pci memory access. "
11a859e5
AM		 1519 "offset is 0x%llx\n", netxen_nic_driver_name,
1520 (unsigned long long)off);
3ce06a32
DP		 1521 return -1;
1522 }
1523
1524 addr = (void *)(pci_base_offset(adapter, start));
1525 if (!addr) {
1526 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1527 mem_base = pci_resource_start(adapter->pdev, 0);
1528 mem_page = start & PAGE_MASK;
1529 /* Map two pages whenever user tries to access addresses in two
1530 * consecutive pages.
1531 */
1532 if (mem_page != ((start + size - 1) & PAGE_MASK))
1533 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
1534 else
1535 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1536 if (mem_ptr == 0UL)
1537 return -1;
1538 addr = mem_ptr;
1539 addr += start & (PAGE_SIZE - 1);
1540 write_lock_irqsave(&adapter->adapter_lock, flags);
1541 }
1542
1543 switch (size) {
1544 case 1:
1545 writeb(*(uint8_t *)data, addr);
1546 break;
1547 case 2:
1548 writew(*(uint16_t *)data, addr);
1549 break;
1550 case 4:
1551 writel(*(uint32_t *)data, addr);
1552 break;
1553 case 8:
1554 writeq(*(uint64_t *)data, addr);
1555 break;
1556 default:
1557 ret = -1;
1558 break;
1559 }
1560 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1561 DPRINTK(1, INFO, "writing data %llx to offset %llx\n",
1562 *(unsigned long long *)data, start);
1563 if (mem_ptr)
1564 iounmap(mem_ptr);
1565 return ret;
1566}
1567
1568#define MAX_CTL_CHECK 1000
1569
1570int
1571netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1572 u64 off, void *data, int size)
1573{
1574 unsigned long flags, mem_crb;
1575 int i, j, ret = 0, loop, sz[2], off0;
1576 uint32_t temp;
1577 uint64_t off8, tmpw, word[2] = {0, 0};
1578
1579 /*
1580 * If not MN, go check for MS or invalid.
1581 */
1582 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1583 return netxen_nic_pci_mem_write_direct(adapter,
1584 off, data, size);
1585
1586 off8 = off & 0xfffffff8;
1587 off0 = off & 0x7;
1588 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1589 sz[1] = size - sz[0];
1590 loop = ((off0 + size - 1) >> 3) + 1;
1591 mem_crb = (unsigned long)pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1592
1593 if ((size != 8) || (off0 != 0)) {
1594 for (i = 0; i < loop; i++) {
1595 if (adapter->pci_mem_read(adapter,
1596 off8 + (i << 3), &word[i], 8))
1597 return -1;
1598 }
1599 }
1600
1601 switch (size) {
1602 case 1:
1603 tmpw = *((uint8_t *)data);
1604 break;
1605 case 2:
1606 tmpw = *((uint16_t *)data);
1607 break;
1608 case 4:
1609 tmpw = *((uint32_t *)data);
1610 break;
1611 case 8:
1612 default:
1613 tmpw = *((uint64_t *)data);
1614 break;
1615 }
1616 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1617 word[0] |= tmpw << (off0 * 8);
1618
1619 if (loop == 2) {
1620 word[1] &= ~(~0ULL << (sz[1] * 8));
1621 word[1] |= tmpw >> (sz[0] * 8);
1622 }
1623
1624 write_lock_irqsave(&adapter->adapter_lock, flags);
1625 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1626
1627 for (i = 0; i < loop; i++) {
1628 writel((uint32_t)(off8 + (i << 3)),
1629 (void *)(mem_crb+MIU_TEST_AGT_ADDR_LO));
1630 writel(0,
1631 (void *)(mem_crb+MIU_TEST_AGT_ADDR_HI));
1632 writel(word[i] & 0xffffffff,
1633 (void *)(mem_crb+MIU_TEST_AGT_WRDATA_LO));
1634 writel((word[i] >> 32) & 0xffffffff,
1635 (void *)(mem_crb+MIU_TEST_AGT_WRDATA_HI));
1636 writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1637 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1638 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1639 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1640
1641 for (j = 0; j < MAX_CTL_CHECK; j++) {
1642 temp = readl(
1643 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1644 if ((temp & MIU_TA_CTL_BUSY) == 0)
1645 break;
1646 }
1647
1648 if (j >= MAX_CTL_CHECK) {
1649 printk("%s: %s Fail to write through agent\n",
1650 __func__, netxen_nic_driver_name);
1651 ret = -1;
1652 break;
1653 }
1654 }
1655
1656 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1657 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1658 return ret;
1659}
1660
1661int
1662netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1663 u64 off, void *data, int size)
1664{
1665 unsigned long flags, mem_crb;
1666 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1667 uint32_t temp;
1668 uint64_t off8, val, word[2] = {0, 0};
1669
1670
1671 /*
1672 * If not MN, go check for MS or invalid.
1673 */
1674 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1675 return netxen_nic_pci_mem_read_direct(adapter, off, data, size);
1676
1677 off8 = off & 0xfffffff8;
1678 off0[0] = off & 0x7;
1679 off0[1] = 0;
1680 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1681 sz[1] = size - sz[0];
1682 loop = ((off0[0] + size - 1) >> 3) + 1;
1683 mem_crb = (unsigned long)pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1684
1685 write_lock_irqsave(&adapter->adapter_lock, flags);
1686 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1687
1688 for (i = 0; i < loop; i++) {
1689 writel((uint32_t)(off8 + (i << 3)),
1690 (void *)(mem_crb+MIU_TEST_AGT_ADDR_LO));
1691 writel(0,
1692 (void *)(mem_crb+MIU_TEST_AGT_ADDR_HI));
1693 writel(MIU_TA_CTL_ENABLE,
1694 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1695 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE,
1696 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1697
1698 for (j = 0; j < MAX_CTL_CHECK; j++) {
1699 temp = readl(
1700 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1701 if ((temp & MIU_TA_CTL_BUSY) == 0)
1702 break;
1703 }
1704
1705 if (j >= MAX_CTL_CHECK) {
1706 printk(KERN_ERR "%s: %s Fail to read through agent\n",
1707 __func__, netxen_nic_driver_name);
1708 break;
1709 }
1710
1711 start = off0[i] >> 2;
1712 end = (off0[i] + sz[i] - 1) >> 2;
1713 for (k = start; k <= end; k++) {
1714 word[i] |= ((uint64_t) readl(
1715 (void *)(mem_crb +
1716 MIU_TEST_AGT_RDDATA(k))) << (32*k));
1717 }
1718 }
1719
1720 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1721 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1722
1723 if (j >= MAX_CTL_CHECK)
1724 return -1;
1725
1726 if (sz[0] == 8) {
1727 val = word[0];
1728 } else {
1729 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1730 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1731 }
1732
1733 switch (size) {
1734 case 1:
1735 *(uint8_t *)data = val;
1736 break;
1737 case 2:
1738 *(uint16_t *)data = val;
1739 break;
1740 case 4:
1741 *(uint32_t *)data = val;
1742 break;
1743 case 8:
1744 *(uint64_t *)data = val;
1745 break;
1746 }
1747 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1748 return 0;
1749}
1750
1751int
1752netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1753 u64 off, void *data, int size)
1754{
1755 int i, j, ret = 0, loop, sz[2], off0;
1756 uint32_t temp;
1757 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1758
1759 /*
1760 * If not MN, go check for MS or invalid.
1761 */
1762 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1763 mem_crb = NETXEN_CRB_QDR_NET;
1764 else {
1765 mem_crb = NETXEN_CRB_DDR_NET;
1766 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1767 return netxen_nic_pci_mem_write_direct(adapter,
1768 off, data, size);
1769 }
1770
1771 off8 = off & 0xfffffff8;
1772 off0 = off & 0x7;
1773 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1774 sz[1] = size - sz[0];
1775 loop = ((off0 + size - 1) >> 3) + 1;
1776
1777 if ((size != 8) || (off0 != 0)) {
1778 for (i = 0; i < loop; i++) {
1779 if (adapter->pci_mem_read(adapter, off8 + (i << 3),
1780 &word[i], 8))
1781 return -1;
1782 }
1783 }
1784
1785 switch (size) {
1786 case 1:
1787 tmpw = *((uint8_t *)data);
1788 break;
1789 case 2:
1790 tmpw = *((uint16_t *)data);
1791 break;
1792 case 4:
1793 tmpw = *((uint32_t *)data);
1794 break;
1795 case 8:
1796 default:
1797 tmpw = *((uint64_t *)data);
1798 break;
1799 }
1800
1801 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1802 word[0] |= tmpw << (off0 * 8);
1803
1804 if (loop == 2) {
1805 word[1] &= ~(~0ULL << (sz[1] * 8));
1806 word[1] |= tmpw >> (sz[0] * 8);
1807 }
1808
1809 /*
1810 * don't lock here - write_wx gets the lock if each time
1811 * write_lock_irqsave(&adapter->adapter_lock, flags);
1812 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1813 */
1814
1815 for (i = 0; i < loop; i++) {
1816 temp = off8 + (i << 3);
1817 adapter->hw_write_wx(adapter,
1818 mem_crb+MIU_TEST_AGT_ADDR_LO, &temp, 4);
1819 temp = 0;
1820 adapter->hw_write_wx(adapter,
1821 mem_crb+MIU_TEST_AGT_ADDR_HI, &temp, 4);
1822 temp = word[i] & 0xffffffff;
1823 adapter->hw_write_wx(adapter,
1824 mem_crb+MIU_TEST_AGT_WRDATA_LO, &temp, 4);
1825 temp = (word[i] >> 32) & 0xffffffff;
1826 adapter->hw_write_wx(adapter,
1827 mem_crb+MIU_TEST_AGT_WRDATA_HI, &temp, 4);
1828 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1829 adapter->hw_write_wx(adapter,
1830 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1831 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1832 adapter->hw_write_wx(adapter,
1833 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1834
1835 for (j = 0; j < MAX_CTL_CHECK; j++) {
1836 adapter->hw_read_wx(adapter,
1837 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1838 if ((temp & MIU_TA_CTL_BUSY) == 0)
1839 break;
1840 }
1841
1842 if (j >= MAX_CTL_CHECK) {
1843 printk(KERN_ERR "%s: Fail to write through agent\n",
1844 netxen_nic_driver_name);
1845 ret = -1;
1846 break;
1847 }
1848 }
1849
1850 /*
1851 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1852 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1853 */
1854 return ret;
1855}
1856
1857int
1858netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1859 u64 off, void *data, int size)
1860{
1861 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1862 uint32_t temp;
1863 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1864
1865 /*
1866 * If not MN, go check for MS or invalid.
1867 */
1868
1869 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1870 mem_crb = NETXEN_CRB_QDR_NET;
1871 else {
1872 mem_crb = NETXEN_CRB_DDR_NET;
1873 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1874 return netxen_nic_pci_mem_read_direct(adapter,
1875 off, data, size);
1876 }
1877
1878 off8 = off & 0xfffffff8;
1879 off0[0] = off & 0x7;
1880 off0[1] = 0;
1881 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1882 sz[1] = size - sz[0];
1883 loop = ((off0[0] + size - 1) >> 3) + 1;
1884
1885 /*
1886 * don't lock here - write_wx gets the lock if each time
1887 * write_lock_irqsave(&adapter->adapter_lock, flags);
1888 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1889 */
1890
1891 for (i = 0; i < loop; i++) {
1892 temp = off8 + (i << 3);
1893 adapter->hw_write_wx(adapter,
1894 mem_crb + MIU_TEST_AGT_ADDR_LO, &temp, 4);
1895 temp = 0;
1896 adapter->hw_write_wx(adapter,
1897 mem_crb + MIU_TEST_AGT_ADDR_HI, &temp, 4);
1898 temp = MIU_TA_CTL_ENABLE;
1899 adapter->hw_write_wx(adapter,
1900 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1901 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1902 adapter->hw_write_wx(adapter,
1903 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1904
1905 for (j = 0; j < MAX_CTL_CHECK; j++) {
1906 adapter->hw_read_wx(adapter,
1907 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1908 if ((temp & MIU_TA_CTL_BUSY) == 0)
1909 break;
1910 }
1911
1912 if (j >= MAX_CTL_CHECK) {
1913 printk(KERN_ERR "%s: Fail to read through agent\n",
1914 netxen_nic_driver_name);
1915 break;
1916 }
1917
1918 start = off0[i] >> 2;
1919 end = (off0[i] + sz[i] - 1) >> 2;
1920 for (k = start; k <= end; k++) {
1921 adapter->hw_read_wx(adapter,
1922 mem_crb + MIU_TEST_AGT_RDDATA(k), &temp, 4);
1923 word[i] |= ((uint64_t)temp << (32 * k));
1924 }
1925 }
1926
1927 /*
1928 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1929 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1930 */
1931
1932 if (j >= MAX_CTL_CHECK)
1933 return -1;
1934
1935 if (sz[0] == 8) {
1936 val = word[0];
1937 } else {
1938 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1939 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1940 }
1941
1942 switch (size) {
1943 case 1:
1944 *(uint8_t *)data = val;
1945 break;
1946 case 2:
1947 *(uint16_t *)data = val;
1948 break;
1949 case 4:
1950 *(uint32_t *)data = val;
1951 break;
1952 case 8:
1953 *(uint64_t *)data = val;
1954 break;
1955 }
1956 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1957 return 0;
1958}
1959
1960/*
1961 * Note : only 32-bit writes!
1962 */
1963int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1964 u64 off, u32 data)
1965{
1966 adapter->hw_write_wx(adapter, off, &data, 4);
1967
1968 return 0;
1969}
1970
1971u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off)
1972{
1973 u32 temp;
1974 adapter->hw_read_wx(adapter, off, &temp, 4);
1975 return temp;
1976}
1977
1978void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
1979 u64 off, u32 data)
1980{
1981 adapter->hw_write_wx(adapter, off, &data, 4);
1982}
1983
1984u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off)
1985{
1986 u32 temp;
1987 adapter->hw_read_wx(adapter, off, &temp, 4);
1988 return temp;
1989}
1990
993fb90c 1991#if 0
13ba9c77
MT		 1992int
1993netxen_nic_erase_pxe(struct netxen_adapter *adapter)
1994{
0d04761d 1995 if (netxen_rom_fast_write(adapter, NETXEN_PXE_START, 0) == -1) {
4790654c 1996 printk(KERN_ERR "%s: erase pxe failed\n",
13ba9c77
MT		 1997 netxen_nic_driver_name);
1998 return -1;
1999 }
2000 return 0;
2001}
993fb90c 2002#endif /* 0 */
13ba9c77 2003
3d396eb1
AK		 2004int netxen_nic_get_board_info(struct netxen_adapter *adapter)
2005{
2006 int rv = 0;
0d04761d 2007 int addr = NETXEN_BRDCFG_START;
3d396eb1
AK		 2008 struct netxen_board_info *boardinfo;
2009 int index;
2010 u32 *ptr32;
2011
2012 boardinfo = &adapter->ahw.boardcfg;
2013 ptr32 = (u32 *) boardinfo;
2014
2015 for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32);
2016 index++) {
2017 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
2018 return -EIO;
2019 }
2020 ptr32++;
2021 addr += sizeof(u32);
2022 }
2023 if (boardinfo->magic != NETXEN_BDINFO_MAGIC) {
2024 printk("%s: ERROR reading %s board config."
2025 " Read %x, expected %x\n", netxen_nic_driver_name,
2026 netxen_nic_driver_name,
2027 boardinfo->magic, NETXEN_BDINFO_MAGIC);
2028 rv = -1;
2029 }
2030 if (boardinfo->header_version != NETXEN_BDINFO_VERSION) {
2031 printk("%s: Unknown board config version."
2032 " Read %x, expected %x\n", netxen_nic_driver_name,
2033 boardinfo->header_version, NETXEN_BDINFO_VERSION);
2034 rv = -1;
2035 }
2036
2037 DPRINTK(INFO, "Discovered board type:0x%x ", boardinfo->board_type);
2038 switch ((netxen_brdtype_t) boardinfo->board_type) {
2039 case NETXEN_BRDTYPE_P2_SB35_4G:
2040 adapter->ahw.board_type = NETXEN_NIC_GBE;
2041 break;
2042 case NETXEN_BRDTYPE_P2_SB31_10G:
2043 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
2044 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
2045 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
e4c93c81
DP		 2046 case NETXEN_BRDTYPE_P3_HMEZ:
2047 case NETXEN_BRDTYPE_P3_XG_LOM:
2048 case NETXEN_BRDTYPE_P3_10G_CX4:
2049 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
2050 case NETXEN_BRDTYPE_P3_IMEZ:
2051 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
a70f9393
DP		 2052 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
2053 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
e4c93c81
DP		 2054 case NETXEN_BRDTYPE_P3_10G_XFP:
2055 case NETXEN_BRDTYPE_P3_10000_BASE_T:
2056
3d396eb1
AK		 2057 adapter->ahw.board_type = NETXEN_NIC_XGBE;
2058 break;
2059 case NETXEN_BRDTYPE_P1_BD:
2060 case NETXEN_BRDTYPE_P1_SB:
2061 case NETXEN_BRDTYPE_P1_SMAX:
2062 case NETXEN_BRDTYPE_P1_SOCK:
e4c93c81
DP		 2063 case NETXEN_BRDTYPE_P3_REF_QG:
2064 case NETXEN_BRDTYPE_P3_4_GB:
2065 case NETXEN_BRDTYPE_P3_4_GB_MM:
2066
3d396eb1
AK		 2067 adapter->ahw.board_type = NETXEN_NIC_GBE;
2068 break;
2069 default:
2070 printk("%s: Unknown(%x)\n", netxen_nic_driver_name,
2071 boardinfo->board_type);
a70f9393 2072 rv = -ENODEV;
3d396eb1
AK		 2073 break;
2074 }
2075
2076 return rv;
2077}
2078
2079/* NIU access sections */
2080
3176ff3e 2081int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
3d396eb1 2082{
9ad27643 2083 new_mtu += MTU_FUDGE_FACTOR;
3d396eb1 2084 netxen_nic_write_w0(adapter,
3276fbad
DP		 2085 NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
2086 new_mtu);
3d396eb1
AK		 2087 return 0;
2088}
2089
3176ff3e 2090int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
3d396eb1 2091{
9ad27643 2092 new_mtu += MTU_FUDGE_FACTOR;
3276fbad 2093 if (adapter->physical_port == 0)
4790654c 2094 netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE,
595e3fb8 2095 new_mtu);
4790654c 2096 else
595e3fb8
MT		 2097 netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE,
2098 new_mtu);
3d396eb1
AK		 2099 return 0;
2100}
2101
3d396eb1 2102void
3ce06a32
DP		 2103netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
2104 unsigned long off, int data)
3d396eb1 2105{
3ce06a32 2106 adapter->hw_write_wx(adapter, off, &data, 4);
3d396eb1
AK		 2107}
2108
3176ff3e 2109void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
3d396eb1 2110{
a608ab9c
AV		 2111 __u32 status;
2112 __u32 autoneg;
2113 __u32 mode;
24a7a455 2114 __u32 port_mode;
3d396eb1
AK		 2115
2116 netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode);
2117 if (netxen_get_niu_enable_ge(mode)) { /* Gb 10/100/1000 Mbps mode */
24a7a455
DP		 2118
2119 adapter->hw_read_wx(adapter,
2120 NETXEN_PORT_MODE_ADDR, &port_mode, 4);
2121 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
2122 adapter->link_speed = SPEED_1000;
2123 adapter->link_duplex = DUPLEX_FULL;
2124 adapter->link_autoneg = AUTONEG_DISABLE;
2125 return;
2126 }
2127
80922fbc 2128 if (adapter->phy_read
24a7a455 2129 && adapter->phy_read(adapter,
3d396eb1
AK		 2130 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
2131 &status) == 0) {
2132 if (netxen_get_phy_link(status)) {
2133 switch (netxen_get_phy_speed(status)) {
2134 case 0:
3176ff3e 2135 adapter->link_speed = SPEED_10;
3d396eb1
AK		 2136 break;
2137 case 1:
3176ff3e 2138 adapter->link_speed = SPEED_100;
3d396eb1
AK		 2139 break;
2140 case 2:
3176ff3e 2141 adapter->link_speed = SPEED_1000;
3d396eb1
AK		 2142 break;
2143 default:
3176ff3e 2144 adapter->link_speed = -1;
3d396eb1
AK		 2145 break;
2146 }
2147 switch (netxen_get_phy_duplex(status)) {
2148 case 0:
3176ff3e 2149 adapter->link_duplex = DUPLEX_HALF;
3d396eb1
AK		 2150 break;
2151 case 1:
3176ff3e 2152 adapter->link_duplex = DUPLEX_FULL;
3d396eb1
AK		 2153 break;
2154 default:
3176ff3e 2155 adapter->link_duplex = -1;
3d396eb1
AK		 2156 break;
2157 }
80922fbc 2158 if (adapter->phy_read
24a7a455 2159 && adapter->phy_read(adapter,
3d396eb1 2160 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
ed25ffa1 2161 &autoneg) != 0)
3176ff3e 2162 adapter->link_autoneg = autoneg;
3d396eb1
AK		 2163 } else
2164 goto link_down;
2165 } else {
2166 link_down:
3176ff3e
MT		 2167 adapter->link_speed = -1;
2168 adapter->link_duplex = -1;
3d396eb1
AK		 2169 }
2170 }
2171}
2172
2173void netxen_nic_flash_print(struct netxen_adapter *adapter)
2174{
3d396eb1
AK		 2175 u32 fw_major = 0;
2176 u32 fw_minor = 0;
2177 u32 fw_build = 0;
cb8011ad 2178 char brd_name[NETXEN_MAX_SHORT_NAME];
8d74849b
HH		 2179 char serial_num[32];
2180 int i, addr;
6d1495f2 2181 __le32 *ptr32;
3d396eb1
AK		 2182
2183 struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
dcd56fdb
DP		 2184
2185 adapter->driver_mismatch = 0;
2186
2187 ptr32 = (u32 *)&serial_num;
2188 addr = NETXEN_USER_START +
2189 offsetof(struct netxen_new_user_info, serial_num);
2190 for (i = 0; i < 8; i++) {
2191 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
2192 printk("%s: ERROR reading %s board userarea.\n",
2193 netxen_nic_driver_name,
2194 netxen_nic_driver_name);
2195 adapter->driver_mismatch = 1;
2196 return;
cb8011ad 2197 }
dcd56fdb
DP		 2198 ptr32++;
2199 addr += sizeof(u32);
2200 }
2201
3ce06a32
DP		 2202 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MAJOR, &fw_major, 4);
2203 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MINOR, &fw_minor, 4);
2204 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_SUB, &fw_build, 4);
8d74849b 2205
2956640d
DP		 2206 adapter->fw_major = fw_major;
2207
dcd56fdb 2208 if (adapter->portnum == 0) {
cb8011ad
AK		 2209 get_brd_name_by_type(board_info->board_type, brd_name);
2210
11d89d63
DP		 2211 printk(KERN_INFO "NetXen %s Board S/N %s Chip rev 0x%x\n",
2212 brd_name, serial_num, adapter->ahw.revision_id);
2213 printk(KERN_INFO "NetXen Firmware version %d.%d.%d\n",
2214 fw_major, fw_minor, fw_build);
3d396eb1 2215 }
dcd56fdb 2216
58735567
DP		 2217 if (NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build) <
2218 NETXEN_VERSION_CODE(3, 4, 216)) {
3d396eb1 2219 adapter->driver_mismatch = 1;
58735567
DP		 2220 printk(KERN_ERR "%s: firmware version %d.%d.%d unsupported\n",
2221 netxen_nic_driver_name,
2222 fw_major, fw_minor, fw_build);
dcd56fdb
DP		 2223 return;
2224 }
3d396eb1
AK		 2225}
2226
Linux kernel - Deliverables
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